This class represents a RISC-V (32 or 64 bit) instruction.
Public Types
Public Functions
The instruction opcode as defined in LLVM.
Iterator over the operands of the current instruction.
Public Static Functions
True if inst is an effective instance of riscv::Instruction.
See LIEF::assembly::riscv::OPCODE in include/asm/riscv/opcodes.hpp
This class represents an operand for a RISC-V instruction.
Subclassed by LIEF::assembly::riscv::operands::Immediate, LIEF::assembly::riscv::operands::Memory, LIEF::assembly::riscv::operands::PCRelative, LIEF::assembly::riscv::operands::Register
Public Functions
Pretty representation of the operand.
This function can be used to down cast an Operand instance:
std::unique_ptr<assembly::riscv::Operand> op = ...;
if (const auto* imm = inst->as<assembly::riscv::operands::Immediate>()) {
const int64_t value = imm->value();
}
This class represents a register operand.
RISC-V exposes two kinds of registers: regular registers (GPR, FPR, vector, …) and control and status registers (CSR / system registers).
csrr a0, mstatus
| |
+------+ +-------+
| |
v v
REG SYSREG
Public Functions