LIEF: Library to Instrument Executable Formats Version 0.15.1
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ProcessorFlags.hpp
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1/* Copyright 2017 - 2024 R. Thomas
2 * Copyright 2017 - 2024 Quarkslab
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16#ifndef LIEF_ELF_PROCESSOR_FLAGS_H
17#define LIEF_ELF_PROCESSOR_FLAGS_H
18#include <cstdint>
19#include "LIEF/visibility.h"
20
21namespace LIEF {
22namespace ELF {
23
24static constexpr uint64_t PFLAGS_BIT = 43;
25static constexpr uint64_t PFLAGS_MASK = (1LLU << PFLAGS_BIT) - 1;
26static constexpr uint64_t PF_ARM_ID = 1;
27static constexpr uint64_t PF_HEX_ID = 2;
28static constexpr uint64_t PF_LOONGARCH_ID = 3;
29static constexpr uint64_t PF_MIPS_ID = 4;
30
31enum class PROCESSOR_FLAGS : uint64_t {
32 ARM_EABI_UNKNOWN = 0x00000000 | (PF_ARM_ID << PFLAGS_BIT),
33 ARM_SOFT_FLOAT = 0x00000200 | (PF_ARM_ID << PFLAGS_BIT),
34 ARM_VFP_FLOAT = 0x00000400 | (PF_ARM_ID << PFLAGS_BIT),
35 ARM_EABI_VER1 = 0x01000000 | (PF_ARM_ID << PFLAGS_BIT),
36 ARM_EABI_VER2 = 0x02000000 | (PF_ARM_ID << PFLAGS_BIT),
37 ARM_EABI_VER3 = 0x03000000 | (PF_ARM_ID << PFLAGS_BIT),
38 ARM_EABI_VER4 = 0x04000000 | (PF_ARM_ID << PFLAGS_BIT),
39 ARM_EABI_VER5 = 0x05000000 | (PF_ARM_ID << PFLAGS_BIT),
40
41 HEXAGON_MACH_V2 = 0x00000001 | (PF_HEX_ID << PFLAGS_BIT), // Hexagon V2
42 HEXAGON_MACH_V3 = 0x00000002 | (PF_HEX_ID << PFLAGS_BIT), // Hexagon V3
43 HEXAGON_MACH_V4 = 0x00000003 | (PF_HEX_ID << PFLAGS_BIT), // Hexagon V4
44 HEXAGON_MACH_V5 = 0x00000004 | (PF_HEX_ID << PFLAGS_BIT), // Hexagon V5
45
46 HEXAGON_ISA_V2 = 0x00000010 | (PF_HEX_ID << PFLAGS_BIT), // Hexagon V2 ISA
47 HEXAGON_ISA_V3 = 0x00000020 | (PF_HEX_ID << PFLAGS_BIT), // Hexagon V3 ISA
48 HEXAGON_ISA_V4 = 0x00000030 | (PF_HEX_ID << PFLAGS_BIT), // Hexagon V4 ISA
49 HEXAGON_ISA_V5 = 0x00000040 | (PF_HEX_ID << PFLAGS_BIT), // Hexagon V5 ISA
50
51 LOONGARCH_ABI_SOFT_FLOAT = 0x1 | (PF_LOONGARCH_ID << PFLAGS_BIT),
52 LOONGARCH_ABI_SINGLE_FLOAT = 0x2 | (PF_LOONGARCH_ID << PFLAGS_BIT),
53 LOONGARCH_ABI_DOUBLE_FLOAT = 0x3 | (PF_LOONGARCH_ID << PFLAGS_BIT),
54
55 MIPS_NOREORDER = 0x00000001 | (PF_MIPS_ID << PFLAGS_BIT), /* Don't reorder instructions */
56 MIPS_PIC = 0x00000002 | (PF_MIPS_ID << PFLAGS_BIT), /* Position independent code */
57 MIPS_CPIC = 0x00000004 | (PF_MIPS_ID << PFLAGS_BIT), /* Call object with Position independent code */
58 MIPS_ABI2 = 0x00000020 | (PF_MIPS_ID << PFLAGS_BIT), /* File uses N32 ABI */
59 MIPS_32BITMODE = 0x00000100 | (PF_MIPS_ID << PFLAGS_BIT), /* Code compiled for a 64-bit machine */
60 /* in 32-bit mode */
61 MIPS_FP64 = 0x00000200 | (PF_MIPS_ID << PFLAGS_BIT), /* Code compiled for a 32-bit machine */
62 /* but uses 64-bit FP registers */
63 MIPS_NAN2008 = 0x00000400 | (PF_MIPS_ID << PFLAGS_BIT), /* Uses IEE 754-2008 NaN encoding */
64
65 /* ABI flags */
66 MIPS_ABI_O32 = 0x00001000 | (PF_MIPS_ID << PFLAGS_BIT), /* This file follows the first MIPS 32 bit ABI */
67 MIPS_ABI_O64 = 0x00002000 | (PF_MIPS_ID << PFLAGS_BIT), /* O32 ABI extended for 64-bit architecture. */
68 MIPS_ABI_EABI32 = 0x00003000 | (PF_MIPS_ID << PFLAGS_BIT), /* EABI in 32 bit mode. */
69 MIPS_ABI_EABI64 = 0x00004000 | (PF_MIPS_ID << PFLAGS_BIT), /* EABI in 64 bit mode. */
70
71 /* MIPS machine variant */
72 MIPS_MACH_3900 = 0x00810000 | (PF_MIPS_ID << PFLAGS_BIT), /* Toshiba R3900 */
73 MIPS_MACH_4010 = 0x00820000 | (PF_MIPS_ID << PFLAGS_BIT), /* LSI R4010 */
74 MIPS_MACH_4100 = 0x00830000 | (PF_MIPS_ID << PFLAGS_BIT), /* NEC VR4100 */
75 MIPS_MACH_4650 = 0x00850000 | (PF_MIPS_ID << PFLAGS_BIT), /* MIPS R4650 */
76 MIPS_MACH_4120 = 0x00870000 | (PF_MIPS_ID << PFLAGS_BIT), /* NEC VR4120 */
77 MIPS_MACH_4111 = 0x00880000 | (PF_MIPS_ID << PFLAGS_BIT), /* NEC VR4111/VR4181 */
78 MIPS_MACH_SB1 = 0x008a0000 | (PF_MIPS_ID << PFLAGS_BIT), /* Broadcom SB-1 */
79 MIPS_MACH_OCTEON = 0x008b0000 | (PF_MIPS_ID << PFLAGS_BIT), /* Cavium Networks Octeon */
80 MIPS_MACH_XLR = 0x008c0000 | (PF_MIPS_ID << PFLAGS_BIT), /* RMI Xlr */
81 MIPS_MACH_OCTEON2 = 0x008d0000 | (PF_MIPS_ID << PFLAGS_BIT), /* Cavium Networks Octeon2 */
82 MIPS_MACH_OCTEON3 = 0x008e0000 | (PF_MIPS_ID << PFLAGS_BIT), /* Cavium Networks Octeon3 */
83 MIPS_MACH_5400 = 0x00910000 | (PF_MIPS_ID << PFLAGS_BIT), /* NEC VR5400 */
84 MIPS_MACH_5900 = 0x00920000 | (PF_MIPS_ID << PFLAGS_BIT), /* MIPS R5900 */
85 MIPS_MACH_5500 = 0x00980000 | (PF_MIPS_ID << PFLAGS_BIT), /* NEC VR5500 */
86 MIPS_MACH_9000 = 0x00990000 | (PF_MIPS_ID << PFLAGS_BIT), /* Unknown */
87 MIPS_MACH_LS2E = 0x00a00000 | (PF_MIPS_ID << PFLAGS_BIT), /* ST Microelectronics Loongson 2E */
88 MIPS_MACH_LS2F = 0x00a10000 | (PF_MIPS_ID << PFLAGS_BIT), /* ST Microelectronics Loongson 2F */
89 MIPS_MACH_LS3A = 0x00a20000 | (PF_MIPS_ID << PFLAGS_BIT), /* Loongson 3A */
90
91 /* ARCH_ASE */
92 MIPS_MICROMIPS = 0x02000000 | (PF_MIPS_ID << PFLAGS_BIT), /* microMIPS */
93 MIPS_ARCH_ASE_M16 = 0x04000000 | (PF_MIPS_ID << PFLAGS_BIT), /* Has Mips-16 ISA extensions */
94 MIPS_ARCH_ASE_MDMX = 0x08000000 | (PF_MIPS_ID << PFLAGS_BIT), /* Has MDMX multimedia extensions */
95
96 /* ARCH */
97 MIPS_ARCH_1 = 0x00000000 | (PF_MIPS_ID << PFLAGS_BIT), /* MIPS1 instruction set */
98 MIPS_ARCH_2 = 0x10000000 | (PF_MIPS_ID << PFLAGS_BIT), /* MIPS2 instruction set */
99 MIPS_ARCH_3 = 0x20000000 | (PF_MIPS_ID << PFLAGS_BIT), /* MIPS3 instruction set */
100 MIPS_ARCH_4 = 0x30000000 | (PF_MIPS_ID << PFLAGS_BIT), /* MIPS4 instruction set */
101 MIPS_ARCH_5 = 0x40000000 | (PF_MIPS_ID << PFLAGS_BIT), /* MIPS5 instruction set */
102 MIPS_ARCH_32 = 0x50000000 | (PF_MIPS_ID << PFLAGS_BIT), /* MIPS32 instruction set per linux not elf.h */
103 MIPS_ARCH_64 = 0x60000000 | (PF_MIPS_ID << PFLAGS_BIT), /* MIPS64 instruction set per linux not elf.h */
104 MIPS_ARCH_32R2 = 0x70000000 | (PF_MIPS_ID << PFLAGS_BIT), /* mips32r2, mips32r3, mips32r5 */
105 MIPS_ARCH_64R2 = 0x80000000 | (PF_MIPS_ID << PFLAGS_BIT), /* mips64r2, mips64r3, mips64r5 */
106 MIPS_ARCH_32R6 = 0x90000000 | (PF_MIPS_ID << PFLAGS_BIT), /* mips32r6 */
107 MIPS_ARCH_64R6 = 0xa0000000 | (PF_MIPS_ID << PFLAGS_BIT), /* mips64r6 */
108};
109
110LIEF_API const char* to_string(PROCESSOR_FLAGS flag);
111
112
113}
114}
115#endif
LIEF::ELF::to_string
const char * to_string(DynamicEntry::TAG e)
LIEF::ELF::PROCESSOR_FLAGS
PROCESSOR_FLAGS
Definition ProcessorFlags.hpp:31
LIEF
LIEF namespace.
Definition Abstract/Binary.hpp:32
LIEF_API
#define LIEF_API
Definition visibility.h:41
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