Bases: Instruction
This class represents an AArch64 instruction
The instruction opcode as defined in LLVM
Iterator over the operands of the current instruction
See: lief.assembly.aarch64.OPCODE
Bases: object
This class represents an operand for an AArch64 instruction
Pretty representation of the operand
Bases: Operand
This class represents a register operand.
mrs x0, TPIDR_EL0
| |
+------+ +-------+
| |
v v
REG SYSREG
The effective register as either: a lief.assembly.aarch64.REG
or a lief.assembly.aarch64.SYSREG
.
Bases: Operand
This class represents a memory operand.
ldr x0, [x1, x2, lsl #3]
| | |
+------------+ | +--------+
| | |
v v v
Base Reg Offset Shift
Bases: Enum
The base register.
For str x3, [x8, #8]
it would return x8
.
The addressing offset.
It can be either:
A register (e.g. ldr x0, [x1, x3]
)
An offset (e.g. ldr x0, [x1, #8]
)
Shift information.
For instance, for ldr x1, [x2, x3, lsl #3]
it would return a LSL
with a value
set to 3
.
Bases: object
This structure holds shift info (type + value)