riscv/operands/Register.hpp

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/* Copyright 2022 - 2026 R. Thomas
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef LIEF_ASM_RISCV_OPERAND_REG_H
#define LIEF_ASM_RISCV_OPERAND_REG_H
 
#include "LIEF/asm/riscv/Operand.hpp"
#include "LIEF/asm/riscv/registers.hpp"
 
 
namespace LIEF::assembly::riscv::operands {

class LIEF_API Register : public Operand {
  public:
  using Operand::Operand;
 
  struct reg_t {
    enum class TYPE {
      NONE = 0,
      SYSREG,
      REG,
    };
 
    union {
      REG reg = REG::NoRegister;
      SYSREG sysreg;
    };
    TYPE type = TYPE::NONE;
  };

  reg_t value() const;
 
  static bool classof(const Operand* op);
  ~Register() override = default;
};
}
 
 
#endif