LIEF: Library to Instrument Executable Formats
Version 1.0.0
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lief-install
x86_64
static
include
LIEF
asm
riscv
operands
riscv/operands/Register.hpp
Go to the documentation of this file.
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/* Copyright 2022 - 2026 R. Thomas
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef LIEF_ASM_RISCV_OPERAND_REG_H
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#define LIEF_ASM_RISCV_OPERAND_REG_H
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#include "
LIEF/asm/riscv/Operand.hpp
"
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#include "
LIEF/asm/riscv/registers.hpp
"
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namespace
LIEF
{
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namespace
assembly
{
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namespace
riscv
{
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namespace
operands
{
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39
class
LIEF_API
Register
:
public
Operand {
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public
:
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using
Operand::Operand;
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struct
reg_t
{
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enum class
TYPE
{
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NONE = 0,
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SYSREG
,
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REG
,
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};
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union
{
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REG
reg
=
REG::NoRegister
;
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SYSREG
sysreg
;
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};
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TYPE
type
=
TYPE::NONE
;
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};
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reg_t
value
()
const
;
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static
bool
classof
(
const
Operand* op);
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~Register
()
override
=
default
;
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};
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}
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}
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}
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}
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#endif
LIEF::assembly::riscv::operands::Register
This class represents a register operand.
Definition
riscv/operands/Register.hpp:39
LIEF::assembly::riscv::operands::Register::~Register
~Register() override=default
LIEF::assembly::riscv::operands::Register::value
reg_t value() const
The effective register as either: a REG or a SYSREG.
LIEF::assembly::riscv::operands::Register::classof
static bool classof(const Operand *op)
LIEF::assembly::riscv::operands
Namespace that wraps the different RISC-V operands.
Definition
riscv/operands/Immediate.hpp:23
LIEF::assembly::riscv
RISC-V architecture-related namespace.
Definition
riscv/Instruction.hpp:27
LIEF::assembly::riscv::REG
REG
Definition
riscv/registers.hpp:25
LIEF::assembly::riscv::REG::NoRegister
@ NoRegister
Definition
riscv/registers.hpp:26
LIEF::assembly::riscv::SYSREG
SYSREG
Definition
riscv/registers.hpp:602
LIEF::assembly
Namespace related to assembly/disassembly support.
Definition
Abstract/Binary.hpp:48
LIEF
LIEF namespace.
Definition
Abstract/Binary.hpp:41
Operand.hpp
registers.hpp
LIEF::assembly::riscv::operands::Register::reg_t
Definition
riscv/operands/Register.hpp:43
LIEF::assembly::riscv::operands::Register::reg_t::TYPE
TYPE
Enum type used to discriminate the anonymous union.
Definition
riscv/operands/Register.hpp:45
LIEF::assembly::riscv::operands::Register::reg_t::TYPE::NONE
@ NONE
Definition
riscv/operands/Register.hpp:46
LIEF::assembly::riscv::operands::Register::reg_t::reg
REG reg
Definition
riscv/operands/Register.hpp:54
LIEF::assembly::riscv::operands::Register::reg_t::sysreg
SYSREG sysreg
Definition
riscv/operands/Register.hpp:55
LIEF::assembly::riscv::operands::Register::reg_t::type
TYPE type
Definition
riscv/operands/Register.hpp:57
LIEF_API
#define LIEF_API
Definition
visibility.h:45
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