LIEF: Library to Instrument Executable Formats Version 0.17.0
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Namespaces | Enumerations | Functions
registers.hpp File Reference
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Namespaces

namespace  LIEF
 LIEF namespace.
 
namespace  LIEF::assembly
 Namespace related to assembly/disassembly support.
 
namespace  LIEF::assembly::riscv
 RISC-V architecture-related namespace.
 

Enumerations

enum class  LIEF::assembly::riscv::REG {
  LIEF::assembly::riscv::NoRegister = 0 , LIEF::assembly::riscv::FFLAGS = 1 , LIEF::assembly::riscv::FRM = 2 , LIEF::assembly::riscv::SSP = 3 ,
  LIEF::assembly::riscv::VCIX_STATE = 4 , LIEF::assembly::riscv::VL = 5 , LIEF::assembly::riscv::VLENB = 6 , LIEF::assembly::riscv::VTYPE = 7 ,
  LIEF::assembly::riscv::VXRM = 8 , LIEF::assembly::riscv::VXSAT = 9 , LIEF::assembly::riscv::DUMMY_REG_PAIR_WITH_X0 = 10 , LIEF::assembly::riscv::V0 = 11 ,
  LIEF::assembly::riscv::V1 = 12 , LIEF::assembly::riscv::V2 = 13 , LIEF::assembly::riscv::V3 = 14 , LIEF::assembly::riscv::V4 = 15 ,
  LIEF::assembly::riscv::V5 = 16 , LIEF::assembly::riscv::V6 = 17 , LIEF::assembly::riscv::V7 = 18 , LIEF::assembly::riscv::V8 = 19 ,
  LIEF::assembly::riscv::V9 = 20 , LIEF::assembly::riscv::V10 = 21 , LIEF::assembly::riscv::V11 = 22 , LIEF::assembly::riscv::V12 = 23 ,
  LIEF::assembly::riscv::V13 = 24 , LIEF::assembly::riscv::V14 = 25 , LIEF::assembly::riscv::V15 = 26 , LIEF::assembly::riscv::V16 = 27 ,
  LIEF::assembly::riscv::V17 = 28 , LIEF::assembly::riscv::V18 = 29 , LIEF::assembly::riscv::V19 = 30 , LIEF::assembly::riscv::V20 = 31 ,
  LIEF::assembly::riscv::V21 = 32 , LIEF::assembly::riscv::V22 = 33 , LIEF::assembly::riscv::V23 = 34 , LIEF::assembly::riscv::V24 = 35 ,
  LIEF::assembly::riscv::V25 = 36 , LIEF::assembly::riscv::V26 = 37 , LIEF::assembly::riscv::V27 = 38 , LIEF::assembly::riscv::V28 = 39 ,
  LIEF::assembly::riscv::V29 = 40 , LIEF::assembly::riscv::V30 = 41 , LIEF::assembly::riscv::V31 = 42 , LIEF::assembly::riscv::X0 = 43 ,
  LIEF::assembly::riscv::X1 = 44 , LIEF::assembly::riscv::X2 = 45 , LIEF::assembly::riscv::X3 = 46 , LIEF::assembly::riscv::X4 = 47 ,
  LIEF::assembly::riscv::X5 = 48 , LIEF::assembly::riscv::X6 = 49 , LIEF::assembly::riscv::X7 = 50 , LIEF::assembly::riscv::X8 = 51 ,
  LIEF::assembly::riscv::X9 = 52 , LIEF::assembly::riscv::X10 = 53 , LIEF::assembly::riscv::X11 = 54 , LIEF::assembly::riscv::X12 = 55 ,
  LIEF::assembly::riscv::X13 = 56 , LIEF::assembly::riscv::X14 = 57 , LIEF::assembly::riscv::X15 = 58 , LIEF::assembly::riscv::X16 = 59 ,
  LIEF::assembly::riscv::X17 = 60 , LIEF::assembly::riscv::X18 = 61 , LIEF::assembly::riscv::X19 = 62 , LIEF::assembly::riscv::X20 = 63 ,
  LIEF::assembly::riscv::X21 = 64 , LIEF::assembly::riscv::X22 = 65 , LIEF::assembly::riscv::X23 = 66 , LIEF::assembly::riscv::X24 = 67 ,
  LIEF::assembly::riscv::X25 = 68 , LIEF::assembly::riscv::X26 = 69 , LIEF::assembly::riscv::X27 = 70 , LIEF::assembly::riscv::X28 = 71 ,
  LIEF::assembly::riscv::X29 = 72 , LIEF::assembly::riscv::X30 = 73 , LIEF::assembly::riscv::X31 = 74 , LIEF::assembly::riscv::F0_D = 75 ,
  LIEF::assembly::riscv::F1_D = 76 , LIEF::assembly::riscv::F2_D = 77 , LIEF::assembly::riscv::F3_D = 78 , LIEF::assembly::riscv::F4_D = 79 ,
  LIEF::assembly::riscv::F5_D = 80 , LIEF::assembly::riscv::F6_D = 81 , LIEF::assembly::riscv::F7_D = 82 , LIEF::assembly::riscv::F8_D = 83 ,
  LIEF::assembly::riscv::F9_D = 84 , LIEF::assembly::riscv::F10_D = 85 , LIEF::assembly::riscv::F11_D = 86 , LIEF::assembly::riscv::F12_D = 87 ,
  LIEF::assembly::riscv::F13_D = 88 , LIEF::assembly::riscv::F14_D = 89 , LIEF::assembly::riscv::F15_D = 90 , LIEF::assembly::riscv::F16_D = 91 ,
  LIEF::assembly::riscv::F17_D = 92 , LIEF::assembly::riscv::F18_D = 93 , LIEF::assembly::riscv::F19_D = 94 , LIEF::assembly::riscv::F20_D = 95 ,
  LIEF::assembly::riscv::F21_D = 96 , LIEF::assembly::riscv::F22_D = 97 , LIEF::assembly::riscv::F23_D = 98 , LIEF::assembly::riscv::F24_D = 99 ,
  LIEF::assembly::riscv::F25_D = 100 , LIEF::assembly::riscv::F26_D = 101 , LIEF::assembly::riscv::F27_D = 102 , LIEF::assembly::riscv::F28_D = 103 ,
  LIEF::assembly::riscv::F29_D = 104 , LIEF::assembly::riscv::F30_D = 105 , LIEF::assembly::riscv::F31_D = 106 , LIEF::assembly::riscv::F0_F = 107 ,
  LIEF::assembly::riscv::F1_F = 108 , LIEF::assembly::riscv::F2_F = 109 , LIEF::assembly::riscv::F3_F = 110 , LIEF::assembly::riscv::F4_F = 111 ,
  LIEF::assembly::riscv::F5_F = 112 , LIEF::assembly::riscv::F6_F = 113 , LIEF::assembly::riscv::F7_F = 114 , LIEF::assembly::riscv::F8_F = 115 ,
  LIEF::assembly::riscv::F9_F = 116 , LIEF::assembly::riscv::F10_F = 117 , LIEF::assembly::riscv::F11_F = 118 , LIEF::assembly::riscv::F12_F = 119 ,
  LIEF::assembly::riscv::F13_F = 120 , LIEF::assembly::riscv::F14_F = 121 , LIEF::assembly::riscv::F15_F = 122 , LIEF::assembly::riscv::F16_F = 123 ,
  LIEF::assembly::riscv::F17_F = 124 , LIEF::assembly::riscv::F18_F = 125 , LIEF::assembly::riscv::F19_F = 126 , LIEF::assembly::riscv::F20_F = 127 ,
  LIEF::assembly::riscv::F21_F = 128 , LIEF::assembly::riscv::F22_F = 129 , LIEF::assembly::riscv::F23_F = 130 , LIEF::assembly::riscv::F24_F = 131 ,
  LIEF::assembly::riscv::F25_F = 132 , LIEF::assembly::riscv::F26_F = 133 , LIEF::assembly::riscv::F27_F = 134 , LIEF::assembly::riscv::F28_F = 135 ,
  LIEF::assembly::riscv::F29_F = 136 , LIEF::assembly::riscv::F30_F = 137 , LIEF::assembly::riscv::F31_F = 138 , LIEF::assembly::riscv::F0_H = 139 ,
  LIEF::assembly::riscv::F1_H = 140 , LIEF::assembly::riscv::F2_H = 141 , LIEF::assembly::riscv::F3_H = 142 , LIEF::assembly::riscv::F4_H = 143 ,
  LIEF::assembly::riscv::F5_H = 144 , LIEF::assembly::riscv::F6_H = 145 , LIEF::assembly::riscv::F7_H = 146 , LIEF::assembly::riscv::F8_H = 147 ,
  LIEF::assembly::riscv::F9_H = 148 , LIEF::assembly::riscv::F10_H = 149 , LIEF::assembly::riscv::F11_H = 150 , LIEF::assembly::riscv::F12_H = 151 ,
  LIEF::assembly::riscv::F13_H = 152 , LIEF::assembly::riscv::F14_H = 153 , LIEF::assembly::riscv::F15_H = 154 , LIEF::assembly::riscv::F16_H = 155 ,
  LIEF::assembly::riscv::F17_H = 156 , LIEF::assembly::riscv::F18_H = 157 , LIEF::assembly::riscv::F19_H = 158 , LIEF::assembly::riscv::F20_H = 159 ,
  LIEF::assembly::riscv::F21_H = 160 , LIEF::assembly::riscv::F22_H = 161 , LIEF::assembly::riscv::F23_H = 162 , LIEF::assembly::riscv::F24_H = 163 ,
  LIEF::assembly::riscv::F25_H = 164 , LIEF::assembly::riscv::F26_H = 165 , LIEF::assembly::riscv::F27_H = 166 , LIEF::assembly::riscv::F28_H = 167 ,
  LIEF::assembly::riscv::F29_H = 168 , LIEF::assembly::riscv::F30_H = 169 , LIEF::assembly::riscv::F31_H = 170 , LIEF::assembly::riscv::X0_Pair = 171 ,
  LIEF::assembly::riscv::V0M2 = 172 , LIEF::assembly::riscv::V0M4 = 173 , LIEF::assembly::riscv::V0M8 = 174 , LIEF::assembly::riscv::V2M2 = 175 ,
  LIEF::assembly::riscv::V4M2 = 176 , LIEF::assembly::riscv::V4M4 = 177 , LIEF::assembly::riscv::V6M2 = 178 , LIEF::assembly::riscv::V8M2 = 179 ,
  LIEF::assembly::riscv::V8M4 = 180 , LIEF::assembly::riscv::V8M8 = 181 , LIEF::assembly::riscv::V10M2 = 182 , LIEF::assembly::riscv::V12M2 = 183 ,
  LIEF::assembly::riscv::V12M4 = 184 , LIEF::assembly::riscv::V14M2 = 185 , LIEF::assembly::riscv::V16M2 = 186 , LIEF::assembly::riscv::V16M4 = 187 ,
  LIEF::assembly::riscv::V16M8 = 188 , LIEF::assembly::riscv::V18M2 = 189 , LIEF::assembly::riscv::V20M2 = 190 , LIEF::assembly::riscv::V20M4 = 191 ,
  LIEF::assembly::riscv::V22M2 = 192 , LIEF::assembly::riscv::V24M2 = 193 , LIEF::assembly::riscv::V24M4 = 194 , LIEF::assembly::riscv::V24M8 = 195 ,
  LIEF::assembly::riscv::V26M2 = 196 , LIEF::assembly::riscv::V28M2 = 197 , LIEF::assembly::riscv::V28M4 = 198 , LIEF::assembly::riscv::V30M2 = 199 ,
  LIEF::assembly::riscv::X2_X3 = 200 , LIEF::assembly::riscv::X4_X5 = 201 , LIEF::assembly::riscv::X6_X7 = 202 , LIEF::assembly::riscv::X8_X9 = 203 ,
  LIEF::assembly::riscv::X10_X11 = 204 , LIEF::assembly::riscv::X12_X13 = 205 , LIEF::assembly::riscv::X14_X15 = 206 , LIEF::assembly::riscv::X16_X17 = 207 ,
  LIEF::assembly::riscv::X18_X19 = 208 , LIEF::assembly::riscv::X20_X21 = 209 , LIEF::assembly::riscv::X22_X23 = 210 , LIEF::assembly::riscv::X24_X25 = 211 ,
  LIEF::assembly::riscv::X26_X27 = 212 , LIEF::assembly::riscv::X28_X29 = 213 , LIEF::assembly::riscv::X30_X31 = 214 , LIEF::assembly::riscv::V1_V2 = 215 ,
  LIEF::assembly::riscv::V2_V3 = 216 , LIEF::assembly::riscv::V3_V4 = 217 , LIEF::assembly::riscv::V4_V5 = 218 , LIEF::assembly::riscv::V5_V6 = 219 ,
  LIEF::assembly::riscv::V6_V7 = 220 , LIEF::assembly::riscv::V7_V8 = 221 , LIEF::assembly::riscv::V8_V9 = 222 , LIEF::assembly::riscv::V9_V10 = 223 ,
  LIEF::assembly::riscv::V10_V11 = 224 , LIEF::assembly::riscv::V11_V12 = 225 , LIEF::assembly::riscv::V12_V13 = 226 , LIEF::assembly::riscv::V13_V14 = 227 ,
  LIEF::assembly::riscv::V14_V15 = 228 , LIEF::assembly::riscv::V15_V16 = 229 , LIEF::assembly::riscv::V16_V17 = 230 , LIEF::assembly::riscv::V17_V18 = 231 ,
  LIEF::assembly::riscv::V18_V19 = 232 , LIEF::assembly::riscv::V19_V20 = 233 , LIEF::assembly::riscv::V20_V21 = 234 , LIEF::assembly::riscv::V21_V22 = 235 ,
  LIEF::assembly::riscv::V22_V23 = 236 , LIEF::assembly::riscv::V23_V24 = 237 , LIEF::assembly::riscv::V24_V25 = 238 , LIEF::assembly::riscv::V25_V26 = 239 ,
  LIEF::assembly::riscv::V26_V27 = 240 , LIEF::assembly::riscv::V27_V28 = 241 , LIEF::assembly::riscv::V28_V29 = 242 , LIEF::assembly::riscv::V29_V30 = 243 ,
  LIEF::assembly::riscv::V30_V31 = 244 , LIEF::assembly::riscv::V0_V1 = 245 , LIEF::assembly::riscv::V2M2_V4M2 = 246 , LIEF::assembly::riscv::V4M2_V6M2 = 247 ,
  LIEF::assembly::riscv::V6M2_V8M2 = 248 , LIEF::assembly::riscv::V8M2_V10M2 = 249 , LIEF::assembly::riscv::V10M2_V12M2 = 250 , LIEF::assembly::riscv::V12M2_V14M2 = 251 ,
  LIEF::assembly::riscv::V14M2_V16M2 = 252 , LIEF::assembly::riscv::V16M2_V18M2 = 253 , LIEF::assembly::riscv::V18M2_V20M2 = 254 , LIEF::assembly::riscv::V20M2_V22M2 = 255 ,
  LIEF::assembly::riscv::V22M2_V24M2 = 256 , LIEF::assembly::riscv::V24M2_V26M2 = 257 , LIEF::assembly::riscv::V26M2_V28M2 = 258 , LIEF::assembly::riscv::V28M2_V30M2 = 259 ,
  LIEF::assembly::riscv::V0M2_V2M2 = 260 , LIEF::assembly::riscv::V4M4_V8M4 = 261 , LIEF::assembly::riscv::V8M4_V12M4 = 262 , LIEF::assembly::riscv::V12M4_V16M4 = 263 ,
  LIEF::assembly::riscv::V16M4_V20M4 = 264 , LIEF::assembly::riscv::V20M4_V24M4 = 265 , LIEF::assembly::riscv::V24M4_V28M4 = 266 , LIEF::assembly::riscv::V0M4_V4M4 = 267 ,
  LIEF::assembly::riscv::V1_V2_V3 = 268 , LIEF::assembly::riscv::V2_V3_V4 = 269 , LIEF::assembly::riscv::V3_V4_V5 = 270 , LIEF::assembly::riscv::V4_V5_V6 = 271 ,
  LIEF::assembly::riscv::V5_V6_V7 = 272 , LIEF::assembly::riscv::V6_V7_V8 = 273 , LIEF::assembly::riscv::V7_V8_V9 = 274 , LIEF::assembly::riscv::V8_V9_V10 = 275 ,
  LIEF::assembly::riscv::V9_V10_V11 = 276 , LIEF::assembly::riscv::V10_V11_V12 = 277 , LIEF::assembly::riscv::V11_V12_V13 = 278 , LIEF::assembly::riscv::V12_V13_V14 = 279 ,
  LIEF::assembly::riscv::V13_V14_V15 = 280 , LIEF::assembly::riscv::V14_V15_V16 = 281 , LIEF::assembly::riscv::V15_V16_V17 = 282 , LIEF::assembly::riscv::V16_V17_V18 = 283 ,
  LIEF::assembly::riscv::V17_V18_V19 = 284 , LIEF::assembly::riscv::V18_V19_V20 = 285 , LIEF::assembly::riscv::V19_V20_V21 = 286 , LIEF::assembly::riscv::V20_V21_V22 = 287 ,
  LIEF::assembly::riscv::V21_V22_V23 = 288 , LIEF::assembly::riscv::V22_V23_V24 = 289 , LIEF::assembly::riscv::V23_V24_V25 = 290 , LIEF::assembly::riscv::V24_V25_V26 = 291 ,
  LIEF::assembly::riscv::V25_V26_V27 = 292 , LIEF::assembly::riscv::V26_V27_V28 = 293 , LIEF::assembly::riscv::V27_V28_V29 = 294 , LIEF::assembly::riscv::V28_V29_V30 = 295 ,
  LIEF::assembly::riscv::V29_V30_V31 = 296 , LIEF::assembly::riscv::V0_V1_V2 = 297 , LIEF::assembly::riscv::V2M2_V4M2_V6M2 = 298 , LIEF::assembly::riscv::V4M2_V6M2_V8M2 = 299 ,
  LIEF::assembly::riscv::V6M2_V8M2_V10M2 = 300 , LIEF::assembly::riscv::V8M2_V10M2_V12M2 = 301 , LIEF::assembly::riscv::V10M2_V12M2_V14M2 = 302 , LIEF::assembly::riscv::V12M2_V14M2_V16M2 = 303 ,
  LIEF::assembly::riscv::V14M2_V16M2_V18M2 = 304 , LIEF::assembly::riscv::V16M2_V18M2_V20M2 = 305 , LIEF::assembly::riscv::V18M2_V20M2_V22M2 = 306 , LIEF::assembly::riscv::V20M2_V22M2_V24M2 = 307 ,
  LIEF::assembly::riscv::V22M2_V24M2_V26M2 = 308 , LIEF::assembly::riscv::V24M2_V26M2_V28M2 = 309 , LIEF::assembly::riscv::V26M2_V28M2_V30M2 = 310 , LIEF::assembly::riscv::V0M2_V2M2_V4M2 = 311 ,
  LIEF::assembly::riscv::V1_V2_V3_V4 = 312 , LIEF::assembly::riscv::V2_V3_V4_V5 = 313 , LIEF::assembly::riscv::V3_V4_V5_V6 = 314 , LIEF::assembly::riscv::V4_V5_V6_V7 = 315 ,
  LIEF::assembly::riscv::V5_V6_V7_V8 = 316 , LIEF::assembly::riscv::V6_V7_V8_V9 = 317 , LIEF::assembly::riscv::V7_V8_V9_V10 = 318 , LIEF::assembly::riscv::V8_V9_V10_V11 = 319 ,
  LIEF::assembly::riscv::V9_V10_V11_V12 = 320 , LIEF::assembly::riscv::V10_V11_V12_V13 = 321 , LIEF::assembly::riscv::V11_V12_V13_V14 = 322 , LIEF::assembly::riscv::V12_V13_V14_V15 = 323 ,
  LIEF::assembly::riscv::V13_V14_V15_V16 = 324 , LIEF::assembly::riscv::V14_V15_V16_V17 = 325 , LIEF::assembly::riscv::V15_V16_V17_V18 = 326 , LIEF::assembly::riscv::V16_V17_V18_V19 = 327 ,
  LIEF::assembly::riscv::V17_V18_V19_V20 = 328 , LIEF::assembly::riscv::V18_V19_V20_V21 = 329 , LIEF::assembly::riscv::V19_V20_V21_V22 = 330 , LIEF::assembly::riscv::V20_V21_V22_V23 = 331 ,
  LIEF::assembly::riscv::V21_V22_V23_V24 = 332 , LIEF::assembly::riscv::V22_V23_V24_V25 = 333 , LIEF::assembly::riscv::V23_V24_V25_V26 = 334 , LIEF::assembly::riscv::V24_V25_V26_V27 = 335 ,
  LIEF::assembly::riscv::V25_V26_V27_V28 = 336 , LIEF::assembly::riscv::V26_V27_V28_V29 = 337 , LIEF::assembly::riscv::V27_V28_V29_V30 = 338 , LIEF::assembly::riscv::V28_V29_V30_V31 = 339 ,
  LIEF::assembly::riscv::V0_V1_V2_V3 = 340 , LIEF::assembly::riscv::V2M2_V4M2_V6M2_V8M2 = 341 , LIEF::assembly::riscv::V4M2_V6M2_V8M2_V10M2 = 342 , LIEF::assembly::riscv::V6M2_V8M2_V10M2_V12M2 = 343 ,
  LIEF::assembly::riscv::V8M2_V10M2_V12M2_V14M2 = 344 , LIEF::assembly::riscv::V10M2_V12M2_V14M2_V16M2 = 345 , LIEF::assembly::riscv::V12M2_V14M2_V16M2_V18M2 = 346 , LIEF::assembly::riscv::V14M2_V16M2_V18M2_V20M2 = 347 ,
  LIEF::assembly::riscv::V16M2_V18M2_V20M2_V22M2 = 348 , LIEF::assembly::riscv::V18M2_V20M2_V22M2_V24M2 = 349 , LIEF::assembly::riscv::V20M2_V22M2_V24M2_V26M2 = 350 , LIEF::assembly::riscv::V22M2_V24M2_V26M2_V28M2 = 351 ,
  LIEF::assembly::riscv::V24M2_V26M2_V28M2_V30M2 = 352 , LIEF::assembly::riscv::V0M2_V2M2_V4M2_V6M2 = 353 , LIEF::assembly::riscv::V1_V2_V3_V4_V5 = 354 , LIEF::assembly::riscv::V2_V3_V4_V5_V6 = 355 ,
  LIEF::assembly::riscv::V3_V4_V5_V6_V7 = 356 , LIEF::assembly::riscv::V4_V5_V6_V7_V8 = 357 , LIEF::assembly::riscv::V5_V6_V7_V8_V9 = 358 , LIEF::assembly::riscv::V6_V7_V8_V9_V10 = 359 ,
  LIEF::assembly::riscv::V7_V8_V9_V10_V11 = 360 , LIEF::assembly::riscv::V8_V9_V10_V11_V12 = 361 , LIEF::assembly::riscv::V9_V10_V11_V12_V13 = 362 , LIEF::assembly::riscv::V10_V11_V12_V13_V14 = 363 ,
  LIEF::assembly::riscv::V11_V12_V13_V14_V15 = 364 , LIEF::assembly::riscv::V12_V13_V14_V15_V16 = 365 , LIEF::assembly::riscv::V13_V14_V15_V16_V17 = 366 , LIEF::assembly::riscv::V14_V15_V16_V17_V18 = 367 ,
  LIEF::assembly::riscv::V15_V16_V17_V18_V19 = 368 , LIEF::assembly::riscv::V16_V17_V18_V19_V20 = 369 , LIEF::assembly::riscv::V17_V18_V19_V20_V21 = 370 , LIEF::assembly::riscv::V18_V19_V20_V21_V22 = 371 ,
  LIEF::assembly::riscv::V19_V20_V21_V22_V23 = 372 , LIEF::assembly::riscv::V20_V21_V22_V23_V24 = 373 , LIEF::assembly::riscv::V21_V22_V23_V24_V25 = 374 , LIEF::assembly::riscv::V22_V23_V24_V25_V26 = 375 ,
  LIEF::assembly::riscv::V23_V24_V25_V26_V27 = 376 , LIEF::assembly::riscv::V24_V25_V26_V27_V28 = 377 , LIEF::assembly::riscv::V25_V26_V27_V28_V29 = 378 , LIEF::assembly::riscv::V26_V27_V28_V29_V30 = 379 ,
  LIEF::assembly::riscv::V27_V28_V29_V30_V31 = 380 , LIEF::assembly::riscv::V0_V1_V2_V3_V4 = 381 , LIEF::assembly::riscv::V1_V2_V3_V4_V5_V6 = 382 , LIEF::assembly::riscv::V2_V3_V4_V5_V6_V7 = 383 ,
  LIEF::assembly::riscv::V3_V4_V5_V6_V7_V8 = 384 , LIEF::assembly::riscv::V4_V5_V6_V7_V8_V9 = 385 , LIEF::assembly::riscv::V5_V6_V7_V8_V9_V10 = 386 , LIEF::assembly::riscv::V6_V7_V8_V9_V10_V11 = 387 ,
  LIEF::assembly::riscv::V7_V8_V9_V10_V11_V12 = 388 , LIEF::assembly::riscv::V8_V9_V10_V11_V12_V13 = 389 , LIEF::assembly::riscv::V9_V10_V11_V12_V13_V14 = 390 , LIEF::assembly::riscv::V10_V11_V12_V13_V14_V15 = 391 ,
  LIEF::assembly::riscv::V11_V12_V13_V14_V15_V16 = 392 , LIEF::assembly::riscv::V12_V13_V14_V15_V16_V17 = 393 , LIEF::assembly::riscv::V13_V14_V15_V16_V17_V18 = 394 , LIEF::assembly::riscv::V14_V15_V16_V17_V18_V19 = 395 ,
  LIEF::assembly::riscv::V15_V16_V17_V18_V19_V20 = 396 , LIEF::assembly::riscv::V16_V17_V18_V19_V20_V21 = 397 , LIEF::assembly::riscv::V17_V18_V19_V20_V21_V22 = 398 , LIEF::assembly::riscv::V18_V19_V20_V21_V22_V23 = 399 ,
  LIEF::assembly::riscv::V19_V20_V21_V22_V23_V24 = 400 , LIEF::assembly::riscv::V20_V21_V22_V23_V24_V25 = 401 , LIEF::assembly::riscv::V21_V22_V23_V24_V25_V26 = 402 , LIEF::assembly::riscv::V22_V23_V24_V25_V26_V27 = 403 ,
  LIEF::assembly::riscv::V23_V24_V25_V26_V27_V28 = 404 , LIEF::assembly::riscv::V24_V25_V26_V27_V28_V29 = 405 , LIEF::assembly::riscv::V25_V26_V27_V28_V29_V30 = 406 , LIEF::assembly::riscv::V26_V27_V28_V29_V30_V31 = 407 ,
  LIEF::assembly::riscv::V0_V1_V2_V3_V4_V5 = 408 , LIEF::assembly::riscv::V1_V2_V3_V4_V5_V6_V7 = 409 , LIEF::assembly::riscv::V2_V3_V4_V5_V6_V7_V8 = 410 , LIEF::assembly::riscv::V3_V4_V5_V6_V7_V8_V9 = 411 ,
  LIEF::assembly::riscv::V4_V5_V6_V7_V8_V9_V10 = 412 , LIEF::assembly::riscv::V5_V6_V7_V8_V9_V10_V11 = 413 , LIEF::assembly::riscv::V6_V7_V8_V9_V10_V11_V12 = 414 , LIEF::assembly::riscv::V7_V8_V9_V10_V11_V12_V13 = 415 ,
  LIEF::assembly::riscv::V8_V9_V10_V11_V12_V13_V14 = 416 , LIEF::assembly::riscv::V9_V10_V11_V12_V13_V14_V15 = 417 , LIEF::assembly::riscv::V10_V11_V12_V13_V14_V15_V16 = 418 , LIEF::assembly::riscv::V11_V12_V13_V14_V15_V16_V17 = 419 ,
  LIEF::assembly::riscv::V12_V13_V14_V15_V16_V17_V18 = 420 , LIEF::assembly::riscv::V13_V14_V15_V16_V17_V18_V19 = 421 , LIEF::assembly::riscv::V14_V15_V16_V17_V18_V19_V20 = 422 , LIEF::assembly::riscv::V15_V16_V17_V18_V19_V20_V21 = 423 ,
  LIEF::assembly::riscv::V16_V17_V18_V19_V20_V21_V22 = 424 , LIEF::assembly::riscv::V17_V18_V19_V20_V21_V22_V23 = 425 , LIEF::assembly::riscv::V18_V19_V20_V21_V22_V23_V24 = 426 , LIEF::assembly::riscv::V19_V20_V21_V22_V23_V24_V25 = 427 ,
  LIEF::assembly::riscv::V20_V21_V22_V23_V24_V25_V26 = 428 , LIEF::assembly::riscv::V21_V22_V23_V24_V25_V26_V27 = 429 , LIEF::assembly::riscv::V22_V23_V24_V25_V26_V27_V28 = 430 , LIEF::assembly::riscv::V23_V24_V25_V26_V27_V28_V29 = 431 ,
  LIEF::assembly::riscv::V24_V25_V26_V27_V28_V29_V30 = 432 , LIEF::assembly::riscv::V25_V26_V27_V28_V29_V30_V31 = 433 , LIEF::assembly::riscv::V0_V1_V2_V3_V4_V5_V6 = 434 , LIEF::assembly::riscv::V1_V2_V3_V4_V5_V6_V7_V8 = 435 ,
  LIEF::assembly::riscv::V2_V3_V4_V5_V6_V7_V8_V9 = 436 , LIEF::assembly::riscv::V3_V4_V5_V6_V7_V8_V9_V10 = 437 , LIEF::assembly::riscv::V4_V5_V6_V7_V8_V9_V10_V11 = 438 , LIEF::assembly::riscv::V5_V6_V7_V8_V9_V10_V11_V12 = 439 ,
  LIEF::assembly::riscv::V6_V7_V8_V9_V10_V11_V12_V13 = 440 , LIEF::assembly::riscv::V7_V8_V9_V10_V11_V12_V13_V14 = 441 , LIEF::assembly::riscv::V8_V9_V10_V11_V12_V13_V14_V15 = 442 , LIEF::assembly::riscv::V9_V10_V11_V12_V13_V14_V15_V16 = 443 ,
  LIEF::assembly::riscv::V10_V11_V12_V13_V14_V15_V16_V17 = 444 , LIEF::assembly::riscv::V11_V12_V13_V14_V15_V16_V17_V18 = 445 , LIEF::assembly::riscv::V12_V13_V14_V15_V16_V17_V18_V19 = 446 , LIEF::assembly::riscv::V13_V14_V15_V16_V17_V18_V19_V20 = 447 ,
  LIEF::assembly::riscv::V14_V15_V16_V17_V18_V19_V20_V21 = 448 , LIEF::assembly::riscv::V15_V16_V17_V18_V19_V20_V21_V22 = 449 , LIEF::assembly::riscv::V16_V17_V18_V19_V20_V21_V22_V23 = 450 , LIEF::assembly::riscv::V17_V18_V19_V20_V21_V22_V23_V24 = 451 ,
  LIEF::assembly::riscv::V18_V19_V20_V21_V22_V23_V24_V25 = 452 , LIEF::assembly::riscv::V19_V20_V21_V22_V23_V24_V25_V26 = 453 , LIEF::assembly::riscv::V20_V21_V22_V23_V24_V25_V26_V27 = 454 , LIEF::assembly::riscv::V21_V22_V23_V24_V25_V26_V27_V28 = 455 ,
  LIEF::assembly::riscv::V22_V23_V24_V25_V26_V27_V28_V29 = 456 , LIEF::assembly::riscv::V23_V24_V25_V26_V27_V28_V29_V30 = 457 , LIEF::assembly::riscv::V24_V25_V26_V27_V28_V29_V30_V31 = 458 , LIEF::assembly::riscv::V0_V1_V2_V3_V4_V5_V6_V7 = 459 ,
  LIEF::assembly::riscv::NUM_TARGET_REGS = 460
}
 

Functions

const char * LIEF::assembly::riscv::get_register_name (REG r)
 
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