LIEF: Library to Instrument Executable Formats Version 0.16.2
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Namespaces | Enumerations
opcodes.hpp File Reference
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Namespaces

namespace  LIEF
 LIEF namespace.
 
namespace  LIEF::assembly
 Namespace related to assembly/disassembly support.
 
namespace  LIEF::assembly::riscv
 RISC-V architecture-related namespace.
 

Enumerations

enum class  LIEF::assembly::riscv::OPCODE {
  LIEF::assembly::riscv::PHI = 0 , LIEF::assembly::riscv::INLINEASM = 1 , LIEF::assembly::riscv::INLINEASM_BR = 2 , LIEF::assembly::riscv::CFI_INSTRUCTION = 3 ,
  LIEF::assembly::riscv::EH_LABEL = 4 , LIEF::assembly::riscv::GC_LABEL = 5 , LIEF::assembly::riscv::ANNOTATION_LABEL = 6 , LIEF::assembly::riscv::KILL = 7 ,
  LIEF::assembly::riscv::EXTRACT_SUBREG = 8 , LIEF::assembly::riscv::INSERT_SUBREG = 9 , LIEF::assembly::riscv::IMPLICIT_DEF = 10 , LIEF::assembly::riscv::SUBREG_TO_REG = 11 ,
  LIEF::assembly::riscv::COPY_TO_REGCLASS = 12 , LIEF::assembly::riscv::DBG_VALUE = 13 , LIEF::assembly::riscv::DBG_VALUE_LIST = 14 , LIEF::assembly::riscv::DBG_INSTR_REF = 15 ,
  LIEF::assembly::riscv::DBG_PHI = 16 , LIEF::assembly::riscv::DBG_LABEL = 17 , LIEF::assembly::riscv::REG_SEQUENCE = 18 , LIEF::assembly::riscv::COPY = 19 ,
  LIEF::assembly::riscv::BUNDLE = 20 , LIEF::assembly::riscv::LIFETIME_START = 21 , LIEF::assembly::riscv::LIFETIME_END = 22 , LIEF::assembly::riscv::PSEUDO_PROBE = 23 ,
  LIEF::assembly::riscv::ARITH_FENCE = 24 , LIEF::assembly::riscv::STACKMAP = 25 , LIEF::assembly::riscv::FENTRY_CALL = 26 , LIEF::assembly::riscv::PATCHPOINT = 27 ,
  LIEF::assembly::riscv::LOAD_STACK_GUARD = 28 , LIEF::assembly::riscv::PREALLOCATED_SETUP = 29 , LIEF::assembly::riscv::PREALLOCATED_ARG = 30 , LIEF::assembly::riscv::STATEPOINT = 31 ,
  LIEF::assembly::riscv::LOCAL_ESCAPE = 32 , LIEF::assembly::riscv::FAULTING_OP = 33 , LIEF::assembly::riscv::PATCHABLE_OP = 34 , LIEF::assembly::riscv::PATCHABLE_FUNCTION_ENTER = 35 ,
  LIEF::assembly::riscv::PATCHABLE_RET = 36 , LIEF::assembly::riscv::PATCHABLE_FUNCTION_EXIT = 37 , LIEF::assembly::riscv::PATCHABLE_TAIL_CALL = 38 , LIEF::assembly::riscv::PATCHABLE_EVENT_CALL = 39 ,
  LIEF::assembly::riscv::PATCHABLE_TYPED_EVENT_CALL = 40 , LIEF::assembly::riscv::ICALL_BRANCH_FUNNEL = 41 , LIEF::assembly::riscv::MEMBARRIER = 42 , LIEF::assembly::riscv::JUMP_TABLE_DEBUG_INFO = 43 ,
  LIEF::assembly::riscv::CONVERGENCECTRL_ENTRY = 44 , LIEF::assembly::riscv::CONVERGENCECTRL_ANCHOR = 45 , LIEF::assembly::riscv::CONVERGENCECTRL_LOOP = 46 , LIEF::assembly::riscv::CONVERGENCECTRL_GLUE = 47 ,
  LIEF::assembly::riscv::G_ASSERT_SEXT = 48 , LIEF::assembly::riscv::G_ASSERT_ZEXT = 49 , LIEF::assembly::riscv::G_ASSERT_ALIGN = 50 , LIEF::assembly::riscv::G_ADD = 51 ,
  LIEF::assembly::riscv::G_SUB = 52 , LIEF::assembly::riscv::G_MUL = 53 , LIEF::assembly::riscv::G_SDIV = 54 , LIEF::assembly::riscv::G_UDIV = 55 ,
  LIEF::assembly::riscv::G_SREM = 56 , LIEF::assembly::riscv::G_UREM = 57 , LIEF::assembly::riscv::G_SDIVREM = 58 , LIEF::assembly::riscv::G_UDIVREM = 59 ,
  LIEF::assembly::riscv::G_AND = 60 , LIEF::assembly::riscv::G_OR = 61 , LIEF::assembly::riscv::G_XOR = 62 , LIEF::assembly::riscv::G_IMPLICIT_DEF = 63 ,
  LIEF::assembly::riscv::G_PHI = 64 , LIEF::assembly::riscv::G_FRAME_INDEX = 65 , LIEF::assembly::riscv::G_GLOBAL_VALUE = 66 , LIEF::assembly::riscv::G_PTRAUTH_GLOBAL_VALUE = 67 ,
  LIEF::assembly::riscv::G_CONSTANT_POOL = 68 , LIEF::assembly::riscv::G_EXTRACT = 69 , LIEF::assembly::riscv::G_UNMERGE_VALUES = 70 , LIEF::assembly::riscv::G_INSERT = 71 ,
  LIEF::assembly::riscv::G_MERGE_VALUES = 72 , LIEF::assembly::riscv::G_BUILD_VECTOR = 73 , LIEF::assembly::riscv::G_BUILD_VECTOR_TRUNC = 74 , LIEF::assembly::riscv::G_CONCAT_VECTORS = 75 ,
  LIEF::assembly::riscv::G_PTRTOINT = 76 , LIEF::assembly::riscv::G_INTTOPTR = 77 , LIEF::assembly::riscv::G_BITCAST = 78 , LIEF::assembly::riscv::G_FREEZE = 79 ,
  LIEF::assembly::riscv::G_CONSTANT_FOLD_BARRIER = 80 , LIEF::assembly::riscv::G_INTRINSIC_FPTRUNC_ROUND = 81 , LIEF::assembly::riscv::G_INTRINSIC_TRUNC = 82 , LIEF::assembly::riscv::G_INTRINSIC_ROUND = 83 ,
  LIEF::assembly::riscv::G_INTRINSIC_LRINT = 84 , LIEF::assembly::riscv::G_INTRINSIC_LLRINT = 85 , LIEF::assembly::riscv::G_INTRINSIC_ROUNDEVEN = 86 , LIEF::assembly::riscv::G_READCYCLECOUNTER = 87 ,
  LIEF::assembly::riscv::G_READSTEADYCOUNTER = 88 , LIEF::assembly::riscv::G_LOAD = 89 , LIEF::assembly::riscv::G_SEXTLOAD = 90 , LIEF::assembly::riscv::G_ZEXTLOAD = 91 ,
  LIEF::assembly::riscv::G_INDEXED_LOAD = 92 , LIEF::assembly::riscv::G_INDEXED_SEXTLOAD = 93 , LIEF::assembly::riscv::G_INDEXED_ZEXTLOAD = 94 , LIEF::assembly::riscv::G_STORE = 95 ,
  LIEF::assembly::riscv::G_INDEXED_STORE = 96 , LIEF::assembly::riscv::G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97 , LIEF::assembly::riscv::G_ATOMIC_CMPXCHG = 98 , LIEF::assembly::riscv::G_ATOMICRMW_XCHG = 99 ,
  LIEF::assembly::riscv::G_ATOMICRMW_ADD = 100 , LIEF::assembly::riscv::G_ATOMICRMW_SUB = 101 , LIEF::assembly::riscv::G_ATOMICRMW_AND = 102 , LIEF::assembly::riscv::G_ATOMICRMW_NAND = 103 ,
  LIEF::assembly::riscv::G_ATOMICRMW_OR = 104 , LIEF::assembly::riscv::G_ATOMICRMW_XOR = 105 , LIEF::assembly::riscv::G_ATOMICRMW_MAX = 106 , LIEF::assembly::riscv::G_ATOMICRMW_MIN = 107 ,
  LIEF::assembly::riscv::G_ATOMICRMW_UMAX = 108 , LIEF::assembly::riscv::G_ATOMICRMW_UMIN = 109 , LIEF::assembly::riscv::G_ATOMICRMW_FADD = 110 , LIEF::assembly::riscv::G_ATOMICRMW_FSUB = 111 ,
  LIEF::assembly::riscv::G_ATOMICRMW_FMAX = 112 , LIEF::assembly::riscv::G_ATOMICRMW_FMIN = 113 , LIEF::assembly::riscv::G_ATOMICRMW_UINC_WRAP = 114 , LIEF::assembly::riscv::G_ATOMICRMW_UDEC_WRAP = 115 ,
  LIEF::assembly::riscv::G_FENCE = 116 , LIEF::assembly::riscv::G_PREFETCH = 117 , LIEF::assembly::riscv::G_BRCOND = 118 , LIEF::assembly::riscv::G_BRINDIRECT = 119 ,
  LIEF::assembly::riscv::G_INVOKE_REGION_START = 120 , LIEF::assembly::riscv::G_INTRINSIC = 121 , LIEF::assembly::riscv::G_INTRINSIC_W_SIDE_EFFECTS = 122 , LIEF::assembly::riscv::G_INTRINSIC_CONVERGENT = 123 ,
  LIEF::assembly::riscv::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124 , LIEF::assembly::riscv::G_ANYEXT = 125 , LIEF::assembly::riscv::G_TRUNC = 126 , LIEF::assembly::riscv::G_CONSTANT = 127 ,
  LIEF::assembly::riscv::G_FCONSTANT = 128 , LIEF::assembly::riscv::G_VASTART = 129 , LIEF::assembly::riscv::G_VAARG = 130 , LIEF::assembly::riscv::G_SEXT = 131 ,
  LIEF::assembly::riscv::G_SEXT_INREG = 132 , LIEF::assembly::riscv::G_ZEXT = 133 , LIEF::assembly::riscv::G_SHL = 134 , LIEF::assembly::riscv::G_LSHR = 135 ,
  LIEF::assembly::riscv::G_ASHR = 136 , LIEF::assembly::riscv::G_FSHL = 137 , LIEF::assembly::riscv::G_FSHR = 138 , LIEF::assembly::riscv::G_ROTR = 139 ,
  LIEF::assembly::riscv::G_ROTL = 140 , LIEF::assembly::riscv::G_ICMP = 141 , LIEF::assembly::riscv::G_FCMP = 142 , LIEF::assembly::riscv::G_SCMP = 143 ,
  LIEF::assembly::riscv::G_UCMP = 144 , LIEF::assembly::riscv::G_SELECT = 145 , LIEF::assembly::riscv::G_UADDO = 146 , LIEF::assembly::riscv::G_UADDE = 147 ,
  LIEF::assembly::riscv::G_USUBO = 148 , LIEF::assembly::riscv::G_USUBE = 149 , LIEF::assembly::riscv::G_SADDO = 150 , LIEF::assembly::riscv::G_SADDE = 151 ,
  LIEF::assembly::riscv::G_SSUBO = 152 , LIEF::assembly::riscv::G_SSUBE = 153 , LIEF::assembly::riscv::G_UMULO = 154 , LIEF::assembly::riscv::G_SMULO = 155 ,
  LIEF::assembly::riscv::G_UMULH = 156 , LIEF::assembly::riscv::G_SMULH = 157 , LIEF::assembly::riscv::G_UADDSAT = 158 , LIEF::assembly::riscv::G_SADDSAT = 159 ,
  LIEF::assembly::riscv::G_USUBSAT = 160 , LIEF::assembly::riscv::G_SSUBSAT = 161 , LIEF::assembly::riscv::G_USHLSAT = 162 , LIEF::assembly::riscv::G_SSHLSAT = 163 ,
  LIEF::assembly::riscv::G_SMULFIX = 164 , LIEF::assembly::riscv::G_UMULFIX = 165 , LIEF::assembly::riscv::G_SMULFIXSAT = 166 , LIEF::assembly::riscv::G_UMULFIXSAT = 167 ,
  LIEF::assembly::riscv::G_SDIVFIX = 168 , LIEF::assembly::riscv::G_UDIVFIX = 169 , LIEF::assembly::riscv::G_SDIVFIXSAT = 170 , LIEF::assembly::riscv::G_UDIVFIXSAT = 171 ,
  LIEF::assembly::riscv::G_FADD = 172 , LIEF::assembly::riscv::G_FSUB = 173 , LIEF::assembly::riscv::G_FMUL = 174 , LIEF::assembly::riscv::G_FMA = 175 ,
  LIEF::assembly::riscv::G_FMAD = 176 , LIEF::assembly::riscv::G_FDIV = 177 , LIEF::assembly::riscv::G_FREM = 178 , LIEF::assembly::riscv::G_FPOW = 179 ,
  LIEF::assembly::riscv::G_FPOWI = 180 , LIEF::assembly::riscv::G_FEXP = 181 , LIEF::assembly::riscv::G_FEXP2 = 182 , LIEF::assembly::riscv::G_FEXP10 = 183 ,
  LIEF::assembly::riscv::G_FLOG = 184 , LIEF::assembly::riscv::G_FLOG2 = 185 , LIEF::assembly::riscv::G_FLOG10 = 186 , LIEF::assembly::riscv::G_FLDEXP = 187 ,
  LIEF::assembly::riscv::G_FFREXP = 188 , LIEF::assembly::riscv::G_FNEG = 189 , LIEF::assembly::riscv::G_FPEXT = 190 , LIEF::assembly::riscv::G_FPTRUNC = 191 ,
  LIEF::assembly::riscv::G_FPTOSI = 192 , LIEF::assembly::riscv::G_FPTOUI = 193 , LIEF::assembly::riscv::G_SITOFP = 194 , LIEF::assembly::riscv::G_UITOFP = 195 ,
  LIEF::assembly::riscv::G_FABS = 196 , LIEF::assembly::riscv::G_FCOPYSIGN = 197 , LIEF::assembly::riscv::G_IS_FPCLASS = 198 , LIEF::assembly::riscv::G_FCANONICALIZE = 199 ,
  LIEF::assembly::riscv::G_FMINNUM = 200 , LIEF::assembly::riscv::G_FMAXNUM = 201 , LIEF::assembly::riscv::G_FMINNUM_IEEE = 202 , LIEF::assembly::riscv::G_FMAXNUM_IEEE = 203 ,
  LIEF::assembly::riscv::G_FMINIMUM = 204 , LIEF::assembly::riscv::G_FMAXIMUM = 205 , LIEF::assembly::riscv::G_GET_FPENV = 206 , LIEF::assembly::riscv::G_SET_FPENV = 207 ,
  LIEF::assembly::riscv::G_RESET_FPENV = 208 , LIEF::assembly::riscv::G_GET_FPMODE = 209 , LIEF::assembly::riscv::G_SET_FPMODE = 210 , LIEF::assembly::riscv::G_RESET_FPMODE = 211 ,
  LIEF::assembly::riscv::G_PTR_ADD = 212 , LIEF::assembly::riscv::G_PTRMASK = 213 , LIEF::assembly::riscv::G_SMIN = 214 , LIEF::assembly::riscv::G_SMAX = 215 ,
  LIEF::assembly::riscv::G_UMIN = 216 , LIEF::assembly::riscv::G_UMAX = 217 , LIEF::assembly::riscv::G_ABS = 218 , LIEF::assembly::riscv::G_LROUND = 219 ,
  LIEF::assembly::riscv::G_LLROUND = 220 , LIEF::assembly::riscv::G_BR = 221 , LIEF::assembly::riscv::G_BRJT = 222 , LIEF::assembly::riscv::G_VSCALE = 223 ,
  LIEF::assembly::riscv::G_INSERT_SUBVECTOR = 224 , LIEF::assembly::riscv::G_EXTRACT_SUBVECTOR = 225 , LIEF::assembly::riscv::G_INSERT_VECTOR_ELT = 226 , LIEF::assembly::riscv::G_EXTRACT_VECTOR_ELT = 227 ,
  LIEF::assembly::riscv::G_SHUFFLE_VECTOR = 228 , LIEF::assembly::riscv::G_SPLAT_VECTOR = 229 , LIEF::assembly::riscv::G_VECTOR_COMPRESS = 230 , LIEF::assembly::riscv::G_CTTZ = 231 ,
  LIEF::assembly::riscv::G_CTTZ_ZERO_UNDEF = 232 , LIEF::assembly::riscv::G_CTLZ = 233 , LIEF::assembly::riscv::G_CTLZ_ZERO_UNDEF = 234 , LIEF::assembly::riscv::G_CTPOP = 235 ,
  LIEF::assembly::riscv::G_BSWAP = 236 , LIEF::assembly::riscv::G_BITREVERSE = 237 , LIEF::assembly::riscv::G_FCEIL = 238 , LIEF::assembly::riscv::G_FCOS = 239 ,
  LIEF::assembly::riscv::G_FSIN = 240 , LIEF::assembly::riscv::G_FTAN = 241 , LIEF::assembly::riscv::G_FACOS = 242 , LIEF::assembly::riscv::G_FASIN = 243 ,
  LIEF::assembly::riscv::G_FATAN = 244 , LIEF::assembly::riscv::G_FCOSH = 245 , LIEF::assembly::riscv::G_FSINH = 246 , LIEF::assembly::riscv::G_FTANH = 247 ,
  LIEF::assembly::riscv::G_FSQRT = 248 , LIEF::assembly::riscv::G_FFLOOR = 249 , LIEF::assembly::riscv::G_FRINT = 250 , LIEF::assembly::riscv::G_FNEARBYINT = 251 ,
  LIEF::assembly::riscv::G_ADDRSPACE_CAST = 252 , LIEF::assembly::riscv::G_BLOCK_ADDR = 253 , LIEF::assembly::riscv::G_JUMP_TABLE = 254 , LIEF::assembly::riscv::G_DYN_STACKALLOC = 255 ,
  LIEF::assembly::riscv::G_STACKSAVE = 256 , LIEF::assembly::riscv::G_STACKRESTORE = 257 , LIEF::assembly::riscv::G_STRICT_FADD = 258 , LIEF::assembly::riscv::G_STRICT_FSUB = 259 ,
  LIEF::assembly::riscv::G_STRICT_FMUL = 260 , LIEF::assembly::riscv::G_STRICT_FDIV = 261 , LIEF::assembly::riscv::G_STRICT_FREM = 262 , LIEF::assembly::riscv::G_STRICT_FMA = 263 ,
  LIEF::assembly::riscv::G_STRICT_FSQRT = 264 , LIEF::assembly::riscv::G_STRICT_FLDEXP = 265 , LIEF::assembly::riscv::G_READ_REGISTER = 266 , LIEF::assembly::riscv::G_WRITE_REGISTER = 267 ,
  LIEF::assembly::riscv::G_MEMCPY = 268 , LIEF::assembly::riscv::G_MEMCPY_INLINE = 269 , LIEF::assembly::riscv::G_MEMMOVE = 270 , LIEF::assembly::riscv::G_MEMSET = 271 ,
  LIEF::assembly::riscv::G_BZERO = 272 , LIEF::assembly::riscv::G_TRAP = 273 , LIEF::assembly::riscv::G_DEBUGTRAP = 274 , LIEF::assembly::riscv::G_UBSANTRAP = 275 ,
  LIEF::assembly::riscv::G_VECREDUCE_SEQ_FADD = 276 , LIEF::assembly::riscv::G_VECREDUCE_SEQ_FMUL = 277 , LIEF::assembly::riscv::G_VECREDUCE_FADD = 278 , LIEF::assembly::riscv::G_VECREDUCE_FMUL = 279 ,
  LIEF::assembly::riscv::G_VECREDUCE_FMAX = 280 , LIEF::assembly::riscv::G_VECREDUCE_FMIN = 281 , LIEF::assembly::riscv::G_VECREDUCE_FMAXIMUM = 282 , LIEF::assembly::riscv::G_VECREDUCE_FMINIMUM = 283 ,
  LIEF::assembly::riscv::G_VECREDUCE_ADD = 284 , LIEF::assembly::riscv::G_VECREDUCE_MUL = 285 , LIEF::assembly::riscv::G_VECREDUCE_AND = 286 , LIEF::assembly::riscv::G_VECREDUCE_OR = 287 ,
  LIEF::assembly::riscv::G_VECREDUCE_XOR = 288 , LIEF::assembly::riscv::G_VECREDUCE_SMAX = 289 , LIEF::assembly::riscv::G_VECREDUCE_SMIN = 290 , LIEF::assembly::riscv::G_VECREDUCE_UMAX = 291 ,
  LIEF::assembly::riscv::G_VECREDUCE_UMIN = 292 , LIEF::assembly::riscv::G_SBFX = 293 , LIEF::assembly::riscv::G_UBFX = 294 , LIEF::assembly::riscv::ADJCALLSTACKDOWN = 295 ,
  LIEF::assembly::riscv::ADJCALLSTACKUP = 296 , LIEF::assembly::riscv::BuildPairF64Pseudo = 297 , LIEF::assembly::riscv::G_FCLASS = 298 , LIEF::assembly::riscv::G_READ_VLENB = 299 ,
  LIEF::assembly::riscv::G_SPLAT_VECTOR_SPLIT_I64_VL = 300 , LIEF::assembly::riscv::G_VMCLR_VL = 301 , LIEF::assembly::riscv::G_VMSET_VL = 302 , LIEF::assembly::riscv::HWASAN_CHECK_MEMACCESS_SHORTGRANULES = 303 ,
  LIEF::assembly::riscv::KCFI_CHECK = 304 , LIEF::assembly::riscv::PseudoAddTPRel = 305 , LIEF::assembly::riscv::PseudoAtomicLoadNand32 = 306 , LIEF::assembly::riscv::PseudoAtomicLoadNand64 = 307 ,
  LIEF::assembly::riscv::PseudoBR = 308 , LIEF::assembly::riscv::PseudoBRIND = 309 , LIEF::assembly::riscv::PseudoBRINDNonX7 = 310 , LIEF::assembly::riscv::PseudoBRINDX7 = 311 ,
  LIEF::assembly::riscv::PseudoCALL = 312 , LIEF::assembly::riscv::PseudoCALLIndirect = 313 , LIEF::assembly::riscv::PseudoCALLIndirectNonX7 = 314 , LIEF::assembly::riscv::PseudoCALLReg = 315 ,
  LIEF::assembly::riscv::PseudoCCADD = 316 , LIEF::assembly::riscv::PseudoCCADDI = 317 , LIEF::assembly::riscv::PseudoCCADDIW = 318 , LIEF::assembly::riscv::PseudoCCADDW = 319 ,
  LIEF::assembly::riscv::PseudoCCAND = 320 , LIEF::assembly::riscv::PseudoCCANDI = 321 , LIEF::assembly::riscv::PseudoCCANDN = 322 , LIEF::assembly::riscv::PseudoCCMOVGPR = 323 ,
  LIEF::assembly::riscv::PseudoCCMOVGPRNoX0 = 324 , LIEF::assembly::riscv::PseudoCCOR = 325 , LIEF::assembly::riscv::PseudoCCORI = 326 , LIEF::assembly::riscv::PseudoCCORN = 327 ,
  LIEF::assembly::riscv::PseudoCCSLL = 328 , LIEF::assembly::riscv::PseudoCCSLLI = 329 , LIEF::assembly::riscv::PseudoCCSLLIW = 330 , LIEF::assembly::riscv::PseudoCCSLLW = 331 ,
  LIEF::assembly::riscv::PseudoCCSRA = 332 , LIEF::assembly::riscv::PseudoCCSRAI = 333 , LIEF::assembly::riscv::PseudoCCSRAIW = 334 , LIEF::assembly::riscv::PseudoCCSRAW = 335 ,
  LIEF::assembly::riscv::PseudoCCSRL = 336 , LIEF::assembly::riscv::PseudoCCSRLI = 337 , LIEF::assembly::riscv::PseudoCCSRLIW = 338 , LIEF::assembly::riscv::PseudoCCSRLW = 339 ,
  LIEF::assembly::riscv::PseudoCCSUB = 340 , LIEF::assembly::riscv::PseudoCCSUBW = 341 , LIEF::assembly::riscv::PseudoCCXNOR = 342 , LIEF::assembly::riscv::PseudoCCXOR = 343 ,
  LIEF::assembly::riscv::PseudoCCXORI = 344 , LIEF::assembly::riscv::PseudoCmpXchg32 = 345 , LIEF::assembly::riscv::PseudoCmpXchg64 = 346 , LIEF::assembly::riscv::PseudoFLD = 347 ,
  LIEF::assembly::riscv::PseudoFLH = 348 , LIEF::assembly::riscv::PseudoFLW = 349 , LIEF::assembly::riscv::PseudoFROUND_D = 350 , LIEF::assembly::riscv::PseudoFROUND_D_IN32X = 351 ,
  LIEF::assembly::riscv::PseudoFROUND_D_INX = 352 , LIEF::assembly::riscv::PseudoFROUND_H = 353 , LIEF::assembly::riscv::PseudoFROUND_H_INX = 354 , LIEF::assembly::riscv::PseudoFROUND_S = 355 ,
  LIEF::assembly::riscv::PseudoFROUND_S_INX = 356 , LIEF::assembly::riscv::PseudoFSD = 357 , LIEF::assembly::riscv::PseudoFSH = 358 , LIEF::assembly::riscv::PseudoFSW = 359 ,
  LIEF::assembly::riscv::PseudoJump = 360 , LIEF::assembly::riscv::PseudoLA = 361 , LIEF::assembly::riscv::PseudoLAImm = 362 , LIEF::assembly::riscv::PseudoLA_TLSDESC = 363 ,
  LIEF::assembly::riscv::PseudoLA_TLS_GD = 364 , LIEF::assembly::riscv::PseudoLA_TLS_IE = 365 , LIEF::assembly::riscv::PseudoLB = 366 , LIEF::assembly::riscv::PseudoLBU = 367 ,
  LIEF::assembly::riscv::PseudoLD = 368 , LIEF::assembly::riscv::PseudoLGA = 369 , LIEF::assembly::riscv::PseudoLH = 370 , LIEF::assembly::riscv::PseudoLHU = 371 ,
  LIEF::assembly::riscv::PseudoLI = 372 , LIEF::assembly::riscv::PseudoLLA = 373 , LIEF::assembly::riscv::PseudoLLAImm = 374 , LIEF::assembly::riscv::PseudoLW = 375 ,
  LIEF::assembly::riscv::PseudoLWU = 376 , LIEF::assembly::riscv::PseudoLongBEQ = 377 , LIEF::assembly::riscv::PseudoLongBGE = 378 , LIEF::assembly::riscv::PseudoLongBGEU = 379 ,
  LIEF::assembly::riscv::PseudoLongBLT = 380 , LIEF::assembly::riscv::PseudoLongBLTU = 381 , LIEF::assembly::riscv::PseudoLongBNE = 382 , LIEF::assembly::riscv::PseudoMaskedAtomicLoadAdd32 = 383 ,
  LIEF::assembly::riscv::PseudoMaskedAtomicLoadMax32 = 384 , LIEF::assembly::riscv::PseudoMaskedAtomicLoadMin32 = 385 , LIEF::assembly::riscv::PseudoMaskedAtomicLoadNand32 = 386 , LIEF::assembly::riscv::PseudoMaskedAtomicLoadSub32 = 387 ,
  LIEF::assembly::riscv::PseudoMaskedAtomicLoadUMax32 = 388 , LIEF::assembly::riscv::PseudoMaskedAtomicLoadUMin32 = 389 , LIEF::assembly::riscv::PseudoMaskedAtomicSwap32 = 390 , LIEF::assembly::riscv::PseudoMaskedCmpXchg32 = 391 ,
  LIEF::assembly::riscv::PseudoMovAddr = 392 , LIEF::assembly::riscv::PseudoMovImm = 393 , LIEF::assembly::riscv::PseudoQuietFLE_D = 394 , LIEF::assembly::riscv::PseudoQuietFLE_D_IN32X = 395 ,
  LIEF::assembly::riscv::PseudoQuietFLE_D_INX = 396 , LIEF::assembly::riscv::PseudoQuietFLE_H = 397 , LIEF::assembly::riscv::PseudoQuietFLE_H_INX = 398 , LIEF::assembly::riscv::PseudoQuietFLE_S = 399 ,
  LIEF::assembly::riscv::PseudoQuietFLE_S_INX = 400 , LIEF::assembly::riscv::PseudoQuietFLT_D = 401 , LIEF::assembly::riscv::PseudoQuietFLT_D_IN32X = 402 , LIEF::assembly::riscv::PseudoQuietFLT_D_INX = 403 ,
  LIEF::assembly::riscv::PseudoQuietFLT_H = 404 , LIEF::assembly::riscv::PseudoQuietFLT_H_INX = 405 , LIEF::assembly::riscv::PseudoQuietFLT_S = 406 , LIEF::assembly::riscv::PseudoQuietFLT_S_INX = 407 ,
  LIEF::assembly::riscv::PseudoRET = 408 , LIEF::assembly::riscv::PseudoRV32ZdinxLD = 409 , LIEF::assembly::riscv::PseudoRV32ZdinxSD = 410 , LIEF::assembly::riscv::PseudoRVVInitUndefM1 = 411 ,
  LIEF::assembly::riscv::PseudoRVVInitUndefM2 = 412 , LIEF::assembly::riscv::PseudoRVVInitUndefM4 = 413 , LIEF::assembly::riscv::PseudoRVVInitUndefM8 = 414 , LIEF::assembly::riscv::PseudoReadVL = 415 ,
  LIEF::assembly::riscv::PseudoReadVLENB = 416 , LIEF::assembly::riscv::PseudoSB = 417 , LIEF::assembly::riscv::PseudoSD = 418 , LIEF::assembly::riscv::PseudoSEXT_B = 419 ,
  LIEF::assembly::riscv::PseudoSEXT_H = 420 , LIEF::assembly::riscv::PseudoSH = 421 , LIEF::assembly::riscv::PseudoSW = 422 , LIEF::assembly::riscv::PseudoTAIL = 423 ,
  LIEF::assembly::riscv::PseudoTAILIndirect = 424 , LIEF::assembly::riscv::PseudoTAILIndirectNonX7 = 425 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VV_M1 = 426 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VV_M1_MASK = 427 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VV_M2 = 428 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VV_M2_MASK = 429 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VV_M4 = 430 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VV_M4_MASK = 431 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VV_M8 = 432 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VV_M8_MASK = 433 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VV_MF2 = 434 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VV_MF2_MASK = 435 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VX_M1 = 436 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VX_M1_MASK = 437 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VX_M2 = 438 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VX_M2_MASK = 439 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VX_M4 = 440 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VX_M4_MASK = 441 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VX_M8 = 442 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VX_M8_MASK = 443 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VX_MF2 = 444 , LIEF::assembly::riscv::PseudoTHVdotVMAQASU_VX_MF2_MASK = 445 , LIEF::assembly::riscv::PseudoTHVdotVMAQAUS_VX_M1 = 446 , LIEF::assembly::riscv::PseudoTHVdotVMAQAUS_VX_M1_MASK = 447 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQAUS_VX_M2 = 448 , LIEF::assembly::riscv::PseudoTHVdotVMAQAUS_VX_M2_MASK = 449 , LIEF::assembly::riscv::PseudoTHVdotVMAQAUS_VX_M4 = 450 , LIEF::assembly::riscv::PseudoTHVdotVMAQAUS_VX_M4_MASK = 451 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQAUS_VX_M8 = 452 , LIEF::assembly::riscv::PseudoTHVdotVMAQAUS_VX_M8_MASK = 453 , LIEF::assembly::riscv::PseudoTHVdotVMAQAUS_VX_MF2 = 454 , LIEF::assembly::riscv::PseudoTHVdotVMAQAUS_VX_MF2_MASK = 455 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VV_M1 = 456 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VV_M1_MASK = 457 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VV_M2 = 458 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VV_M2_MASK = 459 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VV_M4 = 460 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VV_M4_MASK = 461 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VV_M8 = 462 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VV_M8_MASK = 463 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VV_MF2 = 464 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VV_MF2_MASK = 465 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VX_M1 = 466 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VX_M1_MASK = 467 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VX_M2 = 468 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VX_M2_MASK = 469 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VX_M4 = 470 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VX_M4_MASK = 471 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VX_M8 = 472 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VX_M8_MASK = 473 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VX_MF2 = 474 , LIEF::assembly::riscv::PseudoTHVdotVMAQAU_VX_MF2_MASK = 475 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQA_VV_M1 = 476 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VV_M1_MASK = 477 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VV_M2 = 478 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VV_M2_MASK = 479 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQA_VV_M4 = 480 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VV_M4_MASK = 481 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VV_M8 = 482 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VV_M8_MASK = 483 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQA_VV_MF2 = 484 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VV_MF2_MASK = 485 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VX_M1 = 486 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VX_M1_MASK = 487 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQA_VX_M2 = 488 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VX_M2_MASK = 489 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VX_M4 = 490 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VX_M4_MASK = 491 ,
  LIEF::assembly::riscv::PseudoTHVdotVMAQA_VX_M8 = 492 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VX_M8_MASK = 493 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VX_MF2 = 494 , LIEF::assembly::riscv::PseudoTHVdotVMAQA_VX_MF2_MASK = 495 ,
  LIEF::assembly::riscv::PseudoTLSDESCCall = 496 , LIEF::assembly::riscv::PseudoVAADDU_VV_M1 = 497 , LIEF::assembly::riscv::PseudoVAADDU_VV_M1_MASK = 498 , LIEF::assembly::riscv::PseudoVAADDU_VV_M2 = 499 ,
  LIEF::assembly::riscv::PseudoVAADDU_VV_M2_MASK = 500 , LIEF::assembly::riscv::PseudoVAADDU_VV_M4 = 501 , LIEF::assembly::riscv::PseudoVAADDU_VV_M4_MASK = 502 , LIEF::assembly::riscv::PseudoVAADDU_VV_M8 = 503 ,
  LIEF::assembly::riscv::PseudoVAADDU_VV_M8_MASK = 504 , LIEF::assembly::riscv::PseudoVAADDU_VV_MF2 = 505 , LIEF::assembly::riscv::PseudoVAADDU_VV_MF2_MASK = 506 , LIEF::assembly::riscv::PseudoVAADDU_VV_MF4 = 507 ,
  LIEF::assembly::riscv::PseudoVAADDU_VV_MF4_MASK = 508 , LIEF::assembly::riscv::PseudoVAADDU_VV_MF8 = 509 , LIEF::assembly::riscv::PseudoVAADDU_VV_MF8_MASK = 510 , LIEF::assembly::riscv::PseudoVAADDU_VX_M1 = 511 ,
  LIEF::assembly::riscv::PseudoVAADDU_VX_M1_MASK = 512 , LIEF::assembly::riscv::PseudoVAADDU_VX_M2 = 513 , LIEF::assembly::riscv::PseudoVAADDU_VX_M2_MASK = 514 , LIEF::assembly::riscv::PseudoVAADDU_VX_M4 = 515 ,
  LIEF::assembly::riscv::PseudoVAADDU_VX_M4_MASK = 516 , LIEF::assembly::riscv::PseudoVAADDU_VX_M8 = 517 , LIEF::assembly::riscv::PseudoVAADDU_VX_M8_MASK = 518 , LIEF::assembly::riscv::PseudoVAADDU_VX_MF2 = 519 ,
  LIEF::assembly::riscv::PseudoVAADDU_VX_MF2_MASK = 520 , LIEF::assembly::riscv::PseudoVAADDU_VX_MF4 = 521 , LIEF::assembly::riscv::PseudoVAADDU_VX_MF4_MASK = 522 , LIEF::assembly::riscv::PseudoVAADDU_VX_MF8 = 523 ,
  LIEF::assembly::riscv::PseudoVAADDU_VX_MF8_MASK = 524 , LIEF::assembly::riscv::PseudoVAADD_VV_M1 = 525 , LIEF::assembly::riscv::PseudoVAADD_VV_M1_MASK = 526 , LIEF::assembly::riscv::PseudoVAADD_VV_M2 = 527 ,
  LIEF::assembly::riscv::PseudoVAADD_VV_M2_MASK = 528 , LIEF::assembly::riscv::PseudoVAADD_VV_M4 = 529 , LIEF::assembly::riscv::PseudoVAADD_VV_M4_MASK = 530 , LIEF::assembly::riscv::PseudoVAADD_VV_M8 = 531 ,
  LIEF::assembly::riscv::PseudoVAADD_VV_M8_MASK = 532 , LIEF::assembly::riscv::PseudoVAADD_VV_MF2 = 533 , LIEF::assembly::riscv::PseudoVAADD_VV_MF2_MASK = 534 , LIEF::assembly::riscv::PseudoVAADD_VV_MF4 = 535 ,
  LIEF::assembly::riscv::PseudoVAADD_VV_MF4_MASK = 536 , LIEF::assembly::riscv::PseudoVAADD_VV_MF8 = 537 , LIEF::assembly::riscv::PseudoVAADD_VV_MF8_MASK = 538 , LIEF::assembly::riscv::PseudoVAADD_VX_M1 = 539 ,
  LIEF::assembly::riscv::PseudoVAADD_VX_M1_MASK = 540 , LIEF::assembly::riscv::PseudoVAADD_VX_M2 = 541 , LIEF::assembly::riscv::PseudoVAADD_VX_M2_MASK = 542 , LIEF::assembly::riscv::PseudoVAADD_VX_M4 = 543 ,
  LIEF::assembly::riscv::PseudoVAADD_VX_M4_MASK = 544 , LIEF::assembly::riscv::PseudoVAADD_VX_M8 = 545 , LIEF::assembly::riscv::PseudoVAADD_VX_M8_MASK = 546 , LIEF::assembly::riscv::PseudoVAADD_VX_MF2 = 547 ,
  LIEF::assembly::riscv::PseudoVAADD_VX_MF2_MASK = 548 , LIEF::assembly::riscv::PseudoVAADD_VX_MF4 = 549 , LIEF::assembly::riscv::PseudoVAADD_VX_MF4_MASK = 550 , LIEF::assembly::riscv::PseudoVAADD_VX_MF8 = 551 ,
  LIEF::assembly::riscv::PseudoVAADD_VX_MF8_MASK = 552 , LIEF::assembly::riscv::PseudoVADC_VIM_M1 = 553 , LIEF::assembly::riscv::PseudoVADC_VIM_M2 = 554 , LIEF::assembly::riscv::PseudoVADC_VIM_M4 = 555 ,
  LIEF::assembly::riscv::PseudoVADC_VIM_M8 = 556 , LIEF::assembly::riscv::PseudoVADC_VIM_MF2 = 557 , LIEF::assembly::riscv::PseudoVADC_VIM_MF4 = 558 , LIEF::assembly::riscv::PseudoVADC_VIM_MF8 = 559 ,
  LIEF::assembly::riscv::PseudoVADC_VVM_M1 = 560 , LIEF::assembly::riscv::PseudoVADC_VVM_M2 = 561 , LIEF::assembly::riscv::PseudoVADC_VVM_M4 = 562 , LIEF::assembly::riscv::PseudoVADC_VVM_M8 = 563 ,
  LIEF::assembly::riscv::PseudoVADC_VVM_MF2 = 564 , LIEF::assembly::riscv::PseudoVADC_VVM_MF4 = 565 , LIEF::assembly::riscv::PseudoVADC_VVM_MF8 = 566 , LIEF::assembly::riscv::PseudoVADC_VXM_M1 = 567 ,
  LIEF::assembly::riscv::PseudoVADC_VXM_M2 = 568 , LIEF::assembly::riscv::PseudoVADC_VXM_M4 = 569 , LIEF::assembly::riscv::PseudoVADC_VXM_M8 = 570 , LIEF::assembly::riscv::PseudoVADC_VXM_MF2 = 571 ,
  LIEF::assembly::riscv::PseudoVADC_VXM_MF4 = 572 , LIEF::assembly::riscv::PseudoVADC_VXM_MF8 = 573 , LIEF::assembly::riscv::PseudoVADD_VI_M1 = 574 , LIEF::assembly::riscv::PseudoVADD_VI_M1_MASK = 575 ,
  LIEF::assembly::riscv::PseudoVADD_VI_M2 = 576 , LIEF::assembly::riscv::PseudoVADD_VI_M2_MASK = 577 , LIEF::assembly::riscv::PseudoVADD_VI_M4 = 578 , LIEF::assembly::riscv::PseudoVADD_VI_M4_MASK = 579 ,
  LIEF::assembly::riscv::PseudoVADD_VI_M8 = 580 , LIEF::assembly::riscv::PseudoVADD_VI_M8_MASK = 581 , LIEF::assembly::riscv::PseudoVADD_VI_MF2 = 582 , LIEF::assembly::riscv::PseudoVADD_VI_MF2_MASK = 583 ,
  LIEF::assembly::riscv::PseudoVADD_VI_MF4 = 584 , LIEF::assembly::riscv::PseudoVADD_VI_MF4_MASK = 585 , LIEF::assembly::riscv::PseudoVADD_VI_MF8 = 586 , LIEF::assembly::riscv::PseudoVADD_VI_MF8_MASK = 587 ,
  LIEF::assembly::riscv::PseudoVADD_VV_M1 = 588 , LIEF::assembly::riscv::PseudoVADD_VV_M1_MASK = 589 , LIEF::assembly::riscv::PseudoVADD_VV_M2 = 590 , LIEF::assembly::riscv::PseudoVADD_VV_M2_MASK = 591 ,
  LIEF::assembly::riscv::PseudoVADD_VV_M4 = 592 , LIEF::assembly::riscv::PseudoVADD_VV_M4_MASK = 593 , LIEF::assembly::riscv::PseudoVADD_VV_M8 = 594 , LIEF::assembly::riscv::PseudoVADD_VV_M8_MASK = 595 ,
  LIEF::assembly::riscv::PseudoVADD_VV_MF2 = 596 , LIEF::assembly::riscv::PseudoVADD_VV_MF2_MASK = 597 , LIEF::assembly::riscv::PseudoVADD_VV_MF4 = 598 , LIEF::assembly::riscv::PseudoVADD_VV_MF4_MASK = 599 ,
  LIEF::assembly::riscv::PseudoVADD_VV_MF8 = 600 , LIEF::assembly::riscv::PseudoVADD_VV_MF8_MASK = 601 , LIEF::assembly::riscv::PseudoVADD_VX_M1 = 602 , LIEF::assembly::riscv::PseudoVADD_VX_M1_MASK = 603 ,
  LIEF::assembly::riscv::PseudoVADD_VX_M2 = 604 , LIEF::assembly::riscv::PseudoVADD_VX_M2_MASK = 605 , LIEF::assembly::riscv::PseudoVADD_VX_M4 = 606 , LIEF::assembly::riscv::PseudoVADD_VX_M4_MASK = 607 ,
  LIEF::assembly::riscv::PseudoVADD_VX_M8 = 608 , LIEF::assembly::riscv::PseudoVADD_VX_M8_MASK = 609 , LIEF::assembly::riscv::PseudoVADD_VX_MF2 = 610 , LIEF::assembly::riscv::PseudoVADD_VX_MF2_MASK = 611 ,
  LIEF::assembly::riscv::PseudoVADD_VX_MF4 = 612 , LIEF::assembly::riscv::PseudoVADD_VX_MF4_MASK = 613 , LIEF::assembly::riscv::PseudoVADD_VX_MF8 = 614 , LIEF::assembly::riscv::PseudoVADD_VX_MF8_MASK = 615 ,
  LIEF::assembly::riscv::PseudoVAESDF_VS_M1_M1 = 616 , LIEF::assembly::riscv::PseudoVAESDF_VS_M1_MF2 = 617 , LIEF::assembly::riscv::PseudoVAESDF_VS_M1_MF4 = 618 , LIEF::assembly::riscv::PseudoVAESDF_VS_M1_MF8 = 619 ,
  LIEF::assembly::riscv::PseudoVAESDF_VS_M2_M1 = 620 , LIEF::assembly::riscv::PseudoVAESDF_VS_M2_M2 = 621 , LIEF::assembly::riscv::PseudoVAESDF_VS_M2_MF2 = 622 , LIEF::assembly::riscv::PseudoVAESDF_VS_M2_MF4 = 623 ,
  LIEF::assembly::riscv::PseudoVAESDF_VS_M2_MF8 = 624 , LIEF::assembly::riscv::PseudoVAESDF_VS_M4_M1 = 625 , LIEF::assembly::riscv::PseudoVAESDF_VS_M4_M2 = 626 , LIEF::assembly::riscv::PseudoVAESDF_VS_M4_M4 = 627 ,
  LIEF::assembly::riscv::PseudoVAESDF_VS_M4_MF2 = 628 , LIEF::assembly::riscv::PseudoVAESDF_VS_M4_MF4 = 629 , LIEF::assembly::riscv::PseudoVAESDF_VS_M4_MF8 = 630 , LIEF::assembly::riscv::PseudoVAESDF_VS_M8_M1 = 631 ,
  LIEF::assembly::riscv::PseudoVAESDF_VS_M8_M2 = 632 , LIEF::assembly::riscv::PseudoVAESDF_VS_M8_M4 = 633 , LIEF::assembly::riscv::PseudoVAESDF_VS_M8_MF2 = 634 , LIEF::assembly::riscv::PseudoVAESDF_VS_M8_MF4 = 635 ,
  LIEF::assembly::riscv::PseudoVAESDF_VS_M8_MF8 = 636 , LIEF::assembly::riscv::PseudoVAESDF_VS_MF2_MF2 = 637 , LIEF::assembly::riscv::PseudoVAESDF_VS_MF2_MF4 = 638 , LIEF::assembly::riscv::PseudoVAESDF_VS_MF2_MF8 = 639 ,
  LIEF::assembly::riscv::PseudoVAESDF_VV_M1 = 640 , LIEF::assembly::riscv::PseudoVAESDF_VV_M2 = 641 , LIEF::assembly::riscv::PseudoVAESDF_VV_M4 = 642 , LIEF::assembly::riscv::PseudoVAESDF_VV_M8 = 643 ,
  LIEF::assembly::riscv::PseudoVAESDF_VV_MF2 = 644 , LIEF::assembly::riscv::PseudoVAESDM_VS_M1_M1 = 645 , LIEF::assembly::riscv::PseudoVAESDM_VS_M1_MF2 = 646 , LIEF::assembly::riscv::PseudoVAESDM_VS_M1_MF4 = 647 ,
  LIEF::assembly::riscv::PseudoVAESDM_VS_M1_MF8 = 648 , LIEF::assembly::riscv::PseudoVAESDM_VS_M2_M1 = 649 , LIEF::assembly::riscv::PseudoVAESDM_VS_M2_M2 = 650 , LIEF::assembly::riscv::PseudoVAESDM_VS_M2_MF2 = 651 ,
  LIEF::assembly::riscv::PseudoVAESDM_VS_M2_MF4 = 652 , LIEF::assembly::riscv::PseudoVAESDM_VS_M2_MF8 = 653 , LIEF::assembly::riscv::PseudoVAESDM_VS_M4_M1 = 654 , LIEF::assembly::riscv::PseudoVAESDM_VS_M4_M2 = 655 ,
  LIEF::assembly::riscv::PseudoVAESDM_VS_M4_M4 = 656 , LIEF::assembly::riscv::PseudoVAESDM_VS_M4_MF2 = 657 , LIEF::assembly::riscv::PseudoVAESDM_VS_M4_MF4 = 658 , LIEF::assembly::riscv::PseudoVAESDM_VS_M4_MF8 = 659 ,
  LIEF::assembly::riscv::PseudoVAESDM_VS_M8_M1 = 660 , LIEF::assembly::riscv::PseudoVAESDM_VS_M8_M2 = 661 , LIEF::assembly::riscv::PseudoVAESDM_VS_M8_M4 = 662 , LIEF::assembly::riscv::PseudoVAESDM_VS_M8_MF2 = 663 ,
  LIEF::assembly::riscv::PseudoVAESDM_VS_M8_MF4 = 664 , LIEF::assembly::riscv::PseudoVAESDM_VS_M8_MF8 = 665 , LIEF::assembly::riscv::PseudoVAESDM_VS_MF2_MF2 = 666 , LIEF::assembly::riscv::PseudoVAESDM_VS_MF2_MF4 = 667 ,
  LIEF::assembly::riscv::PseudoVAESDM_VS_MF2_MF8 = 668 , LIEF::assembly::riscv::PseudoVAESDM_VV_M1 = 669 , LIEF::assembly::riscv::PseudoVAESDM_VV_M2 = 670 , LIEF::assembly::riscv::PseudoVAESDM_VV_M4 = 671 ,
  LIEF::assembly::riscv::PseudoVAESDM_VV_M8 = 672 , LIEF::assembly::riscv::PseudoVAESDM_VV_MF2 = 673 , LIEF::assembly::riscv::PseudoVAESEF_VS_M1_M1 = 674 , LIEF::assembly::riscv::PseudoVAESEF_VS_M1_MF2 = 675 ,
  LIEF::assembly::riscv::PseudoVAESEF_VS_M1_MF4 = 676 , LIEF::assembly::riscv::PseudoVAESEF_VS_M1_MF8 = 677 , LIEF::assembly::riscv::PseudoVAESEF_VS_M2_M1 = 678 , LIEF::assembly::riscv::PseudoVAESEF_VS_M2_M2 = 679 ,
  LIEF::assembly::riscv::PseudoVAESEF_VS_M2_MF2 = 680 , LIEF::assembly::riscv::PseudoVAESEF_VS_M2_MF4 = 681 , LIEF::assembly::riscv::PseudoVAESEF_VS_M2_MF8 = 682 , LIEF::assembly::riscv::PseudoVAESEF_VS_M4_M1 = 683 ,
  LIEF::assembly::riscv::PseudoVAESEF_VS_M4_M2 = 684 , LIEF::assembly::riscv::PseudoVAESEF_VS_M4_M4 = 685 , LIEF::assembly::riscv::PseudoVAESEF_VS_M4_MF2 = 686 , LIEF::assembly::riscv::PseudoVAESEF_VS_M4_MF4 = 687 ,
  LIEF::assembly::riscv::PseudoVAESEF_VS_M4_MF8 = 688 , LIEF::assembly::riscv::PseudoVAESEF_VS_M8_M1 = 689 , LIEF::assembly::riscv::PseudoVAESEF_VS_M8_M2 = 690 , LIEF::assembly::riscv::PseudoVAESEF_VS_M8_M4 = 691 ,
  LIEF::assembly::riscv::PseudoVAESEF_VS_M8_MF2 = 692 , LIEF::assembly::riscv::PseudoVAESEF_VS_M8_MF4 = 693 , LIEF::assembly::riscv::PseudoVAESEF_VS_M8_MF8 = 694 , LIEF::assembly::riscv::PseudoVAESEF_VS_MF2_MF2 = 695 ,
  LIEF::assembly::riscv::PseudoVAESEF_VS_MF2_MF4 = 696 , LIEF::assembly::riscv::PseudoVAESEF_VS_MF2_MF8 = 697 , LIEF::assembly::riscv::PseudoVAESEF_VV_M1 = 698 , LIEF::assembly::riscv::PseudoVAESEF_VV_M2 = 699 ,
  LIEF::assembly::riscv::PseudoVAESEF_VV_M4 = 700 , LIEF::assembly::riscv::PseudoVAESEF_VV_M8 = 701 , LIEF::assembly::riscv::PseudoVAESEF_VV_MF2 = 702 , LIEF::assembly::riscv::PseudoVAESEM_VS_M1_M1 = 703 ,
  LIEF::assembly::riscv::PseudoVAESEM_VS_M1_MF2 = 704 , LIEF::assembly::riscv::PseudoVAESEM_VS_M1_MF4 = 705 , LIEF::assembly::riscv::PseudoVAESEM_VS_M1_MF8 = 706 , LIEF::assembly::riscv::PseudoVAESEM_VS_M2_M1 = 707 ,
  LIEF::assembly::riscv::PseudoVAESEM_VS_M2_M2 = 708 , LIEF::assembly::riscv::PseudoVAESEM_VS_M2_MF2 = 709 , LIEF::assembly::riscv::PseudoVAESEM_VS_M2_MF4 = 710 , LIEF::assembly::riscv::PseudoVAESEM_VS_M2_MF8 = 711 ,
  LIEF::assembly::riscv::PseudoVAESEM_VS_M4_M1 = 712 , LIEF::assembly::riscv::PseudoVAESEM_VS_M4_M2 = 713 , LIEF::assembly::riscv::PseudoVAESEM_VS_M4_M4 = 714 , LIEF::assembly::riscv::PseudoVAESEM_VS_M4_MF2 = 715 ,
  LIEF::assembly::riscv::PseudoVAESEM_VS_M4_MF4 = 716 , LIEF::assembly::riscv::PseudoVAESEM_VS_M4_MF8 = 717 , LIEF::assembly::riscv::PseudoVAESEM_VS_M8_M1 = 718 , LIEF::assembly::riscv::PseudoVAESEM_VS_M8_M2 = 719 ,
  LIEF::assembly::riscv::PseudoVAESEM_VS_M8_M4 = 720 , LIEF::assembly::riscv::PseudoVAESEM_VS_M8_MF2 = 721 , LIEF::assembly::riscv::PseudoVAESEM_VS_M8_MF4 = 722 , LIEF::assembly::riscv::PseudoVAESEM_VS_M8_MF8 = 723 ,
  LIEF::assembly::riscv::PseudoVAESEM_VS_MF2_MF2 = 724 , LIEF::assembly::riscv::PseudoVAESEM_VS_MF2_MF4 = 725 , LIEF::assembly::riscv::PseudoVAESEM_VS_MF2_MF8 = 726 , LIEF::assembly::riscv::PseudoVAESEM_VV_M1 = 727 ,
  LIEF::assembly::riscv::PseudoVAESEM_VV_M2 = 728 , LIEF::assembly::riscv::PseudoVAESEM_VV_M4 = 729 , LIEF::assembly::riscv::PseudoVAESEM_VV_M8 = 730 , LIEF::assembly::riscv::PseudoVAESEM_VV_MF2 = 731 ,
  LIEF::assembly::riscv::PseudoVAESKF1_VI_M1 = 732 , LIEF::assembly::riscv::PseudoVAESKF1_VI_M2 = 733 , LIEF::assembly::riscv::PseudoVAESKF1_VI_M4 = 734 , LIEF::assembly::riscv::PseudoVAESKF1_VI_M8 = 735 ,
  LIEF::assembly::riscv::PseudoVAESKF1_VI_MF2 = 736 , LIEF::assembly::riscv::PseudoVAESKF2_VI_M1 = 737 , LIEF::assembly::riscv::PseudoVAESKF2_VI_M2 = 738 , LIEF::assembly::riscv::PseudoVAESKF2_VI_M4 = 739 ,
  LIEF::assembly::riscv::PseudoVAESKF2_VI_M8 = 740 , LIEF::assembly::riscv::PseudoVAESKF2_VI_MF2 = 741 , LIEF::assembly::riscv::PseudoVAESZ_VS_M1_M1 = 742 , LIEF::assembly::riscv::PseudoVAESZ_VS_M1_MF2 = 743 ,
  LIEF::assembly::riscv::PseudoVAESZ_VS_M1_MF4 = 744 , LIEF::assembly::riscv::PseudoVAESZ_VS_M1_MF8 = 745 , LIEF::assembly::riscv::PseudoVAESZ_VS_M2_M1 = 746 , LIEF::assembly::riscv::PseudoVAESZ_VS_M2_M2 = 747 ,
  LIEF::assembly::riscv::PseudoVAESZ_VS_M2_MF2 = 748 , LIEF::assembly::riscv::PseudoVAESZ_VS_M2_MF4 = 749 , LIEF::assembly::riscv::PseudoVAESZ_VS_M2_MF8 = 750 , LIEF::assembly::riscv::PseudoVAESZ_VS_M4_M1 = 751 ,
  LIEF::assembly::riscv::PseudoVAESZ_VS_M4_M2 = 752 , LIEF::assembly::riscv::PseudoVAESZ_VS_M4_M4 = 753 , LIEF::assembly::riscv::PseudoVAESZ_VS_M4_MF2 = 754 , LIEF::assembly::riscv::PseudoVAESZ_VS_M4_MF4 = 755 ,
  LIEF::assembly::riscv::PseudoVAESZ_VS_M4_MF8 = 756 , LIEF::assembly::riscv::PseudoVAESZ_VS_M8_M1 = 757 , LIEF::assembly::riscv::PseudoVAESZ_VS_M8_M2 = 758 , LIEF::assembly::riscv::PseudoVAESZ_VS_M8_M4 = 759 ,
  LIEF::assembly::riscv::PseudoVAESZ_VS_M8_MF2 = 760 , LIEF::assembly::riscv::PseudoVAESZ_VS_M8_MF4 = 761 , LIEF::assembly::riscv::PseudoVAESZ_VS_M8_MF8 = 762 , LIEF::assembly::riscv::PseudoVAESZ_VS_MF2_MF2 = 763 ,
  LIEF::assembly::riscv::PseudoVAESZ_VS_MF2_MF4 = 764 , LIEF::assembly::riscv::PseudoVAESZ_VS_MF2_MF8 = 765 , LIEF::assembly::riscv::PseudoVANDN_VV_M1 = 766 , LIEF::assembly::riscv::PseudoVANDN_VV_M1_MASK = 767 ,
  LIEF::assembly::riscv::PseudoVANDN_VV_M2 = 768 , LIEF::assembly::riscv::PseudoVANDN_VV_M2_MASK = 769 , LIEF::assembly::riscv::PseudoVANDN_VV_M4 = 770 , LIEF::assembly::riscv::PseudoVANDN_VV_M4_MASK = 771 ,
  LIEF::assembly::riscv::PseudoVANDN_VV_M8 = 772 , LIEF::assembly::riscv::PseudoVANDN_VV_M8_MASK = 773 , LIEF::assembly::riscv::PseudoVANDN_VV_MF2 = 774 , LIEF::assembly::riscv::PseudoVANDN_VV_MF2_MASK = 775 ,
  LIEF::assembly::riscv::PseudoVANDN_VV_MF4 = 776 , LIEF::assembly::riscv::PseudoVANDN_VV_MF4_MASK = 777 , LIEF::assembly::riscv::PseudoVANDN_VV_MF8 = 778 , LIEF::assembly::riscv::PseudoVANDN_VV_MF8_MASK = 779 ,
  LIEF::assembly::riscv::PseudoVANDN_VX_M1 = 780 , LIEF::assembly::riscv::PseudoVANDN_VX_M1_MASK = 781 , LIEF::assembly::riscv::PseudoVANDN_VX_M2 = 782 , LIEF::assembly::riscv::PseudoVANDN_VX_M2_MASK = 783 ,
  LIEF::assembly::riscv::PseudoVANDN_VX_M4 = 784 , LIEF::assembly::riscv::PseudoVANDN_VX_M4_MASK = 785 , LIEF::assembly::riscv::PseudoVANDN_VX_M8 = 786 , LIEF::assembly::riscv::PseudoVANDN_VX_M8_MASK = 787 ,
  LIEF::assembly::riscv::PseudoVANDN_VX_MF2 = 788 , LIEF::assembly::riscv::PseudoVANDN_VX_MF2_MASK = 789 , LIEF::assembly::riscv::PseudoVANDN_VX_MF4 = 790 , LIEF::assembly::riscv::PseudoVANDN_VX_MF4_MASK = 791 ,
  LIEF::assembly::riscv::PseudoVANDN_VX_MF8 = 792 , LIEF::assembly::riscv::PseudoVANDN_VX_MF8_MASK = 793 , LIEF::assembly::riscv::PseudoVAND_VI_M1 = 794 , LIEF::assembly::riscv::PseudoVAND_VI_M1_MASK = 795 ,
  LIEF::assembly::riscv::PseudoVAND_VI_M2 = 796 , LIEF::assembly::riscv::PseudoVAND_VI_M2_MASK = 797 , LIEF::assembly::riscv::PseudoVAND_VI_M4 = 798 , LIEF::assembly::riscv::PseudoVAND_VI_M4_MASK = 799 ,
  LIEF::assembly::riscv::PseudoVAND_VI_M8 = 800 , LIEF::assembly::riscv::PseudoVAND_VI_M8_MASK = 801 , LIEF::assembly::riscv::PseudoVAND_VI_MF2 = 802 , LIEF::assembly::riscv::PseudoVAND_VI_MF2_MASK = 803 ,
  LIEF::assembly::riscv::PseudoVAND_VI_MF4 = 804 , LIEF::assembly::riscv::PseudoVAND_VI_MF4_MASK = 805 , LIEF::assembly::riscv::PseudoVAND_VI_MF8 = 806 , LIEF::assembly::riscv::PseudoVAND_VI_MF8_MASK = 807 ,
  LIEF::assembly::riscv::PseudoVAND_VV_M1 = 808 , LIEF::assembly::riscv::PseudoVAND_VV_M1_MASK = 809 , LIEF::assembly::riscv::PseudoVAND_VV_M2 = 810 , LIEF::assembly::riscv::PseudoVAND_VV_M2_MASK = 811 ,
  LIEF::assembly::riscv::PseudoVAND_VV_M4 = 812 , LIEF::assembly::riscv::PseudoVAND_VV_M4_MASK = 813 , LIEF::assembly::riscv::PseudoVAND_VV_M8 = 814 , LIEF::assembly::riscv::PseudoVAND_VV_M8_MASK = 815 ,
  LIEF::assembly::riscv::PseudoVAND_VV_MF2 = 816 , LIEF::assembly::riscv::PseudoVAND_VV_MF2_MASK = 817 , LIEF::assembly::riscv::PseudoVAND_VV_MF4 = 818 , LIEF::assembly::riscv::PseudoVAND_VV_MF4_MASK = 819 ,
  LIEF::assembly::riscv::PseudoVAND_VV_MF8 = 820 , LIEF::assembly::riscv::PseudoVAND_VV_MF8_MASK = 821 , LIEF::assembly::riscv::PseudoVAND_VX_M1 = 822 , LIEF::assembly::riscv::PseudoVAND_VX_M1_MASK = 823 ,
  LIEF::assembly::riscv::PseudoVAND_VX_M2 = 824 , LIEF::assembly::riscv::PseudoVAND_VX_M2_MASK = 825 , LIEF::assembly::riscv::PseudoVAND_VX_M4 = 826 , LIEF::assembly::riscv::PseudoVAND_VX_M4_MASK = 827 ,
  LIEF::assembly::riscv::PseudoVAND_VX_M8 = 828 , LIEF::assembly::riscv::PseudoVAND_VX_M8_MASK = 829 , LIEF::assembly::riscv::PseudoVAND_VX_MF2 = 830 , LIEF::assembly::riscv::PseudoVAND_VX_MF2_MASK = 831 ,
  LIEF::assembly::riscv::PseudoVAND_VX_MF4 = 832 , LIEF::assembly::riscv::PseudoVAND_VX_MF4_MASK = 833 , LIEF::assembly::riscv::PseudoVAND_VX_MF8 = 834 , LIEF::assembly::riscv::PseudoVAND_VX_MF8_MASK = 835 ,
  LIEF::assembly::riscv::PseudoVASUBU_VV_M1 = 836 , LIEF::assembly::riscv::PseudoVASUBU_VV_M1_MASK = 837 , LIEF::assembly::riscv::PseudoVASUBU_VV_M2 = 838 , LIEF::assembly::riscv::PseudoVASUBU_VV_M2_MASK = 839 ,
  LIEF::assembly::riscv::PseudoVASUBU_VV_M4 = 840 , LIEF::assembly::riscv::PseudoVASUBU_VV_M4_MASK = 841 , LIEF::assembly::riscv::PseudoVASUBU_VV_M8 = 842 , LIEF::assembly::riscv::PseudoVASUBU_VV_M8_MASK = 843 ,
  LIEF::assembly::riscv::PseudoVASUBU_VV_MF2 = 844 , LIEF::assembly::riscv::PseudoVASUBU_VV_MF2_MASK = 845 , LIEF::assembly::riscv::PseudoVASUBU_VV_MF4 = 846 , LIEF::assembly::riscv::PseudoVASUBU_VV_MF4_MASK = 847 ,
  LIEF::assembly::riscv::PseudoVASUBU_VV_MF8 = 848 , LIEF::assembly::riscv::PseudoVASUBU_VV_MF8_MASK = 849 , LIEF::assembly::riscv::PseudoVASUBU_VX_M1 = 850 , LIEF::assembly::riscv::PseudoVASUBU_VX_M1_MASK = 851 ,
  LIEF::assembly::riscv::PseudoVASUBU_VX_M2 = 852 , LIEF::assembly::riscv::PseudoVASUBU_VX_M2_MASK = 853 , LIEF::assembly::riscv::PseudoVASUBU_VX_M4 = 854 , LIEF::assembly::riscv::PseudoVASUBU_VX_M4_MASK = 855 ,
  LIEF::assembly::riscv::PseudoVASUBU_VX_M8 = 856 , LIEF::assembly::riscv::PseudoVASUBU_VX_M8_MASK = 857 , LIEF::assembly::riscv::PseudoVASUBU_VX_MF2 = 858 , LIEF::assembly::riscv::PseudoVASUBU_VX_MF2_MASK = 859 ,
  LIEF::assembly::riscv::PseudoVASUBU_VX_MF4 = 860 , LIEF::assembly::riscv::PseudoVASUBU_VX_MF4_MASK = 861 , LIEF::assembly::riscv::PseudoVASUBU_VX_MF8 = 862 , LIEF::assembly::riscv::PseudoVASUBU_VX_MF8_MASK = 863 ,
  LIEF::assembly::riscv::PseudoVASUB_VV_M1 = 864 , LIEF::assembly::riscv::PseudoVASUB_VV_M1_MASK = 865 , LIEF::assembly::riscv::PseudoVASUB_VV_M2 = 866 , LIEF::assembly::riscv::PseudoVASUB_VV_M2_MASK = 867 ,
  LIEF::assembly::riscv::PseudoVASUB_VV_M4 = 868 , LIEF::assembly::riscv::PseudoVASUB_VV_M4_MASK = 869 , LIEF::assembly::riscv::PseudoVASUB_VV_M8 = 870 , LIEF::assembly::riscv::PseudoVASUB_VV_M8_MASK = 871 ,
  LIEF::assembly::riscv::PseudoVASUB_VV_MF2 = 872 , LIEF::assembly::riscv::PseudoVASUB_VV_MF2_MASK = 873 , LIEF::assembly::riscv::PseudoVASUB_VV_MF4 = 874 , LIEF::assembly::riscv::PseudoVASUB_VV_MF4_MASK = 875 ,
  LIEF::assembly::riscv::PseudoVASUB_VV_MF8 = 876 , LIEF::assembly::riscv::PseudoVASUB_VV_MF8_MASK = 877 , LIEF::assembly::riscv::PseudoVASUB_VX_M1 = 878 , LIEF::assembly::riscv::PseudoVASUB_VX_M1_MASK = 879 ,
  LIEF::assembly::riscv::PseudoVASUB_VX_M2 = 880 , LIEF::assembly::riscv::PseudoVASUB_VX_M2_MASK = 881 , LIEF::assembly::riscv::PseudoVASUB_VX_M4 = 882 , LIEF::assembly::riscv::PseudoVASUB_VX_M4_MASK = 883 ,
  LIEF::assembly::riscv::PseudoVASUB_VX_M8 = 884 , LIEF::assembly::riscv::PseudoVASUB_VX_M8_MASK = 885 , LIEF::assembly::riscv::PseudoVASUB_VX_MF2 = 886 , LIEF::assembly::riscv::PseudoVASUB_VX_MF2_MASK = 887 ,
  LIEF::assembly::riscv::PseudoVASUB_VX_MF4 = 888 , LIEF::assembly::riscv::PseudoVASUB_VX_MF4_MASK = 889 , LIEF::assembly::riscv::PseudoVASUB_VX_MF8 = 890 , LIEF::assembly::riscv::PseudoVASUB_VX_MF8_MASK = 891 ,
  LIEF::assembly::riscv::PseudoVBREV8_V_M1 = 892 , LIEF::assembly::riscv::PseudoVBREV8_V_M1_MASK = 893 , LIEF::assembly::riscv::PseudoVBREV8_V_M2 = 894 , LIEF::assembly::riscv::PseudoVBREV8_V_M2_MASK = 895 ,
  LIEF::assembly::riscv::PseudoVBREV8_V_M4 = 896 , LIEF::assembly::riscv::PseudoVBREV8_V_M4_MASK = 897 , LIEF::assembly::riscv::PseudoVBREV8_V_M8 = 898 , LIEF::assembly::riscv::PseudoVBREV8_V_M8_MASK = 899 ,
  LIEF::assembly::riscv::PseudoVBREV8_V_MF2 = 900 , LIEF::assembly::riscv::PseudoVBREV8_V_MF2_MASK = 901 , LIEF::assembly::riscv::PseudoVBREV8_V_MF4 = 902 , LIEF::assembly::riscv::PseudoVBREV8_V_MF4_MASK = 903 ,
  LIEF::assembly::riscv::PseudoVBREV8_V_MF8 = 904 , LIEF::assembly::riscv::PseudoVBREV8_V_MF8_MASK = 905 , LIEF::assembly::riscv::PseudoVBREV_V_M1 = 906 , LIEF::assembly::riscv::PseudoVBREV_V_M1_MASK = 907 ,
  LIEF::assembly::riscv::PseudoVBREV_V_M2 = 908 , LIEF::assembly::riscv::PseudoVBREV_V_M2_MASK = 909 , LIEF::assembly::riscv::PseudoVBREV_V_M4 = 910 , LIEF::assembly::riscv::PseudoVBREV_V_M4_MASK = 911 ,
  LIEF::assembly::riscv::PseudoVBREV_V_M8 = 912 , LIEF::assembly::riscv::PseudoVBREV_V_M8_MASK = 913 , LIEF::assembly::riscv::PseudoVBREV_V_MF2 = 914 , LIEF::assembly::riscv::PseudoVBREV_V_MF2_MASK = 915 ,
  LIEF::assembly::riscv::PseudoVBREV_V_MF4 = 916 , LIEF::assembly::riscv::PseudoVBREV_V_MF4_MASK = 917 , LIEF::assembly::riscv::PseudoVBREV_V_MF8 = 918 , LIEF::assembly::riscv::PseudoVBREV_V_MF8_MASK = 919 ,
  LIEF::assembly::riscv::PseudoVCLMULH_VV_M1 = 920 , LIEF::assembly::riscv::PseudoVCLMULH_VV_M1_MASK = 921 , LIEF::assembly::riscv::PseudoVCLMULH_VV_M2 = 922 , LIEF::assembly::riscv::PseudoVCLMULH_VV_M2_MASK = 923 ,
  LIEF::assembly::riscv::PseudoVCLMULH_VV_M4 = 924 , LIEF::assembly::riscv::PseudoVCLMULH_VV_M4_MASK = 925 , LIEF::assembly::riscv::PseudoVCLMULH_VV_M8 = 926 , LIEF::assembly::riscv::PseudoVCLMULH_VV_M8_MASK = 927 ,
  LIEF::assembly::riscv::PseudoVCLMULH_VV_MF2 = 928 , LIEF::assembly::riscv::PseudoVCLMULH_VV_MF2_MASK = 929 , LIEF::assembly::riscv::PseudoVCLMULH_VV_MF4 = 930 , LIEF::assembly::riscv::PseudoVCLMULH_VV_MF4_MASK = 931 ,
  LIEF::assembly::riscv::PseudoVCLMULH_VV_MF8 = 932 , LIEF::assembly::riscv::PseudoVCLMULH_VV_MF8_MASK = 933 , LIEF::assembly::riscv::PseudoVCLMULH_VX_M1 = 934 , LIEF::assembly::riscv::PseudoVCLMULH_VX_M1_MASK = 935 ,
  LIEF::assembly::riscv::PseudoVCLMULH_VX_M2 = 936 , LIEF::assembly::riscv::PseudoVCLMULH_VX_M2_MASK = 937 , LIEF::assembly::riscv::PseudoVCLMULH_VX_M4 = 938 , LIEF::assembly::riscv::PseudoVCLMULH_VX_M4_MASK = 939 ,
  LIEF::assembly::riscv::PseudoVCLMULH_VX_M8 = 940 , LIEF::assembly::riscv::PseudoVCLMULH_VX_M8_MASK = 941 , LIEF::assembly::riscv::PseudoVCLMULH_VX_MF2 = 942 , LIEF::assembly::riscv::PseudoVCLMULH_VX_MF2_MASK = 943 ,
  LIEF::assembly::riscv::PseudoVCLMULH_VX_MF4 = 944 , LIEF::assembly::riscv::PseudoVCLMULH_VX_MF4_MASK = 945 , LIEF::assembly::riscv::PseudoVCLMULH_VX_MF8 = 946 , LIEF::assembly::riscv::PseudoVCLMULH_VX_MF8_MASK = 947 ,
  LIEF::assembly::riscv::PseudoVCLMUL_VV_M1 = 948 , LIEF::assembly::riscv::PseudoVCLMUL_VV_M1_MASK = 949 , LIEF::assembly::riscv::PseudoVCLMUL_VV_M2 = 950 , LIEF::assembly::riscv::PseudoVCLMUL_VV_M2_MASK = 951 ,
  LIEF::assembly::riscv::PseudoVCLMUL_VV_M4 = 952 , LIEF::assembly::riscv::PseudoVCLMUL_VV_M4_MASK = 953 , LIEF::assembly::riscv::PseudoVCLMUL_VV_M8 = 954 , LIEF::assembly::riscv::PseudoVCLMUL_VV_M8_MASK = 955 ,
  LIEF::assembly::riscv::PseudoVCLMUL_VV_MF2 = 956 , LIEF::assembly::riscv::PseudoVCLMUL_VV_MF2_MASK = 957 , LIEF::assembly::riscv::PseudoVCLMUL_VV_MF4 = 958 , LIEF::assembly::riscv::PseudoVCLMUL_VV_MF4_MASK = 959 ,
  LIEF::assembly::riscv::PseudoVCLMUL_VV_MF8 = 960 , LIEF::assembly::riscv::PseudoVCLMUL_VV_MF8_MASK = 961 , LIEF::assembly::riscv::PseudoVCLMUL_VX_M1 = 962 , LIEF::assembly::riscv::PseudoVCLMUL_VX_M1_MASK = 963 ,
  LIEF::assembly::riscv::PseudoVCLMUL_VX_M2 = 964 , LIEF::assembly::riscv::PseudoVCLMUL_VX_M2_MASK = 965 , LIEF::assembly::riscv::PseudoVCLMUL_VX_M4 = 966 , LIEF::assembly::riscv::PseudoVCLMUL_VX_M4_MASK = 967 ,
  LIEF::assembly::riscv::PseudoVCLMUL_VX_M8 = 968 , LIEF::assembly::riscv::PseudoVCLMUL_VX_M8_MASK = 969 , LIEF::assembly::riscv::PseudoVCLMUL_VX_MF2 = 970 , LIEF::assembly::riscv::PseudoVCLMUL_VX_MF2_MASK = 971 ,
  LIEF::assembly::riscv::PseudoVCLMUL_VX_MF4 = 972 , LIEF::assembly::riscv::PseudoVCLMUL_VX_MF4_MASK = 973 , LIEF::assembly::riscv::PseudoVCLMUL_VX_MF8 = 974 , LIEF::assembly::riscv::PseudoVCLMUL_VX_MF8_MASK = 975 ,
  LIEF::assembly::riscv::PseudoVCLZ_V_M1 = 976 , LIEF::assembly::riscv::PseudoVCLZ_V_M1_MASK = 977 , LIEF::assembly::riscv::PseudoVCLZ_V_M2 = 978 , LIEF::assembly::riscv::PseudoVCLZ_V_M2_MASK = 979 ,
  LIEF::assembly::riscv::PseudoVCLZ_V_M4 = 980 , LIEF::assembly::riscv::PseudoVCLZ_V_M4_MASK = 981 , LIEF::assembly::riscv::PseudoVCLZ_V_M8 = 982 , LIEF::assembly::riscv::PseudoVCLZ_V_M8_MASK = 983 ,
  LIEF::assembly::riscv::PseudoVCLZ_V_MF2 = 984 , LIEF::assembly::riscv::PseudoVCLZ_V_MF2_MASK = 985 , LIEF::assembly::riscv::PseudoVCLZ_V_MF4 = 986 , LIEF::assembly::riscv::PseudoVCLZ_V_MF4_MASK = 987 ,
  LIEF::assembly::riscv::PseudoVCLZ_V_MF8 = 988 , LIEF::assembly::riscv::PseudoVCLZ_V_MF8_MASK = 989 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M1_E16 = 990 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M1_E32 = 991 ,
  LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M1_E64 = 992 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M1_E8 = 993 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M2_E16 = 994 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M2_E32 = 995 ,
  LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M2_E64 = 996 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M2_E8 = 997 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M4_E16 = 998 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M4_E32 = 999 ,
  LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M4_E64 = 1000 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M4_E8 = 1001 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M8_E16 = 1002 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M8_E32 = 1003 ,
  LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M8_E64 = 1004 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_M8_E8 = 1005 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_MF2_E16 = 1006 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_MF2_E32 = 1007 ,
  LIEF::assembly::riscv::PseudoVCOMPRESS_VM_MF2_E8 = 1008 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_MF4_E16 = 1009 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_MF4_E8 = 1010 , LIEF::assembly::riscv::PseudoVCOMPRESS_VM_MF8_E8 = 1011 ,
  LIEF::assembly::riscv::PseudoVCPOP_M_B1 = 1012 , LIEF::assembly::riscv::PseudoVCPOP_M_B16 = 1013 , LIEF::assembly::riscv::PseudoVCPOP_M_B16_MASK = 1014 , LIEF::assembly::riscv::PseudoVCPOP_M_B1_MASK = 1015 ,
  LIEF::assembly::riscv::PseudoVCPOP_M_B2 = 1016 , LIEF::assembly::riscv::PseudoVCPOP_M_B2_MASK = 1017 , LIEF::assembly::riscv::PseudoVCPOP_M_B32 = 1018 , LIEF::assembly::riscv::PseudoVCPOP_M_B32_MASK = 1019 ,
  LIEF::assembly::riscv::PseudoVCPOP_M_B4 = 1020 , LIEF::assembly::riscv::PseudoVCPOP_M_B4_MASK = 1021 , LIEF::assembly::riscv::PseudoVCPOP_M_B64 = 1022 , LIEF::assembly::riscv::PseudoVCPOP_M_B64_MASK = 1023 ,
  LIEF::assembly::riscv::PseudoVCPOP_M_B8 = 1024 , LIEF::assembly::riscv::PseudoVCPOP_M_B8_MASK = 1025 , LIEF::assembly::riscv::PseudoVCPOP_V_M1 = 1026 , LIEF::assembly::riscv::PseudoVCPOP_V_M1_MASK = 1027 ,
  LIEF::assembly::riscv::PseudoVCPOP_V_M2 = 1028 , LIEF::assembly::riscv::PseudoVCPOP_V_M2_MASK = 1029 , LIEF::assembly::riscv::PseudoVCPOP_V_M4 = 1030 , LIEF::assembly::riscv::PseudoVCPOP_V_M4_MASK = 1031 ,
  LIEF::assembly::riscv::PseudoVCPOP_V_M8 = 1032 , LIEF::assembly::riscv::PseudoVCPOP_V_M8_MASK = 1033 , LIEF::assembly::riscv::PseudoVCPOP_V_MF2 = 1034 , LIEF::assembly::riscv::PseudoVCPOP_V_MF2_MASK = 1035 ,
  LIEF::assembly::riscv::PseudoVCPOP_V_MF4 = 1036 , LIEF::assembly::riscv::PseudoVCPOP_V_MF4_MASK = 1037 , LIEF::assembly::riscv::PseudoVCPOP_V_MF8 = 1038 , LIEF::assembly::riscv::PseudoVCPOP_V_MF8_MASK = 1039 ,
  LIEF::assembly::riscv::PseudoVCTZ_V_M1 = 1040 , LIEF::assembly::riscv::PseudoVCTZ_V_M1_MASK = 1041 , LIEF::assembly::riscv::PseudoVCTZ_V_M2 = 1042 , LIEF::assembly::riscv::PseudoVCTZ_V_M2_MASK = 1043 ,
  LIEF::assembly::riscv::PseudoVCTZ_V_M4 = 1044 , LIEF::assembly::riscv::PseudoVCTZ_V_M4_MASK = 1045 , LIEF::assembly::riscv::PseudoVCTZ_V_M8 = 1046 , LIEF::assembly::riscv::PseudoVCTZ_V_M8_MASK = 1047 ,
  LIEF::assembly::riscv::PseudoVCTZ_V_MF2 = 1048 , LIEF::assembly::riscv::PseudoVCTZ_V_MF2_MASK = 1049 , LIEF::assembly::riscv::PseudoVCTZ_V_MF4 = 1050 , LIEF::assembly::riscv::PseudoVCTZ_V_MF4_MASK = 1051 ,
  LIEF::assembly::riscv::PseudoVCTZ_V_MF8 = 1052 , LIEF::assembly::riscv::PseudoVCTZ_V_MF8_MASK = 1053 , LIEF::assembly::riscv::PseudoVC_FPR16VV_SE_M1 = 1054 , LIEF::assembly::riscv::PseudoVC_FPR16VV_SE_M2 = 1055 ,
  LIEF::assembly::riscv::PseudoVC_FPR16VV_SE_M4 = 1056 , LIEF::assembly::riscv::PseudoVC_FPR16VV_SE_M8 = 1057 , LIEF::assembly::riscv::PseudoVC_FPR16VV_SE_MF2 = 1058 , LIEF::assembly::riscv::PseudoVC_FPR16VV_SE_MF4 = 1059 ,
  LIEF::assembly::riscv::PseudoVC_FPR16VW_SE_M1 = 1060 , LIEF::assembly::riscv::PseudoVC_FPR16VW_SE_M2 = 1061 , LIEF::assembly::riscv::PseudoVC_FPR16VW_SE_M4 = 1062 , LIEF::assembly::riscv::PseudoVC_FPR16VW_SE_M8 = 1063 ,
  LIEF::assembly::riscv::PseudoVC_FPR16VW_SE_MF2 = 1064 , LIEF::assembly::riscv::PseudoVC_FPR16VW_SE_MF4 = 1065 , LIEF::assembly::riscv::PseudoVC_FPR16V_SE_M1 = 1066 , LIEF::assembly::riscv::PseudoVC_FPR16V_SE_M2 = 1067 ,
  LIEF::assembly::riscv::PseudoVC_FPR16V_SE_M4 = 1068 , LIEF::assembly::riscv::PseudoVC_FPR16V_SE_M8 = 1069 , LIEF::assembly::riscv::PseudoVC_FPR16V_SE_MF2 = 1070 , LIEF::assembly::riscv::PseudoVC_FPR16V_SE_MF4 = 1071 ,
  LIEF::assembly::riscv::PseudoVC_FPR32VV_SE_M1 = 1072 , LIEF::assembly::riscv::PseudoVC_FPR32VV_SE_M2 = 1073 , LIEF::assembly::riscv::PseudoVC_FPR32VV_SE_M4 = 1074 , LIEF::assembly::riscv::PseudoVC_FPR32VV_SE_M8 = 1075 ,
  LIEF::assembly::riscv::PseudoVC_FPR32VV_SE_MF2 = 1076 , LIEF::assembly::riscv::PseudoVC_FPR32VW_SE_M1 = 1077 , LIEF::assembly::riscv::PseudoVC_FPR32VW_SE_M2 = 1078 , LIEF::assembly::riscv::PseudoVC_FPR32VW_SE_M4 = 1079 ,
  LIEF::assembly::riscv::PseudoVC_FPR32VW_SE_M8 = 1080 , LIEF::assembly::riscv::PseudoVC_FPR32VW_SE_MF2 = 1081 , LIEF::assembly::riscv::PseudoVC_FPR32V_SE_M1 = 1082 , LIEF::assembly::riscv::PseudoVC_FPR32V_SE_M2 = 1083 ,
  LIEF::assembly::riscv::PseudoVC_FPR32V_SE_M4 = 1084 , LIEF::assembly::riscv::PseudoVC_FPR32V_SE_M8 = 1085 , LIEF::assembly::riscv::PseudoVC_FPR32V_SE_MF2 = 1086 , LIEF::assembly::riscv::PseudoVC_FPR64VV_SE_M1 = 1087 ,
  LIEF::assembly::riscv::PseudoVC_FPR64VV_SE_M2 = 1088 , LIEF::assembly::riscv::PseudoVC_FPR64VV_SE_M4 = 1089 , LIEF::assembly::riscv::PseudoVC_FPR64VV_SE_M8 = 1090 , LIEF::assembly::riscv::PseudoVC_FPR64V_SE_M1 = 1091 ,
  LIEF::assembly::riscv::PseudoVC_FPR64V_SE_M2 = 1092 , LIEF::assembly::riscv::PseudoVC_FPR64V_SE_M4 = 1093 , LIEF::assembly::riscv::PseudoVC_FPR64V_SE_M8 = 1094 , LIEF::assembly::riscv::PseudoVC_IVV_SE_M1 = 1095 ,
  LIEF::assembly::riscv::PseudoVC_IVV_SE_M2 = 1096 , LIEF::assembly::riscv::PseudoVC_IVV_SE_M4 = 1097 , LIEF::assembly::riscv::PseudoVC_IVV_SE_M8 = 1098 , LIEF::assembly::riscv::PseudoVC_IVV_SE_MF2 = 1099 ,
  LIEF::assembly::riscv::PseudoVC_IVV_SE_MF4 = 1100 , LIEF::assembly::riscv::PseudoVC_IVV_SE_MF8 = 1101 , LIEF::assembly::riscv::PseudoVC_IVW_SE_M1 = 1102 , LIEF::assembly::riscv::PseudoVC_IVW_SE_M2 = 1103 ,
  LIEF::assembly::riscv::PseudoVC_IVW_SE_M4 = 1104 , LIEF::assembly::riscv::PseudoVC_IVW_SE_MF2 = 1105 , LIEF::assembly::riscv::PseudoVC_IVW_SE_MF4 = 1106 , LIEF::assembly::riscv::PseudoVC_IVW_SE_MF8 = 1107 ,
  LIEF::assembly::riscv::PseudoVC_IV_SE_M1 = 1108 , LIEF::assembly::riscv::PseudoVC_IV_SE_M2 = 1109 , LIEF::assembly::riscv::PseudoVC_IV_SE_M4 = 1110 , LIEF::assembly::riscv::PseudoVC_IV_SE_M8 = 1111 ,
  LIEF::assembly::riscv::PseudoVC_IV_SE_MF2 = 1112 , LIEF::assembly::riscv::PseudoVC_IV_SE_MF4 = 1113 , LIEF::assembly::riscv::PseudoVC_IV_SE_MF8 = 1114 , LIEF::assembly::riscv::PseudoVC_I_SE_M1 = 1115 ,
  LIEF::assembly::riscv::PseudoVC_I_SE_M2 = 1116 , LIEF::assembly::riscv::PseudoVC_I_SE_M4 = 1117 , LIEF::assembly::riscv::PseudoVC_I_SE_M8 = 1118 , LIEF::assembly::riscv::PseudoVC_I_SE_MF2 = 1119 ,
  LIEF::assembly::riscv::PseudoVC_I_SE_MF4 = 1120 , LIEF::assembly::riscv::PseudoVC_I_SE_MF8 = 1121 , LIEF::assembly::riscv::PseudoVC_VVV_SE_M1 = 1122 , LIEF::assembly::riscv::PseudoVC_VVV_SE_M2 = 1123 ,
  LIEF::assembly::riscv::PseudoVC_VVV_SE_M4 = 1124 , LIEF::assembly::riscv::PseudoVC_VVV_SE_M8 = 1125 , LIEF::assembly::riscv::PseudoVC_VVV_SE_MF2 = 1126 , LIEF::assembly::riscv::PseudoVC_VVV_SE_MF4 = 1127 ,
  LIEF::assembly::riscv::PseudoVC_VVV_SE_MF8 = 1128 , LIEF::assembly::riscv::PseudoVC_VVW_SE_M1 = 1129 , LIEF::assembly::riscv::PseudoVC_VVW_SE_M2 = 1130 , LIEF::assembly::riscv::PseudoVC_VVW_SE_M4 = 1131 ,
  LIEF::assembly::riscv::PseudoVC_VVW_SE_MF2 = 1132 , LIEF::assembly::riscv::PseudoVC_VVW_SE_MF4 = 1133 , LIEF::assembly::riscv::PseudoVC_VVW_SE_MF8 = 1134 , LIEF::assembly::riscv::PseudoVC_VV_SE_M1 = 1135 ,
  LIEF::assembly::riscv::PseudoVC_VV_SE_M2 = 1136 , LIEF::assembly::riscv::PseudoVC_VV_SE_M4 = 1137 , LIEF::assembly::riscv::PseudoVC_VV_SE_M8 = 1138 , LIEF::assembly::riscv::PseudoVC_VV_SE_MF2 = 1139 ,
  LIEF::assembly::riscv::PseudoVC_VV_SE_MF4 = 1140 , LIEF::assembly::riscv::PseudoVC_VV_SE_MF8 = 1141 , LIEF::assembly::riscv::PseudoVC_V_FPR16VV_M1 = 1142 , LIEF::assembly::riscv::PseudoVC_V_FPR16VV_M2 = 1143 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR16VV_M4 = 1144 , LIEF::assembly::riscv::PseudoVC_V_FPR16VV_M8 = 1145 , LIEF::assembly::riscv::PseudoVC_V_FPR16VV_MF2 = 1146 , LIEF::assembly::riscv::PseudoVC_V_FPR16VV_MF4 = 1147 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR16VV_SE_M1 = 1148 , LIEF::assembly::riscv::PseudoVC_V_FPR16VV_SE_M2 = 1149 , LIEF::assembly::riscv::PseudoVC_V_FPR16VV_SE_M4 = 1150 , LIEF::assembly::riscv::PseudoVC_V_FPR16VV_SE_M8 = 1151 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR16VV_SE_MF2 = 1152 , LIEF::assembly::riscv::PseudoVC_V_FPR16VV_SE_MF4 = 1153 , LIEF::assembly::riscv::PseudoVC_V_FPR16VW_M1 = 1154 , LIEF::assembly::riscv::PseudoVC_V_FPR16VW_M2 = 1155 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR16VW_M4 = 1156 , LIEF::assembly::riscv::PseudoVC_V_FPR16VW_M8 = 1157 , LIEF::assembly::riscv::PseudoVC_V_FPR16VW_MF2 = 1158 , LIEF::assembly::riscv::PseudoVC_V_FPR16VW_MF4 = 1159 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR16VW_SE_M1 = 1160 , LIEF::assembly::riscv::PseudoVC_V_FPR16VW_SE_M2 = 1161 , LIEF::assembly::riscv::PseudoVC_V_FPR16VW_SE_M4 = 1162 , LIEF::assembly::riscv::PseudoVC_V_FPR16VW_SE_M8 = 1163 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR16VW_SE_MF2 = 1164 , LIEF::assembly::riscv::PseudoVC_V_FPR16VW_SE_MF4 = 1165 , LIEF::assembly::riscv::PseudoVC_V_FPR16V_M1 = 1166 , LIEF::assembly::riscv::PseudoVC_V_FPR16V_M2 = 1167 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR16V_M4 = 1168 , LIEF::assembly::riscv::PseudoVC_V_FPR16V_M8 = 1169 , LIEF::assembly::riscv::PseudoVC_V_FPR16V_MF2 = 1170 , LIEF::assembly::riscv::PseudoVC_V_FPR16V_MF4 = 1171 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR16V_SE_M1 = 1172 , LIEF::assembly::riscv::PseudoVC_V_FPR16V_SE_M2 = 1173 , LIEF::assembly::riscv::PseudoVC_V_FPR16V_SE_M4 = 1174 , LIEF::assembly::riscv::PseudoVC_V_FPR16V_SE_M8 = 1175 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR16V_SE_MF2 = 1176 , LIEF::assembly::riscv::PseudoVC_V_FPR16V_SE_MF4 = 1177 , LIEF::assembly::riscv::PseudoVC_V_FPR32VV_M1 = 1178 , LIEF::assembly::riscv::PseudoVC_V_FPR32VV_M2 = 1179 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR32VV_M4 = 1180 , LIEF::assembly::riscv::PseudoVC_V_FPR32VV_M8 = 1181 , LIEF::assembly::riscv::PseudoVC_V_FPR32VV_MF2 = 1182 , LIEF::assembly::riscv::PseudoVC_V_FPR32VV_SE_M1 = 1183 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR32VV_SE_M2 = 1184 , LIEF::assembly::riscv::PseudoVC_V_FPR32VV_SE_M4 = 1185 , LIEF::assembly::riscv::PseudoVC_V_FPR32VV_SE_M8 = 1186 , LIEF::assembly::riscv::PseudoVC_V_FPR32VV_SE_MF2 = 1187 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR32VW_M1 = 1188 , LIEF::assembly::riscv::PseudoVC_V_FPR32VW_M2 = 1189 , LIEF::assembly::riscv::PseudoVC_V_FPR32VW_M4 = 1190 , LIEF::assembly::riscv::PseudoVC_V_FPR32VW_M8 = 1191 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR32VW_MF2 = 1192 , LIEF::assembly::riscv::PseudoVC_V_FPR32VW_SE_M1 = 1193 , LIEF::assembly::riscv::PseudoVC_V_FPR32VW_SE_M2 = 1194 , LIEF::assembly::riscv::PseudoVC_V_FPR32VW_SE_M4 = 1195 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR32VW_SE_M8 = 1196 , LIEF::assembly::riscv::PseudoVC_V_FPR32VW_SE_MF2 = 1197 , LIEF::assembly::riscv::PseudoVC_V_FPR32V_M1 = 1198 , LIEF::assembly::riscv::PseudoVC_V_FPR32V_M2 = 1199 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR32V_M4 = 1200 , LIEF::assembly::riscv::PseudoVC_V_FPR32V_M8 = 1201 , LIEF::assembly::riscv::PseudoVC_V_FPR32V_MF2 = 1202 , LIEF::assembly::riscv::PseudoVC_V_FPR32V_SE_M1 = 1203 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR32V_SE_M2 = 1204 , LIEF::assembly::riscv::PseudoVC_V_FPR32V_SE_M4 = 1205 , LIEF::assembly::riscv::PseudoVC_V_FPR32V_SE_M8 = 1206 , LIEF::assembly::riscv::PseudoVC_V_FPR32V_SE_MF2 = 1207 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR64VV_M1 = 1208 , LIEF::assembly::riscv::PseudoVC_V_FPR64VV_M2 = 1209 , LIEF::assembly::riscv::PseudoVC_V_FPR64VV_M4 = 1210 , LIEF::assembly::riscv::PseudoVC_V_FPR64VV_M8 = 1211 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR64VV_SE_M1 = 1212 , LIEF::assembly::riscv::PseudoVC_V_FPR64VV_SE_M2 = 1213 , LIEF::assembly::riscv::PseudoVC_V_FPR64VV_SE_M4 = 1214 , LIEF::assembly::riscv::PseudoVC_V_FPR64VV_SE_M8 = 1215 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR64V_M1 = 1216 , LIEF::assembly::riscv::PseudoVC_V_FPR64V_M2 = 1217 , LIEF::assembly::riscv::PseudoVC_V_FPR64V_M4 = 1218 , LIEF::assembly::riscv::PseudoVC_V_FPR64V_M8 = 1219 ,
  LIEF::assembly::riscv::PseudoVC_V_FPR64V_SE_M1 = 1220 , LIEF::assembly::riscv::PseudoVC_V_FPR64V_SE_M2 = 1221 , LIEF::assembly::riscv::PseudoVC_V_FPR64V_SE_M4 = 1222 , LIEF::assembly::riscv::PseudoVC_V_FPR64V_SE_M8 = 1223 ,
  LIEF::assembly::riscv::PseudoVC_V_IVV_M1 = 1224 , LIEF::assembly::riscv::PseudoVC_V_IVV_M2 = 1225 , LIEF::assembly::riscv::PseudoVC_V_IVV_M4 = 1226 , LIEF::assembly::riscv::PseudoVC_V_IVV_M8 = 1227 ,
  LIEF::assembly::riscv::PseudoVC_V_IVV_MF2 = 1228 , LIEF::assembly::riscv::PseudoVC_V_IVV_MF4 = 1229 , LIEF::assembly::riscv::PseudoVC_V_IVV_MF8 = 1230 , LIEF::assembly::riscv::PseudoVC_V_IVV_SE_M1 = 1231 ,
  LIEF::assembly::riscv::PseudoVC_V_IVV_SE_M2 = 1232 , LIEF::assembly::riscv::PseudoVC_V_IVV_SE_M4 = 1233 , LIEF::assembly::riscv::PseudoVC_V_IVV_SE_M8 = 1234 , LIEF::assembly::riscv::PseudoVC_V_IVV_SE_MF2 = 1235 ,
  LIEF::assembly::riscv::PseudoVC_V_IVV_SE_MF4 = 1236 , LIEF::assembly::riscv::PseudoVC_V_IVV_SE_MF8 = 1237 , LIEF::assembly::riscv::PseudoVC_V_IVW_M1 = 1238 , LIEF::assembly::riscv::PseudoVC_V_IVW_M2 = 1239 ,
  LIEF::assembly::riscv::PseudoVC_V_IVW_M4 = 1240 , LIEF::assembly::riscv::PseudoVC_V_IVW_MF2 = 1241 , LIEF::assembly::riscv::PseudoVC_V_IVW_MF4 = 1242 , LIEF::assembly::riscv::PseudoVC_V_IVW_MF8 = 1243 ,
  LIEF::assembly::riscv::PseudoVC_V_IVW_SE_M1 = 1244 , LIEF::assembly::riscv::PseudoVC_V_IVW_SE_M2 = 1245 , LIEF::assembly::riscv::PseudoVC_V_IVW_SE_M4 = 1246 , LIEF::assembly::riscv::PseudoVC_V_IVW_SE_MF2 = 1247 ,
  LIEF::assembly::riscv::PseudoVC_V_IVW_SE_MF4 = 1248 , LIEF::assembly::riscv::PseudoVC_V_IVW_SE_MF8 = 1249 , LIEF::assembly::riscv::PseudoVC_V_IV_M1 = 1250 , LIEF::assembly::riscv::PseudoVC_V_IV_M2 = 1251 ,
  LIEF::assembly::riscv::PseudoVC_V_IV_M4 = 1252 , LIEF::assembly::riscv::PseudoVC_V_IV_M8 = 1253 , LIEF::assembly::riscv::PseudoVC_V_IV_MF2 = 1254 , LIEF::assembly::riscv::PseudoVC_V_IV_MF4 = 1255 ,
  LIEF::assembly::riscv::PseudoVC_V_IV_MF8 = 1256 , LIEF::assembly::riscv::PseudoVC_V_IV_SE_M1 = 1257 , LIEF::assembly::riscv::PseudoVC_V_IV_SE_M2 = 1258 , LIEF::assembly::riscv::PseudoVC_V_IV_SE_M4 = 1259 ,
  LIEF::assembly::riscv::PseudoVC_V_IV_SE_M8 = 1260 , LIEF::assembly::riscv::PseudoVC_V_IV_SE_MF2 = 1261 , LIEF::assembly::riscv::PseudoVC_V_IV_SE_MF4 = 1262 , LIEF::assembly::riscv::PseudoVC_V_IV_SE_MF8 = 1263 ,
  LIEF::assembly::riscv::PseudoVC_V_I_M1 = 1264 , LIEF::assembly::riscv::PseudoVC_V_I_M2 = 1265 , LIEF::assembly::riscv::PseudoVC_V_I_M4 = 1266 , LIEF::assembly::riscv::PseudoVC_V_I_M8 = 1267 ,
  LIEF::assembly::riscv::PseudoVC_V_I_MF2 = 1268 , LIEF::assembly::riscv::PseudoVC_V_I_MF4 = 1269 , LIEF::assembly::riscv::PseudoVC_V_I_MF8 = 1270 , LIEF::assembly::riscv::PseudoVC_V_I_SE_M1 = 1271 ,
  LIEF::assembly::riscv::PseudoVC_V_I_SE_M2 = 1272 , LIEF::assembly::riscv::PseudoVC_V_I_SE_M4 = 1273 , LIEF::assembly::riscv::PseudoVC_V_I_SE_M8 = 1274 , LIEF::assembly::riscv::PseudoVC_V_I_SE_MF2 = 1275 ,
  LIEF::assembly::riscv::PseudoVC_V_I_SE_MF4 = 1276 , LIEF::assembly::riscv::PseudoVC_V_I_SE_MF8 = 1277 , LIEF::assembly::riscv::PseudoVC_V_VVV_M1 = 1278 , LIEF::assembly::riscv::PseudoVC_V_VVV_M2 = 1279 ,
  LIEF::assembly::riscv::PseudoVC_V_VVV_M4 = 1280 , LIEF::assembly::riscv::PseudoVC_V_VVV_M8 = 1281 , LIEF::assembly::riscv::PseudoVC_V_VVV_MF2 = 1282 , LIEF::assembly::riscv::PseudoVC_V_VVV_MF4 = 1283 ,
  LIEF::assembly::riscv::PseudoVC_V_VVV_MF8 = 1284 , LIEF::assembly::riscv::PseudoVC_V_VVV_SE_M1 = 1285 , LIEF::assembly::riscv::PseudoVC_V_VVV_SE_M2 = 1286 , LIEF::assembly::riscv::PseudoVC_V_VVV_SE_M4 = 1287 ,
  LIEF::assembly::riscv::PseudoVC_V_VVV_SE_M8 = 1288 , LIEF::assembly::riscv::PseudoVC_V_VVV_SE_MF2 = 1289 , LIEF::assembly::riscv::PseudoVC_V_VVV_SE_MF4 = 1290 , LIEF::assembly::riscv::PseudoVC_V_VVV_SE_MF8 = 1291 ,
  LIEF::assembly::riscv::PseudoVC_V_VVW_M1 = 1292 , LIEF::assembly::riscv::PseudoVC_V_VVW_M2 = 1293 , LIEF::assembly::riscv::PseudoVC_V_VVW_M4 = 1294 , LIEF::assembly::riscv::PseudoVC_V_VVW_MF2 = 1295 ,
  LIEF::assembly::riscv::PseudoVC_V_VVW_MF4 = 1296 , LIEF::assembly::riscv::PseudoVC_V_VVW_MF8 = 1297 , LIEF::assembly::riscv::PseudoVC_V_VVW_SE_M1 = 1298 , LIEF::assembly::riscv::PseudoVC_V_VVW_SE_M2 = 1299 ,
  LIEF::assembly::riscv::PseudoVC_V_VVW_SE_M4 = 1300 , LIEF::assembly::riscv::PseudoVC_V_VVW_SE_MF2 = 1301 , LIEF::assembly::riscv::PseudoVC_V_VVW_SE_MF4 = 1302 , LIEF::assembly::riscv::PseudoVC_V_VVW_SE_MF8 = 1303 ,
  LIEF::assembly::riscv::PseudoVC_V_VV_M1 = 1304 , LIEF::assembly::riscv::PseudoVC_V_VV_M2 = 1305 , LIEF::assembly::riscv::PseudoVC_V_VV_M4 = 1306 , LIEF::assembly::riscv::PseudoVC_V_VV_M8 = 1307 ,
  LIEF::assembly::riscv::PseudoVC_V_VV_MF2 = 1308 , LIEF::assembly::riscv::PseudoVC_V_VV_MF4 = 1309 , LIEF::assembly::riscv::PseudoVC_V_VV_MF8 = 1310 , LIEF::assembly::riscv::PseudoVC_V_VV_SE_M1 = 1311 ,
  LIEF::assembly::riscv::PseudoVC_V_VV_SE_M2 = 1312 , LIEF::assembly::riscv::PseudoVC_V_VV_SE_M4 = 1313 , LIEF::assembly::riscv::PseudoVC_V_VV_SE_M8 = 1314 , LIEF::assembly::riscv::PseudoVC_V_VV_SE_MF2 = 1315 ,
  LIEF::assembly::riscv::PseudoVC_V_VV_SE_MF4 = 1316 , LIEF::assembly::riscv::PseudoVC_V_VV_SE_MF8 = 1317 , LIEF::assembly::riscv::PseudoVC_V_XVV_M1 = 1318 , LIEF::assembly::riscv::PseudoVC_V_XVV_M2 = 1319 ,
  LIEF::assembly::riscv::PseudoVC_V_XVV_M4 = 1320 , LIEF::assembly::riscv::PseudoVC_V_XVV_M8 = 1321 , LIEF::assembly::riscv::PseudoVC_V_XVV_MF2 = 1322 , LIEF::assembly::riscv::PseudoVC_V_XVV_MF4 = 1323 ,
  LIEF::assembly::riscv::PseudoVC_V_XVV_MF8 = 1324 , LIEF::assembly::riscv::PseudoVC_V_XVV_SE_M1 = 1325 , LIEF::assembly::riscv::PseudoVC_V_XVV_SE_M2 = 1326 , LIEF::assembly::riscv::PseudoVC_V_XVV_SE_M4 = 1327 ,
  LIEF::assembly::riscv::PseudoVC_V_XVV_SE_M8 = 1328 , LIEF::assembly::riscv::PseudoVC_V_XVV_SE_MF2 = 1329 , LIEF::assembly::riscv::PseudoVC_V_XVV_SE_MF4 = 1330 , LIEF::assembly::riscv::PseudoVC_V_XVV_SE_MF8 = 1331 ,
  LIEF::assembly::riscv::PseudoVC_V_XVW_M1 = 1332 , LIEF::assembly::riscv::PseudoVC_V_XVW_M2 = 1333 , LIEF::assembly::riscv::PseudoVC_V_XVW_M4 = 1334 , LIEF::assembly::riscv::PseudoVC_V_XVW_MF2 = 1335 ,
  LIEF::assembly::riscv::PseudoVC_V_XVW_MF4 = 1336 , LIEF::assembly::riscv::PseudoVC_V_XVW_MF8 = 1337 , LIEF::assembly::riscv::PseudoVC_V_XVW_SE_M1 = 1338 , LIEF::assembly::riscv::PseudoVC_V_XVW_SE_M2 = 1339 ,
  LIEF::assembly::riscv::PseudoVC_V_XVW_SE_M4 = 1340 , LIEF::assembly::riscv::PseudoVC_V_XVW_SE_MF2 = 1341 , LIEF::assembly::riscv::PseudoVC_V_XVW_SE_MF4 = 1342 , LIEF::assembly::riscv::PseudoVC_V_XVW_SE_MF8 = 1343 ,
  LIEF::assembly::riscv::PseudoVC_V_XV_M1 = 1344 , LIEF::assembly::riscv::PseudoVC_V_XV_M2 = 1345 , LIEF::assembly::riscv::PseudoVC_V_XV_M4 = 1346 , LIEF::assembly::riscv::PseudoVC_V_XV_M8 = 1347 ,
  LIEF::assembly::riscv::PseudoVC_V_XV_MF2 = 1348 , LIEF::assembly::riscv::PseudoVC_V_XV_MF4 = 1349 , LIEF::assembly::riscv::PseudoVC_V_XV_MF8 = 1350 , LIEF::assembly::riscv::PseudoVC_V_XV_SE_M1 = 1351 ,
  LIEF::assembly::riscv::PseudoVC_V_XV_SE_M2 = 1352 , LIEF::assembly::riscv::PseudoVC_V_XV_SE_M4 = 1353 , LIEF::assembly::riscv::PseudoVC_V_XV_SE_M8 = 1354 , LIEF::assembly::riscv::PseudoVC_V_XV_SE_MF2 = 1355 ,
  LIEF::assembly::riscv::PseudoVC_V_XV_SE_MF4 = 1356 , LIEF::assembly::riscv::PseudoVC_V_XV_SE_MF8 = 1357 , LIEF::assembly::riscv::PseudoVC_V_X_M1 = 1358 , LIEF::assembly::riscv::PseudoVC_V_X_M2 = 1359 ,
  LIEF::assembly::riscv::PseudoVC_V_X_M4 = 1360 , LIEF::assembly::riscv::PseudoVC_V_X_M8 = 1361 , LIEF::assembly::riscv::PseudoVC_V_X_MF2 = 1362 , LIEF::assembly::riscv::PseudoVC_V_X_MF4 = 1363 ,
  LIEF::assembly::riscv::PseudoVC_V_X_MF8 = 1364 , LIEF::assembly::riscv::PseudoVC_V_X_SE_M1 = 1365 , LIEF::assembly::riscv::PseudoVC_V_X_SE_M2 = 1366 , LIEF::assembly::riscv::PseudoVC_V_X_SE_M4 = 1367 ,
  LIEF::assembly::riscv::PseudoVC_V_X_SE_M8 = 1368 , LIEF::assembly::riscv::PseudoVC_V_X_SE_MF2 = 1369 , LIEF::assembly::riscv::PseudoVC_V_X_SE_MF4 = 1370 , LIEF::assembly::riscv::PseudoVC_V_X_SE_MF8 = 1371 ,
  LIEF::assembly::riscv::PseudoVC_XVV_SE_M1 = 1372 , LIEF::assembly::riscv::PseudoVC_XVV_SE_M2 = 1373 , LIEF::assembly::riscv::PseudoVC_XVV_SE_M4 = 1374 , LIEF::assembly::riscv::PseudoVC_XVV_SE_M8 = 1375 ,
  LIEF::assembly::riscv::PseudoVC_XVV_SE_MF2 = 1376 , LIEF::assembly::riscv::PseudoVC_XVV_SE_MF4 = 1377 , LIEF::assembly::riscv::PseudoVC_XVV_SE_MF8 = 1378 , LIEF::assembly::riscv::PseudoVC_XVW_SE_M1 = 1379 ,
  LIEF::assembly::riscv::PseudoVC_XVW_SE_M2 = 1380 , LIEF::assembly::riscv::PseudoVC_XVW_SE_M4 = 1381 , LIEF::assembly::riscv::PseudoVC_XVW_SE_MF2 = 1382 , LIEF::assembly::riscv::PseudoVC_XVW_SE_MF4 = 1383 ,
  LIEF::assembly::riscv::PseudoVC_XVW_SE_MF8 = 1384 , LIEF::assembly::riscv::PseudoVC_XV_SE_M1 = 1385 , LIEF::assembly::riscv::PseudoVC_XV_SE_M2 = 1386 , LIEF::assembly::riscv::PseudoVC_XV_SE_M4 = 1387 ,
  LIEF::assembly::riscv::PseudoVC_XV_SE_M8 = 1388 , LIEF::assembly::riscv::PseudoVC_XV_SE_MF2 = 1389 , LIEF::assembly::riscv::PseudoVC_XV_SE_MF4 = 1390 , LIEF::assembly::riscv::PseudoVC_XV_SE_MF8 = 1391 ,
  LIEF::assembly::riscv::PseudoVC_X_SE_M1 = 1392 , LIEF::assembly::riscv::PseudoVC_X_SE_M2 = 1393 , LIEF::assembly::riscv::PseudoVC_X_SE_M4 = 1394 , LIEF::assembly::riscv::PseudoVC_X_SE_M8 = 1395 ,
  LIEF::assembly::riscv::PseudoVC_X_SE_MF2 = 1396 , LIEF::assembly::riscv::PseudoVC_X_SE_MF4 = 1397 , LIEF::assembly::riscv::PseudoVC_X_SE_MF8 = 1398 , LIEF::assembly::riscv::PseudoVDIVU_VV_M1_E16 = 1399 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_M1_E16_MASK = 1400 , LIEF::assembly::riscv::PseudoVDIVU_VV_M1_E32 = 1401 , LIEF::assembly::riscv::PseudoVDIVU_VV_M1_E32_MASK = 1402 , LIEF::assembly::riscv::PseudoVDIVU_VV_M1_E64 = 1403 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_M1_E64_MASK = 1404 , LIEF::assembly::riscv::PseudoVDIVU_VV_M1_E8 = 1405 , LIEF::assembly::riscv::PseudoVDIVU_VV_M1_E8_MASK = 1406 , LIEF::assembly::riscv::PseudoVDIVU_VV_M2_E16 = 1407 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_M2_E16_MASK = 1408 , LIEF::assembly::riscv::PseudoVDIVU_VV_M2_E32 = 1409 , LIEF::assembly::riscv::PseudoVDIVU_VV_M2_E32_MASK = 1410 , LIEF::assembly::riscv::PseudoVDIVU_VV_M2_E64 = 1411 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_M2_E64_MASK = 1412 , LIEF::assembly::riscv::PseudoVDIVU_VV_M2_E8 = 1413 , LIEF::assembly::riscv::PseudoVDIVU_VV_M2_E8_MASK = 1414 , LIEF::assembly::riscv::PseudoVDIVU_VV_M4_E16 = 1415 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_M4_E16_MASK = 1416 , LIEF::assembly::riscv::PseudoVDIVU_VV_M4_E32 = 1417 , LIEF::assembly::riscv::PseudoVDIVU_VV_M4_E32_MASK = 1418 , LIEF::assembly::riscv::PseudoVDIVU_VV_M4_E64 = 1419 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_M4_E64_MASK = 1420 , LIEF::assembly::riscv::PseudoVDIVU_VV_M4_E8 = 1421 , LIEF::assembly::riscv::PseudoVDIVU_VV_M4_E8_MASK = 1422 , LIEF::assembly::riscv::PseudoVDIVU_VV_M8_E16 = 1423 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_M8_E16_MASK = 1424 , LIEF::assembly::riscv::PseudoVDIVU_VV_M8_E32 = 1425 , LIEF::assembly::riscv::PseudoVDIVU_VV_M8_E32_MASK = 1426 , LIEF::assembly::riscv::PseudoVDIVU_VV_M8_E64 = 1427 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_M8_E64_MASK = 1428 , LIEF::assembly::riscv::PseudoVDIVU_VV_M8_E8 = 1429 , LIEF::assembly::riscv::PseudoVDIVU_VV_M8_E8_MASK = 1430 , LIEF::assembly::riscv::PseudoVDIVU_VV_MF2_E16 = 1431 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_MF2_E16_MASK = 1432 , LIEF::assembly::riscv::PseudoVDIVU_VV_MF2_E32 = 1433 , LIEF::assembly::riscv::PseudoVDIVU_VV_MF2_E32_MASK = 1434 , LIEF::assembly::riscv::PseudoVDIVU_VV_MF2_E8 = 1435 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_MF2_E8_MASK = 1436 , LIEF::assembly::riscv::PseudoVDIVU_VV_MF4_E16 = 1437 , LIEF::assembly::riscv::PseudoVDIVU_VV_MF4_E16_MASK = 1438 , LIEF::assembly::riscv::PseudoVDIVU_VV_MF4_E8 = 1439 ,
  LIEF::assembly::riscv::PseudoVDIVU_VV_MF4_E8_MASK = 1440 , LIEF::assembly::riscv::PseudoVDIVU_VV_MF8_E8 = 1441 , LIEF::assembly::riscv::PseudoVDIVU_VV_MF8_E8_MASK = 1442 , LIEF::assembly::riscv::PseudoVDIVU_VX_M1_E16 = 1443 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_M1_E16_MASK = 1444 , LIEF::assembly::riscv::PseudoVDIVU_VX_M1_E32 = 1445 , LIEF::assembly::riscv::PseudoVDIVU_VX_M1_E32_MASK = 1446 , LIEF::assembly::riscv::PseudoVDIVU_VX_M1_E64 = 1447 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_M1_E64_MASK = 1448 , LIEF::assembly::riscv::PseudoVDIVU_VX_M1_E8 = 1449 , LIEF::assembly::riscv::PseudoVDIVU_VX_M1_E8_MASK = 1450 , LIEF::assembly::riscv::PseudoVDIVU_VX_M2_E16 = 1451 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_M2_E16_MASK = 1452 , LIEF::assembly::riscv::PseudoVDIVU_VX_M2_E32 = 1453 , LIEF::assembly::riscv::PseudoVDIVU_VX_M2_E32_MASK = 1454 , LIEF::assembly::riscv::PseudoVDIVU_VX_M2_E64 = 1455 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_M2_E64_MASK = 1456 , LIEF::assembly::riscv::PseudoVDIVU_VX_M2_E8 = 1457 , LIEF::assembly::riscv::PseudoVDIVU_VX_M2_E8_MASK = 1458 , LIEF::assembly::riscv::PseudoVDIVU_VX_M4_E16 = 1459 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_M4_E16_MASK = 1460 , LIEF::assembly::riscv::PseudoVDIVU_VX_M4_E32 = 1461 , LIEF::assembly::riscv::PseudoVDIVU_VX_M4_E32_MASK = 1462 , LIEF::assembly::riscv::PseudoVDIVU_VX_M4_E64 = 1463 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_M4_E64_MASK = 1464 , LIEF::assembly::riscv::PseudoVDIVU_VX_M4_E8 = 1465 , LIEF::assembly::riscv::PseudoVDIVU_VX_M4_E8_MASK = 1466 , LIEF::assembly::riscv::PseudoVDIVU_VX_M8_E16 = 1467 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_M8_E16_MASK = 1468 , LIEF::assembly::riscv::PseudoVDIVU_VX_M8_E32 = 1469 , LIEF::assembly::riscv::PseudoVDIVU_VX_M8_E32_MASK = 1470 , LIEF::assembly::riscv::PseudoVDIVU_VX_M8_E64 = 1471 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_M8_E64_MASK = 1472 , LIEF::assembly::riscv::PseudoVDIVU_VX_M8_E8 = 1473 , LIEF::assembly::riscv::PseudoVDIVU_VX_M8_E8_MASK = 1474 , LIEF::assembly::riscv::PseudoVDIVU_VX_MF2_E16 = 1475 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_MF2_E16_MASK = 1476 , LIEF::assembly::riscv::PseudoVDIVU_VX_MF2_E32 = 1477 , LIEF::assembly::riscv::PseudoVDIVU_VX_MF2_E32_MASK = 1478 , LIEF::assembly::riscv::PseudoVDIVU_VX_MF2_E8 = 1479 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_MF2_E8_MASK = 1480 , LIEF::assembly::riscv::PseudoVDIVU_VX_MF4_E16 = 1481 , LIEF::assembly::riscv::PseudoVDIVU_VX_MF4_E16_MASK = 1482 , LIEF::assembly::riscv::PseudoVDIVU_VX_MF4_E8 = 1483 ,
  LIEF::assembly::riscv::PseudoVDIVU_VX_MF4_E8_MASK = 1484 , LIEF::assembly::riscv::PseudoVDIVU_VX_MF8_E8 = 1485 , LIEF::assembly::riscv::PseudoVDIVU_VX_MF8_E8_MASK = 1486 , LIEF::assembly::riscv::PseudoVDIV_VV_M1_E16 = 1487 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_M1_E16_MASK = 1488 , LIEF::assembly::riscv::PseudoVDIV_VV_M1_E32 = 1489 , LIEF::assembly::riscv::PseudoVDIV_VV_M1_E32_MASK = 1490 , LIEF::assembly::riscv::PseudoVDIV_VV_M1_E64 = 1491 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_M1_E64_MASK = 1492 , LIEF::assembly::riscv::PseudoVDIV_VV_M1_E8 = 1493 , LIEF::assembly::riscv::PseudoVDIV_VV_M1_E8_MASK = 1494 , LIEF::assembly::riscv::PseudoVDIV_VV_M2_E16 = 1495 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_M2_E16_MASK = 1496 , LIEF::assembly::riscv::PseudoVDIV_VV_M2_E32 = 1497 , LIEF::assembly::riscv::PseudoVDIV_VV_M2_E32_MASK = 1498 , LIEF::assembly::riscv::PseudoVDIV_VV_M2_E64 = 1499 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_M2_E64_MASK = 1500 , LIEF::assembly::riscv::PseudoVDIV_VV_M2_E8 = 1501 , LIEF::assembly::riscv::PseudoVDIV_VV_M2_E8_MASK = 1502 , LIEF::assembly::riscv::PseudoVDIV_VV_M4_E16 = 1503 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_M4_E16_MASK = 1504 , LIEF::assembly::riscv::PseudoVDIV_VV_M4_E32 = 1505 , LIEF::assembly::riscv::PseudoVDIV_VV_M4_E32_MASK = 1506 , LIEF::assembly::riscv::PseudoVDIV_VV_M4_E64 = 1507 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_M4_E64_MASK = 1508 , LIEF::assembly::riscv::PseudoVDIV_VV_M4_E8 = 1509 , LIEF::assembly::riscv::PseudoVDIV_VV_M4_E8_MASK = 1510 , LIEF::assembly::riscv::PseudoVDIV_VV_M8_E16 = 1511 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_M8_E16_MASK = 1512 , LIEF::assembly::riscv::PseudoVDIV_VV_M8_E32 = 1513 , LIEF::assembly::riscv::PseudoVDIV_VV_M8_E32_MASK = 1514 , LIEF::assembly::riscv::PseudoVDIV_VV_M8_E64 = 1515 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_M8_E64_MASK = 1516 , LIEF::assembly::riscv::PseudoVDIV_VV_M8_E8 = 1517 , LIEF::assembly::riscv::PseudoVDIV_VV_M8_E8_MASK = 1518 , LIEF::assembly::riscv::PseudoVDIV_VV_MF2_E16 = 1519 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_MF2_E16_MASK = 1520 , LIEF::assembly::riscv::PseudoVDIV_VV_MF2_E32 = 1521 , LIEF::assembly::riscv::PseudoVDIV_VV_MF2_E32_MASK = 1522 , LIEF::assembly::riscv::PseudoVDIV_VV_MF2_E8 = 1523 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_MF2_E8_MASK = 1524 , LIEF::assembly::riscv::PseudoVDIV_VV_MF4_E16 = 1525 , LIEF::assembly::riscv::PseudoVDIV_VV_MF4_E16_MASK = 1526 , LIEF::assembly::riscv::PseudoVDIV_VV_MF4_E8 = 1527 ,
  LIEF::assembly::riscv::PseudoVDIV_VV_MF4_E8_MASK = 1528 , LIEF::assembly::riscv::PseudoVDIV_VV_MF8_E8 = 1529 , LIEF::assembly::riscv::PseudoVDIV_VV_MF8_E8_MASK = 1530 , LIEF::assembly::riscv::PseudoVDIV_VX_M1_E16 = 1531 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_M1_E16_MASK = 1532 , LIEF::assembly::riscv::PseudoVDIV_VX_M1_E32 = 1533 , LIEF::assembly::riscv::PseudoVDIV_VX_M1_E32_MASK = 1534 , LIEF::assembly::riscv::PseudoVDIV_VX_M1_E64 = 1535 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_M1_E64_MASK = 1536 , LIEF::assembly::riscv::PseudoVDIV_VX_M1_E8 = 1537 , LIEF::assembly::riscv::PseudoVDIV_VX_M1_E8_MASK = 1538 , LIEF::assembly::riscv::PseudoVDIV_VX_M2_E16 = 1539 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_M2_E16_MASK = 1540 , LIEF::assembly::riscv::PseudoVDIV_VX_M2_E32 = 1541 , LIEF::assembly::riscv::PseudoVDIV_VX_M2_E32_MASK = 1542 , LIEF::assembly::riscv::PseudoVDIV_VX_M2_E64 = 1543 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_M2_E64_MASK = 1544 , LIEF::assembly::riscv::PseudoVDIV_VX_M2_E8 = 1545 , LIEF::assembly::riscv::PseudoVDIV_VX_M2_E8_MASK = 1546 , LIEF::assembly::riscv::PseudoVDIV_VX_M4_E16 = 1547 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_M4_E16_MASK = 1548 , LIEF::assembly::riscv::PseudoVDIV_VX_M4_E32 = 1549 , LIEF::assembly::riscv::PseudoVDIV_VX_M4_E32_MASK = 1550 , LIEF::assembly::riscv::PseudoVDIV_VX_M4_E64 = 1551 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_M4_E64_MASK = 1552 , LIEF::assembly::riscv::PseudoVDIV_VX_M4_E8 = 1553 , LIEF::assembly::riscv::PseudoVDIV_VX_M4_E8_MASK = 1554 , LIEF::assembly::riscv::PseudoVDIV_VX_M8_E16 = 1555 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_M8_E16_MASK = 1556 , LIEF::assembly::riscv::PseudoVDIV_VX_M8_E32 = 1557 , LIEF::assembly::riscv::PseudoVDIV_VX_M8_E32_MASK = 1558 , LIEF::assembly::riscv::PseudoVDIV_VX_M8_E64 = 1559 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_M8_E64_MASK = 1560 , LIEF::assembly::riscv::PseudoVDIV_VX_M8_E8 = 1561 , LIEF::assembly::riscv::PseudoVDIV_VX_M8_E8_MASK = 1562 , LIEF::assembly::riscv::PseudoVDIV_VX_MF2_E16 = 1563 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_MF2_E16_MASK = 1564 , LIEF::assembly::riscv::PseudoVDIV_VX_MF2_E32 = 1565 , LIEF::assembly::riscv::PseudoVDIV_VX_MF2_E32_MASK = 1566 , LIEF::assembly::riscv::PseudoVDIV_VX_MF2_E8 = 1567 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_MF2_E8_MASK = 1568 , LIEF::assembly::riscv::PseudoVDIV_VX_MF4_E16 = 1569 , LIEF::assembly::riscv::PseudoVDIV_VX_MF4_E16_MASK = 1570 , LIEF::assembly::riscv::PseudoVDIV_VX_MF4_E8 = 1571 ,
  LIEF::assembly::riscv::PseudoVDIV_VX_MF4_E8_MASK = 1572 , LIEF::assembly::riscv::PseudoVDIV_VX_MF8_E8 = 1573 , LIEF::assembly::riscv::PseudoVDIV_VX_MF8_E8_MASK = 1574 , LIEF::assembly::riscv::PseudoVFADD_VFPR16_M1_E16 = 1575 ,
  LIEF::assembly::riscv::PseudoVFADD_VFPR16_M1_E16_MASK = 1576 , LIEF::assembly::riscv::PseudoVFADD_VFPR16_M2_E16 = 1577 , LIEF::assembly::riscv::PseudoVFADD_VFPR16_M2_E16_MASK = 1578 , LIEF::assembly::riscv::PseudoVFADD_VFPR16_M4_E16 = 1579 ,
  LIEF::assembly::riscv::PseudoVFADD_VFPR16_M4_E16_MASK = 1580 , LIEF::assembly::riscv::PseudoVFADD_VFPR16_M8_E16 = 1581 , LIEF::assembly::riscv::PseudoVFADD_VFPR16_M8_E16_MASK = 1582 , LIEF::assembly::riscv::PseudoVFADD_VFPR16_MF2_E16 = 1583 ,
  LIEF::assembly::riscv::PseudoVFADD_VFPR16_MF2_E16_MASK = 1584 , LIEF::assembly::riscv::PseudoVFADD_VFPR16_MF4_E16 = 1585 , LIEF::assembly::riscv::PseudoVFADD_VFPR16_MF4_E16_MASK = 1586 , LIEF::assembly::riscv::PseudoVFADD_VFPR32_M1_E32 = 1587 ,
  LIEF::assembly::riscv::PseudoVFADD_VFPR32_M1_E32_MASK = 1588 , LIEF::assembly::riscv::PseudoVFADD_VFPR32_M2_E32 = 1589 , LIEF::assembly::riscv::PseudoVFADD_VFPR32_M2_E32_MASK = 1590 , LIEF::assembly::riscv::PseudoVFADD_VFPR32_M4_E32 = 1591 ,
  LIEF::assembly::riscv::PseudoVFADD_VFPR32_M4_E32_MASK = 1592 , LIEF::assembly::riscv::PseudoVFADD_VFPR32_M8_E32 = 1593 , LIEF::assembly::riscv::PseudoVFADD_VFPR32_M8_E32_MASK = 1594 , LIEF::assembly::riscv::PseudoVFADD_VFPR32_MF2_E32 = 1595 ,
  LIEF::assembly::riscv::PseudoVFADD_VFPR32_MF2_E32_MASK = 1596 , LIEF::assembly::riscv::PseudoVFADD_VFPR64_M1_E64 = 1597 , LIEF::assembly::riscv::PseudoVFADD_VFPR64_M1_E64_MASK = 1598 , LIEF::assembly::riscv::PseudoVFADD_VFPR64_M2_E64 = 1599 ,
  LIEF::assembly::riscv::PseudoVFADD_VFPR64_M2_E64_MASK = 1600 , LIEF::assembly::riscv::PseudoVFADD_VFPR64_M4_E64 = 1601 , LIEF::assembly::riscv::PseudoVFADD_VFPR64_M4_E64_MASK = 1602 , LIEF::assembly::riscv::PseudoVFADD_VFPR64_M8_E64 = 1603 ,
  LIEF::assembly::riscv::PseudoVFADD_VFPR64_M8_E64_MASK = 1604 , LIEF::assembly::riscv::PseudoVFADD_VV_M1_E16 = 1605 , LIEF::assembly::riscv::PseudoVFADD_VV_M1_E16_MASK = 1606 , LIEF::assembly::riscv::PseudoVFADD_VV_M1_E32 = 1607 ,
  LIEF::assembly::riscv::PseudoVFADD_VV_M1_E32_MASK = 1608 , LIEF::assembly::riscv::PseudoVFADD_VV_M1_E64 = 1609 , LIEF::assembly::riscv::PseudoVFADD_VV_M1_E64_MASK = 1610 , LIEF::assembly::riscv::PseudoVFADD_VV_M2_E16 = 1611 ,
  LIEF::assembly::riscv::PseudoVFADD_VV_M2_E16_MASK = 1612 , LIEF::assembly::riscv::PseudoVFADD_VV_M2_E32 = 1613 , LIEF::assembly::riscv::PseudoVFADD_VV_M2_E32_MASK = 1614 , LIEF::assembly::riscv::PseudoVFADD_VV_M2_E64 = 1615 ,
  LIEF::assembly::riscv::PseudoVFADD_VV_M2_E64_MASK = 1616 , LIEF::assembly::riscv::PseudoVFADD_VV_M4_E16 = 1617 , LIEF::assembly::riscv::PseudoVFADD_VV_M4_E16_MASK = 1618 , LIEF::assembly::riscv::PseudoVFADD_VV_M4_E32 = 1619 ,
  LIEF::assembly::riscv::PseudoVFADD_VV_M4_E32_MASK = 1620 , LIEF::assembly::riscv::PseudoVFADD_VV_M4_E64 = 1621 , LIEF::assembly::riscv::PseudoVFADD_VV_M4_E64_MASK = 1622 , LIEF::assembly::riscv::PseudoVFADD_VV_M8_E16 = 1623 ,
  LIEF::assembly::riscv::PseudoVFADD_VV_M8_E16_MASK = 1624 , LIEF::assembly::riscv::PseudoVFADD_VV_M8_E32 = 1625 , LIEF::assembly::riscv::PseudoVFADD_VV_M8_E32_MASK = 1626 , LIEF::assembly::riscv::PseudoVFADD_VV_M8_E64 = 1627 ,
  LIEF::assembly::riscv::PseudoVFADD_VV_M8_E64_MASK = 1628 , LIEF::assembly::riscv::PseudoVFADD_VV_MF2_E16 = 1629 , LIEF::assembly::riscv::PseudoVFADD_VV_MF2_E16_MASK = 1630 , LIEF::assembly::riscv::PseudoVFADD_VV_MF2_E32 = 1631 ,
  LIEF::assembly::riscv::PseudoVFADD_VV_MF2_E32_MASK = 1632 , LIEF::assembly::riscv::PseudoVFADD_VV_MF4_E16 = 1633 , LIEF::assembly::riscv::PseudoVFADD_VV_MF4_E16_MASK = 1634 , LIEF::assembly::riscv::PseudoVFCLASS_V_M1 = 1635 ,
  LIEF::assembly::riscv::PseudoVFCLASS_V_M1_MASK = 1636 , LIEF::assembly::riscv::PseudoVFCLASS_V_M2 = 1637 , LIEF::assembly::riscv::PseudoVFCLASS_V_M2_MASK = 1638 , LIEF::assembly::riscv::PseudoVFCLASS_V_M4 = 1639 ,
  LIEF::assembly::riscv::PseudoVFCLASS_V_M4_MASK = 1640 , LIEF::assembly::riscv::PseudoVFCLASS_V_M8 = 1641 , LIEF::assembly::riscv::PseudoVFCLASS_V_M8_MASK = 1642 , LIEF::assembly::riscv::PseudoVFCLASS_V_MF2 = 1643 ,
  LIEF::assembly::riscv::PseudoVFCLASS_V_MF2_MASK = 1644 , LIEF::assembly::riscv::PseudoVFCLASS_V_MF4 = 1645 , LIEF::assembly::riscv::PseudoVFCLASS_V_MF4_MASK = 1646 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M1_E16 = 1647 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M1_E16_MASK = 1648 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M1_E32 = 1649 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M1_E32_MASK = 1650 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M1_E64 = 1651 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M1_E64_MASK = 1652 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M2_E16 = 1653 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M2_E16_MASK = 1654 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M2_E32 = 1655 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M2_E32_MASK = 1656 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M2_E64 = 1657 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M2_E64_MASK = 1658 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M4_E16 = 1659 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M4_E16_MASK = 1660 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M4_E32 = 1661 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M4_E32_MASK = 1662 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M4_E64 = 1663 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M4_E64_MASK = 1664 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M8_E16 = 1665 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M8_E16_MASK = 1666 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M8_E32 = 1667 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M8_E32_MASK = 1668 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M8_E64 = 1669 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_M8_E64_MASK = 1670 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_MF2_E16 = 1671 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_MF2_E16_MASK = 1672 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_MF2_E32 = 1673 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_MF2_E32_MASK = 1674 , LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_MF4_E16 = 1675 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_XU_V_MF4_E16_MASK = 1676 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M1_E16 = 1677 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M1_E16_MASK = 1678 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M1_E32 = 1679 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M1_E32_MASK = 1680 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M1_E64 = 1681 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M1_E64_MASK = 1682 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M2_E16 = 1683 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M2_E16_MASK = 1684 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M2_E32 = 1685 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M2_E32_MASK = 1686 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M2_E64 = 1687 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M2_E64_MASK = 1688 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M4_E16 = 1689 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M4_E16_MASK = 1690 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M4_E32 = 1691 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M4_E32_MASK = 1692 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M4_E64 = 1693 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M4_E64_MASK = 1694 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M8_E16 = 1695 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M8_E16_MASK = 1696 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M8_E32 = 1697 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M8_E32_MASK = 1698 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M8_E64 = 1699 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_X_V_M8_E64_MASK = 1700 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_MF2_E16 = 1701 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_MF2_E16_MASK = 1702 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_MF2_E32 = 1703 ,
  LIEF::assembly::riscv::PseudoVFCVT_F_X_V_MF2_E32_MASK = 1704 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_MF4_E16 = 1705 , LIEF::assembly::riscv::PseudoVFCVT_F_X_V_MF4_E16_MASK = 1706 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M1_E16 = 1707 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M1_E16_MASK = 1708 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M1_E32 = 1709 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M1_E32_MASK = 1710 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M1_E64 = 1711 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M1_E64_MASK = 1712 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M2_E16 = 1713 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M2_E16_MASK = 1714 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M2_E32 = 1715 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M2_E32_MASK = 1716 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M2_E64 = 1717 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M2_E64_MASK = 1718 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M4_E16 = 1719 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M4_E16_MASK = 1720 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M4_E32 = 1721 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M4_E32_MASK = 1722 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M4_E64 = 1723 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M4_E64_MASK = 1724 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M8_E16 = 1725 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M8_E16_MASK = 1726 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M8_E32 = 1727 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M8_E32_MASK = 1728 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M8_E64 = 1729 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_M8_E64_MASK = 1730 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_MF2_E16 = 1731 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK = 1732 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_MF2_E32 = 1733 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK = 1734 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_MF4_E16 = 1735 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK = 1736 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M1_E16 = 1737 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M1_E16_MASK = 1738 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M1_E32 = 1739 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M1_E32_MASK = 1740 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M1_E64 = 1741 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M1_E64_MASK = 1742 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M2_E16 = 1743 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M2_E16_MASK = 1744 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M2_E32 = 1745 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M2_E32_MASK = 1746 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M2_E64 = 1747 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M2_E64_MASK = 1748 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M4_E16 = 1749 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M4_E16_MASK = 1750 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M4_E32 = 1751 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M4_E32_MASK = 1752 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M4_E64 = 1753 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M4_E64_MASK = 1754 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M8_E16 = 1755 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M8_E16_MASK = 1756 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M8_E32 = 1757 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M8_E32_MASK = 1758 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M8_E64 = 1759 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_M8_E64_MASK = 1760 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_MF2_E16 = 1761 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_MF2_E16_MASK = 1762 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_MF2_E32 = 1763 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_MF2_E32_MASK = 1764 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_MF4_E16 = 1765 , LIEF::assembly::riscv::PseudoVFCVT_RM_F_X_V_MF4_E16_MASK = 1766 , LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_M1 = 1767 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_M1_MASK = 1768 , LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_M2 = 1769 , LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_M2_MASK = 1770 , LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_M4 = 1771 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_M4_MASK = 1772 , LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_M8 = 1773 , LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_M8_MASK = 1774 , LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_MF2 = 1775 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_MF2_MASK = 1776 , LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_MF4 = 1777 , LIEF::assembly::riscv::PseudoVFCVT_RM_XU_F_V_MF4_MASK = 1778 , LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_M1 = 1779 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_M1_MASK = 1780 , LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_M2 = 1781 , LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_M2_MASK = 1782 , LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_M4 = 1783 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_M4_MASK = 1784 , LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_M8 = 1785 , LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_M8_MASK = 1786 , LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_MF2 = 1787 ,
  LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_MF2_MASK = 1788 , LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_MF4 = 1789 , LIEF::assembly::riscv::PseudoVFCVT_RM_X_F_V_MF4_MASK = 1790 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_M1 = 1791 ,
  LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_M1_MASK = 1792 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_M2 = 1793 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_M2_MASK = 1794 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_M4 = 1795 ,
  LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_M4_MASK = 1796 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_M8 = 1797 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_M8_MASK = 1798 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_MF2 = 1799 ,
  LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_MF2_MASK = 1800 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_MF4 = 1801 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_XU_F_V_MF4_MASK = 1802 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_M1 = 1803 ,
  LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_M1_MASK = 1804 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_M2 = 1805 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_M2_MASK = 1806 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_M4 = 1807 ,
  LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_M4_MASK = 1808 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_M8 = 1809 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_M8_MASK = 1810 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_MF2 = 1811 ,
  LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_MF2_MASK = 1812 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_MF4 = 1813 , LIEF::assembly::riscv::PseudoVFCVT_RTZ_X_F_V_MF4_MASK = 1814 , LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_M1 = 1815 ,
  LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_M1_MASK = 1816 , LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_M2 = 1817 , LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_M2_MASK = 1818 , LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_M4 = 1819 ,
  LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_M4_MASK = 1820 , LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_M8 = 1821 , LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_M8_MASK = 1822 , LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_MF2 = 1823 ,
  LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_MF2_MASK = 1824 , LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_MF4 = 1825 , LIEF::assembly::riscv::PseudoVFCVT_XU_F_V_MF4_MASK = 1826 , LIEF::assembly::riscv::PseudoVFCVT_X_F_V_M1 = 1827 ,
  LIEF::assembly::riscv::PseudoVFCVT_X_F_V_M1_MASK = 1828 , LIEF::assembly::riscv::PseudoVFCVT_X_F_V_M2 = 1829 , LIEF::assembly::riscv::PseudoVFCVT_X_F_V_M2_MASK = 1830 , LIEF::assembly::riscv::PseudoVFCVT_X_F_V_M4 = 1831 ,
  LIEF::assembly::riscv::PseudoVFCVT_X_F_V_M4_MASK = 1832 , LIEF::assembly::riscv::PseudoVFCVT_X_F_V_M8 = 1833 , LIEF::assembly::riscv::PseudoVFCVT_X_F_V_M8_MASK = 1834 , LIEF::assembly::riscv::PseudoVFCVT_X_F_V_MF2 = 1835 ,
  LIEF::assembly::riscv::PseudoVFCVT_X_F_V_MF2_MASK = 1836 , LIEF::assembly::riscv::PseudoVFCVT_X_F_V_MF4 = 1837 , LIEF::assembly::riscv::PseudoVFCVT_X_F_V_MF4_MASK = 1838 , LIEF::assembly::riscv::PseudoVFDIV_VFPR16_M1_E16 = 1839 ,
  LIEF::assembly::riscv::PseudoVFDIV_VFPR16_M1_E16_MASK = 1840 , LIEF::assembly::riscv::PseudoVFDIV_VFPR16_M2_E16 = 1841 , LIEF::assembly::riscv::PseudoVFDIV_VFPR16_M2_E16_MASK = 1842 , LIEF::assembly::riscv::PseudoVFDIV_VFPR16_M4_E16 = 1843 ,
  LIEF::assembly::riscv::PseudoVFDIV_VFPR16_M4_E16_MASK = 1844 , LIEF::assembly::riscv::PseudoVFDIV_VFPR16_M8_E16 = 1845 , LIEF::assembly::riscv::PseudoVFDIV_VFPR16_M8_E16_MASK = 1846 , LIEF::assembly::riscv::PseudoVFDIV_VFPR16_MF2_E16 = 1847 ,
  LIEF::assembly::riscv::PseudoVFDIV_VFPR16_MF2_E16_MASK = 1848 , LIEF::assembly::riscv::PseudoVFDIV_VFPR16_MF4_E16 = 1849 , LIEF::assembly::riscv::PseudoVFDIV_VFPR16_MF4_E16_MASK = 1850 , LIEF::assembly::riscv::PseudoVFDIV_VFPR32_M1_E32 = 1851 ,
  LIEF::assembly::riscv::PseudoVFDIV_VFPR32_M1_E32_MASK = 1852 , LIEF::assembly::riscv::PseudoVFDIV_VFPR32_M2_E32 = 1853 , LIEF::assembly::riscv::PseudoVFDIV_VFPR32_M2_E32_MASK = 1854 , LIEF::assembly::riscv::PseudoVFDIV_VFPR32_M4_E32 = 1855 ,
  LIEF::assembly::riscv::PseudoVFDIV_VFPR32_M4_E32_MASK = 1856 , LIEF::assembly::riscv::PseudoVFDIV_VFPR32_M8_E32 = 1857 , LIEF::assembly::riscv::PseudoVFDIV_VFPR32_M8_E32_MASK = 1858 , LIEF::assembly::riscv::PseudoVFDIV_VFPR32_MF2_E32 = 1859 ,
  LIEF::assembly::riscv::PseudoVFDIV_VFPR32_MF2_E32_MASK = 1860 , LIEF::assembly::riscv::PseudoVFDIV_VFPR64_M1_E64 = 1861 , LIEF::assembly::riscv::PseudoVFDIV_VFPR64_M1_E64_MASK = 1862 , LIEF::assembly::riscv::PseudoVFDIV_VFPR64_M2_E64 = 1863 ,
  LIEF::assembly::riscv::PseudoVFDIV_VFPR64_M2_E64_MASK = 1864 , LIEF::assembly::riscv::PseudoVFDIV_VFPR64_M4_E64 = 1865 , LIEF::assembly::riscv::PseudoVFDIV_VFPR64_M4_E64_MASK = 1866 , LIEF::assembly::riscv::PseudoVFDIV_VFPR64_M8_E64 = 1867 ,
  LIEF::assembly::riscv::PseudoVFDIV_VFPR64_M8_E64_MASK = 1868 , LIEF::assembly::riscv::PseudoVFDIV_VV_M1_E16 = 1869 , LIEF::assembly::riscv::PseudoVFDIV_VV_M1_E16_MASK = 1870 , LIEF::assembly::riscv::PseudoVFDIV_VV_M1_E32 = 1871 ,
  LIEF::assembly::riscv::PseudoVFDIV_VV_M1_E32_MASK = 1872 , LIEF::assembly::riscv::PseudoVFDIV_VV_M1_E64 = 1873 , LIEF::assembly::riscv::PseudoVFDIV_VV_M1_E64_MASK = 1874 , LIEF::assembly::riscv::PseudoVFDIV_VV_M2_E16 = 1875 ,
  LIEF::assembly::riscv::PseudoVFDIV_VV_M2_E16_MASK = 1876 , LIEF::assembly::riscv::PseudoVFDIV_VV_M2_E32 = 1877 , LIEF::assembly::riscv::PseudoVFDIV_VV_M2_E32_MASK = 1878 , LIEF::assembly::riscv::PseudoVFDIV_VV_M2_E64 = 1879 ,
  LIEF::assembly::riscv::PseudoVFDIV_VV_M2_E64_MASK = 1880 , LIEF::assembly::riscv::PseudoVFDIV_VV_M4_E16 = 1881 , LIEF::assembly::riscv::PseudoVFDIV_VV_M4_E16_MASK = 1882 , LIEF::assembly::riscv::PseudoVFDIV_VV_M4_E32 = 1883 ,
  LIEF::assembly::riscv::PseudoVFDIV_VV_M4_E32_MASK = 1884 , LIEF::assembly::riscv::PseudoVFDIV_VV_M4_E64 = 1885 , LIEF::assembly::riscv::PseudoVFDIV_VV_M4_E64_MASK = 1886 , LIEF::assembly::riscv::PseudoVFDIV_VV_M8_E16 = 1887 ,
  LIEF::assembly::riscv::PseudoVFDIV_VV_M8_E16_MASK = 1888 , LIEF::assembly::riscv::PseudoVFDIV_VV_M8_E32 = 1889 , LIEF::assembly::riscv::PseudoVFDIV_VV_M8_E32_MASK = 1890 , LIEF::assembly::riscv::PseudoVFDIV_VV_M8_E64 = 1891 ,
  LIEF::assembly::riscv::PseudoVFDIV_VV_M8_E64_MASK = 1892 , LIEF::assembly::riscv::PseudoVFDIV_VV_MF2_E16 = 1893 , LIEF::assembly::riscv::PseudoVFDIV_VV_MF2_E16_MASK = 1894 , LIEF::assembly::riscv::PseudoVFDIV_VV_MF2_E32 = 1895 ,
  LIEF::assembly::riscv::PseudoVFDIV_VV_MF2_E32_MASK = 1896 , LIEF::assembly::riscv::PseudoVFDIV_VV_MF4_E16 = 1897 , LIEF::assembly::riscv::PseudoVFDIV_VV_MF4_E16_MASK = 1898 , LIEF::assembly::riscv::PseudoVFIRST_M_B1 = 1899 ,
  LIEF::assembly::riscv::PseudoVFIRST_M_B16 = 1900 , LIEF::assembly::riscv::PseudoVFIRST_M_B16_MASK = 1901 , LIEF::assembly::riscv::PseudoVFIRST_M_B1_MASK = 1902 , LIEF::assembly::riscv::PseudoVFIRST_M_B2 = 1903 ,
  LIEF::assembly::riscv::PseudoVFIRST_M_B2_MASK = 1904 , LIEF::assembly::riscv::PseudoVFIRST_M_B32 = 1905 , LIEF::assembly::riscv::PseudoVFIRST_M_B32_MASK = 1906 , LIEF::assembly::riscv::PseudoVFIRST_M_B4 = 1907 ,
  LIEF::assembly::riscv::PseudoVFIRST_M_B4_MASK = 1908 , LIEF::assembly::riscv::PseudoVFIRST_M_B64 = 1909 , LIEF::assembly::riscv::PseudoVFIRST_M_B64_MASK = 1910 , LIEF::assembly::riscv::PseudoVFIRST_M_B8 = 1911 ,
  LIEF::assembly::riscv::PseudoVFIRST_M_B8_MASK = 1912 , LIEF::assembly::riscv::PseudoVFMACC_VFPR16_M1_E16 = 1913 , LIEF::assembly::riscv::PseudoVFMACC_VFPR16_M1_E16_MASK = 1914 , LIEF::assembly::riscv::PseudoVFMACC_VFPR16_M2_E16 = 1915 ,
  LIEF::assembly::riscv::PseudoVFMACC_VFPR16_M2_E16_MASK = 1916 , LIEF::assembly::riscv::PseudoVFMACC_VFPR16_M4_E16 = 1917 , LIEF::assembly::riscv::PseudoVFMACC_VFPR16_M4_E16_MASK = 1918 , LIEF::assembly::riscv::PseudoVFMACC_VFPR16_M8_E16 = 1919 ,
  LIEF::assembly::riscv::PseudoVFMACC_VFPR16_M8_E16_MASK = 1920 , LIEF::assembly::riscv::PseudoVFMACC_VFPR16_MF2_E16 = 1921 , LIEF::assembly::riscv::PseudoVFMACC_VFPR16_MF2_E16_MASK = 1922 , LIEF::assembly::riscv::PseudoVFMACC_VFPR16_MF4_E16 = 1923 ,
  LIEF::assembly::riscv::PseudoVFMACC_VFPR16_MF4_E16_MASK = 1924 , LIEF::assembly::riscv::PseudoVFMACC_VFPR32_M1_E32 = 1925 , LIEF::assembly::riscv::PseudoVFMACC_VFPR32_M1_E32_MASK = 1926 , LIEF::assembly::riscv::PseudoVFMACC_VFPR32_M2_E32 = 1927 ,
  LIEF::assembly::riscv::PseudoVFMACC_VFPR32_M2_E32_MASK = 1928 , LIEF::assembly::riscv::PseudoVFMACC_VFPR32_M4_E32 = 1929 , LIEF::assembly::riscv::PseudoVFMACC_VFPR32_M4_E32_MASK = 1930 , LIEF::assembly::riscv::PseudoVFMACC_VFPR32_M8_E32 = 1931 ,
  LIEF::assembly::riscv::PseudoVFMACC_VFPR32_M8_E32_MASK = 1932 , LIEF::assembly::riscv::PseudoVFMACC_VFPR32_MF2_E32 = 1933 , LIEF::assembly::riscv::PseudoVFMACC_VFPR32_MF2_E32_MASK = 1934 , LIEF::assembly::riscv::PseudoVFMACC_VFPR64_M1_E64 = 1935 ,
  LIEF::assembly::riscv::PseudoVFMACC_VFPR64_M1_E64_MASK = 1936 , LIEF::assembly::riscv::PseudoVFMACC_VFPR64_M2_E64 = 1937 , LIEF::assembly::riscv::PseudoVFMACC_VFPR64_M2_E64_MASK = 1938 , LIEF::assembly::riscv::PseudoVFMACC_VFPR64_M4_E64 = 1939 ,
  LIEF::assembly::riscv::PseudoVFMACC_VFPR64_M4_E64_MASK = 1940 , LIEF::assembly::riscv::PseudoVFMACC_VFPR64_M8_E64 = 1941 , LIEF::assembly::riscv::PseudoVFMACC_VFPR64_M8_E64_MASK = 1942 , LIEF::assembly::riscv::PseudoVFMACC_VV_M1_E16 = 1943 ,
  LIEF::assembly::riscv::PseudoVFMACC_VV_M1_E16_MASK = 1944 , LIEF::assembly::riscv::PseudoVFMACC_VV_M1_E32 = 1945 , LIEF::assembly::riscv::PseudoVFMACC_VV_M1_E32_MASK = 1946 , LIEF::assembly::riscv::PseudoVFMACC_VV_M1_E64 = 1947 ,
  LIEF::assembly::riscv::PseudoVFMACC_VV_M1_E64_MASK = 1948 , LIEF::assembly::riscv::PseudoVFMACC_VV_M2_E16 = 1949 , LIEF::assembly::riscv::PseudoVFMACC_VV_M2_E16_MASK = 1950 , LIEF::assembly::riscv::PseudoVFMACC_VV_M2_E32 = 1951 ,
  LIEF::assembly::riscv::PseudoVFMACC_VV_M2_E32_MASK = 1952 , LIEF::assembly::riscv::PseudoVFMACC_VV_M2_E64 = 1953 , LIEF::assembly::riscv::PseudoVFMACC_VV_M2_E64_MASK = 1954 , LIEF::assembly::riscv::PseudoVFMACC_VV_M4_E16 = 1955 ,
  LIEF::assembly::riscv::PseudoVFMACC_VV_M4_E16_MASK = 1956 , LIEF::assembly::riscv::PseudoVFMACC_VV_M4_E32 = 1957 , LIEF::assembly::riscv::PseudoVFMACC_VV_M4_E32_MASK = 1958 , LIEF::assembly::riscv::PseudoVFMACC_VV_M4_E64 = 1959 ,
  LIEF::assembly::riscv::PseudoVFMACC_VV_M4_E64_MASK = 1960 , LIEF::assembly::riscv::PseudoVFMACC_VV_M8_E16 = 1961 , LIEF::assembly::riscv::PseudoVFMACC_VV_M8_E16_MASK = 1962 , LIEF::assembly::riscv::PseudoVFMACC_VV_M8_E32 = 1963 ,
  LIEF::assembly::riscv::PseudoVFMACC_VV_M8_E32_MASK = 1964 , LIEF::assembly::riscv::PseudoVFMACC_VV_M8_E64 = 1965 , LIEF::assembly::riscv::PseudoVFMACC_VV_M8_E64_MASK = 1966 , LIEF::assembly::riscv::PseudoVFMACC_VV_MF2_E16 = 1967 ,
  LIEF::assembly::riscv::PseudoVFMACC_VV_MF2_E16_MASK = 1968 , LIEF::assembly::riscv::PseudoVFMACC_VV_MF2_E32 = 1969 , LIEF::assembly::riscv::PseudoVFMACC_VV_MF2_E32_MASK = 1970 , LIEF::assembly::riscv::PseudoVFMACC_VV_MF4_E16 = 1971 ,
  LIEF::assembly::riscv::PseudoVFMACC_VV_MF4_E16_MASK = 1972 , LIEF::assembly::riscv::PseudoVFMADD_VFPR16_M1_E16 = 1973 , LIEF::assembly::riscv::PseudoVFMADD_VFPR16_M1_E16_MASK = 1974 , LIEF::assembly::riscv::PseudoVFMADD_VFPR16_M2_E16 = 1975 ,
  LIEF::assembly::riscv::PseudoVFMADD_VFPR16_M2_E16_MASK = 1976 , LIEF::assembly::riscv::PseudoVFMADD_VFPR16_M4_E16 = 1977 , LIEF::assembly::riscv::PseudoVFMADD_VFPR16_M4_E16_MASK = 1978 , LIEF::assembly::riscv::PseudoVFMADD_VFPR16_M8_E16 = 1979 ,
  LIEF::assembly::riscv::PseudoVFMADD_VFPR16_M8_E16_MASK = 1980 , LIEF::assembly::riscv::PseudoVFMADD_VFPR16_MF2_E16 = 1981 , LIEF::assembly::riscv::PseudoVFMADD_VFPR16_MF2_E16_MASK = 1982 , LIEF::assembly::riscv::PseudoVFMADD_VFPR16_MF4_E16 = 1983 ,
  LIEF::assembly::riscv::PseudoVFMADD_VFPR16_MF4_E16_MASK = 1984 , LIEF::assembly::riscv::PseudoVFMADD_VFPR32_M1_E32 = 1985 , LIEF::assembly::riscv::PseudoVFMADD_VFPR32_M1_E32_MASK = 1986 , LIEF::assembly::riscv::PseudoVFMADD_VFPR32_M2_E32 = 1987 ,
  LIEF::assembly::riscv::PseudoVFMADD_VFPR32_M2_E32_MASK = 1988 , LIEF::assembly::riscv::PseudoVFMADD_VFPR32_M4_E32 = 1989 , LIEF::assembly::riscv::PseudoVFMADD_VFPR32_M4_E32_MASK = 1990 , LIEF::assembly::riscv::PseudoVFMADD_VFPR32_M8_E32 = 1991 ,
  LIEF::assembly::riscv::PseudoVFMADD_VFPR32_M8_E32_MASK = 1992 , LIEF::assembly::riscv::PseudoVFMADD_VFPR32_MF2_E32 = 1993 , LIEF::assembly::riscv::PseudoVFMADD_VFPR32_MF2_E32_MASK = 1994 , LIEF::assembly::riscv::PseudoVFMADD_VFPR64_M1_E64 = 1995 ,
  LIEF::assembly::riscv::PseudoVFMADD_VFPR64_M1_E64_MASK = 1996 , LIEF::assembly::riscv::PseudoVFMADD_VFPR64_M2_E64 = 1997 , LIEF::assembly::riscv::PseudoVFMADD_VFPR64_M2_E64_MASK = 1998 , LIEF::assembly::riscv::PseudoVFMADD_VFPR64_M4_E64 = 1999 ,
  LIEF::assembly::riscv::PseudoVFMADD_VFPR64_M4_E64_MASK = 2000 , LIEF::assembly::riscv::PseudoVFMADD_VFPR64_M8_E64 = 2001 , LIEF::assembly::riscv::PseudoVFMADD_VFPR64_M8_E64_MASK = 2002 , LIEF::assembly::riscv::PseudoVFMADD_VV_M1_E16 = 2003 ,
  LIEF::assembly::riscv::PseudoVFMADD_VV_M1_E16_MASK = 2004 , LIEF::assembly::riscv::PseudoVFMADD_VV_M1_E32 = 2005 , LIEF::assembly::riscv::PseudoVFMADD_VV_M1_E32_MASK = 2006 , LIEF::assembly::riscv::PseudoVFMADD_VV_M1_E64 = 2007 ,
  LIEF::assembly::riscv::PseudoVFMADD_VV_M1_E64_MASK = 2008 , LIEF::assembly::riscv::PseudoVFMADD_VV_M2_E16 = 2009 , LIEF::assembly::riscv::PseudoVFMADD_VV_M2_E16_MASK = 2010 , LIEF::assembly::riscv::PseudoVFMADD_VV_M2_E32 = 2011 ,
  LIEF::assembly::riscv::PseudoVFMADD_VV_M2_E32_MASK = 2012 , LIEF::assembly::riscv::PseudoVFMADD_VV_M2_E64 = 2013 , LIEF::assembly::riscv::PseudoVFMADD_VV_M2_E64_MASK = 2014 , LIEF::assembly::riscv::PseudoVFMADD_VV_M4_E16 = 2015 ,
  LIEF::assembly::riscv::PseudoVFMADD_VV_M4_E16_MASK = 2016 , LIEF::assembly::riscv::PseudoVFMADD_VV_M4_E32 = 2017 , LIEF::assembly::riscv::PseudoVFMADD_VV_M4_E32_MASK = 2018 , LIEF::assembly::riscv::PseudoVFMADD_VV_M4_E64 = 2019 ,
  LIEF::assembly::riscv::PseudoVFMADD_VV_M4_E64_MASK = 2020 , LIEF::assembly::riscv::PseudoVFMADD_VV_M8_E16 = 2021 , LIEF::assembly::riscv::PseudoVFMADD_VV_M8_E16_MASK = 2022 , LIEF::assembly::riscv::PseudoVFMADD_VV_M8_E32 = 2023 ,
  LIEF::assembly::riscv::PseudoVFMADD_VV_M8_E32_MASK = 2024 , LIEF::assembly::riscv::PseudoVFMADD_VV_M8_E64 = 2025 , LIEF::assembly::riscv::PseudoVFMADD_VV_M8_E64_MASK = 2026 , LIEF::assembly::riscv::PseudoVFMADD_VV_MF2_E16 = 2027 ,
  LIEF::assembly::riscv::PseudoVFMADD_VV_MF2_E16_MASK = 2028 , LIEF::assembly::riscv::PseudoVFMADD_VV_MF2_E32 = 2029 , LIEF::assembly::riscv::PseudoVFMADD_VV_MF2_E32_MASK = 2030 , LIEF::assembly::riscv::PseudoVFMADD_VV_MF4_E16 = 2031 ,
  LIEF::assembly::riscv::PseudoVFMADD_VV_MF4_E16_MASK = 2032 , LIEF::assembly::riscv::PseudoVFMAX_VFPR16_M1_E16 = 2033 , LIEF::assembly::riscv::PseudoVFMAX_VFPR16_M1_E16_MASK = 2034 , LIEF::assembly::riscv::PseudoVFMAX_VFPR16_M2_E16 = 2035 ,
  LIEF::assembly::riscv::PseudoVFMAX_VFPR16_M2_E16_MASK = 2036 , LIEF::assembly::riscv::PseudoVFMAX_VFPR16_M4_E16 = 2037 , LIEF::assembly::riscv::PseudoVFMAX_VFPR16_M4_E16_MASK = 2038 , LIEF::assembly::riscv::PseudoVFMAX_VFPR16_M8_E16 = 2039 ,
  LIEF::assembly::riscv::PseudoVFMAX_VFPR16_M8_E16_MASK = 2040 , LIEF::assembly::riscv::PseudoVFMAX_VFPR16_MF2_E16 = 2041 , LIEF::assembly::riscv::PseudoVFMAX_VFPR16_MF2_E16_MASK = 2042 , LIEF::assembly::riscv::PseudoVFMAX_VFPR16_MF4_E16 = 2043 ,
  LIEF::assembly::riscv::PseudoVFMAX_VFPR16_MF4_E16_MASK = 2044 , LIEF::assembly::riscv::PseudoVFMAX_VFPR32_M1_E32 = 2045 , LIEF::assembly::riscv::PseudoVFMAX_VFPR32_M1_E32_MASK = 2046 , LIEF::assembly::riscv::PseudoVFMAX_VFPR32_M2_E32 = 2047 ,
  LIEF::assembly::riscv::PseudoVFMAX_VFPR32_M2_E32_MASK = 2048 , LIEF::assembly::riscv::PseudoVFMAX_VFPR32_M4_E32 = 2049 , LIEF::assembly::riscv::PseudoVFMAX_VFPR32_M4_E32_MASK = 2050 , LIEF::assembly::riscv::PseudoVFMAX_VFPR32_M8_E32 = 2051 ,
  LIEF::assembly::riscv::PseudoVFMAX_VFPR32_M8_E32_MASK = 2052 , LIEF::assembly::riscv::PseudoVFMAX_VFPR32_MF2_E32 = 2053 , LIEF::assembly::riscv::PseudoVFMAX_VFPR32_MF2_E32_MASK = 2054 , LIEF::assembly::riscv::PseudoVFMAX_VFPR64_M1_E64 = 2055 ,
  LIEF::assembly::riscv::PseudoVFMAX_VFPR64_M1_E64_MASK = 2056 , LIEF::assembly::riscv::PseudoVFMAX_VFPR64_M2_E64 = 2057 , LIEF::assembly::riscv::PseudoVFMAX_VFPR64_M2_E64_MASK = 2058 , LIEF::assembly::riscv::PseudoVFMAX_VFPR64_M4_E64 = 2059 ,
  LIEF::assembly::riscv::PseudoVFMAX_VFPR64_M4_E64_MASK = 2060 , LIEF::assembly::riscv::PseudoVFMAX_VFPR64_M8_E64 = 2061 , LIEF::assembly::riscv::PseudoVFMAX_VFPR64_M8_E64_MASK = 2062 , LIEF::assembly::riscv::PseudoVFMAX_VV_M1_E16 = 2063 ,
  LIEF::assembly::riscv::PseudoVFMAX_VV_M1_E16_MASK = 2064 , LIEF::assembly::riscv::PseudoVFMAX_VV_M1_E32 = 2065 , LIEF::assembly::riscv::PseudoVFMAX_VV_M1_E32_MASK = 2066 , LIEF::assembly::riscv::PseudoVFMAX_VV_M1_E64 = 2067 ,
  LIEF::assembly::riscv::PseudoVFMAX_VV_M1_E64_MASK = 2068 , LIEF::assembly::riscv::PseudoVFMAX_VV_M2_E16 = 2069 , LIEF::assembly::riscv::PseudoVFMAX_VV_M2_E16_MASK = 2070 , LIEF::assembly::riscv::PseudoVFMAX_VV_M2_E32 = 2071 ,
  LIEF::assembly::riscv::PseudoVFMAX_VV_M2_E32_MASK = 2072 , LIEF::assembly::riscv::PseudoVFMAX_VV_M2_E64 = 2073 , LIEF::assembly::riscv::PseudoVFMAX_VV_M2_E64_MASK = 2074 , LIEF::assembly::riscv::PseudoVFMAX_VV_M4_E16 = 2075 ,
  LIEF::assembly::riscv::PseudoVFMAX_VV_M4_E16_MASK = 2076 , LIEF::assembly::riscv::PseudoVFMAX_VV_M4_E32 = 2077 , LIEF::assembly::riscv::PseudoVFMAX_VV_M4_E32_MASK = 2078 , LIEF::assembly::riscv::PseudoVFMAX_VV_M4_E64 = 2079 ,
  LIEF::assembly::riscv::PseudoVFMAX_VV_M4_E64_MASK = 2080 , LIEF::assembly::riscv::PseudoVFMAX_VV_M8_E16 = 2081 , LIEF::assembly::riscv::PseudoVFMAX_VV_M8_E16_MASK = 2082 , LIEF::assembly::riscv::PseudoVFMAX_VV_M8_E32 = 2083 ,
  LIEF::assembly::riscv::PseudoVFMAX_VV_M8_E32_MASK = 2084 , LIEF::assembly::riscv::PseudoVFMAX_VV_M8_E64 = 2085 , LIEF::assembly::riscv::PseudoVFMAX_VV_M8_E64_MASK = 2086 , LIEF::assembly::riscv::PseudoVFMAX_VV_MF2_E16 = 2087 ,
  LIEF::assembly::riscv::PseudoVFMAX_VV_MF2_E16_MASK = 2088 , LIEF::assembly::riscv::PseudoVFMAX_VV_MF2_E32 = 2089 , LIEF::assembly::riscv::PseudoVFMAX_VV_MF2_E32_MASK = 2090 , LIEF::assembly::riscv::PseudoVFMAX_VV_MF4_E16 = 2091 ,
  LIEF::assembly::riscv::PseudoVFMAX_VV_MF4_E16_MASK = 2092 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR16M_M1 = 2093 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR16M_M2 = 2094 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR16M_M4 = 2095 ,
  LIEF::assembly::riscv::PseudoVFMERGE_VFPR16M_M8 = 2096 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR16M_MF2 = 2097 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR16M_MF4 = 2098 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR32M_M1 = 2099 ,
  LIEF::assembly::riscv::PseudoVFMERGE_VFPR32M_M2 = 2100 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR32M_M4 = 2101 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR32M_M8 = 2102 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR32M_MF2 = 2103 ,
  LIEF::assembly::riscv::PseudoVFMERGE_VFPR64M_M1 = 2104 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR64M_M2 = 2105 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR64M_M4 = 2106 , LIEF::assembly::riscv::PseudoVFMERGE_VFPR64M_M8 = 2107 ,
  LIEF::assembly::riscv::PseudoVFMIN_VFPR16_M1_E16 = 2108 , LIEF::assembly::riscv::PseudoVFMIN_VFPR16_M1_E16_MASK = 2109 , LIEF::assembly::riscv::PseudoVFMIN_VFPR16_M2_E16 = 2110 , LIEF::assembly::riscv::PseudoVFMIN_VFPR16_M2_E16_MASK = 2111 ,
  LIEF::assembly::riscv::PseudoVFMIN_VFPR16_M4_E16 = 2112 , LIEF::assembly::riscv::PseudoVFMIN_VFPR16_M4_E16_MASK = 2113 , LIEF::assembly::riscv::PseudoVFMIN_VFPR16_M8_E16 = 2114 , LIEF::assembly::riscv::PseudoVFMIN_VFPR16_M8_E16_MASK = 2115 ,
  LIEF::assembly::riscv::PseudoVFMIN_VFPR16_MF2_E16 = 2116 , LIEF::assembly::riscv::PseudoVFMIN_VFPR16_MF2_E16_MASK = 2117 , LIEF::assembly::riscv::PseudoVFMIN_VFPR16_MF4_E16 = 2118 , LIEF::assembly::riscv::PseudoVFMIN_VFPR16_MF4_E16_MASK = 2119 ,
  LIEF::assembly::riscv::PseudoVFMIN_VFPR32_M1_E32 = 2120 , LIEF::assembly::riscv::PseudoVFMIN_VFPR32_M1_E32_MASK = 2121 , LIEF::assembly::riscv::PseudoVFMIN_VFPR32_M2_E32 = 2122 , LIEF::assembly::riscv::PseudoVFMIN_VFPR32_M2_E32_MASK = 2123 ,
  LIEF::assembly::riscv::PseudoVFMIN_VFPR32_M4_E32 = 2124 , LIEF::assembly::riscv::PseudoVFMIN_VFPR32_M4_E32_MASK = 2125 , LIEF::assembly::riscv::PseudoVFMIN_VFPR32_M8_E32 = 2126 , LIEF::assembly::riscv::PseudoVFMIN_VFPR32_M8_E32_MASK = 2127 ,
  LIEF::assembly::riscv::PseudoVFMIN_VFPR32_MF2_E32 = 2128 , LIEF::assembly::riscv::PseudoVFMIN_VFPR32_MF2_E32_MASK = 2129 , LIEF::assembly::riscv::PseudoVFMIN_VFPR64_M1_E64 = 2130 , LIEF::assembly::riscv::PseudoVFMIN_VFPR64_M1_E64_MASK = 2131 ,
  LIEF::assembly::riscv::PseudoVFMIN_VFPR64_M2_E64 = 2132 , LIEF::assembly::riscv::PseudoVFMIN_VFPR64_M2_E64_MASK = 2133 , LIEF::assembly::riscv::PseudoVFMIN_VFPR64_M4_E64 = 2134 , LIEF::assembly::riscv::PseudoVFMIN_VFPR64_M4_E64_MASK = 2135 ,
  LIEF::assembly::riscv::PseudoVFMIN_VFPR64_M8_E64 = 2136 , LIEF::assembly::riscv::PseudoVFMIN_VFPR64_M8_E64_MASK = 2137 , LIEF::assembly::riscv::PseudoVFMIN_VV_M1_E16 = 2138 , LIEF::assembly::riscv::PseudoVFMIN_VV_M1_E16_MASK = 2139 ,
  LIEF::assembly::riscv::PseudoVFMIN_VV_M1_E32 = 2140 , LIEF::assembly::riscv::PseudoVFMIN_VV_M1_E32_MASK = 2141 , LIEF::assembly::riscv::PseudoVFMIN_VV_M1_E64 = 2142 , LIEF::assembly::riscv::PseudoVFMIN_VV_M1_E64_MASK = 2143 ,
  LIEF::assembly::riscv::PseudoVFMIN_VV_M2_E16 = 2144 , LIEF::assembly::riscv::PseudoVFMIN_VV_M2_E16_MASK = 2145 , LIEF::assembly::riscv::PseudoVFMIN_VV_M2_E32 = 2146 , LIEF::assembly::riscv::PseudoVFMIN_VV_M2_E32_MASK = 2147 ,
  LIEF::assembly::riscv::PseudoVFMIN_VV_M2_E64 = 2148 , LIEF::assembly::riscv::PseudoVFMIN_VV_M2_E64_MASK = 2149 , LIEF::assembly::riscv::PseudoVFMIN_VV_M4_E16 = 2150 , LIEF::assembly::riscv::PseudoVFMIN_VV_M4_E16_MASK = 2151 ,
  LIEF::assembly::riscv::PseudoVFMIN_VV_M4_E32 = 2152 , LIEF::assembly::riscv::PseudoVFMIN_VV_M4_E32_MASK = 2153 , LIEF::assembly::riscv::PseudoVFMIN_VV_M4_E64 = 2154 , LIEF::assembly::riscv::PseudoVFMIN_VV_M4_E64_MASK = 2155 ,
  LIEF::assembly::riscv::PseudoVFMIN_VV_M8_E16 = 2156 , LIEF::assembly::riscv::PseudoVFMIN_VV_M8_E16_MASK = 2157 , LIEF::assembly::riscv::PseudoVFMIN_VV_M8_E32 = 2158 , LIEF::assembly::riscv::PseudoVFMIN_VV_M8_E32_MASK = 2159 ,
  LIEF::assembly::riscv::PseudoVFMIN_VV_M8_E64 = 2160 , LIEF::assembly::riscv::PseudoVFMIN_VV_M8_E64_MASK = 2161 , LIEF::assembly::riscv::PseudoVFMIN_VV_MF2_E16 = 2162 , LIEF::assembly::riscv::PseudoVFMIN_VV_MF2_E16_MASK = 2163 ,
  LIEF::assembly::riscv::PseudoVFMIN_VV_MF2_E32 = 2164 , LIEF::assembly::riscv::PseudoVFMIN_VV_MF2_E32_MASK = 2165 , LIEF::assembly::riscv::PseudoVFMIN_VV_MF4_E16 = 2166 , LIEF::assembly::riscv::PseudoVFMIN_VV_MF4_E16_MASK = 2167 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_M1_E16 = 2168 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_M1_E16_MASK = 2169 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_M2_E16 = 2170 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_M2_E16_MASK = 2171 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_M4_E16 = 2172 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_M4_E16_MASK = 2173 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_M8_E16 = 2174 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_M8_E16_MASK = 2175 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_MF2_E16 = 2176 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_MF2_E16_MASK = 2177 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_MF4_E16 = 2178 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR16_MF4_E16_MASK = 2179 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VFPR32_M1_E32 = 2180 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR32_M1_E32_MASK = 2181 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR32_M2_E32 = 2182 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR32_M2_E32_MASK = 2183 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VFPR32_M4_E32 = 2184 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR32_M4_E32_MASK = 2185 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR32_M8_E32 = 2186 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR32_M8_E32_MASK = 2187 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VFPR32_MF2_E32 = 2188 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR32_MF2_E32_MASK = 2189 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR64_M1_E64 = 2190 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR64_M1_E64_MASK = 2191 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VFPR64_M2_E64 = 2192 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR64_M2_E64_MASK = 2193 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR64_M4_E64 = 2194 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR64_M4_E64_MASK = 2195 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VFPR64_M8_E64 = 2196 , LIEF::assembly::riscv::PseudoVFMSAC_VFPR64_M8_E64_MASK = 2197 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M1_E16 = 2198 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M1_E16_MASK = 2199 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VV_M1_E32 = 2200 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M1_E32_MASK = 2201 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M1_E64 = 2202 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M1_E64_MASK = 2203 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VV_M2_E16 = 2204 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M2_E16_MASK = 2205 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M2_E32 = 2206 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M2_E32_MASK = 2207 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VV_M2_E64 = 2208 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M2_E64_MASK = 2209 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M4_E16 = 2210 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M4_E16_MASK = 2211 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VV_M4_E32 = 2212 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M4_E32_MASK = 2213 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M4_E64 = 2214 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M4_E64_MASK = 2215 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VV_M8_E16 = 2216 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M8_E16_MASK = 2217 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M8_E32 = 2218 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M8_E32_MASK = 2219 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VV_M8_E64 = 2220 , LIEF::assembly::riscv::PseudoVFMSAC_VV_M8_E64_MASK = 2221 , LIEF::assembly::riscv::PseudoVFMSAC_VV_MF2_E16 = 2222 , LIEF::assembly::riscv::PseudoVFMSAC_VV_MF2_E16_MASK = 2223 ,
  LIEF::assembly::riscv::PseudoVFMSAC_VV_MF2_E32 = 2224 , LIEF::assembly::riscv::PseudoVFMSAC_VV_MF2_E32_MASK = 2225 , LIEF::assembly::riscv::PseudoVFMSAC_VV_MF4_E16 = 2226 , LIEF::assembly::riscv::PseudoVFMSAC_VV_MF4_E16_MASK = 2227 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_M1_E16 = 2228 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_M1_E16_MASK = 2229 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_M2_E16 = 2230 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_M2_E16_MASK = 2231 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_M4_E16 = 2232 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_M4_E16_MASK = 2233 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_M8_E16 = 2234 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_M8_E16_MASK = 2235 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_MF2_E16 = 2236 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_MF2_E16_MASK = 2237 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_MF4_E16 = 2238 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR16_MF4_E16_MASK = 2239 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VFPR32_M1_E32 = 2240 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR32_M1_E32_MASK = 2241 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR32_M2_E32 = 2242 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR32_M2_E32_MASK = 2243 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VFPR32_M4_E32 = 2244 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR32_M4_E32_MASK = 2245 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR32_M8_E32 = 2246 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR32_M8_E32_MASK = 2247 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VFPR32_MF2_E32 = 2248 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR32_MF2_E32_MASK = 2249 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR64_M1_E64 = 2250 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR64_M1_E64_MASK = 2251 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VFPR64_M2_E64 = 2252 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR64_M2_E64_MASK = 2253 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR64_M4_E64 = 2254 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR64_M4_E64_MASK = 2255 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VFPR64_M8_E64 = 2256 , LIEF::assembly::riscv::PseudoVFMSUB_VFPR64_M8_E64_MASK = 2257 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M1_E16 = 2258 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M1_E16_MASK = 2259 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VV_M1_E32 = 2260 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M1_E32_MASK = 2261 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M1_E64 = 2262 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M1_E64_MASK = 2263 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VV_M2_E16 = 2264 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M2_E16_MASK = 2265 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M2_E32 = 2266 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M2_E32_MASK = 2267 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VV_M2_E64 = 2268 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M2_E64_MASK = 2269 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M4_E16 = 2270 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M4_E16_MASK = 2271 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VV_M4_E32 = 2272 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M4_E32_MASK = 2273 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M4_E64 = 2274 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M4_E64_MASK = 2275 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VV_M8_E16 = 2276 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M8_E16_MASK = 2277 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M8_E32 = 2278 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M8_E32_MASK = 2279 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VV_M8_E64 = 2280 , LIEF::assembly::riscv::PseudoVFMSUB_VV_M8_E64_MASK = 2281 , LIEF::assembly::riscv::PseudoVFMSUB_VV_MF2_E16 = 2282 , LIEF::assembly::riscv::PseudoVFMSUB_VV_MF2_E16_MASK = 2283 ,
  LIEF::assembly::riscv::PseudoVFMSUB_VV_MF2_E32 = 2284 , LIEF::assembly::riscv::PseudoVFMSUB_VV_MF2_E32_MASK = 2285 , LIEF::assembly::riscv::PseudoVFMSUB_VV_MF4_E16 = 2286 , LIEF::assembly::riscv::PseudoVFMSUB_VV_MF4_E16_MASK = 2287 ,
  LIEF::assembly::riscv::PseudoVFMUL_VFPR16_M1_E16 = 2288 , LIEF::assembly::riscv::PseudoVFMUL_VFPR16_M1_E16_MASK = 2289 , LIEF::assembly::riscv::PseudoVFMUL_VFPR16_M2_E16 = 2290 , LIEF::assembly::riscv::PseudoVFMUL_VFPR16_M2_E16_MASK = 2291 ,
  LIEF::assembly::riscv::PseudoVFMUL_VFPR16_M4_E16 = 2292 , LIEF::assembly::riscv::PseudoVFMUL_VFPR16_M4_E16_MASK = 2293 , LIEF::assembly::riscv::PseudoVFMUL_VFPR16_M8_E16 = 2294 , LIEF::assembly::riscv::PseudoVFMUL_VFPR16_M8_E16_MASK = 2295 ,
  LIEF::assembly::riscv::PseudoVFMUL_VFPR16_MF2_E16 = 2296 , LIEF::assembly::riscv::PseudoVFMUL_VFPR16_MF2_E16_MASK = 2297 , LIEF::assembly::riscv::PseudoVFMUL_VFPR16_MF4_E16 = 2298 , LIEF::assembly::riscv::PseudoVFMUL_VFPR16_MF4_E16_MASK = 2299 ,
  LIEF::assembly::riscv::PseudoVFMUL_VFPR32_M1_E32 = 2300 , LIEF::assembly::riscv::PseudoVFMUL_VFPR32_M1_E32_MASK = 2301 , LIEF::assembly::riscv::PseudoVFMUL_VFPR32_M2_E32 = 2302 , LIEF::assembly::riscv::PseudoVFMUL_VFPR32_M2_E32_MASK = 2303 ,
  LIEF::assembly::riscv::PseudoVFMUL_VFPR32_M4_E32 = 2304 , LIEF::assembly::riscv::PseudoVFMUL_VFPR32_M4_E32_MASK = 2305 , LIEF::assembly::riscv::PseudoVFMUL_VFPR32_M8_E32 = 2306 , LIEF::assembly::riscv::PseudoVFMUL_VFPR32_M8_E32_MASK = 2307 ,
  LIEF::assembly::riscv::PseudoVFMUL_VFPR32_MF2_E32 = 2308 , LIEF::assembly::riscv::PseudoVFMUL_VFPR32_MF2_E32_MASK = 2309 , LIEF::assembly::riscv::PseudoVFMUL_VFPR64_M1_E64 = 2310 , LIEF::assembly::riscv::PseudoVFMUL_VFPR64_M1_E64_MASK = 2311 ,
  LIEF::assembly::riscv::PseudoVFMUL_VFPR64_M2_E64 = 2312 , LIEF::assembly::riscv::PseudoVFMUL_VFPR64_M2_E64_MASK = 2313 , LIEF::assembly::riscv::PseudoVFMUL_VFPR64_M4_E64 = 2314 , LIEF::assembly::riscv::PseudoVFMUL_VFPR64_M4_E64_MASK = 2315 ,
  LIEF::assembly::riscv::PseudoVFMUL_VFPR64_M8_E64 = 2316 , LIEF::assembly::riscv::PseudoVFMUL_VFPR64_M8_E64_MASK = 2317 , LIEF::assembly::riscv::PseudoVFMUL_VV_M1_E16 = 2318 , LIEF::assembly::riscv::PseudoVFMUL_VV_M1_E16_MASK = 2319 ,
  LIEF::assembly::riscv::PseudoVFMUL_VV_M1_E32 = 2320 , LIEF::assembly::riscv::PseudoVFMUL_VV_M1_E32_MASK = 2321 , LIEF::assembly::riscv::PseudoVFMUL_VV_M1_E64 = 2322 , LIEF::assembly::riscv::PseudoVFMUL_VV_M1_E64_MASK = 2323 ,
  LIEF::assembly::riscv::PseudoVFMUL_VV_M2_E16 = 2324 , LIEF::assembly::riscv::PseudoVFMUL_VV_M2_E16_MASK = 2325 , LIEF::assembly::riscv::PseudoVFMUL_VV_M2_E32 = 2326 , LIEF::assembly::riscv::PseudoVFMUL_VV_M2_E32_MASK = 2327 ,
  LIEF::assembly::riscv::PseudoVFMUL_VV_M2_E64 = 2328 , LIEF::assembly::riscv::PseudoVFMUL_VV_M2_E64_MASK = 2329 , LIEF::assembly::riscv::PseudoVFMUL_VV_M4_E16 = 2330 , LIEF::assembly::riscv::PseudoVFMUL_VV_M4_E16_MASK = 2331 ,
  LIEF::assembly::riscv::PseudoVFMUL_VV_M4_E32 = 2332 , LIEF::assembly::riscv::PseudoVFMUL_VV_M4_E32_MASK = 2333 , LIEF::assembly::riscv::PseudoVFMUL_VV_M4_E64 = 2334 , LIEF::assembly::riscv::PseudoVFMUL_VV_M4_E64_MASK = 2335 ,
  LIEF::assembly::riscv::PseudoVFMUL_VV_M8_E16 = 2336 , LIEF::assembly::riscv::PseudoVFMUL_VV_M8_E16_MASK = 2337 , LIEF::assembly::riscv::PseudoVFMUL_VV_M8_E32 = 2338 , LIEF::assembly::riscv::PseudoVFMUL_VV_M8_E32_MASK = 2339 ,
  LIEF::assembly::riscv::PseudoVFMUL_VV_M8_E64 = 2340 , LIEF::assembly::riscv::PseudoVFMUL_VV_M8_E64_MASK = 2341 , LIEF::assembly::riscv::PseudoVFMUL_VV_MF2_E16 = 2342 , LIEF::assembly::riscv::PseudoVFMUL_VV_MF2_E16_MASK = 2343 ,
  LIEF::assembly::riscv::PseudoVFMUL_VV_MF2_E32 = 2344 , LIEF::assembly::riscv::PseudoVFMUL_VV_MF2_E32_MASK = 2345 , LIEF::assembly::riscv::PseudoVFMUL_VV_MF4_E16 = 2346 , LIEF::assembly::riscv::PseudoVFMUL_VV_MF4_E16_MASK = 2347 ,
  LIEF::assembly::riscv::PseudoVFMV_FPR16_S_M1 = 2348 , LIEF::assembly::riscv::PseudoVFMV_FPR16_S_M2 = 2349 , LIEF::assembly::riscv::PseudoVFMV_FPR16_S_M4 = 2350 , LIEF::assembly::riscv::PseudoVFMV_FPR16_S_M8 = 2351 ,
  LIEF::assembly::riscv::PseudoVFMV_FPR16_S_MF2 = 2352 , LIEF::assembly::riscv::PseudoVFMV_FPR16_S_MF4 = 2353 , LIEF::assembly::riscv::PseudoVFMV_FPR32_S_M1 = 2354 , LIEF::assembly::riscv::PseudoVFMV_FPR32_S_M2 = 2355 ,
  LIEF::assembly::riscv::PseudoVFMV_FPR32_S_M4 = 2356 , LIEF::assembly::riscv::PseudoVFMV_FPR32_S_M8 = 2357 , LIEF::assembly::riscv::PseudoVFMV_FPR32_S_MF2 = 2358 , LIEF::assembly::riscv::PseudoVFMV_FPR64_S_M1 = 2359 ,
  LIEF::assembly::riscv::PseudoVFMV_FPR64_S_M2 = 2360 , LIEF::assembly::riscv::PseudoVFMV_FPR64_S_M4 = 2361 , LIEF::assembly::riscv::PseudoVFMV_FPR64_S_M8 = 2362 , LIEF::assembly::riscv::PseudoVFMV_S_FPR16_M1 = 2363 ,
  LIEF::assembly::riscv::PseudoVFMV_S_FPR16_M2 = 2364 , LIEF::assembly::riscv::PseudoVFMV_S_FPR16_M4 = 2365 , LIEF::assembly::riscv::PseudoVFMV_S_FPR16_M8 = 2366 , LIEF::assembly::riscv::PseudoVFMV_S_FPR16_MF2 = 2367 ,
  LIEF::assembly::riscv::PseudoVFMV_S_FPR16_MF4 = 2368 , LIEF::assembly::riscv::PseudoVFMV_S_FPR32_M1 = 2369 , LIEF::assembly::riscv::PseudoVFMV_S_FPR32_M2 = 2370 , LIEF::assembly::riscv::PseudoVFMV_S_FPR32_M4 = 2371 ,
  LIEF::assembly::riscv::PseudoVFMV_S_FPR32_M8 = 2372 , LIEF::assembly::riscv::PseudoVFMV_S_FPR32_MF2 = 2373 , LIEF::assembly::riscv::PseudoVFMV_S_FPR64_M1 = 2374 , LIEF::assembly::riscv::PseudoVFMV_S_FPR64_M2 = 2375 ,
  LIEF::assembly::riscv::PseudoVFMV_S_FPR64_M4 = 2376 , LIEF::assembly::riscv::PseudoVFMV_S_FPR64_M8 = 2377 , LIEF::assembly::riscv::PseudoVFMV_V_FPR16_M1 = 2378 , LIEF::assembly::riscv::PseudoVFMV_V_FPR16_M2 = 2379 ,
  LIEF::assembly::riscv::PseudoVFMV_V_FPR16_M4 = 2380 , LIEF::assembly::riscv::PseudoVFMV_V_FPR16_M8 = 2381 , LIEF::assembly::riscv::PseudoVFMV_V_FPR16_MF2 = 2382 , LIEF::assembly::riscv::PseudoVFMV_V_FPR16_MF4 = 2383 ,
  LIEF::assembly::riscv::PseudoVFMV_V_FPR32_M1 = 2384 , LIEF::assembly::riscv::PseudoVFMV_V_FPR32_M2 = 2385 , LIEF::assembly::riscv::PseudoVFMV_V_FPR32_M4 = 2386 , LIEF::assembly::riscv::PseudoVFMV_V_FPR32_M8 = 2387 ,
  LIEF::assembly::riscv::PseudoVFMV_V_FPR32_MF2 = 2388 , LIEF::assembly::riscv::PseudoVFMV_V_FPR64_M1 = 2389 , LIEF::assembly::riscv::PseudoVFMV_V_FPR64_M2 = 2390 , LIEF::assembly::riscv::PseudoVFMV_V_FPR64_M4 = 2391 ,
  LIEF::assembly::riscv::PseudoVFMV_V_FPR64_M8 = 2392 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M1_E16 = 2393 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M1_E16_MASK = 2394 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M1_E32 = 2395 ,
  LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M1_E32_MASK = 2396 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M2_E16 = 2397 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M2_E16_MASK = 2398 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M2_E32 = 2399 ,
  LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M2_E32_MASK = 2400 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M4_E16 = 2401 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M4_E16_MASK = 2402 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M4_E32 = 2403 ,
  LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_M4_E32_MASK = 2404 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_MF2_E16 = 2405 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK = 2406 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_MF2_E32 = 2407 ,
  LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK = 2408 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_MF4_E16 = 2409 , LIEF::assembly::riscv::PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK = 2410 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M1_E16 = 2411 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M1_E16_MASK = 2412 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M1_E32 = 2413 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M1_E32_MASK = 2414 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M2_E16 = 2415 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M2_E16_MASK = 2416 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M2_E32 = 2417 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M2_E32_MASK = 2418 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M4_E16 = 2419 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M4_E16_MASK = 2420 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M4_E32 = 2421 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_M4_E32_MASK = 2422 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_MF2_E16 = 2423 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_MF2_E16_MASK = 2424 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_MF2_E32 = 2425 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_MF2_E32_MASK = 2426 , LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_MF4_E16 = 2427 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_F_W_MF4_E16_MASK = 2428 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M1_E16 = 2429 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M1_E16_MASK = 2430 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M1_E32 = 2431 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M1_E32_MASK = 2432 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M2_E16 = 2433 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M2_E16_MASK = 2434 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M2_E32 = 2435 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M2_E32_MASK = 2436 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M4_E16 = 2437 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M4_E16_MASK = 2438 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M4_E32 = 2439 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_M4_E32_MASK = 2440 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_MF2_E16 = 2441 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_MF2_E16_MASK = 2442 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_MF2_E32 = 2443 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_MF2_E32_MASK = 2444 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_MF4_E16 = 2445 , LIEF::assembly::riscv::PseudoVFNCVT_F_XU_W_MF4_E16_MASK = 2446 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M1_E16 = 2447 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M1_E16_MASK = 2448 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M1_E32 = 2449 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M1_E32_MASK = 2450 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M2_E16 = 2451 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M2_E16_MASK = 2452 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M2_E32 = 2453 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M2_E32_MASK = 2454 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M4_E16 = 2455 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M4_E16_MASK = 2456 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M4_E32 = 2457 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_M4_E32_MASK = 2458 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_MF2_E16 = 2459 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_MF2_E16_MASK = 2460 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_MF2_E32 = 2461 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_MF2_E32_MASK = 2462 , LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_MF4_E16 = 2463 ,
  LIEF::assembly::riscv::PseudoVFNCVT_F_X_W_MF4_E16_MASK = 2464 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M1_E16 = 2465 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK = 2466 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M1_E32 = 2467 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK = 2468 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M2_E16 = 2469 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK = 2470 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M2_E32 = 2471 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK = 2472 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M4_E16 = 2473 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK = 2474 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M4_E32 = 2475 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK = 2476 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_MF2_E16 = 2477 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK = 2478 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_MF2_E32 = 2479 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK = 2480 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_MF4_E16 = 2481 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK = 2482 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M1_E16 = 2483 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M1_E16_MASK = 2484 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M1_E32 = 2485 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M1_E32_MASK = 2486 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M2_E16 = 2487 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M2_E16_MASK = 2488 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M2_E32 = 2489 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M2_E32_MASK = 2490 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M4_E16 = 2491 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M4_E16_MASK = 2492 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M4_E32 = 2493 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_M4_E32_MASK = 2494 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_MF2_E16 = 2495 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK = 2496 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_MF2_E32 = 2497 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK = 2498 , LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_MF4_E16 = 2499 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK = 2500 , LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_M1 = 2501 , LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_M1_MASK = 2502 , LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_M2 = 2503 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_M2_MASK = 2504 , LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_M4 = 2505 , LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_M4_MASK = 2506 , LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_MF2 = 2507 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_MF2_MASK = 2508 , LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_MF4 = 2509 , LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_MF4_MASK = 2510 , LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_MF8 = 2511 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_XU_F_W_MF8_MASK = 2512 , LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_M1 = 2513 , LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_M1_MASK = 2514 , LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_M2 = 2515 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_M2_MASK = 2516 , LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_M4 = 2517 , LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_M4_MASK = 2518 , LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_MF2 = 2519 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_MF2_MASK = 2520 , LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_MF4 = 2521 , LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_MF4_MASK = 2522 , LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_MF8 = 2523 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RM_X_F_W_MF8_MASK = 2524 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M1_E16 = 2525 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK = 2526 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M1_E32 = 2527 ,
  LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK = 2528 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M2_E16 = 2529 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK = 2530 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M2_E32 = 2531 ,
  LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK = 2532 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M4_E16 = 2533 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK = 2534 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M4_E32 = 2535 ,
  LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK = 2536 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_MF2_E16 = 2537 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK = 2538 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_MF2_E32 = 2539 ,
  LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK = 2540 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_MF4_E16 = 2541 , LIEF::assembly::riscv::PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK = 2542 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_M1 = 2543 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_M1_MASK = 2544 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_M2 = 2545 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_M2_MASK = 2546 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_M4 = 2547 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_M4_MASK = 2548 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_MF2 = 2549 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK = 2550 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_MF4 = 2551 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK = 2552 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_MF8 = 2553 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK = 2554 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_M1 = 2555 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_M1_MASK = 2556 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_M2 = 2557 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_M2_MASK = 2558 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_M4 = 2559 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_M4_MASK = 2560 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_MF2 = 2561 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_MF2_MASK = 2562 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_MF4 = 2563 ,
  LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_MF4_MASK = 2564 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_MF8 = 2565 , LIEF::assembly::riscv::PseudoVFNCVT_RTZ_X_F_W_MF8_MASK = 2566 , LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_M1 = 2567 ,
  LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_M1_MASK = 2568 , LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_M2 = 2569 , LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_M2_MASK = 2570 , LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_M4 = 2571 ,
  LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_M4_MASK = 2572 , LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_MF2 = 2573 , LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_MF2_MASK = 2574 , LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_MF4 = 2575 ,
  LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_MF4_MASK = 2576 , LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_MF8 = 2577 , LIEF::assembly::riscv::PseudoVFNCVT_XU_F_W_MF8_MASK = 2578 , LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_M1 = 2579 ,
  LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_M1_MASK = 2580 , LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_M2 = 2581 , LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_M2_MASK = 2582 , LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_M4 = 2583 ,
  LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_M4_MASK = 2584 , LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_MF2 = 2585 , LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_MF2_MASK = 2586 , LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_MF4 = 2587 ,
  LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_MF4_MASK = 2588 , LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_MF8 = 2589 , LIEF::assembly::riscv::PseudoVFNCVT_X_F_W_MF8_MASK = 2590 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_M1_E16 = 2591 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_M1_E16_MASK = 2592 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_M2_E16 = 2593 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_M2_E16_MASK = 2594 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_M4_E16 = 2595 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_M4_E16_MASK = 2596 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_M8_E16 = 2597 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_M8_E16_MASK = 2598 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_MF2_E16 = 2599 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_MF2_E16_MASK = 2600 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_MF4_E16 = 2601 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR16_MF4_E16_MASK = 2602 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR32_M1_E32 = 2603 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VFPR32_M1_E32_MASK = 2604 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR32_M2_E32 = 2605 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR32_M2_E32_MASK = 2606 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR32_M4_E32 = 2607 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VFPR32_M4_E32_MASK = 2608 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR32_M8_E32 = 2609 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR32_M8_E32_MASK = 2610 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR32_MF2_E32 = 2611 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VFPR32_MF2_E32_MASK = 2612 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR64_M1_E64 = 2613 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR64_M1_E64_MASK = 2614 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR64_M2_E64 = 2615 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VFPR64_M2_E64_MASK = 2616 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR64_M4_E64 = 2617 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR64_M4_E64_MASK = 2618 , LIEF::assembly::riscv::PseudoVFNMACC_VFPR64_M8_E64 = 2619 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VFPR64_M8_E64_MASK = 2620 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M1_E16 = 2621 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M1_E16_MASK = 2622 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M1_E32 = 2623 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VV_M1_E32_MASK = 2624 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M1_E64 = 2625 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M1_E64_MASK = 2626 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M2_E16 = 2627 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VV_M2_E16_MASK = 2628 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M2_E32 = 2629 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M2_E32_MASK = 2630 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M2_E64 = 2631 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VV_M2_E64_MASK = 2632 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M4_E16 = 2633 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M4_E16_MASK = 2634 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M4_E32 = 2635 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VV_M4_E32_MASK = 2636 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M4_E64 = 2637 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M4_E64_MASK = 2638 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M8_E16 = 2639 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VV_M8_E16_MASK = 2640 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M8_E32 = 2641 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M8_E32_MASK = 2642 , LIEF::assembly::riscv::PseudoVFNMACC_VV_M8_E64 = 2643 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VV_M8_E64_MASK = 2644 , LIEF::assembly::riscv::PseudoVFNMACC_VV_MF2_E16 = 2645 , LIEF::assembly::riscv::PseudoVFNMACC_VV_MF2_E16_MASK = 2646 , LIEF::assembly::riscv::PseudoVFNMACC_VV_MF2_E32 = 2647 ,
  LIEF::assembly::riscv::PseudoVFNMACC_VV_MF2_E32_MASK = 2648 , LIEF::assembly::riscv::PseudoVFNMACC_VV_MF4_E16 = 2649 , LIEF::assembly::riscv::PseudoVFNMACC_VV_MF4_E16_MASK = 2650 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_M1_E16 = 2651 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_M1_E16_MASK = 2652 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_M2_E16 = 2653 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_M2_E16_MASK = 2654 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_M4_E16 = 2655 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_M4_E16_MASK = 2656 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_M8_E16 = 2657 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_M8_E16_MASK = 2658 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_MF2_E16 = 2659 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_MF2_E16_MASK = 2660 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_MF4_E16 = 2661 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR16_MF4_E16_MASK = 2662 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR32_M1_E32 = 2663 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VFPR32_M1_E32_MASK = 2664 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR32_M2_E32 = 2665 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR32_M2_E32_MASK = 2666 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR32_M4_E32 = 2667 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VFPR32_M4_E32_MASK = 2668 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR32_M8_E32 = 2669 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR32_M8_E32_MASK = 2670 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR32_MF2_E32 = 2671 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VFPR32_MF2_E32_MASK = 2672 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR64_M1_E64 = 2673 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR64_M1_E64_MASK = 2674 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR64_M2_E64 = 2675 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VFPR64_M2_E64_MASK = 2676 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR64_M4_E64 = 2677 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR64_M4_E64_MASK = 2678 , LIEF::assembly::riscv::PseudoVFNMADD_VFPR64_M8_E64 = 2679 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VFPR64_M8_E64_MASK = 2680 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M1_E16 = 2681 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M1_E16_MASK = 2682 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M1_E32 = 2683 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VV_M1_E32_MASK = 2684 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M1_E64 = 2685 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M1_E64_MASK = 2686 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M2_E16 = 2687 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VV_M2_E16_MASK = 2688 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M2_E32 = 2689 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M2_E32_MASK = 2690 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M2_E64 = 2691 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VV_M2_E64_MASK = 2692 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M4_E16 = 2693 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M4_E16_MASK = 2694 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M4_E32 = 2695 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VV_M4_E32_MASK = 2696 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M4_E64 = 2697 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M4_E64_MASK = 2698 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M8_E16 = 2699 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VV_M8_E16_MASK = 2700 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M8_E32 = 2701 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M8_E32_MASK = 2702 , LIEF::assembly::riscv::PseudoVFNMADD_VV_M8_E64 = 2703 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VV_M8_E64_MASK = 2704 , LIEF::assembly::riscv::PseudoVFNMADD_VV_MF2_E16 = 2705 , LIEF::assembly::riscv::PseudoVFNMADD_VV_MF2_E16_MASK = 2706 , LIEF::assembly::riscv::PseudoVFNMADD_VV_MF2_E32 = 2707 ,
  LIEF::assembly::riscv::PseudoVFNMADD_VV_MF2_E32_MASK = 2708 , LIEF::assembly::riscv::PseudoVFNMADD_VV_MF4_E16 = 2709 , LIEF::assembly::riscv::PseudoVFNMADD_VV_MF4_E16_MASK = 2710 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_M1_E16 = 2711 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_M1_E16_MASK = 2712 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_M2_E16 = 2713 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_M2_E16_MASK = 2714 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_M4_E16 = 2715 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_M4_E16_MASK = 2716 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_M8_E16 = 2717 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_M8_E16_MASK = 2718 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_MF2_E16 = 2719 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_MF2_E16_MASK = 2720 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_MF4_E16 = 2721 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR16_MF4_E16_MASK = 2722 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR32_M1_E32 = 2723 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VFPR32_M1_E32_MASK = 2724 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR32_M2_E32 = 2725 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR32_M2_E32_MASK = 2726 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR32_M4_E32 = 2727 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VFPR32_M4_E32_MASK = 2728 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR32_M8_E32 = 2729 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR32_M8_E32_MASK = 2730 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR32_MF2_E32 = 2731 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VFPR32_MF2_E32_MASK = 2732 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR64_M1_E64 = 2733 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR64_M1_E64_MASK = 2734 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR64_M2_E64 = 2735 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VFPR64_M2_E64_MASK = 2736 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR64_M4_E64 = 2737 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR64_M4_E64_MASK = 2738 , LIEF::assembly::riscv::PseudoVFNMSAC_VFPR64_M8_E64 = 2739 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VFPR64_M8_E64_MASK = 2740 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M1_E16 = 2741 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M1_E16_MASK = 2742 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M1_E32 = 2743 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VV_M1_E32_MASK = 2744 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M1_E64 = 2745 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M1_E64_MASK = 2746 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M2_E16 = 2747 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VV_M2_E16_MASK = 2748 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M2_E32 = 2749 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M2_E32_MASK = 2750 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M2_E64 = 2751 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VV_M2_E64_MASK = 2752 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M4_E16 = 2753 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M4_E16_MASK = 2754 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M4_E32 = 2755 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VV_M4_E32_MASK = 2756 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M4_E64 = 2757 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M4_E64_MASK = 2758 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M8_E16 = 2759 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VV_M8_E16_MASK = 2760 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M8_E32 = 2761 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M8_E32_MASK = 2762 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_M8_E64 = 2763 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VV_M8_E64_MASK = 2764 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_MF2_E16 = 2765 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_MF2_E16_MASK = 2766 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_MF2_E32 = 2767 ,
  LIEF::assembly::riscv::PseudoVFNMSAC_VV_MF2_E32_MASK = 2768 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_MF4_E16 = 2769 , LIEF::assembly::riscv::PseudoVFNMSAC_VV_MF4_E16_MASK = 2770 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_M1_E16 = 2771 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_M1_E16_MASK = 2772 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_M2_E16 = 2773 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_M2_E16_MASK = 2774 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_M4_E16 = 2775 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_M4_E16_MASK = 2776 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_M8_E16 = 2777 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_M8_E16_MASK = 2778 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_MF2_E16 = 2779 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_MF2_E16_MASK = 2780 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_MF4_E16 = 2781 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR16_MF4_E16_MASK = 2782 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR32_M1_E32 = 2783 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VFPR32_M1_E32_MASK = 2784 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR32_M2_E32 = 2785 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR32_M2_E32_MASK = 2786 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR32_M4_E32 = 2787 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VFPR32_M4_E32_MASK = 2788 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR32_M8_E32 = 2789 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR32_M8_E32_MASK = 2790 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR32_MF2_E32 = 2791 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VFPR32_MF2_E32_MASK = 2792 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR64_M1_E64 = 2793 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR64_M1_E64_MASK = 2794 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR64_M2_E64 = 2795 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VFPR64_M2_E64_MASK = 2796 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR64_M4_E64 = 2797 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR64_M4_E64_MASK = 2798 , LIEF::assembly::riscv::PseudoVFNMSUB_VFPR64_M8_E64 = 2799 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VFPR64_M8_E64_MASK = 2800 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M1_E16 = 2801 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M1_E16_MASK = 2802 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M1_E32 = 2803 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VV_M1_E32_MASK = 2804 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M1_E64 = 2805 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M1_E64_MASK = 2806 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M2_E16 = 2807 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VV_M2_E16_MASK = 2808 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M2_E32 = 2809 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M2_E32_MASK = 2810 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M2_E64 = 2811 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VV_M2_E64_MASK = 2812 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M4_E16 = 2813 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M4_E16_MASK = 2814 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M4_E32 = 2815 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VV_M4_E32_MASK = 2816 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M4_E64 = 2817 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M4_E64_MASK = 2818 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M8_E16 = 2819 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VV_M8_E16_MASK = 2820 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M8_E32 = 2821 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M8_E32_MASK = 2822 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_M8_E64 = 2823 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VV_M8_E64_MASK = 2824 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_MF2_E16 = 2825 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_MF2_E16_MASK = 2826 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_MF2_E32 = 2827 ,
  LIEF::assembly::riscv::PseudoVFNMSUB_VV_MF2_E32_MASK = 2828 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_MF4_E16 = 2829 , LIEF::assembly::riscv::PseudoVFNMSUB_VV_MF4_E16_MASK = 2830 , LIEF::assembly::riscv::PseudoVFNRCLIP_XU_F_QF_M1 = 2831 ,
  LIEF::assembly::riscv::PseudoVFNRCLIP_XU_F_QF_M1_MASK = 2832 , LIEF::assembly::riscv::PseudoVFNRCLIP_XU_F_QF_M2 = 2833 , LIEF::assembly::riscv::PseudoVFNRCLIP_XU_F_QF_M2_MASK = 2834 , LIEF::assembly::riscv::PseudoVFNRCLIP_XU_F_QF_MF2 = 2835 ,
  LIEF::assembly::riscv::PseudoVFNRCLIP_XU_F_QF_MF2_MASK = 2836 , LIEF::assembly::riscv::PseudoVFNRCLIP_XU_F_QF_MF4 = 2837 , LIEF::assembly::riscv::PseudoVFNRCLIP_XU_F_QF_MF4_MASK = 2838 , LIEF::assembly::riscv::PseudoVFNRCLIP_XU_F_QF_MF8 = 2839 ,
  LIEF::assembly::riscv::PseudoVFNRCLIP_XU_F_QF_MF8_MASK = 2840 , LIEF::assembly::riscv::PseudoVFNRCLIP_X_F_QF_M1 = 2841 , LIEF::assembly::riscv::PseudoVFNRCLIP_X_F_QF_M1_MASK = 2842 , LIEF::assembly::riscv::PseudoVFNRCLIP_X_F_QF_M2 = 2843 ,
  LIEF::assembly::riscv::PseudoVFNRCLIP_X_F_QF_M2_MASK = 2844 , LIEF::assembly::riscv::PseudoVFNRCLIP_X_F_QF_MF2 = 2845 , LIEF::assembly::riscv::PseudoVFNRCLIP_X_F_QF_MF2_MASK = 2846 , LIEF::assembly::riscv::PseudoVFNRCLIP_X_F_QF_MF4 = 2847 ,
  LIEF::assembly::riscv::PseudoVFNRCLIP_X_F_QF_MF4_MASK = 2848 , LIEF::assembly::riscv::PseudoVFNRCLIP_X_F_QF_MF8 = 2849 , LIEF::assembly::riscv::PseudoVFNRCLIP_X_F_QF_MF8_MASK = 2850 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_M1_E16 = 2851 ,
  LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_M1_E16_MASK = 2852 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_M2_E16 = 2853 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_M2_E16_MASK = 2854 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_M4_E16 = 2855 ,
  LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_M4_E16_MASK = 2856 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_M8_E16 = 2857 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_M8_E16_MASK = 2858 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_MF2_E16 = 2859 ,
  LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_MF2_E16_MASK = 2860 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_MF4_E16 = 2861 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR16_MF4_E16_MASK = 2862 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR32_M1_E32 = 2863 ,
  LIEF::assembly::riscv::PseudoVFRDIV_VFPR32_M1_E32_MASK = 2864 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR32_M2_E32 = 2865 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR32_M2_E32_MASK = 2866 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR32_M4_E32 = 2867 ,
  LIEF::assembly::riscv::PseudoVFRDIV_VFPR32_M4_E32_MASK = 2868 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR32_M8_E32 = 2869 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR32_M8_E32_MASK = 2870 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR32_MF2_E32 = 2871 ,
  LIEF::assembly::riscv::PseudoVFRDIV_VFPR32_MF2_E32_MASK = 2872 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR64_M1_E64 = 2873 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR64_M1_E64_MASK = 2874 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR64_M2_E64 = 2875 ,
  LIEF::assembly::riscv::PseudoVFRDIV_VFPR64_M2_E64_MASK = 2876 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR64_M4_E64 = 2877 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR64_M4_E64_MASK = 2878 , LIEF::assembly::riscv::PseudoVFRDIV_VFPR64_M8_E64 = 2879 ,
  LIEF::assembly::riscv::PseudoVFRDIV_VFPR64_M8_E64_MASK = 2880 , LIEF::assembly::riscv::PseudoVFREC7_V_M1_E16 = 2881 , LIEF::assembly::riscv::PseudoVFREC7_V_M1_E16_MASK = 2882 , LIEF::assembly::riscv::PseudoVFREC7_V_M1_E32 = 2883 ,
  LIEF::assembly::riscv::PseudoVFREC7_V_M1_E32_MASK = 2884 , LIEF::assembly::riscv::PseudoVFREC7_V_M1_E64 = 2885 , LIEF::assembly::riscv::PseudoVFREC7_V_M1_E64_MASK = 2886 , LIEF::assembly::riscv::PseudoVFREC7_V_M2_E16 = 2887 ,
  LIEF::assembly::riscv::PseudoVFREC7_V_M2_E16_MASK = 2888 , LIEF::assembly::riscv::PseudoVFREC7_V_M2_E32 = 2889 , LIEF::assembly::riscv::PseudoVFREC7_V_M2_E32_MASK = 2890 , LIEF::assembly::riscv::PseudoVFREC7_V_M2_E64 = 2891 ,
  LIEF::assembly::riscv::PseudoVFREC7_V_M2_E64_MASK = 2892 , LIEF::assembly::riscv::PseudoVFREC7_V_M4_E16 = 2893 , LIEF::assembly::riscv::PseudoVFREC7_V_M4_E16_MASK = 2894 , LIEF::assembly::riscv::PseudoVFREC7_V_M4_E32 = 2895 ,
  LIEF::assembly::riscv::PseudoVFREC7_V_M4_E32_MASK = 2896 , LIEF::assembly::riscv::PseudoVFREC7_V_M4_E64 = 2897 , LIEF::assembly::riscv::PseudoVFREC7_V_M4_E64_MASK = 2898 , LIEF::assembly::riscv::PseudoVFREC7_V_M8_E16 = 2899 ,
  LIEF::assembly::riscv::PseudoVFREC7_V_M8_E16_MASK = 2900 , LIEF::assembly::riscv::PseudoVFREC7_V_M8_E32 = 2901 , LIEF::assembly::riscv::PseudoVFREC7_V_M8_E32_MASK = 2902 , LIEF::assembly::riscv::PseudoVFREC7_V_M8_E64 = 2903 ,
  LIEF::assembly::riscv::PseudoVFREC7_V_M8_E64_MASK = 2904 , LIEF::assembly::riscv::PseudoVFREC7_V_MF2_E16 = 2905 , LIEF::assembly::riscv::PseudoVFREC7_V_MF2_E16_MASK = 2906 , LIEF::assembly::riscv::PseudoVFREC7_V_MF2_E32 = 2907 ,
  LIEF::assembly::riscv::PseudoVFREC7_V_MF2_E32_MASK = 2908 , LIEF::assembly::riscv::PseudoVFREC7_V_MF4_E16 = 2909 , LIEF::assembly::riscv::PseudoVFREC7_V_MF4_E16_MASK = 2910 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M1_E16 = 2911 ,
  LIEF::assembly::riscv::PseudoVFREDMAX_VS_M1_E16_MASK = 2912 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M1_E32 = 2913 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M1_E32_MASK = 2914 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M1_E64 = 2915 ,
  LIEF::assembly::riscv::PseudoVFREDMAX_VS_M1_E64_MASK = 2916 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M2_E16 = 2917 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M2_E16_MASK = 2918 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M2_E32 = 2919 ,
  LIEF::assembly::riscv::PseudoVFREDMAX_VS_M2_E32_MASK = 2920 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M2_E64 = 2921 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M2_E64_MASK = 2922 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M4_E16 = 2923 ,
  LIEF::assembly::riscv::PseudoVFREDMAX_VS_M4_E16_MASK = 2924 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M4_E32 = 2925 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M4_E32_MASK = 2926 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M4_E64 = 2927 ,
  LIEF::assembly::riscv::PseudoVFREDMAX_VS_M4_E64_MASK = 2928 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M8_E16 = 2929 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M8_E16_MASK = 2930 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M8_E32 = 2931 ,
  LIEF::assembly::riscv::PseudoVFREDMAX_VS_M8_E32_MASK = 2932 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M8_E64 = 2933 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_M8_E64_MASK = 2934 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_MF2_E16 = 2935 ,
  LIEF::assembly::riscv::PseudoVFREDMAX_VS_MF2_E16_MASK = 2936 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_MF2_E32 = 2937 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_MF2_E32_MASK = 2938 , LIEF::assembly::riscv::PseudoVFREDMAX_VS_MF4_E16 = 2939 ,
  LIEF::assembly::riscv::PseudoVFREDMAX_VS_MF4_E16_MASK = 2940 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M1_E16 = 2941 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M1_E16_MASK = 2942 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M1_E32 = 2943 ,
  LIEF::assembly::riscv::PseudoVFREDMIN_VS_M1_E32_MASK = 2944 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M1_E64 = 2945 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M1_E64_MASK = 2946 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M2_E16 = 2947 ,
  LIEF::assembly::riscv::PseudoVFREDMIN_VS_M2_E16_MASK = 2948 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M2_E32 = 2949 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M2_E32_MASK = 2950 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M2_E64 = 2951 ,
  LIEF::assembly::riscv::PseudoVFREDMIN_VS_M2_E64_MASK = 2952 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M4_E16 = 2953 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M4_E16_MASK = 2954 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M4_E32 = 2955 ,
  LIEF::assembly::riscv::PseudoVFREDMIN_VS_M4_E32_MASK = 2956 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M4_E64 = 2957 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M4_E64_MASK = 2958 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M8_E16 = 2959 ,
  LIEF::assembly::riscv::PseudoVFREDMIN_VS_M8_E16_MASK = 2960 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M8_E32 = 2961 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M8_E32_MASK = 2962 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_M8_E64 = 2963 ,
  LIEF::assembly::riscv::PseudoVFREDMIN_VS_M8_E64_MASK = 2964 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_MF2_E16 = 2965 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_MF2_E16_MASK = 2966 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_MF2_E32 = 2967 ,
  LIEF::assembly::riscv::PseudoVFREDMIN_VS_MF2_E32_MASK = 2968 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_MF4_E16 = 2969 , LIEF::assembly::riscv::PseudoVFREDMIN_VS_MF4_E16_MASK = 2970 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M1_E16 = 2971 ,
  LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M1_E16_MASK = 2972 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M1_E32 = 2973 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M1_E32_MASK = 2974 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M1_E64 = 2975 ,
  LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M1_E64_MASK = 2976 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M2_E16 = 2977 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M2_E16_MASK = 2978 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M2_E32 = 2979 ,
  LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M2_E32_MASK = 2980 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M2_E64 = 2981 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M2_E64_MASK = 2982 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M4_E16 = 2983 ,
  LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M4_E16_MASK = 2984 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M4_E32 = 2985 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M4_E32_MASK = 2986 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M4_E64 = 2987 ,
  LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M4_E64_MASK = 2988 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M8_E16 = 2989 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M8_E16_MASK = 2990 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M8_E32 = 2991 ,
  LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M8_E32_MASK = 2992 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M8_E64 = 2993 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_M8_E64_MASK = 2994 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_MF2_E16 = 2995 ,
  LIEF::assembly::riscv::PseudoVFREDOSUM_VS_MF2_E16_MASK = 2996 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_MF2_E32 = 2997 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_MF2_E32_MASK = 2998 , LIEF::assembly::riscv::PseudoVFREDOSUM_VS_MF4_E16 = 2999 ,
  LIEF::assembly::riscv::PseudoVFREDOSUM_VS_MF4_E16_MASK = 3000 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M1_E16 = 3001 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M1_E16_MASK = 3002 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M1_E32 = 3003 ,
  LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M1_E32_MASK = 3004 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M1_E64 = 3005 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M1_E64_MASK = 3006 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M2_E16 = 3007 ,
  LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M2_E16_MASK = 3008 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M2_E32 = 3009 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M2_E32_MASK = 3010 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M2_E64 = 3011 ,
  LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M2_E64_MASK = 3012 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M4_E16 = 3013 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M4_E16_MASK = 3014 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M4_E32 = 3015 ,
  LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M4_E32_MASK = 3016 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M4_E64 = 3017 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M4_E64_MASK = 3018 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M8_E16 = 3019 ,
  LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M8_E16_MASK = 3020 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M8_E32 = 3021 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M8_E32_MASK = 3022 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M8_E64 = 3023 ,
  LIEF::assembly::riscv::PseudoVFREDUSUM_VS_M8_E64_MASK = 3024 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_MF2_E16 = 3025 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_MF2_E16_MASK = 3026 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_MF2_E32 = 3027 ,
  LIEF::assembly::riscv::PseudoVFREDUSUM_VS_MF2_E32_MASK = 3028 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_MF4_E16 = 3029 , LIEF::assembly::riscv::PseudoVFREDUSUM_VS_MF4_E16_MASK = 3030 , LIEF::assembly::riscv::PseudoVFROUND_NOEXCEPT_V_M1_MASK = 3031 ,
  LIEF::assembly::riscv::PseudoVFROUND_NOEXCEPT_V_M2_MASK = 3032 , LIEF::assembly::riscv::PseudoVFROUND_NOEXCEPT_V_M4_MASK = 3033 , LIEF::assembly::riscv::PseudoVFROUND_NOEXCEPT_V_M8_MASK = 3034 , LIEF::assembly::riscv::PseudoVFROUND_NOEXCEPT_V_MF2_MASK = 3035 ,
  LIEF::assembly::riscv::PseudoVFROUND_NOEXCEPT_V_MF4_MASK = 3036 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M1_E16 = 3037 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M1_E16_MASK = 3038 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M1_E32 = 3039 ,
  LIEF::assembly::riscv::PseudoVFRSQRT7_V_M1_E32_MASK = 3040 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M1_E64 = 3041 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M1_E64_MASK = 3042 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M2_E16 = 3043 ,
  LIEF::assembly::riscv::PseudoVFRSQRT7_V_M2_E16_MASK = 3044 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M2_E32 = 3045 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M2_E32_MASK = 3046 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M2_E64 = 3047 ,
  LIEF::assembly::riscv::PseudoVFRSQRT7_V_M2_E64_MASK = 3048 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M4_E16 = 3049 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M4_E16_MASK = 3050 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M4_E32 = 3051 ,
  LIEF::assembly::riscv::PseudoVFRSQRT7_V_M4_E32_MASK = 3052 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M4_E64 = 3053 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M4_E64_MASK = 3054 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M8_E16 = 3055 ,
  LIEF::assembly::riscv::PseudoVFRSQRT7_V_M8_E16_MASK = 3056 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M8_E32 = 3057 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M8_E32_MASK = 3058 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_M8_E64 = 3059 ,
  LIEF::assembly::riscv::PseudoVFRSQRT7_V_M8_E64_MASK = 3060 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_MF2_E16 = 3061 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_MF2_E16_MASK = 3062 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_MF2_E32 = 3063 ,
  LIEF::assembly::riscv::PseudoVFRSQRT7_V_MF2_E32_MASK = 3064 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_MF4_E16 = 3065 , LIEF::assembly::riscv::PseudoVFRSQRT7_V_MF4_E16_MASK = 3066 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_M1_E16 = 3067 ,
  LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_M1_E16_MASK = 3068 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_M2_E16 = 3069 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_M2_E16_MASK = 3070 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_M4_E16 = 3071 ,
  LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_M4_E16_MASK = 3072 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_M8_E16 = 3073 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_M8_E16_MASK = 3074 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_MF2_E16 = 3075 ,
  LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_MF2_E16_MASK = 3076 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_MF4_E16 = 3077 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR16_MF4_E16_MASK = 3078 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR32_M1_E32 = 3079 ,
  LIEF::assembly::riscv::PseudoVFRSUB_VFPR32_M1_E32_MASK = 3080 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR32_M2_E32 = 3081 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR32_M2_E32_MASK = 3082 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR32_M4_E32 = 3083 ,
  LIEF::assembly::riscv::PseudoVFRSUB_VFPR32_M4_E32_MASK = 3084 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR32_M8_E32 = 3085 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR32_M8_E32_MASK = 3086 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR32_MF2_E32 = 3087 ,
  LIEF::assembly::riscv::PseudoVFRSUB_VFPR32_MF2_E32_MASK = 3088 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR64_M1_E64 = 3089 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR64_M1_E64_MASK = 3090 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR64_M2_E64 = 3091 ,
  LIEF::assembly::riscv::PseudoVFRSUB_VFPR64_M2_E64_MASK = 3092 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR64_M4_E64 = 3093 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR64_M4_E64_MASK = 3094 , LIEF::assembly::riscv::PseudoVFRSUB_VFPR64_M8_E64 = 3095 ,
  LIEF::assembly::riscv::PseudoVFRSUB_VFPR64_M8_E64_MASK = 3096 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_M1_E16 = 3097 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_M1_E16_MASK = 3098 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_M2_E16 = 3099 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_M2_E16_MASK = 3100 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_M4_E16 = 3101 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_M4_E16_MASK = 3102 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_M8_E16 = 3103 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_M8_E16_MASK = 3104 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_MF2_E16 = 3105 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_MF2_E16_MASK = 3106 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_MF4_E16 = 3107 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VFPR16_MF4_E16_MASK = 3108 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR32_M1_E32 = 3109 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR32_M1_E32_MASK = 3110 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR32_M2_E32 = 3111 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VFPR32_M2_E32_MASK = 3112 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR32_M4_E32 = 3113 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR32_M4_E32_MASK = 3114 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR32_M8_E32 = 3115 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VFPR32_M8_E32_MASK = 3116 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR32_MF2_E32 = 3117 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR32_MF2_E32_MASK = 3118 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR64_M1_E64 = 3119 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VFPR64_M1_E64_MASK = 3120 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR64_M2_E64 = 3121 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR64_M2_E64_MASK = 3122 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR64_M4_E64 = 3123 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VFPR64_M4_E64_MASK = 3124 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR64_M8_E64 = 3125 , LIEF::assembly::riscv::PseudoVFSGNJN_VFPR64_M8_E64_MASK = 3126 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M1_E16 = 3127 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VV_M1_E16_MASK = 3128 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M1_E32 = 3129 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M1_E32_MASK = 3130 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M1_E64 = 3131 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VV_M1_E64_MASK = 3132 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M2_E16 = 3133 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M2_E16_MASK = 3134 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M2_E32 = 3135 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VV_M2_E32_MASK = 3136 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M2_E64 = 3137 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M2_E64_MASK = 3138 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M4_E16 = 3139 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VV_M4_E16_MASK = 3140 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M4_E32 = 3141 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M4_E32_MASK = 3142 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M4_E64 = 3143 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VV_M4_E64_MASK = 3144 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M8_E16 = 3145 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M8_E16_MASK = 3146 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M8_E32 = 3147 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VV_M8_E32_MASK = 3148 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M8_E64 = 3149 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_M8_E64_MASK = 3150 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_MF2_E16 = 3151 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VV_MF2_E16_MASK = 3152 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_MF2_E32 = 3153 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_MF2_E32_MASK = 3154 , LIEF::assembly::riscv::PseudoVFSGNJN_VV_MF4_E16 = 3155 ,
  LIEF::assembly::riscv::PseudoVFSGNJN_VV_MF4_E16_MASK = 3156 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_M1_E16 = 3157 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_M1_E16_MASK = 3158 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_M2_E16 = 3159 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_M2_E16_MASK = 3160 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_M4_E16 = 3161 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_M4_E16_MASK = 3162 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_M8_E16 = 3163 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_M8_E16_MASK = 3164 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_MF2_E16 = 3165 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_MF2_E16_MASK = 3166 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_MF4_E16 = 3167 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VFPR16_MF4_E16_MASK = 3168 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR32_M1_E32 = 3169 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR32_M1_E32_MASK = 3170 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR32_M2_E32 = 3171 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VFPR32_M2_E32_MASK = 3172 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR32_M4_E32 = 3173 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR32_M4_E32_MASK = 3174 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR32_M8_E32 = 3175 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VFPR32_M8_E32_MASK = 3176 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR32_MF2_E32 = 3177 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR32_MF2_E32_MASK = 3178 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR64_M1_E64 = 3179 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VFPR64_M1_E64_MASK = 3180 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR64_M2_E64 = 3181 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR64_M2_E64_MASK = 3182 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR64_M4_E64 = 3183 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VFPR64_M4_E64_MASK = 3184 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR64_M8_E64 = 3185 , LIEF::assembly::riscv::PseudoVFSGNJX_VFPR64_M8_E64_MASK = 3186 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M1_E16 = 3187 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VV_M1_E16_MASK = 3188 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M1_E32 = 3189 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M1_E32_MASK = 3190 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M1_E64 = 3191 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VV_M1_E64_MASK = 3192 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M2_E16 = 3193 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M2_E16_MASK = 3194 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M2_E32 = 3195 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VV_M2_E32_MASK = 3196 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M2_E64 = 3197 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M2_E64_MASK = 3198 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M4_E16 = 3199 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VV_M4_E16_MASK = 3200 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M4_E32 = 3201 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M4_E32_MASK = 3202 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M4_E64 = 3203 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VV_M4_E64_MASK = 3204 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M8_E16 = 3205 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M8_E16_MASK = 3206 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M8_E32 = 3207 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VV_M8_E32_MASK = 3208 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M8_E64 = 3209 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_M8_E64_MASK = 3210 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_MF2_E16 = 3211 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VV_MF2_E16_MASK = 3212 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_MF2_E32 = 3213 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_MF2_E32_MASK = 3214 , LIEF::assembly::riscv::PseudoVFSGNJX_VV_MF4_E16 = 3215 ,
  LIEF::assembly::riscv::PseudoVFSGNJX_VV_MF4_E16_MASK = 3216 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_M1_E16 = 3217 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_M1_E16_MASK = 3218 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_M2_E16 = 3219 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_M2_E16_MASK = 3220 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_M4_E16 = 3221 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_M4_E16_MASK = 3222 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_M8_E16 = 3223 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_M8_E16_MASK = 3224 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_MF2_E16 = 3225 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_MF2_E16_MASK = 3226 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_MF4_E16 = 3227 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VFPR16_MF4_E16_MASK = 3228 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR32_M1_E32 = 3229 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR32_M1_E32_MASK = 3230 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR32_M2_E32 = 3231 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VFPR32_M2_E32_MASK = 3232 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR32_M4_E32 = 3233 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR32_M4_E32_MASK = 3234 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR32_M8_E32 = 3235 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VFPR32_M8_E32_MASK = 3236 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR32_MF2_E32 = 3237 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR32_MF2_E32_MASK = 3238 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR64_M1_E64 = 3239 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VFPR64_M1_E64_MASK = 3240 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR64_M2_E64 = 3241 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR64_M2_E64_MASK = 3242 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR64_M4_E64 = 3243 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VFPR64_M4_E64_MASK = 3244 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR64_M8_E64 = 3245 , LIEF::assembly::riscv::PseudoVFSGNJ_VFPR64_M8_E64_MASK = 3246 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M1_E16 = 3247 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VV_M1_E16_MASK = 3248 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M1_E32 = 3249 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M1_E32_MASK = 3250 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M1_E64 = 3251 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VV_M1_E64_MASK = 3252 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M2_E16 = 3253 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M2_E16_MASK = 3254 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M2_E32 = 3255 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VV_M2_E32_MASK = 3256 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M2_E64 = 3257 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M2_E64_MASK = 3258 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M4_E16 = 3259 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VV_M4_E16_MASK = 3260 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M4_E32 = 3261 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M4_E32_MASK = 3262 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M4_E64 = 3263 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VV_M4_E64_MASK = 3264 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M8_E16 = 3265 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M8_E16_MASK = 3266 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M8_E32 = 3267 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VV_M8_E32_MASK = 3268 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M8_E64 = 3269 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_M8_E64_MASK = 3270 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_MF2_E16 = 3271 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VV_MF2_E16_MASK = 3272 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_MF2_E32 = 3273 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_MF2_E32_MASK = 3274 , LIEF::assembly::riscv::PseudoVFSGNJ_VV_MF4_E16 = 3275 ,
  LIEF::assembly::riscv::PseudoVFSGNJ_VV_MF4_E16_MASK = 3276 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_M1 = 3277 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_M1_MASK = 3278 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_M2 = 3279 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_M2_MASK = 3280 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_M4 = 3281 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_M4_MASK = 3282 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_M8 = 3283 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_M8_MASK = 3284 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_MF2 = 3285 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK = 3286 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_MF4 = 3287 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK = 3288 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR32_M1 = 3289 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR32_M1_MASK = 3290 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR32_M2 = 3291 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR32_M2_MASK = 3292 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR32_M4 = 3293 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR32_M4_MASK = 3294 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR32_M8 = 3295 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR32_M8_MASK = 3296 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR32_MF2 = 3297 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK = 3298 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR64_M1 = 3299 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR64_M1_MASK = 3300 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR64_M2 = 3301 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR64_M2_MASK = 3302 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR64_M4 = 3303 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR64_M4_MASK = 3304 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR64_M8 = 3305 , LIEF::assembly::riscv::PseudoVFSLIDE1DOWN_VFPR64_M8_MASK = 3306 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_M1 = 3307 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_M1_MASK = 3308 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_M2 = 3309 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_M2_MASK = 3310 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_M4 = 3311 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_M4_MASK = 3312 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_M8 = 3313 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_M8_MASK = 3314 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_MF2 = 3315 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_MF2_MASK = 3316 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_MF4 = 3317 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR16_MF4_MASK = 3318 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR32_M1 = 3319 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR32_M1_MASK = 3320 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR32_M2 = 3321 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR32_M2_MASK = 3322 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR32_M4 = 3323 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR32_M4_MASK = 3324 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR32_M8 = 3325 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR32_M8_MASK = 3326 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR32_MF2 = 3327 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR32_MF2_MASK = 3328 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR64_M1 = 3329 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR64_M1_MASK = 3330 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR64_M2 = 3331 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR64_M2_MASK = 3332 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR64_M4 = 3333 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR64_M4_MASK = 3334 , LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR64_M8 = 3335 ,
  LIEF::assembly::riscv::PseudoVFSLIDE1UP_VFPR64_M8_MASK = 3336 , LIEF::assembly::riscv::PseudoVFSQRT_V_M1_E16 = 3337 , LIEF::assembly::riscv::PseudoVFSQRT_V_M1_E16_MASK = 3338 , LIEF::assembly::riscv::PseudoVFSQRT_V_M1_E32 = 3339 ,
  LIEF::assembly::riscv::PseudoVFSQRT_V_M1_E32_MASK = 3340 , LIEF::assembly::riscv::PseudoVFSQRT_V_M1_E64 = 3341 , LIEF::assembly::riscv::PseudoVFSQRT_V_M1_E64_MASK = 3342 , LIEF::assembly::riscv::PseudoVFSQRT_V_M2_E16 = 3343 ,
  LIEF::assembly::riscv::PseudoVFSQRT_V_M2_E16_MASK = 3344 , LIEF::assembly::riscv::PseudoVFSQRT_V_M2_E32 = 3345 , LIEF::assembly::riscv::PseudoVFSQRT_V_M2_E32_MASK = 3346 , LIEF::assembly::riscv::PseudoVFSQRT_V_M2_E64 = 3347 ,
  LIEF::assembly::riscv::PseudoVFSQRT_V_M2_E64_MASK = 3348 , LIEF::assembly::riscv::PseudoVFSQRT_V_M4_E16 = 3349 , LIEF::assembly::riscv::PseudoVFSQRT_V_M4_E16_MASK = 3350 , LIEF::assembly::riscv::PseudoVFSQRT_V_M4_E32 = 3351 ,
  LIEF::assembly::riscv::PseudoVFSQRT_V_M4_E32_MASK = 3352 , LIEF::assembly::riscv::PseudoVFSQRT_V_M4_E64 = 3353 , LIEF::assembly::riscv::PseudoVFSQRT_V_M4_E64_MASK = 3354 , LIEF::assembly::riscv::PseudoVFSQRT_V_M8_E16 = 3355 ,
  LIEF::assembly::riscv::PseudoVFSQRT_V_M8_E16_MASK = 3356 , LIEF::assembly::riscv::PseudoVFSQRT_V_M8_E32 = 3357 , LIEF::assembly::riscv::PseudoVFSQRT_V_M8_E32_MASK = 3358 , LIEF::assembly::riscv::PseudoVFSQRT_V_M8_E64 = 3359 ,
  LIEF::assembly::riscv::PseudoVFSQRT_V_M8_E64_MASK = 3360 , LIEF::assembly::riscv::PseudoVFSQRT_V_MF2_E16 = 3361 , LIEF::assembly::riscv::PseudoVFSQRT_V_MF2_E16_MASK = 3362 , LIEF::assembly::riscv::PseudoVFSQRT_V_MF2_E32 = 3363 ,
  LIEF::assembly::riscv::PseudoVFSQRT_V_MF2_E32_MASK = 3364 , LIEF::assembly::riscv::PseudoVFSQRT_V_MF4_E16 = 3365 , LIEF::assembly::riscv::PseudoVFSQRT_V_MF4_E16_MASK = 3366 , LIEF::assembly::riscv::PseudoVFSUB_VFPR16_M1_E16 = 3367 ,
  LIEF::assembly::riscv::PseudoVFSUB_VFPR16_M1_E16_MASK = 3368 , LIEF::assembly::riscv::PseudoVFSUB_VFPR16_M2_E16 = 3369 , LIEF::assembly::riscv::PseudoVFSUB_VFPR16_M2_E16_MASK = 3370 , LIEF::assembly::riscv::PseudoVFSUB_VFPR16_M4_E16 = 3371 ,
  LIEF::assembly::riscv::PseudoVFSUB_VFPR16_M4_E16_MASK = 3372 , LIEF::assembly::riscv::PseudoVFSUB_VFPR16_M8_E16 = 3373 , LIEF::assembly::riscv::PseudoVFSUB_VFPR16_M8_E16_MASK = 3374 , LIEF::assembly::riscv::PseudoVFSUB_VFPR16_MF2_E16 = 3375 ,
  LIEF::assembly::riscv::PseudoVFSUB_VFPR16_MF2_E16_MASK = 3376 , LIEF::assembly::riscv::PseudoVFSUB_VFPR16_MF4_E16 = 3377 , LIEF::assembly::riscv::PseudoVFSUB_VFPR16_MF4_E16_MASK = 3378 , LIEF::assembly::riscv::PseudoVFSUB_VFPR32_M1_E32 = 3379 ,
  LIEF::assembly::riscv::PseudoVFSUB_VFPR32_M1_E32_MASK = 3380 , LIEF::assembly::riscv::PseudoVFSUB_VFPR32_M2_E32 = 3381 , LIEF::assembly::riscv::PseudoVFSUB_VFPR32_M2_E32_MASK = 3382 , LIEF::assembly::riscv::PseudoVFSUB_VFPR32_M4_E32 = 3383 ,
  LIEF::assembly::riscv::PseudoVFSUB_VFPR32_M4_E32_MASK = 3384 , LIEF::assembly::riscv::PseudoVFSUB_VFPR32_M8_E32 = 3385 , LIEF::assembly::riscv::PseudoVFSUB_VFPR32_M8_E32_MASK = 3386 , LIEF::assembly::riscv::PseudoVFSUB_VFPR32_MF2_E32 = 3387 ,
  LIEF::assembly::riscv::PseudoVFSUB_VFPR32_MF2_E32_MASK = 3388 , LIEF::assembly::riscv::PseudoVFSUB_VFPR64_M1_E64 = 3389 , LIEF::assembly::riscv::PseudoVFSUB_VFPR64_M1_E64_MASK = 3390 , LIEF::assembly::riscv::PseudoVFSUB_VFPR64_M2_E64 = 3391 ,
  LIEF::assembly::riscv::PseudoVFSUB_VFPR64_M2_E64_MASK = 3392 , LIEF::assembly::riscv::PseudoVFSUB_VFPR64_M4_E64 = 3393 , LIEF::assembly::riscv::PseudoVFSUB_VFPR64_M4_E64_MASK = 3394 , LIEF::assembly::riscv::PseudoVFSUB_VFPR64_M8_E64 = 3395 ,
  LIEF::assembly::riscv::PseudoVFSUB_VFPR64_M8_E64_MASK = 3396 , LIEF::assembly::riscv::PseudoVFSUB_VV_M1_E16 = 3397 , LIEF::assembly::riscv::PseudoVFSUB_VV_M1_E16_MASK = 3398 , LIEF::assembly::riscv::PseudoVFSUB_VV_M1_E32 = 3399 ,
  LIEF::assembly::riscv::PseudoVFSUB_VV_M1_E32_MASK = 3400 , LIEF::assembly::riscv::PseudoVFSUB_VV_M1_E64 = 3401 , LIEF::assembly::riscv::PseudoVFSUB_VV_M1_E64_MASK = 3402 , LIEF::assembly::riscv::PseudoVFSUB_VV_M2_E16 = 3403 ,
  LIEF::assembly::riscv::PseudoVFSUB_VV_M2_E16_MASK = 3404 , LIEF::assembly::riscv::PseudoVFSUB_VV_M2_E32 = 3405 , LIEF::assembly::riscv::PseudoVFSUB_VV_M2_E32_MASK = 3406 , LIEF::assembly::riscv::PseudoVFSUB_VV_M2_E64 = 3407 ,
  LIEF::assembly::riscv::PseudoVFSUB_VV_M2_E64_MASK = 3408 , LIEF::assembly::riscv::PseudoVFSUB_VV_M4_E16 = 3409 , LIEF::assembly::riscv::PseudoVFSUB_VV_M4_E16_MASK = 3410 , LIEF::assembly::riscv::PseudoVFSUB_VV_M4_E32 = 3411 ,
  LIEF::assembly::riscv::PseudoVFSUB_VV_M4_E32_MASK = 3412 , LIEF::assembly::riscv::PseudoVFSUB_VV_M4_E64 = 3413 , LIEF::assembly::riscv::PseudoVFSUB_VV_M4_E64_MASK = 3414 , LIEF::assembly::riscv::PseudoVFSUB_VV_M8_E16 = 3415 ,
  LIEF::assembly::riscv::PseudoVFSUB_VV_M8_E16_MASK = 3416 , LIEF::assembly::riscv::PseudoVFSUB_VV_M8_E32 = 3417 , LIEF::assembly::riscv::PseudoVFSUB_VV_M8_E32_MASK = 3418 , LIEF::assembly::riscv::PseudoVFSUB_VV_M8_E64 = 3419 ,
  LIEF::assembly::riscv::PseudoVFSUB_VV_M8_E64_MASK = 3420 , LIEF::assembly::riscv::PseudoVFSUB_VV_MF2_E16 = 3421 , LIEF::assembly::riscv::PseudoVFSUB_VV_MF2_E16_MASK = 3422 , LIEF::assembly::riscv::PseudoVFSUB_VV_MF2_E32 = 3423 ,
  LIEF::assembly::riscv::PseudoVFSUB_VV_MF2_E32_MASK = 3424 , LIEF::assembly::riscv::PseudoVFSUB_VV_MF4_E16 = 3425 , LIEF::assembly::riscv::PseudoVFSUB_VV_MF4_E16_MASK = 3426 , LIEF::assembly::riscv::PseudoVFWADD_VFPR16_M1_E16 = 3427 ,
  LIEF::assembly::riscv::PseudoVFWADD_VFPR16_M1_E16_MASK = 3428 , LIEF::assembly::riscv::PseudoVFWADD_VFPR16_M2_E16 = 3429 , LIEF::assembly::riscv::PseudoVFWADD_VFPR16_M2_E16_MASK = 3430 , LIEF::assembly::riscv::PseudoVFWADD_VFPR16_M4_E16 = 3431 ,
  LIEF::assembly::riscv::PseudoVFWADD_VFPR16_M4_E16_MASK = 3432 , LIEF::assembly::riscv::PseudoVFWADD_VFPR16_MF2_E16 = 3433 , LIEF::assembly::riscv::PseudoVFWADD_VFPR16_MF2_E16_MASK = 3434 , LIEF::assembly::riscv::PseudoVFWADD_VFPR16_MF4_E16 = 3435 ,
  LIEF::assembly::riscv::PseudoVFWADD_VFPR16_MF4_E16_MASK = 3436 , LIEF::assembly::riscv::PseudoVFWADD_VFPR32_M1_E32 = 3437 , LIEF::assembly::riscv::PseudoVFWADD_VFPR32_M1_E32_MASK = 3438 , LIEF::assembly::riscv::PseudoVFWADD_VFPR32_M2_E32 = 3439 ,
  LIEF::assembly::riscv::PseudoVFWADD_VFPR32_M2_E32_MASK = 3440 , LIEF::assembly::riscv::PseudoVFWADD_VFPR32_M4_E32 = 3441 , LIEF::assembly::riscv::PseudoVFWADD_VFPR32_M4_E32_MASK = 3442 , LIEF::assembly::riscv::PseudoVFWADD_VFPR32_MF2_E32 = 3443 ,
  LIEF::assembly::riscv::PseudoVFWADD_VFPR32_MF2_E32_MASK = 3444 , LIEF::assembly::riscv::PseudoVFWADD_VV_M1_E16 = 3445 , LIEF::assembly::riscv::PseudoVFWADD_VV_M1_E16_MASK = 3446 , LIEF::assembly::riscv::PseudoVFWADD_VV_M1_E32 = 3447 ,
  LIEF::assembly::riscv::PseudoVFWADD_VV_M1_E32_MASK = 3448 , LIEF::assembly::riscv::PseudoVFWADD_VV_M2_E16 = 3449 , LIEF::assembly::riscv::PseudoVFWADD_VV_M2_E16_MASK = 3450 , LIEF::assembly::riscv::PseudoVFWADD_VV_M2_E32 = 3451 ,
  LIEF::assembly::riscv::PseudoVFWADD_VV_M2_E32_MASK = 3452 , LIEF::assembly::riscv::PseudoVFWADD_VV_M4_E16 = 3453 , LIEF::assembly::riscv::PseudoVFWADD_VV_M4_E16_MASK = 3454 , LIEF::assembly::riscv::PseudoVFWADD_VV_M4_E32 = 3455 ,
  LIEF::assembly::riscv::PseudoVFWADD_VV_M4_E32_MASK = 3456 , LIEF::assembly::riscv::PseudoVFWADD_VV_MF2_E16 = 3457 , LIEF::assembly::riscv::PseudoVFWADD_VV_MF2_E16_MASK = 3458 , LIEF::assembly::riscv::PseudoVFWADD_VV_MF2_E32 = 3459 ,
  LIEF::assembly::riscv::PseudoVFWADD_VV_MF2_E32_MASK = 3460 , LIEF::assembly::riscv::PseudoVFWADD_VV_MF4_E16 = 3461 , LIEF::assembly::riscv::PseudoVFWADD_VV_MF4_E16_MASK = 3462 , LIEF::assembly::riscv::PseudoVFWADD_WFPR16_M1_E16 = 3463 ,
  LIEF::assembly::riscv::PseudoVFWADD_WFPR16_M1_E16_MASK = 3464 , LIEF::assembly::riscv::PseudoVFWADD_WFPR16_M2_E16 = 3465 , LIEF::assembly::riscv::PseudoVFWADD_WFPR16_M2_E16_MASK = 3466 , LIEF::assembly::riscv::PseudoVFWADD_WFPR16_M4_E16 = 3467 ,
  LIEF::assembly::riscv::PseudoVFWADD_WFPR16_M4_E16_MASK = 3468 , LIEF::assembly::riscv::PseudoVFWADD_WFPR16_MF2_E16 = 3469 , LIEF::assembly::riscv::PseudoVFWADD_WFPR16_MF2_E16_MASK = 3470 , LIEF::assembly::riscv::PseudoVFWADD_WFPR16_MF4_E16 = 3471 ,
  LIEF::assembly::riscv::PseudoVFWADD_WFPR16_MF4_E16_MASK = 3472 , LIEF::assembly::riscv::PseudoVFWADD_WFPR32_M1_E32 = 3473 , LIEF::assembly::riscv::PseudoVFWADD_WFPR32_M1_E32_MASK = 3474 , LIEF::assembly::riscv::PseudoVFWADD_WFPR32_M2_E32 = 3475 ,
  LIEF::assembly::riscv::PseudoVFWADD_WFPR32_M2_E32_MASK = 3476 , LIEF::assembly::riscv::PseudoVFWADD_WFPR32_M4_E32 = 3477 , LIEF::assembly::riscv::PseudoVFWADD_WFPR32_M4_E32_MASK = 3478 , LIEF::assembly::riscv::PseudoVFWADD_WFPR32_MF2_E32 = 3479 ,
  LIEF::assembly::riscv::PseudoVFWADD_WFPR32_MF2_E32_MASK = 3480 , LIEF::assembly::riscv::PseudoVFWADD_WV_M1_E16 = 3481 , LIEF::assembly::riscv::PseudoVFWADD_WV_M1_E16_MASK = 3482 , LIEF::assembly::riscv::PseudoVFWADD_WV_M1_E16_MASK_TIED = 3483 ,
  LIEF::assembly::riscv::PseudoVFWADD_WV_M1_E16_TIED = 3484 , LIEF::assembly::riscv::PseudoVFWADD_WV_M1_E32 = 3485 , LIEF::assembly::riscv::PseudoVFWADD_WV_M1_E32_MASK = 3486 , LIEF::assembly::riscv::PseudoVFWADD_WV_M1_E32_MASK_TIED = 3487 ,
  LIEF::assembly::riscv::PseudoVFWADD_WV_M1_E32_TIED = 3488 , LIEF::assembly::riscv::PseudoVFWADD_WV_M2_E16 = 3489 , LIEF::assembly::riscv::PseudoVFWADD_WV_M2_E16_MASK = 3490 , LIEF::assembly::riscv::PseudoVFWADD_WV_M2_E16_MASK_TIED = 3491 ,
  LIEF::assembly::riscv::PseudoVFWADD_WV_M2_E16_TIED = 3492 , LIEF::assembly::riscv::PseudoVFWADD_WV_M2_E32 = 3493 , LIEF::assembly::riscv::PseudoVFWADD_WV_M2_E32_MASK = 3494 , LIEF::assembly::riscv::PseudoVFWADD_WV_M2_E32_MASK_TIED = 3495 ,
  LIEF::assembly::riscv::PseudoVFWADD_WV_M2_E32_TIED = 3496 , LIEF::assembly::riscv::PseudoVFWADD_WV_M4_E16 = 3497 , LIEF::assembly::riscv::PseudoVFWADD_WV_M4_E16_MASK = 3498 , LIEF::assembly::riscv::PseudoVFWADD_WV_M4_E16_MASK_TIED = 3499 ,
  LIEF::assembly::riscv::PseudoVFWADD_WV_M4_E16_TIED = 3500 , LIEF::assembly::riscv::PseudoVFWADD_WV_M4_E32 = 3501 , LIEF::assembly::riscv::PseudoVFWADD_WV_M4_E32_MASK = 3502 , LIEF::assembly::riscv::PseudoVFWADD_WV_M4_E32_MASK_TIED = 3503 ,
  LIEF::assembly::riscv::PseudoVFWADD_WV_M4_E32_TIED = 3504 , LIEF::assembly::riscv::PseudoVFWADD_WV_MF2_E16 = 3505 , LIEF::assembly::riscv::PseudoVFWADD_WV_MF2_E16_MASK = 3506 , LIEF::assembly::riscv::PseudoVFWADD_WV_MF2_E16_MASK_TIED = 3507 ,
  LIEF::assembly::riscv::PseudoVFWADD_WV_MF2_E16_TIED = 3508 , LIEF::assembly::riscv::PseudoVFWADD_WV_MF2_E32 = 3509 , LIEF::assembly::riscv::PseudoVFWADD_WV_MF2_E32_MASK = 3510 , LIEF::assembly::riscv::PseudoVFWADD_WV_MF2_E32_MASK_TIED = 3511 ,
  LIEF::assembly::riscv::PseudoVFWADD_WV_MF2_E32_TIED = 3512 , LIEF::assembly::riscv::PseudoVFWADD_WV_MF4_E16 = 3513 , LIEF::assembly::riscv::PseudoVFWADD_WV_MF4_E16_MASK = 3514 , LIEF::assembly::riscv::PseudoVFWADD_WV_MF4_E16_MASK_TIED = 3515 ,
  LIEF::assembly::riscv::PseudoVFWADD_WV_MF4_E16_TIED = 3516 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M1_E16 = 3517 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M1_E16_MASK = 3518 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M1_E32 = 3519 ,
  LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M1_E32_MASK = 3520 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M2_E16 = 3521 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M2_E16_MASK = 3522 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M2_E32 = 3523 ,
  LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M2_E32_MASK = 3524 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M4_E16 = 3525 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M4_E16_MASK = 3526 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M4_E32 = 3527 ,
  LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_M4_E32_MASK = 3528 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_MF2_E16 = 3529 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK = 3530 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_MF2_E32 = 3531 ,
  LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK = 3532 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_MF4_E16 = 3533 , LIEF::assembly::riscv::PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK = 3534 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M1_E16 = 3535 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M1_E16_MASK = 3536 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M1_E32 = 3537 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M1_E32_MASK = 3538 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M2_E16 = 3539 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M2_E16_MASK = 3540 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M2_E32 = 3541 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M2_E32_MASK = 3542 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M4_E16 = 3543 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M4_E16_MASK = 3544 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M4_E32 = 3545 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_M4_E32_MASK = 3546 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_MF2_E16 = 3547 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_MF2_E16_MASK = 3548 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_MF2_E32 = 3549 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_MF2_E32_MASK = 3550 , LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_MF4_E16 = 3551 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_F_V_MF4_E16_MASK = 3552 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M1_E16 = 3553 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M1_E16_MASK = 3554 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M1_E32 = 3555 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M1_E32_MASK = 3556 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M1_E8 = 3557 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M1_E8_MASK = 3558 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M2_E16 = 3559 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M2_E16_MASK = 3560 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M2_E32 = 3561 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M2_E32_MASK = 3562 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M2_E8 = 3563 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M2_E8_MASK = 3564 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M4_E16 = 3565 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M4_E16_MASK = 3566 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M4_E32 = 3567 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M4_E32_MASK = 3568 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M4_E8 = 3569 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_M4_E8_MASK = 3570 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF2_E16 = 3571 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF2_E16_MASK = 3572 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF2_E32 = 3573 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF2_E32_MASK = 3574 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF2_E8 = 3575 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF2_E8_MASK = 3576 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF4_E16 = 3577 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF4_E16_MASK = 3578 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF4_E8 = 3579 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF4_E8_MASK = 3580 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF8_E8 = 3581 , LIEF::assembly::riscv::PseudoVFWCVT_F_XU_V_MF8_E8_MASK = 3582 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M1_E16 = 3583 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M1_E16_MASK = 3584 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M1_E32 = 3585 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M1_E32_MASK = 3586 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M1_E8 = 3587 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M1_E8_MASK = 3588 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M2_E16 = 3589 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M2_E16_MASK = 3590 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M2_E32 = 3591 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M2_E32_MASK = 3592 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M2_E8 = 3593 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M2_E8_MASK = 3594 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M4_E16 = 3595 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M4_E16_MASK = 3596 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M4_E32 = 3597 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M4_E32_MASK = 3598 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M4_E8 = 3599 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_M4_E8_MASK = 3600 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF2_E16 = 3601 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF2_E16_MASK = 3602 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF2_E32 = 3603 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF2_E32_MASK = 3604 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF2_E8 = 3605 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF2_E8_MASK = 3606 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF4_E16 = 3607 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF4_E16_MASK = 3608 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF4_E8 = 3609 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF4_E8_MASK = 3610 , LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF8_E8 = 3611 ,
  LIEF::assembly::riscv::PseudoVFWCVT_F_X_V_MF8_E8_MASK = 3612 , LIEF::assembly::riscv::PseudoVFWCVT_RM_XU_F_V_M1 = 3613 , LIEF::assembly::riscv::PseudoVFWCVT_RM_XU_F_V_M1_MASK = 3614 , LIEF::assembly::riscv::PseudoVFWCVT_RM_XU_F_V_M2 = 3615 ,
  LIEF::assembly::riscv::PseudoVFWCVT_RM_XU_F_V_M2_MASK = 3616 , LIEF::assembly::riscv::PseudoVFWCVT_RM_XU_F_V_M4 = 3617 , LIEF::assembly::riscv::PseudoVFWCVT_RM_XU_F_V_M4_MASK = 3618 , LIEF::assembly::riscv::PseudoVFWCVT_RM_XU_F_V_MF2 = 3619 ,
  LIEF::assembly::riscv::PseudoVFWCVT_RM_XU_F_V_MF2_MASK = 3620 , LIEF::assembly::riscv::PseudoVFWCVT_RM_XU_F_V_MF4 = 3621 , LIEF::assembly::riscv::PseudoVFWCVT_RM_XU_F_V_MF4_MASK = 3622 , LIEF::assembly::riscv::PseudoVFWCVT_RM_X_F_V_M1 = 3623 ,
  LIEF::assembly::riscv::PseudoVFWCVT_RM_X_F_V_M1_MASK = 3624 , LIEF::assembly::riscv::PseudoVFWCVT_RM_X_F_V_M2 = 3625 , LIEF::assembly::riscv::PseudoVFWCVT_RM_X_F_V_M2_MASK = 3626 , LIEF::assembly::riscv::PseudoVFWCVT_RM_X_F_V_M4 = 3627 ,
  LIEF::assembly::riscv::PseudoVFWCVT_RM_X_F_V_M4_MASK = 3628 , LIEF::assembly::riscv::PseudoVFWCVT_RM_X_F_V_MF2 = 3629 , LIEF::assembly::riscv::PseudoVFWCVT_RM_X_F_V_MF2_MASK = 3630 , LIEF::assembly::riscv::PseudoVFWCVT_RM_X_F_V_MF4 = 3631 ,
  LIEF::assembly::riscv::PseudoVFWCVT_RM_X_F_V_MF4_MASK = 3632 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_XU_F_V_M1 = 3633 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_XU_F_V_M1_MASK = 3634 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_XU_F_V_M2 = 3635 ,
  LIEF::assembly::riscv::PseudoVFWCVT_RTZ_XU_F_V_M2_MASK = 3636 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_XU_F_V_M4 = 3637 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_XU_F_V_M4_MASK = 3638 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_XU_F_V_MF2 = 3639 ,
  LIEF::assembly::riscv::PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK = 3640 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_XU_F_V_MF4 = 3641 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK = 3642 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_X_F_V_M1 = 3643 ,
  LIEF::assembly::riscv::PseudoVFWCVT_RTZ_X_F_V_M1_MASK = 3644 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_X_F_V_M2 = 3645 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_X_F_V_M2_MASK = 3646 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_X_F_V_M4 = 3647 ,
  LIEF::assembly::riscv::PseudoVFWCVT_RTZ_X_F_V_M4_MASK = 3648 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_X_F_V_MF2 = 3649 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_X_F_V_MF2_MASK = 3650 , LIEF::assembly::riscv::PseudoVFWCVT_RTZ_X_F_V_MF4 = 3651 ,
  LIEF::assembly::riscv::PseudoVFWCVT_RTZ_X_F_V_MF4_MASK = 3652 , LIEF::assembly::riscv::PseudoVFWCVT_XU_F_V_M1 = 3653 , LIEF::assembly::riscv::PseudoVFWCVT_XU_F_V_M1_MASK = 3654 , LIEF::assembly::riscv::PseudoVFWCVT_XU_F_V_M2 = 3655 ,
  LIEF::assembly::riscv::PseudoVFWCVT_XU_F_V_M2_MASK = 3656 , LIEF::assembly::riscv::PseudoVFWCVT_XU_F_V_M4 = 3657 , LIEF::assembly::riscv::PseudoVFWCVT_XU_F_V_M4_MASK = 3658 , LIEF::assembly::riscv::PseudoVFWCVT_XU_F_V_MF2 = 3659 ,
  LIEF::assembly::riscv::PseudoVFWCVT_XU_F_V_MF2_MASK = 3660 , LIEF::assembly::riscv::PseudoVFWCVT_XU_F_V_MF4 = 3661 , LIEF::assembly::riscv::PseudoVFWCVT_XU_F_V_MF4_MASK = 3662 , LIEF::assembly::riscv::PseudoVFWCVT_X_F_V_M1 = 3663 ,
  LIEF::assembly::riscv::PseudoVFWCVT_X_F_V_M1_MASK = 3664 , LIEF::assembly::riscv::PseudoVFWCVT_X_F_V_M2 = 3665 , LIEF::assembly::riscv::PseudoVFWCVT_X_F_V_M2_MASK = 3666 , LIEF::assembly::riscv::PseudoVFWCVT_X_F_V_M4 = 3667 ,
  LIEF::assembly::riscv::PseudoVFWCVT_X_F_V_M4_MASK = 3668 , LIEF::assembly::riscv::PseudoVFWCVT_X_F_V_MF2 = 3669 , LIEF::assembly::riscv::PseudoVFWCVT_X_F_V_MF2_MASK = 3670 , LIEF::assembly::riscv::PseudoVFWCVT_X_F_V_MF4 = 3671 ,
  LIEF::assembly::riscv::PseudoVFWCVT_X_F_V_MF4_MASK = 3672 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VFPR16_M1_E16 = 3673 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VFPR16_M1_E16_MASK = 3674 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VFPR16_M2_E16 = 3675 ,
  LIEF::assembly::riscv::PseudoVFWMACCBF16_VFPR16_M2_E16_MASK = 3676 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VFPR16_M4_E16 = 3677 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VFPR16_M4_E16_MASK = 3678 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VFPR16_MF2_E16 = 3679 ,
  LIEF::assembly::riscv::PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK = 3680 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VFPR16_MF4_E16 = 3681 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK = 3682 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M1_E16 = 3683 ,
  LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M1_E16_MASK = 3684 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M1_E32 = 3685 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M1_E32_MASK = 3686 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M2_E16 = 3687 ,
  LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M2_E16_MASK = 3688 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M2_E32 = 3689 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M2_E32_MASK = 3690 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M4_E16 = 3691 ,
  LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M4_E16_MASK = 3692 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M4_E32 = 3693 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_M4_E32_MASK = 3694 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_MF2_E16 = 3695 ,
  LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_MF2_E16_MASK = 3696 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_MF2_E32 = 3697 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_MF2_E32_MASK = 3698 , LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_MF4_E16 = 3699 ,
  LIEF::assembly::riscv::PseudoVFWMACCBF16_VV_MF4_E16_MASK = 3700 , LIEF::assembly::riscv::PseudoVFWMACC_4x4x4_M1 = 3701 , LIEF::assembly::riscv::PseudoVFWMACC_4x4x4_M2 = 3702 , LIEF::assembly::riscv::PseudoVFWMACC_4x4x4_M4 = 3703 ,
  LIEF::assembly::riscv::PseudoVFWMACC_4x4x4_M8 = 3704 , LIEF::assembly::riscv::PseudoVFWMACC_4x4x4_MF2 = 3705 , LIEF::assembly::riscv::PseudoVFWMACC_4x4x4_MF4 = 3706 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR16_M1_E16 = 3707 ,
  LIEF::assembly::riscv::PseudoVFWMACC_VFPR16_M1_E16_MASK = 3708 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR16_M2_E16 = 3709 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR16_M2_E16_MASK = 3710 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR16_M4_E16 = 3711 ,
  LIEF::assembly::riscv::PseudoVFWMACC_VFPR16_M4_E16_MASK = 3712 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR16_MF2_E16 = 3713 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR16_MF2_E16_MASK = 3714 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR16_MF4_E16 = 3715 ,
  LIEF::assembly::riscv::PseudoVFWMACC_VFPR16_MF4_E16_MASK = 3716 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR32_M1_E32 = 3717 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR32_M1_E32_MASK = 3718 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR32_M2_E32 = 3719 ,
  LIEF::assembly::riscv::PseudoVFWMACC_VFPR32_M2_E32_MASK = 3720 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR32_M4_E32 = 3721 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR32_M4_E32_MASK = 3722 , LIEF::assembly::riscv::PseudoVFWMACC_VFPR32_MF2_E32 = 3723 ,
  LIEF::assembly::riscv::PseudoVFWMACC_VFPR32_MF2_E32_MASK = 3724 , LIEF::assembly::riscv::PseudoVFWMACC_VV_M1_E16 = 3725 , LIEF::assembly::riscv::PseudoVFWMACC_VV_M1_E16_MASK = 3726 , LIEF::assembly::riscv::PseudoVFWMACC_VV_M1_E32 = 3727 ,
  LIEF::assembly::riscv::PseudoVFWMACC_VV_M1_E32_MASK = 3728 , LIEF::assembly::riscv::PseudoVFWMACC_VV_M2_E16 = 3729 , LIEF::assembly::riscv::PseudoVFWMACC_VV_M2_E16_MASK = 3730 , LIEF::assembly::riscv::PseudoVFWMACC_VV_M2_E32 = 3731 ,
  LIEF::assembly::riscv::PseudoVFWMACC_VV_M2_E32_MASK = 3732 , LIEF::assembly::riscv::PseudoVFWMACC_VV_M4_E16 = 3733 , LIEF::assembly::riscv::PseudoVFWMACC_VV_M4_E16_MASK = 3734 , LIEF::assembly::riscv::PseudoVFWMACC_VV_M4_E32 = 3735 ,
  LIEF::assembly::riscv::PseudoVFWMACC_VV_M4_E32_MASK = 3736 , LIEF::assembly::riscv::PseudoVFWMACC_VV_MF2_E16 = 3737 , LIEF::assembly::riscv::PseudoVFWMACC_VV_MF2_E16_MASK = 3738 , LIEF::assembly::riscv::PseudoVFWMACC_VV_MF2_E32 = 3739 ,
  LIEF::assembly::riscv::PseudoVFWMACC_VV_MF2_E32_MASK = 3740 , LIEF::assembly::riscv::PseudoVFWMACC_VV_MF4_E16 = 3741 , LIEF::assembly::riscv::PseudoVFWMACC_VV_MF4_E16_MASK = 3742 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR16_M1_E16 = 3743 ,
  LIEF::assembly::riscv::PseudoVFWMSAC_VFPR16_M1_E16_MASK = 3744 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR16_M2_E16 = 3745 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR16_M2_E16_MASK = 3746 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR16_M4_E16 = 3747 ,
  LIEF::assembly::riscv::PseudoVFWMSAC_VFPR16_M4_E16_MASK = 3748 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR16_MF2_E16 = 3749 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR16_MF2_E16_MASK = 3750 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR16_MF4_E16 = 3751 ,
  LIEF::assembly::riscv::PseudoVFWMSAC_VFPR16_MF4_E16_MASK = 3752 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR32_M1_E32 = 3753 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR32_M1_E32_MASK = 3754 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR32_M2_E32 = 3755 ,
  LIEF::assembly::riscv::PseudoVFWMSAC_VFPR32_M2_E32_MASK = 3756 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR32_M4_E32 = 3757 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR32_M4_E32_MASK = 3758 , LIEF::assembly::riscv::PseudoVFWMSAC_VFPR32_MF2_E32 = 3759 ,
  LIEF::assembly::riscv::PseudoVFWMSAC_VFPR32_MF2_E32_MASK = 3760 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_M1_E16 = 3761 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_M1_E16_MASK = 3762 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_M1_E32 = 3763 ,
  LIEF::assembly::riscv::PseudoVFWMSAC_VV_M1_E32_MASK = 3764 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_M2_E16 = 3765 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_M2_E16_MASK = 3766 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_M2_E32 = 3767 ,
  LIEF::assembly::riscv::PseudoVFWMSAC_VV_M2_E32_MASK = 3768 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_M4_E16 = 3769 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_M4_E16_MASK = 3770 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_M4_E32 = 3771 ,
  LIEF::assembly::riscv::PseudoVFWMSAC_VV_M4_E32_MASK = 3772 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_MF2_E16 = 3773 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_MF2_E16_MASK = 3774 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_MF2_E32 = 3775 ,
  LIEF::assembly::riscv::PseudoVFWMSAC_VV_MF2_E32_MASK = 3776 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_MF4_E16 = 3777 , LIEF::assembly::riscv::PseudoVFWMSAC_VV_MF4_E16_MASK = 3778 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR16_M1_E16 = 3779 ,
  LIEF::assembly::riscv::PseudoVFWMUL_VFPR16_M1_E16_MASK = 3780 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR16_M2_E16 = 3781 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR16_M2_E16_MASK = 3782 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR16_M4_E16 = 3783 ,
  LIEF::assembly::riscv::PseudoVFWMUL_VFPR16_M4_E16_MASK = 3784 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR16_MF2_E16 = 3785 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR16_MF2_E16_MASK = 3786 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR16_MF4_E16 = 3787 ,
  LIEF::assembly::riscv::PseudoVFWMUL_VFPR16_MF4_E16_MASK = 3788 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR32_M1_E32 = 3789 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR32_M1_E32_MASK = 3790 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR32_M2_E32 = 3791 ,
  LIEF::assembly::riscv::PseudoVFWMUL_VFPR32_M2_E32_MASK = 3792 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR32_M4_E32 = 3793 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR32_M4_E32_MASK = 3794 , LIEF::assembly::riscv::PseudoVFWMUL_VFPR32_MF2_E32 = 3795 ,
  LIEF::assembly::riscv::PseudoVFWMUL_VFPR32_MF2_E32_MASK = 3796 , LIEF::assembly::riscv::PseudoVFWMUL_VV_M1_E16 = 3797 , LIEF::assembly::riscv::PseudoVFWMUL_VV_M1_E16_MASK = 3798 , LIEF::assembly::riscv::PseudoVFWMUL_VV_M1_E32 = 3799 ,
  LIEF::assembly::riscv::PseudoVFWMUL_VV_M1_E32_MASK = 3800 , LIEF::assembly::riscv::PseudoVFWMUL_VV_M2_E16 = 3801 , LIEF::assembly::riscv::PseudoVFWMUL_VV_M2_E16_MASK = 3802 , LIEF::assembly::riscv::PseudoVFWMUL_VV_M2_E32 = 3803 ,
  LIEF::assembly::riscv::PseudoVFWMUL_VV_M2_E32_MASK = 3804 , LIEF::assembly::riscv::PseudoVFWMUL_VV_M4_E16 = 3805 , LIEF::assembly::riscv::PseudoVFWMUL_VV_M4_E16_MASK = 3806 , LIEF::assembly::riscv::PseudoVFWMUL_VV_M4_E32 = 3807 ,
  LIEF::assembly::riscv::PseudoVFWMUL_VV_M4_E32_MASK = 3808 , LIEF::assembly::riscv::PseudoVFWMUL_VV_MF2_E16 = 3809 , LIEF::assembly::riscv::PseudoVFWMUL_VV_MF2_E16_MASK = 3810 , LIEF::assembly::riscv::PseudoVFWMUL_VV_MF2_E32 = 3811 ,
  LIEF::assembly::riscv::PseudoVFWMUL_VV_MF2_E32_MASK = 3812 , LIEF::assembly::riscv::PseudoVFWMUL_VV_MF4_E16 = 3813 , LIEF::assembly::riscv::PseudoVFWMUL_VV_MF4_E16_MASK = 3814 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR16_M1_E16 = 3815 ,
  LIEF::assembly::riscv::PseudoVFWNMACC_VFPR16_M1_E16_MASK = 3816 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR16_M2_E16 = 3817 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR16_M2_E16_MASK = 3818 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR16_M4_E16 = 3819 ,
  LIEF::assembly::riscv::PseudoVFWNMACC_VFPR16_M4_E16_MASK = 3820 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR16_MF2_E16 = 3821 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR16_MF2_E16_MASK = 3822 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR16_MF4_E16 = 3823 ,
  LIEF::assembly::riscv::PseudoVFWNMACC_VFPR16_MF4_E16_MASK = 3824 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR32_M1_E32 = 3825 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR32_M1_E32_MASK = 3826 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR32_M2_E32 = 3827 ,
  LIEF::assembly::riscv::PseudoVFWNMACC_VFPR32_M2_E32_MASK = 3828 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR32_M4_E32 = 3829 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR32_M4_E32_MASK = 3830 , LIEF::assembly::riscv::PseudoVFWNMACC_VFPR32_MF2_E32 = 3831 ,
  LIEF::assembly::riscv::PseudoVFWNMACC_VFPR32_MF2_E32_MASK = 3832 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_M1_E16 = 3833 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_M1_E16_MASK = 3834 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_M1_E32 = 3835 ,
  LIEF::assembly::riscv::PseudoVFWNMACC_VV_M1_E32_MASK = 3836 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_M2_E16 = 3837 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_M2_E16_MASK = 3838 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_M2_E32 = 3839 ,
  LIEF::assembly::riscv::PseudoVFWNMACC_VV_M2_E32_MASK = 3840 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_M4_E16 = 3841 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_M4_E16_MASK = 3842 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_M4_E32 = 3843 ,
  LIEF::assembly::riscv::PseudoVFWNMACC_VV_M4_E32_MASK = 3844 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_MF2_E16 = 3845 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_MF2_E16_MASK = 3846 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_MF2_E32 = 3847 ,
  LIEF::assembly::riscv::PseudoVFWNMACC_VV_MF2_E32_MASK = 3848 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_MF4_E16 = 3849 , LIEF::assembly::riscv::PseudoVFWNMACC_VV_MF4_E16_MASK = 3850 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR16_M1_E16 = 3851 ,
  LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR16_M1_E16_MASK = 3852 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR16_M2_E16 = 3853 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR16_M2_E16_MASK = 3854 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR16_M4_E16 = 3855 ,
  LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR16_M4_E16_MASK = 3856 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR16_MF2_E16 = 3857 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR16_MF2_E16_MASK = 3858 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR16_MF4_E16 = 3859 ,
  LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR16_MF4_E16_MASK = 3860 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR32_M1_E32 = 3861 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR32_M1_E32_MASK = 3862 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR32_M2_E32 = 3863 ,
  LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR32_M2_E32_MASK = 3864 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR32_M4_E32 = 3865 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR32_M4_E32_MASK = 3866 , LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR32_MF2_E32 = 3867 ,
  LIEF::assembly::riscv::PseudoVFWNMSAC_VFPR32_MF2_E32_MASK = 3868 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M1_E16 = 3869 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M1_E16_MASK = 3870 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M1_E32 = 3871 ,
  LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M1_E32_MASK = 3872 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M2_E16 = 3873 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M2_E16_MASK = 3874 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M2_E32 = 3875 ,
  LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M2_E32_MASK = 3876 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M4_E16 = 3877 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M4_E16_MASK = 3878 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M4_E32 = 3879 ,
  LIEF::assembly::riscv::PseudoVFWNMSAC_VV_M4_E32_MASK = 3880 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_MF2_E16 = 3881 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_MF2_E16_MASK = 3882 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_MF2_E32 = 3883 ,
  LIEF::assembly::riscv::PseudoVFWNMSAC_VV_MF2_E32_MASK = 3884 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_MF4_E16 = 3885 , LIEF::assembly::riscv::PseudoVFWNMSAC_VV_MF4_E16_MASK = 3886 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M1_E16 = 3887 ,
  LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M1_E16_MASK = 3888 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M1_E32 = 3889 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M1_E32_MASK = 3890 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M2_E16 = 3891 ,
  LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M2_E16_MASK = 3892 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M2_E32 = 3893 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M2_E32_MASK = 3894 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M4_E16 = 3895 ,
  LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M4_E16_MASK = 3896 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M4_E32 = 3897 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M4_E32_MASK = 3898 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M8_E16 = 3899 ,
  LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M8_E16_MASK = 3900 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M8_E32 = 3901 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_M8_E32_MASK = 3902 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_MF2_E16 = 3903 ,
  LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_MF2_E16_MASK = 3904 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_MF2_E32 = 3905 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_MF2_E32_MASK = 3906 , LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_MF4_E16 = 3907 ,
  LIEF::assembly::riscv::PseudoVFWREDOSUM_VS_MF4_E16_MASK = 3908 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M1_E16 = 3909 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M1_E16_MASK = 3910 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M1_E32 = 3911 ,
  LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M1_E32_MASK = 3912 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M2_E16 = 3913 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M2_E16_MASK = 3914 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M2_E32 = 3915 ,
  LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M2_E32_MASK = 3916 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M4_E16 = 3917 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M4_E16_MASK = 3918 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M4_E32 = 3919 ,
  LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M4_E32_MASK = 3920 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M8_E16 = 3921 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M8_E16_MASK = 3922 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M8_E32 = 3923 ,
  LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_M8_E32_MASK = 3924 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_MF2_E16 = 3925 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_MF2_E16_MASK = 3926 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_MF2_E32 = 3927 ,
  LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_MF2_E32_MASK = 3928 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_MF4_E16 = 3929 , LIEF::assembly::riscv::PseudoVFWREDUSUM_VS_MF4_E16_MASK = 3930 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR16_M1_E16 = 3931 ,
  LIEF::assembly::riscv::PseudoVFWSUB_VFPR16_M1_E16_MASK = 3932 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR16_M2_E16 = 3933 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR16_M2_E16_MASK = 3934 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR16_M4_E16 = 3935 ,
  LIEF::assembly::riscv::PseudoVFWSUB_VFPR16_M4_E16_MASK = 3936 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR16_MF2_E16 = 3937 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR16_MF2_E16_MASK = 3938 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR16_MF4_E16 = 3939 ,
  LIEF::assembly::riscv::PseudoVFWSUB_VFPR16_MF4_E16_MASK = 3940 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR32_M1_E32 = 3941 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR32_M1_E32_MASK = 3942 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR32_M2_E32 = 3943 ,
  LIEF::assembly::riscv::PseudoVFWSUB_VFPR32_M2_E32_MASK = 3944 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR32_M4_E32 = 3945 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR32_M4_E32_MASK = 3946 , LIEF::assembly::riscv::PseudoVFWSUB_VFPR32_MF2_E32 = 3947 ,
  LIEF::assembly::riscv::PseudoVFWSUB_VFPR32_MF2_E32_MASK = 3948 , LIEF::assembly::riscv::PseudoVFWSUB_VV_M1_E16 = 3949 , LIEF::assembly::riscv::PseudoVFWSUB_VV_M1_E16_MASK = 3950 , LIEF::assembly::riscv::PseudoVFWSUB_VV_M1_E32 = 3951 ,
  LIEF::assembly::riscv::PseudoVFWSUB_VV_M1_E32_MASK = 3952 , LIEF::assembly::riscv::PseudoVFWSUB_VV_M2_E16 = 3953 , LIEF::assembly::riscv::PseudoVFWSUB_VV_M2_E16_MASK = 3954 , LIEF::assembly::riscv::PseudoVFWSUB_VV_M2_E32 = 3955 ,
  LIEF::assembly::riscv::PseudoVFWSUB_VV_M2_E32_MASK = 3956 , LIEF::assembly::riscv::PseudoVFWSUB_VV_M4_E16 = 3957 , LIEF::assembly::riscv::PseudoVFWSUB_VV_M4_E16_MASK = 3958 , LIEF::assembly::riscv::PseudoVFWSUB_VV_M4_E32 = 3959 ,
  LIEF::assembly::riscv::PseudoVFWSUB_VV_M4_E32_MASK = 3960 , LIEF::assembly::riscv::PseudoVFWSUB_VV_MF2_E16 = 3961 , LIEF::assembly::riscv::PseudoVFWSUB_VV_MF2_E16_MASK = 3962 , LIEF::assembly::riscv::PseudoVFWSUB_VV_MF2_E32 = 3963 ,
  LIEF::assembly::riscv::PseudoVFWSUB_VV_MF2_E32_MASK = 3964 , LIEF::assembly::riscv::PseudoVFWSUB_VV_MF4_E16 = 3965 , LIEF::assembly::riscv::PseudoVFWSUB_VV_MF4_E16_MASK = 3966 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR16_M1_E16 = 3967 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WFPR16_M1_E16_MASK = 3968 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR16_M2_E16 = 3969 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR16_M2_E16_MASK = 3970 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR16_M4_E16 = 3971 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WFPR16_M4_E16_MASK = 3972 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR16_MF2_E16 = 3973 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR16_MF2_E16_MASK = 3974 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR16_MF4_E16 = 3975 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WFPR16_MF4_E16_MASK = 3976 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR32_M1_E32 = 3977 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR32_M1_E32_MASK = 3978 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR32_M2_E32 = 3979 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WFPR32_M2_E32_MASK = 3980 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR32_M4_E32 = 3981 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR32_M4_E32_MASK = 3982 , LIEF::assembly::riscv::PseudoVFWSUB_WFPR32_MF2_E32 = 3983 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WFPR32_MF2_E32_MASK = 3984 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M1_E16 = 3985 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M1_E16_MASK = 3986 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M1_E16_MASK_TIED = 3987 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WV_M1_E16_TIED = 3988 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M1_E32 = 3989 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M1_E32_MASK = 3990 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M1_E32_MASK_TIED = 3991 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WV_M1_E32_TIED = 3992 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M2_E16 = 3993 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M2_E16_MASK = 3994 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M2_E16_MASK_TIED = 3995 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WV_M2_E16_TIED = 3996 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M2_E32 = 3997 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M2_E32_MASK = 3998 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M2_E32_MASK_TIED = 3999 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WV_M2_E32_TIED = 4000 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M4_E16 = 4001 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M4_E16_MASK = 4002 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M4_E16_MASK_TIED = 4003 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WV_M4_E16_TIED = 4004 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M4_E32 = 4005 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M4_E32_MASK = 4006 , LIEF::assembly::riscv::PseudoVFWSUB_WV_M4_E32_MASK_TIED = 4007 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WV_M4_E32_TIED = 4008 , LIEF::assembly::riscv::PseudoVFWSUB_WV_MF2_E16 = 4009 , LIEF::assembly::riscv::PseudoVFWSUB_WV_MF2_E16_MASK = 4010 , LIEF::assembly::riscv::PseudoVFWSUB_WV_MF2_E16_MASK_TIED = 4011 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WV_MF2_E16_TIED = 4012 , LIEF::assembly::riscv::PseudoVFWSUB_WV_MF2_E32 = 4013 , LIEF::assembly::riscv::PseudoVFWSUB_WV_MF2_E32_MASK = 4014 , LIEF::assembly::riscv::PseudoVFWSUB_WV_MF2_E32_MASK_TIED = 4015 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WV_MF2_E32_TIED = 4016 , LIEF::assembly::riscv::PseudoVFWSUB_WV_MF4_E16 = 4017 , LIEF::assembly::riscv::PseudoVFWSUB_WV_MF4_E16_MASK = 4018 , LIEF::assembly::riscv::PseudoVFWSUB_WV_MF4_E16_MASK_TIED = 4019 ,
  LIEF::assembly::riscv::PseudoVFWSUB_WV_MF4_E16_TIED = 4020 , LIEF::assembly::riscv::PseudoVGHSH_VV_M1 = 4021 , LIEF::assembly::riscv::PseudoVGHSH_VV_M2 = 4022 , LIEF::assembly::riscv::PseudoVGHSH_VV_M4 = 4023 ,
  LIEF::assembly::riscv::PseudoVGHSH_VV_M8 = 4024 , LIEF::assembly::riscv::PseudoVGHSH_VV_MF2 = 4025 , LIEF::assembly::riscv::PseudoVGMUL_VV_M1 = 4026 , LIEF::assembly::riscv::PseudoVGMUL_VV_M2 = 4027 ,
  LIEF::assembly::riscv::PseudoVGMUL_VV_M4 = 4028 , LIEF::assembly::riscv::PseudoVGMUL_VV_M8 = 4029 , LIEF::assembly::riscv::PseudoVGMUL_VV_MF2 = 4030 , LIEF::assembly::riscv::PseudoVID_V_M1 = 4031 ,
  LIEF::assembly::riscv::PseudoVID_V_M1_MASK = 4032 , LIEF::assembly::riscv::PseudoVID_V_M2 = 4033 , LIEF::assembly::riscv::PseudoVID_V_M2_MASK = 4034 , LIEF::assembly::riscv::PseudoVID_V_M4 = 4035 ,
  LIEF::assembly::riscv::PseudoVID_V_M4_MASK = 4036 , LIEF::assembly::riscv::PseudoVID_V_M8 = 4037 , LIEF::assembly::riscv::PseudoVID_V_M8_MASK = 4038 , LIEF::assembly::riscv::PseudoVID_V_MF2 = 4039 ,
  LIEF::assembly::riscv::PseudoVID_V_MF2_MASK = 4040 , LIEF::assembly::riscv::PseudoVID_V_MF4 = 4041 , LIEF::assembly::riscv::PseudoVID_V_MF4_MASK = 4042 , LIEF::assembly::riscv::PseudoVID_V_MF8 = 4043 ,
  LIEF::assembly::riscv::PseudoVID_V_MF8_MASK = 4044 , LIEF::assembly::riscv::PseudoVIOTA_M_M1 = 4045 , LIEF::assembly::riscv::PseudoVIOTA_M_M1_MASK = 4046 , LIEF::assembly::riscv::PseudoVIOTA_M_M2 = 4047 ,
  LIEF::assembly::riscv::PseudoVIOTA_M_M2_MASK = 4048 , LIEF::assembly::riscv::PseudoVIOTA_M_M4 = 4049 , LIEF::assembly::riscv::PseudoVIOTA_M_M4_MASK = 4050 , LIEF::assembly::riscv::PseudoVIOTA_M_M8 = 4051 ,
  LIEF::assembly::riscv::PseudoVIOTA_M_M8_MASK = 4052 , LIEF::assembly::riscv::PseudoVIOTA_M_MF2 = 4053 , LIEF::assembly::riscv::PseudoVIOTA_M_MF2_MASK = 4054 , LIEF::assembly::riscv::PseudoVIOTA_M_MF4 = 4055 ,
  LIEF::assembly::riscv::PseudoVIOTA_M_MF4_MASK = 4056 , LIEF::assembly::riscv::PseudoVIOTA_M_MF8 = 4057 , LIEF::assembly::riscv::PseudoVIOTA_M_MF8_MASK = 4058 , LIEF::assembly::riscv::PseudoVLE16FF_V_M1 = 4059 ,
  LIEF::assembly::riscv::PseudoVLE16FF_V_M1_MASK = 4060 , LIEF::assembly::riscv::PseudoVLE16FF_V_M2 = 4061 , LIEF::assembly::riscv::PseudoVLE16FF_V_M2_MASK = 4062 , LIEF::assembly::riscv::PseudoVLE16FF_V_M4 = 4063 ,
  LIEF::assembly::riscv::PseudoVLE16FF_V_M4_MASK = 4064 , LIEF::assembly::riscv::PseudoVLE16FF_V_M8 = 4065 , LIEF::assembly::riscv::PseudoVLE16FF_V_M8_MASK = 4066 , LIEF::assembly::riscv::PseudoVLE16FF_V_MF2 = 4067 ,
  LIEF::assembly::riscv::PseudoVLE16FF_V_MF2_MASK = 4068 , LIEF::assembly::riscv::PseudoVLE16FF_V_MF4 = 4069 , LIEF::assembly::riscv::PseudoVLE16FF_V_MF4_MASK = 4070 , LIEF::assembly::riscv::PseudoVLE16_V_M1 = 4071 ,
  LIEF::assembly::riscv::PseudoVLE16_V_M1_MASK = 4072 , LIEF::assembly::riscv::PseudoVLE16_V_M2 = 4073 , LIEF::assembly::riscv::PseudoVLE16_V_M2_MASK = 4074 , LIEF::assembly::riscv::PseudoVLE16_V_M4 = 4075 ,
  LIEF::assembly::riscv::PseudoVLE16_V_M4_MASK = 4076 , LIEF::assembly::riscv::PseudoVLE16_V_M8 = 4077 , LIEF::assembly::riscv::PseudoVLE16_V_M8_MASK = 4078 , LIEF::assembly::riscv::PseudoVLE16_V_MF2 = 4079 ,
  LIEF::assembly::riscv::PseudoVLE16_V_MF2_MASK = 4080 , LIEF::assembly::riscv::PseudoVLE16_V_MF4 = 4081 , LIEF::assembly::riscv::PseudoVLE16_V_MF4_MASK = 4082 , LIEF::assembly::riscv::PseudoVLE32FF_V_M1 = 4083 ,
  LIEF::assembly::riscv::PseudoVLE32FF_V_M1_MASK = 4084 , LIEF::assembly::riscv::PseudoVLE32FF_V_M2 = 4085 , LIEF::assembly::riscv::PseudoVLE32FF_V_M2_MASK = 4086 , LIEF::assembly::riscv::PseudoVLE32FF_V_M4 = 4087 ,
  LIEF::assembly::riscv::PseudoVLE32FF_V_M4_MASK = 4088 , LIEF::assembly::riscv::PseudoVLE32FF_V_M8 = 4089 , LIEF::assembly::riscv::PseudoVLE32FF_V_M8_MASK = 4090 , LIEF::assembly::riscv::PseudoVLE32FF_V_MF2 = 4091 ,
  LIEF::assembly::riscv::PseudoVLE32FF_V_MF2_MASK = 4092 , LIEF::assembly::riscv::PseudoVLE32_V_M1 = 4093 , LIEF::assembly::riscv::PseudoVLE32_V_M1_MASK = 4094 , LIEF::assembly::riscv::PseudoVLE32_V_M2 = 4095 ,
  LIEF::assembly::riscv::PseudoVLE32_V_M2_MASK = 4096 , LIEF::assembly::riscv::PseudoVLE32_V_M4 = 4097 , LIEF::assembly::riscv::PseudoVLE32_V_M4_MASK = 4098 , LIEF::assembly::riscv::PseudoVLE32_V_M8 = 4099 ,
  LIEF::assembly::riscv::PseudoVLE32_V_M8_MASK = 4100 , LIEF::assembly::riscv::PseudoVLE32_V_MF2 = 4101 , LIEF::assembly::riscv::PseudoVLE32_V_MF2_MASK = 4102 , LIEF::assembly::riscv::PseudoVLE64FF_V_M1 = 4103 ,
  LIEF::assembly::riscv::PseudoVLE64FF_V_M1_MASK = 4104 , LIEF::assembly::riscv::PseudoVLE64FF_V_M2 = 4105 , LIEF::assembly::riscv::PseudoVLE64FF_V_M2_MASK = 4106 , LIEF::assembly::riscv::PseudoVLE64FF_V_M4 = 4107 ,
  LIEF::assembly::riscv::PseudoVLE64FF_V_M4_MASK = 4108 , LIEF::assembly::riscv::PseudoVLE64FF_V_M8 = 4109 , LIEF::assembly::riscv::PseudoVLE64FF_V_M8_MASK = 4110 , LIEF::assembly::riscv::PseudoVLE64_V_M1 = 4111 ,
  LIEF::assembly::riscv::PseudoVLE64_V_M1_MASK = 4112 , LIEF::assembly::riscv::PseudoVLE64_V_M2 = 4113 , LIEF::assembly::riscv::PseudoVLE64_V_M2_MASK = 4114 , LIEF::assembly::riscv::PseudoVLE64_V_M4 = 4115 ,
  LIEF::assembly::riscv::PseudoVLE64_V_M4_MASK = 4116 , LIEF::assembly::riscv::PseudoVLE64_V_M8 = 4117 , LIEF::assembly::riscv::PseudoVLE64_V_M8_MASK = 4118 , LIEF::assembly::riscv::PseudoVLE8FF_V_M1 = 4119 ,
  LIEF::assembly::riscv::PseudoVLE8FF_V_M1_MASK = 4120 , LIEF::assembly::riscv::PseudoVLE8FF_V_M2 = 4121 , LIEF::assembly::riscv::PseudoVLE8FF_V_M2_MASK = 4122 , LIEF::assembly::riscv::PseudoVLE8FF_V_M4 = 4123 ,
  LIEF::assembly::riscv::PseudoVLE8FF_V_M4_MASK = 4124 , LIEF::assembly::riscv::PseudoVLE8FF_V_M8 = 4125 , LIEF::assembly::riscv::PseudoVLE8FF_V_M8_MASK = 4126 , LIEF::assembly::riscv::PseudoVLE8FF_V_MF2 = 4127 ,
  LIEF::assembly::riscv::PseudoVLE8FF_V_MF2_MASK = 4128 , LIEF::assembly::riscv::PseudoVLE8FF_V_MF4 = 4129 , LIEF::assembly::riscv::PseudoVLE8FF_V_MF4_MASK = 4130 , LIEF::assembly::riscv::PseudoVLE8FF_V_MF8 = 4131 ,
  LIEF::assembly::riscv::PseudoVLE8FF_V_MF8_MASK = 4132 , LIEF::assembly::riscv::PseudoVLE8_V_M1 = 4133 , LIEF::assembly::riscv::PseudoVLE8_V_M1_MASK = 4134 , LIEF::assembly::riscv::PseudoVLE8_V_M2 = 4135 ,
  LIEF::assembly::riscv::PseudoVLE8_V_M2_MASK = 4136 , LIEF::assembly::riscv::PseudoVLE8_V_M4 = 4137 , LIEF::assembly::riscv::PseudoVLE8_V_M4_MASK = 4138 , LIEF::assembly::riscv::PseudoVLE8_V_M8 = 4139 ,
  LIEF::assembly::riscv::PseudoVLE8_V_M8_MASK = 4140 , LIEF::assembly::riscv::PseudoVLE8_V_MF2 = 4141 , LIEF::assembly::riscv::PseudoVLE8_V_MF2_MASK = 4142 , LIEF::assembly::riscv::PseudoVLE8_V_MF4 = 4143 ,
  LIEF::assembly::riscv::PseudoVLE8_V_MF4_MASK = 4144 , LIEF::assembly::riscv::PseudoVLE8_V_MF8 = 4145 , LIEF::assembly::riscv::PseudoVLE8_V_MF8_MASK = 4146 , LIEF::assembly::riscv::PseudoVLM_V_B1 = 4147 ,
  LIEF::assembly::riscv::PseudoVLM_V_B16 = 4148 , LIEF::assembly::riscv::PseudoVLM_V_B2 = 4149 , LIEF::assembly::riscv::PseudoVLM_V_B32 = 4150 , LIEF::assembly::riscv::PseudoVLM_V_B4 = 4151 ,
  LIEF::assembly::riscv::PseudoVLM_V_B64 = 4152 , LIEF::assembly::riscv::PseudoVLM_V_B8 = 4153 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M1_M1 = 4154 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M1_M1_MASK = 4155 ,
  LIEF::assembly::riscv::PseudoVLOXEI16_V_M1_M2 = 4156 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M1_M2_MASK = 4157 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M1_M4 = 4158 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M1_M4_MASK = 4159 ,
  LIEF::assembly::riscv::PseudoVLOXEI16_V_M1_MF2 = 4160 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M1_MF2_MASK = 4161 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M2_M1 = 4162 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M2_M1_MASK = 4163 ,
  LIEF::assembly::riscv::PseudoVLOXEI16_V_M2_M2 = 4164 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M2_M2_MASK = 4165 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M2_M4 = 4166 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M2_M4_MASK = 4167 ,
  LIEF::assembly::riscv::PseudoVLOXEI16_V_M2_M8 = 4168 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M2_M8_MASK = 4169 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M4_M2 = 4170 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M4_M2_MASK = 4171 ,
  LIEF::assembly::riscv::PseudoVLOXEI16_V_M4_M4 = 4172 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M4_M4_MASK = 4173 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M4_M8 = 4174 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M4_M8_MASK = 4175 ,
  LIEF::assembly::riscv::PseudoVLOXEI16_V_M8_M4 = 4176 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M8_M4_MASK = 4177 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M8_M8 = 4178 , LIEF::assembly::riscv::PseudoVLOXEI16_V_M8_M8_MASK = 4179 ,
  LIEF::assembly::riscv::PseudoVLOXEI16_V_MF2_M1 = 4180 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF2_M1_MASK = 4181 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF2_M2 = 4182 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF2_M2_MASK = 4183 ,
  LIEF::assembly::riscv::PseudoVLOXEI16_V_MF2_MF2 = 4184 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF2_MF2_MASK = 4185 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF2_MF4 = 4186 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF2_MF4_MASK = 4187 ,
  LIEF::assembly::riscv::PseudoVLOXEI16_V_MF4_M1 = 4188 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF4_M1_MASK = 4189 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF4_MF2 = 4190 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF4_MF2_MASK = 4191 ,
  LIEF::assembly::riscv::PseudoVLOXEI16_V_MF4_MF4 = 4192 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF4_MF4_MASK = 4193 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF4_MF8 = 4194 , LIEF::assembly::riscv::PseudoVLOXEI16_V_MF4_MF8_MASK = 4195 ,
  LIEF::assembly::riscv::PseudoVLOXEI32_V_M1_M1 = 4196 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M1_M1_MASK = 4197 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M1_M2 = 4198 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M1_M2_MASK = 4199 ,
  LIEF::assembly::riscv::PseudoVLOXEI32_V_M1_MF2 = 4200 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M1_MF2_MASK = 4201 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M1_MF4 = 4202 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M1_MF4_MASK = 4203 ,
  LIEF::assembly::riscv::PseudoVLOXEI32_V_M2_M1 = 4204 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M2_M1_MASK = 4205 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M2_M2 = 4206 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M2_M2_MASK = 4207 ,
  LIEF::assembly::riscv::PseudoVLOXEI32_V_M2_M4 = 4208 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M2_M4_MASK = 4209 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M2_MF2 = 4210 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M2_MF2_MASK = 4211 ,
  LIEF::assembly::riscv::PseudoVLOXEI32_V_M4_M1 = 4212 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M4_M1_MASK = 4213 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M4_M2 = 4214 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M4_M2_MASK = 4215 ,
  LIEF::assembly::riscv::PseudoVLOXEI32_V_M4_M4 = 4216 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M4_M4_MASK = 4217 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M4_M8 = 4218 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M4_M8_MASK = 4219 ,
  LIEF::assembly::riscv::PseudoVLOXEI32_V_M8_M2 = 4220 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M8_M2_MASK = 4221 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M8_M4 = 4222 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M8_M4_MASK = 4223 ,
  LIEF::assembly::riscv::PseudoVLOXEI32_V_M8_M8 = 4224 , LIEF::assembly::riscv::PseudoVLOXEI32_V_M8_M8_MASK = 4225 , LIEF::assembly::riscv::PseudoVLOXEI32_V_MF2_M1 = 4226 , LIEF::assembly::riscv::PseudoVLOXEI32_V_MF2_M1_MASK = 4227 ,
  LIEF::assembly::riscv::PseudoVLOXEI32_V_MF2_MF2 = 4228 , LIEF::assembly::riscv::PseudoVLOXEI32_V_MF2_MF2_MASK = 4229 , LIEF::assembly::riscv::PseudoVLOXEI32_V_MF2_MF4 = 4230 , LIEF::assembly::riscv::PseudoVLOXEI32_V_MF2_MF4_MASK = 4231 ,
  LIEF::assembly::riscv::PseudoVLOXEI32_V_MF2_MF8 = 4232 , LIEF::assembly::riscv::PseudoVLOXEI32_V_MF2_MF8_MASK = 4233 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M1_M1 = 4234 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M1_M1_MASK = 4235 ,
  LIEF::assembly::riscv::PseudoVLOXEI64_V_M1_MF2 = 4236 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M1_MF2_MASK = 4237 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M1_MF4 = 4238 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M1_MF4_MASK = 4239 ,
  LIEF::assembly::riscv::PseudoVLOXEI64_V_M1_MF8 = 4240 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M1_MF8_MASK = 4241 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M2_M1 = 4242 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M2_M1_MASK = 4243 ,
  LIEF::assembly::riscv::PseudoVLOXEI64_V_M2_M2 = 4244 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M2_M2_MASK = 4245 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M2_MF2 = 4246 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M2_MF2_MASK = 4247 ,
  LIEF::assembly::riscv::PseudoVLOXEI64_V_M2_MF4 = 4248 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M2_MF4_MASK = 4249 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M4_M1 = 4250 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M4_M1_MASK = 4251 ,
  LIEF::assembly::riscv::PseudoVLOXEI64_V_M4_M2 = 4252 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M4_M2_MASK = 4253 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M4_M4 = 4254 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M4_M4_MASK = 4255 ,
  LIEF::assembly::riscv::PseudoVLOXEI64_V_M4_MF2 = 4256 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M4_MF2_MASK = 4257 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M8_M1 = 4258 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M8_M1_MASK = 4259 ,
  LIEF::assembly::riscv::PseudoVLOXEI64_V_M8_M2 = 4260 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M8_M2_MASK = 4261 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M8_M4 = 4262 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M8_M4_MASK = 4263 ,
  LIEF::assembly::riscv::PseudoVLOXEI64_V_M8_M8 = 4264 , LIEF::assembly::riscv::PseudoVLOXEI64_V_M8_M8_MASK = 4265 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M1_M1 = 4266 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M1_M1_MASK = 4267 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_M1_M2 = 4268 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M1_M2_MASK = 4269 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M1_M4 = 4270 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M1_M4_MASK = 4271 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_M1_M8 = 4272 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M1_M8_MASK = 4273 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M2_M2 = 4274 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M2_M2_MASK = 4275 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_M2_M4 = 4276 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M2_M4_MASK = 4277 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M2_M8 = 4278 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M2_M8_MASK = 4279 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_M4_M4 = 4280 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M4_M4_MASK = 4281 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M4_M8 = 4282 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M4_M8_MASK = 4283 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_M8_M8 = 4284 , LIEF::assembly::riscv::PseudoVLOXEI8_V_M8_M8_MASK = 4285 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF2_M1 = 4286 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF2_M1_MASK = 4287 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_MF2_M2 = 4288 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF2_M2_MASK = 4289 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF2_M4 = 4290 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF2_M4_MASK = 4291 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_MF2_MF2 = 4292 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF2_MF2_MASK = 4293 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF4_M1 = 4294 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF4_M1_MASK = 4295 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_MF4_M2 = 4296 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF4_M2_MASK = 4297 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF4_MF2 = 4298 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF4_MF2_MASK = 4299 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_MF4_MF4 = 4300 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF4_MF4_MASK = 4301 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF8_M1 = 4302 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF8_M1_MASK = 4303 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_MF8_MF2 = 4304 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF8_MF2_MASK = 4305 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF8_MF4 = 4306 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF8_MF4_MASK = 4307 ,
  LIEF::assembly::riscv::PseudoVLOXEI8_V_MF8_MF8 = 4308 , LIEF::assembly::riscv::PseudoVLOXEI8_V_MF8_MF8_MASK = 4309 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M1_M1 = 4310 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M1_M1_MASK = 4311 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M1_M2 = 4312 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M1_M2_MASK = 4313 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M1_M4 = 4314 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M1_M4_MASK = 4315 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M1_MF2 = 4316 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M1_MF2_MASK = 4317 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M2_M1 = 4318 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M2_M1_MASK = 4319 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M2_M2 = 4320 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M2_M2_MASK = 4321 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M2_M4 = 4322 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M2_M4_MASK = 4323 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M4_M2 = 4324 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M4_M2_MASK = 4325 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M4_M4 = 4326 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M4_M4_MASK = 4327 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M8_M4 = 4328 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_M8_M4_MASK = 4329 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF2_M1 = 4330 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF2_M1_MASK = 4331 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF2_M2 = 4332 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF2_M2_MASK = 4333 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF2_MF2 = 4334 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF2_MF2_MASK = 4335 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF2_MF4 = 4336 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF2_MF4_MASK = 4337 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF4_M1 = 4338 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF4_M1_MASK = 4339 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF4_MF2 = 4340 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF4_MF2_MASK = 4341 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF4_MF4 = 4342 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF4_MF4_MASK = 4343 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF4_MF8 = 4344 , LIEF::assembly::riscv::PseudoVLOXSEG2EI16_V_MF4_MF8_MASK = 4345 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M1_M1 = 4346 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M1_M1_MASK = 4347 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M1_M2 = 4348 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M1_M2_MASK = 4349 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M1_MF2 = 4350 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M1_MF2_MASK = 4351 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M1_MF4 = 4352 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M1_MF4_MASK = 4353 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M2_M1 = 4354 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M2_M1_MASK = 4355 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M2_M2 = 4356 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M2_M2_MASK = 4357 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M2_M4 = 4358 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M2_M4_MASK = 4359 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M2_MF2 = 4360 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M2_MF2_MASK = 4361 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M4_M1 = 4362 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M4_M1_MASK = 4363 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M4_M2 = 4364 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M4_M2_MASK = 4365 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M4_M4 = 4366 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M4_M4_MASK = 4367 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M8_M2 = 4368 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M8_M2_MASK = 4369 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M8_M4 = 4370 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_M8_M4_MASK = 4371 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_MF2_M1 = 4372 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_MF2_M1_MASK = 4373 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_MF2_MF2 = 4374 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_MF2_MF2_MASK = 4375 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_MF2_MF4 = 4376 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_MF2_MF4_MASK = 4377 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_MF2_MF8 = 4378 , LIEF::assembly::riscv::PseudoVLOXSEG2EI32_V_MF2_MF8_MASK = 4379 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M1_M1 = 4380 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M1_M1_MASK = 4381 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M1_MF2 = 4382 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M1_MF2_MASK = 4383 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M1_MF4 = 4384 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M1_MF4_MASK = 4385 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M1_MF8 = 4386 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M1_MF8_MASK = 4387 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M2_M1 = 4388 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M2_M1_MASK = 4389 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M2_M2 = 4390 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M2_M2_MASK = 4391 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M2_MF2 = 4392 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M2_MF2_MASK = 4393 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M2_MF4 = 4394 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M2_MF4_MASK = 4395 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M4_M1 = 4396 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M4_M1_MASK = 4397 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M4_M2 = 4398 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M4_M2_MASK = 4399 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M4_M4 = 4400 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M4_M4_MASK = 4401 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M4_MF2 = 4402 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M4_MF2_MASK = 4403 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M8_M1 = 4404 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M8_M1_MASK = 4405 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M8_M2 = 4406 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M8_M2_MASK = 4407 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M8_M4 = 4408 , LIEF::assembly::riscv::PseudoVLOXSEG2EI64_V_M8_M4_MASK = 4409 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M1_M1 = 4410 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M1_M1_MASK = 4411 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M1_M2 = 4412 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M1_M2_MASK = 4413 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M1_M4 = 4414 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M1_M4_MASK = 4415 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M2_M2 = 4416 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M2_M2_MASK = 4417 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M2_M4 = 4418 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M2_M4_MASK = 4419 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M4_M4 = 4420 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_M4_M4_MASK = 4421 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF2_M1 = 4422 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF2_M1_MASK = 4423 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF2_M2 = 4424 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF2_M2_MASK = 4425 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF2_M4 = 4426 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF2_M4_MASK = 4427 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF2_MF2 = 4428 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF2_MF2_MASK = 4429 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF4_M1 = 4430 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF4_M1_MASK = 4431 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF4_M2 = 4432 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF4_M2_MASK = 4433 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF4_MF2 = 4434 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF4_MF2_MASK = 4435 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF4_MF4 = 4436 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF4_MF4_MASK = 4437 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF8_M1 = 4438 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF8_M1_MASK = 4439 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF8_MF2 = 4440 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF8_MF2_MASK = 4441 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF8_MF4 = 4442 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF8_MF4_MASK = 4443 ,
  LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF8_MF8 = 4444 , LIEF::assembly::riscv::PseudoVLOXSEG2EI8_V_MF8_MF8_MASK = 4445 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M1_M1 = 4446 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M1_M1_MASK = 4447 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M1_M2 = 4448 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M1_M2_MASK = 4449 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M1_MF2 = 4450 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M1_MF2_MASK = 4451 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M2_M1 = 4452 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M2_M1_MASK = 4453 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M2_M2 = 4454 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M2_M2_MASK = 4455 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M4_M2 = 4456 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_M4_M2_MASK = 4457 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF2_M1 = 4458 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF2_M1_MASK = 4459 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF2_M2 = 4460 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF2_M2_MASK = 4461 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF2_MF2 = 4462 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF2_MF2_MASK = 4463 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF2_MF4 = 4464 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF2_MF4_MASK = 4465 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF4_M1 = 4466 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF4_M1_MASK = 4467 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF4_MF2 = 4468 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF4_MF2_MASK = 4469 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF4_MF4 = 4470 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF4_MF4_MASK = 4471 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF4_MF8 = 4472 , LIEF::assembly::riscv::PseudoVLOXSEG3EI16_V_MF4_MF8_MASK = 4473 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M1_M1 = 4474 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M1_M1_MASK = 4475 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M1_M2 = 4476 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M1_M2_MASK = 4477 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M1_MF2 = 4478 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M1_MF2_MASK = 4479 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M1_MF4 = 4480 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M1_MF4_MASK = 4481 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M2_M1 = 4482 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M2_M1_MASK = 4483 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M2_M2 = 4484 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M2_M2_MASK = 4485 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M2_MF2 = 4486 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M2_MF2_MASK = 4487 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M4_M1 = 4488 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M4_M1_MASK = 4489 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M4_M2 = 4490 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M4_M2_MASK = 4491 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M8_M2 = 4492 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_M8_M2_MASK = 4493 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_MF2_M1 = 4494 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_MF2_M1_MASK = 4495 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_MF2_MF2 = 4496 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_MF2_MF2_MASK = 4497 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_MF2_MF4 = 4498 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_MF2_MF4_MASK = 4499 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_MF2_MF8 = 4500 , LIEF::assembly::riscv::PseudoVLOXSEG3EI32_V_MF2_MF8_MASK = 4501 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M1_M1 = 4502 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M1_M1_MASK = 4503 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M1_MF2 = 4504 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M1_MF2_MASK = 4505 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M1_MF4 = 4506 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M1_MF4_MASK = 4507 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M1_MF8 = 4508 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M1_MF8_MASK = 4509 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M2_M1 = 4510 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M2_M1_MASK = 4511 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M2_M2 = 4512 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M2_M2_MASK = 4513 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M2_MF2 = 4514 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M2_MF2_MASK = 4515 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M2_MF4 = 4516 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M2_MF4_MASK = 4517 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M4_M1 = 4518 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M4_M1_MASK = 4519 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M4_M2 = 4520 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M4_M2_MASK = 4521 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M4_MF2 = 4522 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M4_MF2_MASK = 4523 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M8_M1 = 4524 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M8_M1_MASK = 4525 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M8_M2 = 4526 , LIEF::assembly::riscv::PseudoVLOXSEG3EI64_V_M8_M2_MASK = 4527 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_M1_M1 = 4528 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_M1_M1_MASK = 4529 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_M1_M2 = 4530 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_M1_M2_MASK = 4531 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_M2_M2 = 4532 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_M2_M2_MASK = 4533 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF2_M1 = 4534 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF2_M1_MASK = 4535 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF2_M2 = 4536 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF2_M2_MASK = 4537 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF2_MF2 = 4538 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF2_MF2_MASK = 4539 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF4_M1 = 4540 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF4_M1_MASK = 4541 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF4_M2 = 4542 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF4_M2_MASK = 4543 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF4_MF2 = 4544 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF4_MF2_MASK = 4545 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF4_MF4 = 4546 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF4_MF4_MASK = 4547 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF8_M1 = 4548 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF8_M1_MASK = 4549 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF8_MF2 = 4550 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF8_MF2_MASK = 4551 ,
  LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF8_MF4 = 4552 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF8_MF4_MASK = 4553 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF8_MF8 = 4554 , LIEF::assembly::riscv::PseudoVLOXSEG3EI8_V_MF8_MF8_MASK = 4555 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M1_M1 = 4556 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M1_M1_MASK = 4557 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M1_M2 = 4558 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M1_M2_MASK = 4559 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M1_MF2 = 4560 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M1_MF2_MASK = 4561 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M2_M1 = 4562 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M2_M1_MASK = 4563 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M2_M2 = 4564 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M2_M2_MASK = 4565 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M4_M2 = 4566 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_M4_M2_MASK = 4567 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF2_M1 = 4568 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF2_M1_MASK = 4569 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF2_M2 = 4570 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF2_M2_MASK = 4571 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF2_MF2 = 4572 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF2_MF2_MASK = 4573 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF2_MF4 = 4574 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF2_MF4_MASK = 4575 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF4_M1 = 4576 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF4_M1_MASK = 4577 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF4_MF2 = 4578 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF4_MF2_MASK = 4579 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF4_MF4 = 4580 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF4_MF4_MASK = 4581 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF4_MF8 = 4582 , LIEF::assembly::riscv::PseudoVLOXSEG4EI16_V_MF4_MF8_MASK = 4583 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M1_M1 = 4584 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M1_M1_MASK = 4585 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M1_M2 = 4586 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M1_M2_MASK = 4587 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M1_MF2 = 4588 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M1_MF2_MASK = 4589 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M1_MF4 = 4590 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M1_MF4_MASK = 4591 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M2_M1 = 4592 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M2_M1_MASK = 4593 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M2_M2 = 4594 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M2_M2_MASK = 4595 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M2_MF2 = 4596 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M2_MF2_MASK = 4597 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M4_M1 = 4598 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M4_M1_MASK = 4599 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M4_M2 = 4600 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M4_M2_MASK = 4601 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M8_M2 = 4602 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_M8_M2_MASK = 4603 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_MF2_M1 = 4604 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_MF2_M1_MASK = 4605 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_MF2_MF2 = 4606 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_MF2_MF2_MASK = 4607 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_MF2_MF4 = 4608 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_MF2_MF4_MASK = 4609 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_MF2_MF8 = 4610 , LIEF::assembly::riscv::PseudoVLOXSEG4EI32_V_MF2_MF8_MASK = 4611 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M1_M1 = 4612 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M1_M1_MASK = 4613 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M1_MF2 = 4614 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M1_MF2_MASK = 4615 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M1_MF4 = 4616 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M1_MF4_MASK = 4617 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M1_MF8 = 4618 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M1_MF8_MASK = 4619 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M2_M1 = 4620 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M2_M1_MASK = 4621 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M2_M2 = 4622 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M2_M2_MASK = 4623 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M2_MF2 = 4624 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M2_MF2_MASK = 4625 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M2_MF4 = 4626 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M2_MF4_MASK = 4627 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M4_M1 = 4628 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M4_M1_MASK = 4629 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M4_M2 = 4630 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M4_M2_MASK = 4631 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M4_MF2 = 4632 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M4_MF2_MASK = 4633 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M8_M1 = 4634 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M8_M1_MASK = 4635 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M8_M2 = 4636 , LIEF::assembly::riscv::PseudoVLOXSEG4EI64_V_M8_M2_MASK = 4637 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_M1_M1 = 4638 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_M1_M1_MASK = 4639 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_M1_M2 = 4640 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_M1_M2_MASK = 4641 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_M2_M2 = 4642 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_M2_M2_MASK = 4643 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF2_M1 = 4644 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF2_M1_MASK = 4645 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF2_M2 = 4646 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF2_M2_MASK = 4647 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF2_MF2 = 4648 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF2_MF2_MASK = 4649 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF4_M1 = 4650 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF4_M1_MASK = 4651 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF4_M2 = 4652 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF4_M2_MASK = 4653 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF4_MF2 = 4654 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF4_MF2_MASK = 4655 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF4_MF4 = 4656 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF4_MF4_MASK = 4657 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF8_M1 = 4658 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF8_M1_MASK = 4659 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF8_MF2 = 4660 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF8_MF2_MASK = 4661 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF8_MF4 = 4662 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF8_MF4_MASK = 4663 ,
  LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF8_MF8 = 4664 , LIEF::assembly::riscv::PseudoVLOXSEG4EI8_V_MF8_MF8_MASK = 4665 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_M1_M1 = 4666 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_M1_M1_MASK = 4667 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_M1_MF2 = 4668 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_M1_MF2_MASK = 4669 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_M2_M1 = 4670 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_M2_M1_MASK = 4671 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF2_M1 = 4672 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF2_M1_MASK = 4673 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF2_MF2 = 4674 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF2_MF2_MASK = 4675 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF2_MF4 = 4676 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF2_MF4_MASK = 4677 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF4_M1 = 4678 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF4_M1_MASK = 4679 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF4_MF2 = 4680 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF4_MF2_MASK = 4681 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF4_MF4 = 4682 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF4_MF4_MASK = 4683 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF4_MF8 = 4684 , LIEF::assembly::riscv::PseudoVLOXSEG5EI16_V_MF4_MF8_MASK = 4685 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M1_M1 = 4686 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M1_M1_MASK = 4687 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M1_MF2 = 4688 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M1_MF2_MASK = 4689 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M1_MF4 = 4690 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M1_MF4_MASK = 4691 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M2_M1 = 4692 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M2_M1_MASK = 4693 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M2_MF2 = 4694 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M2_MF2_MASK = 4695 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M4_M1 = 4696 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_M4_M1_MASK = 4697 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_MF2_M1 = 4698 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_MF2_M1_MASK = 4699 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_MF2_MF2 = 4700 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_MF2_MF2_MASK = 4701 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_MF2_MF4 = 4702 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_MF2_MF4_MASK = 4703 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_MF2_MF8 = 4704 , LIEF::assembly::riscv::PseudoVLOXSEG5EI32_V_MF2_MF8_MASK = 4705 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M1_M1 = 4706 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M1_M1_MASK = 4707 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M1_MF2 = 4708 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M1_MF2_MASK = 4709 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M1_MF4 = 4710 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M1_MF4_MASK = 4711 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M1_MF8 = 4712 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M1_MF8_MASK = 4713 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M2_M1 = 4714 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M2_M1_MASK = 4715 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M2_MF2 = 4716 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M2_MF2_MASK = 4717 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M2_MF4 = 4718 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M2_MF4_MASK = 4719 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M4_M1 = 4720 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M4_M1_MASK = 4721 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M4_MF2 = 4722 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M4_MF2_MASK = 4723 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M8_M1 = 4724 , LIEF::assembly::riscv::PseudoVLOXSEG5EI64_V_M8_M1_MASK = 4725 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_M1_M1 = 4726 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_M1_M1_MASK = 4727 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF2_M1 = 4728 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF2_M1_MASK = 4729 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF2_MF2 = 4730 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF2_MF2_MASK = 4731 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF4_M1 = 4732 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF4_M1_MASK = 4733 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF4_MF2 = 4734 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF4_MF2_MASK = 4735 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF4_MF4 = 4736 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF4_MF4_MASK = 4737 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF8_M1 = 4738 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF8_M1_MASK = 4739 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF8_MF2 = 4740 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF8_MF2_MASK = 4741 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF8_MF4 = 4742 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF8_MF4_MASK = 4743 ,
  LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF8_MF8 = 4744 , LIEF::assembly::riscv::PseudoVLOXSEG5EI8_V_MF8_MF8_MASK = 4745 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_M1_M1 = 4746 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_M1_M1_MASK = 4747 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_M1_MF2 = 4748 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_M1_MF2_MASK = 4749 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_M2_M1 = 4750 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_M2_M1_MASK = 4751 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF2_M1 = 4752 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF2_M1_MASK = 4753 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF2_MF2 = 4754 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF2_MF2_MASK = 4755 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF2_MF4 = 4756 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF2_MF4_MASK = 4757 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF4_M1 = 4758 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF4_M1_MASK = 4759 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF4_MF2 = 4760 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF4_MF2_MASK = 4761 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF4_MF4 = 4762 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF4_MF4_MASK = 4763 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF4_MF8 = 4764 , LIEF::assembly::riscv::PseudoVLOXSEG6EI16_V_MF4_MF8_MASK = 4765 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M1_M1 = 4766 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M1_M1_MASK = 4767 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M1_MF2 = 4768 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M1_MF2_MASK = 4769 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M1_MF4 = 4770 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M1_MF4_MASK = 4771 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M2_M1 = 4772 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M2_M1_MASK = 4773 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M2_MF2 = 4774 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M2_MF2_MASK = 4775 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M4_M1 = 4776 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_M4_M1_MASK = 4777 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_MF2_M1 = 4778 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_MF2_M1_MASK = 4779 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_MF2_MF2 = 4780 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_MF2_MF2_MASK = 4781 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_MF2_MF4 = 4782 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_MF2_MF4_MASK = 4783 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_MF2_MF8 = 4784 , LIEF::assembly::riscv::PseudoVLOXSEG6EI32_V_MF2_MF8_MASK = 4785 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M1_M1 = 4786 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M1_M1_MASK = 4787 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M1_MF2 = 4788 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M1_MF2_MASK = 4789 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M1_MF4 = 4790 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M1_MF4_MASK = 4791 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M1_MF8 = 4792 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M1_MF8_MASK = 4793 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M2_M1 = 4794 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M2_M1_MASK = 4795 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M2_MF2 = 4796 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M2_MF2_MASK = 4797 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M2_MF4 = 4798 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M2_MF4_MASK = 4799 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M4_M1 = 4800 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M4_M1_MASK = 4801 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M4_MF2 = 4802 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M4_MF2_MASK = 4803 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M8_M1 = 4804 , LIEF::assembly::riscv::PseudoVLOXSEG6EI64_V_M8_M1_MASK = 4805 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_M1_M1 = 4806 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_M1_M1_MASK = 4807 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF2_M1 = 4808 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF2_M1_MASK = 4809 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF2_MF2 = 4810 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF2_MF2_MASK = 4811 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF4_M1 = 4812 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF4_M1_MASK = 4813 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF4_MF2 = 4814 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF4_MF2_MASK = 4815 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF4_MF4 = 4816 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF4_MF4_MASK = 4817 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF8_M1 = 4818 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF8_M1_MASK = 4819 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF8_MF2 = 4820 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF8_MF2_MASK = 4821 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF8_MF4 = 4822 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF8_MF4_MASK = 4823 ,
  LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF8_MF8 = 4824 , LIEF::assembly::riscv::PseudoVLOXSEG6EI8_V_MF8_MF8_MASK = 4825 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_M1_M1 = 4826 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_M1_M1_MASK = 4827 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_M1_MF2 = 4828 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_M1_MF2_MASK = 4829 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_M2_M1 = 4830 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_M2_M1_MASK = 4831 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF2_M1 = 4832 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF2_M1_MASK = 4833 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF2_MF2 = 4834 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF2_MF2_MASK = 4835 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF2_MF4 = 4836 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF2_MF4_MASK = 4837 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF4_M1 = 4838 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF4_M1_MASK = 4839 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF4_MF2 = 4840 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF4_MF2_MASK = 4841 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF4_MF4 = 4842 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF4_MF4_MASK = 4843 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF4_MF8 = 4844 , LIEF::assembly::riscv::PseudoVLOXSEG7EI16_V_MF4_MF8_MASK = 4845 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M1_M1 = 4846 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M1_M1_MASK = 4847 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M1_MF2 = 4848 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M1_MF2_MASK = 4849 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M1_MF4 = 4850 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M1_MF4_MASK = 4851 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M2_M1 = 4852 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M2_M1_MASK = 4853 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M2_MF2 = 4854 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M2_MF2_MASK = 4855 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M4_M1 = 4856 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_M4_M1_MASK = 4857 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_MF2_M1 = 4858 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_MF2_M1_MASK = 4859 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_MF2_MF2 = 4860 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_MF2_MF2_MASK = 4861 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_MF2_MF4 = 4862 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_MF2_MF4_MASK = 4863 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_MF2_MF8 = 4864 , LIEF::assembly::riscv::PseudoVLOXSEG7EI32_V_MF2_MF8_MASK = 4865 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M1_M1 = 4866 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M1_M1_MASK = 4867 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M1_MF2 = 4868 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M1_MF2_MASK = 4869 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M1_MF4 = 4870 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M1_MF4_MASK = 4871 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M1_MF8 = 4872 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M1_MF8_MASK = 4873 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M2_M1 = 4874 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M2_M1_MASK = 4875 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M2_MF2 = 4876 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M2_MF2_MASK = 4877 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M2_MF4 = 4878 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M2_MF4_MASK = 4879 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M4_M1 = 4880 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M4_M1_MASK = 4881 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M4_MF2 = 4882 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M4_MF2_MASK = 4883 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M8_M1 = 4884 , LIEF::assembly::riscv::PseudoVLOXSEG7EI64_V_M8_M1_MASK = 4885 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_M1_M1 = 4886 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_M1_M1_MASK = 4887 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF2_M1 = 4888 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF2_M1_MASK = 4889 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF2_MF2 = 4890 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF2_MF2_MASK = 4891 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF4_M1 = 4892 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF4_M1_MASK = 4893 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF4_MF2 = 4894 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF4_MF2_MASK = 4895 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF4_MF4 = 4896 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF4_MF4_MASK = 4897 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF8_M1 = 4898 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF8_M1_MASK = 4899 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF8_MF2 = 4900 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF8_MF2_MASK = 4901 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF8_MF4 = 4902 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF8_MF4_MASK = 4903 ,
  LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF8_MF8 = 4904 , LIEF::assembly::riscv::PseudoVLOXSEG7EI8_V_MF8_MF8_MASK = 4905 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_M1_M1 = 4906 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_M1_M1_MASK = 4907 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_M1_MF2 = 4908 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_M1_MF2_MASK = 4909 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_M2_M1 = 4910 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_M2_M1_MASK = 4911 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF2_M1 = 4912 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF2_M1_MASK = 4913 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF2_MF2 = 4914 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF2_MF2_MASK = 4915 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF2_MF4 = 4916 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF2_MF4_MASK = 4917 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF4_M1 = 4918 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF4_M1_MASK = 4919 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF4_MF2 = 4920 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF4_MF2_MASK = 4921 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF4_MF4 = 4922 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF4_MF4_MASK = 4923 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF4_MF8 = 4924 , LIEF::assembly::riscv::PseudoVLOXSEG8EI16_V_MF4_MF8_MASK = 4925 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M1_M1 = 4926 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M1_M1_MASK = 4927 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M1_MF2 = 4928 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M1_MF2_MASK = 4929 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M1_MF4 = 4930 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M1_MF4_MASK = 4931 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M2_M1 = 4932 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M2_M1_MASK = 4933 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M2_MF2 = 4934 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M2_MF2_MASK = 4935 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M4_M1 = 4936 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_M4_M1_MASK = 4937 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_MF2_M1 = 4938 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_MF2_M1_MASK = 4939 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_MF2_MF2 = 4940 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_MF2_MF2_MASK = 4941 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_MF2_MF4 = 4942 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_MF2_MF4_MASK = 4943 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_MF2_MF8 = 4944 , LIEF::assembly::riscv::PseudoVLOXSEG8EI32_V_MF2_MF8_MASK = 4945 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M1_M1 = 4946 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M1_M1_MASK = 4947 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M1_MF2 = 4948 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M1_MF2_MASK = 4949 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M1_MF4 = 4950 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M1_MF4_MASK = 4951 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M1_MF8 = 4952 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M1_MF8_MASK = 4953 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M2_M1 = 4954 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M2_M1_MASK = 4955 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M2_MF2 = 4956 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M2_MF2_MASK = 4957 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M2_MF4 = 4958 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M2_MF4_MASK = 4959 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M4_M1 = 4960 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M4_M1_MASK = 4961 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M4_MF2 = 4962 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M4_MF2_MASK = 4963 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M8_M1 = 4964 , LIEF::assembly::riscv::PseudoVLOXSEG8EI64_V_M8_M1_MASK = 4965 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_M1_M1 = 4966 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_M1_M1_MASK = 4967 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF2_M1 = 4968 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF2_M1_MASK = 4969 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF2_MF2 = 4970 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF2_MF2_MASK = 4971 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF4_M1 = 4972 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF4_M1_MASK = 4973 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF4_MF2 = 4974 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF4_MF2_MASK = 4975 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF4_MF4 = 4976 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF4_MF4_MASK = 4977 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF8_M1 = 4978 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF8_M1_MASK = 4979 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF8_MF2 = 4980 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF8_MF2_MASK = 4981 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF8_MF4 = 4982 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF8_MF4_MASK = 4983 ,
  LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF8_MF8 = 4984 , LIEF::assembly::riscv::PseudoVLOXSEG8EI8_V_MF8_MF8_MASK = 4985 , LIEF::assembly::riscv::PseudoVLSE16_V_M1 = 4986 , LIEF::assembly::riscv::PseudoVLSE16_V_M1_MASK = 4987 ,
  LIEF::assembly::riscv::PseudoVLSE16_V_M2 = 4988 , LIEF::assembly::riscv::PseudoVLSE16_V_M2_MASK = 4989 , LIEF::assembly::riscv::PseudoVLSE16_V_M4 = 4990 , LIEF::assembly::riscv::PseudoVLSE16_V_M4_MASK = 4991 ,
  LIEF::assembly::riscv::PseudoVLSE16_V_M8 = 4992 , LIEF::assembly::riscv::PseudoVLSE16_V_M8_MASK = 4993 , LIEF::assembly::riscv::PseudoVLSE16_V_MF2 = 4994 , LIEF::assembly::riscv::PseudoVLSE16_V_MF2_MASK = 4995 ,
  LIEF::assembly::riscv::PseudoVLSE16_V_MF4 = 4996 , LIEF::assembly::riscv::PseudoVLSE16_V_MF4_MASK = 4997 , LIEF::assembly::riscv::PseudoVLSE32_V_M1 = 4998 , LIEF::assembly::riscv::PseudoVLSE32_V_M1_MASK = 4999 ,
  LIEF::assembly::riscv::PseudoVLSE32_V_M2 = 5000 , LIEF::assembly::riscv::PseudoVLSE32_V_M2_MASK = 5001 , LIEF::assembly::riscv::PseudoVLSE32_V_M4 = 5002 , LIEF::assembly::riscv::PseudoVLSE32_V_M4_MASK = 5003 ,
  LIEF::assembly::riscv::PseudoVLSE32_V_M8 = 5004 , LIEF::assembly::riscv::PseudoVLSE32_V_M8_MASK = 5005 , LIEF::assembly::riscv::PseudoVLSE32_V_MF2 = 5006 , LIEF::assembly::riscv::PseudoVLSE32_V_MF2_MASK = 5007 ,
  LIEF::assembly::riscv::PseudoVLSE64_V_M1 = 5008 , LIEF::assembly::riscv::PseudoVLSE64_V_M1_MASK = 5009 , LIEF::assembly::riscv::PseudoVLSE64_V_M2 = 5010 , LIEF::assembly::riscv::PseudoVLSE64_V_M2_MASK = 5011 ,
  LIEF::assembly::riscv::PseudoVLSE64_V_M4 = 5012 , LIEF::assembly::riscv::PseudoVLSE64_V_M4_MASK = 5013 , LIEF::assembly::riscv::PseudoVLSE64_V_M8 = 5014 , LIEF::assembly::riscv::PseudoVLSE64_V_M8_MASK = 5015 ,
  LIEF::assembly::riscv::PseudoVLSE8_V_M1 = 5016 , LIEF::assembly::riscv::PseudoVLSE8_V_M1_MASK = 5017 , LIEF::assembly::riscv::PseudoVLSE8_V_M2 = 5018 , LIEF::assembly::riscv::PseudoVLSE8_V_M2_MASK = 5019 ,
  LIEF::assembly::riscv::PseudoVLSE8_V_M4 = 5020 , LIEF::assembly::riscv::PseudoVLSE8_V_M4_MASK = 5021 , LIEF::assembly::riscv::PseudoVLSE8_V_M8 = 5022 , LIEF::assembly::riscv::PseudoVLSE8_V_M8_MASK = 5023 ,
  LIEF::assembly::riscv::PseudoVLSE8_V_MF2 = 5024 , LIEF::assembly::riscv::PseudoVLSE8_V_MF2_MASK = 5025 , LIEF::assembly::riscv::PseudoVLSE8_V_MF4 = 5026 , LIEF::assembly::riscv::PseudoVLSE8_V_MF4_MASK = 5027 ,
  LIEF::assembly::riscv::PseudoVLSE8_V_MF8 = 5028 , LIEF::assembly::riscv::PseudoVLSE8_V_MF8_MASK = 5029 , LIEF::assembly::riscv::PseudoVLSEG2E16FF_V_M1 = 5030 , LIEF::assembly::riscv::PseudoVLSEG2E16FF_V_M1_MASK = 5031 ,
  LIEF::assembly::riscv::PseudoVLSEG2E16FF_V_M2 = 5032 , LIEF::assembly::riscv::PseudoVLSEG2E16FF_V_M2_MASK = 5033 , LIEF::assembly::riscv::PseudoVLSEG2E16FF_V_M4 = 5034 , LIEF::assembly::riscv::PseudoVLSEG2E16FF_V_M4_MASK = 5035 ,
  LIEF::assembly::riscv::PseudoVLSEG2E16FF_V_MF2 = 5036 , LIEF::assembly::riscv::PseudoVLSEG2E16FF_V_MF2_MASK = 5037 , LIEF::assembly::riscv::PseudoVLSEG2E16FF_V_MF4 = 5038 , LIEF::assembly::riscv::PseudoVLSEG2E16FF_V_MF4_MASK = 5039 ,
  LIEF::assembly::riscv::PseudoVLSEG2E16_V_M1 = 5040 , LIEF::assembly::riscv::PseudoVLSEG2E16_V_M1_MASK = 5041 , LIEF::assembly::riscv::PseudoVLSEG2E16_V_M2 = 5042 , LIEF::assembly::riscv::PseudoVLSEG2E16_V_M2_MASK = 5043 ,
  LIEF::assembly::riscv::PseudoVLSEG2E16_V_M4 = 5044 , LIEF::assembly::riscv::PseudoVLSEG2E16_V_M4_MASK = 5045 , LIEF::assembly::riscv::PseudoVLSEG2E16_V_MF2 = 5046 , LIEF::assembly::riscv::PseudoVLSEG2E16_V_MF2_MASK = 5047 ,
  LIEF::assembly::riscv::PseudoVLSEG2E16_V_MF4 = 5048 , LIEF::assembly::riscv::PseudoVLSEG2E16_V_MF4_MASK = 5049 , LIEF::assembly::riscv::PseudoVLSEG2E32FF_V_M1 = 5050 , LIEF::assembly::riscv::PseudoVLSEG2E32FF_V_M1_MASK = 5051 ,
  LIEF::assembly::riscv::PseudoVLSEG2E32FF_V_M2 = 5052 , LIEF::assembly::riscv::PseudoVLSEG2E32FF_V_M2_MASK = 5053 , LIEF::assembly::riscv::PseudoVLSEG2E32FF_V_M4 = 5054 , LIEF::assembly::riscv::PseudoVLSEG2E32FF_V_M4_MASK = 5055 ,
  LIEF::assembly::riscv::PseudoVLSEG2E32FF_V_MF2 = 5056 , LIEF::assembly::riscv::PseudoVLSEG2E32FF_V_MF2_MASK = 5057 , LIEF::assembly::riscv::PseudoVLSEG2E32_V_M1 = 5058 , LIEF::assembly::riscv::PseudoVLSEG2E32_V_M1_MASK = 5059 ,
  LIEF::assembly::riscv::PseudoVLSEG2E32_V_M2 = 5060 , LIEF::assembly::riscv::PseudoVLSEG2E32_V_M2_MASK = 5061 , LIEF::assembly::riscv::PseudoVLSEG2E32_V_M4 = 5062 , LIEF::assembly::riscv::PseudoVLSEG2E32_V_M4_MASK = 5063 ,
  LIEF::assembly::riscv::PseudoVLSEG2E32_V_MF2 = 5064 , LIEF::assembly::riscv::PseudoVLSEG2E32_V_MF2_MASK = 5065 , LIEF::assembly::riscv::PseudoVLSEG2E64FF_V_M1 = 5066 , LIEF::assembly::riscv::PseudoVLSEG2E64FF_V_M1_MASK = 5067 ,
  LIEF::assembly::riscv::PseudoVLSEG2E64FF_V_M2 = 5068 , LIEF::assembly::riscv::PseudoVLSEG2E64FF_V_M2_MASK = 5069 , LIEF::assembly::riscv::PseudoVLSEG2E64FF_V_M4 = 5070 , LIEF::assembly::riscv::PseudoVLSEG2E64FF_V_M4_MASK = 5071 ,
  LIEF::assembly::riscv::PseudoVLSEG2E64_V_M1 = 5072 , LIEF::assembly::riscv::PseudoVLSEG2E64_V_M1_MASK = 5073 , LIEF::assembly::riscv::PseudoVLSEG2E64_V_M2 = 5074 , LIEF::assembly::riscv::PseudoVLSEG2E64_V_M2_MASK = 5075 ,
  LIEF::assembly::riscv::PseudoVLSEG2E64_V_M4 = 5076 , LIEF::assembly::riscv::PseudoVLSEG2E64_V_M4_MASK = 5077 , LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_M1 = 5078 , LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_M1_MASK = 5079 ,
  LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_M2 = 5080 , LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_M2_MASK = 5081 , LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_M4 = 5082 , LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_M4_MASK = 5083 ,
  LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_MF2 = 5084 , LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_MF2_MASK = 5085 , LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_MF4 = 5086 , LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_MF4_MASK = 5087 ,
  LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_MF8 = 5088 , LIEF::assembly::riscv::PseudoVLSEG2E8FF_V_MF8_MASK = 5089 , LIEF::assembly::riscv::PseudoVLSEG2E8_V_M1 = 5090 , LIEF::assembly::riscv::PseudoVLSEG2E8_V_M1_MASK = 5091 ,
  LIEF::assembly::riscv::PseudoVLSEG2E8_V_M2 = 5092 , LIEF::assembly::riscv::PseudoVLSEG2E8_V_M2_MASK = 5093 , LIEF::assembly::riscv::PseudoVLSEG2E8_V_M4 = 5094 , LIEF::assembly::riscv::PseudoVLSEG2E8_V_M4_MASK = 5095 ,
  LIEF::assembly::riscv::PseudoVLSEG2E8_V_MF2 = 5096 , LIEF::assembly::riscv::PseudoVLSEG2E8_V_MF2_MASK = 5097 , LIEF::assembly::riscv::PseudoVLSEG2E8_V_MF4 = 5098 , LIEF::assembly::riscv::PseudoVLSEG2E8_V_MF4_MASK = 5099 ,
  LIEF::assembly::riscv::PseudoVLSEG2E8_V_MF8 = 5100 , LIEF::assembly::riscv::PseudoVLSEG2E8_V_MF8_MASK = 5101 , LIEF::assembly::riscv::PseudoVLSEG3E16FF_V_M1 = 5102 , LIEF::assembly::riscv::PseudoVLSEG3E16FF_V_M1_MASK = 5103 ,
  LIEF::assembly::riscv::PseudoVLSEG3E16FF_V_M2 = 5104 , LIEF::assembly::riscv::PseudoVLSEG3E16FF_V_M2_MASK = 5105 , LIEF::assembly::riscv::PseudoVLSEG3E16FF_V_MF2 = 5106 , LIEF::assembly::riscv::PseudoVLSEG3E16FF_V_MF2_MASK = 5107 ,
  LIEF::assembly::riscv::PseudoVLSEG3E16FF_V_MF4 = 5108 , LIEF::assembly::riscv::PseudoVLSEG3E16FF_V_MF4_MASK = 5109 , LIEF::assembly::riscv::PseudoVLSEG3E16_V_M1 = 5110 , LIEF::assembly::riscv::PseudoVLSEG3E16_V_M1_MASK = 5111 ,
  LIEF::assembly::riscv::PseudoVLSEG3E16_V_M2 = 5112 , LIEF::assembly::riscv::PseudoVLSEG3E16_V_M2_MASK = 5113 , LIEF::assembly::riscv::PseudoVLSEG3E16_V_MF2 = 5114 , LIEF::assembly::riscv::PseudoVLSEG3E16_V_MF2_MASK = 5115 ,
  LIEF::assembly::riscv::PseudoVLSEG3E16_V_MF4 = 5116 , LIEF::assembly::riscv::PseudoVLSEG3E16_V_MF4_MASK = 5117 , LIEF::assembly::riscv::PseudoVLSEG3E32FF_V_M1 = 5118 , LIEF::assembly::riscv::PseudoVLSEG3E32FF_V_M1_MASK = 5119 ,
  LIEF::assembly::riscv::PseudoVLSEG3E32FF_V_M2 = 5120 , LIEF::assembly::riscv::PseudoVLSEG3E32FF_V_M2_MASK = 5121 , LIEF::assembly::riscv::PseudoVLSEG3E32FF_V_MF2 = 5122 , LIEF::assembly::riscv::PseudoVLSEG3E32FF_V_MF2_MASK = 5123 ,
  LIEF::assembly::riscv::PseudoVLSEG3E32_V_M1 = 5124 , LIEF::assembly::riscv::PseudoVLSEG3E32_V_M1_MASK = 5125 , LIEF::assembly::riscv::PseudoVLSEG3E32_V_M2 = 5126 , LIEF::assembly::riscv::PseudoVLSEG3E32_V_M2_MASK = 5127 ,
  LIEF::assembly::riscv::PseudoVLSEG3E32_V_MF2 = 5128 , LIEF::assembly::riscv::PseudoVLSEG3E32_V_MF2_MASK = 5129 , LIEF::assembly::riscv::PseudoVLSEG3E64FF_V_M1 = 5130 , LIEF::assembly::riscv::PseudoVLSEG3E64FF_V_M1_MASK = 5131 ,
  LIEF::assembly::riscv::PseudoVLSEG3E64FF_V_M2 = 5132 , LIEF::assembly::riscv::PseudoVLSEG3E64FF_V_M2_MASK = 5133 , LIEF::assembly::riscv::PseudoVLSEG3E64_V_M1 = 5134 , LIEF::assembly::riscv::PseudoVLSEG3E64_V_M1_MASK = 5135 ,
  LIEF::assembly::riscv::PseudoVLSEG3E64_V_M2 = 5136 , LIEF::assembly::riscv::PseudoVLSEG3E64_V_M2_MASK = 5137 , LIEF::assembly::riscv::PseudoVLSEG3E8FF_V_M1 = 5138 , LIEF::assembly::riscv::PseudoVLSEG3E8FF_V_M1_MASK = 5139 ,
  LIEF::assembly::riscv::PseudoVLSEG3E8FF_V_M2 = 5140 , LIEF::assembly::riscv::PseudoVLSEG3E8FF_V_M2_MASK = 5141 , LIEF::assembly::riscv::PseudoVLSEG3E8FF_V_MF2 = 5142 , LIEF::assembly::riscv::PseudoVLSEG3E8FF_V_MF2_MASK = 5143 ,
  LIEF::assembly::riscv::PseudoVLSEG3E8FF_V_MF4 = 5144 , LIEF::assembly::riscv::PseudoVLSEG3E8FF_V_MF4_MASK = 5145 , LIEF::assembly::riscv::PseudoVLSEG3E8FF_V_MF8 = 5146 , LIEF::assembly::riscv::PseudoVLSEG3E8FF_V_MF8_MASK = 5147 ,
  LIEF::assembly::riscv::PseudoVLSEG3E8_V_M1 = 5148 , LIEF::assembly::riscv::PseudoVLSEG3E8_V_M1_MASK = 5149 , LIEF::assembly::riscv::PseudoVLSEG3E8_V_M2 = 5150 , LIEF::assembly::riscv::PseudoVLSEG3E8_V_M2_MASK = 5151 ,
  LIEF::assembly::riscv::PseudoVLSEG3E8_V_MF2 = 5152 , LIEF::assembly::riscv::PseudoVLSEG3E8_V_MF2_MASK = 5153 , LIEF::assembly::riscv::PseudoVLSEG3E8_V_MF4 = 5154 , LIEF::assembly::riscv::PseudoVLSEG3E8_V_MF4_MASK = 5155 ,
  LIEF::assembly::riscv::PseudoVLSEG3E8_V_MF8 = 5156 , LIEF::assembly::riscv::PseudoVLSEG3E8_V_MF8_MASK = 5157 , LIEF::assembly::riscv::PseudoVLSEG4E16FF_V_M1 = 5158 , LIEF::assembly::riscv::PseudoVLSEG4E16FF_V_M1_MASK = 5159 ,
  LIEF::assembly::riscv::PseudoVLSEG4E16FF_V_M2 = 5160 , LIEF::assembly::riscv::PseudoVLSEG4E16FF_V_M2_MASK = 5161 , LIEF::assembly::riscv::PseudoVLSEG4E16FF_V_MF2 = 5162 , LIEF::assembly::riscv::PseudoVLSEG4E16FF_V_MF2_MASK = 5163 ,
  LIEF::assembly::riscv::PseudoVLSEG4E16FF_V_MF4 = 5164 , LIEF::assembly::riscv::PseudoVLSEG4E16FF_V_MF4_MASK = 5165 , LIEF::assembly::riscv::PseudoVLSEG4E16_V_M1 = 5166 , LIEF::assembly::riscv::PseudoVLSEG4E16_V_M1_MASK = 5167 ,
  LIEF::assembly::riscv::PseudoVLSEG4E16_V_M2 = 5168 , LIEF::assembly::riscv::PseudoVLSEG4E16_V_M2_MASK = 5169 , LIEF::assembly::riscv::PseudoVLSEG4E16_V_MF2 = 5170 , LIEF::assembly::riscv::PseudoVLSEG4E16_V_MF2_MASK = 5171 ,
  LIEF::assembly::riscv::PseudoVLSEG4E16_V_MF4 = 5172 , LIEF::assembly::riscv::PseudoVLSEG4E16_V_MF4_MASK = 5173 , LIEF::assembly::riscv::PseudoVLSEG4E32FF_V_M1 = 5174 , LIEF::assembly::riscv::PseudoVLSEG4E32FF_V_M1_MASK = 5175 ,
  LIEF::assembly::riscv::PseudoVLSEG4E32FF_V_M2 = 5176 , LIEF::assembly::riscv::PseudoVLSEG4E32FF_V_M2_MASK = 5177 , LIEF::assembly::riscv::PseudoVLSEG4E32FF_V_MF2 = 5178 , LIEF::assembly::riscv::PseudoVLSEG4E32FF_V_MF2_MASK = 5179 ,
  LIEF::assembly::riscv::PseudoVLSEG4E32_V_M1 = 5180 , LIEF::assembly::riscv::PseudoVLSEG4E32_V_M1_MASK = 5181 , LIEF::assembly::riscv::PseudoVLSEG4E32_V_M2 = 5182 , LIEF::assembly::riscv::PseudoVLSEG4E32_V_M2_MASK = 5183 ,
  LIEF::assembly::riscv::PseudoVLSEG4E32_V_MF2 = 5184 , LIEF::assembly::riscv::PseudoVLSEG4E32_V_MF2_MASK = 5185 , LIEF::assembly::riscv::PseudoVLSEG4E64FF_V_M1 = 5186 , LIEF::assembly::riscv::PseudoVLSEG4E64FF_V_M1_MASK = 5187 ,
  LIEF::assembly::riscv::PseudoVLSEG4E64FF_V_M2 = 5188 , LIEF::assembly::riscv::PseudoVLSEG4E64FF_V_M2_MASK = 5189 , LIEF::assembly::riscv::PseudoVLSEG4E64_V_M1 = 5190 , LIEF::assembly::riscv::PseudoVLSEG4E64_V_M1_MASK = 5191 ,
  LIEF::assembly::riscv::PseudoVLSEG4E64_V_M2 = 5192 , LIEF::assembly::riscv::PseudoVLSEG4E64_V_M2_MASK = 5193 , LIEF::assembly::riscv::PseudoVLSEG4E8FF_V_M1 = 5194 , LIEF::assembly::riscv::PseudoVLSEG4E8FF_V_M1_MASK = 5195 ,
  LIEF::assembly::riscv::PseudoVLSEG4E8FF_V_M2 = 5196 , LIEF::assembly::riscv::PseudoVLSEG4E8FF_V_M2_MASK = 5197 , LIEF::assembly::riscv::PseudoVLSEG4E8FF_V_MF2 = 5198 , LIEF::assembly::riscv::PseudoVLSEG4E8FF_V_MF2_MASK = 5199 ,
  LIEF::assembly::riscv::PseudoVLSEG4E8FF_V_MF4 = 5200 , LIEF::assembly::riscv::PseudoVLSEG4E8FF_V_MF4_MASK = 5201 , LIEF::assembly::riscv::PseudoVLSEG4E8FF_V_MF8 = 5202 , LIEF::assembly::riscv::PseudoVLSEG4E8FF_V_MF8_MASK = 5203 ,
  LIEF::assembly::riscv::PseudoVLSEG4E8_V_M1 = 5204 , LIEF::assembly::riscv::PseudoVLSEG4E8_V_M1_MASK = 5205 , LIEF::assembly::riscv::PseudoVLSEG4E8_V_M2 = 5206 , LIEF::assembly::riscv::PseudoVLSEG4E8_V_M2_MASK = 5207 ,
  LIEF::assembly::riscv::PseudoVLSEG4E8_V_MF2 = 5208 , LIEF::assembly::riscv::PseudoVLSEG4E8_V_MF2_MASK = 5209 , LIEF::assembly::riscv::PseudoVLSEG4E8_V_MF4 = 5210 , LIEF::assembly::riscv::PseudoVLSEG4E8_V_MF4_MASK = 5211 ,
  LIEF::assembly::riscv::PseudoVLSEG4E8_V_MF8 = 5212 , LIEF::assembly::riscv::PseudoVLSEG4E8_V_MF8_MASK = 5213 , LIEF::assembly::riscv::PseudoVLSEG5E16FF_V_M1 = 5214 , LIEF::assembly::riscv::PseudoVLSEG5E16FF_V_M1_MASK = 5215 ,
  LIEF::assembly::riscv::PseudoVLSEG5E16FF_V_MF2 = 5216 , LIEF::assembly::riscv::PseudoVLSEG5E16FF_V_MF2_MASK = 5217 , LIEF::assembly::riscv::PseudoVLSEG5E16FF_V_MF4 = 5218 , LIEF::assembly::riscv::PseudoVLSEG5E16FF_V_MF4_MASK = 5219 ,
  LIEF::assembly::riscv::PseudoVLSEG5E16_V_M1 = 5220 , LIEF::assembly::riscv::PseudoVLSEG5E16_V_M1_MASK = 5221 , LIEF::assembly::riscv::PseudoVLSEG5E16_V_MF2 = 5222 , LIEF::assembly::riscv::PseudoVLSEG5E16_V_MF2_MASK = 5223 ,
  LIEF::assembly::riscv::PseudoVLSEG5E16_V_MF4 = 5224 , LIEF::assembly::riscv::PseudoVLSEG5E16_V_MF4_MASK = 5225 , LIEF::assembly::riscv::PseudoVLSEG5E32FF_V_M1 = 5226 , LIEF::assembly::riscv::PseudoVLSEG5E32FF_V_M1_MASK = 5227 ,
  LIEF::assembly::riscv::PseudoVLSEG5E32FF_V_MF2 = 5228 , LIEF::assembly::riscv::PseudoVLSEG5E32FF_V_MF2_MASK = 5229 , LIEF::assembly::riscv::PseudoVLSEG5E32_V_M1 = 5230 , LIEF::assembly::riscv::PseudoVLSEG5E32_V_M1_MASK = 5231 ,
  LIEF::assembly::riscv::PseudoVLSEG5E32_V_MF2 = 5232 , LIEF::assembly::riscv::PseudoVLSEG5E32_V_MF2_MASK = 5233 , LIEF::assembly::riscv::PseudoVLSEG5E64FF_V_M1 = 5234 , LIEF::assembly::riscv::PseudoVLSEG5E64FF_V_M1_MASK = 5235 ,
  LIEF::assembly::riscv::PseudoVLSEG5E64_V_M1 = 5236 , LIEF::assembly::riscv::PseudoVLSEG5E64_V_M1_MASK = 5237 , LIEF::assembly::riscv::PseudoVLSEG5E8FF_V_M1 = 5238 , LIEF::assembly::riscv::PseudoVLSEG5E8FF_V_M1_MASK = 5239 ,
  LIEF::assembly::riscv::PseudoVLSEG5E8FF_V_MF2 = 5240 , LIEF::assembly::riscv::PseudoVLSEG5E8FF_V_MF2_MASK = 5241 , LIEF::assembly::riscv::PseudoVLSEG5E8FF_V_MF4 = 5242 , LIEF::assembly::riscv::PseudoVLSEG5E8FF_V_MF4_MASK = 5243 ,
  LIEF::assembly::riscv::PseudoVLSEG5E8FF_V_MF8 = 5244 , LIEF::assembly::riscv::PseudoVLSEG5E8FF_V_MF8_MASK = 5245 , LIEF::assembly::riscv::PseudoVLSEG5E8_V_M1 = 5246 , LIEF::assembly::riscv::PseudoVLSEG5E8_V_M1_MASK = 5247 ,
  LIEF::assembly::riscv::PseudoVLSEG5E8_V_MF2 = 5248 , LIEF::assembly::riscv::PseudoVLSEG5E8_V_MF2_MASK = 5249 , LIEF::assembly::riscv::PseudoVLSEG5E8_V_MF4 = 5250 , LIEF::assembly::riscv::PseudoVLSEG5E8_V_MF4_MASK = 5251 ,
  LIEF::assembly::riscv::PseudoVLSEG5E8_V_MF8 = 5252 , LIEF::assembly::riscv::PseudoVLSEG5E8_V_MF8_MASK = 5253 , LIEF::assembly::riscv::PseudoVLSEG6E16FF_V_M1 = 5254 , LIEF::assembly::riscv::PseudoVLSEG6E16FF_V_M1_MASK = 5255 ,
  LIEF::assembly::riscv::PseudoVLSEG6E16FF_V_MF2 = 5256 , LIEF::assembly::riscv::PseudoVLSEG6E16FF_V_MF2_MASK = 5257 , LIEF::assembly::riscv::PseudoVLSEG6E16FF_V_MF4 = 5258 , LIEF::assembly::riscv::PseudoVLSEG6E16FF_V_MF4_MASK = 5259 ,
  LIEF::assembly::riscv::PseudoVLSEG6E16_V_M1 = 5260 , LIEF::assembly::riscv::PseudoVLSEG6E16_V_M1_MASK = 5261 , LIEF::assembly::riscv::PseudoVLSEG6E16_V_MF2 = 5262 , LIEF::assembly::riscv::PseudoVLSEG6E16_V_MF2_MASK = 5263 ,
  LIEF::assembly::riscv::PseudoVLSEG6E16_V_MF4 = 5264 , LIEF::assembly::riscv::PseudoVLSEG6E16_V_MF4_MASK = 5265 , LIEF::assembly::riscv::PseudoVLSEG6E32FF_V_M1 = 5266 , LIEF::assembly::riscv::PseudoVLSEG6E32FF_V_M1_MASK = 5267 ,
  LIEF::assembly::riscv::PseudoVLSEG6E32FF_V_MF2 = 5268 , LIEF::assembly::riscv::PseudoVLSEG6E32FF_V_MF2_MASK = 5269 , LIEF::assembly::riscv::PseudoVLSEG6E32_V_M1 = 5270 , LIEF::assembly::riscv::PseudoVLSEG6E32_V_M1_MASK = 5271 ,
  LIEF::assembly::riscv::PseudoVLSEG6E32_V_MF2 = 5272 , LIEF::assembly::riscv::PseudoVLSEG6E32_V_MF2_MASK = 5273 , LIEF::assembly::riscv::PseudoVLSEG6E64FF_V_M1 = 5274 , LIEF::assembly::riscv::PseudoVLSEG6E64FF_V_M1_MASK = 5275 ,
  LIEF::assembly::riscv::PseudoVLSEG6E64_V_M1 = 5276 , LIEF::assembly::riscv::PseudoVLSEG6E64_V_M1_MASK = 5277 , LIEF::assembly::riscv::PseudoVLSEG6E8FF_V_M1 = 5278 , LIEF::assembly::riscv::PseudoVLSEG6E8FF_V_M1_MASK = 5279 ,
  LIEF::assembly::riscv::PseudoVLSEG6E8FF_V_MF2 = 5280 , LIEF::assembly::riscv::PseudoVLSEG6E8FF_V_MF2_MASK = 5281 , LIEF::assembly::riscv::PseudoVLSEG6E8FF_V_MF4 = 5282 , LIEF::assembly::riscv::PseudoVLSEG6E8FF_V_MF4_MASK = 5283 ,
  LIEF::assembly::riscv::PseudoVLSEG6E8FF_V_MF8 = 5284 , LIEF::assembly::riscv::PseudoVLSEG6E8FF_V_MF8_MASK = 5285 , LIEF::assembly::riscv::PseudoVLSEG6E8_V_M1 = 5286 , LIEF::assembly::riscv::PseudoVLSEG6E8_V_M1_MASK = 5287 ,
  LIEF::assembly::riscv::PseudoVLSEG6E8_V_MF2 = 5288 , LIEF::assembly::riscv::PseudoVLSEG6E8_V_MF2_MASK = 5289 , LIEF::assembly::riscv::PseudoVLSEG6E8_V_MF4 = 5290 , LIEF::assembly::riscv::PseudoVLSEG6E8_V_MF4_MASK = 5291 ,
  LIEF::assembly::riscv::PseudoVLSEG6E8_V_MF8 = 5292 , LIEF::assembly::riscv::PseudoVLSEG6E8_V_MF8_MASK = 5293 , LIEF::assembly::riscv::PseudoVLSEG7E16FF_V_M1 = 5294 , LIEF::assembly::riscv::PseudoVLSEG7E16FF_V_M1_MASK = 5295 ,
  LIEF::assembly::riscv::PseudoVLSEG7E16FF_V_MF2 = 5296 , LIEF::assembly::riscv::PseudoVLSEG7E16FF_V_MF2_MASK = 5297 , LIEF::assembly::riscv::PseudoVLSEG7E16FF_V_MF4 = 5298 , LIEF::assembly::riscv::PseudoVLSEG7E16FF_V_MF4_MASK = 5299 ,
  LIEF::assembly::riscv::PseudoVLSEG7E16_V_M1 = 5300 , LIEF::assembly::riscv::PseudoVLSEG7E16_V_M1_MASK = 5301 , LIEF::assembly::riscv::PseudoVLSEG7E16_V_MF2 = 5302 , LIEF::assembly::riscv::PseudoVLSEG7E16_V_MF2_MASK = 5303 ,
  LIEF::assembly::riscv::PseudoVLSEG7E16_V_MF4 = 5304 , LIEF::assembly::riscv::PseudoVLSEG7E16_V_MF4_MASK = 5305 , LIEF::assembly::riscv::PseudoVLSEG7E32FF_V_M1 = 5306 , LIEF::assembly::riscv::PseudoVLSEG7E32FF_V_M1_MASK = 5307 ,
  LIEF::assembly::riscv::PseudoVLSEG7E32FF_V_MF2 = 5308 , LIEF::assembly::riscv::PseudoVLSEG7E32FF_V_MF2_MASK = 5309 , LIEF::assembly::riscv::PseudoVLSEG7E32_V_M1 = 5310 , LIEF::assembly::riscv::PseudoVLSEG7E32_V_M1_MASK = 5311 ,
  LIEF::assembly::riscv::PseudoVLSEG7E32_V_MF2 = 5312 , LIEF::assembly::riscv::PseudoVLSEG7E32_V_MF2_MASK = 5313 , LIEF::assembly::riscv::PseudoVLSEG7E64FF_V_M1 = 5314 , LIEF::assembly::riscv::PseudoVLSEG7E64FF_V_M1_MASK = 5315 ,
  LIEF::assembly::riscv::PseudoVLSEG7E64_V_M1 = 5316 , LIEF::assembly::riscv::PseudoVLSEG7E64_V_M1_MASK = 5317 , LIEF::assembly::riscv::PseudoVLSEG7E8FF_V_M1 = 5318 , LIEF::assembly::riscv::PseudoVLSEG7E8FF_V_M1_MASK = 5319 ,
  LIEF::assembly::riscv::PseudoVLSEG7E8FF_V_MF2 = 5320 , LIEF::assembly::riscv::PseudoVLSEG7E8FF_V_MF2_MASK = 5321 , LIEF::assembly::riscv::PseudoVLSEG7E8FF_V_MF4 = 5322 , LIEF::assembly::riscv::PseudoVLSEG7E8FF_V_MF4_MASK = 5323 ,
  LIEF::assembly::riscv::PseudoVLSEG7E8FF_V_MF8 = 5324 , LIEF::assembly::riscv::PseudoVLSEG7E8FF_V_MF8_MASK = 5325 , LIEF::assembly::riscv::PseudoVLSEG7E8_V_M1 = 5326 , LIEF::assembly::riscv::PseudoVLSEG7E8_V_M1_MASK = 5327 ,
  LIEF::assembly::riscv::PseudoVLSEG7E8_V_MF2 = 5328 , LIEF::assembly::riscv::PseudoVLSEG7E8_V_MF2_MASK = 5329 , LIEF::assembly::riscv::PseudoVLSEG7E8_V_MF4 = 5330 , LIEF::assembly::riscv::PseudoVLSEG7E8_V_MF4_MASK = 5331 ,
  LIEF::assembly::riscv::PseudoVLSEG7E8_V_MF8 = 5332 , LIEF::assembly::riscv::PseudoVLSEG7E8_V_MF8_MASK = 5333 , LIEF::assembly::riscv::PseudoVLSEG8E16FF_V_M1 = 5334 , LIEF::assembly::riscv::PseudoVLSEG8E16FF_V_M1_MASK = 5335 ,
  LIEF::assembly::riscv::PseudoVLSEG8E16FF_V_MF2 = 5336 , LIEF::assembly::riscv::PseudoVLSEG8E16FF_V_MF2_MASK = 5337 , LIEF::assembly::riscv::PseudoVLSEG8E16FF_V_MF4 = 5338 , LIEF::assembly::riscv::PseudoVLSEG8E16FF_V_MF4_MASK = 5339 ,
  LIEF::assembly::riscv::PseudoVLSEG8E16_V_M1 = 5340 , LIEF::assembly::riscv::PseudoVLSEG8E16_V_M1_MASK = 5341 , LIEF::assembly::riscv::PseudoVLSEG8E16_V_MF2 = 5342 , LIEF::assembly::riscv::PseudoVLSEG8E16_V_MF2_MASK = 5343 ,
  LIEF::assembly::riscv::PseudoVLSEG8E16_V_MF4 = 5344 , LIEF::assembly::riscv::PseudoVLSEG8E16_V_MF4_MASK = 5345 , LIEF::assembly::riscv::PseudoVLSEG8E32FF_V_M1 = 5346 , LIEF::assembly::riscv::PseudoVLSEG8E32FF_V_M1_MASK = 5347 ,
  LIEF::assembly::riscv::PseudoVLSEG8E32FF_V_MF2 = 5348 , LIEF::assembly::riscv::PseudoVLSEG8E32FF_V_MF2_MASK = 5349 , LIEF::assembly::riscv::PseudoVLSEG8E32_V_M1 = 5350 , LIEF::assembly::riscv::PseudoVLSEG8E32_V_M1_MASK = 5351 ,
  LIEF::assembly::riscv::PseudoVLSEG8E32_V_MF2 = 5352 , LIEF::assembly::riscv::PseudoVLSEG8E32_V_MF2_MASK = 5353 , LIEF::assembly::riscv::PseudoVLSEG8E64FF_V_M1 = 5354 , LIEF::assembly::riscv::PseudoVLSEG8E64FF_V_M1_MASK = 5355 ,
  LIEF::assembly::riscv::PseudoVLSEG8E64_V_M1 = 5356 , LIEF::assembly::riscv::PseudoVLSEG8E64_V_M1_MASK = 5357 , LIEF::assembly::riscv::PseudoVLSEG8E8FF_V_M1 = 5358 , LIEF::assembly::riscv::PseudoVLSEG8E8FF_V_M1_MASK = 5359 ,
  LIEF::assembly::riscv::PseudoVLSEG8E8FF_V_MF2 = 5360 , LIEF::assembly::riscv::PseudoVLSEG8E8FF_V_MF2_MASK = 5361 , LIEF::assembly::riscv::PseudoVLSEG8E8FF_V_MF4 = 5362 , LIEF::assembly::riscv::PseudoVLSEG8E8FF_V_MF4_MASK = 5363 ,
  LIEF::assembly::riscv::PseudoVLSEG8E8FF_V_MF8 = 5364 , LIEF::assembly::riscv::PseudoVLSEG8E8FF_V_MF8_MASK = 5365 , LIEF::assembly::riscv::PseudoVLSEG8E8_V_M1 = 5366 , LIEF::assembly::riscv::PseudoVLSEG8E8_V_M1_MASK = 5367 ,
  LIEF::assembly::riscv::PseudoVLSEG8E8_V_MF2 = 5368 , LIEF::assembly::riscv::PseudoVLSEG8E8_V_MF2_MASK = 5369 , LIEF::assembly::riscv::PseudoVLSEG8E8_V_MF4 = 5370 , LIEF::assembly::riscv::PseudoVLSEG8E8_V_MF4_MASK = 5371 ,
  LIEF::assembly::riscv::PseudoVLSEG8E8_V_MF8 = 5372 , LIEF::assembly::riscv::PseudoVLSEG8E8_V_MF8_MASK = 5373 , LIEF::assembly::riscv::PseudoVLSSEG2E16_V_M1 = 5374 , LIEF::assembly::riscv::PseudoVLSSEG2E16_V_M1_MASK = 5375 ,
  LIEF::assembly::riscv::PseudoVLSSEG2E16_V_M2 = 5376 , LIEF::assembly::riscv::PseudoVLSSEG2E16_V_M2_MASK = 5377 , LIEF::assembly::riscv::PseudoVLSSEG2E16_V_M4 = 5378 , LIEF::assembly::riscv::PseudoVLSSEG2E16_V_M4_MASK = 5379 ,
  LIEF::assembly::riscv::PseudoVLSSEG2E16_V_MF2 = 5380 , LIEF::assembly::riscv::PseudoVLSSEG2E16_V_MF2_MASK = 5381 , LIEF::assembly::riscv::PseudoVLSSEG2E16_V_MF4 = 5382 , LIEF::assembly::riscv::PseudoVLSSEG2E16_V_MF4_MASK = 5383 ,
  LIEF::assembly::riscv::PseudoVLSSEG2E32_V_M1 = 5384 , LIEF::assembly::riscv::PseudoVLSSEG2E32_V_M1_MASK = 5385 , LIEF::assembly::riscv::PseudoVLSSEG2E32_V_M2 = 5386 , LIEF::assembly::riscv::PseudoVLSSEG2E32_V_M2_MASK = 5387 ,
  LIEF::assembly::riscv::PseudoVLSSEG2E32_V_M4 = 5388 , LIEF::assembly::riscv::PseudoVLSSEG2E32_V_M4_MASK = 5389 , LIEF::assembly::riscv::PseudoVLSSEG2E32_V_MF2 = 5390 , LIEF::assembly::riscv::PseudoVLSSEG2E32_V_MF2_MASK = 5391 ,
  LIEF::assembly::riscv::PseudoVLSSEG2E64_V_M1 = 5392 , LIEF::assembly::riscv::PseudoVLSSEG2E64_V_M1_MASK = 5393 , LIEF::assembly::riscv::PseudoVLSSEG2E64_V_M2 = 5394 , LIEF::assembly::riscv::PseudoVLSSEG2E64_V_M2_MASK = 5395 ,
  LIEF::assembly::riscv::PseudoVLSSEG2E64_V_M4 = 5396 , LIEF::assembly::riscv::PseudoVLSSEG2E64_V_M4_MASK = 5397 , LIEF::assembly::riscv::PseudoVLSSEG2E8_V_M1 = 5398 , LIEF::assembly::riscv::PseudoVLSSEG2E8_V_M1_MASK = 5399 ,
  LIEF::assembly::riscv::PseudoVLSSEG2E8_V_M2 = 5400 , LIEF::assembly::riscv::PseudoVLSSEG2E8_V_M2_MASK = 5401 , LIEF::assembly::riscv::PseudoVLSSEG2E8_V_M4 = 5402 , LIEF::assembly::riscv::PseudoVLSSEG2E8_V_M4_MASK = 5403 ,
  LIEF::assembly::riscv::PseudoVLSSEG2E8_V_MF2 = 5404 , LIEF::assembly::riscv::PseudoVLSSEG2E8_V_MF2_MASK = 5405 , LIEF::assembly::riscv::PseudoVLSSEG2E8_V_MF4 = 5406 , LIEF::assembly::riscv::PseudoVLSSEG2E8_V_MF4_MASK = 5407 ,
  LIEF::assembly::riscv::PseudoVLSSEG2E8_V_MF8 = 5408 , LIEF::assembly::riscv::PseudoVLSSEG2E8_V_MF8_MASK = 5409 , LIEF::assembly::riscv::PseudoVLSSEG3E16_V_M1 = 5410 , LIEF::assembly::riscv::PseudoVLSSEG3E16_V_M1_MASK = 5411 ,
  LIEF::assembly::riscv::PseudoVLSSEG3E16_V_M2 = 5412 , LIEF::assembly::riscv::PseudoVLSSEG3E16_V_M2_MASK = 5413 , LIEF::assembly::riscv::PseudoVLSSEG3E16_V_MF2 = 5414 , LIEF::assembly::riscv::PseudoVLSSEG3E16_V_MF2_MASK = 5415 ,
  LIEF::assembly::riscv::PseudoVLSSEG3E16_V_MF4 = 5416 , LIEF::assembly::riscv::PseudoVLSSEG3E16_V_MF4_MASK = 5417 , LIEF::assembly::riscv::PseudoVLSSEG3E32_V_M1 = 5418 , LIEF::assembly::riscv::PseudoVLSSEG3E32_V_M1_MASK = 5419 ,
  LIEF::assembly::riscv::PseudoVLSSEG3E32_V_M2 = 5420 , LIEF::assembly::riscv::PseudoVLSSEG3E32_V_M2_MASK = 5421 , LIEF::assembly::riscv::PseudoVLSSEG3E32_V_MF2 = 5422 , LIEF::assembly::riscv::PseudoVLSSEG3E32_V_MF2_MASK = 5423 ,
  LIEF::assembly::riscv::PseudoVLSSEG3E64_V_M1 = 5424 , LIEF::assembly::riscv::PseudoVLSSEG3E64_V_M1_MASK = 5425 , LIEF::assembly::riscv::PseudoVLSSEG3E64_V_M2 = 5426 , LIEF::assembly::riscv::PseudoVLSSEG3E64_V_M2_MASK = 5427 ,
  LIEF::assembly::riscv::PseudoVLSSEG3E8_V_M1 = 5428 , LIEF::assembly::riscv::PseudoVLSSEG3E8_V_M1_MASK = 5429 , LIEF::assembly::riscv::PseudoVLSSEG3E8_V_M2 = 5430 , LIEF::assembly::riscv::PseudoVLSSEG3E8_V_M2_MASK = 5431 ,
  LIEF::assembly::riscv::PseudoVLSSEG3E8_V_MF2 = 5432 , LIEF::assembly::riscv::PseudoVLSSEG3E8_V_MF2_MASK = 5433 , LIEF::assembly::riscv::PseudoVLSSEG3E8_V_MF4 = 5434 , LIEF::assembly::riscv::PseudoVLSSEG3E8_V_MF4_MASK = 5435 ,
  LIEF::assembly::riscv::PseudoVLSSEG3E8_V_MF8 = 5436 , LIEF::assembly::riscv::PseudoVLSSEG3E8_V_MF8_MASK = 5437 , LIEF::assembly::riscv::PseudoVLSSEG4E16_V_M1 = 5438 , LIEF::assembly::riscv::PseudoVLSSEG4E16_V_M1_MASK = 5439 ,
  LIEF::assembly::riscv::PseudoVLSSEG4E16_V_M2 = 5440 , LIEF::assembly::riscv::PseudoVLSSEG4E16_V_M2_MASK = 5441 , LIEF::assembly::riscv::PseudoVLSSEG4E16_V_MF2 = 5442 , LIEF::assembly::riscv::PseudoVLSSEG4E16_V_MF2_MASK = 5443 ,
  LIEF::assembly::riscv::PseudoVLSSEG4E16_V_MF4 = 5444 , LIEF::assembly::riscv::PseudoVLSSEG4E16_V_MF4_MASK = 5445 , LIEF::assembly::riscv::PseudoVLSSEG4E32_V_M1 = 5446 , LIEF::assembly::riscv::PseudoVLSSEG4E32_V_M1_MASK = 5447 ,
  LIEF::assembly::riscv::PseudoVLSSEG4E32_V_M2 = 5448 , LIEF::assembly::riscv::PseudoVLSSEG4E32_V_M2_MASK = 5449 , LIEF::assembly::riscv::PseudoVLSSEG4E32_V_MF2 = 5450 , LIEF::assembly::riscv::PseudoVLSSEG4E32_V_MF2_MASK = 5451 ,
  LIEF::assembly::riscv::PseudoVLSSEG4E64_V_M1 = 5452 , LIEF::assembly::riscv::PseudoVLSSEG4E64_V_M1_MASK = 5453 , LIEF::assembly::riscv::PseudoVLSSEG4E64_V_M2 = 5454 , LIEF::assembly::riscv::PseudoVLSSEG4E64_V_M2_MASK = 5455 ,
  LIEF::assembly::riscv::PseudoVLSSEG4E8_V_M1 = 5456 , LIEF::assembly::riscv::PseudoVLSSEG4E8_V_M1_MASK = 5457 , LIEF::assembly::riscv::PseudoVLSSEG4E8_V_M2 = 5458 , LIEF::assembly::riscv::PseudoVLSSEG4E8_V_M2_MASK = 5459 ,
  LIEF::assembly::riscv::PseudoVLSSEG4E8_V_MF2 = 5460 , LIEF::assembly::riscv::PseudoVLSSEG4E8_V_MF2_MASK = 5461 , LIEF::assembly::riscv::PseudoVLSSEG4E8_V_MF4 = 5462 , LIEF::assembly::riscv::PseudoVLSSEG4E8_V_MF4_MASK = 5463 ,
  LIEF::assembly::riscv::PseudoVLSSEG4E8_V_MF8 = 5464 , LIEF::assembly::riscv::PseudoVLSSEG4E8_V_MF8_MASK = 5465 , LIEF::assembly::riscv::PseudoVLSSEG5E16_V_M1 = 5466 , LIEF::assembly::riscv::PseudoVLSSEG5E16_V_M1_MASK = 5467 ,
  LIEF::assembly::riscv::PseudoVLSSEG5E16_V_MF2 = 5468 , LIEF::assembly::riscv::PseudoVLSSEG5E16_V_MF2_MASK = 5469 , LIEF::assembly::riscv::PseudoVLSSEG5E16_V_MF4 = 5470 , LIEF::assembly::riscv::PseudoVLSSEG5E16_V_MF4_MASK = 5471 ,
  LIEF::assembly::riscv::PseudoVLSSEG5E32_V_M1 = 5472 , LIEF::assembly::riscv::PseudoVLSSEG5E32_V_M1_MASK = 5473 , LIEF::assembly::riscv::PseudoVLSSEG5E32_V_MF2 = 5474 , LIEF::assembly::riscv::PseudoVLSSEG5E32_V_MF2_MASK = 5475 ,
  LIEF::assembly::riscv::PseudoVLSSEG5E64_V_M1 = 5476 , LIEF::assembly::riscv::PseudoVLSSEG5E64_V_M1_MASK = 5477 , LIEF::assembly::riscv::PseudoVLSSEG5E8_V_M1 = 5478 , LIEF::assembly::riscv::PseudoVLSSEG5E8_V_M1_MASK = 5479 ,
  LIEF::assembly::riscv::PseudoVLSSEG5E8_V_MF2 = 5480 , LIEF::assembly::riscv::PseudoVLSSEG5E8_V_MF2_MASK = 5481 , LIEF::assembly::riscv::PseudoVLSSEG5E8_V_MF4 = 5482 , LIEF::assembly::riscv::PseudoVLSSEG5E8_V_MF4_MASK = 5483 ,
  LIEF::assembly::riscv::PseudoVLSSEG5E8_V_MF8 = 5484 , LIEF::assembly::riscv::PseudoVLSSEG5E8_V_MF8_MASK = 5485 , LIEF::assembly::riscv::PseudoVLSSEG6E16_V_M1 = 5486 , LIEF::assembly::riscv::PseudoVLSSEG6E16_V_M1_MASK = 5487 ,
  LIEF::assembly::riscv::PseudoVLSSEG6E16_V_MF2 = 5488 , LIEF::assembly::riscv::PseudoVLSSEG6E16_V_MF2_MASK = 5489 , LIEF::assembly::riscv::PseudoVLSSEG6E16_V_MF4 = 5490 , LIEF::assembly::riscv::PseudoVLSSEG6E16_V_MF4_MASK = 5491 ,
  LIEF::assembly::riscv::PseudoVLSSEG6E32_V_M1 = 5492 , LIEF::assembly::riscv::PseudoVLSSEG6E32_V_M1_MASK = 5493 , LIEF::assembly::riscv::PseudoVLSSEG6E32_V_MF2 = 5494 , LIEF::assembly::riscv::PseudoVLSSEG6E32_V_MF2_MASK = 5495 ,
  LIEF::assembly::riscv::PseudoVLSSEG6E64_V_M1 = 5496 , LIEF::assembly::riscv::PseudoVLSSEG6E64_V_M1_MASK = 5497 , LIEF::assembly::riscv::PseudoVLSSEG6E8_V_M1 = 5498 , LIEF::assembly::riscv::PseudoVLSSEG6E8_V_M1_MASK = 5499 ,
  LIEF::assembly::riscv::PseudoVLSSEG6E8_V_MF2 = 5500 , LIEF::assembly::riscv::PseudoVLSSEG6E8_V_MF2_MASK = 5501 , LIEF::assembly::riscv::PseudoVLSSEG6E8_V_MF4 = 5502 , LIEF::assembly::riscv::PseudoVLSSEG6E8_V_MF4_MASK = 5503 ,
  LIEF::assembly::riscv::PseudoVLSSEG6E8_V_MF8 = 5504 , LIEF::assembly::riscv::PseudoVLSSEG6E8_V_MF8_MASK = 5505 , LIEF::assembly::riscv::PseudoVLSSEG7E16_V_M1 = 5506 , LIEF::assembly::riscv::PseudoVLSSEG7E16_V_M1_MASK = 5507 ,
  LIEF::assembly::riscv::PseudoVLSSEG7E16_V_MF2 = 5508 , LIEF::assembly::riscv::PseudoVLSSEG7E16_V_MF2_MASK = 5509 , LIEF::assembly::riscv::PseudoVLSSEG7E16_V_MF4 = 5510 , LIEF::assembly::riscv::PseudoVLSSEG7E16_V_MF4_MASK = 5511 ,
  LIEF::assembly::riscv::PseudoVLSSEG7E32_V_M1 = 5512 , LIEF::assembly::riscv::PseudoVLSSEG7E32_V_M1_MASK = 5513 , LIEF::assembly::riscv::PseudoVLSSEG7E32_V_MF2 = 5514 , LIEF::assembly::riscv::PseudoVLSSEG7E32_V_MF2_MASK = 5515 ,
  LIEF::assembly::riscv::PseudoVLSSEG7E64_V_M1 = 5516 , LIEF::assembly::riscv::PseudoVLSSEG7E64_V_M1_MASK = 5517 , LIEF::assembly::riscv::PseudoVLSSEG7E8_V_M1 = 5518 , LIEF::assembly::riscv::PseudoVLSSEG7E8_V_M1_MASK = 5519 ,
  LIEF::assembly::riscv::PseudoVLSSEG7E8_V_MF2 = 5520 , LIEF::assembly::riscv::PseudoVLSSEG7E8_V_MF2_MASK = 5521 , LIEF::assembly::riscv::PseudoVLSSEG7E8_V_MF4 = 5522 , LIEF::assembly::riscv::PseudoVLSSEG7E8_V_MF4_MASK = 5523 ,
  LIEF::assembly::riscv::PseudoVLSSEG7E8_V_MF8 = 5524 , LIEF::assembly::riscv::PseudoVLSSEG7E8_V_MF8_MASK = 5525 , LIEF::assembly::riscv::PseudoVLSSEG8E16_V_M1 = 5526 , LIEF::assembly::riscv::PseudoVLSSEG8E16_V_M1_MASK = 5527 ,
  LIEF::assembly::riscv::PseudoVLSSEG8E16_V_MF2 = 5528 , LIEF::assembly::riscv::PseudoVLSSEG8E16_V_MF2_MASK = 5529 , LIEF::assembly::riscv::PseudoVLSSEG8E16_V_MF4 = 5530 , LIEF::assembly::riscv::PseudoVLSSEG8E16_V_MF4_MASK = 5531 ,
  LIEF::assembly::riscv::PseudoVLSSEG8E32_V_M1 = 5532 , LIEF::assembly::riscv::PseudoVLSSEG8E32_V_M1_MASK = 5533 , LIEF::assembly::riscv::PseudoVLSSEG8E32_V_MF2 = 5534 , LIEF::assembly::riscv::PseudoVLSSEG8E32_V_MF2_MASK = 5535 ,
  LIEF::assembly::riscv::PseudoVLSSEG8E64_V_M1 = 5536 , LIEF::assembly::riscv::PseudoVLSSEG8E64_V_M1_MASK = 5537 , LIEF::assembly::riscv::PseudoVLSSEG8E8_V_M1 = 5538 , LIEF::assembly::riscv::PseudoVLSSEG8E8_V_M1_MASK = 5539 ,
  LIEF::assembly::riscv::PseudoVLSSEG8E8_V_MF2 = 5540 , LIEF::assembly::riscv::PseudoVLSSEG8E8_V_MF2_MASK = 5541 , LIEF::assembly::riscv::PseudoVLSSEG8E8_V_MF4 = 5542 , LIEF::assembly::riscv::PseudoVLSSEG8E8_V_MF4_MASK = 5543 ,
  LIEF::assembly::riscv::PseudoVLSSEG8E8_V_MF8 = 5544 , LIEF::assembly::riscv::PseudoVLSSEG8E8_V_MF8_MASK = 5545 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M1_M1 = 5546 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M1_M1_MASK = 5547 ,
  LIEF::assembly::riscv::PseudoVLUXEI16_V_M1_M2 = 5548 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M1_M2_MASK = 5549 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M1_M4 = 5550 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M1_M4_MASK = 5551 ,
  LIEF::assembly::riscv::PseudoVLUXEI16_V_M1_MF2 = 5552 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M1_MF2_MASK = 5553 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M2_M1 = 5554 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M2_M1_MASK = 5555 ,
  LIEF::assembly::riscv::PseudoVLUXEI16_V_M2_M2 = 5556 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M2_M2_MASK = 5557 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M2_M4 = 5558 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M2_M4_MASK = 5559 ,
  LIEF::assembly::riscv::PseudoVLUXEI16_V_M2_M8 = 5560 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M2_M8_MASK = 5561 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M4_M2 = 5562 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M4_M2_MASK = 5563 ,
  LIEF::assembly::riscv::PseudoVLUXEI16_V_M4_M4 = 5564 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M4_M4_MASK = 5565 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M4_M8 = 5566 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M4_M8_MASK = 5567 ,
  LIEF::assembly::riscv::PseudoVLUXEI16_V_M8_M4 = 5568 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M8_M4_MASK = 5569 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M8_M8 = 5570 , LIEF::assembly::riscv::PseudoVLUXEI16_V_M8_M8_MASK = 5571 ,
  LIEF::assembly::riscv::PseudoVLUXEI16_V_MF2_M1 = 5572 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF2_M1_MASK = 5573 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF2_M2 = 5574 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF2_M2_MASK = 5575 ,
  LIEF::assembly::riscv::PseudoVLUXEI16_V_MF2_MF2 = 5576 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF2_MF2_MASK = 5577 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF2_MF4 = 5578 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF2_MF4_MASK = 5579 ,
  LIEF::assembly::riscv::PseudoVLUXEI16_V_MF4_M1 = 5580 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF4_M1_MASK = 5581 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF4_MF2 = 5582 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF4_MF2_MASK = 5583 ,
  LIEF::assembly::riscv::PseudoVLUXEI16_V_MF4_MF4 = 5584 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF4_MF4_MASK = 5585 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF4_MF8 = 5586 , LIEF::assembly::riscv::PseudoVLUXEI16_V_MF4_MF8_MASK = 5587 ,
  LIEF::assembly::riscv::PseudoVLUXEI32_V_M1_M1 = 5588 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M1_M1_MASK = 5589 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M1_M2 = 5590 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M1_M2_MASK = 5591 ,
  LIEF::assembly::riscv::PseudoVLUXEI32_V_M1_MF2 = 5592 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M1_MF2_MASK = 5593 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M1_MF4 = 5594 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M1_MF4_MASK = 5595 ,
  LIEF::assembly::riscv::PseudoVLUXEI32_V_M2_M1 = 5596 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M2_M1_MASK = 5597 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M2_M2 = 5598 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M2_M2_MASK = 5599 ,
  LIEF::assembly::riscv::PseudoVLUXEI32_V_M2_M4 = 5600 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M2_M4_MASK = 5601 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M2_MF2 = 5602 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M2_MF2_MASK = 5603 ,
  LIEF::assembly::riscv::PseudoVLUXEI32_V_M4_M1 = 5604 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M4_M1_MASK = 5605 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M4_M2 = 5606 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M4_M2_MASK = 5607 ,
  LIEF::assembly::riscv::PseudoVLUXEI32_V_M4_M4 = 5608 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M4_M4_MASK = 5609 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M4_M8 = 5610 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M4_M8_MASK = 5611 ,
  LIEF::assembly::riscv::PseudoVLUXEI32_V_M8_M2 = 5612 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M8_M2_MASK = 5613 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M8_M4 = 5614 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M8_M4_MASK = 5615 ,
  LIEF::assembly::riscv::PseudoVLUXEI32_V_M8_M8 = 5616 , LIEF::assembly::riscv::PseudoVLUXEI32_V_M8_M8_MASK = 5617 , LIEF::assembly::riscv::PseudoVLUXEI32_V_MF2_M1 = 5618 , LIEF::assembly::riscv::PseudoVLUXEI32_V_MF2_M1_MASK = 5619 ,
  LIEF::assembly::riscv::PseudoVLUXEI32_V_MF2_MF2 = 5620 , LIEF::assembly::riscv::PseudoVLUXEI32_V_MF2_MF2_MASK = 5621 , LIEF::assembly::riscv::PseudoVLUXEI32_V_MF2_MF4 = 5622 , LIEF::assembly::riscv::PseudoVLUXEI32_V_MF2_MF4_MASK = 5623 ,
  LIEF::assembly::riscv::PseudoVLUXEI32_V_MF2_MF8 = 5624 , LIEF::assembly::riscv::PseudoVLUXEI32_V_MF2_MF8_MASK = 5625 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M1_M1 = 5626 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M1_M1_MASK = 5627 ,
  LIEF::assembly::riscv::PseudoVLUXEI64_V_M1_MF2 = 5628 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M1_MF2_MASK = 5629 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M1_MF4 = 5630 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M1_MF4_MASK = 5631 ,
  LIEF::assembly::riscv::PseudoVLUXEI64_V_M1_MF8 = 5632 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M1_MF8_MASK = 5633 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M2_M1 = 5634 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M2_M1_MASK = 5635 ,
  LIEF::assembly::riscv::PseudoVLUXEI64_V_M2_M2 = 5636 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M2_M2_MASK = 5637 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M2_MF2 = 5638 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M2_MF2_MASK = 5639 ,
  LIEF::assembly::riscv::PseudoVLUXEI64_V_M2_MF4 = 5640 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M2_MF4_MASK = 5641 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M4_M1 = 5642 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M4_M1_MASK = 5643 ,
  LIEF::assembly::riscv::PseudoVLUXEI64_V_M4_M2 = 5644 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M4_M2_MASK = 5645 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M4_M4 = 5646 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M4_M4_MASK = 5647 ,
  LIEF::assembly::riscv::PseudoVLUXEI64_V_M4_MF2 = 5648 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M4_MF2_MASK = 5649 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M8_M1 = 5650 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M8_M1_MASK = 5651 ,
  LIEF::assembly::riscv::PseudoVLUXEI64_V_M8_M2 = 5652 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M8_M2_MASK = 5653 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M8_M4 = 5654 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M8_M4_MASK = 5655 ,
  LIEF::assembly::riscv::PseudoVLUXEI64_V_M8_M8 = 5656 , LIEF::assembly::riscv::PseudoVLUXEI64_V_M8_M8_MASK = 5657 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M1_M1 = 5658 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M1_M1_MASK = 5659 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_M1_M2 = 5660 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M1_M2_MASK = 5661 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M1_M4 = 5662 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M1_M4_MASK = 5663 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_M1_M8 = 5664 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M1_M8_MASK = 5665 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M2_M2 = 5666 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M2_M2_MASK = 5667 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_M2_M4 = 5668 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M2_M4_MASK = 5669 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M2_M8 = 5670 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M2_M8_MASK = 5671 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_M4_M4 = 5672 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M4_M4_MASK = 5673 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M4_M8 = 5674 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M4_M8_MASK = 5675 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_M8_M8 = 5676 , LIEF::assembly::riscv::PseudoVLUXEI8_V_M8_M8_MASK = 5677 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF2_M1 = 5678 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF2_M1_MASK = 5679 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_MF2_M2 = 5680 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF2_M2_MASK = 5681 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF2_M4 = 5682 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF2_M4_MASK = 5683 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_MF2_MF2 = 5684 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF2_MF2_MASK = 5685 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF4_M1 = 5686 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF4_M1_MASK = 5687 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_MF4_M2 = 5688 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF4_M2_MASK = 5689 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF4_MF2 = 5690 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF4_MF2_MASK = 5691 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_MF4_MF4 = 5692 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF4_MF4_MASK = 5693 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF8_M1 = 5694 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF8_M1_MASK = 5695 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_MF8_MF2 = 5696 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF8_MF2_MASK = 5697 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF8_MF4 = 5698 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF8_MF4_MASK = 5699 ,
  LIEF::assembly::riscv::PseudoVLUXEI8_V_MF8_MF8 = 5700 , LIEF::assembly::riscv::PseudoVLUXEI8_V_MF8_MF8_MASK = 5701 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M1_M1 = 5702 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M1_M1_MASK = 5703 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M1_M2 = 5704 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M1_M2_MASK = 5705 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M1_M4 = 5706 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M1_M4_MASK = 5707 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M1_MF2 = 5708 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M1_MF2_MASK = 5709 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M2_M1 = 5710 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M2_M1_MASK = 5711 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M2_M2 = 5712 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M2_M2_MASK = 5713 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M2_M4 = 5714 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M2_M4_MASK = 5715 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M4_M2 = 5716 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M4_M2_MASK = 5717 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M4_M4 = 5718 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M4_M4_MASK = 5719 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M8_M4 = 5720 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_M8_M4_MASK = 5721 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF2_M1 = 5722 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF2_M1_MASK = 5723 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF2_M2 = 5724 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF2_M2_MASK = 5725 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF2_MF2 = 5726 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF2_MF2_MASK = 5727 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF2_MF4 = 5728 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF2_MF4_MASK = 5729 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF4_M1 = 5730 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF4_M1_MASK = 5731 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF4_MF2 = 5732 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF4_MF2_MASK = 5733 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF4_MF4 = 5734 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF4_MF4_MASK = 5735 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF4_MF8 = 5736 , LIEF::assembly::riscv::PseudoVLUXSEG2EI16_V_MF4_MF8_MASK = 5737 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M1_M1 = 5738 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M1_M1_MASK = 5739 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M1_M2 = 5740 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M1_M2_MASK = 5741 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M1_MF2 = 5742 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M1_MF2_MASK = 5743 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M1_MF4 = 5744 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M1_MF4_MASK = 5745 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M2_M1 = 5746 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M2_M1_MASK = 5747 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M2_M2 = 5748 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M2_M2_MASK = 5749 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M2_M4 = 5750 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M2_M4_MASK = 5751 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M2_MF2 = 5752 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M2_MF2_MASK = 5753 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M4_M1 = 5754 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M4_M1_MASK = 5755 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M4_M2 = 5756 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M4_M2_MASK = 5757 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M4_M4 = 5758 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M4_M4_MASK = 5759 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M8_M2 = 5760 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M8_M2_MASK = 5761 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M8_M4 = 5762 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_M8_M4_MASK = 5763 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_MF2_M1 = 5764 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_MF2_M1_MASK = 5765 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_MF2_MF2 = 5766 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_MF2_MF2_MASK = 5767 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_MF2_MF4 = 5768 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_MF2_MF4_MASK = 5769 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_MF2_MF8 = 5770 , LIEF::assembly::riscv::PseudoVLUXSEG2EI32_V_MF2_MF8_MASK = 5771 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M1_M1 = 5772 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M1_M1_MASK = 5773 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M1_MF2 = 5774 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M1_MF2_MASK = 5775 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M1_MF4 = 5776 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M1_MF4_MASK = 5777 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M1_MF8 = 5778 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M1_MF8_MASK = 5779 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M2_M1 = 5780 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M2_M1_MASK = 5781 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M2_M2 = 5782 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M2_M2_MASK = 5783 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M2_MF2 = 5784 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M2_MF2_MASK = 5785 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M2_MF4 = 5786 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M2_MF4_MASK = 5787 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M4_M1 = 5788 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M4_M1_MASK = 5789 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M4_M2 = 5790 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M4_M2_MASK = 5791 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M4_M4 = 5792 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M4_M4_MASK = 5793 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M4_MF2 = 5794 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M4_MF2_MASK = 5795 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M8_M1 = 5796 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M8_M1_MASK = 5797 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M8_M2 = 5798 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M8_M2_MASK = 5799 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M8_M4 = 5800 , LIEF::assembly::riscv::PseudoVLUXSEG2EI64_V_M8_M4_MASK = 5801 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M1_M1 = 5802 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M1_M1_MASK = 5803 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M1_M2 = 5804 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M1_M2_MASK = 5805 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M1_M4 = 5806 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M1_M4_MASK = 5807 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M2_M2 = 5808 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M2_M2_MASK = 5809 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M2_M4 = 5810 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M2_M4_MASK = 5811 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M4_M4 = 5812 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_M4_M4_MASK = 5813 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF2_M1 = 5814 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF2_M1_MASK = 5815 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF2_M2 = 5816 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF2_M2_MASK = 5817 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF2_M4 = 5818 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF2_M4_MASK = 5819 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF2_MF2 = 5820 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF2_MF2_MASK = 5821 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF4_M1 = 5822 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF4_M1_MASK = 5823 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF4_M2 = 5824 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF4_M2_MASK = 5825 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF4_MF2 = 5826 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF4_MF2_MASK = 5827 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF4_MF4 = 5828 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF4_MF4_MASK = 5829 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF8_M1 = 5830 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF8_M1_MASK = 5831 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF8_MF2 = 5832 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF8_MF2_MASK = 5833 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF8_MF4 = 5834 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF8_MF4_MASK = 5835 ,
  LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF8_MF8 = 5836 , LIEF::assembly::riscv::PseudoVLUXSEG2EI8_V_MF8_MF8_MASK = 5837 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M1_M1 = 5838 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M1_M1_MASK = 5839 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M1_M2 = 5840 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M1_M2_MASK = 5841 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M1_MF2 = 5842 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M1_MF2_MASK = 5843 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M2_M1 = 5844 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M2_M1_MASK = 5845 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M2_M2 = 5846 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M2_M2_MASK = 5847 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M4_M2 = 5848 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_M4_M2_MASK = 5849 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF2_M1 = 5850 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF2_M1_MASK = 5851 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF2_M2 = 5852 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF2_M2_MASK = 5853 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF2_MF2 = 5854 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF2_MF2_MASK = 5855 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF2_MF4 = 5856 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF2_MF4_MASK = 5857 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF4_M1 = 5858 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF4_M1_MASK = 5859 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF4_MF2 = 5860 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF4_MF2_MASK = 5861 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF4_MF4 = 5862 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF4_MF4_MASK = 5863 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF4_MF8 = 5864 , LIEF::assembly::riscv::PseudoVLUXSEG3EI16_V_MF4_MF8_MASK = 5865 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M1_M1 = 5866 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M1_M1_MASK = 5867 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M1_M2 = 5868 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M1_M2_MASK = 5869 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M1_MF2 = 5870 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M1_MF2_MASK = 5871 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M1_MF4 = 5872 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M1_MF4_MASK = 5873 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M2_M1 = 5874 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M2_M1_MASK = 5875 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M2_M2 = 5876 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M2_M2_MASK = 5877 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M2_MF2 = 5878 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M2_MF2_MASK = 5879 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M4_M1 = 5880 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M4_M1_MASK = 5881 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M4_M2 = 5882 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M4_M2_MASK = 5883 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M8_M2 = 5884 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_M8_M2_MASK = 5885 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_MF2_M1 = 5886 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_MF2_M1_MASK = 5887 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_MF2_MF2 = 5888 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_MF2_MF2_MASK = 5889 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_MF2_MF4 = 5890 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_MF2_MF4_MASK = 5891 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_MF2_MF8 = 5892 , LIEF::assembly::riscv::PseudoVLUXSEG3EI32_V_MF2_MF8_MASK = 5893 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M1_M1 = 5894 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M1_M1_MASK = 5895 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M1_MF2 = 5896 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M1_MF2_MASK = 5897 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M1_MF4 = 5898 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M1_MF4_MASK = 5899 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M1_MF8 = 5900 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M1_MF8_MASK = 5901 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M2_M1 = 5902 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M2_M1_MASK = 5903 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M2_M2 = 5904 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M2_M2_MASK = 5905 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M2_MF2 = 5906 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M2_MF2_MASK = 5907 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M2_MF4 = 5908 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M2_MF4_MASK = 5909 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M4_M1 = 5910 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M4_M1_MASK = 5911 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M4_M2 = 5912 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M4_M2_MASK = 5913 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M4_MF2 = 5914 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M4_MF2_MASK = 5915 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M8_M1 = 5916 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M8_M1_MASK = 5917 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M8_M2 = 5918 , LIEF::assembly::riscv::PseudoVLUXSEG3EI64_V_M8_M2_MASK = 5919 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_M1_M1 = 5920 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_M1_M1_MASK = 5921 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_M1_M2 = 5922 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_M1_M2_MASK = 5923 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_M2_M2 = 5924 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_M2_M2_MASK = 5925 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF2_M1 = 5926 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF2_M1_MASK = 5927 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF2_M2 = 5928 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF2_M2_MASK = 5929 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF2_MF2 = 5930 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF2_MF2_MASK = 5931 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF4_M1 = 5932 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF4_M1_MASK = 5933 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF4_M2 = 5934 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF4_M2_MASK = 5935 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF4_MF2 = 5936 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF4_MF2_MASK = 5937 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF4_MF4 = 5938 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF4_MF4_MASK = 5939 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF8_M1 = 5940 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF8_M1_MASK = 5941 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF8_MF2 = 5942 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF8_MF2_MASK = 5943 ,
  LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF8_MF4 = 5944 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF8_MF4_MASK = 5945 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF8_MF8 = 5946 , LIEF::assembly::riscv::PseudoVLUXSEG3EI8_V_MF8_MF8_MASK = 5947 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M1_M1 = 5948 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M1_M1_MASK = 5949 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M1_M2 = 5950 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M1_M2_MASK = 5951 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M1_MF2 = 5952 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M1_MF2_MASK = 5953 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M2_M1 = 5954 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M2_M1_MASK = 5955 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M2_M2 = 5956 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M2_M2_MASK = 5957 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M4_M2 = 5958 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_M4_M2_MASK = 5959 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF2_M1 = 5960 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF2_M1_MASK = 5961 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF2_M2 = 5962 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF2_M2_MASK = 5963 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF2_MF2 = 5964 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF2_MF2_MASK = 5965 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF2_MF4 = 5966 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF2_MF4_MASK = 5967 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF4_M1 = 5968 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF4_M1_MASK = 5969 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF4_MF2 = 5970 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF4_MF2_MASK = 5971 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF4_MF4 = 5972 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF4_MF4_MASK = 5973 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF4_MF8 = 5974 , LIEF::assembly::riscv::PseudoVLUXSEG4EI16_V_MF4_MF8_MASK = 5975 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M1_M1 = 5976 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M1_M1_MASK = 5977 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M1_M2 = 5978 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M1_M2_MASK = 5979 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M1_MF2 = 5980 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M1_MF2_MASK = 5981 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M1_MF4 = 5982 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M1_MF4_MASK = 5983 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M2_M1 = 5984 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M2_M1_MASK = 5985 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M2_M2 = 5986 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M2_M2_MASK = 5987 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M2_MF2 = 5988 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M2_MF2_MASK = 5989 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M4_M1 = 5990 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M4_M1_MASK = 5991 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M4_M2 = 5992 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M4_M2_MASK = 5993 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M8_M2 = 5994 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_M8_M2_MASK = 5995 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_MF2_M1 = 5996 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_MF2_M1_MASK = 5997 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_MF2_MF2 = 5998 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_MF2_MF2_MASK = 5999 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_MF2_MF4 = 6000 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_MF2_MF4_MASK = 6001 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_MF2_MF8 = 6002 , LIEF::assembly::riscv::PseudoVLUXSEG4EI32_V_MF2_MF8_MASK = 6003 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M1_M1 = 6004 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M1_M1_MASK = 6005 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M1_MF2 = 6006 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M1_MF2_MASK = 6007 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M1_MF4 = 6008 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M1_MF4_MASK = 6009 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M1_MF8 = 6010 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M1_MF8_MASK = 6011 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M2_M1 = 6012 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M2_M1_MASK = 6013 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M2_M2 = 6014 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M2_M2_MASK = 6015 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M2_MF2 = 6016 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M2_MF2_MASK = 6017 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M2_MF4 = 6018 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M2_MF4_MASK = 6019 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M4_M1 = 6020 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M4_M1_MASK = 6021 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M4_M2 = 6022 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M4_M2_MASK = 6023 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M4_MF2 = 6024 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M4_MF2_MASK = 6025 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M8_M1 = 6026 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M8_M1_MASK = 6027 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M8_M2 = 6028 , LIEF::assembly::riscv::PseudoVLUXSEG4EI64_V_M8_M2_MASK = 6029 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_M1_M1 = 6030 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_M1_M1_MASK = 6031 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_M1_M2 = 6032 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_M1_M2_MASK = 6033 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_M2_M2 = 6034 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_M2_M2_MASK = 6035 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF2_M1 = 6036 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF2_M1_MASK = 6037 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF2_M2 = 6038 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF2_M2_MASK = 6039 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF2_MF2 = 6040 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF2_MF2_MASK = 6041 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF4_M1 = 6042 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF4_M1_MASK = 6043 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF4_M2 = 6044 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF4_M2_MASK = 6045 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF4_MF2 = 6046 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF4_MF2_MASK = 6047 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF4_MF4 = 6048 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF4_MF4_MASK = 6049 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF8_M1 = 6050 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF8_M1_MASK = 6051 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF8_MF2 = 6052 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF8_MF2_MASK = 6053 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF8_MF4 = 6054 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF8_MF4_MASK = 6055 ,
  LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF8_MF8 = 6056 , LIEF::assembly::riscv::PseudoVLUXSEG4EI8_V_MF8_MF8_MASK = 6057 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_M1_M1 = 6058 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_M1_M1_MASK = 6059 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_M1_MF2 = 6060 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_M1_MF2_MASK = 6061 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_M2_M1 = 6062 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_M2_M1_MASK = 6063 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF2_M1 = 6064 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF2_M1_MASK = 6065 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF2_MF2 = 6066 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF2_MF2_MASK = 6067 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF2_MF4 = 6068 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF2_MF4_MASK = 6069 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF4_M1 = 6070 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF4_M1_MASK = 6071 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF4_MF2 = 6072 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF4_MF2_MASK = 6073 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF4_MF4 = 6074 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF4_MF4_MASK = 6075 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF4_MF8 = 6076 , LIEF::assembly::riscv::PseudoVLUXSEG5EI16_V_MF4_MF8_MASK = 6077 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M1_M1 = 6078 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M1_M1_MASK = 6079 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M1_MF2 = 6080 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M1_MF2_MASK = 6081 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M1_MF4 = 6082 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M1_MF4_MASK = 6083 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M2_M1 = 6084 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M2_M1_MASK = 6085 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M2_MF2 = 6086 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M2_MF2_MASK = 6087 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M4_M1 = 6088 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_M4_M1_MASK = 6089 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_MF2_M1 = 6090 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_MF2_M1_MASK = 6091 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_MF2_MF2 = 6092 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_MF2_MF2_MASK = 6093 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_MF2_MF4 = 6094 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_MF2_MF4_MASK = 6095 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_MF2_MF8 = 6096 , LIEF::assembly::riscv::PseudoVLUXSEG5EI32_V_MF2_MF8_MASK = 6097 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M1_M1 = 6098 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M1_M1_MASK = 6099 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M1_MF2 = 6100 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M1_MF2_MASK = 6101 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M1_MF4 = 6102 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M1_MF4_MASK = 6103 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M1_MF8 = 6104 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M1_MF8_MASK = 6105 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M2_M1 = 6106 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M2_M1_MASK = 6107 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M2_MF2 = 6108 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M2_MF2_MASK = 6109 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M2_MF4 = 6110 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M2_MF4_MASK = 6111 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M4_M1 = 6112 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M4_M1_MASK = 6113 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M4_MF2 = 6114 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M4_MF2_MASK = 6115 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M8_M1 = 6116 , LIEF::assembly::riscv::PseudoVLUXSEG5EI64_V_M8_M1_MASK = 6117 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_M1_M1 = 6118 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_M1_M1_MASK = 6119 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF2_M1 = 6120 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF2_M1_MASK = 6121 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF2_MF2 = 6122 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF2_MF2_MASK = 6123 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF4_M1 = 6124 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF4_M1_MASK = 6125 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF4_MF2 = 6126 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF4_MF2_MASK = 6127 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF4_MF4 = 6128 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF4_MF4_MASK = 6129 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF8_M1 = 6130 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF8_M1_MASK = 6131 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF8_MF2 = 6132 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF8_MF2_MASK = 6133 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF8_MF4 = 6134 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF8_MF4_MASK = 6135 ,
  LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF8_MF8 = 6136 , LIEF::assembly::riscv::PseudoVLUXSEG5EI8_V_MF8_MF8_MASK = 6137 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_M1_M1 = 6138 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_M1_M1_MASK = 6139 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_M1_MF2 = 6140 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_M1_MF2_MASK = 6141 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_M2_M1 = 6142 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_M2_M1_MASK = 6143 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF2_M1 = 6144 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF2_M1_MASK = 6145 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF2_MF2 = 6146 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF2_MF2_MASK = 6147 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF2_MF4 = 6148 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF2_MF4_MASK = 6149 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF4_M1 = 6150 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF4_M1_MASK = 6151 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF4_MF2 = 6152 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF4_MF2_MASK = 6153 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF4_MF4 = 6154 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF4_MF4_MASK = 6155 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF4_MF8 = 6156 , LIEF::assembly::riscv::PseudoVLUXSEG6EI16_V_MF4_MF8_MASK = 6157 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M1_M1 = 6158 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M1_M1_MASK = 6159 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M1_MF2 = 6160 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M1_MF2_MASK = 6161 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M1_MF4 = 6162 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M1_MF4_MASK = 6163 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M2_M1 = 6164 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M2_M1_MASK = 6165 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M2_MF2 = 6166 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M2_MF2_MASK = 6167 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M4_M1 = 6168 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_M4_M1_MASK = 6169 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_MF2_M1 = 6170 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_MF2_M1_MASK = 6171 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_MF2_MF2 = 6172 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_MF2_MF2_MASK = 6173 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_MF2_MF4 = 6174 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_MF2_MF4_MASK = 6175 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_MF2_MF8 = 6176 , LIEF::assembly::riscv::PseudoVLUXSEG6EI32_V_MF2_MF8_MASK = 6177 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M1_M1 = 6178 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M1_M1_MASK = 6179 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M1_MF2 = 6180 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M1_MF2_MASK = 6181 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M1_MF4 = 6182 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M1_MF4_MASK = 6183 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M1_MF8 = 6184 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M1_MF8_MASK = 6185 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M2_M1 = 6186 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M2_M1_MASK = 6187 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M2_MF2 = 6188 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M2_MF2_MASK = 6189 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M2_MF4 = 6190 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M2_MF4_MASK = 6191 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M4_M1 = 6192 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M4_M1_MASK = 6193 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M4_MF2 = 6194 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M4_MF2_MASK = 6195 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M8_M1 = 6196 , LIEF::assembly::riscv::PseudoVLUXSEG6EI64_V_M8_M1_MASK = 6197 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_M1_M1 = 6198 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_M1_M1_MASK = 6199 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF2_M1 = 6200 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF2_M1_MASK = 6201 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF2_MF2 = 6202 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF2_MF2_MASK = 6203 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF4_M1 = 6204 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF4_M1_MASK = 6205 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF4_MF2 = 6206 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF4_MF2_MASK = 6207 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF4_MF4 = 6208 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF4_MF4_MASK = 6209 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF8_M1 = 6210 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF8_M1_MASK = 6211 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF8_MF2 = 6212 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF8_MF2_MASK = 6213 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF8_MF4 = 6214 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF8_MF4_MASK = 6215 ,
  LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF8_MF8 = 6216 , LIEF::assembly::riscv::PseudoVLUXSEG6EI8_V_MF8_MF8_MASK = 6217 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_M1_M1 = 6218 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_M1_M1_MASK = 6219 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_M1_MF2 = 6220 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_M1_MF2_MASK = 6221 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_M2_M1 = 6222 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_M2_M1_MASK = 6223 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF2_M1 = 6224 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF2_M1_MASK = 6225 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF2_MF2 = 6226 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF2_MF2_MASK = 6227 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF2_MF4 = 6228 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF2_MF4_MASK = 6229 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF4_M1 = 6230 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF4_M1_MASK = 6231 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF4_MF2 = 6232 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF4_MF2_MASK = 6233 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF4_MF4 = 6234 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF4_MF4_MASK = 6235 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF4_MF8 = 6236 , LIEF::assembly::riscv::PseudoVLUXSEG7EI16_V_MF4_MF8_MASK = 6237 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M1_M1 = 6238 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M1_M1_MASK = 6239 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M1_MF2 = 6240 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M1_MF2_MASK = 6241 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M1_MF4 = 6242 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M1_MF4_MASK = 6243 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M2_M1 = 6244 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M2_M1_MASK = 6245 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M2_MF2 = 6246 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M2_MF2_MASK = 6247 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M4_M1 = 6248 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_M4_M1_MASK = 6249 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_MF2_M1 = 6250 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_MF2_M1_MASK = 6251 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_MF2_MF2 = 6252 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_MF2_MF2_MASK = 6253 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_MF2_MF4 = 6254 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_MF2_MF4_MASK = 6255 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_MF2_MF8 = 6256 , LIEF::assembly::riscv::PseudoVLUXSEG7EI32_V_MF2_MF8_MASK = 6257 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M1_M1 = 6258 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M1_M1_MASK = 6259 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M1_MF2 = 6260 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M1_MF2_MASK = 6261 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M1_MF4 = 6262 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M1_MF4_MASK = 6263 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M1_MF8 = 6264 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M1_MF8_MASK = 6265 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M2_M1 = 6266 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M2_M1_MASK = 6267 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M2_MF2 = 6268 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M2_MF2_MASK = 6269 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M2_MF4 = 6270 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M2_MF4_MASK = 6271 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M4_M1 = 6272 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M4_M1_MASK = 6273 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M4_MF2 = 6274 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M4_MF2_MASK = 6275 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M8_M1 = 6276 , LIEF::assembly::riscv::PseudoVLUXSEG7EI64_V_M8_M1_MASK = 6277 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_M1_M1 = 6278 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_M1_M1_MASK = 6279 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF2_M1 = 6280 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF2_M1_MASK = 6281 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF2_MF2 = 6282 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF2_MF2_MASK = 6283 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF4_M1 = 6284 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF4_M1_MASK = 6285 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF4_MF2 = 6286 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF4_MF2_MASK = 6287 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF4_MF4 = 6288 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF4_MF4_MASK = 6289 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF8_M1 = 6290 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF8_M1_MASK = 6291 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF8_MF2 = 6292 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF8_MF2_MASK = 6293 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF8_MF4 = 6294 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF8_MF4_MASK = 6295 ,
  LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF8_MF8 = 6296 , LIEF::assembly::riscv::PseudoVLUXSEG7EI8_V_MF8_MF8_MASK = 6297 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_M1_M1 = 6298 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_M1_M1_MASK = 6299 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_M1_MF2 = 6300 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_M1_MF2_MASK = 6301 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_M2_M1 = 6302 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_M2_M1_MASK = 6303 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF2_M1 = 6304 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF2_M1_MASK = 6305 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF2_MF2 = 6306 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF2_MF2_MASK = 6307 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF2_MF4 = 6308 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF2_MF4_MASK = 6309 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF4_M1 = 6310 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF4_M1_MASK = 6311 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF4_MF2 = 6312 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF4_MF2_MASK = 6313 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF4_MF4 = 6314 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF4_MF4_MASK = 6315 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF4_MF8 = 6316 , LIEF::assembly::riscv::PseudoVLUXSEG8EI16_V_MF4_MF8_MASK = 6317 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M1_M1 = 6318 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M1_M1_MASK = 6319 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M1_MF2 = 6320 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M1_MF2_MASK = 6321 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M1_MF4 = 6322 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M1_MF4_MASK = 6323 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M2_M1 = 6324 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M2_M1_MASK = 6325 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M2_MF2 = 6326 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M2_MF2_MASK = 6327 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M4_M1 = 6328 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_M4_M1_MASK = 6329 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_MF2_M1 = 6330 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_MF2_M1_MASK = 6331 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_MF2_MF2 = 6332 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_MF2_MF2_MASK = 6333 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_MF2_MF4 = 6334 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_MF2_MF4_MASK = 6335 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_MF2_MF8 = 6336 , LIEF::assembly::riscv::PseudoVLUXSEG8EI32_V_MF2_MF8_MASK = 6337 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M1_M1 = 6338 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M1_M1_MASK = 6339 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M1_MF2 = 6340 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M1_MF2_MASK = 6341 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M1_MF4 = 6342 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M1_MF4_MASK = 6343 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M1_MF8 = 6344 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M1_MF8_MASK = 6345 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M2_M1 = 6346 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M2_M1_MASK = 6347 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M2_MF2 = 6348 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M2_MF2_MASK = 6349 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M2_MF4 = 6350 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M2_MF4_MASK = 6351 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M4_M1 = 6352 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M4_M1_MASK = 6353 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M4_MF2 = 6354 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M4_MF2_MASK = 6355 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M8_M1 = 6356 , LIEF::assembly::riscv::PseudoVLUXSEG8EI64_V_M8_M1_MASK = 6357 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_M1_M1 = 6358 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_M1_M1_MASK = 6359 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF2_M1 = 6360 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF2_M1_MASK = 6361 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF2_MF2 = 6362 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF2_MF2_MASK = 6363 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF4_M1 = 6364 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF4_M1_MASK = 6365 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF4_MF2 = 6366 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF4_MF2_MASK = 6367 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF4_MF4 = 6368 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF4_MF4_MASK = 6369 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF8_M1 = 6370 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF8_M1_MASK = 6371 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF8_MF2 = 6372 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF8_MF2_MASK = 6373 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF8_MF4 = 6374 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF8_MF4_MASK = 6375 ,
  LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF8_MF8 = 6376 , LIEF::assembly::riscv::PseudoVLUXSEG8EI8_V_MF8_MF8_MASK = 6377 , LIEF::assembly::riscv::PseudoVMACC_VV_M1 = 6378 , LIEF::assembly::riscv::PseudoVMACC_VV_M1_MASK = 6379 ,
  LIEF::assembly::riscv::PseudoVMACC_VV_M2 = 6380 , LIEF::assembly::riscv::PseudoVMACC_VV_M2_MASK = 6381 , LIEF::assembly::riscv::PseudoVMACC_VV_M4 = 6382 , LIEF::assembly::riscv::PseudoVMACC_VV_M4_MASK = 6383 ,
  LIEF::assembly::riscv::PseudoVMACC_VV_M8 = 6384 , LIEF::assembly::riscv::PseudoVMACC_VV_M8_MASK = 6385 , LIEF::assembly::riscv::PseudoVMACC_VV_MF2 = 6386 , LIEF::assembly::riscv::PseudoVMACC_VV_MF2_MASK = 6387 ,
  LIEF::assembly::riscv::PseudoVMACC_VV_MF4 = 6388 , LIEF::assembly::riscv::PseudoVMACC_VV_MF4_MASK = 6389 , LIEF::assembly::riscv::PseudoVMACC_VV_MF8 = 6390 , LIEF::assembly::riscv::PseudoVMACC_VV_MF8_MASK = 6391 ,
  LIEF::assembly::riscv::PseudoVMACC_VX_M1 = 6392 , LIEF::assembly::riscv::PseudoVMACC_VX_M1_MASK = 6393 , LIEF::assembly::riscv::PseudoVMACC_VX_M2 = 6394 , LIEF::assembly::riscv::PseudoVMACC_VX_M2_MASK = 6395 ,
  LIEF::assembly::riscv::PseudoVMACC_VX_M4 = 6396 , LIEF::assembly::riscv::PseudoVMACC_VX_M4_MASK = 6397 , LIEF::assembly::riscv::PseudoVMACC_VX_M8 = 6398 , LIEF::assembly::riscv::PseudoVMACC_VX_M8_MASK = 6399 ,
  LIEF::assembly::riscv::PseudoVMACC_VX_MF2 = 6400 , LIEF::assembly::riscv::PseudoVMACC_VX_MF2_MASK = 6401 , LIEF::assembly::riscv::PseudoVMACC_VX_MF4 = 6402 , LIEF::assembly::riscv::PseudoVMACC_VX_MF4_MASK = 6403 ,
  LIEF::assembly::riscv::PseudoVMACC_VX_MF8 = 6404 , LIEF::assembly::riscv::PseudoVMACC_VX_MF8_MASK = 6405 , LIEF::assembly::riscv::PseudoVMADC_VIM_M1 = 6406 , LIEF::assembly::riscv::PseudoVMADC_VIM_M2 = 6407 ,
  LIEF::assembly::riscv::PseudoVMADC_VIM_M4 = 6408 , LIEF::assembly::riscv::PseudoVMADC_VIM_M8 = 6409 , LIEF::assembly::riscv::PseudoVMADC_VIM_MF2 = 6410 , LIEF::assembly::riscv::PseudoVMADC_VIM_MF4 = 6411 ,
  LIEF::assembly::riscv::PseudoVMADC_VIM_MF8 = 6412 , LIEF::assembly::riscv::PseudoVMADC_VI_M1 = 6413 , LIEF::assembly::riscv::PseudoVMADC_VI_M2 = 6414 , LIEF::assembly::riscv::PseudoVMADC_VI_M4 = 6415 ,
  LIEF::assembly::riscv::PseudoVMADC_VI_M8 = 6416 , LIEF::assembly::riscv::PseudoVMADC_VI_MF2 = 6417 , LIEF::assembly::riscv::PseudoVMADC_VI_MF4 = 6418 , LIEF::assembly::riscv::PseudoVMADC_VI_MF8 = 6419 ,
  LIEF::assembly::riscv::PseudoVMADC_VVM_M1 = 6420 , LIEF::assembly::riscv::PseudoVMADC_VVM_M2 = 6421 , LIEF::assembly::riscv::PseudoVMADC_VVM_M4 = 6422 , LIEF::assembly::riscv::PseudoVMADC_VVM_M8 = 6423 ,
  LIEF::assembly::riscv::PseudoVMADC_VVM_MF2 = 6424 , LIEF::assembly::riscv::PseudoVMADC_VVM_MF4 = 6425 , LIEF::assembly::riscv::PseudoVMADC_VVM_MF8 = 6426 , LIEF::assembly::riscv::PseudoVMADC_VV_M1 = 6427 ,
  LIEF::assembly::riscv::PseudoVMADC_VV_M2 = 6428 , LIEF::assembly::riscv::PseudoVMADC_VV_M4 = 6429 , LIEF::assembly::riscv::PseudoVMADC_VV_M8 = 6430 , LIEF::assembly::riscv::PseudoVMADC_VV_MF2 = 6431 ,
  LIEF::assembly::riscv::PseudoVMADC_VV_MF4 = 6432 , LIEF::assembly::riscv::PseudoVMADC_VV_MF8 = 6433 , LIEF::assembly::riscv::PseudoVMADC_VXM_M1 = 6434 , LIEF::assembly::riscv::PseudoVMADC_VXM_M2 = 6435 ,
  LIEF::assembly::riscv::PseudoVMADC_VXM_M4 = 6436 , LIEF::assembly::riscv::PseudoVMADC_VXM_M8 = 6437 , LIEF::assembly::riscv::PseudoVMADC_VXM_MF2 = 6438 , LIEF::assembly::riscv::PseudoVMADC_VXM_MF4 = 6439 ,
  LIEF::assembly::riscv::PseudoVMADC_VXM_MF8 = 6440 , LIEF::assembly::riscv::PseudoVMADC_VX_M1 = 6441 , LIEF::assembly::riscv::PseudoVMADC_VX_M2 = 6442 , LIEF::assembly::riscv::PseudoVMADC_VX_M4 = 6443 ,
  LIEF::assembly::riscv::PseudoVMADC_VX_M8 = 6444 , LIEF::assembly::riscv::PseudoVMADC_VX_MF2 = 6445 , LIEF::assembly::riscv::PseudoVMADC_VX_MF4 = 6446 , LIEF::assembly::riscv::PseudoVMADC_VX_MF8 = 6447 ,
  LIEF::assembly::riscv::PseudoVMADD_VV_M1 = 6448 , LIEF::assembly::riscv::PseudoVMADD_VV_M1_MASK = 6449 , LIEF::assembly::riscv::PseudoVMADD_VV_M2 = 6450 , LIEF::assembly::riscv::PseudoVMADD_VV_M2_MASK = 6451 ,
  LIEF::assembly::riscv::PseudoVMADD_VV_M4 = 6452 , LIEF::assembly::riscv::PseudoVMADD_VV_M4_MASK = 6453 , LIEF::assembly::riscv::PseudoVMADD_VV_M8 = 6454 , LIEF::assembly::riscv::PseudoVMADD_VV_M8_MASK = 6455 ,
  LIEF::assembly::riscv::PseudoVMADD_VV_MF2 = 6456 , LIEF::assembly::riscv::PseudoVMADD_VV_MF2_MASK = 6457 , LIEF::assembly::riscv::PseudoVMADD_VV_MF4 = 6458 , LIEF::assembly::riscv::PseudoVMADD_VV_MF4_MASK = 6459 ,
  LIEF::assembly::riscv::PseudoVMADD_VV_MF8 = 6460 , LIEF::assembly::riscv::PseudoVMADD_VV_MF8_MASK = 6461 , LIEF::assembly::riscv::PseudoVMADD_VX_M1 = 6462 , LIEF::assembly::riscv::PseudoVMADD_VX_M1_MASK = 6463 ,
  LIEF::assembly::riscv::PseudoVMADD_VX_M2 = 6464 , LIEF::assembly::riscv::PseudoVMADD_VX_M2_MASK = 6465 , LIEF::assembly::riscv::PseudoVMADD_VX_M4 = 6466 , LIEF::assembly::riscv::PseudoVMADD_VX_M4_MASK = 6467 ,
  LIEF::assembly::riscv::PseudoVMADD_VX_M8 = 6468 , LIEF::assembly::riscv::PseudoVMADD_VX_M8_MASK = 6469 , LIEF::assembly::riscv::PseudoVMADD_VX_MF2 = 6470 , LIEF::assembly::riscv::PseudoVMADD_VX_MF2_MASK = 6471 ,
  LIEF::assembly::riscv::PseudoVMADD_VX_MF4 = 6472 , LIEF::assembly::riscv::PseudoVMADD_VX_MF4_MASK = 6473 , LIEF::assembly::riscv::PseudoVMADD_VX_MF8 = 6474 , LIEF::assembly::riscv::PseudoVMADD_VX_MF8_MASK = 6475 ,
  LIEF::assembly::riscv::PseudoVMANDN_MM_M1 = 6476 , LIEF::assembly::riscv::PseudoVMANDN_MM_M2 = 6477 , LIEF::assembly::riscv::PseudoVMANDN_MM_M4 = 6478 , LIEF::assembly::riscv::PseudoVMANDN_MM_M8 = 6479 ,
  LIEF::assembly::riscv::PseudoVMANDN_MM_MF2 = 6480 , LIEF::assembly::riscv::PseudoVMANDN_MM_MF4 = 6481 , LIEF::assembly::riscv::PseudoVMANDN_MM_MF8 = 6482 , LIEF::assembly::riscv::PseudoVMAND_MM_M1 = 6483 ,
  LIEF::assembly::riscv::PseudoVMAND_MM_M2 = 6484 , LIEF::assembly::riscv::PseudoVMAND_MM_M4 = 6485 , LIEF::assembly::riscv::PseudoVMAND_MM_M8 = 6486 , LIEF::assembly::riscv::PseudoVMAND_MM_MF2 = 6487 ,
  LIEF::assembly::riscv::PseudoVMAND_MM_MF4 = 6488 , LIEF::assembly::riscv::PseudoVMAND_MM_MF8 = 6489 , LIEF::assembly::riscv::PseudoVMAXU_VV_M1 = 6490 , LIEF::assembly::riscv::PseudoVMAXU_VV_M1_MASK = 6491 ,
  LIEF::assembly::riscv::PseudoVMAXU_VV_M2 = 6492 , LIEF::assembly::riscv::PseudoVMAXU_VV_M2_MASK = 6493 , LIEF::assembly::riscv::PseudoVMAXU_VV_M4 = 6494 , LIEF::assembly::riscv::PseudoVMAXU_VV_M4_MASK = 6495 ,
  LIEF::assembly::riscv::PseudoVMAXU_VV_M8 = 6496 , LIEF::assembly::riscv::PseudoVMAXU_VV_M8_MASK = 6497 , LIEF::assembly::riscv::PseudoVMAXU_VV_MF2 = 6498 , LIEF::assembly::riscv::PseudoVMAXU_VV_MF2_MASK = 6499 ,
  LIEF::assembly::riscv::PseudoVMAXU_VV_MF4 = 6500 , LIEF::assembly::riscv::PseudoVMAXU_VV_MF4_MASK = 6501 , LIEF::assembly::riscv::PseudoVMAXU_VV_MF8 = 6502 , LIEF::assembly::riscv::PseudoVMAXU_VV_MF8_MASK = 6503 ,
  LIEF::assembly::riscv::PseudoVMAXU_VX_M1 = 6504 , LIEF::assembly::riscv::PseudoVMAXU_VX_M1_MASK = 6505 , LIEF::assembly::riscv::PseudoVMAXU_VX_M2 = 6506 , LIEF::assembly::riscv::PseudoVMAXU_VX_M2_MASK = 6507 ,
  LIEF::assembly::riscv::PseudoVMAXU_VX_M4 = 6508 , LIEF::assembly::riscv::PseudoVMAXU_VX_M4_MASK = 6509 , LIEF::assembly::riscv::PseudoVMAXU_VX_M8 = 6510 , LIEF::assembly::riscv::PseudoVMAXU_VX_M8_MASK = 6511 ,
  LIEF::assembly::riscv::PseudoVMAXU_VX_MF2 = 6512 , LIEF::assembly::riscv::PseudoVMAXU_VX_MF2_MASK = 6513 , LIEF::assembly::riscv::PseudoVMAXU_VX_MF4 = 6514 , LIEF::assembly::riscv::PseudoVMAXU_VX_MF4_MASK = 6515 ,
  LIEF::assembly::riscv::PseudoVMAXU_VX_MF8 = 6516 , LIEF::assembly::riscv::PseudoVMAXU_VX_MF8_MASK = 6517 , LIEF::assembly::riscv::PseudoVMAX_VV_M1 = 6518 , LIEF::assembly::riscv::PseudoVMAX_VV_M1_MASK = 6519 ,
  LIEF::assembly::riscv::PseudoVMAX_VV_M2 = 6520 , LIEF::assembly::riscv::PseudoVMAX_VV_M2_MASK = 6521 , LIEF::assembly::riscv::PseudoVMAX_VV_M4 = 6522 , LIEF::assembly::riscv::PseudoVMAX_VV_M4_MASK = 6523 ,
  LIEF::assembly::riscv::PseudoVMAX_VV_M8 = 6524 , LIEF::assembly::riscv::PseudoVMAX_VV_M8_MASK = 6525 , LIEF::assembly::riscv::PseudoVMAX_VV_MF2 = 6526 , LIEF::assembly::riscv::PseudoVMAX_VV_MF2_MASK = 6527 ,
  LIEF::assembly::riscv::PseudoVMAX_VV_MF4 = 6528 , LIEF::assembly::riscv::PseudoVMAX_VV_MF4_MASK = 6529 , LIEF::assembly::riscv::PseudoVMAX_VV_MF8 = 6530 , LIEF::assembly::riscv::PseudoVMAX_VV_MF8_MASK = 6531 ,
  LIEF::assembly::riscv::PseudoVMAX_VX_M1 = 6532 , LIEF::assembly::riscv::PseudoVMAX_VX_M1_MASK = 6533 , LIEF::assembly::riscv::PseudoVMAX_VX_M2 = 6534 , LIEF::assembly::riscv::PseudoVMAX_VX_M2_MASK = 6535 ,
  LIEF::assembly::riscv::PseudoVMAX_VX_M4 = 6536 , LIEF::assembly::riscv::PseudoVMAX_VX_M4_MASK = 6537 , LIEF::assembly::riscv::PseudoVMAX_VX_M8 = 6538 , LIEF::assembly::riscv::PseudoVMAX_VX_M8_MASK = 6539 ,
  LIEF::assembly::riscv::PseudoVMAX_VX_MF2 = 6540 , LIEF::assembly::riscv::PseudoVMAX_VX_MF2_MASK = 6541 , LIEF::assembly::riscv::PseudoVMAX_VX_MF4 = 6542 , LIEF::assembly::riscv::PseudoVMAX_VX_MF4_MASK = 6543 ,
  LIEF::assembly::riscv::PseudoVMAX_VX_MF8 = 6544 , LIEF::assembly::riscv::PseudoVMAX_VX_MF8_MASK = 6545 , LIEF::assembly::riscv::PseudoVMCLR_M_B1 = 6546 , LIEF::assembly::riscv::PseudoVMCLR_M_B16 = 6547 ,
  LIEF::assembly::riscv::PseudoVMCLR_M_B2 = 6548 , LIEF::assembly::riscv::PseudoVMCLR_M_B32 = 6549 , LIEF::assembly::riscv::PseudoVMCLR_M_B4 = 6550 , LIEF::assembly::riscv::PseudoVMCLR_M_B64 = 6551 ,
  LIEF::assembly::riscv::PseudoVMCLR_M_B8 = 6552 , LIEF::assembly::riscv::PseudoVMERGE_VIM_M1 = 6553 , LIEF::assembly::riscv::PseudoVMERGE_VIM_M2 = 6554 , LIEF::assembly::riscv::PseudoVMERGE_VIM_M4 = 6555 ,
  LIEF::assembly::riscv::PseudoVMERGE_VIM_M8 = 6556 , LIEF::assembly::riscv::PseudoVMERGE_VIM_MF2 = 6557 , LIEF::assembly::riscv::PseudoVMERGE_VIM_MF4 = 6558 , LIEF::assembly::riscv::PseudoVMERGE_VIM_MF8 = 6559 ,
  LIEF::assembly::riscv::PseudoVMERGE_VVM_M1 = 6560 , LIEF::assembly::riscv::PseudoVMERGE_VVM_M2 = 6561 , LIEF::assembly::riscv::PseudoVMERGE_VVM_M4 = 6562 , LIEF::assembly::riscv::PseudoVMERGE_VVM_M8 = 6563 ,
  LIEF::assembly::riscv::PseudoVMERGE_VVM_MF2 = 6564 , LIEF::assembly::riscv::PseudoVMERGE_VVM_MF4 = 6565 , LIEF::assembly::riscv::PseudoVMERGE_VVM_MF8 = 6566 , LIEF::assembly::riscv::PseudoVMERGE_VXM_M1 = 6567 ,
  LIEF::assembly::riscv::PseudoVMERGE_VXM_M2 = 6568 , LIEF::assembly::riscv::PseudoVMERGE_VXM_M4 = 6569 , LIEF::assembly::riscv::PseudoVMERGE_VXM_M8 = 6570 , LIEF::assembly::riscv::PseudoVMERGE_VXM_MF2 = 6571 ,
  LIEF::assembly::riscv::PseudoVMERGE_VXM_MF4 = 6572 , LIEF::assembly::riscv::PseudoVMERGE_VXM_MF8 = 6573 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_M1 = 6574 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_M1_MASK = 6575 ,
  LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_M2 = 6576 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_M2_MASK = 6577 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_M4 = 6578 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_M4_MASK = 6579 ,
  LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_M8 = 6580 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_M8_MASK = 6581 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_MF2 = 6582 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_MF2_MASK = 6583 ,
  LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_MF4 = 6584 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR16_MF4_MASK = 6585 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR32_M1 = 6586 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR32_M1_MASK = 6587 ,
  LIEF::assembly::riscv::PseudoVMFEQ_VFPR32_M2 = 6588 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR32_M2_MASK = 6589 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR32_M4 = 6590 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR32_M4_MASK = 6591 ,
  LIEF::assembly::riscv::PseudoVMFEQ_VFPR32_M8 = 6592 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR32_M8_MASK = 6593 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR32_MF2 = 6594 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR32_MF2_MASK = 6595 ,
  LIEF::assembly::riscv::PseudoVMFEQ_VFPR64_M1 = 6596 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR64_M1_MASK = 6597 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR64_M2 = 6598 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR64_M2_MASK = 6599 ,
  LIEF::assembly::riscv::PseudoVMFEQ_VFPR64_M4 = 6600 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR64_M4_MASK = 6601 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR64_M8 = 6602 , LIEF::assembly::riscv::PseudoVMFEQ_VFPR64_M8_MASK = 6603 ,
  LIEF::assembly::riscv::PseudoVMFEQ_VV_M1 = 6604 , LIEF::assembly::riscv::PseudoVMFEQ_VV_M1_MASK = 6605 , LIEF::assembly::riscv::PseudoVMFEQ_VV_M2 = 6606 , LIEF::assembly::riscv::PseudoVMFEQ_VV_M2_MASK = 6607 ,
  LIEF::assembly::riscv::PseudoVMFEQ_VV_M4 = 6608 , LIEF::assembly::riscv::PseudoVMFEQ_VV_M4_MASK = 6609 , LIEF::assembly::riscv::PseudoVMFEQ_VV_M8 = 6610 , LIEF::assembly::riscv::PseudoVMFEQ_VV_M8_MASK = 6611 ,
  LIEF::assembly::riscv::PseudoVMFEQ_VV_MF2 = 6612 , LIEF::assembly::riscv::PseudoVMFEQ_VV_MF2_MASK = 6613 , LIEF::assembly::riscv::PseudoVMFEQ_VV_MF4 = 6614 , LIEF::assembly::riscv::PseudoVMFEQ_VV_MF4_MASK = 6615 ,
  LIEF::assembly::riscv::PseudoVMFGE_VFPR16_M1 = 6616 , LIEF::assembly::riscv::PseudoVMFGE_VFPR16_M1_MASK = 6617 , LIEF::assembly::riscv::PseudoVMFGE_VFPR16_M2 = 6618 , LIEF::assembly::riscv::PseudoVMFGE_VFPR16_M2_MASK = 6619 ,
  LIEF::assembly::riscv::PseudoVMFGE_VFPR16_M4 = 6620 , LIEF::assembly::riscv::PseudoVMFGE_VFPR16_M4_MASK = 6621 , LIEF::assembly::riscv::PseudoVMFGE_VFPR16_M8 = 6622 , LIEF::assembly::riscv::PseudoVMFGE_VFPR16_M8_MASK = 6623 ,
  LIEF::assembly::riscv::PseudoVMFGE_VFPR16_MF2 = 6624 , LIEF::assembly::riscv::PseudoVMFGE_VFPR16_MF2_MASK = 6625 , LIEF::assembly::riscv::PseudoVMFGE_VFPR16_MF4 = 6626 , LIEF::assembly::riscv::PseudoVMFGE_VFPR16_MF4_MASK = 6627 ,
  LIEF::assembly::riscv::PseudoVMFGE_VFPR32_M1 = 6628 , LIEF::assembly::riscv::PseudoVMFGE_VFPR32_M1_MASK = 6629 , LIEF::assembly::riscv::PseudoVMFGE_VFPR32_M2 = 6630 , LIEF::assembly::riscv::PseudoVMFGE_VFPR32_M2_MASK = 6631 ,
  LIEF::assembly::riscv::PseudoVMFGE_VFPR32_M4 = 6632 , LIEF::assembly::riscv::PseudoVMFGE_VFPR32_M4_MASK = 6633 , LIEF::assembly::riscv::PseudoVMFGE_VFPR32_M8 = 6634 , LIEF::assembly::riscv::PseudoVMFGE_VFPR32_M8_MASK = 6635 ,
  LIEF::assembly::riscv::PseudoVMFGE_VFPR32_MF2 = 6636 , LIEF::assembly::riscv::PseudoVMFGE_VFPR32_MF2_MASK = 6637 , LIEF::assembly::riscv::PseudoVMFGE_VFPR64_M1 = 6638 , LIEF::assembly::riscv::PseudoVMFGE_VFPR64_M1_MASK = 6639 ,
  LIEF::assembly::riscv::PseudoVMFGE_VFPR64_M2 = 6640 , LIEF::assembly::riscv::PseudoVMFGE_VFPR64_M2_MASK = 6641 , LIEF::assembly::riscv::PseudoVMFGE_VFPR64_M4 = 6642 , LIEF::assembly::riscv::PseudoVMFGE_VFPR64_M4_MASK = 6643 ,
  LIEF::assembly::riscv::PseudoVMFGE_VFPR64_M8 = 6644 , LIEF::assembly::riscv::PseudoVMFGE_VFPR64_M8_MASK = 6645 , LIEF::assembly::riscv::PseudoVMFGT_VFPR16_M1 = 6646 , LIEF::assembly::riscv::PseudoVMFGT_VFPR16_M1_MASK = 6647 ,
  LIEF::assembly::riscv::PseudoVMFGT_VFPR16_M2 = 6648 , LIEF::assembly::riscv::PseudoVMFGT_VFPR16_M2_MASK = 6649 , LIEF::assembly::riscv::PseudoVMFGT_VFPR16_M4 = 6650 , LIEF::assembly::riscv::PseudoVMFGT_VFPR16_M4_MASK = 6651 ,
  LIEF::assembly::riscv::PseudoVMFGT_VFPR16_M8 = 6652 , LIEF::assembly::riscv::PseudoVMFGT_VFPR16_M8_MASK = 6653 , LIEF::assembly::riscv::PseudoVMFGT_VFPR16_MF2 = 6654 , LIEF::assembly::riscv::PseudoVMFGT_VFPR16_MF2_MASK = 6655 ,
  LIEF::assembly::riscv::PseudoVMFGT_VFPR16_MF4 = 6656 , LIEF::assembly::riscv::PseudoVMFGT_VFPR16_MF4_MASK = 6657 , LIEF::assembly::riscv::PseudoVMFGT_VFPR32_M1 = 6658 , LIEF::assembly::riscv::PseudoVMFGT_VFPR32_M1_MASK = 6659 ,
  LIEF::assembly::riscv::PseudoVMFGT_VFPR32_M2 = 6660 , LIEF::assembly::riscv::PseudoVMFGT_VFPR32_M2_MASK = 6661 , LIEF::assembly::riscv::PseudoVMFGT_VFPR32_M4 = 6662 , LIEF::assembly::riscv::PseudoVMFGT_VFPR32_M4_MASK = 6663 ,
  LIEF::assembly::riscv::PseudoVMFGT_VFPR32_M8 = 6664 , LIEF::assembly::riscv::PseudoVMFGT_VFPR32_M8_MASK = 6665 , LIEF::assembly::riscv::PseudoVMFGT_VFPR32_MF2 = 6666 , LIEF::assembly::riscv::PseudoVMFGT_VFPR32_MF2_MASK = 6667 ,
  LIEF::assembly::riscv::PseudoVMFGT_VFPR64_M1 = 6668 , LIEF::assembly::riscv::PseudoVMFGT_VFPR64_M1_MASK = 6669 , LIEF::assembly::riscv::PseudoVMFGT_VFPR64_M2 = 6670 , LIEF::assembly::riscv::PseudoVMFGT_VFPR64_M2_MASK = 6671 ,
  LIEF::assembly::riscv::PseudoVMFGT_VFPR64_M4 = 6672 , LIEF::assembly::riscv::PseudoVMFGT_VFPR64_M4_MASK = 6673 , LIEF::assembly::riscv::PseudoVMFGT_VFPR64_M8 = 6674 , LIEF::assembly::riscv::PseudoVMFGT_VFPR64_M8_MASK = 6675 ,
  LIEF::assembly::riscv::PseudoVMFLE_VFPR16_M1 = 6676 , LIEF::assembly::riscv::PseudoVMFLE_VFPR16_M1_MASK = 6677 , LIEF::assembly::riscv::PseudoVMFLE_VFPR16_M2 = 6678 , LIEF::assembly::riscv::PseudoVMFLE_VFPR16_M2_MASK = 6679 ,
  LIEF::assembly::riscv::PseudoVMFLE_VFPR16_M4 = 6680 , LIEF::assembly::riscv::PseudoVMFLE_VFPR16_M4_MASK = 6681 , LIEF::assembly::riscv::PseudoVMFLE_VFPR16_M8 = 6682 , LIEF::assembly::riscv::PseudoVMFLE_VFPR16_M8_MASK = 6683 ,
  LIEF::assembly::riscv::PseudoVMFLE_VFPR16_MF2 = 6684 , LIEF::assembly::riscv::PseudoVMFLE_VFPR16_MF2_MASK = 6685 , LIEF::assembly::riscv::PseudoVMFLE_VFPR16_MF4 = 6686 , LIEF::assembly::riscv::PseudoVMFLE_VFPR16_MF4_MASK = 6687 ,
  LIEF::assembly::riscv::PseudoVMFLE_VFPR32_M1 = 6688 , LIEF::assembly::riscv::PseudoVMFLE_VFPR32_M1_MASK = 6689 , LIEF::assembly::riscv::PseudoVMFLE_VFPR32_M2 = 6690 , LIEF::assembly::riscv::PseudoVMFLE_VFPR32_M2_MASK = 6691 ,
  LIEF::assembly::riscv::PseudoVMFLE_VFPR32_M4 = 6692 , LIEF::assembly::riscv::PseudoVMFLE_VFPR32_M4_MASK = 6693 , LIEF::assembly::riscv::PseudoVMFLE_VFPR32_M8 = 6694 , LIEF::assembly::riscv::PseudoVMFLE_VFPR32_M8_MASK = 6695 ,
  LIEF::assembly::riscv::PseudoVMFLE_VFPR32_MF2 = 6696 , LIEF::assembly::riscv::PseudoVMFLE_VFPR32_MF2_MASK = 6697 , LIEF::assembly::riscv::PseudoVMFLE_VFPR64_M1 = 6698 , LIEF::assembly::riscv::PseudoVMFLE_VFPR64_M1_MASK = 6699 ,
  LIEF::assembly::riscv::PseudoVMFLE_VFPR64_M2 = 6700 , LIEF::assembly::riscv::PseudoVMFLE_VFPR64_M2_MASK = 6701 , LIEF::assembly::riscv::PseudoVMFLE_VFPR64_M4 = 6702 , LIEF::assembly::riscv::PseudoVMFLE_VFPR64_M4_MASK = 6703 ,
  LIEF::assembly::riscv::PseudoVMFLE_VFPR64_M8 = 6704 , LIEF::assembly::riscv::PseudoVMFLE_VFPR64_M8_MASK = 6705 , LIEF::assembly::riscv::PseudoVMFLE_VV_M1 = 6706 , LIEF::assembly::riscv::PseudoVMFLE_VV_M1_MASK = 6707 ,
  LIEF::assembly::riscv::PseudoVMFLE_VV_M2 = 6708 , LIEF::assembly::riscv::PseudoVMFLE_VV_M2_MASK = 6709 , LIEF::assembly::riscv::PseudoVMFLE_VV_M4 = 6710 , LIEF::assembly::riscv::PseudoVMFLE_VV_M4_MASK = 6711 ,
  LIEF::assembly::riscv::PseudoVMFLE_VV_M8 = 6712 , LIEF::assembly::riscv::PseudoVMFLE_VV_M8_MASK = 6713 , LIEF::assembly::riscv::PseudoVMFLE_VV_MF2 = 6714 , LIEF::assembly::riscv::PseudoVMFLE_VV_MF2_MASK = 6715 ,
  LIEF::assembly::riscv::PseudoVMFLE_VV_MF4 = 6716 , LIEF::assembly::riscv::PseudoVMFLE_VV_MF4_MASK = 6717 , LIEF::assembly::riscv::PseudoVMFLT_VFPR16_M1 = 6718 , LIEF::assembly::riscv::PseudoVMFLT_VFPR16_M1_MASK = 6719 ,
  LIEF::assembly::riscv::PseudoVMFLT_VFPR16_M2 = 6720 , LIEF::assembly::riscv::PseudoVMFLT_VFPR16_M2_MASK = 6721 , LIEF::assembly::riscv::PseudoVMFLT_VFPR16_M4 = 6722 , LIEF::assembly::riscv::PseudoVMFLT_VFPR16_M4_MASK = 6723 ,
  LIEF::assembly::riscv::PseudoVMFLT_VFPR16_M8 = 6724 , LIEF::assembly::riscv::PseudoVMFLT_VFPR16_M8_MASK = 6725 , LIEF::assembly::riscv::PseudoVMFLT_VFPR16_MF2 = 6726 , LIEF::assembly::riscv::PseudoVMFLT_VFPR16_MF2_MASK = 6727 ,
  LIEF::assembly::riscv::PseudoVMFLT_VFPR16_MF4 = 6728 , LIEF::assembly::riscv::PseudoVMFLT_VFPR16_MF4_MASK = 6729 , LIEF::assembly::riscv::PseudoVMFLT_VFPR32_M1 = 6730 , LIEF::assembly::riscv::PseudoVMFLT_VFPR32_M1_MASK = 6731 ,
  LIEF::assembly::riscv::PseudoVMFLT_VFPR32_M2 = 6732 , LIEF::assembly::riscv::PseudoVMFLT_VFPR32_M2_MASK = 6733 , LIEF::assembly::riscv::PseudoVMFLT_VFPR32_M4 = 6734 , LIEF::assembly::riscv::PseudoVMFLT_VFPR32_M4_MASK = 6735 ,
  LIEF::assembly::riscv::PseudoVMFLT_VFPR32_M8 = 6736 , LIEF::assembly::riscv::PseudoVMFLT_VFPR32_M8_MASK = 6737 , LIEF::assembly::riscv::PseudoVMFLT_VFPR32_MF2 = 6738 , LIEF::assembly::riscv::PseudoVMFLT_VFPR32_MF2_MASK = 6739 ,
  LIEF::assembly::riscv::PseudoVMFLT_VFPR64_M1 = 6740 , LIEF::assembly::riscv::PseudoVMFLT_VFPR64_M1_MASK = 6741 , LIEF::assembly::riscv::PseudoVMFLT_VFPR64_M2 = 6742 , LIEF::assembly::riscv::PseudoVMFLT_VFPR64_M2_MASK = 6743 ,
  LIEF::assembly::riscv::PseudoVMFLT_VFPR64_M4 = 6744 , LIEF::assembly::riscv::PseudoVMFLT_VFPR64_M4_MASK = 6745 , LIEF::assembly::riscv::PseudoVMFLT_VFPR64_M8 = 6746 , LIEF::assembly::riscv::PseudoVMFLT_VFPR64_M8_MASK = 6747 ,
  LIEF::assembly::riscv::PseudoVMFLT_VV_M1 = 6748 , LIEF::assembly::riscv::PseudoVMFLT_VV_M1_MASK = 6749 , LIEF::assembly::riscv::PseudoVMFLT_VV_M2 = 6750 , LIEF::assembly::riscv::PseudoVMFLT_VV_M2_MASK = 6751 ,
  LIEF::assembly::riscv::PseudoVMFLT_VV_M4 = 6752 , LIEF::assembly::riscv::PseudoVMFLT_VV_M4_MASK = 6753 , LIEF::assembly::riscv::PseudoVMFLT_VV_M8 = 6754 , LIEF::assembly::riscv::PseudoVMFLT_VV_M8_MASK = 6755 ,
  LIEF::assembly::riscv::PseudoVMFLT_VV_MF2 = 6756 , LIEF::assembly::riscv::PseudoVMFLT_VV_MF2_MASK = 6757 , LIEF::assembly::riscv::PseudoVMFLT_VV_MF4 = 6758 , LIEF::assembly::riscv::PseudoVMFLT_VV_MF4_MASK = 6759 ,
  LIEF::assembly::riscv::PseudoVMFNE_VFPR16_M1 = 6760 , LIEF::assembly::riscv::PseudoVMFNE_VFPR16_M1_MASK = 6761 , LIEF::assembly::riscv::PseudoVMFNE_VFPR16_M2 = 6762 , LIEF::assembly::riscv::PseudoVMFNE_VFPR16_M2_MASK = 6763 ,
  LIEF::assembly::riscv::PseudoVMFNE_VFPR16_M4 = 6764 , LIEF::assembly::riscv::PseudoVMFNE_VFPR16_M4_MASK = 6765 , LIEF::assembly::riscv::PseudoVMFNE_VFPR16_M8 = 6766 , LIEF::assembly::riscv::PseudoVMFNE_VFPR16_M8_MASK = 6767 ,
  LIEF::assembly::riscv::PseudoVMFNE_VFPR16_MF2 = 6768 , LIEF::assembly::riscv::PseudoVMFNE_VFPR16_MF2_MASK = 6769 , LIEF::assembly::riscv::PseudoVMFNE_VFPR16_MF4 = 6770 , LIEF::assembly::riscv::PseudoVMFNE_VFPR16_MF4_MASK = 6771 ,
  LIEF::assembly::riscv::PseudoVMFNE_VFPR32_M1 = 6772 , LIEF::assembly::riscv::PseudoVMFNE_VFPR32_M1_MASK = 6773 , LIEF::assembly::riscv::PseudoVMFNE_VFPR32_M2 = 6774 , LIEF::assembly::riscv::PseudoVMFNE_VFPR32_M2_MASK = 6775 ,
  LIEF::assembly::riscv::PseudoVMFNE_VFPR32_M4 = 6776 , LIEF::assembly::riscv::PseudoVMFNE_VFPR32_M4_MASK = 6777 , LIEF::assembly::riscv::PseudoVMFNE_VFPR32_M8 = 6778 , LIEF::assembly::riscv::PseudoVMFNE_VFPR32_M8_MASK = 6779 ,
  LIEF::assembly::riscv::PseudoVMFNE_VFPR32_MF2 = 6780 , LIEF::assembly::riscv::PseudoVMFNE_VFPR32_MF2_MASK = 6781 , LIEF::assembly::riscv::PseudoVMFNE_VFPR64_M1 = 6782 , LIEF::assembly::riscv::PseudoVMFNE_VFPR64_M1_MASK = 6783 ,
  LIEF::assembly::riscv::PseudoVMFNE_VFPR64_M2 = 6784 , LIEF::assembly::riscv::PseudoVMFNE_VFPR64_M2_MASK = 6785 , LIEF::assembly::riscv::PseudoVMFNE_VFPR64_M4 = 6786 , LIEF::assembly::riscv::PseudoVMFNE_VFPR64_M4_MASK = 6787 ,
  LIEF::assembly::riscv::PseudoVMFNE_VFPR64_M8 = 6788 , LIEF::assembly::riscv::PseudoVMFNE_VFPR64_M8_MASK = 6789 , LIEF::assembly::riscv::PseudoVMFNE_VV_M1 = 6790 , LIEF::assembly::riscv::PseudoVMFNE_VV_M1_MASK = 6791 ,
  LIEF::assembly::riscv::PseudoVMFNE_VV_M2 = 6792 , LIEF::assembly::riscv::PseudoVMFNE_VV_M2_MASK = 6793 , LIEF::assembly::riscv::PseudoVMFNE_VV_M4 = 6794 , LIEF::assembly::riscv::PseudoVMFNE_VV_M4_MASK = 6795 ,
  LIEF::assembly::riscv::PseudoVMFNE_VV_M8 = 6796 , LIEF::assembly::riscv::PseudoVMFNE_VV_M8_MASK = 6797 , LIEF::assembly::riscv::PseudoVMFNE_VV_MF2 = 6798 , LIEF::assembly::riscv::PseudoVMFNE_VV_MF2_MASK = 6799 ,
  LIEF::assembly::riscv::PseudoVMFNE_VV_MF4 = 6800 , LIEF::assembly::riscv::PseudoVMFNE_VV_MF4_MASK = 6801 , LIEF::assembly::riscv::PseudoVMINU_VV_M1 = 6802 , LIEF::assembly::riscv::PseudoVMINU_VV_M1_MASK = 6803 ,
  LIEF::assembly::riscv::PseudoVMINU_VV_M2 = 6804 , LIEF::assembly::riscv::PseudoVMINU_VV_M2_MASK = 6805 , LIEF::assembly::riscv::PseudoVMINU_VV_M4 = 6806 , LIEF::assembly::riscv::PseudoVMINU_VV_M4_MASK = 6807 ,
  LIEF::assembly::riscv::PseudoVMINU_VV_M8 = 6808 , LIEF::assembly::riscv::PseudoVMINU_VV_M8_MASK = 6809 , LIEF::assembly::riscv::PseudoVMINU_VV_MF2 = 6810 , LIEF::assembly::riscv::PseudoVMINU_VV_MF2_MASK = 6811 ,
  LIEF::assembly::riscv::PseudoVMINU_VV_MF4 = 6812 , LIEF::assembly::riscv::PseudoVMINU_VV_MF4_MASK = 6813 , LIEF::assembly::riscv::PseudoVMINU_VV_MF8 = 6814 , LIEF::assembly::riscv::PseudoVMINU_VV_MF8_MASK = 6815 ,
  LIEF::assembly::riscv::PseudoVMINU_VX_M1 = 6816 , LIEF::assembly::riscv::PseudoVMINU_VX_M1_MASK = 6817 , LIEF::assembly::riscv::PseudoVMINU_VX_M2 = 6818 , LIEF::assembly::riscv::PseudoVMINU_VX_M2_MASK = 6819 ,
  LIEF::assembly::riscv::PseudoVMINU_VX_M4 = 6820 , LIEF::assembly::riscv::PseudoVMINU_VX_M4_MASK = 6821 , LIEF::assembly::riscv::PseudoVMINU_VX_M8 = 6822 , LIEF::assembly::riscv::PseudoVMINU_VX_M8_MASK = 6823 ,
  LIEF::assembly::riscv::PseudoVMINU_VX_MF2 = 6824 , LIEF::assembly::riscv::PseudoVMINU_VX_MF2_MASK = 6825 , LIEF::assembly::riscv::PseudoVMINU_VX_MF4 = 6826 , LIEF::assembly::riscv::PseudoVMINU_VX_MF4_MASK = 6827 ,
  LIEF::assembly::riscv::PseudoVMINU_VX_MF8 = 6828 , LIEF::assembly::riscv::PseudoVMINU_VX_MF8_MASK = 6829 , LIEF::assembly::riscv::PseudoVMIN_VV_M1 = 6830 , LIEF::assembly::riscv::PseudoVMIN_VV_M1_MASK = 6831 ,
  LIEF::assembly::riscv::PseudoVMIN_VV_M2 = 6832 , LIEF::assembly::riscv::PseudoVMIN_VV_M2_MASK = 6833 , LIEF::assembly::riscv::PseudoVMIN_VV_M4 = 6834 , LIEF::assembly::riscv::PseudoVMIN_VV_M4_MASK = 6835 ,
  LIEF::assembly::riscv::PseudoVMIN_VV_M8 = 6836 , LIEF::assembly::riscv::PseudoVMIN_VV_M8_MASK = 6837 , LIEF::assembly::riscv::PseudoVMIN_VV_MF2 = 6838 , LIEF::assembly::riscv::PseudoVMIN_VV_MF2_MASK = 6839 ,
  LIEF::assembly::riscv::PseudoVMIN_VV_MF4 = 6840 , LIEF::assembly::riscv::PseudoVMIN_VV_MF4_MASK = 6841 , LIEF::assembly::riscv::PseudoVMIN_VV_MF8 = 6842 , LIEF::assembly::riscv::PseudoVMIN_VV_MF8_MASK = 6843 ,
  LIEF::assembly::riscv::PseudoVMIN_VX_M1 = 6844 , LIEF::assembly::riscv::PseudoVMIN_VX_M1_MASK = 6845 , LIEF::assembly::riscv::PseudoVMIN_VX_M2 = 6846 , LIEF::assembly::riscv::PseudoVMIN_VX_M2_MASK = 6847 ,
  LIEF::assembly::riscv::PseudoVMIN_VX_M4 = 6848 , LIEF::assembly::riscv::PseudoVMIN_VX_M4_MASK = 6849 , LIEF::assembly::riscv::PseudoVMIN_VX_M8 = 6850 , LIEF::assembly::riscv::PseudoVMIN_VX_M8_MASK = 6851 ,
  LIEF::assembly::riscv::PseudoVMIN_VX_MF2 = 6852 , LIEF::assembly::riscv::PseudoVMIN_VX_MF2_MASK = 6853 , LIEF::assembly::riscv::PseudoVMIN_VX_MF4 = 6854 , LIEF::assembly::riscv::PseudoVMIN_VX_MF4_MASK = 6855 ,
  LIEF::assembly::riscv::PseudoVMIN_VX_MF8 = 6856 , LIEF::assembly::riscv::PseudoVMIN_VX_MF8_MASK = 6857 , LIEF::assembly::riscv::PseudoVMNAND_MM_M1 = 6858 , LIEF::assembly::riscv::PseudoVMNAND_MM_M2 = 6859 ,
  LIEF::assembly::riscv::PseudoVMNAND_MM_M4 = 6860 , LIEF::assembly::riscv::PseudoVMNAND_MM_M8 = 6861 , LIEF::assembly::riscv::PseudoVMNAND_MM_MF2 = 6862 , LIEF::assembly::riscv::PseudoVMNAND_MM_MF4 = 6863 ,
  LIEF::assembly::riscv::PseudoVMNAND_MM_MF8 = 6864 , LIEF::assembly::riscv::PseudoVMNOR_MM_M1 = 6865 , LIEF::assembly::riscv::PseudoVMNOR_MM_M2 = 6866 , LIEF::assembly::riscv::PseudoVMNOR_MM_M4 = 6867 ,
  LIEF::assembly::riscv::PseudoVMNOR_MM_M8 = 6868 , LIEF::assembly::riscv::PseudoVMNOR_MM_MF2 = 6869 , LIEF::assembly::riscv::PseudoVMNOR_MM_MF4 = 6870 , LIEF::assembly::riscv::PseudoVMNOR_MM_MF8 = 6871 ,
  LIEF::assembly::riscv::PseudoVMORN_MM_M1 = 6872 , LIEF::assembly::riscv::PseudoVMORN_MM_M2 = 6873 , LIEF::assembly::riscv::PseudoVMORN_MM_M4 = 6874 , LIEF::assembly::riscv::PseudoVMORN_MM_M8 = 6875 ,
  LIEF::assembly::riscv::PseudoVMORN_MM_MF2 = 6876 , LIEF::assembly::riscv::PseudoVMORN_MM_MF4 = 6877 , LIEF::assembly::riscv::PseudoVMORN_MM_MF8 = 6878 , LIEF::assembly::riscv::PseudoVMOR_MM_M1 = 6879 ,
  LIEF::assembly::riscv::PseudoVMOR_MM_M2 = 6880 , LIEF::assembly::riscv::PseudoVMOR_MM_M4 = 6881 , LIEF::assembly::riscv::PseudoVMOR_MM_M8 = 6882 , LIEF::assembly::riscv::PseudoVMOR_MM_MF2 = 6883 ,
  LIEF::assembly::riscv::PseudoVMOR_MM_MF4 = 6884 , LIEF::assembly::riscv::PseudoVMOR_MM_MF8 = 6885 , LIEF::assembly::riscv::PseudoVMSBC_VVM_M1 = 6886 , LIEF::assembly::riscv::PseudoVMSBC_VVM_M2 = 6887 ,
  LIEF::assembly::riscv::PseudoVMSBC_VVM_M4 = 6888 , LIEF::assembly::riscv::PseudoVMSBC_VVM_M8 = 6889 , LIEF::assembly::riscv::PseudoVMSBC_VVM_MF2 = 6890 , LIEF::assembly::riscv::PseudoVMSBC_VVM_MF4 = 6891 ,
  LIEF::assembly::riscv::PseudoVMSBC_VVM_MF8 = 6892 , LIEF::assembly::riscv::PseudoVMSBC_VV_M1 = 6893 , LIEF::assembly::riscv::PseudoVMSBC_VV_M2 = 6894 , LIEF::assembly::riscv::PseudoVMSBC_VV_M4 = 6895 ,
  LIEF::assembly::riscv::PseudoVMSBC_VV_M8 = 6896 , LIEF::assembly::riscv::PseudoVMSBC_VV_MF2 = 6897 , LIEF::assembly::riscv::PseudoVMSBC_VV_MF4 = 6898 , LIEF::assembly::riscv::PseudoVMSBC_VV_MF8 = 6899 ,
  LIEF::assembly::riscv::PseudoVMSBC_VXM_M1 = 6900 , LIEF::assembly::riscv::PseudoVMSBC_VXM_M2 = 6901 , LIEF::assembly::riscv::PseudoVMSBC_VXM_M4 = 6902 , LIEF::assembly::riscv::PseudoVMSBC_VXM_M8 = 6903 ,
  LIEF::assembly::riscv::PseudoVMSBC_VXM_MF2 = 6904 , LIEF::assembly::riscv::PseudoVMSBC_VXM_MF4 = 6905 , LIEF::assembly::riscv::PseudoVMSBC_VXM_MF8 = 6906 , LIEF::assembly::riscv::PseudoVMSBC_VX_M1 = 6907 ,
  LIEF::assembly::riscv::PseudoVMSBC_VX_M2 = 6908 , LIEF::assembly::riscv::PseudoVMSBC_VX_M4 = 6909 , LIEF::assembly::riscv::PseudoVMSBC_VX_M8 = 6910 , LIEF::assembly::riscv::PseudoVMSBC_VX_MF2 = 6911 ,
  LIEF::assembly::riscv::PseudoVMSBC_VX_MF4 = 6912 , LIEF::assembly::riscv::PseudoVMSBC_VX_MF8 = 6913 , LIEF::assembly::riscv::PseudoVMSBF_M_B1 = 6914 , LIEF::assembly::riscv::PseudoVMSBF_M_B16 = 6915 ,
  LIEF::assembly::riscv::PseudoVMSBF_M_B16_MASK = 6916 , LIEF::assembly::riscv::PseudoVMSBF_M_B1_MASK = 6917 , LIEF::assembly::riscv::PseudoVMSBF_M_B2 = 6918 , LIEF::assembly::riscv::PseudoVMSBF_M_B2_MASK = 6919 ,
  LIEF::assembly::riscv::PseudoVMSBF_M_B32 = 6920 , LIEF::assembly::riscv::PseudoVMSBF_M_B32_MASK = 6921 , LIEF::assembly::riscv::PseudoVMSBF_M_B4 = 6922 , LIEF::assembly::riscv::PseudoVMSBF_M_B4_MASK = 6923 ,
  LIEF::assembly::riscv::PseudoVMSBF_M_B64 = 6924 , LIEF::assembly::riscv::PseudoVMSBF_M_B64_MASK = 6925 , LIEF::assembly::riscv::PseudoVMSBF_M_B8 = 6926 , LIEF::assembly::riscv::PseudoVMSBF_M_B8_MASK = 6927 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VI_M1 = 6928 , LIEF::assembly::riscv::PseudoVMSEQ_VI_M1_MASK = 6929 , LIEF::assembly::riscv::PseudoVMSEQ_VI_M2 = 6930 , LIEF::assembly::riscv::PseudoVMSEQ_VI_M2_MASK = 6931 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VI_M4 = 6932 , LIEF::assembly::riscv::PseudoVMSEQ_VI_M4_MASK = 6933 , LIEF::assembly::riscv::PseudoVMSEQ_VI_M8 = 6934 , LIEF::assembly::riscv::PseudoVMSEQ_VI_M8_MASK = 6935 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VI_MF2 = 6936 , LIEF::assembly::riscv::PseudoVMSEQ_VI_MF2_MASK = 6937 , LIEF::assembly::riscv::PseudoVMSEQ_VI_MF4 = 6938 , LIEF::assembly::riscv::PseudoVMSEQ_VI_MF4_MASK = 6939 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VI_MF8 = 6940 , LIEF::assembly::riscv::PseudoVMSEQ_VI_MF8_MASK = 6941 , LIEF::assembly::riscv::PseudoVMSEQ_VV_M1 = 6942 , LIEF::assembly::riscv::PseudoVMSEQ_VV_M1_MASK = 6943 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VV_M2 = 6944 , LIEF::assembly::riscv::PseudoVMSEQ_VV_M2_MASK = 6945 , LIEF::assembly::riscv::PseudoVMSEQ_VV_M4 = 6946 , LIEF::assembly::riscv::PseudoVMSEQ_VV_M4_MASK = 6947 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VV_M8 = 6948 , LIEF::assembly::riscv::PseudoVMSEQ_VV_M8_MASK = 6949 , LIEF::assembly::riscv::PseudoVMSEQ_VV_MF2 = 6950 , LIEF::assembly::riscv::PseudoVMSEQ_VV_MF2_MASK = 6951 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VV_MF4 = 6952 , LIEF::assembly::riscv::PseudoVMSEQ_VV_MF4_MASK = 6953 , LIEF::assembly::riscv::PseudoVMSEQ_VV_MF8 = 6954 , LIEF::assembly::riscv::PseudoVMSEQ_VV_MF8_MASK = 6955 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VX_M1 = 6956 , LIEF::assembly::riscv::PseudoVMSEQ_VX_M1_MASK = 6957 , LIEF::assembly::riscv::PseudoVMSEQ_VX_M2 = 6958 , LIEF::assembly::riscv::PseudoVMSEQ_VX_M2_MASK = 6959 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VX_M4 = 6960 , LIEF::assembly::riscv::PseudoVMSEQ_VX_M4_MASK = 6961 , LIEF::assembly::riscv::PseudoVMSEQ_VX_M8 = 6962 , LIEF::assembly::riscv::PseudoVMSEQ_VX_M8_MASK = 6963 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VX_MF2 = 6964 , LIEF::assembly::riscv::PseudoVMSEQ_VX_MF2_MASK = 6965 , LIEF::assembly::riscv::PseudoVMSEQ_VX_MF4 = 6966 , LIEF::assembly::riscv::PseudoVMSEQ_VX_MF4_MASK = 6967 ,
  LIEF::assembly::riscv::PseudoVMSEQ_VX_MF8 = 6968 , LIEF::assembly::riscv::PseudoVMSEQ_VX_MF8_MASK = 6969 , LIEF::assembly::riscv::PseudoVMSET_M_B1 = 6970 , LIEF::assembly::riscv::PseudoVMSET_M_B16 = 6971 ,
  LIEF::assembly::riscv::PseudoVMSET_M_B2 = 6972 , LIEF::assembly::riscv::PseudoVMSET_M_B32 = 6973 , LIEF::assembly::riscv::PseudoVMSET_M_B4 = 6974 , LIEF::assembly::riscv::PseudoVMSET_M_B64 = 6975 ,
  LIEF::assembly::riscv::PseudoVMSET_M_B8 = 6976 , LIEF::assembly::riscv::PseudoVMSGEU_VI = 6977 , LIEF::assembly::riscv::PseudoVMSGEU_VX = 6978 , LIEF::assembly::riscv::PseudoVMSGEU_VX_M = 6979 ,
  LIEF::assembly::riscv::PseudoVMSGEU_VX_M_T = 6980 , LIEF::assembly::riscv::PseudoVMSGE_VI = 6981 , LIEF::assembly::riscv::PseudoVMSGE_VX = 6982 , LIEF::assembly::riscv::PseudoVMSGE_VX_M = 6983 ,
  LIEF::assembly::riscv::PseudoVMSGE_VX_M_T = 6984 , LIEF::assembly::riscv::PseudoVMSGTU_VI_M1 = 6985 , LIEF::assembly::riscv::PseudoVMSGTU_VI_M1_MASK = 6986 , LIEF::assembly::riscv::PseudoVMSGTU_VI_M2 = 6987 ,
  LIEF::assembly::riscv::PseudoVMSGTU_VI_M2_MASK = 6988 , LIEF::assembly::riscv::PseudoVMSGTU_VI_M4 = 6989 , LIEF::assembly::riscv::PseudoVMSGTU_VI_M4_MASK = 6990 , LIEF::assembly::riscv::PseudoVMSGTU_VI_M8 = 6991 ,
  LIEF::assembly::riscv::PseudoVMSGTU_VI_M8_MASK = 6992 , LIEF::assembly::riscv::PseudoVMSGTU_VI_MF2 = 6993 , LIEF::assembly::riscv::PseudoVMSGTU_VI_MF2_MASK = 6994 , LIEF::assembly::riscv::PseudoVMSGTU_VI_MF4 = 6995 ,
  LIEF::assembly::riscv::PseudoVMSGTU_VI_MF4_MASK = 6996 , LIEF::assembly::riscv::PseudoVMSGTU_VI_MF8 = 6997 , LIEF::assembly::riscv::PseudoVMSGTU_VI_MF8_MASK = 6998 , LIEF::assembly::riscv::PseudoVMSGTU_VX_M1 = 6999 ,
  LIEF::assembly::riscv::PseudoVMSGTU_VX_M1_MASK = 7000 , LIEF::assembly::riscv::PseudoVMSGTU_VX_M2 = 7001 , LIEF::assembly::riscv::PseudoVMSGTU_VX_M2_MASK = 7002 , LIEF::assembly::riscv::PseudoVMSGTU_VX_M4 = 7003 ,
  LIEF::assembly::riscv::PseudoVMSGTU_VX_M4_MASK = 7004 , LIEF::assembly::riscv::PseudoVMSGTU_VX_M8 = 7005 , LIEF::assembly::riscv::PseudoVMSGTU_VX_M8_MASK = 7006 , LIEF::assembly::riscv::PseudoVMSGTU_VX_MF2 = 7007 ,
  LIEF::assembly::riscv::PseudoVMSGTU_VX_MF2_MASK = 7008 , LIEF::assembly::riscv::PseudoVMSGTU_VX_MF4 = 7009 , LIEF::assembly::riscv::PseudoVMSGTU_VX_MF4_MASK = 7010 , LIEF::assembly::riscv::PseudoVMSGTU_VX_MF8 = 7011 ,
  LIEF::assembly::riscv::PseudoVMSGTU_VX_MF8_MASK = 7012 , LIEF::assembly::riscv::PseudoVMSGT_VI_M1 = 7013 , LIEF::assembly::riscv::PseudoVMSGT_VI_M1_MASK = 7014 , LIEF::assembly::riscv::PseudoVMSGT_VI_M2 = 7015 ,
  LIEF::assembly::riscv::PseudoVMSGT_VI_M2_MASK = 7016 , LIEF::assembly::riscv::PseudoVMSGT_VI_M4 = 7017 , LIEF::assembly::riscv::PseudoVMSGT_VI_M4_MASK = 7018 , LIEF::assembly::riscv::PseudoVMSGT_VI_M8 = 7019 ,
  LIEF::assembly::riscv::PseudoVMSGT_VI_M8_MASK = 7020 , LIEF::assembly::riscv::PseudoVMSGT_VI_MF2 = 7021 , LIEF::assembly::riscv::PseudoVMSGT_VI_MF2_MASK = 7022 , LIEF::assembly::riscv::PseudoVMSGT_VI_MF4 = 7023 ,
  LIEF::assembly::riscv::PseudoVMSGT_VI_MF4_MASK = 7024 , LIEF::assembly::riscv::PseudoVMSGT_VI_MF8 = 7025 , LIEF::assembly::riscv::PseudoVMSGT_VI_MF8_MASK = 7026 , LIEF::assembly::riscv::PseudoVMSGT_VX_M1 = 7027 ,
  LIEF::assembly::riscv::PseudoVMSGT_VX_M1_MASK = 7028 , LIEF::assembly::riscv::PseudoVMSGT_VX_M2 = 7029 , LIEF::assembly::riscv::PseudoVMSGT_VX_M2_MASK = 7030 , LIEF::assembly::riscv::PseudoVMSGT_VX_M4 = 7031 ,
  LIEF::assembly::riscv::PseudoVMSGT_VX_M4_MASK = 7032 , LIEF::assembly::riscv::PseudoVMSGT_VX_M8 = 7033 , LIEF::assembly::riscv::PseudoVMSGT_VX_M8_MASK = 7034 , LIEF::assembly::riscv::PseudoVMSGT_VX_MF2 = 7035 ,
  LIEF::assembly::riscv::PseudoVMSGT_VX_MF2_MASK = 7036 , LIEF::assembly::riscv::PseudoVMSGT_VX_MF4 = 7037 , LIEF::assembly::riscv::PseudoVMSGT_VX_MF4_MASK = 7038 , LIEF::assembly::riscv::PseudoVMSGT_VX_MF8 = 7039 ,
  LIEF::assembly::riscv::PseudoVMSGT_VX_MF8_MASK = 7040 , LIEF::assembly::riscv::PseudoVMSIF_M_B1 = 7041 , LIEF::assembly::riscv::PseudoVMSIF_M_B16 = 7042 , LIEF::assembly::riscv::PseudoVMSIF_M_B16_MASK = 7043 ,
  LIEF::assembly::riscv::PseudoVMSIF_M_B1_MASK = 7044 , LIEF::assembly::riscv::PseudoVMSIF_M_B2 = 7045 , LIEF::assembly::riscv::PseudoVMSIF_M_B2_MASK = 7046 , LIEF::assembly::riscv::PseudoVMSIF_M_B32 = 7047 ,
  LIEF::assembly::riscv::PseudoVMSIF_M_B32_MASK = 7048 , LIEF::assembly::riscv::PseudoVMSIF_M_B4 = 7049 , LIEF::assembly::riscv::PseudoVMSIF_M_B4_MASK = 7050 , LIEF::assembly::riscv::PseudoVMSIF_M_B64 = 7051 ,
  LIEF::assembly::riscv::PseudoVMSIF_M_B64_MASK = 7052 , LIEF::assembly::riscv::PseudoVMSIF_M_B8 = 7053 , LIEF::assembly::riscv::PseudoVMSIF_M_B8_MASK = 7054 , LIEF::assembly::riscv::PseudoVMSLEU_VI_M1 = 7055 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VI_M1_MASK = 7056 , LIEF::assembly::riscv::PseudoVMSLEU_VI_M2 = 7057 , LIEF::assembly::riscv::PseudoVMSLEU_VI_M2_MASK = 7058 , LIEF::assembly::riscv::PseudoVMSLEU_VI_M4 = 7059 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VI_M4_MASK = 7060 , LIEF::assembly::riscv::PseudoVMSLEU_VI_M8 = 7061 , LIEF::assembly::riscv::PseudoVMSLEU_VI_M8_MASK = 7062 , LIEF::assembly::riscv::PseudoVMSLEU_VI_MF2 = 7063 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VI_MF2_MASK = 7064 , LIEF::assembly::riscv::PseudoVMSLEU_VI_MF4 = 7065 , LIEF::assembly::riscv::PseudoVMSLEU_VI_MF4_MASK = 7066 , LIEF::assembly::riscv::PseudoVMSLEU_VI_MF8 = 7067 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VI_MF8_MASK = 7068 , LIEF::assembly::riscv::PseudoVMSLEU_VV_M1 = 7069 , LIEF::assembly::riscv::PseudoVMSLEU_VV_M1_MASK = 7070 , LIEF::assembly::riscv::PseudoVMSLEU_VV_M2 = 7071 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VV_M2_MASK = 7072 , LIEF::assembly::riscv::PseudoVMSLEU_VV_M4 = 7073 , LIEF::assembly::riscv::PseudoVMSLEU_VV_M4_MASK = 7074 , LIEF::assembly::riscv::PseudoVMSLEU_VV_M8 = 7075 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VV_M8_MASK = 7076 , LIEF::assembly::riscv::PseudoVMSLEU_VV_MF2 = 7077 , LIEF::assembly::riscv::PseudoVMSLEU_VV_MF2_MASK = 7078 , LIEF::assembly::riscv::PseudoVMSLEU_VV_MF4 = 7079 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VV_MF4_MASK = 7080 , LIEF::assembly::riscv::PseudoVMSLEU_VV_MF8 = 7081 , LIEF::assembly::riscv::PseudoVMSLEU_VV_MF8_MASK = 7082 , LIEF::assembly::riscv::PseudoVMSLEU_VX_M1 = 7083 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VX_M1_MASK = 7084 , LIEF::assembly::riscv::PseudoVMSLEU_VX_M2 = 7085 , LIEF::assembly::riscv::PseudoVMSLEU_VX_M2_MASK = 7086 , LIEF::assembly::riscv::PseudoVMSLEU_VX_M4 = 7087 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VX_M4_MASK = 7088 , LIEF::assembly::riscv::PseudoVMSLEU_VX_M8 = 7089 , LIEF::assembly::riscv::PseudoVMSLEU_VX_M8_MASK = 7090 , LIEF::assembly::riscv::PseudoVMSLEU_VX_MF2 = 7091 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VX_MF2_MASK = 7092 , LIEF::assembly::riscv::PseudoVMSLEU_VX_MF4 = 7093 , LIEF::assembly::riscv::PseudoVMSLEU_VX_MF4_MASK = 7094 , LIEF::assembly::riscv::PseudoVMSLEU_VX_MF8 = 7095 ,
  LIEF::assembly::riscv::PseudoVMSLEU_VX_MF8_MASK = 7096 , LIEF::assembly::riscv::PseudoVMSLE_VI_M1 = 7097 , LIEF::assembly::riscv::PseudoVMSLE_VI_M1_MASK = 7098 , LIEF::assembly::riscv::PseudoVMSLE_VI_M2 = 7099 ,
  LIEF::assembly::riscv::PseudoVMSLE_VI_M2_MASK = 7100 , LIEF::assembly::riscv::PseudoVMSLE_VI_M4 = 7101 , LIEF::assembly::riscv::PseudoVMSLE_VI_M4_MASK = 7102 , LIEF::assembly::riscv::PseudoVMSLE_VI_M8 = 7103 ,
  LIEF::assembly::riscv::PseudoVMSLE_VI_M8_MASK = 7104 , LIEF::assembly::riscv::PseudoVMSLE_VI_MF2 = 7105 , LIEF::assembly::riscv::PseudoVMSLE_VI_MF2_MASK = 7106 , LIEF::assembly::riscv::PseudoVMSLE_VI_MF4 = 7107 ,
  LIEF::assembly::riscv::PseudoVMSLE_VI_MF4_MASK = 7108 , LIEF::assembly::riscv::PseudoVMSLE_VI_MF8 = 7109 , LIEF::assembly::riscv::PseudoVMSLE_VI_MF8_MASK = 7110 , LIEF::assembly::riscv::PseudoVMSLE_VV_M1 = 7111 ,
  LIEF::assembly::riscv::PseudoVMSLE_VV_M1_MASK = 7112 , LIEF::assembly::riscv::PseudoVMSLE_VV_M2 = 7113 , LIEF::assembly::riscv::PseudoVMSLE_VV_M2_MASK = 7114 , LIEF::assembly::riscv::PseudoVMSLE_VV_M4 = 7115 ,
  LIEF::assembly::riscv::PseudoVMSLE_VV_M4_MASK = 7116 , LIEF::assembly::riscv::PseudoVMSLE_VV_M8 = 7117 , LIEF::assembly::riscv::PseudoVMSLE_VV_M8_MASK = 7118 , LIEF::assembly::riscv::PseudoVMSLE_VV_MF2 = 7119 ,
  LIEF::assembly::riscv::PseudoVMSLE_VV_MF2_MASK = 7120 , LIEF::assembly::riscv::PseudoVMSLE_VV_MF4 = 7121 , LIEF::assembly::riscv::PseudoVMSLE_VV_MF4_MASK = 7122 , LIEF::assembly::riscv::PseudoVMSLE_VV_MF8 = 7123 ,
  LIEF::assembly::riscv::PseudoVMSLE_VV_MF8_MASK = 7124 , LIEF::assembly::riscv::PseudoVMSLE_VX_M1 = 7125 , LIEF::assembly::riscv::PseudoVMSLE_VX_M1_MASK = 7126 , LIEF::assembly::riscv::PseudoVMSLE_VX_M2 = 7127 ,
  LIEF::assembly::riscv::PseudoVMSLE_VX_M2_MASK = 7128 , LIEF::assembly::riscv::PseudoVMSLE_VX_M4 = 7129 , LIEF::assembly::riscv::PseudoVMSLE_VX_M4_MASK = 7130 , LIEF::assembly::riscv::PseudoVMSLE_VX_M8 = 7131 ,
  LIEF::assembly::riscv::PseudoVMSLE_VX_M8_MASK = 7132 , LIEF::assembly::riscv::PseudoVMSLE_VX_MF2 = 7133 , LIEF::assembly::riscv::PseudoVMSLE_VX_MF2_MASK = 7134 , LIEF::assembly::riscv::PseudoVMSLE_VX_MF4 = 7135 ,
  LIEF::assembly::riscv::PseudoVMSLE_VX_MF4_MASK = 7136 , LIEF::assembly::riscv::PseudoVMSLE_VX_MF8 = 7137 , LIEF::assembly::riscv::PseudoVMSLE_VX_MF8_MASK = 7138 , LIEF::assembly::riscv::PseudoVMSLTU_VI = 7139 ,
  LIEF::assembly::riscv::PseudoVMSLTU_VV_M1 = 7140 , LIEF::assembly::riscv::PseudoVMSLTU_VV_M1_MASK = 7141 , LIEF::assembly::riscv::PseudoVMSLTU_VV_M2 = 7142 , LIEF::assembly::riscv::PseudoVMSLTU_VV_M2_MASK = 7143 ,
  LIEF::assembly::riscv::PseudoVMSLTU_VV_M4 = 7144 , LIEF::assembly::riscv::PseudoVMSLTU_VV_M4_MASK = 7145 , LIEF::assembly::riscv::PseudoVMSLTU_VV_M8 = 7146 , LIEF::assembly::riscv::PseudoVMSLTU_VV_M8_MASK = 7147 ,
  LIEF::assembly::riscv::PseudoVMSLTU_VV_MF2 = 7148 , LIEF::assembly::riscv::PseudoVMSLTU_VV_MF2_MASK = 7149 , LIEF::assembly::riscv::PseudoVMSLTU_VV_MF4 = 7150 , LIEF::assembly::riscv::PseudoVMSLTU_VV_MF4_MASK = 7151 ,
  LIEF::assembly::riscv::PseudoVMSLTU_VV_MF8 = 7152 , LIEF::assembly::riscv::PseudoVMSLTU_VV_MF8_MASK = 7153 , LIEF::assembly::riscv::PseudoVMSLTU_VX_M1 = 7154 , LIEF::assembly::riscv::PseudoVMSLTU_VX_M1_MASK = 7155 ,
  LIEF::assembly::riscv::PseudoVMSLTU_VX_M2 = 7156 , LIEF::assembly::riscv::PseudoVMSLTU_VX_M2_MASK = 7157 , LIEF::assembly::riscv::PseudoVMSLTU_VX_M4 = 7158 , LIEF::assembly::riscv::PseudoVMSLTU_VX_M4_MASK = 7159 ,
  LIEF::assembly::riscv::PseudoVMSLTU_VX_M8 = 7160 , LIEF::assembly::riscv::PseudoVMSLTU_VX_M8_MASK = 7161 , LIEF::assembly::riscv::PseudoVMSLTU_VX_MF2 = 7162 , LIEF::assembly::riscv::PseudoVMSLTU_VX_MF2_MASK = 7163 ,
  LIEF::assembly::riscv::PseudoVMSLTU_VX_MF4 = 7164 , LIEF::assembly::riscv::PseudoVMSLTU_VX_MF4_MASK = 7165 , LIEF::assembly::riscv::PseudoVMSLTU_VX_MF8 = 7166 , LIEF::assembly::riscv::PseudoVMSLTU_VX_MF8_MASK = 7167 ,
  LIEF::assembly::riscv::PseudoVMSLT_VI = 7168 , LIEF::assembly::riscv::PseudoVMSLT_VV_M1 = 7169 , LIEF::assembly::riscv::PseudoVMSLT_VV_M1_MASK = 7170 , LIEF::assembly::riscv::PseudoVMSLT_VV_M2 = 7171 ,
  LIEF::assembly::riscv::PseudoVMSLT_VV_M2_MASK = 7172 , LIEF::assembly::riscv::PseudoVMSLT_VV_M4 = 7173 , LIEF::assembly::riscv::PseudoVMSLT_VV_M4_MASK = 7174 , LIEF::assembly::riscv::PseudoVMSLT_VV_M8 = 7175 ,
  LIEF::assembly::riscv::PseudoVMSLT_VV_M8_MASK = 7176 , LIEF::assembly::riscv::PseudoVMSLT_VV_MF2 = 7177 , LIEF::assembly::riscv::PseudoVMSLT_VV_MF2_MASK = 7178 , LIEF::assembly::riscv::PseudoVMSLT_VV_MF4 = 7179 ,
  LIEF::assembly::riscv::PseudoVMSLT_VV_MF4_MASK = 7180 , LIEF::assembly::riscv::PseudoVMSLT_VV_MF8 = 7181 , LIEF::assembly::riscv::PseudoVMSLT_VV_MF8_MASK = 7182 , LIEF::assembly::riscv::PseudoVMSLT_VX_M1 = 7183 ,
  LIEF::assembly::riscv::PseudoVMSLT_VX_M1_MASK = 7184 , LIEF::assembly::riscv::PseudoVMSLT_VX_M2 = 7185 , LIEF::assembly::riscv::PseudoVMSLT_VX_M2_MASK = 7186 , LIEF::assembly::riscv::PseudoVMSLT_VX_M4 = 7187 ,
  LIEF::assembly::riscv::PseudoVMSLT_VX_M4_MASK = 7188 , LIEF::assembly::riscv::PseudoVMSLT_VX_M8 = 7189 , LIEF::assembly::riscv::PseudoVMSLT_VX_M8_MASK = 7190 , LIEF::assembly::riscv::PseudoVMSLT_VX_MF2 = 7191 ,
  LIEF::assembly::riscv::PseudoVMSLT_VX_MF2_MASK = 7192 , LIEF::assembly::riscv::PseudoVMSLT_VX_MF4 = 7193 , LIEF::assembly::riscv::PseudoVMSLT_VX_MF4_MASK = 7194 , LIEF::assembly::riscv::PseudoVMSLT_VX_MF8 = 7195 ,
  LIEF::assembly::riscv::PseudoVMSLT_VX_MF8_MASK = 7196 , LIEF::assembly::riscv::PseudoVMSNE_VI_M1 = 7197 , LIEF::assembly::riscv::PseudoVMSNE_VI_M1_MASK = 7198 , LIEF::assembly::riscv::PseudoVMSNE_VI_M2 = 7199 ,
  LIEF::assembly::riscv::PseudoVMSNE_VI_M2_MASK = 7200 , LIEF::assembly::riscv::PseudoVMSNE_VI_M4 = 7201 , LIEF::assembly::riscv::PseudoVMSNE_VI_M4_MASK = 7202 , LIEF::assembly::riscv::PseudoVMSNE_VI_M8 = 7203 ,
  LIEF::assembly::riscv::PseudoVMSNE_VI_M8_MASK = 7204 , LIEF::assembly::riscv::PseudoVMSNE_VI_MF2 = 7205 , LIEF::assembly::riscv::PseudoVMSNE_VI_MF2_MASK = 7206 , LIEF::assembly::riscv::PseudoVMSNE_VI_MF4 = 7207 ,
  LIEF::assembly::riscv::PseudoVMSNE_VI_MF4_MASK = 7208 , LIEF::assembly::riscv::PseudoVMSNE_VI_MF8 = 7209 , LIEF::assembly::riscv::PseudoVMSNE_VI_MF8_MASK = 7210 , LIEF::assembly::riscv::PseudoVMSNE_VV_M1 = 7211 ,
  LIEF::assembly::riscv::PseudoVMSNE_VV_M1_MASK = 7212 , LIEF::assembly::riscv::PseudoVMSNE_VV_M2 = 7213 , LIEF::assembly::riscv::PseudoVMSNE_VV_M2_MASK = 7214 , LIEF::assembly::riscv::PseudoVMSNE_VV_M4 = 7215 ,
  LIEF::assembly::riscv::PseudoVMSNE_VV_M4_MASK = 7216 , LIEF::assembly::riscv::PseudoVMSNE_VV_M8 = 7217 , LIEF::assembly::riscv::PseudoVMSNE_VV_M8_MASK = 7218 , LIEF::assembly::riscv::PseudoVMSNE_VV_MF2 = 7219 ,
  LIEF::assembly::riscv::PseudoVMSNE_VV_MF2_MASK = 7220 , LIEF::assembly::riscv::PseudoVMSNE_VV_MF4 = 7221 , LIEF::assembly::riscv::PseudoVMSNE_VV_MF4_MASK = 7222 , LIEF::assembly::riscv::PseudoVMSNE_VV_MF8 = 7223 ,
  LIEF::assembly::riscv::PseudoVMSNE_VV_MF8_MASK = 7224 , LIEF::assembly::riscv::PseudoVMSNE_VX_M1 = 7225 , LIEF::assembly::riscv::PseudoVMSNE_VX_M1_MASK = 7226 , LIEF::assembly::riscv::PseudoVMSNE_VX_M2 = 7227 ,
  LIEF::assembly::riscv::PseudoVMSNE_VX_M2_MASK = 7228 , LIEF::assembly::riscv::PseudoVMSNE_VX_M4 = 7229 , LIEF::assembly::riscv::PseudoVMSNE_VX_M4_MASK = 7230 , LIEF::assembly::riscv::PseudoVMSNE_VX_M8 = 7231 ,
  LIEF::assembly::riscv::PseudoVMSNE_VX_M8_MASK = 7232 , LIEF::assembly::riscv::PseudoVMSNE_VX_MF2 = 7233 , LIEF::assembly::riscv::PseudoVMSNE_VX_MF2_MASK = 7234 , LIEF::assembly::riscv::PseudoVMSNE_VX_MF4 = 7235 ,
  LIEF::assembly::riscv::PseudoVMSNE_VX_MF4_MASK = 7236 , LIEF::assembly::riscv::PseudoVMSNE_VX_MF8 = 7237 , LIEF::assembly::riscv::PseudoVMSNE_VX_MF8_MASK = 7238 , LIEF::assembly::riscv::PseudoVMSOF_M_B1 = 7239 ,
  LIEF::assembly::riscv::PseudoVMSOF_M_B16 = 7240 , LIEF::assembly::riscv::PseudoVMSOF_M_B16_MASK = 7241 , LIEF::assembly::riscv::PseudoVMSOF_M_B1_MASK = 7242 , LIEF::assembly::riscv::PseudoVMSOF_M_B2 = 7243 ,
  LIEF::assembly::riscv::PseudoVMSOF_M_B2_MASK = 7244 , LIEF::assembly::riscv::PseudoVMSOF_M_B32 = 7245 , LIEF::assembly::riscv::PseudoVMSOF_M_B32_MASK = 7246 , LIEF::assembly::riscv::PseudoVMSOF_M_B4 = 7247 ,
  LIEF::assembly::riscv::PseudoVMSOF_M_B4_MASK = 7248 , LIEF::assembly::riscv::PseudoVMSOF_M_B64 = 7249 , LIEF::assembly::riscv::PseudoVMSOF_M_B64_MASK = 7250 , LIEF::assembly::riscv::PseudoVMSOF_M_B8 = 7251 ,
  LIEF::assembly::riscv::PseudoVMSOF_M_B8_MASK = 7252 , LIEF::assembly::riscv::PseudoVMULHSU_VV_M1 = 7253 , LIEF::assembly::riscv::PseudoVMULHSU_VV_M1_MASK = 7254 , LIEF::assembly::riscv::PseudoVMULHSU_VV_M2 = 7255 ,
  LIEF::assembly::riscv::PseudoVMULHSU_VV_M2_MASK = 7256 , LIEF::assembly::riscv::PseudoVMULHSU_VV_M4 = 7257 , LIEF::assembly::riscv::PseudoVMULHSU_VV_M4_MASK = 7258 , LIEF::assembly::riscv::PseudoVMULHSU_VV_M8 = 7259 ,
  LIEF::assembly::riscv::PseudoVMULHSU_VV_M8_MASK = 7260 , LIEF::assembly::riscv::PseudoVMULHSU_VV_MF2 = 7261 , LIEF::assembly::riscv::PseudoVMULHSU_VV_MF2_MASK = 7262 , LIEF::assembly::riscv::PseudoVMULHSU_VV_MF4 = 7263 ,
  LIEF::assembly::riscv::PseudoVMULHSU_VV_MF4_MASK = 7264 , LIEF::assembly::riscv::PseudoVMULHSU_VV_MF8 = 7265 , LIEF::assembly::riscv::PseudoVMULHSU_VV_MF8_MASK = 7266 , LIEF::assembly::riscv::PseudoVMULHSU_VX_M1 = 7267 ,
  LIEF::assembly::riscv::PseudoVMULHSU_VX_M1_MASK = 7268 , LIEF::assembly::riscv::PseudoVMULHSU_VX_M2 = 7269 , LIEF::assembly::riscv::PseudoVMULHSU_VX_M2_MASK = 7270 , LIEF::assembly::riscv::PseudoVMULHSU_VX_M4 = 7271 ,
  LIEF::assembly::riscv::PseudoVMULHSU_VX_M4_MASK = 7272 , LIEF::assembly::riscv::PseudoVMULHSU_VX_M8 = 7273 , LIEF::assembly::riscv::PseudoVMULHSU_VX_M8_MASK = 7274 , LIEF::assembly::riscv::PseudoVMULHSU_VX_MF2 = 7275 ,
  LIEF::assembly::riscv::PseudoVMULHSU_VX_MF2_MASK = 7276 , LIEF::assembly::riscv::PseudoVMULHSU_VX_MF4 = 7277 , LIEF::assembly::riscv::PseudoVMULHSU_VX_MF4_MASK = 7278 , LIEF::assembly::riscv::PseudoVMULHSU_VX_MF8 = 7279 ,
  LIEF::assembly::riscv::PseudoVMULHSU_VX_MF8_MASK = 7280 , LIEF::assembly::riscv::PseudoVMULHU_VV_M1 = 7281 , LIEF::assembly::riscv::PseudoVMULHU_VV_M1_MASK = 7282 , LIEF::assembly::riscv::PseudoVMULHU_VV_M2 = 7283 ,
  LIEF::assembly::riscv::PseudoVMULHU_VV_M2_MASK = 7284 , LIEF::assembly::riscv::PseudoVMULHU_VV_M4 = 7285 , LIEF::assembly::riscv::PseudoVMULHU_VV_M4_MASK = 7286 , LIEF::assembly::riscv::PseudoVMULHU_VV_M8 = 7287 ,
  LIEF::assembly::riscv::PseudoVMULHU_VV_M8_MASK = 7288 , LIEF::assembly::riscv::PseudoVMULHU_VV_MF2 = 7289 , LIEF::assembly::riscv::PseudoVMULHU_VV_MF2_MASK = 7290 , LIEF::assembly::riscv::PseudoVMULHU_VV_MF4 = 7291 ,
  LIEF::assembly::riscv::PseudoVMULHU_VV_MF4_MASK = 7292 , LIEF::assembly::riscv::PseudoVMULHU_VV_MF8 = 7293 , LIEF::assembly::riscv::PseudoVMULHU_VV_MF8_MASK = 7294 , LIEF::assembly::riscv::PseudoVMULHU_VX_M1 = 7295 ,
  LIEF::assembly::riscv::PseudoVMULHU_VX_M1_MASK = 7296 , LIEF::assembly::riscv::PseudoVMULHU_VX_M2 = 7297 , LIEF::assembly::riscv::PseudoVMULHU_VX_M2_MASK = 7298 , LIEF::assembly::riscv::PseudoVMULHU_VX_M4 = 7299 ,
  LIEF::assembly::riscv::PseudoVMULHU_VX_M4_MASK = 7300 , LIEF::assembly::riscv::PseudoVMULHU_VX_M8 = 7301 , LIEF::assembly::riscv::PseudoVMULHU_VX_M8_MASK = 7302 , LIEF::assembly::riscv::PseudoVMULHU_VX_MF2 = 7303 ,
  LIEF::assembly::riscv::PseudoVMULHU_VX_MF2_MASK = 7304 , LIEF::assembly::riscv::PseudoVMULHU_VX_MF4 = 7305 , LIEF::assembly::riscv::PseudoVMULHU_VX_MF4_MASK = 7306 , LIEF::assembly::riscv::PseudoVMULHU_VX_MF8 = 7307 ,
  LIEF::assembly::riscv::PseudoVMULHU_VX_MF8_MASK = 7308 , LIEF::assembly::riscv::PseudoVMULH_VV_M1 = 7309 , LIEF::assembly::riscv::PseudoVMULH_VV_M1_MASK = 7310 , LIEF::assembly::riscv::PseudoVMULH_VV_M2 = 7311 ,
  LIEF::assembly::riscv::PseudoVMULH_VV_M2_MASK = 7312 , LIEF::assembly::riscv::PseudoVMULH_VV_M4 = 7313 , LIEF::assembly::riscv::PseudoVMULH_VV_M4_MASK = 7314 , LIEF::assembly::riscv::PseudoVMULH_VV_M8 = 7315 ,
  LIEF::assembly::riscv::PseudoVMULH_VV_M8_MASK = 7316 , LIEF::assembly::riscv::PseudoVMULH_VV_MF2 = 7317 , LIEF::assembly::riscv::PseudoVMULH_VV_MF2_MASK = 7318 , LIEF::assembly::riscv::PseudoVMULH_VV_MF4 = 7319 ,
  LIEF::assembly::riscv::PseudoVMULH_VV_MF4_MASK = 7320 , LIEF::assembly::riscv::PseudoVMULH_VV_MF8 = 7321 , LIEF::assembly::riscv::PseudoVMULH_VV_MF8_MASK = 7322 , LIEF::assembly::riscv::PseudoVMULH_VX_M1 = 7323 ,
  LIEF::assembly::riscv::PseudoVMULH_VX_M1_MASK = 7324 , LIEF::assembly::riscv::PseudoVMULH_VX_M2 = 7325 , LIEF::assembly::riscv::PseudoVMULH_VX_M2_MASK = 7326 , LIEF::assembly::riscv::PseudoVMULH_VX_M4 = 7327 ,
  LIEF::assembly::riscv::PseudoVMULH_VX_M4_MASK = 7328 , LIEF::assembly::riscv::PseudoVMULH_VX_M8 = 7329 , LIEF::assembly::riscv::PseudoVMULH_VX_M8_MASK = 7330 , LIEF::assembly::riscv::PseudoVMULH_VX_MF2 = 7331 ,
  LIEF::assembly::riscv::PseudoVMULH_VX_MF2_MASK = 7332 , LIEF::assembly::riscv::PseudoVMULH_VX_MF4 = 7333 , LIEF::assembly::riscv::PseudoVMULH_VX_MF4_MASK = 7334 , LIEF::assembly::riscv::PseudoVMULH_VX_MF8 = 7335 ,
  LIEF::assembly::riscv::PseudoVMULH_VX_MF8_MASK = 7336 , LIEF::assembly::riscv::PseudoVMUL_VV_M1 = 7337 , LIEF::assembly::riscv::PseudoVMUL_VV_M1_MASK = 7338 , LIEF::assembly::riscv::PseudoVMUL_VV_M2 = 7339 ,
  LIEF::assembly::riscv::PseudoVMUL_VV_M2_MASK = 7340 , LIEF::assembly::riscv::PseudoVMUL_VV_M4 = 7341 , LIEF::assembly::riscv::PseudoVMUL_VV_M4_MASK = 7342 , LIEF::assembly::riscv::PseudoVMUL_VV_M8 = 7343 ,
  LIEF::assembly::riscv::PseudoVMUL_VV_M8_MASK = 7344 , LIEF::assembly::riscv::PseudoVMUL_VV_MF2 = 7345 , LIEF::assembly::riscv::PseudoVMUL_VV_MF2_MASK = 7346 , LIEF::assembly::riscv::PseudoVMUL_VV_MF4 = 7347 ,
  LIEF::assembly::riscv::PseudoVMUL_VV_MF4_MASK = 7348 , LIEF::assembly::riscv::PseudoVMUL_VV_MF8 = 7349 , LIEF::assembly::riscv::PseudoVMUL_VV_MF8_MASK = 7350 , LIEF::assembly::riscv::PseudoVMUL_VX_M1 = 7351 ,
  LIEF::assembly::riscv::PseudoVMUL_VX_M1_MASK = 7352 , LIEF::assembly::riscv::PseudoVMUL_VX_M2 = 7353 , LIEF::assembly::riscv::PseudoVMUL_VX_M2_MASK = 7354 , LIEF::assembly::riscv::PseudoVMUL_VX_M4 = 7355 ,
  LIEF::assembly::riscv::PseudoVMUL_VX_M4_MASK = 7356 , LIEF::assembly::riscv::PseudoVMUL_VX_M8 = 7357 , LIEF::assembly::riscv::PseudoVMUL_VX_M8_MASK = 7358 , LIEF::assembly::riscv::PseudoVMUL_VX_MF2 = 7359 ,
  LIEF::assembly::riscv::PseudoVMUL_VX_MF2_MASK = 7360 , LIEF::assembly::riscv::PseudoVMUL_VX_MF4 = 7361 , LIEF::assembly::riscv::PseudoVMUL_VX_MF4_MASK = 7362 , LIEF::assembly::riscv::PseudoVMUL_VX_MF8 = 7363 ,
  LIEF::assembly::riscv::PseudoVMUL_VX_MF8_MASK = 7364 , LIEF::assembly::riscv::PseudoVMV_S_X = 7365 , LIEF::assembly::riscv::PseudoVMV_V_I_M1 = 7366 , LIEF::assembly::riscv::PseudoVMV_V_I_M2 = 7367 ,
  LIEF::assembly::riscv::PseudoVMV_V_I_M4 = 7368 , LIEF::assembly::riscv::PseudoVMV_V_I_M8 = 7369 , LIEF::assembly::riscv::PseudoVMV_V_I_MF2 = 7370 , LIEF::assembly::riscv::PseudoVMV_V_I_MF4 = 7371 ,
  LIEF::assembly::riscv::PseudoVMV_V_I_MF8 = 7372 , LIEF::assembly::riscv::PseudoVMV_V_V_M1 = 7373 , LIEF::assembly::riscv::PseudoVMV_V_V_M2 = 7374 , LIEF::assembly::riscv::PseudoVMV_V_V_M4 = 7375 ,
  LIEF::assembly::riscv::PseudoVMV_V_V_M8 = 7376 , LIEF::assembly::riscv::PseudoVMV_V_V_MF2 = 7377 , LIEF::assembly::riscv::PseudoVMV_V_V_MF4 = 7378 , LIEF::assembly::riscv::PseudoVMV_V_V_MF8 = 7379 ,
  LIEF::assembly::riscv::PseudoVMV_V_X_M1 = 7380 , LIEF::assembly::riscv::PseudoVMV_V_X_M2 = 7381 , LIEF::assembly::riscv::PseudoVMV_V_X_M4 = 7382 , LIEF::assembly::riscv::PseudoVMV_V_X_M8 = 7383 ,
  LIEF::assembly::riscv::PseudoVMV_V_X_MF2 = 7384 , LIEF::assembly::riscv::PseudoVMV_V_X_MF4 = 7385 , LIEF::assembly::riscv::PseudoVMV_V_X_MF8 = 7386 , LIEF::assembly::riscv::PseudoVMV_X_S = 7387 ,
  LIEF::assembly::riscv::PseudoVMXNOR_MM_M1 = 7388 , LIEF::assembly::riscv::PseudoVMXNOR_MM_M2 = 7389 , LIEF::assembly::riscv::PseudoVMXNOR_MM_M4 = 7390 , LIEF::assembly::riscv::PseudoVMXNOR_MM_M8 = 7391 ,
  LIEF::assembly::riscv::PseudoVMXNOR_MM_MF2 = 7392 , LIEF::assembly::riscv::PseudoVMXNOR_MM_MF4 = 7393 , LIEF::assembly::riscv::PseudoVMXNOR_MM_MF8 = 7394 , LIEF::assembly::riscv::PseudoVMXOR_MM_M1 = 7395 ,
  LIEF::assembly::riscv::PseudoVMXOR_MM_M2 = 7396 , LIEF::assembly::riscv::PseudoVMXOR_MM_M4 = 7397 , LIEF::assembly::riscv::PseudoVMXOR_MM_M8 = 7398 , LIEF::assembly::riscv::PseudoVMXOR_MM_MF2 = 7399 ,
  LIEF::assembly::riscv::PseudoVMXOR_MM_MF4 = 7400 , LIEF::assembly::riscv::PseudoVMXOR_MM_MF8 = 7401 , LIEF::assembly::riscv::PseudoVNCLIPU_WI_M1 = 7402 , LIEF::assembly::riscv::PseudoVNCLIPU_WI_M1_MASK = 7403 ,
  LIEF::assembly::riscv::PseudoVNCLIPU_WI_M2 = 7404 , LIEF::assembly::riscv::PseudoVNCLIPU_WI_M2_MASK = 7405 , LIEF::assembly::riscv::PseudoVNCLIPU_WI_M4 = 7406 , LIEF::assembly::riscv::PseudoVNCLIPU_WI_M4_MASK = 7407 ,
  LIEF::assembly::riscv::PseudoVNCLIPU_WI_MF2 = 7408 , LIEF::assembly::riscv::PseudoVNCLIPU_WI_MF2_MASK = 7409 , LIEF::assembly::riscv::PseudoVNCLIPU_WI_MF4 = 7410 , LIEF::assembly::riscv::PseudoVNCLIPU_WI_MF4_MASK = 7411 ,
  LIEF::assembly::riscv::PseudoVNCLIPU_WI_MF8 = 7412 , LIEF::assembly::riscv::PseudoVNCLIPU_WI_MF8_MASK = 7413 , LIEF::assembly::riscv::PseudoVNCLIPU_WV_M1 = 7414 , LIEF::assembly::riscv::PseudoVNCLIPU_WV_M1_MASK = 7415 ,
  LIEF::assembly::riscv::PseudoVNCLIPU_WV_M2 = 7416 , LIEF::assembly::riscv::PseudoVNCLIPU_WV_M2_MASK = 7417 , LIEF::assembly::riscv::PseudoVNCLIPU_WV_M4 = 7418 , LIEF::assembly::riscv::PseudoVNCLIPU_WV_M4_MASK = 7419 ,
  LIEF::assembly::riscv::PseudoVNCLIPU_WV_MF2 = 7420 , LIEF::assembly::riscv::PseudoVNCLIPU_WV_MF2_MASK = 7421 , LIEF::assembly::riscv::PseudoVNCLIPU_WV_MF4 = 7422 , LIEF::assembly::riscv::PseudoVNCLIPU_WV_MF4_MASK = 7423 ,
  LIEF::assembly::riscv::PseudoVNCLIPU_WV_MF8 = 7424 , LIEF::assembly::riscv::PseudoVNCLIPU_WV_MF8_MASK = 7425 , LIEF::assembly::riscv::PseudoVNCLIPU_WX_M1 = 7426 , LIEF::assembly::riscv::PseudoVNCLIPU_WX_M1_MASK = 7427 ,
  LIEF::assembly::riscv::PseudoVNCLIPU_WX_M2 = 7428 , LIEF::assembly::riscv::PseudoVNCLIPU_WX_M2_MASK = 7429 , LIEF::assembly::riscv::PseudoVNCLIPU_WX_M4 = 7430 , LIEF::assembly::riscv::PseudoVNCLIPU_WX_M4_MASK = 7431 ,
  LIEF::assembly::riscv::PseudoVNCLIPU_WX_MF2 = 7432 , LIEF::assembly::riscv::PseudoVNCLIPU_WX_MF2_MASK = 7433 , LIEF::assembly::riscv::PseudoVNCLIPU_WX_MF4 = 7434 , LIEF::assembly::riscv::PseudoVNCLIPU_WX_MF4_MASK = 7435 ,
  LIEF::assembly::riscv::PseudoVNCLIPU_WX_MF8 = 7436 , LIEF::assembly::riscv::PseudoVNCLIPU_WX_MF8_MASK = 7437 , LIEF::assembly::riscv::PseudoVNCLIP_WI_M1 = 7438 , LIEF::assembly::riscv::PseudoVNCLIP_WI_M1_MASK = 7439 ,
  LIEF::assembly::riscv::PseudoVNCLIP_WI_M2 = 7440 , LIEF::assembly::riscv::PseudoVNCLIP_WI_M2_MASK = 7441 , LIEF::assembly::riscv::PseudoVNCLIP_WI_M4 = 7442 , LIEF::assembly::riscv::PseudoVNCLIP_WI_M4_MASK = 7443 ,
  LIEF::assembly::riscv::PseudoVNCLIP_WI_MF2 = 7444 , LIEF::assembly::riscv::PseudoVNCLIP_WI_MF2_MASK = 7445 , LIEF::assembly::riscv::PseudoVNCLIP_WI_MF4 = 7446 , LIEF::assembly::riscv::PseudoVNCLIP_WI_MF4_MASK = 7447 ,
  LIEF::assembly::riscv::PseudoVNCLIP_WI_MF8 = 7448 , LIEF::assembly::riscv::PseudoVNCLIP_WI_MF8_MASK = 7449 , LIEF::assembly::riscv::PseudoVNCLIP_WV_M1 = 7450 , LIEF::assembly::riscv::PseudoVNCLIP_WV_M1_MASK = 7451 ,
  LIEF::assembly::riscv::PseudoVNCLIP_WV_M2 = 7452 , LIEF::assembly::riscv::PseudoVNCLIP_WV_M2_MASK = 7453 , LIEF::assembly::riscv::PseudoVNCLIP_WV_M4 = 7454 , LIEF::assembly::riscv::PseudoVNCLIP_WV_M4_MASK = 7455 ,
  LIEF::assembly::riscv::PseudoVNCLIP_WV_MF2 = 7456 , LIEF::assembly::riscv::PseudoVNCLIP_WV_MF2_MASK = 7457 , LIEF::assembly::riscv::PseudoVNCLIP_WV_MF4 = 7458 , LIEF::assembly::riscv::PseudoVNCLIP_WV_MF4_MASK = 7459 ,
  LIEF::assembly::riscv::PseudoVNCLIP_WV_MF8 = 7460 , LIEF::assembly::riscv::PseudoVNCLIP_WV_MF8_MASK = 7461 , LIEF::assembly::riscv::PseudoVNCLIP_WX_M1 = 7462 , LIEF::assembly::riscv::PseudoVNCLIP_WX_M1_MASK = 7463 ,
  LIEF::assembly::riscv::PseudoVNCLIP_WX_M2 = 7464 , LIEF::assembly::riscv::PseudoVNCLIP_WX_M2_MASK = 7465 , LIEF::assembly::riscv::PseudoVNCLIP_WX_M4 = 7466 , LIEF::assembly::riscv::PseudoVNCLIP_WX_M4_MASK = 7467 ,
  LIEF::assembly::riscv::PseudoVNCLIP_WX_MF2 = 7468 , LIEF::assembly::riscv::PseudoVNCLIP_WX_MF2_MASK = 7469 , LIEF::assembly::riscv::PseudoVNCLIP_WX_MF4 = 7470 , LIEF::assembly::riscv::PseudoVNCLIP_WX_MF4_MASK = 7471 ,
  LIEF::assembly::riscv::PseudoVNCLIP_WX_MF8 = 7472 , LIEF::assembly::riscv::PseudoVNCLIP_WX_MF8_MASK = 7473 , LIEF::assembly::riscv::PseudoVNMSAC_VV_M1 = 7474 , LIEF::assembly::riscv::PseudoVNMSAC_VV_M1_MASK = 7475 ,
  LIEF::assembly::riscv::PseudoVNMSAC_VV_M2 = 7476 , LIEF::assembly::riscv::PseudoVNMSAC_VV_M2_MASK = 7477 , LIEF::assembly::riscv::PseudoVNMSAC_VV_M4 = 7478 , LIEF::assembly::riscv::PseudoVNMSAC_VV_M4_MASK = 7479 ,
  LIEF::assembly::riscv::PseudoVNMSAC_VV_M8 = 7480 , LIEF::assembly::riscv::PseudoVNMSAC_VV_M8_MASK = 7481 , LIEF::assembly::riscv::PseudoVNMSAC_VV_MF2 = 7482 , LIEF::assembly::riscv::PseudoVNMSAC_VV_MF2_MASK = 7483 ,
  LIEF::assembly::riscv::PseudoVNMSAC_VV_MF4 = 7484 , LIEF::assembly::riscv::PseudoVNMSAC_VV_MF4_MASK = 7485 , LIEF::assembly::riscv::PseudoVNMSAC_VV_MF8 = 7486 , LIEF::assembly::riscv::PseudoVNMSAC_VV_MF8_MASK = 7487 ,
  LIEF::assembly::riscv::PseudoVNMSAC_VX_M1 = 7488 , LIEF::assembly::riscv::PseudoVNMSAC_VX_M1_MASK = 7489 , LIEF::assembly::riscv::PseudoVNMSAC_VX_M2 = 7490 , LIEF::assembly::riscv::PseudoVNMSAC_VX_M2_MASK = 7491 ,
  LIEF::assembly::riscv::PseudoVNMSAC_VX_M4 = 7492 , LIEF::assembly::riscv::PseudoVNMSAC_VX_M4_MASK = 7493 , LIEF::assembly::riscv::PseudoVNMSAC_VX_M8 = 7494 , LIEF::assembly::riscv::PseudoVNMSAC_VX_M8_MASK = 7495 ,
  LIEF::assembly::riscv::PseudoVNMSAC_VX_MF2 = 7496 , LIEF::assembly::riscv::PseudoVNMSAC_VX_MF2_MASK = 7497 , LIEF::assembly::riscv::PseudoVNMSAC_VX_MF4 = 7498 , LIEF::assembly::riscv::PseudoVNMSAC_VX_MF4_MASK = 7499 ,
  LIEF::assembly::riscv::PseudoVNMSAC_VX_MF8 = 7500 , LIEF::assembly::riscv::PseudoVNMSAC_VX_MF8_MASK = 7501 , LIEF::assembly::riscv::PseudoVNMSUB_VV_M1 = 7502 , LIEF::assembly::riscv::PseudoVNMSUB_VV_M1_MASK = 7503 ,
  LIEF::assembly::riscv::PseudoVNMSUB_VV_M2 = 7504 , LIEF::assembly::riscv::PseudoVNMSUB_VV_M2_MASK = 7505 , LIEF::assembly::riscv::PseudoVNMSUB_VV_M4 = 7506 , LIEF::assembly::riscv::PseudoVNMSUB_VV_M4_MASK = 7507 ,
  LIEF::assembly::riscv::PseudoVNMSUB_VV_M8 = 7508 , LIEF::assembly::riscv::PseudoVNMSUB_VV_M8_MASK = 7509 , LIEF::assembly::riscv::PseudoVNMSUB_VV_MF2 = 7510 , LIEF::assembly::riscv::PseudoVNMSUB_VV_MF2_MASK = 7511 ,
  LIEF::assembly::riscv::PseudoVNMSUB_VV_MF4 = 7512 , LIEF::assembly::riscv::PseudoVNMSUB_VV_MF4_MASK = 7513 , LIEF::assembly::riscv::PseudoVNMSUB_VV_MF8 = 7514 , LIEF::assembly::riscv::PseudoVNMSUB_VV_MF8_MASK = 7515 ,
  LIEF::assembly::riscv::PseudoVNMSUB_VX_M1 = 7516 , LIEF::assembly::riscv::PseudoVNMSUB_VX_M1_MASK = 7517 , LIEF::assembly::riscv::PseudoVNMSUB_VX_M2 = 7518 , LIEF::assembly::riscv::PseudoVNMSUB_VX_M2_MASK = 7519 ,
  LIEF::assembly::riscv::PseudoVNMSUB_VX_M4 = 7520 , LIEF::assembly::riscv::PseudoVNMSUB_VX_M4_MASK = 7521 , LIEF::assembly::riscv::PseudoVNMSUB_VX_M8 = 7522 , LIEF::assembly::riscv::PseudoVNMSUB_VX_M8_MASK = 7523 ,
  LIEF::assembly::riscv::PseudoVNMSUB_VX_MF2 = 7524 , LIEF::assembly::riscv::PseudoVNMSUB_VX_MF2_MASK = 7525 , LIEF::assembly::riscv::PseudoVNMSUB_VX_MF4 = 7526 , LIEF::assembly::riscv::PseudoVNMSUB_VX_MF4_MASK = 7527 ,
  LIEF::assembly::riscv::PseudoVNMSUB_VX_MF8 = 7528 , LIEF::assembly::riscv::PseudoVNMSUB_VX_MF8_MASK = 7529 , LIEF::assembly::riscv::PseudoVNSRA_WI_M1 = 7530 , LIEF::assembly::riscv::PseudoVNSRA_WI_M1_MASK = 7531 ,
  LIEF::assembly::riscv::PseudoVNSRA_WI_M2 = 7532 , LIEF::assembly::riscv::PseudoVNSRA_WI_M2_MASK = 7533 , LIEF::assembly::riscv::PseudoVNSRA_WI_M4 = 7534 , LIEF::assembly::riscv::PseudoVNSRA_WI_M4_MASK = 7535 ,
  LIEF::assembly::riscv::PseudoVNSRA_WI_MF2 = 7536 , LIEF::assembly::riscv::PseudoVNSRA_WI_MF2_MASK = 7537 , LIEF::assembly::riscv::PseudoVNSRA_WI_MF4 = 7538 , LIEF::assembly::riscv::PseudoVNSRA_WI_MF4_MASK = 7539 ,
  LIEF::assembly::riscv::PseudoVNSRA_WI_MF8 = 7540 , LIEF::assembly::riscv::PseudoVNSRA_WI_MF8_MASK = 7541 , LIEF::assembly::riscv::PseudoVNSRA_WV_M1 = 7542 , LIEF::assembly::riscv::PseudoVNSRA_WV_M1_MASK = 7543 ,
  LIEF::assembly::riscv::PseudoVNSRA_WV_M2 = 7544 , LIEF::assembly::riscv::PseudoVNSRA_WV_M2_MASK = 7545 , LIEF::assembly::riscv::PseudoVNSRA_WV_M4 = 7546 , LIEF::assembly::riscv::PseudoVNSRA_WV_M4_MASK = 7547 ,
  LIEF::assembly::riscv::PseudoVNSRA_WV_MF2 = 7548 , LIEF::assembly::riscv::PseudoVNSRA_WV_MF2_MASK = 7549 , LIEF::assembly::riscv::PseudoVNSRA_WV_MF4 = 7550 , LIEF::assembly::riscv::PseudoVNSRA_WV_MF4_MASK = 7551 ,
  LIEF::assembly::riscv::PseudoVNSRA_WV_MF8 = 7552 , LIEF::assembly::riscv::PseudoVNSRA_WV_MF8_MASK = 7553 , LIEF::assembly::riscv::PseudoVNSRA_WX_M1 = 7554 , LIEF::assembly::riscv::PseudoVNSRA_WX_M1_MASK = 7555 ,
  LIEF::assembly::riscv::PseudoVNSRA_WX_M2 = 7556 , LIEF::assembly::riscv::PseudoVNSRA_WX_M2_MASK = 7557 , LIEF::assembly::riscv::PseudoVNSRA_WX_M4 = 7558 , LIEF::assembly::riscv::PseudoVNSRA_WX_M4_MASK = 7559 ,
  LIEF::assembly::riscv::PseudoVNSRA_WX_MF2 = 7560 , LIEF::assembly::riscv::PseudoVNSRA_WX_MF2_MASK = 7561 , LIEF::assembly::riscv::PseudoVNSRA_WX_MF4 = 7562 , LIEF::assembly::riscv::PseudoVNSRA_WX_MF4_MASK = 7563 ,
  LIEF::assembly::riscv::PseudoVNSRA_WX_MF8 = 7564 , LIEF::assembly::riscv::PseudoVNSRA_WX_MF8_MASK = 7565 , LIEF::assembly::riscv::PseudoVNSRL_WI_M1 = 7566 , LIEF::assembly::riscv::PseudoVNSRL_WI_M1_MASK = 7567 ,
  LIEF::assembly::riscv::PseudoVNSRL_WI_M2 = 7568 , LIEF::assembly::riscv::PseudoVNSRL_WI_M2_MASK = 7569 , LIEF::assembly::riscv::PseudoVNSRL_WI_M4 = 7570 , LIEF::assembly::riscv::PseudoVNSRL_WI_M4_MASK = 7571 ,
  LIEF::assembly::riscv::PseudoVNSRL_WI_MF2 = 7572 , LIEF::assembly::riscv::PseudoVNSRL_WI_MF2_MASK = 7573 , LIEF::assembly::riscv::PseudoVNSRL_WI_MF4 = 7574 , LIEF::assembly::riscv::PseudoVNSRL_WI_MF4_MASK = 7575 ,
  LIEF::assembly::riscv::PseudoVNSRL_WI_MF8 = 7576 , LIEF::assembly::riscv::PseudoVNSRL_WI_MF8_MASK = 7577 , LIEF::assembly::riscv::PseudoVNSRL_WV_M1 = 7578 , LIEF::assembly::riscv::PseudoVNSRL_WV_M1_MASK = 7579 ,
  LIEF::assembly::riscv::PseudoVNSRL_WV_M2 = 7580 , LIEF::assembly::riscv::PseudoVNSRL_WV_M2_MASK = 7581 , LIEF::assembly::riscv::PseudoVNSRL_WV_M4 = 7582 , LIEF::assembly::riscv::PseudoVNSRL_WV_M4_MASK = 7583 ,
  LIEF::assembly::riscv::PseudoVNSRL_WV_MF2 = 7584 , LIEF::assembly::riscv::PseudoVNSRL_WV_MF2_MASK = 7585 , LIEF::assembly::riscv::PseudoVNSRL_WV_MF4 = 7586 , LIEF::assembly::riscv::PseudoVNSRL_WV_MF4_MASK = 7587 ,
  LIEF::assembly::riscv::PseudoVNSRL_WV_MF8 = 7588 , LIEF::assembly::riscv::PseudoVNSRL_WV_MF8_MASK = 7589 , LIEF::assembly::riscv::PseudoVNSRL_WX_M1 = 7590 , LIEF::assembly::riscv::PseudoVNSRL_WX_M1_MASK = 7591 ,
  LIEF::assembly::riscv::PseudoVNSRL_WX_M2 = 7592 , LIEF::assembly::riscv::PseudoVNSRL_WX_M2_MASK = 7593 , LIEF::assembly::riscv::PseudoVNSRL_WX_M4 = 7594 , LIEF::assembly::riscv::PseudoVNSRL_WX_M4_MASK = 7595 ,
  LIEF::assembly::riscv::PseudoVNSRL_WX_MF2 = 7596 , LIEF::assembly::riscv::PseudoVNSRL_WX_MF2_MASK = 7597 , LIEF::assembly::riscv::PseudoVNSRL_WX_MF4 = 7598 , LIEF::assembly::riscv::PseudoVNSRL_WX_MF4_MASK = 7599 ,
  LIEF::assembly::riscv::PseudoVNSRL_WX_MF8 = 7600 , LIEF::assembly::riscv::PseudoVNSRL_WX_MF8_MASK = 7601 , LIEF::assembly::riscv::PseudoVOR_VI_M1 = 7602 , LIEF::assembly::riscv::PseudoVOR_VI_M1_MASK = 7603 ,
  LIEF::assembly::riscv::PseudoVOR_VI_M2 = 7604 , LIEF::assembly::riscv::PseudoVOR_VI_M2_MASK = 7605 , LIEF::assembly::riscv::PseudoVOR_VI_M4 = 7606 , LIEF::assembly::riscv::PseudoVOR_VI_M4_MASK = 7607 ,
  LIEF::assembly::riscv::PseudoVOR_VI_M8 = 7608 , LIEF::assembly::riscv::PseudoVOR_VI_M8_MASK = 7609 , LIEF::assembly::riscv::PseudoVOR_VI_MF2 = 7610 , LIEF::assembly::riscv::PseudoVOR_VI_MF2_MASK = 7611 ,
  LIEF::assembly::riscv::PseudoVOR_VI_MF4 = 7612 , LIEF::assembly::riscv::PseudoVOR_VI_MF4_MASK = 7613 , LIEF::assembly::riscv::PseudoVOR_VI_MF8 = 7614 , LIEF::assembly::riscv::PseudoVOR_VI_MF8_MASK = 7615 ,
  LIEF::assembly::riscv::PseudoVOR_VV_M1 = 7616 , LIEF::assembly::riscv::PseudoVOR_VV_M1_MASK = 7617 , LIEF::assembly::riscv::PseudoVOR_VV_M2 = 7618 , LIEF::assembly::riscv::PseudoVOR_VV_M2_MASK = 7619 ,
  LIEF::assembly::riscv::PseudoVOR_VV_M4 = 7620 , LIEF::assembly::riscv::PseudoVOR_VV_M4_MASK = 7621 , LIEF::assembly::riscv::PseudoVOR_VV_M8 = 7622 , LIEF::assembly::riscv::PseudoVOR_VV_M8_MASK = 7623 ,
  LIEF::assembly::riscv::PseudoVOR_VV_MF2 = 7624 , LIEF::assembly::riscv::PseudoVOR_VV_MF2_MASK = 7625 , LIEF::assembly::riscv::PseudoVOR_VV_MF4 = 7626 , LIEF::assembly::riscv::PseudoVOR_VV_MF4_MASK = 7627 ,
  LIEF::assembly::riscv::PseudoVOR_VV_MF8 = 7628 , LIEF::assembly::riscv::PseudoVOR_VV_MF8_MASK = 7629 , LIEF::assembly::riscv::PseudoVOR_VX_M1 = 7630 , LIEF::assembly::riscv::PseudoVOR_VX_M1_MASK = 7631 ,
  LIEF::assembly::riscv::PseudoVOR_VX_M2 = 7632 , LIEF::assembly::riscv::PseudoVOR_VX_M2_MASK = 7633 , LIEF::assembly::riscv::PseudoVOR_VX_M4 = 7634 , LIEF::assembly::riscv::PseudoVOR_VX_M4_MASK = 7635 ,
  LIEF::assembly::riscv::PseudoVOR_VX_M8 = 7636 , LIEF::assembly::riscv::PseudoVOR_VX_M8_MASK = 7637 , LIEF::assembly::riscv::PseudoVOR_VX_MF2 = 7638 , LIEF::assembly::riscv::PseudoVOR_VX_MF2_MASK = 7639 ,
  LIEF::assembly::riscv::PseudoVOR_VX_MF4 = 7640 , LIEF::assembly::riscv::PseudoVOR_VX_MF4_MASK = 7641 , LIEF::assembly::riscv::PseudoVOR_VX_MF8 = 7642 , LIEF::assembly::riscv::PseudoVOR_VX_MF8_MASK = 7643 ,
  LIEF::assembly::riscv::PseudoVQMACCSU_2x8x2_M1 = 7644 , LIEF::assembly::riscv::PseudoVQMACCSU_2x8x2_M2 = 7645 , LIEF::assembly::riscv::PseudoVQMACCSU_2x8x2_M4 = 7646 , LIEF::assembly::riscv::PseudoVQMACCSU_2x8x2_M8 = 7647 ,
  LIEF::assembly::riscv::PseudoVQMACCSU_4x8x4_M1 = 7648 , LIEF::assembly::riscv::PseudoVQMACCSU_4x8x4_M2 = 7649 , LIEF::assembly::riscv::PseudoVQMACCSU_4x8x4_M4 = 7650 , LIEF::assembly::riscv::PseudoVQMACCSU_4x8x4_MF2 = 7651 ,
  LIEF::assembly::riscv::PseudoVQMACCUS_2x8x2_M1 = 7652 , LIEF::assembly::riscv::PseudoVQMACCUS_2x8x2_M2 = 7653 , LIEF::assembly::riscv::PseudoVQMACCUS_2x8x2_M4 = 7654 , LIEF::assembly::riscv::PseudoVQMACCUS_2x8x2_M8 = 7655 ,
  LIEF::assembly::riscv::PseudoVQMACCUS_4x8x4_M1 = 7656 , LIEF::assembly::riscv::PseudoVQMACCUS_4x8x4_M2 = 7657 , LIEF::assembly::riscv::PseudoVQMACCUS_4x8x4_M4 = 7658 , LIEF::assembly::riscv::PseudoVQMACCUS_4x8x4_MF2 = 7659 ,
  LIEF::assembly::riscv::PseudoVQMACCU_2x8x2_M1 = 7660 , LIEF::assembly::riscv::PseudoVQMACCU_2x8x2_M2 = 7661 , LIEF::assembly::riscv::PseudoVQMACCU_2x8x2_M4 = 7662 , LIEF::assembly::riscv::PseudoVQMACCU_2x8x2_M8 = 7663 ,
  LIEF::assembly::riscv::PseudoVQMACCU_4x8x4_M1 = 7664 , LIEF::assembly::riscv::PseudoVQMACCU_4x8x4_M2 = 7665 , LIEF::assembly::riscv::PseudoVQMACCU_4x8x4_M4 = 7666 , LIEF::assembly::riscv::PseudoVQMACCU_4x8x4_MF2 = 7667 ,
  LIEF::assembly::riscv::PseudoVQMACC_2x8x2_M1 = 7668 , LIEF::assembly::riscv::PseudoVQMACC_2x8x2_M2 = 7669 , LIEF::assembly::riscv::PseudoVQMACC_2x8x2_M4 = 7670 , LIEF::assembly::riscv::PseudoVQMACC_2x8x2_M8 = 7671 ,
  LIEF::assembly::riscv::PseudoVQMACC_4x8x4_M1 = 7672 , LIEF::assembly::riscv::PseudoVQMACC_4x8x4_M2 = 7673 , LIEF::assembly::riscv::PseudoVQMACC_4x8x4_M4 = 7674 , LIEF::assembly::riscv::PseudoVQMACC_4x8x4_MF2 = 7675 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_M1_E16 = 7676 , LIEF::assembly::riscv::PseudoVREDAND_VS_M1_E16_MASK = 7677 , LIEF::assembly::riscv::PseudoVREDAND_VS_M1_E32 = 7678 , LIEF::assembly::riscv::PseudoVREDAND_VS_M1_E32_MASK = 7679 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_M1_E64 = 7680 , LIEF::assembly::riscv::PseudoVREDAND_VS_M1_E64_MASK = 7681 , LIEF::assembly::riscv::PseudoVREDAND_VS_M1_E8 = 7682 , LIEF::assembly::riscv::PseudoVREDAND_VS_M1_E8_MASK = 7683 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_M2_E16 = 7684 , LIEF::assembly::riscv::PseudoVREDAND_VS_M2_E16_MASK = 7685 , LIEF::assembly::riscv::PseudoVREDAND_VS_M2_E32 = 7686 , LIEF::assembly::riscv::PseudoVREDAND_VS_M2_E32_MASK = 7687 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_M2_E64 = 7688 , LIEF::assembly::riscv::PseudoVREDAND_VS_M2_E64_MASK = 7689 , LIEF::assembly::riscv::PseudoVREDAND_VS_M2_E8 = 7690 , LIEF::assembly::riscv::PseudoVREDAND_VS_M2_E8_MASK = 7691 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_M4_E16 = 7692 , LIEF::assembly::riscv::PseudoVREDAND_VS_M4_E16_MASK = 7693 , LIEF::assembly::riscv::PseudoVREDAND_VS_M4_E32 = 7694 , LIEF::assembly::riscv::PseudoVREDAND_VS_M4_E32_MASK = 7695 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_M4_E64 = 7696 , LIEF::assembly::riscv::PseudoVREDAND_VS_M4_E64_MASK = 7697 , LIEF::assembly::riscv::PseudoVREDAND_VS_M4_E8 = 7698 , LIEF::assembly::riscv::PseudoVREDAND_VS_M4_E8_MASK = 7699 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_M8_E16 = 7700 , LIEF::assembly::riscv::PseudoVREDAND_VS_M8_E16_MASK = 7701 , LIEF::assembly::riscv::PseudoVREDAND_VS_M8_E32 = 7702 , LIEF::assembly::riscv::PseudoVREDAND_VS_M8_E32_MASK = 7703 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_M8_E64 = 7704 , LIEF::assembly::riscv::PseudoVREDAND_VS_M8_E64_MASK = 7705 , LIEF::assembly::riscv::PseudoVREDAND_VS_M8_E8 = 7706 , LIEF::assembly::riscv::PseudoVREDAND_VS_M8_E8_MASK = 7707 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_MF2_E16 = 7708 , LIEF::assembly::riscv::PseudoVREDAND_VS_MF2_E16_MASK = 7709 , LIEF::assembly::riscv::PseudoVREDAND_VS_MF2_E32 = 7710 , LIEF::assembly::riscv::PseudoVREDAND_VS_MF2_E32_MASK = 7711 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_MF2_E8 = 7712 , LIEF::assembly::riscv::PseudoVREDAND_VS_MF2_E8_MASK = 7713 , LIEF::assembly::riscv::PseudoVREDAND_VS_MF4_E16 = 7714 , LIEF::assembly::riscv::PseudoVREDAND_VS_MF4_E16_MASK = 7715 ,
  LIEF::assembly::riscv::PseudoVREDAND_VS_MF4_E8 = 7716 , LIEF::assembly::riscv::PseudoVREDAND_VS_MF4_E8_MASK = 7717 , LIEF::assembly::riscv::PseudoVREDAND_VS_MF8_E8 = 7718 , LIEF::assembly::riscv::PseudoVREDAND_VS_MF8_E8_MASK = 7719 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_M1_E16 = 7720 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M1_E16_MASK = 7721 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M1_E32 = 7722 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M1_E32_MASK = 7723 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_M1_E64 = 7724 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M1_E64_MASK = 7725 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M1_E8 = 7726 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M1_E8_MASK = 7727 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_M2_E16 = 7728 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M2_E16_MASK = 7729 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M2_E32 = 7730 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M2_E32_MASK = 7731 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_M2_E64 = 7732 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M2_E64_MASK = 7733 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M2_E8 = 7734 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M2_E8_MASK = 7735 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_M4_E16 = 7736 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M4_E16_MASK = 7737 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M4_E32 = 7738 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M4_E32_MASK = 7739 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_M4_E64 = 7740 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M4_E64_MASK = 7741 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M4_E8 = 7742 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M4_E8_MASK = 7743 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_M8_E16 = 7744 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M8_E16_MASK = 7745 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M8_E32 = 7746 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M8_E32_MASK = 7747 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_M8_E64 = 7748 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M8_E64_MASK = 7749 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M8_E8 = 7750 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_M8_E8_MASK = 7751 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF2_E16 = 7752 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF2_E16_MASK = 7753 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF2_E32 = 7754 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF2_E32_MASK = 7755 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF2_E8 = 7756 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF2_E8_MASK = 7757 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF4_E16 = 7758 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF4_E16_MASK = 7759 ,
  LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF4_E8 = 7760 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF4_E8_MASK = 7761 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF8_E8 = 7762 , LIEF::assembly::riscv::PseudoVREDMAXU_VS_MF8_E8_MASK = 7763 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_M1_E16 = 7764 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M1_E16_MASK = 7765 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M1_E32 = 7766 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M1_E32_MASK = 7767 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_M1_E64 = 7768 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M1_E64_MASK = 7769 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M1_E8 = 7770 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M1_E8_MASK = 7771 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_M2_E16 = 7772 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M2_E16_MASK = 7773 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M2_E32 = 7774 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M2_E32_MASK = 7775 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_M2_E64 = 7776 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M2_E64_MASK = 7777 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M2_E8 = 7778 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M2_E8_MASK = 7779 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_M4_E16 = 7780 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M4_E16_MASK = 7781 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M4_E32 = 7782 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M4_E32_MASK = 7783 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_M4_E64 = 7784 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M4_E64_MASK = 7785 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M4_E8 = 7786 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M4_E8_MASK = 7787 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_M8_E16 = 7788 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M8_E16_MASK = 7789 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M8_E32 = 7790 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M8_E32_MASK = 7791 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_M8_E64 = 7792 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M8_E64_MASK = 7793 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M8_E8 = 7794 , LIEF::assembly::riscv::PseudoVREDMAX_VS_M8_E8_MASK = 7795 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_MF2_E16 = 7796 , LIEF::assembly::riscv::PseudoVREDMAX_VS_MF2_E16_MASK = 7797 , LIEF::assembly::riscv::PseudoVREDMAX_VS_MF2_E32 = 7798 , LIEF::assembly::riscv::PseudoVREDMAX_VS_MF2_E32_MASK = 7799 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_MF2_E8 = 7800 , LIEF::assembly::riscv::PseudoVREDMAX_VS_MF2_E8_MASK = 7801 , LIEF::assembly::riscv::PseudoVREDMAX_VS_MF4_E16 = 7802 , LIEF::assembly::riscv::PseudoVREDMAX_VS_MF4_E16_MASK = 7803 ,
  LIEF::assembly::riscv::PseudoVREDMAX_VS_MF4_E8 = 7804 , LIEF::assembly::riscv::PseudoVREDMAX_VS_MF4_E8_MASK = 7805 , LIEF::assembly::riscv::PseudoVREDMAX_VS_MF8_E8 = 7806 , LIEF::assembly::riscv::PseudoVREDMAX_VS_MF8_E8_MASK = 7807 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_M1_E16 = 7808 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M1_E16_MASK = 7809 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M1_E32 = 7810 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M1_E32_MASK = 7811 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_M1_E64 = 7812 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M1_E64_MASK = 7813 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M1_E8 = 7814 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M1_E8_MASK = 7815 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_M2_E16 = 7816 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M2_E16_MASK = 7817 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M2_E32 = 7818 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M2_E32_MASK = 7819 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_M2_E64 = 7820 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M2_E64_MASK = 7821 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M2_E8 = 7822 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M2_E8_MASK = 7823 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_M4_E16 = 7824 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M4_E16_MASK = 7825 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M4_E32 = 7826 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M4_E32_MASK = 7827 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_M4_E64 = 7828 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M4_E64_MASK = 7829 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M4_E8 = 7830 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M4_E8_MASK = 7831 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_M8_E16 = 7832 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M8_E16_MASK = 7833 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M8_E32 = 7834 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M8_E32_MASK = 7835 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_M8_E64 = 7836 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M8_E64_MASK = 7837 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M8_E8 = 7838 , LIEF::assembly::riscv::PseudoVREDMINU_VS_M8_E8_MASK = 7839 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_MF2_E16 = 7840 , LIEF::assembly::riscv::PseudoVREDMINU_VS_MF2_E16_MASK = 7841 , LIEF::assembly::riscv::PseudoVREDMINU_VS_MF2_E32 = 7842 , LIEF::assembly::riscv::PseudoVREDMINU_VS_MF2_E32_MASK = 7843 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_MF2_E8 = 7844 , LIEF::assembly::riscv::PseudoVREDMINU_VS_MF2_E8_MASK = 7845 , LIEF::assembly::riscv::PseudoVREDMINU_VS_MF4_E16 = 7846 , LIEF::assembly::riscv::PseudoVREDMINU_VS_MF4_E16_MASK = 7847 ,
  LIEF::assembly::riscv::PseudoVREDMINU_VS_MF4_E8 = 7848 , LIEF::assembly::riscv::PseudoVREDMINU_VS_MF4_E8_MASK = 7849 , LIEF::assembly::riscv::PseudoVREDMINU_VS_MF8_E8 = 7850 , LIEF::assembly::riscv::PseudoVREDMINU_VS_MF8_E8_MASK = 7851 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_M1_E16 = 7852 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M1_E16_MASK = 7853 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M1_E32 = 7854 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M1_E32_MASK = 7855 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_M1_E64 = 7856 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M1_E64_MASK = 7857 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M1_E8 = 7858 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M1_E8_MASK = 7859 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_M2_E16 = 7860 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M2_E16_MASK = 7861 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M2_E32 = 7862 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M2_E32_MASK = 7863 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_M2_E64 = 7864 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M2_E64_MASK = 7865 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M2_E8 = 7866 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M2_E8_MASK = 7867 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_M4_E16 = 7868 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M4_E16_MASK = 7869 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M4_E32 = 7870 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M4_E32_MASK = 7871 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_M4_E64 = 7872 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M4_E64_MASK = 7873 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M4_E8 = 7874 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M4_E8_MASK = 7875 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_M8_E16 = 7876 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M8_E16_MASK = 7877 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M8_E32 = 7878 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M8_E32_MASK = 7879 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_M8_E64 = 7880 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M8_E64_MASK = 7881 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M8_E8 = 7882 , LIEF::assembly::riscv::PseudoVREDMIN_VS_M8_E8_MASK = 7883 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_MF2_E16 = 7884 , LIEF::assembly::riscv::PseudoVREDMIN_VS_MF2_E16_MASK = 7885 , LIEF::assembly::riscv::PseudoVREDMIN_VS_MF2_E32 = 7886 , LIEF::assembly::riscv::PseudoVREDMIN_VS_MF2_E32_MASK = 7887 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_MF2_E8 = 7888 , LIEF::assembly::riscv::PseudoVREDMIN_VS_MF2_E8_MASK = 7889 , LIEF::assembly::riscv::PseudoVREDMIN_VS_MF4_E16 = 7890 , LIEF::assembly::riscv::PseudoVREDMIN_VS_MF4_E16_MASK = 7891 ,
  LIEF::assembly::riscv::PseudoVREDMIN_VS_MF4_E8 = 7892 , LIEF::assembly::riscv::PseudoVREDMIN_VS_MF4_E8_MASK = 7893 , LIEF::assembly::riscv::PseudoVREDMIN_VS_MF8_E8 = 7894 , LIEF::assembly::riscv::PseudoVREDMIN_VS_MF8_E8_MASK = 7895 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_M1_E16 = 7896 , LIEF::assembly::riscv::PseudoVREDOR_VS_M1_E16_MASK = 7897 , LIEF::assembly::riscv::PseudoVREDOR_VS_M1_E32 = 7898 , LIEF::assembly::riscv::PseudoVREDOR_VS_M1_E32_MASK = 7899 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_M1_E64 = 7900 , LIEF::assembly::riscv::PseudoVREDOR_VS_M1_E64_MASK = 7901 , LIEF::assembly::riscv::PseudoVREDOR_VS_M1_E8 = 7902 , LIEF::assembly::riscv::PseudoVREDOR_VS_M1_E8_MASK = 7903 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_M2_E16 = 7904 , LIEF::assembly::riscv::PseudoVREDOR_VS_M2_E16_MASK = 7905 , LIEF::assembly::riscv::PseudoVREDOR_VS_M2_E32 = 7906 , LIEF::assembly::riscv::PseudoVREDOR_VS_M2_E32_MASK = 7907 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_M2_E64 = 7908 , LIEF::assembly::riscv::PseudoVREDOR_VS_M2_E64_MASK = 7909 , LIEF::assembly::riscv::PseudoVREDOR_VS_M2_E8 = 7910 , LIEF::assembly::riscv::PseudoVREDOR_VS_M2_E8_MASK = 7911 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_M4_E16 = 7912 , LIEF::assembly::riscv::PseudoVREDOR_VS_M4_E16_MASK = 7913 , LIEF::assembly::riscv::PseudoVREDOR_VS_M4_E32 = 7914 , LIEF::assembly::riscv::PseudoVREDOR_VS_M4_E32_MASK = 7915 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_M4_E64 = 7916 , LIEF::assembly::riscv::PseudoVREDOR_VS_M4_E64_MASK = 7917 , LIEF::assembly::riscv::PseudoVREDOR_VS_M4_E8 = 7918 , LIEF::assembly::riscv::PseudoVREDOR_VS_M4_E8_MASK = 7919 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_M8_E16 = 7920 , LIEF::assembly::riscv::PseudoVREDOR_VS_M8_E16_MASK = 7921 , LIEF::assembly::riscv::PseudoVREDOR_VS_M8_E32 = 7922 , LIEF::assembly::riscv::PseudoVREDOR_VS_M8_E32_MASK = 7923 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_M8_E64 = 7924 , LIEF::assembly::riscv::PseudoVREDOR_VS_M8_E64_MASK = 7925 , LIEF::assembly::riscv::PseudoVREDOR_VS_M8_E8 = 7926 , LIEF::assembly::riscv::PseudoVREDOR_VS_M8_E8_MASK = 7927 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_MF2_E16 = 7928 , LIEF::assembly::riscv::PseudoVREDOR_VS_MF2_E16_MASK = 7929 , LIEF::assembly::riscv::PseudoVREDOR_VS_MF2_E32 = 7930 , LIEF::assembly::riscv::PseudoVREDOR_VS_MF2_E32_MASK = 7931 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_MF2_E8 = 7932 , LIEF::assembly::riscv::PseudoVREDOR_VS_MF2_E8_MASK = 7933 , LIEF::assembly::riscv::PseudoVREDOR_VS_MF4_E16 = 7934 , LIEF::assembly::riscv::PseudoVREDOR_VS_MF4_E16_MASK = 7935 ,
  LIEF::assembly::riscv::PseudoVREDOR_VS_MF4_E8 = 7936 , LIEF::assembly::riscv::PseudoVREDOR_VS_MF4_E8_MASK = 7937 , LIEF::assembly::riscv::PseudoVREDOR_VS_MF8_E8 = 7938 , LIEF::assembly::riscv::PseudoVREDOR_VS_MF8_E8_MASK = 7939 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_M1_E16 = 7940 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M1_E16_MASK = 7941 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M1_E32 = 7942 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M1_E32_MASK = 7943 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_M1_E64 = 7944 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M1_E64_MASK = 7945 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M1_E8 = 7946 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M1_E8_MASK = 7947 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_M2_E16 = 7948 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M2_E16_MASK = 7949 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M2_E32 = 7950 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M2_E32_MASK = 7951 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_M2_E64 = 7952 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M2_E64_MASK = 7953 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M2_E8 = 7954 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M2_E8_MASK = 7955 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_M4_E16 = 7956 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M4_E16_MASK = 7957 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M4_E32 = 7958 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M4_E32_MASK = 7959 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_M4_E64 = 7960 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M4_E64_MASK = 7961 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M4_E8 = 7962 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M4_E8_MASK = 7963 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_M8_E16 = 7964 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M8_E16_MASK = 7965 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M8_E32 = 7966 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M8_E32_MASK = 7967 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_M8_E64 = 7968 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M8_E64_MASK = 7969 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M8_E8 = 7970 , LIEF::assembly::riscv::PseudoVREDSUM_VS_M8_E8_MASK = 7971 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_MF2_E16 = 7972 , LIEF::assembly::riscv::PseudoVREDSUM_VS_MF2_E16_MASK = 7973 , LIEF::assembly::riscv::PseudoVREDSUM_VS_MF2_E32 = 7974 , LIEF::assembly::riscv::PseudoVREDSUM_VS_MF2_E32_MASK = 7975 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_MF2_E8 = 7976 , LIEF::assembly::riscv::PseudoVREDSUM_VS_MF2_E8_MASK = 7977 , LIEF::assembly::riscv::PseudoVREDSUM_VS_MF4_E16 = 7978 , LIEF::assembly::riscv::PseudoVREDSUM_VS_MF4_E16_MASK = 7979 ,
  LIEF::assembly::riscv::PseudoVREDSUM_VS_MF4_E8 = 7980 , LIEF::assembly::riscv::PseudoVREDSUM_VS_MF4_E8_MASK = 7981 , LIEF::assembly::riscv::PseudoVREDSUM_VS_MF8_E8 = 7982 , LIEF::assembly::riscv::PseudoVREDSUM_VS_MF8_E8_MASK = 7983 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_M1_E16 = 7984 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M1_E16_MASK = 7985 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M1_E32 = 7986 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M1_E32_MASK = 7987 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_M1_E64 = 7988 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M1_E64_MASK = 7989 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M1_E8 = 7990 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M1_E8_MASK = 7991 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_M2_E16 = 7992 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M2_E16_MASK = 7993 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M2_E32 = 7994 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M2_E32_MASK = 7995 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_M2_E64 = 7996 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M2_E64_MASK = 7997 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M2_E8 = 7998 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M2_E8_MASK = 7999 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_M4_E16 = 8000 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M4_E16_MASK = 8001 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M4_E32 = 8002 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M4_E32_MASK = 8003 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_M4_E64 = 8004 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M4_E64_MASK = 8005 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M4_E8 = 8006 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M4_E8_MASK = 8007 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_M8_E16 = 8008 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M8_E16_MASK = 8009 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M8_E32 = 8010 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M8_E32_MASK = 8011 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_M8_E64 = 8012 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M8_E64_MASK = 8013 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M8_E8 = 8014 , LIEF::assembly::riscv::PseudoVREDXOR_VS_M8_E8_MASK = 8015 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_MF2_E16 = 8016 , LIEF::assembly::riscv::PseudoVREDXOR_VS_MF2_E16_MASK = 8017 , LIEF::assembly::riscv::PseudoVREDXOR_VS_MF2_E32 = 8018 , LIEF::assembly::riscv::PseudoVREDXOR_VS_MF2_E32_MASK = 8019 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_MF2_E8 = 8020 , LIEF::assembly::riscv::PseudoVREDXOR_VS_MF2_E8_MASK = 8021 , LIEF::assembly::riscv::PseudoVREDXOR_VS_MF4_E16 = 8022 , LIEF::assembly::riscv::PseudoVREDXOR_VS_MF4_E16_MASK = 8023 ,
  LIEF::assembly::riscv::PseudoVREDXOR_VS_MF4_E8 = 8024 , LIEF::assembly::riscv::PseudoVREDXOR_VS_MF4_E8_MASK = 8025 , LIEF::assembly::riscv::PseudoVREDXOR_VS_MF8_E8 = 8026 , LIEF::assembly::riscv::PseudoVREDXOR_VS_MF8_E8_MASK = 8027 ,
  LIEF::assembly::riscv::PseudoVRELOAD2_M1 = 8028 , LIEF::assembly::riscv::PseudoVRELOAD2_M2 = 8029 , LIEF::assembly::riscv::PseudoVRELOAD2_M4 = 8030 , LIEF::assembly::riscv::PseudoVRELOAD2_MF2 = 8031 ,
  LIEF::assembly::riscv::PseudoVRELOAD2_MF4 = 8032 , LIEF::assembly::riscv::PseudoVRELOAD2_MF8 = 8033 , LIEF::assembly::riscv::PseudoVRELOAD3_M1 = 8034 , LIEF::assembly::riscv::PseudoVRELOAD3_M2 = 8035 ,
  LIEF::assembly::riscv::PseudoVRELOAD3_MF2 = 8036 , LIEF::assembly::riscv::PseudoVRELOAD3_MF4 = 8037 , LIEF::assembly::riscv::PseudoVRELOAD3_MF8 = 8038 , LIEF::assembly::riscv::PseudoVRELOAD4_M1 = 8039 ,
  LIEF::assembly::riscv::PseudoVRELOAD4_M2 = 8040 , LIEF::assembly::riscv::PseudoVRELOAD4_MF2 = 8041 , LIEF::assembly::riscv::PseudoVRELOAD4_MF4 = 8042 , LIEF::assembly::riscv::PseudoVRELOAD4_MF8 = 8043 ,
  LIEF::assembly::riscv::PseudoVRELOAD5_M1 = 8044 , LIEF::assembly::riscv::PseudoVRELOAD5_MF2 = 8045 , LIEF::assembly::riscv::PseudoVRELOAD5_MF4 = 8046 , LIEF::assembly::riscv::PseudoVRELOAD5_MF8 = 8047 ,
  LIEF::assembly::riscv::PseudoVRELOAD6_M1 = 8048 , LIEF::assembly::riscv::PseudoVRELOAD6_MF2 = 8049 , LIEF::assembly::riscv::PseudoVRELOAD6_MF4 = 8050 , LIEF::assembly::riscv::PseudoVRELOAD6_MF8 = 8051 ,
  LIEF::assembly::riscv::PseudoVRELOAD7_M1 = 8052 , LIEF::assembly::riscv::PseudoVRELOAD7_MF2 = 8053 , LIEF::assembly::riscv::PseudoVRELOAD7_MF4 = 8054 , LIEF::assembly::riscv::PseudoVRELOAD7_MF8 = 8055 ,
  LIEF::assembly::riscv::PseudoVRELOAD8_M1 = 8056 , LIEF::assembly::riscv::PseudoVRELOAD8_MF2 = 8057 , LIEF::assembly::riscv::PseudoVRELOAD8_MF4 = 8058 , LIEF::assembly::riscv::PseudoVRELOAD8_MF8 = 8059 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_M1_E16 = 8060 , LIEF::assembly::riscv::PseudoVREMU_VV_M1_E16_MASK = 8061 , LIEF::assembly::riscv::PseudoVREMU_VV_M1_E32 = 8062 , LIEF::assembly::riscv::PseudoVREMU_VV_M1_E32_MASK = 8063 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_M1_E64 = 8064 , LIEF::assembly::riscv::PseudoVREMU_VV_M1_E64_MASK = 8065 , LIEF::assembly::riscv::PseudoVREMU_VV_M1_E8 = 8066 , LIEF::assembly::riscv::PseudoVREMU_VV_M1_E8_MASK = 8067 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_M2_E16 = 8068 , LIEF::assembly::riscv::PseudoVREMU_VV_M2_E16_MASK = 8069 , LIEF::assembly::riscv::PseudoVREMU_VV_M2_E32 = 8070 , LIEF::assembly::riscv::PseudoVREMU_VV_M2_E32_MASK = 8071 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_M2_E64 = 8072 , LIEF::assembly::riscv::PseudoVREMU_VV_M2_E64_MASK = 8073 , LIEF::assembly::riscv::PseudoVREMU_VV_M2_E8 = 8074 , LIEF::assembly::riscv::PseudoVREMU_VV_M2_E8_MASK = 8075 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_M4_E16 = 8076 , LIEF::assembly::riscv::PseudoVREMU_VV_M4_E16_MASK = 8077 , LIEF::assembly::riscv::PseudoVREMU_VV_M4_E32 = 8078 , LIEF::assembly::riscv::PseudoVREMU_VV_M4_E32_MASK = 8079 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_M4_E64 = 8080 , LIEF::assembly::riscv::PseudoVREMU_VV_M4_E64_MASK = 8081 , LIEF::assembly::riscv::PseudoVREMU_VV_M4_E8 = 8082 , LIEF::assembly::riscv::PseudoVREMU_VV_M4_E8_MASK = 8083 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_M8_E16 = 8084 , LIEF::assembly::riscv::PseudoVREMU_VV_M8_E16_MASK = 8085 , LIEF::assembly::riscv::PseudoVREMU_VV_M8_E32 = 8086 , LIEF::assembly::riscv::PseudoVREMU_VV_M8_E32_MASK = 8087 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_M8_E64 = 8088 , LIEF::assembly::riscv::PseudoVREMU_VV_M8_E64_MASK = 8089 , LIEF::assembly::riscv::PseudoVREMU_VV_M8_E8 = 8090 , LIEF::assembly::riscv::PseudoVREMU_VV_M8_E8_MASK = 8091 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_MF2_E16 = 8092 , LIEF::assembly::riscv::PseudoVREMU_VV_MF2_E16_MASK = 8093 , LIEF::assembly::riscv::PseudoVREMU_VV_MF2_E32 = 8094 , LIEF::assembly::riscv::PseudoVREMU_VV_MF2_E32_MASK = 8095 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_MF2_E8 = 8096 , LIEF::assembly::riscv::PseudoVREMU_VV_MF2_E8_MASK = 8097 , LIEF::assembly::riscv::PseudoVREMU_VV_MF4_E16 = 8098 , LIEF::assembly::riscv::PseudoVREMU_VV_MF4_E16_MASK = 8099 ,
  LIEF::assembly::riscv::PseudoVREMU_VV_MF4_E8 = 8100 , LIEF::assembly::riscv::PseudoVREMU_VV_MF4_E8_MASK = 8101 , LIEF::assembly::riscv::PseudoVREMU_VV_MF8_E8 = 8102 , LIEF::assembly::riscv::PseudoVREMU_VV_MF8_E8_MASK = 8103 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_M1_E16 = 8104 , LIEF::assembly::riscv::PseudoVREMU_VX_M1_E16_MASK = 8105 , LIEF::assembly::riscv::PseudoVREMU_VX_M1_E32 = 8106 , LIEF::assembly::riscv::PseudoVREMU_VX_M1_E32_MASK = 8107 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_M1_E64 = 8108 , LIEF::assembly::riscv::PseudoVREMU_VX_M1_E64_MASK = 8109 , LIEF::assembly::riscv::PseudoVREMU_VX_M1_E8 = 8110 , LIEF::assembly::riscv::PseudoVREMU_VX_M1_E8_MASK = 8111 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_M2_E16 = 8112 , LIEF::assembly::riscv::PseudoVREMU_VX_M2_E16_MASK = 8113 , LIEF::assembly::riscv::PseudoVREMU_VX_M2_E32 = 8114 , LIEF::assembly::riscv::PseudoVREMU_VX_M2_E32_MASK = 8115 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_M2_E64 = 8116 , LIEF::assembly::riscv::PseudoVREMU_VX_M2_E64_MASK = 8117 , LIEF::assembly::riscv::PseudoVREMU_VX_M2_E8 = 8118 , LIEF::assembly::riscv::PseudoVREMU_VX_M2_E8_MASK = 8119 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_M4_E16 = 8120 , LIEF::assembly::riscv::PseudoVREMU_VX_M4_E16_MASK = 8121 , LIEF::assembly::riscv::PseudoVREMU_VX_M4_E32 = 8122 , LIEF::assembly::riscv::PseudoVREMU_VX_M4_E32_MASK = 8123 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_M4_E64 = 8124 , LIEF::assembly::riscv::PseudoVREMU_VX_M4_E64_MASK = 8125 , LIEF::assembly::riscv::PseudoVREMU_VX_M4_E8 = 8126 , LIEF::assembly::riscv::PseudoVREMU_VX_M4_E8_MASK = 8127 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_M8_E16 = 8128 , LIEF::assembly::riscv::PseudoVREMU_VX_M8_E16_MASK = 8129 , LIEF::assembly::riscv::PseudoVREMU_VX_M8_E32 = 8130 , LIEF::assembly::riscv::PseudoVREMU_VX_M8_E32_MASK = 8131 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_M8_E64 = 8132 , LIEF::assembly::riscv::PseudoVREMU_VX_M8_E64_MASK = 8133 , LIEF::assembly::riscv::PseudoVREMU_VX_M8_E8 = 8134 , LIEF::assembly::riscv::PseudoVREMU_VX_M8_E8_MASK = 8135 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_MF2_E16 = 8136 , LIEF::assembly::riscv::PseudoVREMU_VX_MF2_E16_MASK = 8137 , LIEF::assembly::riscv::PseudoVREMU_VX_MF2_E32 = 8138 , LIEF::assembly::riscv::PseudoVREMU_VX_MF2_E32_MASK = 8139 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_MF2_E8 = 8140 , LIEF::assembly::riscv::PseudoVREMU_VX_MF2_E8_MASK = 8141 , LIEF::assembly::riscv::PseudoVREMU_VX_MF4_E16 = 8142 , LIEF::assembly::riscv::PseudoVREMU_VX_MF4_E16_MASK = 8143 ,
  LIEF::assembly::riscv::PseudoVREMU_VX_MF4_E8 = 8144 , LIEF::assembly::riscv::PseudoVREMU_VX_MF4_E8_MASK = 8145 , LIEF::assembly::riscv::PseudoVREMU_VX_MF8_E8 = 8146 , LIEF::assembly::riscv::PseudoVREMU_VX_MF8_E8_MASK = 8147 ,
  LIEF::assembly::riscv::PseudoVREM_VV_M1_E16 = 8148 , LIEF::assembly::riscv::PseudoVREM_VV_M1_E16_MASK = 8149 , LIEF::assembly::riscv::PseudoVREM_VV_M1_E32 = 8150 , LIEF::assembly::riscv::PseudoVREM_VV_M1_E32_MASK = 8151 ,
  LIEF::assembly::riscv::PseudoVREM_VV_M1_E64 = 8152 , LIEF::assembly::riscv::PseudoVREM_VV_M1_E64_MASK = 8153 , LIEF::assembly::riscv::PseudoVREM_VV_M1_E8 = 8154 , LIEF::assembly::riscv::PseudoVREM_VV_M1_E8_MASK = 8155 ,
  LIEF::assembly::riscv::PseudoVREM_VV_M2_E16 = 8156 , LIEF::assembly::riscv::PseudoVREM_VV_M2_E16_MASK = 8157 , LIEF::assembly::riscv::PseudoVREM_VV_M2_E32 = 8158 , LIEF::assembly::riscv::PseudoVREM_VV_M2_E32_MASK = 8159 ,
  LIEF::assembly::riscv::PseudoVREM_VV_M2_E64 = 8160 , LIEF::assembly::riscv::PseudoVREM_VV_M2_E64_MASK = 8161 , LIEF::assembly::riscv::PseudoVREM_VV_M2_E8 = 8162 , LIEF::assembly::riscv::PseudoVREM_VV_M2_E8_MASK = 8163 ,
  LIEF::assembly::riscv::PseudoVREM_VV_M4_E16 = 8164 , LIEF::assembly::riscv::PseudoVREM_VV_M4_E16_MASK = 8165 , LIEF::assembly::riscv::PseudoVREM_VV_M4_E32 = 8166 , LIEF::assembly::riscv::PseudoVREM_VV_M4_E32_MASK = 8167 ,
  LIEF::assembly::riscv::PseudoVREM_VV_M4_E64 = 8168 , LIEF::assembly::riscv::PseudoVREM_VV_M4_E64_MASK = 8169 , LIEF::assembly::riscv::PseudoVREM_VV_M4_E8 = 8170 , LIEF::assembly::riscv::PseudoVREM_VV_M4_E8_MASK = 8171 ,
  LIEF::assembly::riscv::PseudoVREM_VV_M8_E16 = 8172 , LIEF::assembly::riscv::PseudoVREM_VV_M8_E16_MASK = 8173 , LIEF::assembly::riscv::PseudoVREM_VV_M8_E32 = 8174 , LIEF::assembly::riscv::PseudoVREM_VV_M8_E32_MASK = 8175 ,
  LIEF::assembly::riscv::PseudoVREM_VV_M8_E64 = 8176 , LIEF::assembly::riscv::PseudoVREM_VV_M8_E64_MASK = 8177 , LIEF::assembly::riscv::PseudoVREM_VV_M8_E8 = 8178 , LIEF::assembly::riscv::PseudoVREM_VV_M8_E8_MASK = 8179 ,
  LIEF::assembly::riscv::PseudoVREM_VV_MF2_E16 = 8180 , LIEF::assembly::riscv::PseudoVREM_VV_MF2_E16_MASK = 8181 , LIEF::assembly::riscv::PseudoVREM_VV_MF2_E32 = 8182 , LIEF::assembly::riscv::PseudoVREM_VV_MF2_E32_MASK = 8183 ,
  LIEF::assembly::riscv::PseudoVREM_VV_MF2_E8 = 8184 , LIEF::assembly::riscv::PseudoVREM_VV_MF2_E8_MASK = 8185 , LIEF::assembly::riscv::PseudoVREM_VV_MF4_E16 = 8186 , LIEF::assembly::riscv::PseudoVREM_VV_MF4_E16_MASK = 8187 ,
  LIEF::assembly::riscv::PseudoVREM_VV_MF4_E8 = 8188 , LIEF::assembly::riscv::PseudoVREM_VV_MF4_E8_MASK = 8189 , LIEF::assembly::riscv::PseudoVREM_VV_MF8_E8 = 8190 , LIEF::assembly::riscv::PseudoVREM_VV_MF8_E8_MASK = 8191 ,
  LIEF::assembly::riscv::PseudoVREM_VX_M1_E16 = 8192 , LIEF::assembly::riscv::PseudoVREM_VX_M1_E16_MASK = 8193 , LIEF::assembly::riscv::PseudoVREM_VX_M1_E32 = 8194 , LIEF::assembly::riscv::PseudoVREM_VX_M1_E32_MASK = 8195 ,
  LIEF::assembly::riscv::PseudoVREM_VX_M1_E64 = 8196 , LIEF::assembly::riscv::PseudoVREM_VX_M1_E64_MASK = 8197 , LIEF::assembly::riscv::PseudoVREM_VX_M1_E8 = 8198 , LIEF::assembly::riscv::PseudoVREM_VX_M1_E8_MASK = 8199 ,
  LIEF::assembly::riscv::PseudoVREM_VX_M2_E16 = 8200 , LIEF::assembly::riscv::PseudoVREM_VX_M2_E16_MASK = 8201 , LIEF::assembly::riscv::PseudoVREM_VX_M2_E32 = 8202 , LIEF::assembly::riscv::PseudoVREM_VX_M2_E32_MASK = 8203 ,
  LIEF::assembly::riscv::PseudoVREM_VX_M2_E64 = 8204 , LIEF::assembly::riscv::PseudoVREM_VX_M2_E64_MASK = 8205 , LIEF::assembly::riscv::PseudoVREM_VX_M2_E8 = 8206 , LIEF::assembly::riscv::PseudoVREM_VX_M2_E8_MASK = 8207 ,
  LIEF::assembly::riscv::PseudoVREM_VX_M4_E16 = 8208 , LIEF::assembly::riscv::PseudoVREM_VX_M4_E16_MASK = 8209 , LIEF::assembly::riscv::PseudoVREM_VX_M4_E32 = 8210 , LIEF::assembly::riscv::PseudoVREM_VX_M4_E32_MASK = 8211 ,
  LIEF::assembly::riscv::PseudoVREM_VX_M4_E64 = 8212 , LIEF::assembly::riscv::PseudoVREM_VX_M4_E64_MASK = 8213 , LIEF::assembly::riscv::PseudoVREM_VX_M4_E8 = 8214 , LIEF::assembly::riscv::PseudoVREM_VX_M4_E8_MASK = 8215 ,
  LIEF::assembly::riscv::PseudoVREM_VX_M8_E16 = 8216 , LIEF::assembly::riscv::PseudoVREM_VX_M8_E16_MASK = 8217 , LIEF::assembly::riscv::PseudoVREM_VX_M8_E32 = 8218 , LIEF::assembly::riscv::PseudoVREM_VX_M8_E32_MASK = 8219 ,
  LIEF::assembly::riscv::PseudoVREM_VX_M8_E64 = 8220 , LIEF::assembly::riscv::PseudoVREM_VX_M8_E64_MASK = 8221 , LIEF::assembly::riscv::PseudoVREM_VX_M8_E8 = 8222 , LIEF::assembly::riscv::PseudoVREM_VX_M8_E8_MASK = 8223 ,
  LIEF::assembly::riscv::PseudoVREM_VX_MF2_E16 = 8224 , LIEF::assembly::riscv::PseudoVREM_VX_MF2_E16_MASK = 8225 , LIEF::assembly::riscv::PseudoVREM_VX_MF2_E32 = 8226 , LIEF::assembly::riscv::PseudoVREM_VX_MF2_E32_MASK = 8227 ,
  LIEF::assembly::riscv::PseudoVREM_VX_MF2_E8 = 8228 , LIEF::assembly::riscv::PseudoVREM_VX_MF2_E8_MASK = 8229 , LIEF::assembly::riscv::PseudoVREM_VX_MF4_E16 = 8230 , LIEF::assembly::riscv::PseudoVREM_VX_MF4_E16_MASK = 8231 ,
  LIEF::assembly::riscv::PseudoVREM_VX_MF4_E8 = 8232 , LIEF::assembly::riscv::PseudoVREM_VX_MF4_E8_MASK = 8233 , LIEF::assembly::riscv::PseudoVREM_VX_MF8_E8 = 8234 , LIEF::assembly::riscv::PseudoVREM_VX_MF8_E8_MASK = 8235 ,
  LIEF::assembly::riscv::PseudoVREV8_V_M1 = 8236 , LIEF::assembly::riscv::PseudoVREV8_V_M1_MASK = 8237 , LIEF::assembly::riscv::PseudoVREV8_V_M2 = 8238 , LIEF::assembly::riscv::PseudoVREV8_V_M2_MASK = 8239 ,
  LIEF::assembly::riscv::PseudoVREV8_V_M4 = 8240 , LIEF::assembly::riscv::PseudoVREV8_V_M4_MASK = 8241 , LIEF::assembly::riscv::PseudoVREV8_V_M8 = 8242 , LIEF::assembly::riscv::PseudoVREV8_V_M8_MASK = 8243 ,
  LIEF::assembly::riscv::PseudoVREV8_V_MF2 = 8244 , LIEF::assembly::riscv::PseudoVREV8_V_MF2_MASK = 8245 , LIEF::assembly::riscv::PseudoVREV8_V_MF4 = 8246 , LIEF::assembly::riscv::PseudoVREV8_V_MF4_MASK = 8247 ,
  LIEF::assembly::riscv::PseudoVREV8_V_MF8 = 8248 , LIEF::assembly::riscv::PseudoVREV8_V_MF8_MASK = 8249 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E16_M1 = 8250 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E16_M1_MASK = 8251 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E16_M2 = 8252 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E16_M2_MASK = 8253 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E16_MF2 = 8254 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK = 8255 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E16_MF4 = 8256 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK = 8257 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E32_M1 = 8258 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E32_M1_MASK = 8259 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E32_M2 = 8260 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E32_M2_MASK = 8261 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E32_MF2 = 8262 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK = 8263 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E32_MF4 = 8264 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK = 8265 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E64_M1 = 8266 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E64_M1_MASK = 8267 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E64_M2 = 8268 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E64_M2_MASK = 8269 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E64_MF2 = 8270 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK = 8271 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E64_MF4 = 8272 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK = 8273 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E8_M1 = 8274 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E8_M1_MASK = 8275 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E8_M2 = 8276 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E8_M2_MASK = 8277 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E8_MF2 = 8278 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK = 8279 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E8_MF4 = 8280 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK = 8281 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E16_M1 = 8282 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E16_M1_MASK = 8283 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E16_M2 = 8284 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E16_M2_MASK = 8285 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E16_M4 = 8286 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E16_M4_MASK = 8287 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E16_MF2 = 8288 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK = 8289 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E32_M1 = 8290 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E32_M1_MASK = 8291 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E32_M2 = 8292 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E32_M2_MASK = 8293 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E32_M4 = 8294 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E32_M4_MASK = 8295 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E32_MF2 = 8296 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK = 8297 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E64_M1 = 8298 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E64_M1_MASK = 8299 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E64_M2 = 8300 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E64_M2_MASK = 8301 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E64_M4 = 8302 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E64_M4_MASK = 8303 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E64_MF2 = 8304 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK = 8305 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E8_M1 = 8306 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E8_M1_MASK = 8307 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E8_M2 = 8308 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E8_M2_MASK = 8309 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E8_M4 = 8310 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E8_M4_MASK = 8311 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E8_MF2 = 8312 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK = 8313 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E16_M1 = 8314 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E16_M1_MASK = 8315 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E16_M2 = 8316 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E16_M2_MASK = 8317 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E16_M4 = 8318 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E16_M4_MASK = 8319 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E16_M8 = 8320 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E16_M8_MASK = 8321 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E32_M1 = 8322 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E32_M1_MASK = 8323 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E32_M2 = 8324 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E32_M2_MASK = 8325 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E32_M4 = 8326 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E32_M4_MASK = 8327 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E32_M8 = 8328 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E32_M8_MASK = 8329 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E64_M1 = 8330 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E64_M1_MASK = 8331 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E64_M2 = 8332 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E64_M2_MASK = 8333 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E64_M4 = 8334 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E64_M4_MASK = 8335 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E64_M8 = 8336 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E64_M8_MASK = 8337 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E8_M1 = 8338 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E8_M1_MASK = 8339 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E8_M2 = 8340 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E8_M2_MASK = 8341 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E8_M4 = 8342 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E8_M4_MASK = 8343 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E8_M8 = 8344 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M4_E8_M8_MASK = 8345 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E16_M2 = 8346 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E16_M2_MASK = 8347 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E16_M4 = 8348 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E16_M4_MASK = 8349 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E16_M8 = 8350 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E16_M8_MASK = 8351 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E32_M2 = 8352 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E32_M2_MASK = 8353 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E32_M4 = 8354 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E32_M4_MASK = 8355 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E32_M8 = 8356 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E32_M8_MASK = 8357 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E64_M2 = 8358 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E64_M2_MASK = 8359 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E64_M4 = 8360 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E64_M4_MASK = 8361 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E64_M8 = 8362 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E64_M8_MASK = 8363 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E8_M2 = 8364 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E8_M2_MASK = 8365 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E8_M4 = 8366 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E8_M4_MASK = 8367 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E8_M8 = 8368 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_M8_E8_M8_MASK = 8369 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E16_M1 = 8370 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK = 8371 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E16_MF2 = 8372 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK = 8373 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E16_MF4 = 8374 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK = 8375 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E16_MF8 = 8376 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK = 8377 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E32_M1 = 8378 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK = 8379 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E32_MF2 = 8380 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK = 8381 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E32_MF4 = 8382 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK = 8383 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E32_MF8 = 8384 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK = 8385 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E8_M1 = 8386 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK = 8387 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E8_MF2 = 8388 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK = 8389 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E8_MF4 = 8390 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK = 8391 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E8_MF8 = 8392 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK = 8393 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E16_MF2 = 8394 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK = 8395 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E16_MF4 = 8396 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK = 8397 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E16_MF8 = 8398 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK = 8399 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E8_MF2 = 8400 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK = 8401 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E8_MF4 = 8402 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK = 8403 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E8_MF8 = 8404 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK = 8405 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF8_E8_MF4 = 8406 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK = 8407 ,
  LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF8_E8_MF8 = 8408 , LIEF::assembly::riscv::PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK = 8409 , LIEF::assembly::riscv::PseudoVRGATHER_VI_M1 = 8410 , LIEF::assembly::riscv::PseudoVRGATHER_VI_M1_MASK = 8411 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VI_M2 = 8412 , LIEF::assembly::riscv::PseudoVRGATHER_VI_M2_MASK = 8413 , LIEF::assembly::riscv::PseudoVRGATHER_VI_M4 = 8414 , LIEF::assembly::riscv::PseudoVRGATHER_VI_M4_MASK = 8415 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VI_M8 = 8416 , LIEF::assembly::riscv::PseudoVRGATHER_VI_M8_MASK = 8417 , LIEF::assembly::riscv::PseudoVRGATHER_VI_MF2 = 8418 , LIEF::assembly::riscv::PseudoVRGATHER_VI_MF2_MASK = 8419 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VI_MF4 = 8420 , LIEF::assembly::riscv::PseudoVRGATHER_VI_MF4_MASK = 8421 , LIEF::assembly::riscv::PseudoVRGATHER_VI_MF8 = 8422 , LIEF::assembly::riscv::PseudoVRGATHER_VI_MF8_MASK = 8423 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_M1_E16 = 8424 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M1_E16_MASK = 8425 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M1_E32 = 8426 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M1_E32_MASK = 8427 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_M1_E64 = 8428 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M1_E64_MASK = 8429 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M1_E8 = 8430 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M1_E8_MASK = 8431 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_M2_E16 = 8432 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M2_E16_MASK = 8433 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M2_E32 = 8434 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M2_E32_MASK = 8435 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_M2_E64 = 8436 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M2_E64_MASK = 8437 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M2_E8 = 8438 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M2_E8_MASK = 8439 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_M4_E16 = 8440 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M4_E16_MASK = 8441 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M4_E32 = 8442 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M4_E32_MASK = 8443 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_M4_E64 = 8444 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M4_E64_MASK = 8445 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M4_E8 = 8446 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M4_E8_MASK = 8447 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_M8_E16 = 8448 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M8_E16_MASK = 8449 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M8_E32 = 8450 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M8_E32_MASK = 8451 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_M8_E64 = 8452 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M8_E64_MASK = 8453 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M8_E8 = 8454 , LIEF::assembly::riscv::PseudoVRGATHER_VV_M8_E8_MASK = 8455 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_MF2_E16 = 8456 , LIEF::assembly::riscv::PseudoVRGATHER_VV_MF2_E16_MASK = 8457 , LIEF::assembly::riscv::PseudoVRGATHER_VV_MF2_E32 = 8458 , LIEF::assembly::riscv::PseudoVRGATHER_VV_MF2_E32_MASK = 8459 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_MF2_E8 = 8460 , LIEF::assembly::riscv::PseudoVRGATHER_VV_MF2_E8_MASK = 8461 , LIEF::assembly::riscv::PseudoVRGATHER_VV_MF4_E16 = 8462 , LIEF::assembly::riscv::PseudoVRGATHER_VV_MF4_E16_MASK = 8463 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VV_MF4_E8 = 8464 , LIEF::assembly::riscv::PseudoVRGATHER_VV_MF4_E8_MASK = 8465 , LIEF::assembly::riscv::PseudoVRGATHER_VV_MF8_E8 = 8466 , LIEF::assembly::riscv::PseudoVRGATHER_VV_MF8_E8_MASK = 8467 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VX_M1 = 8468 , LIEF::assembly::riscv::PseudoVRGATHER_VX_M1_MASK = 8469 , LIEF::assembly::riscv::PseudoVRGATHER_VX_M2 = 8470 , LIEF::assembly::riscv::PseudoVRGATHER_VX_M2_MASK = 8471 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VX_M4 = 8472 , LIEF::assembly::riscv::PseudoVRGATHER_VX_M4_MASK = 8473 , LIEF::assembly::riscv::PseudoVRGATHER_VX_M8 = 8474 , LIEF::assembly::riscv::PseudoVRGATHER_VX_M8_MASK = 8475 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VX_MF2 = 8476 , LIEF::assembly::riscv::PseudoVRGATHER_VX_MF2_MASK = 8477 , LIEF::assembly::riscv::PseudoVRGATHER_VX_MF4 = 8478 , LIEF::assembly::riscv::PseudoVRGATHER_VX_MF4_MASK = 8479 ,
  LIEF::assembly::riscv::PseudoVRGATHER_VX_MF8 = 8480 , LIEF::assembly::riscv::PseudoVRGATHER_VX_MF8_MASK = 8481 , LIEF::assembly::riscv::PseudoVROL_VV_M1 = 8482 , LIEF::assembly::riscv::PseudoVROL_VV_M1_MASK = 8483 ,
  LIEF::assembly::riscv::PseudoVROL_VV_M2 = 8484 , LIEF::assembly::riscv::PseudoVROL_VV_M2_MASK = 8485 , LIEF::assembly::riscv::PseudoVROL_VV_M4 = 8486 , LIEF::assembly::riscv::PseudoVROL_VV_M4_MASK = 8487 ,
  LIEF::assembly::riscv::PseudoVROL_VV_M8 = 8488 , LIEF::assembly::riscv::PseudoVROL_VV_M8_MASK = 8489 , LIEF::assembly::riscv::PseudoVROL_VV_MF2 = 8490 , LIEF::assembly::riscv::PseudoVROL_VV_MF2_MASK = 8491 ,
  LIEF::assembly::riscv::PseudoVROL_VV_MF4 = 8492 , LIEF::assembly::riscv::PseudoVROL_VV_MF4_MASK = 8493 , LIEF::assembly::riscv::PseudoVROL_VV_MF8 = 8494 , LIEF::assembly::riscv::PseudoVROL_VV_MF8_MASK = 8495 ,
  LIEF::assembly::riscv::PseudoVROL_VX_M1 = 8496 , LIEF::assembly::riscv::PseudoVROL_VX_M1_MASK = 8497 , LIEF::assembly::riscv::PseudoVROL_VX_M2 = 8498 , LIEF::assembly::riscv::PseudoVROL_VX_M2_MASK = 8499 ,
  LIEF::assembly::riscv::PseudoVROL_VX_M4 = 8500 , LIEF::assembly::riscv::PseudoVROL_VX_M4_MASK = 8501 , LIEF::assembly::riscv::PseudoVROL_VX_M8 = 8502 , LIEF::assembly::riscv::PseudoVROL_VX_M8_MASK = 8503 ,
  LIEF::assembly::riscv::PseudoVROL_VX_MF2 = 8504 , LIEF::assembly::riscv::PseudoVROL_VX_MF2_MASK = 8505 , LIEF::assembly::riscv::PseudoVROL_VX_MF4 = 8506 , LIEF::assembly::riscv::PseudoVROL_VX_MF4_MASK = 8507 ,
  LIEF::assembly::riscv::PseudoVROL_VX_MF8 = 8508 , LIEF::assembly::riscv::PseudoVROL_VX_MF8_MASK = 8509 , LIEF::assembly::riscv::PseudoVROR_VI_M1 = 8510 , LIEF::assembly::riscv::PseudoVROR_VI_M1_MASK = 8511 ,
  LIEF::assembly::riscv::PseudoVROR_VI_M2 = 8512 , LIEF::assembly::riscv::PseudoVROR_VI_M2_MASK = 8513 , LIEF::assembly::riscv::PseudoVROR_VI_M4 = 8514 , LIEF::assembly::riscv::PseudoVROR_VI_M4_MASK = 8515 ,
  LIEF::assembly::riscv::PseudoVROR_VI_M8 = 8516 , LIEF::assembly::riscv::PseudoVROR_VI_M8_MASK = 8517 , LIEF::assembly::riscv::PseudoVROR_VI_MF2 = 8518 , LIEF::assembly::riscv::PseudoVROR_VI_MF2_MASK = 8519 ,
  LIEF::assembly::riscv::PseudoVROR_VI_MF4 = 8520 , LIEF::assembly::riscv::PseudoVROR_VI_MF4_MASK = 8521 , LIEF::assembly::riscv::PseudoVROR_VI_MF8 = 8522 , LIEF::assembly::riscv::PseudoVROR_VI_MF8_MASK = 8523 ,
  LIEF::assembly::riscv::PseudoVROR_VV_M1 = 8524 , LIEF::assembly::riscv::PseudoVROR_VV_M1_MASK = 8525 , LIEF::assembly::riscv::PseudoVROR_VV_M2 = 8526 , LIEF::assembly::riscv::PseudoVROR_VV_M2_MASK = 8527 ,
  LIEF::assembly::riscv::PseudoVROR_VV_M4 = 8528 , LIEF::assembly::riscv::PseudoVROR_VV_M4_MASK = 8529 , LIEF::assembly::riscv::PseudoVROR_VV_M8 = 8530 , LIEF::assembly::riscv::PseudoVROR_VV_M8_MASK = 8531 ,
  LIEF::assembly::riscv::PseudoVROR_VV_MF2 = 8532 , LIEF::assembly::riscv::PseudoVROR_VV_MF2_MASK = 8533 , LIEF::assembly::riscv::PseudoVROR_VV_MF4 = 8534 , LIEF::assembly::riscv::PseudoVROR_VV_MF4_MASK = 8535 ,
  LIEF::assembly::riscv::PseudoVROR_VV_MF8 = 8536 , LIEF::assembly::riscv::PseudoVROR_VV_MF8_MASK = 8537 , LIEF::assembly::riscv::PseudoVROR_VX_M1 = 8538 , LIEF::assembly::riscv::PseudoVROR_VX_M1_MASK = 8539 ,
  LIEF::assembly::riscv::PseudoVROR_VX_M2 = 8540 , LIEF::assembly::riscv::PseudoVROR_VX_M2_MASK = 8541 , LIEF::assembly::riscv::PseudoVROR_VX_M4 = 8542 , LIEF::assembly::riscv::PseudoVROR_VX_M4_MASK = 8543 ,
  LIEF::assembly::riscv::PseudoVROR_VX_M8 = 8544 , LIEF::assembly::riscv::PseudoVROR_VX_M8_MASK = 8545 , LIEF::assembly::riscv::PseudoVROR_VX_MF2 = 8546 , LIEF::assembly::riscv::PseudoVROR_VX_MF2_MASK = 8547 ,
  LIEF::assembly::riscv::PseudoVROR_VX_MF4 = 8548 , LIEF::assembly::riscv::PseudoVROR_VX_MF4_MASK = 8549 , LIEF::assembly::riscv::PseudoVROR_VX_MF8 = 8550 , LIEF::assembly::riscv::PseudoVROR_VX_MF8_MASK = 8551 ,
  LIEF::assembly::riscv::PseudoVRSUB_VI_M1 = 8552 , LIEF::assembly::riscv::PseudoVRSUB_VI_M1_MASK = 8553 , LIEF::assembly::riscv::PseudoVRSUB_VI_M2 = 8554 , LIEF::assembly::riscv::PseudoVRSUB_VI_M2_MASK = 8555 ,
  LIEF::assembly::riscv::PseudoVRSUB_VI_M4 = 8556 , LIEF::assembly::riscv::PseudoVRSUB_VI_M4_MASK = 8557 , LIEF::assembly::riscv::PseudoVRSUB_VI_M8 = 8558 , LIEF::assembly::riscv::PseudoVRSUB_VI_M8_MASK = 8559 ,
  LIEF::assembly::riscv::PseudoVRSUB_VI_MF2 = 8560 , LIEF::assembly::riscv::PseudoVRSUB_VI_MF2_MASK = 8561 , LIEF::assembly::riscv::PseudoVRSUB_VI_MF4 = 8562 , LIEF::assembly::riscv::PseudoVRSUB_VI_MF4_MASK = 8563 ,
  LIEF::assembly::riscv::PseudoVRSUB_VI_MF8 = 8564 , LIEF::assembly::riscv::PseudoVRSUB_VI_MF8_MASK = 8565 , LIEF::assembly::riscv::PseudoVRSUB_VX_M1 = 8566 , LIEF::assembly::riscv::PseudoVRSUB_VX_M1_MASK = 8567 ,
  LIEF::assembly::riscv::PseudoVRSUB_VX_M2 = 8568 , LIEF::assembly::riscv::PseudoVRSUB_VX_M2_MASK = 8569 , LIEF::assembly::riscv::PseudoVRSUB_VX_M4 = 8570 , LIEF::assembly::riscv::PseudoVRSUB_VX_M4_MASK = 8571 ,
  LIEF::assembly::riscv::PseudoVRSUB_VX_M8 = 8572 , LIEF::assembly::riscv::PseudoVRSUB_VX_M8_MASK = 8573 , LIEF::assembly::riscv::PseudoVRSUB_VX_MF2 = 8574 , LIEF::assembly::riscv::PseudoVRSUB_VX_MF2_MASK = 8575 ,
  LIEF::assembly::riscv::PseudoVRSUB_VX_MF4 = 8576 , LIEF::assembly::riscv::PseudoVRSUB_VX_MF4_MASK = 8577 , LIEF::assembly::riscv::PseudoVRSUB_VX_MF8 = 8578 , LIEF::assembly::riscv::PseudoVRSUB_VX_MF8_MASK = 8579 ,
  LIEF::assembly::riscv::PseudoVSADDU_VI_M1 = 8580 , LIEF::assembly::riscv::PseudoVSADDU_VI_M1_MASK = 8581 , LIEF::assembly::riscv::PseudoVSADDU_VI_M2 = 8582 , LIEF::assembly::riscv::PseudoVSADDU_VI_M2_MASK = 8583 ,
  LIEF::assembly::riscv::PseudoVSADDU_VI_M4 = 8584 , LIEF::assembly::riscv::PseudoVSADDU_VI_M4_MASK = 8585 , LIEF::assembly::riscv::PseudoVSADDU_VI_M8 = 8586 , LIEF::assembly::riscv::PseudoVSADDU_VI_M8_MASK = 8587 ,
  LIEF::assembly::riscv::PseudoVSADDU_VI_MF2 = 8588 , LIEF::assembly::riscv::PseudoVSADDU_VI_MF2_MASK = 8589 , LIEF::assembly::riscv::PseudoVSADDU_VI_MF4 = 8590 , LIEF::assembly::riscv::PseudoVSADDU_VI_MF4_MASK = 8591 ,
  LIEF::assembly::riscv::PseudoVSADDU_VI_MF8 = 8592 , LIEF::assembly::riscv::PseudoVSADDU_VI_MF8_MASK = 8593 , LIEF::assembly::riscv::PseudoVSADDU_VV_M1 = 8594 , LIEF::assembly::riscv::PseudoVSADDU_VV_M1_MASK = 8595 ,
  LIEF::assembly::riscv::PseudoVSADDU_VV_M2 = 8596 , LIEF::assembly::riscv::PseudoVSADDU_VV_M2_MASK = 8597 , LIEF::assembly::riscv::PseudoVSADDU_VV_M4 = 8598 , LIEF::assembly::riscv::PseudoVSADDU_VV_M4_MASK = 8599 ,
  LIEF::assembly::riscv::PseudoVSADDU_VV_M8 = 8600 , LIEF::assembly::riscv::PseudoVSADDU_VV_M8_MASK = 8601 , LIEF::assembly::riscv::PseudoVSADDU_VV_MF2 = 8602 , LIEF::assembly::riscv::PseudoVSADDU_VV_MF2_MASK = 8603 ,
  LIEF::assembly::riscv::PseudoVSADDU_VV_MF4 = 8604 , LIEF::assembly::riscv::PseudoVSADDU_VV_MF4_MASK = 8605 , LIEF::assembly::riscv::PseudoVSADDU_VV_MF8 = 8606 , LIEF::assembly::riscv::PseudoVSADDU_VV_MF8_MASK = 8607 ,
  LIEF::assembly::riscv::PseudoVSADDU_VX_M1 = 8608 , LIEF::assembly::riscv::PseudoVSADDU_VX_M1_MASK = 8609 , LIEF::assembly::riscv::PseudoVSADDU_VX_M2 = 8610 , LIEF::assembly::riscv::PseudoVSADDU_VX_M2_MASK = 8611 ,
  LIEF::assembly::riscv::PseudoVSADDU_VX_M4 = 8612 , LIEF::assembly::riscv::PseudoVSADDU_VX_M4_MASK = 8613 , LIEF::assembly::riscv::PseudoVSADDU_VX_M8 = 8614 , LIEF::assembly::riscv::PseudoVSADDU_VX_M8_MASK = 8615 ,
  LIEF::assembly::riscv::PseudoVSADDU_VX_MF2 = 8616 , LIEF::assembly::riscv::PseudoVSADDU_VX_MF2_MASK = 8617 , LIEF::assembly::riscv::PseudoVSADDU_VX_MF4 = 8618 , LIEF::assembly::riscv::PseudoVSADDU_VX_MF4_MASK = 8619 ,
  LIEF::assembly::riscv::PseudoVSADDU_VX_MF8 = 8620 , LIEF::assembly::riscv::PseudoVSADDU_VX_MF8_MASK = 8621 , LIEF::assembly::riscv::PseudoVSADD_VI_M1 = 8622 , LIEF::assembly::riscv::PseudoVSADD_VI_M1_MASK = 8623 ,
  LIEF::assembly::riscv::PseudoVSADD_VI_M2 = 8624 , LIEF::assembly::riscv::PseudoVSADD_VI_M2_MASK = 8625 , LIEF::assembly::riscv::PseudoVSADD_VI_M4 = 8626 , LIEF::assembly::riscv::PseudoVSADD_VI_M4_MASK = 8627 ,
  LIEF::assembly::riscv::PseudoVSADD_VI_M8 = 8628 , LIEF::assembly::riscv::PseudoVSADD_VI_M8_MASK = 8629 , LIEF::assembly::riscv::PseudoVSADD_VI_MF2 = 8630 , LIEF::assembly::riscv::PseudoVSADD_VI_MF2_MASK = 8631 ,
  LIEF::assembly::riscv::PseudoVSADD_VI_MF4 = 8632 , LIEF::assembly::riscv::PseudoVSADD_VI_MF4_MASK = 8633 , LIEF::assembly::riscv::PseudoVSADD_VI_MF8 = 8634 , LIEF::assembly::riscv::PseudoVSADD_VI_MF8_MASK = 8635 ,
  LIEF::assembly::riscv::PseudoVSADD_VV_M1 = 8636 , LIEF::assembly::riscv::PseudoVSADD_VV_M1_MASK = 8637 , LIEF::assembly::riscv::PseudoVSADD_VV_M2 = 8638 , LIEF::assembly::riscv::PseudoVSADD_VV_M2_MASK = 8639 ,
  LIEF::assembly::riscv::PseudoVSADD_VV_M4 = 8640 , LIEF::assembly::riscv::PseudoVSADD_VV_M4_MASK = 8641 , LIEF::assembly::riscv::PseudoVSADD_VV_M8 = 8642 , LIEF::assembly::riscv::PseudoVSADD_VV_M8_MASK = 8643 ,
  LIEF::assembly::riscv::PseudoVSADD_VV_MF2 = 8644 , LIEF::assembly::riscv::PseudoVSADD_VV_MF2_MASK = 8645 , LIEF::assembly::riscv::PseudoVSADD_VV_MF4 = 8646 , LIEF::assembly::riscv::PseudoVSADD_VV_MF4_MASK = 8647 ,
  LIEF::assembly::riscv::PseudoVSADD_VV_MF8 = 8648 , LIEF::assembly::riscv::PseudoVSADD_VV_MF8_MASK = 8649 , LIEF::assembly::riscv::PseudoVSADD_VX_M1 = 8650 , LIEF::assembly::riscv::PseudoVSADD_VX_M1_MASK = 8651 ,
  LIEF::assembly::riscv::PseudoVSADD_VX_M2 = 8652 , LIEF::assembly::riscv::PseudoVSADD_VX_M2_MASK = 8653 , LIEF::assembly::riscv::PseudoVSADD_VX_M4 = 8654 , LIEF::assembly::riscv::PseudoVSADD_VX_M4_MASK = 8655 ,
  LIEF::assembly::riscv::PseudoVSADD_VX_M8 = 8656 , LIEF::assembly::riscv::PseudoVSADD_VX_M8_MASK = 8657 , LIEF::assembly::riscv::PseudoVSADD_VX_MF2 = 8658 , LIEF::assembly::riscv::PseudoVSADD_VX_MF2_MASK = 8659 ,
  LIEF::assembly::riscv::PseudoVSADD_VX_MF4 = 8660 , LIEF::assembly::riscv::PseudoVSADD_VX_MF4_MASK = 8661 , LIEF::assembly::riscv::PseudoVSADD_VX_MF8 = 8662 , LIEF::assembly::riscv::PseudoVSADD_VX_MF8_MASK = 8663 ,
  LIEF::assembly::riscv::PseudoVSBC_VVM_M1 = 8664 , LIEF::assembly::riscv::PseudoVSBC_VVM_M2 = 8665 , LIEF::assembly::riscv::PseudoVSBC_VVM_M4 = 8666 , LIEF::assembly::riscv::PseudoVSBC_VVM_M8 = 8667 ,
  LIEF::assembly::riscv::PseudoVSBC_VVM_MF2 = 8668 , LIEF::assembly::riscv::PseudoVSBC_VVM_MF4 = 8669 , LIEF::assembly::riscv::PseudoVSBC_VVM_MF8 = 8670 , LIEF::assembly::riscv::PseudoVSBC_VXM_M1 = 8671 ,
  LIEF::assembly::riscv::PseudoVSBC_VXM_M2 = 8672 , LIEF::assembly::riscv::PseudoVSBC_VXM_M4 = 8673 , LIEF::assembly::riscv::PseudoVSBC_VXM_M8 = 8674 , LIEF::assembly::riscv::PseudoVSBC_VXM_MF2 = 8675 ,
  LIEF::assembly::riscv::PseudoVSBC_VXM_MF4 = 8676 , LIEF::assembly::riscv::PseudoVSBC_VXM_MF8 = 8677 , LIEF::assembly::riscv::PseudoVSE16_V_M1 = 8678 , LIEF::assembly::riscv::PseudoVSE16_V_M1_MASK = 8679 ,
  LIEF::assembly::riscv::PseudoVSE16_V_M2 = 8680 , LIEF::assembly::riscv::PseudoVSE16_V_M2_MASK = 8681 , LIEF::assembly::riscv::PseudoVSE16_V_M4 = 8682 , LIEF::assembly::riscv::PseudoVSE16_V_M4_MASK = 8683 ,
  LIEF::assembly::riscv::PseudoVSE16_V_M8 = 8684 , LIEF::assembly::riscv::PseudoVSE16_V_M8_MASK = 8685 , LIEF::assembly::riscv::PseudoVSE16_V_MF2 = 8686 , LIEF::assembly::riscv::PseudoVSE16_V_MF2_MASK = 8687 ,
  LIEF::assembly::riscv::PseudoVSE16_V_MF4 = 8688 , LIEF::assembly::riscv::PseudoVSE16_V_MF4_MASK = 8689 , LIEF::assembly::riscv::PseudoVSE32_V_M1 = 8690 , LIEF::assembly::riscv::PseudoVSE32_V_M1_MASK = 8691 ,
  LIEF::assembly::riscv::PseudoVSE32_V_M2 = 8692 , LIEF::assembly::riscv::PseudoVSE32_V_M2_MASK = 8693 , LIEF::assembly::riscv::PseudoVSE32_V_M4 = 8694 , LIEF::assembly::riscv::PseudoVSE32_V_M4_MASK = 8695 ,
  LIEF::assembly::riscv::PseudoVSE32_V_M8 = 8696 , LIEF::assembly::riscv::PseudoVSE32_V_M8_MASK = 8697 , LIEF::assembly::riscv::PseudoVSE32_V_MF2 = 8698 , LIEF::assembly::riscv::PseudoVSE32_V_MF2_MASK = 8699 ,
  LIEF::assembly::riscv::PseudoVSE64_V_M1 = 8700 , LIEF::assembly::riscv::PseudoVSE64_V_M1_MASK = 8701 , LIEF::assembly::riscv::PseudoVSE64_V_M2 = 8702 , LIEF::assembly::riscv::PseudoVSE64_V_M2_MASK = 8703 ,
  LIEF::assembly::riscv::PseudoVSE64_V_M4 = 8704 , LIEF::assembly::riscv::PseudoVSE64_V_M4_MASK = 8705 , LIEF::assembly::riscv::PseudoVSE64_V_M8 = 8706 , LIEF::assembly::riscv::PseudoVSE64_V_M8_MASK = 8707 ,
  LIEF::assembly::riscv::PseudoVSE8_V_M1 = 8708 , LIEF::assembly::riscv::PseudoVSE8_V_M1_MASK = 8709 , LIEF::assembly::riscv::PseudoVSE8_V_M2 = 8710 , LIEF::assembly::riscv::PseudoVSE8_V_M2_MASK = 8711 ,
  LIEF::assembly::riscv::PseudoVSE8_V_M4 = 8712 , LIEF::assembly::riscv::PseudoVSE8_V_M4_MASK = 8713 , LIEF::assembly::riscv::PseudoVSE8_V_M8 = 8714 , LIEF::assembly::riscv::PseudoVSE8_V_M8_MASK = 8715 ,
  LIEF::assembly::riscv::PseudoVSE8_V_MF2 = 8716 , LIEF::assembly::riscv::PseudoVSE8_V_MF2_MASK = 8717 , LIEF::assembly::riscv::PseudoVSE8_V_MF4 = 8718 , LIEF::assembly::riscv::PseudoVSE8_V_MF4_MASK = 8719 ,
  LIEF::assembly::riscv::PseudoVSE8_V_MF8 = 8720 , LIEF::assembly::riscv::PseudoVSE8_V_MF8_MASK = 8721 , LIEF::assembly::riscv::PseudoVSETIVLI = 8722 , LIEF::assembly::riscv::PseudoVSETVLI = 8723 ,
  LIEF::assembly::riscv::PseudoVSETVLIX0 = 8724 , LIEF::assembly::riscv::PseudoVSEXT_VF2_M1 = 8725 , LIEF::assembly::riscv::PseudoVSEXT_VF2_M1_MASK = 8726 , LIEF::assembly::riscv::PseudoVSEXT_VF2_M2 = 8727 ,
  LIEF::assembly::riscv::PseudoVSEXT_VF2_M2_MASK = 8728 , LIEF::assembly::riscv::PseudoVSEXT_VF2_M4 = 8729 , LIEF::assembly::riscv::PseudoVSEXT_VF2_M4_MASK = 8730 , LIEF::assembly::riscv::PseudoVSEXT_VF2_M8 = 8731 ,
  LIEF::assembly::riscv::PseudoVSEXT_VF2_M8_MASK = 8732 , LIEF::assembly::riscv::PseudoVSEXT_VF2_MF2 = 8733 , LIEF::assembly::riscv::PseudoVSEXT_VF2_MF2_MASK = 8734 , LIEF::assembly::riscv::PseudoVSEXT_VF2_MF4 = 8735 ,
  LIEF::assembly::riscv::PseudoVSEXT_VF2_MF4_MASK = 8736 , LIEF::assembly::riscv::PseudoVSEXT_VF4_M1 = 8737 , LIEF::assembly::riscv::PseudoVSEXT_VF4_M1_MASK = 8738 , LIEF::assembly::riscv::PseudoVSEXT_VF4_M2 = 8739 ,
  LIEF::assembly::riscv::PseudoVSEXT_VF4_M2_MASK = 8740 , LIEF::assembly::riscv::PseudoVSEXT_VF4_M4 = 8741 , LIEF::assembly::riscv::PseudoVSEXT_VF4_M4_MASK = 8742 , LIEF::assembly::riscv::PseudoVSEXT_VF4_M8 = 8743 ,
  LIEF::assembly::riscv::PseudoVSEXT_VF4_M8_MASK = 8744 , LIEF::assembly::riscv::PseudoVSEXT_VF4_MF2 = 8745 , LIEF::assembly::riscv::PseudoVSEXT_VF4_MF2_MASK = 8746 , LIEF::assembly::riscv::PseudoVSEXT_VF8_M1 = 8747 ,
  LIEF::assembly::riscv::PseudoVSEXT_VF8_M1_MASK = 8748 , LIEF::assembly::riscv::PseudoVSEXT_VF8_M2 = 8749 , LIEF::assembly::riscv::PseudoVSEXT_VF8_M2_MASK = 8750 , LIEF::assembly::riscv::PseudoVSEXT_VF8_M4 = 8751 ,
  LIEF::assembly::riscv::PseudoVSEXT_VF8_M4_MASK = 8752 , LIEF::assembly::riscv::PseudoVSEXT_VF8_M8 = 8753 , LIEF::assembly::riscv::PseudoVSEXT_VF8_M8_MASK = 8754 , LIEF::assembly::riscv::PseudoVSHA2CH_VV_M1 = 8755 ,
  LIEF::assembly::riscv::PseudoVSHA2CH_VV_M2 = 8756 , LIEF::assembly::riscv::PseudoVSHA2CH_VV_M4 = 8757 , LIEF::assembly::riscv::PseudoVSHA2CH_VV_M8 = 8758 , LIEF::assembly::riscv::PseudoVSHA2CH_VV_MF2 = 8759 ,
  LIEF::assembly::riscv::PseudoVSHA2CL_VV_M1 = 8760 , LIEF::assembly::riscv::PseudoVSHA2CL_VV_M2 = 8761 , LIEF::assembly::riscv::PseudoVSHA2CL_VV_M4 = 8762 , LIEF::assembly::riscv::PseudoVSHA2CL_VV_M8 = 8763 ,
  LIEF::assembly::riscv::PseudoVSHA2CL_VV_MF2 = 8764 , LIEF::assembly::riscv::PseudoVSHA2MS_VV_M1 = 8765 , LIEF::assembly::riscv::PseudoVSHA2MS_VV_M2 = 8766 , LIEF::assembly::riscv::PseudoVSHA2MS_VV_M4 = 8767 ,
  LIEF::assembly::riscv::PseudoVSHA2MS_VV_M8 = 8768 , LIEF::assembly::riscv::PseudoVSHA2MS_VV_MF2 = 8769 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_M1 = 8770 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_M1_MASK = 8771 ,
  LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_M2 = 8772 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_M2_MASK = 8773 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_M4 = 8774 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_M4_MASK = 8775 ,
  LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_M8 = 8776 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_M8_MASK = 8777 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_MF2 = 8778 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_MF2_MASK = 8779 ,
  LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_MF4 = 8780 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_MF4_MASK = 8781 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_MF8 = 8782 , LIEF::assembly::riscv::PseudoVSLIDE1DOWN_VX_MF8_MASK = 8783 ,
  LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_M1 = 8784 , LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_M1_MASK = 8785 , LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_M2 = 8786 , LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_M2_MASK = 8787 ,
  LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_M4 = 8788 , LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_M4_MASK = 8789 , LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_M8 = 8790 , LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_M8_MASK = 8791 ,
  LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_MF2 = 8792 , LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_MF2_MASK = 8793 , LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_MF4 = 8794 , LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_MF4_MASK = 8795 ,
  LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_MF8 = 8796 , LIEF::assembly::riscv::PseudoVSLIDE1UP_VX_MF8_MASK = 8797 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_M1 = 8798 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_M1_MASK = 8799 ,
  LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_M2 = 8800 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_M2_MASK = 8801 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_M4 = 8802 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_M4_MASK = 8803 ,
  LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_M8 = 8804 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_M8_MASK = 8805 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_MF2 = 8806 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_MF2_MASK = 8807 ,
  LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_MF4 = 8808 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_MF4_MASK = 8809 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_MF8 = 8810 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VI_MF8_MASK = 8811 ,
  LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_M1 = 8812 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_M1_MASK = 8813 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_M2 = 8814 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_M2_MASK = 8815 ,
  LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_M4 = 8816 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_M4_MASK = 8817 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_M8 = 8818 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_M8_MASK = 8819 ,
  LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_MF2 = 8820 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_MF2_MASK = 8821 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_MF4 = 8822 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_MF4_MASK = 8823 ,
  LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_MF8 = 8824 , LIEF::assembly::riscv::PseudoVSLIDEDOWN_VX_MF8_MASK = 8825 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_M1 = 8826 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_M1_MASK = 8827 ,
  LIEF::assembly::riscv::PseudoVSLIDEUP_VI_M2 = 8828 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_M2_MASK = 8829 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_M4 = 8830 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_M4_MASK = 8831 ,
  LIEF::assembly::riscv::PseudoVSLIDEUP_VI_M8 = 8832 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_M8_MASK = 8833 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_MF2 = 8834 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_MF2_MASK = 8835 ,
  LIEF::assembly::riscv::PseudoVSLIDEUP_VI_MF4 = 8836 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_MF4_MASK = 8837 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_MF8 = 8838 , LIEF::assembly::riscv::PseudoVSLIDEUP_VI_MF8_MASK = 8839 ,
  LIEF::assembly::riscv::PseudoVSLIDEUP_VX_M1 = 8840 , LIEF::assembly::riscv::PseudoVSLIDEUP_VX_M1_MASK = 8841 , LIEF::assembly::riscv::PseudoVSLIDEUP_VX_M2 = 8842 , LIEF::assembly::riscv::PseudoVSLIDEUP_VX_M2_MASK = 8843 ,
  LIEF::assembly::riscv::PseudoVSLIDEUP_VX_M4 = 8844 , LIEF::assembly::riscv::PseudoVSLIDEUP_VX_M4_MASK = 8845 , LIEF::assembly::riscv::PseudoVSLIDEUP_VX_M8 = 8846 , LIEF::assembly::riscv::PseudoVSLIDEUP_VX_M8_MASK = 8847 ,
  LIEF::assembly::riscv::PseudoVSLIDEUP_VX_MF2 = 8848 , LIEF::assembly::riscv::PseudoVSLIDEUP_VX_MF2_MASK = 8849 , LIEF::assembly::riscv::PseudoVSLIDEUP_VX_MF4 = 8850 , LIEF::assembly::riscv::PseudoVSLIDEUP_VX_MF4_MASK = 8851 ,
  LIEF::assembly::riscv::PseudoVSLIDEUP_VX_MF8 = 8852 , LIEF::assembly::riscv::PseudoVSLIDEUP_VX_MF8_MASK = 8853 , LIEF::assembly::riscv::PseudoVSLL_VI_M1 = 8854 , LIEF::assembly::riscv::PseudoVSLL_VI_M1_MASK = 8855 ,
  LIEF::assembly::riscv::PseudoVSLL_VI_M2 = 8856 , LIEF::assembly::riscv::PseudoVSLL_VI_M2_MASK = 8857 , LIEF::assembly::riscv::PseudoVSLL_VI_M4 = 8858 , LIEF::assembly::riscv::PseudoVSLL_VI_M4_MASK = 8859 ,
  LIEF::assembly::riscv::PseudoVSLL_VI_M8 = 8860 , LIEF::assembly::riscv::PseudoVSLL_VI_M8_MASK = 8861 , LIEF::assembly::riscv::PseudoVSLL_VI_MF2 = 8862 , LIEF::assembly::riscv::PseudoVSLL_VI_MF2_MASK = 8863 ,
  LIEF::assembly::riscv::PseudoVSLL_VI_MF4 = 8864 , LIEF::assembly::riscv::PseudoVSLL_VI_MF4_MASK = 8865 , LIEF::assembly::riscv::PseudoVSLL_VI_MF8 = 8866 , LIEF::assembly::riscv::PseudoVSLL_VI_MF8_MASK = 8867 ,
  LIEF::assembly::riscv::PseudoVSLL_VV_M1 = 8868 , LIEF::assembly::riscv::PseudoVSLL_VV_M1_MASK = 8869 , LIEF::assembly::riscv::PseudoVSLL_VV_M2 = 8870 , LIEF::assembly::riscv::PseudoVSLL_VV_M2_MASK = 8871 ,
  LIEF::assembly::riscv::PseudoVSLL_VV_M4 = 8872 , LIEF::assembly::riscv::PseudoVSLL_VV_M4_MASK = 8873 , LIEF::assembly::riscv::PseudoVSLL_VV_M8 = 8874 , LIEF::assembly::riscv::PseudoVSLL_VV_M8_MASK = 8875 ,
  LIEF::assembly::riscv::PseudoVSLL_VV_MF2 = 8876 , LIEF::assembly::riscv::PseudoVSLL_VV_MF2_MASK = 8877 , LIEF::assembly::riscv::PseudoVSLL_VV_MF4 = 8878 , LIEF::assembly::riscv::PseudoVSLL_VV_MF4_MASK = 8879 ,
  LIEF::assembly::riscv::PseudoVSLL_VV_MF8 = 8880 , LIEF::assembly::riscv::PseudoVSLL_VV_MF8_MASK = 8881 , LIEF::assembly::riscv::PseudoVSLL_VX_M1 = 8882 , LIEF::assembly::riscv::PseudoVSLL_VX_M1_MASK = 8883 ,
  LIEF::assembly::riscv::PseudoVSLL_VX_M2 = 8884 , LIEF::assembly::riscv::PseudoVSLL_VX_M2_MASK = 8885 , LIEF::assembly::riscv::PseudoVSLL_VX_M4 = 8886 , LIEF::assembly::riscv::PseudoVSLL_VX_M4_MASK = 8887 ,
  LIEF::assembly::riscv::PseudoVSLL_VX_M8 = 8888 , LIEF::assembly::riscv::PseudoVSLL_VX_M8_MASK = 8889 , LIEF::assembly::riscv::PseudoVSLL_VX_MF2 = 8890 , LIEF::assembly::riscv::PseudoVSLL_VX_MF2_MASK = 8891 ,
  LIEF::assembly::riscv::PseudoVSLL_VX_MF4 = 8892 , LIEF::assembly::riscv::PseudoVSLL_VX_MF4_MASK = 8893 , LIEF::assembly::riscv::PseudoVSLL_VX_MF8 = 8894 , LIEF::assembly::riscv::PseudoVSLL_VX_MF8_MASK = 8895 ,
  LIEF::assembly::riscv::PseudoVSM3C_VI_M1 = 8896 , LIEF::assembly::riscv::PseudoVSM3C_VI_M2 = 8897 , LIEF::assembly::riscv::PseudoVSM3C_VI_M4 = 8898 , LIEF::assembly::riscv::PseudoVSM3C_VI_M8 = 8899 ,
  LIEF::assembly::riscv::PseudoVSM3C_VI_MF2 = 8900 , LIEF::assembly::riscv::PseudoVSM3ME_VV_M1 = 8901 , LIEF::assembly::riscv::PseudoVSM3ME_VV_M2 = 8902 , LIEF::assembly::riscv::PseudoVSM3ME_VV_M4 = 8903 ,
  LIEF::assembly::riscv::PseudoVSM3ME_VV_M8 = 8904 , LIEF::assembly::riscv::PseudoVSM3ME_VV_MF2 = 8905 , LIEF::assembly::riscv::PseudoVSM4K_VI_M1 = 8906 , LIEF::assembly::riscv::PseudoVSM4K_VI_M2 = 8907 ,
  LIEF::assembly::riscv::PseudoVSM4K_VI_M4 = 8908 , LIEF::assembly::riscv::PseudoVSM4K_VI_M8 = 8909 , LIEF::assembly::riscv::PseudoVSM4K_VI_MF2 = 8910 , LIEF::assembly::riscv::PseudoVSM4R_VS_M1_M1 = 8911 ,
  LIEF::assembly::riscv::PseudoVSM4R_VS_M1_MF2 = 8912 , LIEF::assembly::riscv::PseudoVSM4R_VS_M1_MF4 = 8913 , LIEF::assembly::riscv::PseudoVSM4R_VS_M1_MF8 = 8914 , LIEF::assembly::riscv::PseudoVSM4R_VS_M2_M1 = 8915 ,
  LIEF::assembly::riscv::PseudoVSM4R_VS_M2_M2 = 8916 , LIEF::assembly::riscv::PseudoVSM4R_VS_M2_MF2 = 8917 , LIEF::assembly::riscv::PseudoVSM4R_VS_M2_MF4 = 8918 , LIEF::assembly::riscv::PseudoVSM4R_VS_M2_MF8 = 8919 ,
  LIEF::assembly::riscv::PseudoVSM4R_VS_M4_M1 = 8920 , LIEF::assembly::riscv::PseudoVSM4R_VS_M4_M2 = 8921 , LIEF::assembly::riscv::PseudoVSM4R_VS_M4_M4 = 8922 , LIEF::assembly::riscv::PseudoVSM4R_VS_M4_MF2 = 8923 ,
  LIEF::assembly::riscv::PseudoVSM4R_VS_M4_MF4 = 8924 , LIEF::assembly::riscv::PseudoVSM4R_VS_M4_MF8 = 8925 , LIEF::assembly::riscv::PseudoVSM4R_VS_M8_M1 = 8926 , LIEF::assembly::riscv::PseudoVSM4R_VS_M8_M2 = 8927 ,
  LIEF::assembly::riscv::PseudoVSM4R_VS_M8_M4 = 8928 , LIEF::assembly::riscv::PseudoVSM4R_VS_M8_MF2 = 8929 , LIEF::assembly::riscv::PseudoVSM4R_VS_M8_MF4 = 8930 , LIEF::assembly::riscv::PseudoVSM4R_VS_M8_MF8 = 8931 ,
  LIEF::assembly::riscv::PseudoVSM4R_VS_MF2_MF2 = 8932 , LIEF::assembly::riscv::PseudoVSM4R_VS_MF2_MF4 = 8933 , LIEF::assembly::riscv::PseudoVSM4R_VS_MF2_MF8 = 8934 , LIEF::assembly::riscv::PseudoVSM4R_VV_M1 = 8935 ,
  LIEF::assembly::riscv::PseudoVSM4R_VV_M2 = 8936 , LIEF::assembly::riscv::PseudoVSM4R_VV_M4 = 8937 , LIEF::assembly::riscv::PseudoVSM4R_VV_M8 = 8938 , LIEF::assembly::riscv::PseudoVSM4R_VV_MF2 = 8939 ,
  LIEF::assembly::riscv::PseudoVSMUL_VV_M1 = 8940 , LIEF::assembly::riscv::PseudoVSMUL_VV_M1_MASK = 8941 , LIEF::assembly::riscv::PseudoVSMUL_VV_M2 = 8942 , LIEF::assembly::riscv::PseudoVSMUL_VV_M2_MASK = 8943 ,
  LIEF::assembly::riscv::PseudoVSMUL_VV_M4 = 8944 , LIEF::assembly::riscv::PseudoVSMUL_VV_M4_MASK = 8945 , LIEF::assembly::riscv::PseudoVSMUL_VV_M8 = 8946 , LIEF::assembly::riscv::PseudoVSMUL_VV_M8_MASK = 8947 ,
  LIEF::assembly::riscv::PseudoVSMUL_VV_MF2 = 8948 , LIEF::assembly::riscv::PseudoVSMUL_VV_MF2_MASK = 8949 , LIEF::assembly::riscv::PseudoVSMUL_VV_MF4 = 8950 , LIEF::assembly::riscv::PseudoVSMUL_VV_MF4_MASK = 8951 ,
  LIEF::assembly::riscv::PseudoVSMUL_VV_MF8 = 8952 , LIEF::assembly::riscv::PseudoVSMUL_VV_MF8_MASK = 8953 , LIEF::assembly::riscv::PseudoVSMUL_VX_M1 = 8954 , LIEF::assembly::riscv::PseudoVSMUL_VX_M1_MASK = 8955 ,
  LIEF::assembly::riscv::PseudoVSMUL_VX_M2 = 8956 , LIEF::assembly::riscv::PseudoVSMUL_VX_M2_MASK = 8957 , LIEF::assembly::riscv::PseudoVSMUL_VX_M4 = 8958 , LIEF::assembly::riscv::PseudoVSMUL_VX_M4_MASK = 8959 ,
  LIEF::assembly::riscv::PseudoVSMUL_VX_M8 = 8960 , LIEF::assembly::riscv::PseudoVSMUL_VX_M8_MASK = 8961 , LIEF::assembly::riscv::PseudoVSMUL_VX_MF2 = 8962 , LIEF::assembly::riscv::PseudoVSMUL_VX_MF2_MASK = 8963 ,
  LIEF::assembly::riscv::PseudoVSMUL_VX_MF4 = 8964 , LIEF::assembly::riscv::PseudoVSMUL_VX_MF4_MASK = 8965 , LIEF::assembly::riscv::PseudoVSMUL_VX_MF8 = 8966 , LIEF::assembly::riscv::PseudoVSMUL_VX_MF8_MASK = 8967 ,
  LIEF::assembly::riscv::PseudoVSM_V_B1 = 8968 , LIEF::assembly::riscv::PseudoVSM_V_B16 = 8969 , LIEF::assembly::riscv::PseudoVSM_V_B2 = 8970 , LIEF::assembly::riscv::PseudoVSM_V_B32 = 8971 ,
  LIEF::assembly::riscv::PseudoVSM_V_B4 = 8972 , LIEF::assembly::riscv::PseudoVSM_V_B64 = 8973 , LIEF::assembly::riscv::PseudoVSM_V_B8 = 8974 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M1_M1 = 8975 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_M1_M1_MASK = 8976 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M1_M2 = 8977 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M1_M2_MASK = 8978 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M1_M4 = 8979 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_M1_M4_MASK = 8980 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M1_MF2 = 8981 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M1_MF2_MASK = 8982 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M2_M1 = 8983 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_M2_M1_MASK = 8984 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M2_M2 = 8985 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M2_M2_MASK = 8986 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M2_M4 = 8987 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_M2_M4_MASK = 8988 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M2_M8 = 8989 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M2_M8_MASK = 8990 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M4_M2 = 8991 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_M4_M2_MASK = 8992 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M4_M4 = 8993 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M4_M4_MASK = 8994 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M4_M8 = 8995 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_M4_M8_MASK = 8996 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M8_M4 = 8997 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M8_M4_MASK = 8998 , LIEF::assembly::riscv::PseudoVSOXEI16_V_M8_M8 = 8999 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_M8_M8_MASK = 9000 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF2_M1 = 9001 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF2_M1_MASK = 9002 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF2_M2 = 9003 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_MF2_M2_MASK = 9004 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF2_MF2 = 9005 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF2_MF2_MASK = 9006 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF2_MF4 = 9007 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_MF2_MF4_MASK = 9008 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF4_M1 = 9009 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF4_M1_MASK = 9010 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF4_MF2 = 9011 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_MF4_MF2_MASK = 9012 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF4_MF4 = 9013 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF4_MF4_MASK = 9014 , LIEF::assembly::riscv::PseudoVSOXEI16_V_MF4_MF8 = 9015 ,
  LIEF::assembly::riscv::PseudoVSOXEI16_V_MF4_MF8_MASK = 9016 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M1_M1 = 9017 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M1_M1_MASK = 9018 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M1_M2 = 9019 ,
  LIEF::assembly::riscv::PseudoVSOXEI32_V_M1_M2_MASK = 9020 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M1_MF2 = 9021 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M1_MF2_MASK = 9022 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M1_MF4 = 9023 ,
  LIEF::assembly::riscv::PseudoVSOXEI32_V_M1_MF4_MASK = 9024 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M2_M1 = 9025 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M2_M1_MASK = 9026 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M2_M2 = 9027 ,
  LIEF::assembly::riscv::PseudoVSOXEI32_V_M2_M2_MASK = 9028 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M2_M4 = 9029 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M2_M4_MASK = 9030 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M2_MF2 = 9031 ,
  LIEF::assembly::riscv::PseudoVSOXEI32_V_M2_MF2_MASK = 9032 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M4_M1 = 9033 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M4_M1_MASK = 9034 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M4_M2 = 9035 ,
  LIEF::assembly::riscv::PseudoVSOXEI32_V_M4_M2_MASK = 9036 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M4_M4 = 9037 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M4_M4_MASK = 9038 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M4_M8 = 9039 ,
  LIEF::assembly::riscv::PseudoVSOXEI32_V_M4_M8_MASK = 9040 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M8_M2 = 9041 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M8_M2_MASK = 9042 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M8_M4 = 9043 ,
  LIEF::assembly::riscv::PseudoVSOXEI32_V_M8_M4_MASK = 9044 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M8_M8 = 9045 , LIEF::assembly::riscv::PseudoVSOXEI32_V_M8_M8_MASK = 9046 , LIEF::assembly::riscv::PseudoVSOXEI32_V_MF2_M1 = 9047 ,
  LIEF::assembly::riscv::PseudoVSOXEI32_V_MF2_M1_MASK = 9048 , LIEF::assembly::riscv::PseudoVSOXEI32_V_MF2_MF2 = 9049 , LIEF::assembly::riscv::PseudoVSOXEI32_V_MF2_MF2_MASK = 9050 , LIEF::assembly::riscv::PseudoVSOXEI32_V_MF2_MF4 = 9051 ,
  LIEF::assembly::riscv::PseudoVSOXEI32_V_MF2_MF4_MASK = 9052 , LIEF::assembly::riscv::PseudoVSOXEI32_V_MF2_MF8 = 9053 , LIEF::assembly::riscv::PseudoVSOXEI32_V_MF2_MF8_MASK = 9054 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M1_M1 = 9055 ,
  LIEF::assembly::riscv::PseudoVSOXEI64_V_M1_M1_MASK = 9056 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M1_MF2 = 9057 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M1_MF2_MASK = 9058 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M1_MF4 = 9059 ,
  LIEF::assembly::riscv::PseudoVSOXEI64_V_M1_MF4_MASK = 9060 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M1_MF8 = 9061 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M1_MF8_MASK = 9062 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M2_M1 = 9063 ,
  LIEF::assembly::riscv::PseudoVSOXEI64_V_M2_M1_MASK = 9064 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M2_M2 = 9065 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M2_M2_MASK = 9066 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M2_MF2 = 9067 ,
  LIEF::assembly::riscv::PseudoVSOXEI64_V_M2_MF2_MASK = 9068 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M2_MF4 = 9069 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M2_MF4_MASK = 9070 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M4_M1 = 9071 ,
  LIEF::assembly::riscv::PseudoVSOXEI64_V_M4_M1_MASK = 9072 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M4_M2 = 9073 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M4_M2_MASK = 9074 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M4_M4 = 9075 ,
  LIEF::assembly::riscv::PseudoVSOXEI64_V_M4_M4_MASK = 9076 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M4_MF2 = 9077 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M4_MF2_MASK = 9078 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M8_M1 = 9079 ,
  LIEF::assembly::riscv::PseudoVSOXEI64_V_M8_M1_MASK = 9080 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M8_M2 = 9081 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M8_M2_MASK = 9082 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M8_M4 = 9083 ,
  LIEF::assembly::riscv::PseudoVSOXEI64_V_M8_M4_MASK = 9084 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M8_M8 = 9085 , LIEF::assembly::riscv::PseudoVSOXEI64_V_M8_M8_MASK = 9086 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M1_M1 = 9087 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_M1_M1_MASK = 9088 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M1_M2 = 9089 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M1_M2_MASK = 9090 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M1_M4 = 9091 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_M1_M4_MASK = 9092 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M1_M8 = 9093 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M1_M8_MASK = 9094 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M2_M2 = 9095 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_M2_M2_MASK = 9096 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M2_M4 = 9097 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M2_M4_MASK = 9098 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M2_M8 = 9099 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_M2_M8_MASK = 9100 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M4_M4 = 9101 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M4_M4_MASK = 9102 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M4_M8 = 9103 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_M4_M8_MASK = 9104 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M8_M8 = 9105 , LIEF::assembly::riscv::PseudoVSOXEI8_V_M8_M8_MASK = 9106 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF2_M1 = 9107 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_MF2_M1_MASK = 9108 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF2_M2 = 9109 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF2_M2_MASK = 9110 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF2_M4 = 9111 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_MF2_M4_MASK = 9112 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF2_MF2 = 9113 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF2_MF2_MASK = 9114 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF4_M1 = 9115 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_MF4_M1_MASK = 9116 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF4_M2 = 9117 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF4_M2_MASK = 9118 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF4_MF2 = 9119 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_MF4_MF2_MASK = 9120 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF4_MF4 = 9121 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF4_MF4_MASK = 9122 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF8_M1 = 9123 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_MF8_M1_MASK = 9124 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF8_MF2 = 9125 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF8_MF2_MASK = 9126 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF8_MF4 = 9127 ,
  LIEF::assembly::riscv::PseudoVSOXEI8_V_MF8_MF4_MASK = 9128 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF8_MF8 = 9129 , LIEF::assembly::riscv::PseudoVSOXEI8_V_MF8_MF8_MASK = 9130 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M1_M1 = 9131 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M1_M1_MASK = 9132 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M1_M2 = 9133 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M1_M2_MASK = 9134 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M1_M4 = 9135 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M1_M4_MASK = 9136 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M1_MF2 = 9137 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M1_MF2_MASK = 9138 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M2_M1 = 9139 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M2_M1_MASK = 9140 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M2_M2 = 9141 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M2_M2_MASK = 9142 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M2_M4 = 9143 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M2_M4_MASK = 9144 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M4_M2 = 9145 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M4_M2_MASK = 9146 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M4_M4 = 9147 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M4_M4_MASK = 9148 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M8_M4 = 9149 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_M8_M4_MASK = 9150 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF2_M1 = 9151 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF2_M1_MASK = 9152 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF2_M2 = 9153 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF2_M2_MASK = 9154 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF2_MF2 = 9155 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF2_MF2_MASK = 9156 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF2_MF4 = 9157 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF2_MF4_MASK = 9158 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF4_M1 = 9159 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF4_M1_MASK = 9160 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF4_MF2 = 9161 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF4_MF2_MASK = 9162 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF4_MF4 = 9163 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF4_MF4_MASK = 9164 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF4_MF8 = 9165 , LIEF::assembly::riscv::PseudoVSOXSEG2EI16_V_MF4_MF8_MASK = 9166 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M1_M1 = 9167 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M1_M1_MASK = 9168 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M1_M2 = 9169 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M1_M2_MASK = 9170 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M1_MF2 = 9171 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M1_MF2_MASK = 9172 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M1_MF4 = 9173 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M1_MF4_MASK = 9174 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M2_M1 = 9175 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M2_M1_MASK = 9176 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M2_M2 = 9177 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M2_M2_MASK = 9178 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M2_M4 = 9179 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M2_M4_MASK = 9180 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M2_MF2 = 9181 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M2_MF2_MASK = 9182 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M4_M1 = 9183 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M4_M1_MASK = 9184 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M4_M2 = 9185 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M4_M2_MASK = 9186 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M4_M4 = 9187 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M4_M4_MASK = 9188 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M8_M2 = 9189 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M8_M2_MASK = 9190 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M8_M4 = 9191 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_M8_M4_MASK = 9192 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_MF2_M1 = 9193 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_MF2_M1_MASK = 9194 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_MF2_MF2 = 9195 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_MF2_MF2_MASK = 9196 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_MF2_MF4 = 9197 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_MF2_MF4_MASK = 9198 , LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_MF2_MF8 = 9199 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI32_V_MF2_MF8_MASK = 9200 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M1_M1 = 9201 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M1_M1_MASK = 9202 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M1_MF2 = 9203 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M1_MF2_MASK = 9204 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M1_MF4 = 9205 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M1_MF4_MASK = 9206 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M1_MF8 = 9207 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M1_MF8_MASK = 9208 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M2_M1 = 9209 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M2_M1_MASK = 9210 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M2_M2 = 9211 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M2_M2_MASK = 9212 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M2_MF2 = 9213 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M2_MF2_MASK = 9214 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M2_MF4 = 9215 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M2_MF4_MASK = 9216 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M4_M1 = 9217 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M4_M1_MASK = 9218 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M4_M2 = 9219 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M4_M2_MASK = 9220 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M4_M4 = 9221 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M4_M4_MASK = 9222 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M4_MF2 = 9223 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M4_MF2_MASK = 9224 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M8_M1 = 9225 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M8_M1_MASK = 9226 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M8_M2 = 9227 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M8_M2_MASK = 9228 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M8_M4 = 9229 , LIEF::assembly::riscv::PseudoVSOXSEG2EI64_V_M8_M4_MASK = 9230 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M1_M1 = 9231 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M1_M1_MASK = 9232 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M1_M2 = 9233 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M1_M2_MASK = 9234 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M1_M4 = 9235 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M1_M4_MASK = 9236 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M2_M2 = 9237 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M2_M2_MASK = 9238 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M2_M4 = 9239 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M2_M4_MASK = 9240 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M4_M4 = 9241 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_M4_M4_MASK = 9242 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF2_M1 = 9243 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF2_M1_MASK = 9244 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF2_M2 = 9245 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF2_M2_MASK = 9246 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF2_M4 = 9247 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF2_M4_MASK = 9248 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF2_MF2 = 9249 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF2_MF2_MASK = 9250 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF4_M1 = 9251 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF4_M1_MASK = 9252 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF4_M2 = 9253 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF4_M2_MASK = 9254 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF4_MF2 = 9255 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF4_MF2_MASK = 9256 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF4_MF4 = 9257 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF4_MF4_MASK = 9258 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF8_M1 = 9259 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF8_M1_MASK = 9260 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF8_MF2 = 9261 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF8_MF2_MASK = 9262 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF8_MF4 = 9263 ,
  LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF8_MF4_MASK = 9264 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF8_MF8 = 9265 , LIEF::assembly::riscv::PseudoVSOXSEG2EI8_V_MF8_MF8_MASK = 9266 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M1_M1 = 9267 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M1_M1_MASK = 9268 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M1_M2 = 9269 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M1_M2_MASK = 9270 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M1_MF2 = 9271 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M1_MF2_MASK = 9272 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M2_M1 = 9273 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M2_M1_MASK = 9274 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M2_M2 = 9275 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M2_M2_MASK = 9276 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M4_M2 = 9277 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_M4_M2_MASK = 9278 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF2_M1 = 9279 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF2_M1_MASK = 9280 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF2_M2 = 9281 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF2_M2_MASK = 9282 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF2_MF2 = 9283 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF2_MF2_MASK = 9284 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF2_MF4 = 9285 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF2_MF4_MASK = 9286 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF4_M1 = 9287 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF4_M1_MASK = 9288 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF4_MF2 = 9289 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF4_MF2_MASK = 9290 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF4_MF4 = 9291 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF4_MF4_MASK = 9292 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF4_MF8 = 9293 , LIEF::assembly::riscv::PseudoVSOXSEG3EI16_V_MF4_MF8_MASK = 9294 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M1_M1 = 9295 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M1_M1_MASK = 9296 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M1_M2 = 9297 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M1_M2_MASK = 9298 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M1_MF2 = 9299 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M1_MF2_MASK = 9300 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M1_MF4 = 9301 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M1_MF4_MASK = 9302 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M2_M1 = 9303 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M2_M1_MASK = 9304 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M2_M2 = 9305 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M2_M2_MASK = 9306 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M2_MF2 = 9307 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M2_MF2_MASK = 9308 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M4_M1 = 9309 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M4_M1_MASK = 9310 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M4_M2 = 9311 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M4_M2_MASK = 9312 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M8_M2 = 9313 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_M8_M2_MASK = 9314 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_MF2_M1 = 9315 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_MF2_M1_MASK = 9316 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_MF2_MF2 = 9317 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_MF2_MF2_MASK = 9318 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_MF2_MF4 = 9319 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_MF2_MF4_MASK = 9320 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_MF2_MF8 = 9321 , LIEF::assembly::riscv::PseudoVSOXSEG3EI32_V_MF2_MF8_MASK = 9322 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M1_M1 = 9323 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M1_M1_MASK = 9324 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M1_MF2 = 9325 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M1_MF2_MASK = 9326 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M1_MF4 = 9327 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M1_MF4_MASK = 9328 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M1_MF8 = 9329 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M1_MF8_MASK = 9330 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M2_M1 = 9331 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M2_M1_MASK = 9332 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M2_M2 = 9333 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M2_M2_MASK = 9334 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M2_MF2 = 9335 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M2_MF2_MASK = 9336 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M2_MF4 = 9337 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M2_MF4_MASK = 9338 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M4_M1 = 9339 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M4_M1_MASK = 9340 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M4_M2 = 9341 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M4_M2_MASK = 9342 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M4_MF2 = 9343 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M4_MF2_MASK = 9344 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M8_M1 = 9345 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M8_M1_MASK = 9346 , LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M8_M2 = 9347 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI64_V_M8_M2_MASK = 9348 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_M1_M1 = 9349 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_M1_M1_MASK = 9350 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_M1_M2 = 9351 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_M1_M2_MASK = 9352 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_M2_M2 = 9353 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_M2_M2_MASK = 9354 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF2_M1 = 9355 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF2_M1_MASK = 9356 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF2_M2 = 9357 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF2_M2_MASK = 9358 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF2_MF2 = 9359 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF2_MF2_MASK = 9360 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF4_M1 = 9361 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF4_M1_MASK = 9362 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF4_M2 = 9363 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF4_M2_MASK = 9364 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF4_MF2 = 9365 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF4_MF2_MASK = 9366 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF4_MF4 = 9367 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF4_MF4_MASK = 9368 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF8_M1 = 9369 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF8_M1_MASK = 9370 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF8_MF2 = 9371 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF8_MF2_MASK = 9372 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF8_MF4 = 9373 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF8_MF4_MASK = 9374 , LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF8_MF8 = 9375 ,
  LIEF::assembly::riscv::PseudoVSOXSEG3EI8_V_MF8_MF8_MASK = 9376 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M1_M1 = 9377 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M1_M1_MASK = 9378 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M1_M2 = 9379 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M1_M2_MASK = 9380 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M1_MF2 = 9381 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M1_MF2_MASK = 9382 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M2_M1 = 9383 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M2_M1_MASK = 9384 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M2_M2 = 9385 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M2_M2_MASK = 9386 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M4_M2 = 9387 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_M4_M2_MASK = 9388 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF2_M1 = 9389 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF2_M1_MASK = 9390 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF2_M2 = 9391 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF2_M2_MASK = 9392 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF2_MF2 = 9393 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF2_MF2_MASK = 9394 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF2_MF4 = 9395 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF2_MF4_MASK = 9396 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF4_M1 = 9397 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF4_M1_MASK = 9398 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF4_MF2 = 9399 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF4_MF2_MASK = 9400 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF4_MF4 = 9401 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF4_MF4_MASK = 9402 , LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF4_MF8 = 9403 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI16_V_MF4_MF8_MASK = 9404 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M1_M1 = 9405 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M1_M1_MASK = 9406 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M1_M2 = 9407 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M1_M2_MASK = 9408 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M1_MF2 = 9409 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M1_MF2_MASK = 9410 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M1_MF4 = 9411 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M1_MF4_MASK = 9412 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M2_M1 = 9413 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M2_M1_MASK = 9414 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M2_M2 = 9415 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M2_M2_MASK = 9416 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M2_MF2 = 9417 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M2_MF2_MASK = 9418 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M4_M1 = 9419 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M4_M1_MASK = 9420 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M4_M2 = 9421 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M4_M2_MASK = 9422 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M8_M2 = 9423 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_M8_M2_MASK = 9424 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_MF2_M1 = 9425 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_MF2_M1_MASK = 9426 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_MF2_MF2 = 9427 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_MF2_MF2_MASK = 9428 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_MF2_MF4 = 9429 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_MF2_MF4_MASK = 9430 , LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_MF2_MF8 = 9431 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI32_V_MF2_MF8_MASK = 9432 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M1_M1 = 9433 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M1_M1_MASK = 9434 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M1_MF2 = 9435 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M1_MF2_MASK = 9436 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M1_MF4 = 9437 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M1_MF4_MASK = 9438 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M1_MF8 = 9439 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M1_MF8_MASK = 9440 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M2_M1 = 9441 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M2_M1_MASK = 9442 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M2_M2 = 9443 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M2_M2_MASK = 9444 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M2_MF2 = 9445 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M2_MF2_MASK = 9446 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M2_MF4 = 9447 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M2_MF4_MASK = 9448 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M4_M1 = 9449 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M4_M1_MASK = 9450 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M4_M2 = 9451 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M4_M2_MASK = 9452 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M4_MF2 = 9453 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M4_MF2_MASK = 9454 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M8_M1 = 9455 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M8_M1_MASK = 9456 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M8_M2 = 9457 , LIEF::assembly::riscv::PseudoVSOXSEG4EI64_V_M8_M2_MASK = 9458 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_M1_M1 = 9459 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_M1_M1_MASK = 9460 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_M1_M2 = 9461 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_M1_M2_MASK = 9462 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_M2_M2 = 9463 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_M2_M2_MASK = 9464 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF2_M1 = 9465 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF2_M1_MASK = 9466 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF2_M2 = 9467 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF2_M2_MASK = 9468 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF2_MF2 = 9469 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF2_MF2_MASK = 9470 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF4_M1 = 9471 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF4_M1_MASK = 9472 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF4_M2 = 9473 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF4_M2_MASK = 9474 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF4_MF2 = 9475 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF4_MF2_MASK = 9476 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF4_MF4 = 9477 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF4_MF4_MASK = 9478 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF8_M1 = 9479 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF8_M1_MASK = 9480 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF8_MF2 = 9481 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF8_MF2_MASK = 9482 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF8_MF4 = 9483 ,
  LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF8_MF4_MASK = 9484 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF8_MF8 = 9485 , LIEF::assembly::riscv::PseudoVSOXSEG4EI8_V_MF8_MF8_MASK = 9486 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_M1_M1 = 9487 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_M1_M1_MASK = 9488 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_M1_MF2 = 9489 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_M1_MF2_MASK = 9490 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_M2_M1 = 9491 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_M2_M1_MASK = 9492 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF2_M1 = 9493 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF2_M1_MASK = 9494 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF2_MF2 = 9495 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF2_MF2_MASK = 9496 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF2_MF4 = 9497 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF2_MF4_MASK = 9498 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF4_M1 = 9499 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF4_M1_MASK = 9500 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF4_MF2 = 9501 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF4_MF2_MASK = 9502 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF4_MF4 = 9503 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF4_MF4_MASK = 9504 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF4_MF8 = 9505 , LIEF::assembly::riscv::PseudoVSOXSEG5EI16_V_MF4_MF8_MASK = 9506 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M1_M1 = 9507 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M1_M1_MASK = 9508 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M1_MF2 = 9509 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M1_MF2_MASK = 9510 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M1_MF4 = 9511 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M1_MF4_MASK = 9512 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M2_M1 = 9513 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M2_M1_MASK = 9514 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M2_MF2 = 9515 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M2_MF2_MASK = 9516 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M4_M1 = 9517 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_M4_M1_MASK = 9518 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_MF2_M1 = 9519 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_MF2_M1_MASK = 9520 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_MF2_MF2 = 9521 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_MF2_MF2_MASK = 9522 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_MF2_MF4 = 9523 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_MF2_MF4_MASK = 9524 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_MF2_MF8 = 9525 , LIEF::assembly::riscv::PseudoVSOXSEG5EI32_V_MF2_MF8_MASK = 9526 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M1_M1 = 9527 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M1_M1_MASK = 9528 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M1_MF2 = 9529 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M1_MF2_MASK = 9530 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M1_MF4 = 9531 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M1_MF4_MASK = 9532 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M1_MF8 = 9533 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M1_MF8_MASK = 9534 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M2_M1 = 9535 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M2_M1_MASK = 9536 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M2_MF2 = 9537 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M2_MF2_MASK = 9538 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M2_MF4 = 9539 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M2_MF4_MASK = 9540 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M4_M1 = 9541 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M4_M1_MASK = 9542 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M4_MF2 = 9543 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M4_MF2_MASK = 9544 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M8_M1 = 9545 , LIEF::assembly::riscv::PseudoVSOXSEG5EI64_V_M8_M1_MASK = 9546 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_M1_M1 = 9547 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_M1_M1_MASK = 9548 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF2_M1 = 9549 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF2_M1_MASK = 9550 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF2_MF2 = 9551 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF2_MF2_MASK = 9552 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF4_M1 = 9553 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF4_M1_MASK = 9554 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF4_MF2 = 9555 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF4_MF2_MASK = 9556 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF4_MF4 = 9557 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF4_MF4_MASK = 9558 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF8_M1 = 9559 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF8_M1_MASK = 9560 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF8_MF2 = 9561 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF8_MF2_MASK = 9562 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF8_MF4 = 9563 ,
  LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF8_MF4_MASK = 9564 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF8_MF8 = 9565 , LIEF::assembly::riscv::PseudoVSOXSEG5EI8_V_MF8_MF8_MASK = 9566 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_M1_M1 = 9567 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_M1_M1_MASK = 9568 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_M1_MF2 = 9569 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_M1_MF2_MASK = 9570 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_M2_M1 = 9571 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_M2_M1_MASK = 9572 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF2_M1 = 9573 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF2_M1_MASK = 9574 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF2_MF2 = 9575 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF2_MF2_MASK = 9576 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF2_MF4 = 9577 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF2_MF4_MASK = 9578 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF4_M1 = 9579 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF4_M1_MASK = 9580 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF4_MF2 = 9581 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF4_MF2_MASK = 9582 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF4_MF4 = 9583 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF4_MF4_MASK = 9584 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF4_MF8 = 9585 , LIEF::assembly::riscv::PseudoVSOXSEG6EI16_V_MF4_MF8_MASK = 9586 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M1_M1 = 9587 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M1_M1_MASK = 9588 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M1_MF2 = 9589 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M1_MF2_MASK = 9590 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M1_MF4 = 9591 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M1_MF4_MASK = 9592 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M2_M1 = 9593 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M2_M1_MASK = 9594 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M2_MF2 = 9595 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M2_MF2_MASK = 9596 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M4_M1 = 9597 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_M4_M1_MASK = 9598 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_MF2_M1 = 9599 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_MF2_M1_MASK = 9600 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_MF2_MF2 = 9601 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_MF2_MF2_MASK = 9602 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_MF2_MF4 = 9603 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_MF2_MF4_MASK = 9604 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_MF2_MF8 = 9605 , LIEF::assembly::riscv::PseudoVSOXSEG6EI32_V_MF2_MF8_MASK = 9606 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M1_M1 = 9607 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M1_M1_MASK = 9608 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M1_MF2 = 9609 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M1_MF2_MASK = 9610 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M1_MF4 = 9611 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M1_MF4_MASK = 9612 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M1_MF8 = 9613 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M1_MF8_MASK = 9614 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M2_M1 = 9615 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M2_M1_MASK = 9616 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M2_MF2 = 9617 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M2_MF2_MASK = 9618 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M2_MF4 = 9619 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M2_MF4_MASK = 9620 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M4_M1 = 9621 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M4_M1_MASK = 9622 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M4_MF2 = 9623 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M4_MF2_MASK = 9624 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M8_M1 = 9625 , LIEF::assembly::riscv::PseudoVSOXSEG6EI64_V_M8_M1_MASK = 9626 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_M1_M1 = 9627 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_M1_M1_MASK = 9628 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF2_M1 = 9629 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF2_M1_MASK = 9630 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF2_MF2 = 9631 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF2_MF2_MASK = 9632 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF4_M1 = 9633 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF4_M1_MASK = 9634 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF4_MF2 = 9635 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF4_MF2_MASK = 9636 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF4_MF4 = 9637 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF4_MF4_MASK = 9638 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF8_M1 = 9639 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF8_M1_MASK = 9640 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF8_MF2 = 9641 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF8_MF2_MASK = 9642 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF8_MF4 = 9643 ,
  LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF8_MF4_MASK = 9644 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF8_MF8 = 9645 , LIEF::assembly::riscv::PseudoVSOXSEG6EI8_V_MF8_MF8_MASK = 9646 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_M1_M1 = 9647 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_M1_M1_MASK = 9648 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_M1_MF2 = 9649 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_M1_MF2_MASK = 9650 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_M2_M1 = 9651 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_M2_M1_MASK = 9652 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF2_M1 = 9653 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF2_M1_MASK = 9654 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF2_MF2 = 9655 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF2_MF2_MASK = 9656 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF2_MF4 = 9657 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF2_MF4_MASK = 9658 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF4_M1 = 9659 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF4_M1_MASK = 9660 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF4_MF2 = 9661 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF4_MF2_MASK = 9662 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF4_MF4 = 9663 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF4_MF4_MASK = 9664 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF4_MF8 = 9665 , LIEF::assembly::riscv::PseudoVSOXSEG7EI16_V_MF4_MF8_MASK = 9666 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M1_M1 = 9667 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M1_M1_MASK = 9668 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M1_MF2 = 9669 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M1_MF2_MASK = 9670 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M1_MF4 = 9671 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M1_MF4_MASK = 9672 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M2_M1 = 9673 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M2_M1_MASK = 9674 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M2_MF2 = 9675 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M2_MF2_MASK = 9676 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M4_M1 = 9677 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_M4_M1_MASK = 9678 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_MF2_M1 = 9679 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_MF2_M1_MASK = 9680 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_MF2_MF2 = 9681 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_MF2_MF2_MASK = 9682 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_MF2_MF4 = 9683 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_MF2_MF4_MASK = 9684 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_MF2_MF8 = 9685 , LIEF::assembly::riscv::PseudoVSOXSEG7EI32_V_MF2_MF8_MASK = 9686 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M1_M1 = 9687 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M1_M1_MASK = 9688 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M1_MF2 = 9689 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M1_MF2_MASK = 9690 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M1_MF4 = 9691 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M1_MF4_MASK = 9692 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M1_MF8 = 9693 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M1_MF8_MASK = 9694 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M2_M1 = 9695 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M2_M1_MASK = 9696 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M2_MF2 = 9697 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M2_MF2_MASK = 9698 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M2_MF4 = 9699 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M2_MF4_MASK = 9700 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M4_M1 = 9701 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M4_M1_MASK = 9702 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M4_MF2 = 9703 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M4_MF2_MASK = 9704 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M8_M1 = 9705 , LIEF::assembly::riscv::PseudoVSOXSEG7EI64_V_M8_M1_MASK = 9706 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_M1_M1 = 9707 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_M1_M1_MASK = 9708 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF2_M1 = 9709 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF2_M1_MASK = 9710 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF2_MF2 = 9711 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF2_MF2_MASK = 9712 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF4_M1 = 9713 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF4_M1_MASK = 9714 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF4_MF2 = 9715 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF4_MF2_MASK = 9716 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF4_MF4 = 9717 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF4_MF4_MASK = 9718 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF8_M1 = 9719 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF8_M1_MASK = 9720 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF8_MF2 = 9721 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF8_MF2_MASK = 9722 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF8_MF4 = 9723 ,
  LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF8_MF4_MASK = 9724 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF8_MF8 = 9725 , LIEF::assembly::riscv::PseudoVSOXSEG7EI8_V_MF8_MF8_MASK = 9726 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_M1_M1 = 9727 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_M1_M1_MASK = 9728 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_M1_MF2 = 9729 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_M1_MF2_MASK = 9730 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_M2_M1 = 9731 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_M2_M1_MASK = 9732 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF2_M1 = 9733 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF2_M1_MASK = 9734 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF2_MF2 = 9735 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF2_MF2_MASK = 9736 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF2_MF4 = 9737 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF2_MF4_MASK = 9738 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF4_M1 = 9739 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF4_M1_MASK = 9740 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF4_MF2 = 9741 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF4_MF2_MASK = 9742 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF4_MF4 = 9743 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF4_MF4_MASK = 9744 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF4_MF8 = 9745 , LIEF::assembly::riscv::PseudoVSOXSEG8EI16_V_MF4_MF8_MASK = 9746 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M1_M1 = 9747 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M1_M1_MASK = 9748 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M1_MF2 = 9749 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M1_MF2_MASK = 9750 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M1_MF4 = 9751 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M1_MF4_MASK = 9752 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M2_M1 = 9753 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M2_M1_MASK = 9754 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M2_MF2 = 9755 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M2_MF2_MASK = 9756 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M4_M1 = 9757 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_M4_M1_MASK = 9758 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_MF2_M1 = 9759 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_MF2_M1_MASK = 9760 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_MF2_MF2 = 9761 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_MF2_MF2_MASK = 9762 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_MF2_MF4 = 9763 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_MF2_MF4_MASK = 9764 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_MF2_MF8 = 9765 , LIEF::assembly::riscv::PseudoVSOXSEG8EI32_V_MF2_MF8_MASK = 9766 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M1_M1 = 9767 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M1_M1_MASK = 9768 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M1_MF2 = 9769 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M1_MF2_MASK = 9770 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M1_MF4 = 9771 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M1_MF4_MASK = 9772 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M1_MF8 = 9773 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M1_MF8_MASK = 9774 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M2_M1 = 9775 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M2_M1_MASK = 9776 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M2_MF2 = 9777 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M2_MF2_MASK = 9778 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M2_MF4 = 9779 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M2_MF4_MASK = 9780 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M4_M1 = 9781 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M4_M1_MASK = 9782 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M4_MF2 = 9783 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M4_MF2_MASK = 9784 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M8_M1 = 9785 , LIEF::assembly::riscv::PseudoVSOXSEG8EI64_V_M8_M1_MASK = 9786 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_M1_M1 = 9787 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_M1_M1_MASK = 9788 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF2_M1 = 9789 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF2_M1_MASK = 9790 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF2_MF2 = 9791 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF2_MF2_MASK = 9792 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF4_M1 = 9793 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF4_M1_MASK = 9794 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF4_MF2 = 9795 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF4_MF2_MASK = 9796 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF4_MF4 = 9797 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF4_MF4_MASK = 9798 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF8_M1 = 9799 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF8_M1_MASK = 9800 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF8_MF2 = 9801 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF8_MF2_MASK = 9802 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF8_MF4 = 9803 ,
  LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF8_MF4_MASK = 9804 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF8_MF8 = 9805 , LIEF::assembly::riscv::PseudoVSOXSEG8EI8_V_MF8_MF8_MASK = 9806 , LIEF::assembly::riscv::PseudoVSPILL2_M1 = 9807 ,
  LIEF::assembly::riscv::PseudoVSPILL2_M2 = 9808 , LIEF::assembly::riscv::PseudoVSPILL2_M4 = 9809 , LIEF::assembly::riscv::PseudoVSPILL2_MF2 = 9810 , LIEF::assembly::riscv::PseudoVSPILL2_MF4 = 9811 ,
  LIEF::assembly::riscv::PseudoVSPILL2_MF8 = 9812 , LIEF::assembly::riscv::PseudoVSPILL3_M1 = 9813 , LIEF::assembly::riscv::PseudoVSPILL3_M2 = 9814 , LIEF::assembly::riscv::PseudoVSPILL3_MF2 = 9815 ,
  LIEF::assembly::riscv::PseudoVSPILL3_MF4 = 9816 , LIEF::assembly::riscv::PseudoVSPILL3_MF8 = 9817 , LIEF::assembly::riscv::PseudoVSPILL4_M1 = 9818 , LIEF::assembly::riscv::PseudoVSPILL4_M2 = 9819 ,
  LIEF::assembly::riscv::PseudoVSPILL4_MF2 = 9820 , LIEF::assembly::riscv::PseudoVSPILL4_MF4 = 9821 , LIEF::assembly::riscv::PseudoVSPILL4_MF8 = 9822 , LIEF::assembly::riscv::PseudoVSPILL5_M1 = 9823 ,
  LIEF::assembly::riscv::PseudoVSPILL5_MF2 = 9824 , LIEF::assembly::riscv::PseudoVSPILL5_MF4 = 9825 , LIEF::assembly::riscv::PseudoVSPILL5_MF8 = 9826 , LIEF::assembly::riscv::PseudoVSPILL6_M1 = 9827 ,
  LIEF::assembly::riscv::PseudoVSPILL6_MF2 = 9828 , LIEF::assembly::riscv::PseudoVSPILL6_MF4 = 9829 , LIEF::assembly::riscv::PseudoVSPILL6_MF8 = 9830 , LIEF::assembly::riscv::PseudoVSPILL7_M1 = 9831 ,
  LIEF::assembly::riscv::PseudoVSPILL7_MF2 = 9832 , LIEF::assembly::riscv::PseudoVSPILL7_MF4 = 9833 , LIEF::assembly::riscv::PseudoVSPILL7_MF8 = 9834 , LIEF::assembly::riscv::PseudoVSPILL8_M1 = 9835 ,
  LIEF::assembly::riscv::PseudoVSPILL8_MF2 = 9836 , LIEF::assembly::riscv::PseudoVSPILL8_MF4 = 9837 , LIEF::assembly::riscv::PseudoVSPILL8_MF8 = 9838 , LIEF::assembly::riscv::PseudoVSRA_VI_M1 = 9839 ,
  LIEF::assembly::riscv::PseudoVSRA_VI_M1_MASK = 9840 , LIEF::assembly::riscv::PseudoVSRA_VI_M2 = 9841 , LIEF::assembly::riscv::PseudoVSRA_VI_M2_MASK = 9842 , LIEF::assembly::riscv::PseudoVSRA_VI_M4 = 9843 ,
  LIEF::assembly::riscv::PseudoVSRA_VI_M4_MASK = 9844 , LIEF::assembly::riscv::PseudoVSRA_VI_M8 = 9845 , LIEF::assembly::riscv::PseudoVSRA_VI_M8_MASK = 9846 , LIEF::assembly::riscv::PseudoVSRA_VI_MF2 = 9847 ,
  LIEF::assembly::riscv::PseudoVSRA_VI_MF2_MASK = 9848 , LIEF::assembly::riscv::PseudoVSRA_VI_MF4 = 9849 , LIEF::assembly::riscv::PseudoVSRA_VI_MF4_MASK = 9850 , LIEF::assembly::riscv::PseudoVSRA_VI_MF8 = 9851 ,
  LIEF::assembly::riscv::PseudoVSRA_VI_MF8_MASK = 9852 , LIEF::assembly::riscv::PseudoVSRA_VV_M1 = 9853 , LIEF::assembly::riscv::PseudoVSRA_VV_M1_MASK = 9854 , LIEF::assembly::riscv::PseudoVSRA_VV_M2 = 9855 ,
  LIEF::assembly::riscv::PseudoVSRA_VV_M2_MASK = 9856 , LIEF::assembly::riscv::PseudoVSRA_VV_M4 = 9857 , LIEF::assembly::riscv::PseudoVSRA_VV_M4_MASK = 9858 , LIEF::assembly::riscv::PseudoVSRA_VV_M8 = 9859 ,
  LIEF::assembly::riscv::PseudoVSRA_VV_M8_MASK = 9860 , LIEF::assembly::riscv::PseudoVSRA_VV_MF2 = 9861 , LIEF::assembly::riscv::PseudoVSRA_VV_MF2_MASK = 9862 , LIEF::assembly::riscv::PseudoVSRA_VV_MF4 = 9863 ,
  LIEF::assembly::riscv::PseudoVSRA_VV_MF4_MASK = 9864 , LIEF::assembly::riscv::PseudoVSRA_VV_MF8 = 9865 , LIEF::assembly::riscv::PseudoVSRA_VV_MF8_MASK = 9866 , LIEF::assembly::riscv::PseudoVSRA_VX_M1 = 9867 ,
  LIEF::assembly::riscv::PseudoVSRA_VX_M1_MASK = 9868 , LIEF::assembly::riscv::PseudoVSRA_VX_M2 = 9869 , LIEF::assembly::riscv::PseudoVSRA_VX_M2_MASK = 9870 , LIEF::assembly::riscv::PseudoVSRA_VX_M4 = 9871 ,
  LIEF::assembly::riscv::PseudoVSRA_VX_M4_MASK = 9872 , LIEF::assembly::riscv::PseudoVSRA_VX_M8 = 9873 , LIEF::assembly::riscv::PseudoVSRA_VX_M8_MASK = 9874 , LIEF::assembly::riscv::PseudoVSRA_VX_MF2 = 9875 ,
  LIEF::assembly::riscv::PseudoVSRA_VX_MF2_MASK = 9876 , LIEF::assembly::riscv::PseudoVSRA_VX_MF4 = 9877 , LIEF::assembly::riscv::PseudoVSRA_VX_MF4_MASK = 9878 , LIEF::assembly::riscv::PseudoVSRA_VX_MF8 = 9879 ,
  LIEF::assembly::riscv::PseudoVSRA_VX_MF8_MASK = 9880 , LIEF::assembly::riscv::PseudoVSRL_VI_M1 = 9881 , LIEF::assembly::riscv::PseudoVSRL_VI_M1_MASK = 9882 , LIEF::assembly::riscv::PseudoVSRL_VI_M2 = 9883 ,
  LIEF::assembly::riscv::PseudoVSRL_VI_M2_MASK = 9884 , LIEF::assembly::riscv::PseudoVSRL_VI_M4 = 9885 , LIEF::assembly::riscv::PseudoVSRL_VI_M4_MASK = 9886 , LIEF::assembly::riscv::PseudoVSRL_VI_M8 = 9887 ,
  LIEF::assembly::riscv::PseudoVSRL_VI_M8_MASK = 9888 , LIEF::assembly::riscv::PseudoVSRL_VI_MF2 = 9889 , LIEF::assembly::riscv::PseudoVSRL_VI_MF2_MASK = 9890 , LIEF::assembly::riscv::PseudoVSRL_VI_MF4 = 9891 ,
  LIEF::assembly::riscv::PseudoVSRL_VI_MF4_MASK = 9892 , LIEF::assembly::riscv::PseudoVSRL_VI_MF8 = 9893 , LIEF::assembly::riscv::PseudoVSRL_VI_MF8_MASK = 9894 , LIEF::assembly::riscv::PseudoVSRL_VV_M1 = 9895 ,
  LIEF::assembly::riscv::PseudoVSRL_VV_M1_MASK = 9896 , LIEF::assembly::riscv::PseudoVSRL_VV_M2 = 9897 , LIEF::assembly::riscv::PseudoVSRL_VV_M2_MASK = 9898 , LIEF::assembly::riscv::PseudoVSRL_VV_M4 = 9899 ,
  LIEF::assembly::riscv::PseudoVSRL_VV_M4_MASK = 9900 , LIEF::assembly::riscv::PseudoVSRL_VV_M8 = 9901 , LIEF::assembly::riscv::PseudoVSRL_VV_M8_MASK = 9902 , LIEF::assembly::riscv::PseudoVSRL_VV_MF2 = 9903 ,
  LIEF::assembly::riscv::PseudoVSRL_VV_MF2_MASK = 9904 , LIEF::assembly::riscv::PseudoVSRL_VV_MF4 = 9905 , LIEF::assembly::riscv::PseudoVSRL_VV_MF4_MASK = 9906 , LIEF::assembly::riscv::PseudoVSRL_VV_MF8 = 9907 ,
  LIEF::assembly::riscv::PseudoVSRL_VV_MF8_MASK = 9908 , LIEF::assembly::riscv::PseudoVSRL_VX_M1 = 9909 , LIEF::assembly::riscv::PseudoVSRL_VX_M1_MASK = 9910 , LIEF::assembly::riscv::PseudoVSRL_VX_M2 = 9911 ,
  LIEF::assembly::riscv::PseudoVSRL_VX_M2_MASK = 9912 , LIEF::assembly::riscv::PseudoVSRL_VX_M4 = 9913 , LIEF::assembly::riscv::PseudoVSRL_VX_M4_MASK = 9914 , LIEF::assembly::riscv::PseudoVSRL_VX_M8 = 9915 ,
  LIEF::assembly::riscv::PseudoVSRL_VX_M8_MASK = 9916 , LIEF::assembly::riscv::PseudoVSRL_VX_MF2 = 9917 , LIEF::assembly::riscv::PseudoVSRL_VX_MF2_MASK = 9918 , LIEF::assembly::riscv::PseudoVSRL_VX_MF4 = 9919 ,
  LIEF::assembly::riscv::PseudoVSRL_VX_MF4_MASK = 9920 , LIEF::assembly::riscv::PseudoVSRL_VX_MF8 = 9921 , LIEF::assembly::riscv::PseudoVSRL_VX_MF8_MASK = 9922 , LIEF::assembly::riscv::PseudoVSSE16_V_M1 = 9923 ,
  LIEF::assembly::riscv::PseudoVSSE16_V_M1_MASK = 9924 , LIEF::assembly::riscv::PseudoVSSE16_V_M2 = 9925 , LIEF::assembly::riscv::PseudoVSSE16_V_M2_MASK = 9926 , LIEF::assembly::riscv::PseudoVSSE16_V_M4 = 9927 ,
  LIEF::assembly::riscv::PseudoVSSE16_V_M4_MASK = 9928 , LIEF::assembly::riscv::PseudoVSSE16_V_M8 = 9929 , LIEF::assembly::riscv::PseudoVSSE16_V_M8_MASK = 9930 , LIEF::assembly::riscv::PseudoVSSE16_V_MF2 = 9931 ,
  LIEF::assembly::riscv::PseudoVSSE16_V_MF2_MASK = 9932 , LIEF::assembly::riscv::PseudoVSSE16_V_MF4 = 9933 , LIEF::assembly::riscv::PseudoVSSE16_V_MF4_MASK = 9934 , LIEF::assembly::riscv::PseudoVSSE32_V_M1 = 9935 ,
  LIEF::assembly::riscv::PseudoVSSE32_V_M1_MASK = 9936 , LIEF::assembly::riscv::PseudoVSSE32_V_M2 = 9937 , LIEF::assembly::riscv::PseudoVSSE32_V_M2_MASK = 9938 , LIEF::assembly::riscv::PseudoVSSE32_V_M4 = 9939 ,
  LIEF::assembly::riscv::PseudoVSSE32_V_M4_MASK = 9940 , LIEF::assembly::riscv::PseudoVSSE32_V_M8 = 9941 , LIEF::assembly::riscv::PseudoVSSE32_V_M8_MASK = 9942 , LIEF::assembly::riscv::PseudoVSSE32_V_MF2 = 9943 ,
  LIEF::assembly::riscv::PseudoVSSE32_V_MF2_MASK = 9944 , LIEF::assembly::riscv::PseudoVSSE64_V_M1 = 9945 , LIEF::assembly::riscv::PseudoVSSE64_V_M1_MASK = 9946 , LIEF::assembly::riscv::PseudoVSSE64_V_M2 = 9947 ,
  LIEF::assembly::riscv::PseudoVSSE64_V_M2_MASK = 9948 , LIEF::assembly::riscv::PseudoVSSE64_V_M4 = 9949 , LIEF::assembly::riscv::PseudoVSSE64_V_M4_MASK = 9950 , LIEF::assembly::riscv::PseudoVSSE64_V_M8 = 9951 ,
  LIEF::assembly::riscv::PseudoVSSE64_V_M8_MASK = 9952 , LIEF::assembly::riscv::PseudoVSSE8_V_M1 = 9953 , LIEF::assembly::riscv::PseudoVSSE8_V_M1_MASK = 9954 , LIEF::assembly::riscv::PseudoVSSE8_V_M2 = 9955 ,
  LIEF::assembly::riscv::PseudoVSSE8_V_M2_MASK = 9956 , LIEF::assembly::riscv::PseudoVSSE8_V_M4 = 9957 , LIEF::assembly::riscv::PseudoVSSE8_V_M4_MASK = 9958 , LIEF::assembly::riscv::PseudoVSSE8_V_M8 = 9959 ,
  LIEF::assembly::riscv::PseudoVSSE8_V_M8_MASK = 9960 , LIEF::assembly::riscv::PseudoVSSE8_V_MF2 = 9961 , LIEF::assembly::riscv::PseudoVSSE8_V_MF2_MASK = 9962 , LIEF::assembly::riscv::PseudoVSSE8_V_MF4 = 9963 ,
  LIEF::assembly::riscv::PseudoVSSE8_V_MF4_MASK = 9964 , LIEF::assembly::riscv::PseudoVSSE8_V_MF8 = 9965 , LIEF::assembly::riscv::PseudoVSSE8_V_MF8_MASK = 9966 , LIEF::assembly::riscv::PseudoVSSEG2E16_V_M1 = 9967 ,
  LIEF::assembly::riscv::PseudoVSSEG2E16_V_M1_MASK = 9968 , LIEF::assembly::riscv::PseudoVSSEG2E16_V_M2 = 9969 , LIEF::assembly::riscv::PseudoVSSEG2E16_V_M2_MASK = 9970 , LIEF::assembly::riscv::PseudoVSSEG2E16_V_M4 = 9971 ,
  LIEF::assembly::riscv::PseudoVSSEG2E16_V_M4_MASK = 9972 , LIEF::assembly::riscv::PseudoVSSEG2E16_V_MF2 = 9973 , LIEF::assembly::riscv::PseudoVSSEG2E16_V_MF2_MASK = 9974 , LIEF::assembly::riscv::PseudoVSSEG2E16_V_MF4 = 9975 ,
  LIEF::assembly::riscv::PseudoVSSEG2E16_V_MF4_MASK = 9976 , LIEF::assembly::riscv::PseudoVSSEG2E32_V_M1 = 9977 , LIEF::assembly::riscv::PseudoVSSEG2E32_V_M1_MASK = 9978 , LIEF::assembly::riscv::PseudoVSSEG2E32_V_M2 = 9979 ,
  LIEF::assembly::riscv::PseudoVSSEG2E32_V_M2_MASK = 9980 , LIEF::assembly::riscv::PseudoVSSEG2E32_V_M4 = 9981 , LIEF::assembly::riscv::PseudoVSSEG2E32_V_M4_MASK = 9982 , LIEF::assembly::riscv::PseudoVSSEG2E32_V_MF2 = 9983 ,
  LIEF::assembly::riscv::PseudoVSSEG2E32_V_MF2_MASK = 9984 , LIEF::assembly::riscv::PseudoVSSEG2E64_V_M1 = 9985 , LIEF::assembly::riscv::PseudoVSSEG2E64_V_M1_MASK = 9986 , LIEF::assembly::riscv::PseudoVSSEG2E64_V_M2 = 9987 ,
  LIEF::assembly::riscv::PseudoVSSEG2E64_V_M2_MASK = 9988 , LIEF::assembly::riscv::PseudoVSSEG2E64_V_M4 = 9989 , LIEF::assembly::riscv::PseudoVSSEG2E64_V_M4_MASK = 9990 , LIEF::assembly::riscv::PseudoVSSEG2E8_V_M1 = 9991 ,
  LIEF::assembly::riscv::PseudoVSSEG2E8_V_M1_MASK = 9992 , LIEF::assembly::riscv::PseudoVSSEG2E8_V_M2 = 9993 , LIEF::assembly::riscv::PseudoVSSEG2E8_V_M2_MASK = 9994 , LIEF::assembly::riscv::PseudoVSSEG2E8_V_M4 = 9995 ,
  LIEF::assembly::riscv::PseudoVSSEG2E8_V_M4_MASK = 9996 , LIEF::assembly::riscv::PseudoVSSEG2E8_V_MF2 = 9997 , LIEF::assembly::riscv::PseudoVSSEG2E8_V_MF2_MASK = 9998 , LIEF::assembly::riscv::PseudoVSSEG2E8_V_MF4 = 9999 ,
  LIEF::assembly::riscv::PseudoVSSEG2E8_V_MF4_MASK = 10000 , LIEF::assembly::riscv::PseudoVSSEG2E8_V_MF8 = 10001 , LIEF::assembly::riscv::PseudoVSSEG2E8_V_MF8_MASK = 10002 , LIEF::assembly::riscv::PseudoVSSEG3E16_V_M1 = 10003 ,
  LIEF::assembly::riscv::PseudoVSSEG3E16_V_M1_MASK = 10004 , LIEF::assembly::riscv::PseudoVSSEG3E16_V_M2 = 10005 , LIEF::assembly::riscv::PseudoVSSEG3E16_V_M2_MASK = 10006 , LIEF::assembly::riscv::PseudoVSSEG3E16_V_MF2 = 10007 ,
  LIEF::assembly::riscv::PseudoVSSEG3E16_V_MF2_MASK = 10008 , LIEF::assembly::riscv::PseudoVSSEG3E16_V_MF4 = 10009 , LIEF::assembly::riscv::PseudoVSSEG3E16_V_MF4_MASK = 10010 , LIEF::assembly::riscv::PseudoVSSEG3E32_V_M1 = 10011 ,
  LIEF::assembly::riscv::PseudoVSSEG3E32_V_M1_MASK = 10012 , LIEF::assembly::riscv::PseudoVSSEG3E32_V_M2 = 10013 , LIEF::assembly::riscv::PseudoVSSEG3E32_V_M2_MASK = 10014 , LIEF::assembly::riscv::PseudoVSSEG3E32_V_MF2 = 10015 ,
  LIEF::assembly::riscv::PseudoVSSEG3E32_V_MF2_MASK = 10016 , LIEF::assembly::riscv::PseudoVSSEG3E64_V_M1 = 10017 , LIEF::assembly::riscv::PseudoVSSEG3E64_V_M1_MASK = 10018 , LIEF::assembly::riscv::PseudoVSSEG3E64_V_M2 = 10019 ,
  LIEF::assembly::riscv::PseudoVSSEG3E64_V_M2_MASK = 10020 , LIEF::assembly::riscv::PseudoVSSEG3E8_V_M1 = 10021 , LIEF::assembly::riscv::PseudoVSSEG3E8_V_M1_MASK = 10022 , LIEF::assembly::riscv::PseudoVSSEG3E8_V_M2 = 10023 ,
  LIEF::assembly::riscv::PseudoVSSEG3E8_V_M2_MASK = 10024 , LIEF::assembly::riscv::PseudoVSSEG3E8_V_MF2 = 10025 , LIEF::assembly::riscv::PseudoVSSEG3E8_V_MF2_MASK = 10026 , LIEF::assembly::riscv::PseudoVSSEG3E8_V_MF4 = 10027 ,
  LIEF::assembly::riscv::PseudoVSSEG3E8_V_MF4_MASK = 10028 , LIEF::assembly::riscv::PseudoVSSEG3E8_V_MF8 = 10029 , LIEF::assembly::riscv::PseudoVSSEG3E8_V_MF8_MASK = 10030 , LIEF::assembly::riscv::PseudoVSSEG4E16_V_M1 = 10031 ,
  LIEF::assembly::riscv::PseudoVSSEG4E16_V_M1_MASK = 10032 , LIEF::assembly::riscv::PseudoVSSEG4E16_V_M2 = 10033 , LIEF::assembly::riscv::PseudoVSSEG4E16_V_M2_MASK = 10034 , LIEF::assembly::riscv::PseudoVSSEG4E16_V_MF2 = 10035 ,
  LIEF::assembly::riscv::PseudoVSSEG4E16_V_MF2_MASK = 10036 , LIEF::assembly::riscv::PseudoVSSEG4E16_V_MF4 = 10037 , LIEF::assembly::riscv::PseudoVSSEG4E16_V_MF4_MASK = 10038 , LIEF::assembly::riscv::PseudoVSSEG4E32_V_M1 = 10039 ,
  LIEF::assembly::riscv::PseudoVSSEG4E32_V_M1_MASK = 10040 , LIEF::assembly::riscv::PseudoVSSEG4E32_V_M2 = 10041 , LIEF::assembly::riscv::PseudoVSSEG4E32_V_M2_MASK = 10042 , LIEF::assembly::riscv::PseudoVSSEG4E32_V_MF2 = 10043 ,
  LIEF::assembly::riscv::PseudoVSSEG4E32_V_MF2_MASK = 10044 , LIEF::assembly::riscv::PseudoVSSEG4E64_V_M1 = 10045 , LIEF::assembly::riscv::PseudoVSSEG4E64_V_M1_MASK = 10046 , LIEF::assembly::riscv::PseudoVSSEG4E64_V_M2 = 10047 ,
  LIEF::assembly::riscv::PseudoVSSEG4E64_V_M2_MASK = 10048 , LIEF::assembly::riscv::PseudoVSSEG4E8_V_M1 = 10049 , LIEF::assembly::riscv::PseudoVSSEG4E8_V_M1_MASK = 10050 , LIEF::assembly::riscv::PseudoVSSEG4E8_V_M2 = 10051 ,
  LIEF::assembly::riscv::PseudoVSSEG4E8_V_M2_MASK = 10052 , LIEF::assembly::riscv::PseudoVSSEG4E8_V_MF2 = 10053 , LIEF::assembly::riscv::PseudoVSSEG4E8_V_MF2_MASK = 10054 , LIEF::assembly::riscv::PseudoVSSEG4E8_V_MF4 = 10055 ,
  LIEF::assembly::riscv::PseudoVSSEG4E8_V_MF4_MASK = 10056 , LIEF::assembly::riscv::PseudoVSSEG4E8_V_MF8 = 10057 , LIEF::assembly::riscv::PseudoVSSEG4E8_V_MF8_MASK = 10058 , LIEF::assembly::riscv::PseudoVSSEG5E16_V_M1 = 10059 ,
  LIEF::assembly::riscv::PseudoVSSEG5E16_V_M1_MASK = 10060 , LIEF::assembly::riscv::PseudoVSSEG5E16_V_MF2 = 10061 , LIEF::assembly::riscv::PseudoVSSEG5E16_V_MF2_MASK = 10062 , LIEF::assembly::riscv::PseudoVSSEG5E16_V_MF4 = 10063 ,
  LIEF::assembly::riscv::PseudoVSSEG5E16_V_MF4_MASK = 10064 , LIEF::assembly::riscv::PseudoVSSEG5E32_V_M1 = 10065 , LIEF::assembly::riscv::PseudoVSSEG5E32_V_M1_MASK = 10066 , LIEF::assembly::riscv::PseudoVSSEG5E32_V_MF2 = 10067 ,
  LIEF::assembly::riscv::PseudoVSSEG5E32_V_MF2_MASK = 10068 , LIEF::assembly::riscv::PseudoVSSEG5E64_V_M1 = 10069 , LIEF::assembly::riscv::PseudoVSSEG5E64_V_M1_MASK = 10070 , LIEF::assembly::riscv::PseudoVSSEG5E8_V_M1 = 10071 ,
  LIEF::assembly::riscv::PseudoVSSEG5E8_V_M1_MASK = 10072 , LIEF::assembly::riscv::PseudoVSSEG5E8_V_MF2 = 10073 , LIEF::assembly::riscv::PseudoVSSEG5E8_V_MF2_MASK = 10074 , LIEF::assembly::riscv::PseudoVSSEG5E8_V_MF4 = 10075 ,
  LIEF::assembly::riscv::PseudoVSSEG5E8_V_MF4_MASK = 10076 , LIEF::assembly::riscv::PseudoVSSEG5E8_V_MF8 = 10077 , LIEF::assembly::riscv::PseudoVSSEG5E8_V_MF8_MASK = 10078 , LIEF::assembly::riscv::PseudoVSSEG6E16_V_M1 = 10079 ,
  LIEF::assembly::riscv::PseudoVSSEG6E16_V_M1_MASK = 10080 , LIEF::assembly::riscv::PseudoVSSEG6E16_V_MF2 = 10081 , LIEF::assembly::riscv::PseudoVSSEG6E16_V_MF2_MASK = 10082 , LIEF::assembly::riscv::PseudoVSSEG6E16_V_MF4 = 10083 ,
  LIEF::assembly::riscv::PseudoVSSEG6E16_V_MF4_MASK = 10084 , LIEF::assembly::riscv::PseudoVSSEG6E32_V_M1 = 10085 , LIEF::assembly::riscv::PseudoVSSEG6E32_V_M1_MASK = 10086 , LIEF::assembly::riscv::PseudoVSSEG6E32_V_MF2 = 10087 ,
  LIEF::assembly::riscv::PseudoVSSEG6E32_V_MF2_MASK = 10088 , LIEF::assembly::riscv::PseudoVSSEG6E64_V_M1 = 10089 , LIEF::assembly::riscv::PseudoVSSEG6E64_V_M1_MASK = 10090 , LIEF::assembly::riscv::PseudoVSSEG6E8_V_M1 = 10091 ,
  LIEF::assembly::riscv::PseudoVSSEG6E8_V_M1_MASK = 10092 , LIEF::assembly::riscv::PseudoVSSEG6E8_V_MF2 = 10093 , LIEF::assembly::riscv::PseudoVSSEG6E8_V_MF2_MASK = 10094 , LIEF::assembly::riscv::PseudoVSSEG6E8_V_MF4 = 10095 ,
  LIEF::assembly::riscv::PseudoVSSEG6E8_V_MF4_MASK = 10096 , LIEF::assembly::riscv::PseudoVSSEG6E8_V_MF8 = 10097 , LIEF::assembly::riscv::PseudoVSSEG6E8_V_MF8_MASK = 10098 , LIEF::assembly::riscv::PseudoVSSEG7E16_V_M1 = 10099 ,
  LIEF::assembly::riscv::PseudoVSSEG7E16_V_M1_MASK = 10100 , LIEF::assembly::riscv::PseudoVSSEG7E16_V_MF2 = 10101 , LIEF::assembly::riscv::PseudoVSSEG7E16_V_MF2_MASK = 10102 , LIEF::assembly::riscv::PseudoVSSEG7E16_V_MF4 = 10103 ,
  LIEF::assembly::riscv::PseudoVSSEG7E16_V_MF4_MASK = 10104 , LIEF::assembly::riscv::PseudoVSSEG7E32_V_M1 = 10105 , LIEF::assembly::riscv::PseudoVSSEG7E32_V_M1_MASK = 10106 , LIEF::assembly::riscv::PseudoVSSEG7E32_V_MF2 = 10107 ,
  LIEF::assembly::riscv::PseudoVSSEG7E32_V_MF2_MASK = 10108 , LIEF::assembly::riscv::PseudoVSSEG7E64_V_M1 = 10109 , LIEF::assembly::riscv::PseudoVSSEG7E64_V_M1_MASK = 10110 , LIEF::assembly::riscv::PseudoVSSEG7E8_V_M1 = 10111 ,
  LIEF::assembly::riscv::PseudoVSSEG7E8_V_M1_MASK = 10112 , LIEF::assembly::riscv::PseudoVSSEG7E8_V_MF2 = 10113 , LIEF::assembly::riscv::PseudoVSSEG7E8_V_MF2_MASK = 10114 , LIEF::assembly::riscv::PseudoVSSEG7E8_V_MF4 = 10115 ,
  LIEF::assembly::riscv::PseudoVSSEG7E8_V_MF4_MASK = 10116 , LIEF::assembly::riscv::PseudoVSSEG7E8_V_MF8 = 10117 , LIEF::assembly::riscv::PseudoVSSEG7E8_V_MF8_MASK = 10118 , LIEF::assembly::riscv::PseudoVSSEG8E16_V_M1 = 10119 ,
  LIEF::assembly::riscv::PseudoVSSEG8E16_V_M1_MASK = 10120 , LIEF::assembly::riscv::PseudoVSSEG8E16_V_MF2 = 10121 , LIEF::assembly::riscv::PseudoVSSEG8E16_V_MF2_MASK = 10122 , LIEF::assembly::riscv::PseudoVSSEG8E16_V_MF4 = 10123 ,
  LIEF::assembly::riscv::PseudoVSSEG8E16_V_MF4_MASK = 10124 , LIEF::assembly::riscv::PseudoVSSEG8E32_V_M1 = 10125 , LIEF::assembly::riscv::PseudoVSSEG8E32_V_M1_MASK = 10126 , LIEF::assembly::riscv::PseudoVSSEG8E32_V_MF2 = 10127 ,
  LIEF::assembly::riscv::PseudoVSSEG8E32_V_MF2_MASK = 10128 , LIEF::assembly::riscv::PseudoVSSEG8E64_V_M1 = 10129 , LIEF::assembly::riscv::PseudoVSSEG8E64_V_M1_MASK = 10130 , LIEF::assembly::riscv::PseudoVSSEG8E8_V_M1 = 10131 ,
  LIEF::assembly::riscv::PseudoVSSEG8E8_V_M1_MASK = 10132 , LIEF::assembly::riscv::PseudoVSSEG8E8_V_MF2 = 10133 , LIEF::assembly::riscv::PseudoVSSEG8E8_V_MF2_MASK = 10134 , LIEF::assembly::riscv::PseudoVSSEG8E8_V_MF4 = 10135 ,
  LIEF::assembly::riscv::PseudoVSSEG8E8_V_MF4_MASK = 10136 , LIEF::assembly::riscv::PseudoVSSEG8E8_V_MF8 = 10137 , LIEF::assembly::riscv::PseudoVSSEG8E8_V_MF8_MASK = 10138 , LIEF::assembly::riscv::PseudoVSSRA_VI_M1 = 10139 ,
  LIEF::assembly::riscv::PseudoVSSRA_VI_M1_MASK = 10140 , LIEF::assembly::riscv::PseudoVSSRA_VI_M2 = 10141 , LIEF::assembly::riscv::PseudoVSSRA_VI_M2_MASK = 10142 , LIEF::assembly::riscv::PseudoVSSRA_VI_M4 = 10143 ,
  LIEF::assembly::riscv::PseudoVSSRA_VI_M4_MASK = 10144 , LIEF::assembly::riscv::PseudoVSSRA_VI_M8 = 10145 , LIEF::assembly::riscv::PseudoVSSRA_VI_M8_MASK = 10146 , LIEF::assembly::riscv::PseudoVSSRA_VI_MF2 = 10147 ,
  LIEF::assembly::riscv::PseudoVSSRA_VI_MF2_MASK = 10148 , LIEF::assembly::riscv::PseudoVSSRA_VI_MF4 = 10149 , LIEF::assembly::riscv::PseudoVSSRA_VI_MF4_MASK = 10150 , LIEF::assembly::riscv::PseudoVSSRA_VI_MF8 = 10151 ,
  LIEF::assembly::riscv::PseudoVSSRA_VI_MF8_MASK = 10152 , LIEF::assembly::riscv::PseudoVSSRA_VV_M1 = 10153 , LIEF::assembly::riscv::PseudoVSSRA_VV_M1_MASK = 10154 , LIEF::assembly::riscv::PseudoVSSRA_VV_M2 = 10155 ,
  LIEF::assembly::riscv::PseudoVSSRA_VV_M2_MASK = 10156 , LIEF::assembly::riscv::PseudoVSSRA_VV_M4 = 10157 , LIEF::assembly::riscv::PseudoVSSRA_VV_M4_MASK = 10158 , LIEF::assembly::riscv::PseudoVSSRA_VV_M8 = 10159 ,
  LIEF::assembly::riscv::PseudoVSSRA_VV_M8_MASK = 10160 , LIEF::assembly::riscv::PseudoVSSRA_VV_MF2 = 10161 , LIEF::assembly::riscv::PseudoVSSRA_VV_MF2_MASK = 10162 , LIEF::assembly::riscv::PseudoVSSRA_VV_MF4 = 10163 ,
  LIEF::assembly::riscv::PseudoVSSRA_VV_MF4_MASK = 10164 , LIEF::assembly::riscv::PseudoVSSRA_VV_MF8 = 10165 , LIEF::assembly::riscv::PseudoVSSRA_VV_MF8_MASK = 10166 , LIEF::assembly::riscv::PseudoVSSRA_VX_M1 = 10167 ,
  LIEF::assembly::riscv::PseudoVSSRA_VX_M1_MASK = 10168 , LIEF::assembly::riscv::PseudoVSSRA_VX_M2 = 10169 , LIEF::assembly::riscv::PseudoVSSRA_VX_M2_MASK = 10170 , LIEF::assembly::riscv::PseudoVSSRA_VX_M4 = 10171 ,
  LIEF::assembly::riscv::PseudoVSSRA_VX_M4_MASK = 10172 , LIEF::assembly::riscv::PseudoVSSRA_VX_M8 = 10173 , LIEF::assembly::riscv::PseudoVSSRA_VX_M8_MASK = 10174 , LIEF::assembly::riscv::PseudoVSSRA_VX_MF2 = 10175 ,
  LIEF::assembly::riscv::PseudoVSSRA_VX_MF2_MASK = 10176 , LIEF::assembly::riscv::PseudoVSSRA_VX_MF4 = 10177 , LIEF::assembly::riscv::PseudoVSSRA_VX_MF4_MASK = 10178 , LIEF::assembly::riscv::PseudoVSSRA_VX_MF8 = 10179 ,
  LIEF::assembly::riscv::PseudoVSSRA_VX_MF8_MASK = 10180 , LIEF::assembly::riscv::PseudoVSSRL_VI_M1 = 10181 , LIEF::assembly::riscv::PseudoVSSRL_VI_M1_MASK = 10182 , LIEF::assembly::riscv::PseudoVSSRL_VI_M2 = 10183 ,
  LIEF::assembly::riscv::PseudoVSSRL_VI_M2_MASK = 10184 , LIEF::assembly::riscv::PseudoVSSRL_VI_M4 = 10185 , LIEF::assembly::riscv::PseudoVSSRL_VI_M4_MASK = 10186 , LIEF::assembly::riscv::PseudoVSSRL_VI_M8 = 10187 ,
  LIEF::assembly::riscv::PseudoVSSRL_VI_M8_MASK = 10188 , LIEF::assembly::riscv::PseudoVSSRL_VI_MF2 = 10189 , LIEF::assembly::riscv::PseudoVSSRL_VI_MF2_MASK = 10190 , LIEF::assembly::riscv::PseudoVSSRL_VI_MF4 = 10191 ,
  LIEF::assembly::riscv::PseudoVSSRL_VI_MF4_MASK = 10192 , LIEF::assembly::riscv::PseudoVSSRL_VI_MF8 = 10193 , LIEF::assembly::riscv::PseudoVSSRL_VI_MF8_MASK = 10194 , LIEF::assembly::riscv::PseudoVSSRL_VV_M1 = 10195 ,
  LIEF::assembly::riscv::PseudoVSSRL_VV_M1_MASK = 10196 , LIEF::assembly::riscv::PseudoVSSRL_VV_M2 = 10197 , LIEF::assembly::riscv::PseudoVSSRL_VV_M2_MASK = 10198 , LIEF::assembly::riscv::PseudoVSSRL_VV_M4 = 10199 ,
  LIEF::assembly::riscv::PseudoVSSRL_VV_M4_MASK = 10200 , LIEF::assembly::riscv::PseudoVSSRL_VV_M8 = 10201 , LIEF::assembly::riscv::PseudoVSSRL_VV_M8_MASK = 10202 , LIEF::assembly::riscv::PseudoVSSRL_VV_MF2 = 10203 ,
  LIEF::assembly::riscv::PseudoVSSRL_VV_MF2_MASK = 10204 , LIEF::assembly::riscv::PseudoVSSRL_VV_MF4 = 10205 , LIEF::assembly::riscv::PseudoVSSRL_VV_MF4_MASK = 10206 , LIEF::assembly::riscv::PseudoVSSRL_VV_MF8 = 10207 ,
  LIEF::assembly::riscv::PseudoVSSRL_VV_MF8_MASK = 10208 , LIEF::assembly::riscv::PseudoVSSRL_VX_M1 = 10209 , LIEF::assembly::riscv::PseudoVSSRL_VX_M1_MASK = 10210 , LIEF::assembly::riscv::PseudoVSSRL_VX_M2 = 10211 ,
  LIEF::assembly::riscv::PseudoVSSRL_VX_M2_MASK = 10212 , LIEF::assembly::riscv::PseudoVSSRL_VX_M4 = 10213 , LIEF::assembly::riscv::PseudoVSSRL_VX_M4_MASK = 10214 , LIEF::assembly::riscv::PseudoVSSRL_VX_M8 = 10215 ,
  LIEF::assembly::riscv::PseudoVSSRL_VX_M8_MASK = 10216 , LIEF::assembly::riscv::PseudoVSSRL_VX_MF2 = 10217 , LIEF::assembly::riscv::PseudoVSSRL_VX_MF2_MASK = 10218 , LIEF::assembly::riscv::PseudoVSSRL_VX_MF4 = 10219 ,
  LIEF::assembly::riscv::PseudoVSSRL_VX_MF4_MASK = 10220 , LIEF::assembly::riscv::PseudoVSSRL_VX_MF8 = 10221 , LIEF::assembly::riscv::PseudoVSSRL_VX_MF8_MASK = 10222 , LIEF::assembly::riscv::PseudoVSSSEG2E16_V_M1 = 10223 ,
  LIEF::assembly::riscv::PseudoVSSSEG2E16_V_M1_MASK = 10224 , LIEF::assembly::riscv::PseudoVSSSEG2E16_V_M2 = 10225 , LIEF::assembly::riscv::PseudoVSSSEG2E16_V_M2_MASK = 10226 , LIEF::assembly::riscv::PseudoVSSSEG2E16_V_M4 = 10227 ,
  LIEF::assembly::riscv::PseudoVSSSEG2E16_V_M4_MASK = 10228 , LIEF::assembly::riscv::PseudoVSSSEG2E16_V_MF2 = 10229 , LIEF::assembly::riscv::PseudoVSSSEG2E16_V_MF2_MASK = 10230 , LIEF::assembly::riscv::PseudoVSSSEG2E16_V_MF4 = 10231 ,
  LIEF::assembly::riscv::PseudoVSSSEG2E16_V_MF4_MASK = 10232 , LIEF::assembly::riscv::PseudoVSSSEG2E32_V_M1 = 10233 , LIEF::assembly::riscv::PseudoVSSSEG2E32_V_M1_MASK = 10234 , LIEF::assembly::riscv::PseudoVSSSEG2E32_V_M2 = 10235 ,
  LIEF::assembly::riscv::PseudoVSSSEG2E32_V_M2_MASK = 10236 , LIEF::assembly::riscv::PseudoVSSSEG2E32_V_M4 = 10237 , LIEF::assembly::riscv::PseudoVSSSEG2E32_V_M4_MASK = 10238 , LIEF::assembly::riscv::PseudoVSSSEG2E32_V_MF2 = 10239 ,
  LIEF::assembly::riscv::PseudoVSSSEG2E32_V_MF2_MASK = 10240 , LIEF::assembly::riscv::PseudoVSSSEG2E64_V_M1 = 10241 , LIEF::assembly::riscv::PseudoVSSSEG2E64_V_M1_MASK = 10242 , LIEF::assembly::riscv::PseudoVSSSEG2E64_V_M2 = 10243 ,
  LIEF::assembly::riscv::PseudoVSSSEG2E64_V_M2_MASK = 10244 , LIEF::assembly::riscv::PseudoVSSSEG2E64_V_M4 = 10245 , LIEF::assembly::riscv::PseudoVSSSEG2E64_V_M4_MASK = 10246 , LIEF::assembly::riscv::PseudoVSSSEG2E8_V_M1 = 10247 ,
  LIEF::assembly::riscv::PseudoVSSSEG2E8_V_M1_MASK = 10248 , LIEF::assembly::riscv::PseudoVSSSEG2E8_V_M2 = 10249 , LIEF::assembly::riscv::PseudoVSSSEG2E8_V_M2_MASK = 10250 , LIEF::assembly::riscv::PseudoVSSSEG2E8_V_M4 = 10251 ,
  LIEF::assembly::riscv::PseudoVSSSEG2E8_V_M4_MASK = 10252 , LIEF::assembly::riscv::PseudoVSSSEG2E8_V_MF2 = 10253 , LIEF::assembly::riscv::PseudoVSSSEG2E8_V_MF2_MASK = 10254 , LIEF::assembly::riscv::PseudoVSSSEG2E8_V_MF4 = 10255 ,
  LIEF::assembly::riscv::PseudoVSSSEG2E8_V_MF4_MASK = 10256 , LIEF::assembly::riscv::PseudoVSSSEG2E8_V_MF8 = 10257 , LIEF::assembly::riscv::PseudoVSSSEG2E8_V_MF8_MASK = 10258 , LIEF::assembly::riscv::PseudoVSSSEG3E16_V_M1 = 10259 ,
  LIEF::assembly::riscv::PseudoVSSSEG3E16_V_M1_MASK = 10260 , LIEF::assembly::riscv::PseudoVSSSEG3E16_V_M2 = 10261 , LIEF::assembly::riscv::PseudoVSSSEG3E16_V_M2_MASK = 10262 , LIEF::assembly::riscv::PseudoVSSSEG3E16_V_MF2 = 10263 ,
  LIEF::assembly::riscv::PseudoVSSSEG3E16_V_MF2_MASK = 10264 , LIEF::assembly::riscv::PseudoVSSSEG3E16_V_MF4 = 10265 , LIEF::assembly::riscv::PseudoVSSSEG3E16_V_MF4_MASK = 10266 , LIEF::assembly::riscv::PseudoVSSSEG3E32_V_M1 = 10267 ,
  LIEF::assembly::riscv::PseudoVSSSEG3E32_V_M1_MASK = 10268 , LIEF::assembly::riscv::PseudoVSSSEG3E32_V_M2 = 10269 , LIEF::assembly::riscv::PseudoVSSSEG3E32_V_M2_MASK = 10270 , LIEF::assembly::riscv::PseudoVSSSEG3E32_V_MF2 = 10271 ,
  LIEF::assembly::riscv::PseudoVSSSEG3E32_V_MF2_MASK = 10272 , LIEF::assembly::riscv::PseudoVSSSEG3E64_V_M1 = 10273 , LIEF::assembly::riscv::PseudoVSSSEG3E64_V_M1_MASK = 10274 , LIEF::assembly::riscv::PseudoVSSSEG3E64_V_M2 = 10275 ,
  LIEF::assembly::riscv::PseudoVSSSEG3E64_V_M2_MASK = 10276 , LIEF::assembly::riscv::PseudoVSSSEG3E8_V_M1 = 10277 , LIEF::assembly::riscv::PseudoVSSSEG3E8_V_M1_MASK = 10278 , LIEF::assembly::riscv::PseudoVSSSEG3E8_V_M2 = 10279 ,
  LIEF::assembly::riscv::PseudoVSSSEG3E8_V_M2_MASK = 10280 , LIEF::assembly::riscv::PseudoVSSSEG3E8_V_MF2 = 10281 , LIEF::assembly::riscv::PseudoVSSSEG3E8_V_MF2_MASK = 10282 , LIEF::assembly::riscv::PseudoVSSSEG3E8_V_MF4 = 10283 ,
  LIEF::assembly::riscv::PseudoVSSSEG3E8_V_MF4_MASK = 10284 , LIEF::assembly::riscv::PseudoVSSSEG3E8_V_MF8 = 10285 , LIEF::assembly::riscv::PseudoVSSSEG3E8_V_MF8_MASK = 10286 , LIEF::assembly::riscv::PseudoVSSSEG4E16_V_M1 = 10287 ,
  LIEF::assembly::riscv::PseudoVSSSEG4E16_V_M1_MASK = 10288 , LIEF::assembly::riscv::PseudoVSSSEG4E16_V_M2 = 10289 , LIEF::assembly::riscv::PseudoVSSSEG4E16_V_M2_MASK = 10290 , LIEF::assembly::riscv::PseudoVSSSEG4E16_V_MF2 = 10291 ,
  LIEF::assembly::riscv::PseudoVSSSEG4E16_V_MF2_MASK = 10292 , LIEF::assembly::riscv::PseudoVSSSEG4E16_V_MF4 = 10293 , LIEF::assembly::riscv::PseudoVSSSEG4E16_V_MF4_MASK = 10294 , LIEF::assembly::riscv::PseudoVSSSEG4E32_V_M1 = 10295 ,
  LIEF::assembly::riscv::PseudoVSSSEG4E32_V_M1_MASK = 10296 , LIEF::assembly::riscv::PseudoVSSSEG4E32_V_M2 = 10297 , LIEF::assembly::riscv::PseudoVSSSEG4E32_V_M2_MASK = 10298 , LIEF::assembly::riscv::PseudoVSSSEG4E32_V_MF2 = 10299 ,
  LIEF::assembly::riscv::PseudoVSSSEG4E32_V_MF2_MASK = 10300 , LIEF::assembly::riscv::PseudoVSSSEG4E64_V_M1 = 10301 , LIEF::assembly::riscv::PseudoVSSSEG4E64_V_M1_MASK = 10302 , LIEF::assembly::riscv::PseudoVSSSEG4E64_V_M2 = 10303 ,
  LIEF::assembly::riscv::PseudoVSSSEG4E64_V_M2_MASK = 10304 , LIEF::assembly::riscv::PseudoVSSSEG4E8_V_M1 = 10305 , LIEF::assembly::riscv::PseudoVSSSEG4E8_V_M1_MASK = 10306 , LIEF::assembly::riscv::PseudoVSSSEG4E8_V_M2 = 10307 ,
  LIEF::assembly::riscv::PseudoVSSSEG4E8_V_M2_MASK = 10308 , LIEF::assembly::riscv::PseudoVSSSEG4E8_V_MF2 = 10309 , LIEF::assembly::riscv::PseudoVSSSEG4E8_V_MF2_MASK = 10310 , LIEF::assembly::riscv::PseudoVSSSEG4E8_V_MF4 = 10311 ,
  LIEF::assembly::riscv::PseudoVSSSEG4E8_V_MF4_MASK = 10312 , LIEF::assembly::riscv::PseudoVSSSEG4E8_V_MF8 = 10313 , LIEF::assembly::riscv::PseudoVSSSEG4E8_V_MF8_MASK = 10314 , LIEF::assembly::riscv::PseudoVSSSEG5E16_V_M1 = 10315 ,
  LIEF::assembly::riscv::PseudoVSSSEG5E16_V_M1_MASK = 10316 , LIEF::assembly::riscv::PseudoVSSSEG5E16_V_MF2 = 10317 , LIEF::assembly::riscv::PseudoVSSSEG5E16_V_MF2_MASK = 10318 , LIEF::assembly::riscv::PseudoVSSSEG5E16_V_MF4 = 10319 ,
  LIEF::assembly::riscv::PseudoVSSSEG5E16_V_MF4_MASK = 10320 , LIEF::assembly::riscv::PseudoVSSSEG5E32_V_M1 = 10321 , LIEF::assembly::riscv::PseudoVSSSEG5E32_V_M1_MASK = 10322 , LIEF::assembly::riscv::PseudoVSSSEG5E32_V_MF2 = 10323 ,
  LIEF::assembly::riscv::PseudoVSSSEG5E32_V_MF2_MASK = 10324 , LIEF::assembly::riscv::PseudoVSSSEG5E64_V_M1 = 10325 , LIEF::assembly::riscv::PseudoVSSSEG5E64_V_M1_MASK = 10326 , LIEF::assembly::riscv::PseudoVSSSEG5E8_V_M1 = 10327 ,
  LIEF::assembly::riscv::PseudoVSSSEG5E8_V_M1_MASK = 10328 , LIEF::assembly::riscv::PseudoVSSSEG5E8_V_MF2 = 10329 , LIEF::assembly::riscv::PseudoVSSSEG5E8_V_MF2_MASK = 10330 , LIEF::assembly::riscv::PseudoVSSSEG5E8_V_MF4 = 10331 ,
  LIEF::assembly::riscv::PseudoVSSSEG5E8_V_MF4_MASK = 10332 , LIEF::assembly::riscv::PseudoVSSSEG5E8_V_MF8 = 10333 , LIEF::assembly::riscv::PseudoVSSSEG5E8_V_MF8_MASK = 10334 , LIEF::assembly::riscv::PseudoVSSSEG6E16_V_M1 = 10335 ,
  LIEF::assembly::riscv::PseudoVSSSEG6E16_V_M1_MASK = 10336 , LIEF::assembly::riscv::PseudoVSSSEG6E16_V_MF2 = 10337 , LIEF::assembly::riscv::PseudoVSSSEG6E16_V_MF2_MASK = 10338 , LIEF::assembly::riscv::PseudoVSSSEG6E16_V_MF4 = 10339 ,
  LIEF::assembly::riscv::PseudoVSSSEG6E16_V_MF4_MASK = 10340 , LIEF::assembly::riscv::PseudoVSSSEG6E32_V_M1 = 10341 , LIEF::assembly::riscv::PseudoVSSSEG6E32_V_M1_MASK = 10342 , LIEF::assembly::riscv::PseudoVSSSEG6E32_V_MF2 = 10343 ,
  LIEF::assembly::riscv::PseudoVSSSEG6E32_V_MF2_MASK = 10344 , LIEF::assembly::riscv::PseudoVSSSEG6E64_V_M1 = 10345 , LIEF::assembly::riscv::PseudoVSSSEG6E64_V_M1_MASK = 10346 , LIEF::assembly::riscv::PseudoVSSSEG6E8_V_M1 = 10347 ,
  LIEF::assembly::riscv::PseudoVSSSEG6E8_V_M1_MASK = 10348 , LIEF::assembly::riscv::PseudoVSSSEG6E8_V_MF2 = 10349 , LIEF::assembly::riscv::PseudoVSSSEG6E8_V_MF2_MASK = 10350 , LIEF::assembly::riscv::PseudoVSSSEG6E8_V_MF4 = 10351 ,
  LIEF::assembly::riscv::PseudoVSSSEG6E8_V_MF4_MASK = 10352 , LIEF::assembly::riscv::PseudoVSSSEG6E8_V_MF8 = 10353 , LIEF::assembly::riscv::PseudoVSSSEG6E8_V_MF8_MASK = 10354 , LIEF::assembly::riscv::PseudoVSSSEG7E16_V_M1 = 10355 ,
  LIEF::assembly::riscv::PseudoVSSSEG7E16_V_M1_MASK = 10356 , LIEF::assembly::riscv::PseudoVSSSEG7E16_V_MF2 = 10357 , LIEF::assembly::riscv::PseudoVSSSEG7E16_V_MF2_MASK = 10358 , LIEF::assembly::riscv::PseudoVSSSEG7E16_V_MF4 = 10359 ,
  LIEF::assembly::riscv::PseudoVSSSEG7E16_V_MF4_MASK = 10360 , LIEF::assembly::riscv::PseudoVSSSEG7E32_V_M1 = 10361 , LIEF::assembly::riscv::PseudoVSSSEG7E32_V_M1_MASK = 10362 , LIEF::assembly::riscv::PseudoVSSSEG7E32_V_MF2 = 10363 ,
  LIEF::assembly::riscv::PseudoVSSSEG7E32_V_MF2_MASK = 10364 , LIEF::assembly::riscv::PseudoVSSSEG7E64_V_M1 = 10365 , LIEF::assembly::riscv::PseudoVSSSEG7E64_V_M1_MASK = 10366 , LIEF::assembly::riscv::PseudoVSSSEG7E8_V_M1 = 10367 ,
  LIEF::assembly::riscv::PseudoVSSSEG7E8_V_M1_MASK = 10368 , LIEF::assembly::riscv::PseudoVSSSEG7E8_V_MF2 = 10369 , LIEF::assembly::riscv::PseudoVSSSEG7E8_V_MF2_MASK = 10370 , LIEF::assembly::riscv::PseudoVSSSEG7E8_V_MF4 = 10371 ,
  LIEF::assembly::riscv::PseudoVSSSEG7E8_V_MF4_MASK = 10372 , LIEF::assembly::riscv::PseudoVSSSEG7E8_V_MF8 = 10373 , LIEF::assembly::riscv::PseudoVSSSEG7E8_V_MF8_MASK = 10374 , LIEF::assembly::riscv::PseudoVSSSEG8E16_V_M1 = 10375 ,
  LIEF::assembly::riscv::PseudoVSSSEG8E16_V_M1_MASK = 10376 , LIEF::assembly::riscv::PseudoVSSSEG8E16_V_MF2 = 10377 , LIEF::assembly::riscv::PseudoVSSSEG8E16_V_MF2_MASK = 10378 , LIEF::assembly::riscv::PseudoVSSSEG8E16_V_MF4 = 10379 ,
  LIEF::assembly::riscv::PseudoVSSSEG8E16_V_MF4_MASK = 10380 , LIEF::assembly::riscv::PseudoVSSSEG8E32_V_M1 = 10381 , LIEF::assembly::riscv::PseudoVSSSEG8E32_V_M1_MASK = 10382 , LIEF::assembly::riscv::PseudoVSSSEG8E32_V_MF2 = 10383 ,
  LIEF::assembly::riscv::PseudoVSSSEG8E32_V_MF2_MASK = 10384 , LIEF::assembly::riscv::PseudoVSSSEG8E64_V_M1 = 10385 , LIEF::assembly::riscv::PseudoVSSSEG8E64_V_M1_MASK = 10386 , LIEF::assembly::riscv::PseudoVSSSEG8E8_V_M1 = 10387 ,
  LIEF::assembly::riscv::PseudoVSSSEG8E8_V_M1_MASK = 10388 , LIEF::assembly::riscv::PseudoVSSSEG8E8_V_MF2 = 10389 , LIEF::assembly::riscv::PseudoVSSSEG8E8_V_MF2_MASK = 10390 , LIEF::assembly::riscv::PseudoVSSSEG8E8_V_MF4 = 10391 ,
  LIEF::assembly::riscv::PseudoVSSSEG8E8_V_MF4_MASK = 10392 , LIEF::assembly::riscv::PseudoVSSSEG8E8_V_MF8 = 10393 , LIEF::assembly::riscv::PseudoVSSSEG8E8_V_MF8_MASK = 10394 , LIEF::assembly::riscv::PseudoVSSUBU_VV_M1 = 10395 ,
  LIEF::assembly::riscv::PseudoVSSUBU_VV_M1_MASK = 10396 , LIEF::assembly::riscv::PseudoVSSUBU_VV_M2 = 10397 , LIEF::assembly::riscv::PseudoVSSUBU_VV_M2_MASK = 10398 , LIEF::assembly::riscv::PseudoVSSUBU_VV_M4 = 10399 ,
  LIEF::assembly::riscv::PseudoVSSUBU_VV_M4_MASK = 10400 , LIEF::assembly::riscv::PseudoVSSUBU_VV_M8 = 10401 , LIEF::assembly::riscv::PseudoVSSUBU_VV_M8_MASK = 10402 , LIEF::assembly::riscv::PseudoVSSUBU_VV_MF2 = 10403 ,
  LIEF::assembly::riscv::PseudoVSSUBU_VV_MF2_MASK = 10404 , LIEF::assembly::riscv::PseudoVSSUBU_VV_MF4 = 10405 , LIEF::assembly::riscv::PseudoVSSUBU_VV_MF4_MASK = 10406 , LIEF::assembly::riscv::PseudoVSSUBU_VV_MF8 = 10407 ,
  LIEF::assembly::riscv::PseudoVSSUBU_VV_MF8_MASK = 10408 , LIEF::assembly::riscv::PseudoVSSUBU_VX_M1 = 10409 , LIEF::assembly::riscv::PseudoVSSUBU_VX_M1_MASK = 10410 , LIEF::assembly::riscv::PseudoVSSUBU_VX_M2 = 10411 ,
  LIEF::assembly::riscv::PseudoVSSUBU_VX_M2_MASK = 10412 , LIEF::assembly::riscv::PseudoVSSUBU_VX_M4 = 10413 , LIEF::assembly::riscv::PseudoVSSUBU_VX_M4_MASK = 10414 , LIEF::assembly::riscv::PseudoVSSUBU_VX_M8 = 10415 ,
  LIEF::assembly::riscv::PseudoVSSUBU_VX_M8_MASK = 10416 , LIEF::assembly::riscv::PseudoVSSUBU_VX_MF2 = 10417 , LIEF::assembly::riscv::PseudoVSSUBU_VX_MF2_MASK = 10418 , LIEF::assembly::riscv::PseudoVSSUBU_VX_MF4 = 10419 ,
  LIEF::assembly::riscv::PseudoVSSUBU_VX_MF4_MASK = 10420 , LIEF::assembly::riscv::PseudoVSSUBU_VX_MF8 = 10421 , LIEF::assembly::riscv::PseudoVSSUBU_VX_MF8_MASK = 10422 , LIEF::assembly::riscv::PseudoVSSUB_VV_M1 = 10423 ,
  LIEF::assembly::riscv::PseudoVSSUB_VV_M1_MASK = 10424 , LIEF::assembly::riscv::PseudoVSSUB_VV_M2 = 10425 , LIEF::assembly::riscv::PseudoVSSUB_VV_M2_MASK = 10426 , LIEF::assembly::riscv::PseudoVSSUB_VV_M4 = 10427 ,
  LIEF::assembly::riscv::PseudoVSSUB_VV_M4_MASK = 10428 , LIEF::assembly::riscv::PseudoVSSUB_VV_M8 = 10429 , LIEF::assembly::riscv::PseudoVSSUB_VV_M8_MASK = 10430 , LIEF::assembly::riscv::PseudoVSSUB_VV_MF2 = 10431 ,
  LIEF::assembly::riscv::PseudoVSSUB_VV_MF2_MASK = 10432 , LIEF::assembly::riscv::PseudoVSSUB_VV_MF4 = 10433 , LIEF::assembly::riscv::PseudoVSSUB_VV_MF4_MASK = 10434 , LIEF::assembly::riscv::PseudoVSSUB_VV_MF8 = 10435 ,
  LIEF::assembly::riscv::PseudoVSSUB_VV_MF8_MASK = 10436 , LIEF::assembly::riscv::PseudoVSSUB_VX_M1 = 10437 , LIEF::assembly::riscv::PseudoVSSUB_VX_M1_MASK = 10438 , LIEF::assembly::riscv::PseudoVSSUB_VX_M2 = 10439 ,
  LIEF::assembly::riscv::PseudoVSSUB_VX_M2_MASK = 10440 , LIEF::assembly::riscv::PseudoVSSUB_VX_M4 = 10441 , LIEF::assembly::riscv::PseudoVSSUB_VX_M4_MASK = 10442 , LIEF::assembly::riscv::PseudoVSSUB_VX_M8 = 10443 ,
  LIEF::assembly::riscv::PseudoVSSUB_VX_M8_MASK = 10444 , LIEF::assembly::riscv::PseudoVSSUB_VX_MF2 = 10445 , LIEF::assembly::riscv::PseudoVSSUB_VX_MF2_MASK = 10446 , LIEF::assembly::riscv::PseudoVSSUB_VX_MF4 = 10447 ,
  LIEF::assembly::riscv::PseudoVSSUB_VX_MF4_MASK = 10448 , LIEF::assembly::riscv::PseudoVSSUB_VX_MF8 = 10449 , LIEF::assembly::riscv::PseudoVSSUB_VX_MF8_MASK = 10450 , LIEF::assembly::riscv::PseudoVSUB_VV_M1 = 10451 ,
  LIEF::assembly::riscv::PseudoVSUB_VV_M1_MASK = 10452 , LIEF::assembly::riscv::PseudoVSUB_VV_M2 = 10453 , LIEF::assembly::riscv::PseudoVSUB_VV_M2_MASK = 10454 , LIEF::assembly::riscv::PseudoVSUB_VV_M4 = 10455 ,
  LIEF::assembly::riscv::PseudoVSUB_VV_M4_MASK = 10456 , LIEF::assembly::riscv::PseudoVSUB_VV_M8 = 10457 , LIEF::assembly::riscv::PseudoVSUB_VV_M8_MASK = 10458 , LIEF::assembly::riscv::PseudoVSUB_VV_MF2 = 10459 ,
  LIEF::assembly::riscv::PseudoVSUB_VV_MF2_MASK = 10460 , LIEF::assembly::riscv::PseudoVSUB_VV_MF4 = 10461 , LIEF::assembly::riscv::PseudoVSUB_VV_MF4_MASK = 10462 , LIEF::assembly::riscv::PseudoVSUB_VV_MF8 = 10463 ,
  LIEF::assembly::riscv::PseudoVSUB_VV_MF8_MASK = 10464 , LIEF::assembly::riscv::PseudoVSUB_VX_M1 = 10465 , LIEF::assembly::riscv::PseudoVSUB_VX_M1_MASK = 10466 , LIEF::assembly::riscv::PseudoVSUB_VX_M2 = 10467 ,
  LIEF::assembly::riscv::PseudoVSUB_VX_M2_MASK = 10468 , LIEF::assembly::riscv::PseudoVSUB_VX_M4 = 10469 , LIEF::assembly::riscv::PseudoVSUB_VX_M4_MASK = 10470 , LIEF::assembly::riscv::PseudoVSUB_VX_M8 = 10471 ,
  LIEF::assembly::riscv::PseudoVSUB_VX_M8_MASK = 10472 , LIEF::assembly::riscv::PseudoVSUB_VX_MF2 = 10473 , LIEF::assembly::riscv::PseudoVSUB_VX_MF2_MASK = 10474 , LIEF::assembly::riscv::PseudoVSUB_VX_MF4 = 10475 ,
  LIEF::assembly::riscv::PseudoVSUB_VX_MF4_MASK = 10476 , LIEF::assembly::riscv::PseudoVSUB_VX_MF8 = 10477 , LIEF::assembly::riscv::PseudoVSUB_VX_MF8_MASK = 10478 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M1_M1 = 10479 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_M1_M1_MASK = 10480 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M1_M2 = 10481 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M1_M2_MASK = 10482 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M1_M4 = 10483 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_M1_M4_MASK = 10484 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M1_MF2 = 10485 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M1_MF2_MASK = 10486 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M2_M1 = 10487 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_M2_M1_MASK = 10488 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M2_M2 = 10489 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M2_M2_MASK = 10490 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M2_M4 = 10491 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_M2_M4_MASK = 10492 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M2_M8 = 10493 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M2_M8_MASK = 10494 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M4_M2 = 10495 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_M4_M2_MASK = 10496 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M4_M4 = 10497 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M4_M4_MASK = 10498 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M4_M8 = 10499 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_M4_M8_MASK = 10500 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M8_M4 = 10501 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M8_M4_MASK = 10502 , LIEF::assembly::riscv::PseudoVSUXEI16_V_M8_M8 = 10503 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_M8_M8_MASK = 10504 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF2_M1 = 10505 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF2_M1_MASK = 10506 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF2_M2 = 10507 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_MF2_M2_MASK = 10508 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF2_MF2 = 10509 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF2_MF2_MASK = 10510 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF2_MF4 = 10511 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_MF2_MF4_MASK = 10512 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF4_M1 = 10513 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF4_M1_MASK = 10514 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF4_MF2 = 10515 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_MF4_MF2_MASK = 10516 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF4_MF4 = 10517 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF4_MF4_MASK = 10518 , LIEF::assembly::riscv::PseudoVSUXEI16_V_MF4_MF8 = 10519 ,
  LIEF::assembly::riscv::PseudoVSUXEI16_V_MF4_MF8_MASK = 10520 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M1_M1 = 10521 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M1_M1_MASK = 10522 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M1_M2 = 10523 ,
  LIEF::assembly::riscv::PseudoVSUXEI32_V_M1_M2_MASK = 10524 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M1_MF2 = 10525 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M1_MF2_MASK = 10526 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M1_MF4 = 10527 ,
  LIEF::assembly::riscv::PseudoVSUXEI32_V_M1_MF4_MASK = 10528 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M2_M1 = 10529 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M2_M1_MASK = 10530 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M2_M2 = 10531 ,
  LIEF::assembly::riscv::PseudoVSUXEI32_V_M2_M2_MASK = 10532 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M2_M4 = 10533 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M2_M4_MASK = 10534 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M2_MF2 = 10535 ,
  LIEF::assembly::riscv::PseudoVSUXEI32_V_M2_MF2_MASK = 10536 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M4_M1 = 10537 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M4_M1_MASK = 10538 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M4_M2 = 10539 ,
  LIEF::assembly::riscv::PseudoVSUXEI32_V_M4_M2_MASK = 10540 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M4_M4 = 10541 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M4_M4_MASK = 10542 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M4_M8 = 10543 ,
  LIEF::assembly::riscv::PseudoVSUXEI32_V_M4_M8_MASK = 10544 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M8_M2 = 10545 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M8_M2_MASK = 10546 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M8_M4 = 10547 ,
  LIEF::assembly::riscv::PseudoVSUXEI32_V_M8_M4_MASK = 10548 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M8_M8 = 10549 , LIEF::assembly::riscv::PseudoVSUXEI32_V_M8_M8_MASK = 10550 , LIEF::assembly::riscv::PseudoVSUXEI32_V_MF2_M1 = 10551 ,
  LIEF::assembly::riscv::PseudoVSUXEI32_V_MF2_M1_MASK = 10552 , LIEF::assembly::riscv::PseudoVSUXEI32_V_MF2_MF2 = 10553 , LIEF::assembly::riscv::PseudoVSUXEI32_V_MF2_MF2_MASK = 10554 , LIEF::assembly::riscv::PseudoVSUXEI32_V_MF2_MF4 = 10555 ,
  LIEF::assembly::riscv::PseudoVSUXEI32_V_MF2_MF4_MASK = 10556 , LIEF::assembly::riscv::PseudoVSUXEI32_V_MF2_MF8 = 10557 , LIEF::assembly::riscv::PseudoVSUXEI32_V_MF2_MF8_MASK = 10558 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M1_M1 = 10559 ,
  LIEF::assembly::riscv::PseudoVSUXEI64_V_M1_M1_MASK = 10560 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M1_MF2 = 10561 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M1_MF2_MASK = 10562 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M1_MF4 = 10563 ,
  LIEF::assembly::riscv::PseudoVSUXEI64_V_M1_MF4_MASK = 10564 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M1_MF8 = 10565 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M1_MF8_MASK = 10566 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M2_M1 = 10567 ,
  LIEF::assembly::riscv::PseudoVSUXEI64_V_M2_M1_MASK = 10568 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M2_M2 = 10569 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M2_M2_MASK = 10570 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M2_MF2 = 10571 ,
  LIEF::assembly::riscv::PseudoVSUXEI64_V_M2_MF2_MASK = 10572 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M2_MF4 = 10573 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M2_MF4_MASK = 10574 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M4_M1 = 10575 ,
  LIEF::assembly::riscv::PseudoVSUXEI64_V_M4_M1_MASK = 10576 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M4_M2 = 10577 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M4_M2_MASK = 10578 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M4_M4 = 10579 ,
  LIEF::assembly::riscv::PseudoVSUXEI64_V_M4_M4_MASK = 10580 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M4_MF2 = 10581 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M4_MF2_MASK = 10582 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M8_M1 = 10583 ,
  LIEF::assembly::riscv::PseudoVSUXEI64_V_M8_M1_MASK = 10584 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M8_M2 = 10585 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M8_M2_MASK = 10586 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M8_M4 = 10587 ,
  LIEF::assembly::riscv::PseudoVSUXEI64_V_M8_M4_MASK = 10588 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M8_M8 = 10589 , LIEF::assembly::riscv::PseudoVSUXEI64_V_M8_M8_MASK = 10590 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M1_M1 = 10591 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_M1_M1_MASK = 10592 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M1_M2 = 10593 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M1_M2_MASK = 10594 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M1_M4 = 10595 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_M1_M4_MASK = 10596 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M1_M8 = 10597 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M1_M8_MASK = 10598 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M2_M2 = 10599 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_M2_M2_MASK = 10600 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M2_M4 = 10601 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M2_M4_MASK = 10602 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M2_M8 = 10603 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_M2_M8_MASK = 10604 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M4_M4 = 10605 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M4_M4_MASK = 10606 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M4_M8 = 10607 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_M4_M8_MASK = 10608 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M8_M8 = 10609 , LIEF::assembly::riscv::PseudoVSUXEI8_V_M8_M8_MASK = 10610 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF2_M1 = 10611 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_MF2_M1_MASK = 10612 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF2_M2 = 10613 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF2_M2_MASK = 10614 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF2_M4 = 10615 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_MF2_M4_MASK = 10616 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF2_MF2 = 10617 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF2_MF2_MASK = 10618 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF4_M1 = 10619 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_MF4_M1_MASK = 10620 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF4_M2 = 10621 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF4_M2_MASK = 10622 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF4_MF2 = 10623 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_MF4_MF2_MASK = 10624 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF4_MF4 = 10625 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF4_MF4_MASK = 10626 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF8_M1 = 10627 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_MF8_M1_MASK = 10628 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF8_MF2 = 10629 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF8_MF2_MASK = 10630 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF8_MF4 = 10631 ,
  LIEF::assembly::riscv::PseudoVSUXEI8_V_MF8_MF4_MASK = 10632 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF8_MF8 = 10633 , LIEF::assembly::riscv::PseudoVSUXEI8_V_MF8_MF8_MASK = 10634 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M1_M1 = 10635 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M1_M1_MASK = 10636 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M1_M2 = 10637 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M1_M2_MASK = 10638 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M1_M4 = 10639 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M1_M4_MASK = 10640 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M1_MF2 = 10641 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M1_MF2_MASK = 10642 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M2_M1 = 10643 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M2_M1_MASK = 10644 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M2_M2 = 10645 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M2_M2_MASK = 10646 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M2_M4 = 10647 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M2_M4_MASK = 10648 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M4_M2 = 10649 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M4_M2_MASK = 10650 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M4_M4 = 10651 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M4_M4_MASK = 10652 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M8_M4 = 10653 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_M8_M4_MASK = 10654 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF2_M1 = 10655 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF2_M1_MASK = 10656 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF2_M2 = 10657 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF2_M2_MASK = 10658 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF2_MF2 = 10659 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF2_MF2_MASK = 10660 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF2_MF4 = 10661 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF2_MF4_MASK = 10662 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF4_M1 = 10663 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF4_M1_MASK = 10664 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF4_MF2 = 10665 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF4_MF2_MASK = 10666 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF4_MF4 = 10667 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF4_MF4_MASK = 10668 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF4_MF8 = 10669 , LIEF::assembly::riscv::PseudoVSUXSEG2EI16_V_MF4_MF8_MASK = 10670 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M1_M1 = 10671 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M1_M1_MASK = 10672 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M1_M2 = 10673 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M1_M2_MASK = 10674 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M1_MF2 = 10675 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M1_MF2_MASK = 10676 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M1_MF4 = 10677 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M1_MF4_MASK = 10678 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M2_M1 = 10679 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M2_M1_MASK = 10680 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M2_M2 = 10681 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M2_M2_MASK = 10682 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M2_M4 = 10683 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M2_M4_MASK = 10684 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M2_MF2 = 10685 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M2_MF2_MASK = 10686 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M4_M1 = 10687 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M4_M1_MASK = 10688 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M4_M2 = 10689 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M4_M2_MASK = 10690 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M4_M4 = 10691 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M4_M4_MASK = 10692 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M8_M2 = 10693 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M8_M2_MASK = 10694 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M8_M4 = 10695 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_M8_M4_MASK = 10696 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_MF2_M1 = 10697 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_MF2_M1_MASK = 10698 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_MF2_MF2 = 10699 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_MF2_MF2_MASK = 10700 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_MF2_MF4 = 10701 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_MF2_MF4_MASK = 10702 , LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_MF2_MF8 = 10703 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI32_V_MF2_MF8_MASK = 10704 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M1_M1 = 10705 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M1_M1_MASK = 10706 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M1_MF2 = 10707 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M1_MF2_MASK = 10708 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M1_MF4 = 10709 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M1_MF4_MASK = 10710 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M1_MF8 = 10711 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M1_MF8_MASK = 10712 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M2_M1 = 10713 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M2_M1_MASK = 10714 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M2_M2 = 10715 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M2_M2_MASK = 10716 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M2_MF2 = 10717 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M2_MF2_MASK = 10718 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M2_MF4 = 10719 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M2_MF4_MASK = 10720 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M4_M1 = 10721 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M4_M1_MASK = 10722 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M4_M2 = 10723 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M4_M2_MASK = 10724 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M4_M4 = 10725 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M4_M4_MASK = 10726 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M4_MF2 = 10727 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M4_MF2_MASK = 10728 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M8_M1 = 10729 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M8_M1_MASK = 10730 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M8_M2 = 10731 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M8_M2_MASK = 10732 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M8_M4 = 10733 , LIEF::assembly::riscv::PseudoVSUXSEG2EI64_V_M8_M4_MASK = 10734 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M1_M1 = 10735 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M1_M1_MASK = 10736 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M1_M2 = 10737 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M1_M2_MASK = 10738 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M1_M4 = 10739 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M1_M4_MASK = 10740 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M2_M2 = 10741 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M2_M2_MASK = 10742 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M2_M4 = 10743 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M2_M4_MASK = 10744 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M4_M4 = 10745 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_M4_M4_MASK = 10746 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF2_M1 = 10747 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF2_M1_MASK = 10748 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF2_M2 = 10749 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF2_M2_MASK = 10750 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF2_M4 = 10751 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF2_M4_MASK = 10752 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF2_MF2 = 10753 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF2_MF2_MASK = 10754 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF4_M1 = 10755 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF4_M1_MASK = 10756 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF4_M2 = 10757 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF4_M2_MASK = 10758 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF4_MF2 = 10759 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF4_MF2_MASK = 10760 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF4_MF4 = 10761 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF4_MF4_MASK = 10762 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF8_M1 = 10763 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF8_M1_MASK = 10764 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF8_MF2 = 10765 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF8_MF2_MASK = 10766 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF8_MF4 = 10767 ,
  LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF8_MF4_MASK = 10768 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF8_MF8 = 10769 , LIEF::assembly::riscv::PseudoVSUXSEG2EI8_V_MF8_MF8_MASK = 10770 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M1_M1 = 10771 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M1_M1_MASK = 10772 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M1_M2 = 10773 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M1_M2_MASK = 10774 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M1_MF2 = 10775 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M1_MF2_MASK = 10776 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M2_M1 = 10777 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M2_M1_MASK = 10778 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M2_M2 = 10779 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M2_M2_MASK = 10780 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M4_M2 = 10781 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_M4_M2_MASK = 10782 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF2_M1 = 10783 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF2_M1_MASK = 10784 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF2_M2 = 10785 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF2_M2_MASK = 10786 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF2_MF2 = 10787 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF2_MF2_MASK = 10788 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF2_MF4 = 10789 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF2_MF4_MASK = 10790 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF4_M1 = 10791 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF4_M1_MASK = 10792 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF4_MF2 = 10793 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF4_MF2_MASK = 10794 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF4_MF4 = 10795 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF4_MF4_MASK = 10796 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF4_MF8 = 10797 , LIEF::assembly::riscv::PseudoVSUXSEG3EI16_V_MF4_MF8_MASK = 10798 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M1_M1 = 10799 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M1_M1_MASK = 10800 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M1_M2 = 10801 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M1_M2_MASK = 10802 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M1_MF2 = 10803 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M1_MF2_MASK = 10804 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M1_MF4 = 10805 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M1_MF4_MASK = 10806 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M2_M1 = 10807 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M2_M1_MASK = 10808 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M2_M2 = 10809 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M2_M2_MASK = 10810 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M2_MF2 = 10811 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M2_MF2_MASK = 10812 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M4_M1 = 10813 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M4_M1_MASK = 10814 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M4_M2 = 10815 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M4_M2_MASK = 10816 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M8_M2 = 10817 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_M8_M2_MASK = 10818 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_MF2_M1 = 10819 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_MF2_M1_MASK = 10820 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_MF2_MF2 = 10821 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_MF2_MF2_MASK = 10822 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_MF2_MF4 = 10823 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_MF2_MF4_MASK = 10824 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_MF2_MF8 = 10825 , LIEF::assembly::riscv::PseudoVSUXSEG3EI32_V_MF2_MF8_MASK = 10826 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M1_M1 = 10827 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M1_M1_MASK = 10828 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M1_MF2 = 10829 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M1_MF2_MASK = 10830 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M1_MF4 = 10831 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M1_MF4_MASK = 10832 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M1_MF8 = 10833 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M1_MF8_MASK = 10834 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M2_M1 = 10835 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M2_M1_MASK = 10836 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M2_M2 = 10837 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M2_M2_MASK = 10838 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M2_MF2 = 10839 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M2_MF2_MASK = 10840 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M2_MF4 = 10841 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M2_MF4_MASK = 10842 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M4_M1 = 10843 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M4_M1_MASK = 10844 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M4_M2 = 10845 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M4_M2_MASK = 10846 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M4_MF2 = 10847 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M4_MF2_MASK = 10848 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M8_M1 = 10849 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M8_M1_MASK = 10850 , LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M8_M2 = 10851 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI64_V_M8_M2_MASK = 10852 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_M1_M1 = 10853 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_M1_M1_MASK = 10854 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_M1_M2 = 10855 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_M1_M2_MASK = 10856 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_M2_M2 = 10857 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_M2_M2_MASK = 10858 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF2_M1 = 10859 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF2_M1_MASK = 10860 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF2_M2 = 10861 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF2_M2_MASK = 10862 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF2_MF2 = 10863 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF2_MF2_MASK = 10864 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF4_M1 = 10865 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF4_M1_MASK = 10866 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF4_M2 = 10867 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF4_M2_MASK = 10868 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF4_MF2 = 10869 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF4_MF2_MASK = 10870 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF4_MF4 = 10871 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF4_MF4_MASK = 10872 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF8_M1 = 10873 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF8_M1_MASK = 10874 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF8_MF2 = 10875 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF8_MF2_MASK = 10876 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF8_MF4 = 10877 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF8_MF4_MASK = 10878 , LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF8_MF8 = 10879 ,
  LIEF::assembly::riscv::PseudoVSUXSEG3EI8_V_MF8_MF8_MASK = 10880 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M1_M1 = 10881 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M1_M1_MASK = 10882 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M1_M2 = 10883 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M1_M2_MASK = 10884 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M1_MF2 = 10885 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M1_MF2_MASK = 10886 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M2_M1 = 10887 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M2_M1_MASK = 10888 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M2_M2 = 10889 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M2_M2_MASK = 10890 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M4_M2 = 10891 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_M4_M2_MASK = 10892 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF2_M1 = 10893 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF2_M1_MASK = 10894 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF2_M2 = 10895 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF2_M2_MASK = 10896 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF2_MF2 = 10897 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF2_MF2_MASK = 10898 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF2_MF4 = 10899 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF2_MF4_MASK = 10900 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF4_M1 = 10901 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF4_M1_MASK = 10902 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF4_MF2 = 10903 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF4_MF2_MASK = 10904 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF4_MF4 = 10905 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF4_MF4_MASK = 10906 , LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF4_MF8 = 10907 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI16_V_MF4_MF8_MASK = 10908 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M1_M1 = 10909 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M1_M1_MASK = 10910 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M1_M2 = 10911 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M1_M2_MASK = 10912 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M1_MF2 = 10913 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M1_MF2_MASK = 10914 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M1_MF4 = 10915 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M1_MF4_MASK = 10916 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M2_M1 = 10917 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M2_M1_MASK = 10918 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M2_M2 = 10919 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M2_M2_MASK = 10920 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M2_MF2 = 10921 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M2_MF2_MASK = 10922 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M4_M1 = 10923 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M4_M1_MASK = 10924 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M4_M2 = 10925 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M4_M2_MASK = 10926 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M8_M2 = 10927 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_M8_M2_MASK = 10928 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_MF2_M1 = 10929 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_MF2_M1_MASK = 10930 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_MF2_MF2 = 10931 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_MF2_MF2_MASK = 10932 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_MF2_MF4 = 10933 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_MF2_MF4_MASK = 10934 , LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_MF2_MF8 = 10935 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI32_V_MF2_MF8_MASK = 10936 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M1_M1 = 10937 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M1_M1_MASK = 10938 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M1_MF2 = 10939 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M1_MF2_MASK = 10940 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M1_MF4 = 10941 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M1_MF4_MASK = 10942 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M1_MF8 = 10943 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M1_MF8_MASK = 10944 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M2_M1 = 10945 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M2_M1_MASK = 10946 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M2_M2 = 10947 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M2_M2_MASK = 10948 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M2_MF2 = 10949 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M2_MF2_MASK = 10950 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M2_MF4 = 10951 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M2_MF4_MASK = 10952 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M4_M1 = 10953 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M4_M1_MASK = 10954 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M4_M2 = 10955 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M4_M2_MASK = 10956 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M4_MF2 = 10957 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M4_MF2_MASK = 10958 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M8_M1 = 10959 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M8_M1_MASK = 10960 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M8_M2 = 10961 , LIEF::assembly::riscv::PseudoVSUXSEG4EI64_V_M8_M2_MASK = 10962 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_M1_M1 = 10963 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_M1_M1_MASK = 10964 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_M1_M2 = 10965 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_M1_M2_MASK = 10966 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_M2_M2 = 10967 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_M2_M2_MASK = 10968 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF2_M1 = 10969 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF2_M1_MASK = 10970 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF2_M2 = 10971 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF2_M2_MASK = 10972 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF2_MF2 = 10973 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF2_MF2_MASK = 10974 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF4_M1 = 10975 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF4_M1_MASK = 10976 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF4_M2 = 10977 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF4_M2_MASK = 10978 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF4_MF2 = 10979 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF4_MF2_MASK = 10980 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF4_MF4 = 10981 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF4_MF4_MASK = 10982 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF8_M1 = 10983 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF8_M1_MASK = 10984 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF8_MF2 = 10985 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF8_MF2_MASK = 10986 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF8_MF4 = 10987 ,
  LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF8_MF4_MASK = 10988 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF8_MF8 = 10989 , LIEF::assembly::riscv::PseudoVSUXSEG4EI8_V_MF8_MF8_MASK = 10990 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_M1_M1 = 10991 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_M1_M1_MASK = 10992 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_M1_MF2 = 10993 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_M1_MF2_MASK = 10994 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_M2_M1 = 10995 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_M2_M1_MASK = 10996 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF2_M1 = 10997 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF2_M1_MASK = 10998 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF2_MF2 = 10999 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF2_MF2_MASK = 11000 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF2_MF4 = 11001 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF2_MF4_MASK = 11002 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF4_M1 = 11003 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF4_M1_MASK = 11004 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF4_MF2 = 11005 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF4_MF2_MASK = 11006 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF4_MF4 = 11007 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF4_MF4_MASK = 11008 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF4_MF8 = 11009 , LIEF::assembly::riscv::PseudoVSUXSEG5EI16_V_MF4_MF8_MASK = 11010 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M1_M1 = 11011 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M1_M1_MASK = 11012 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M1_MF2 = 11013 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M1_MF2_MASK = 11014 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M1_MF4 = 11015 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M1_MF4_MASK = 11016 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M2_M1 = 11017 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M2_M1_MASK = 11018 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M2_MF2 = 11019 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M2_MF2_MASK = 11020 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M4_M1 = 11021 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_M4_M1_MASK = 11022 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_MF2_M1 = 11023 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_MF2_M1_MASK = 11024 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_MF2_MF2 = 11025 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_MF2_MF2_MASK = 11026 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_MF2_MF4 = 11027 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_MF2_MF4_MASK = 11028 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_MF2_MF8 = 11029 , LIEF::assembly::riscv::PseudoVSUXSEG5EI32_V_MF2_MF8_MASK = 11030 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M1_M1 = 11031 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M1_M1_MASK = 11032 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M1_MF2 = 11033 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M1_MF2_MASK = 11034 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M1_MF4 = 11035 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M1_MF4_MASK = 11036 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M1_MF8 = 11037 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M1_MF8_MASK = 11038 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M2_M1 = 11039 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M2_M1_MASK = 11040 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M2_MF2 = 11041 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M2_MF2_MASK = 11042 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M2_MF4 = 11043 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M2_MF4_MASK = 11044 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M4_M1 = 11045 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M4_M1_MASK = 11046 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M4_MF2 = 11047 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M4_MF2_MASK = 11048 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M8_M1 = 11049 , LIEF::assembly::riscv::PseudoVSUXSEG5EI64_V_M8_M1_MASK = 11050 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_M1_M1 = 11051 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_M1_M1_MASK = 11052 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF2_M1 = 11053 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF2_M1_MASK = 11054 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF2_MF2 = 11055 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF2_MF2_MASK = 11056 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF4_M1 = 11057 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF4_M1_MASK = 11058 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF4_MF2 = 11059 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF4_MF2_MASK = 11060 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF4_MF4 = 11061 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF4_MF4_MASK = 11062 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF8_M1 = 11063 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF8_M1_MASK = 11064 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF8_MF2 = 11065 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF8_MF2_MASK = 11066 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF8_MF4 = 11067 ,
  LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF8_MF4_MASK = 11068 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF8_MF8 = 11069 , LIEF::assembly::riscv::PseudoVSUXSEG5EI8_V_MF8_MF8_MASK = 11070 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_M1_M1 = 11071 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_M1_M1_MASK = 11072 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_M1_MF2 = 11073 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_M1_MF2_MASK = 11074 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_M2_M1 = 11075 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_M2_M1_MASK = 11076 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF2_M1 = 11077 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF2_M1_MASK = 11078 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF2_MF2 = 11079 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF2_MF2_MASK = 11080 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF2_MF4 = 11081 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF2_MF4_MASK = 11082 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF4_M1 = 11083 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF4_M1_MASK = 11084 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF4_MF2 = 11085 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF4_MF2_MASK = 11086 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF4_MF4 = 11087 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF4_MF4_MASK = 11088 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF4_MF8 = 11089 , LIEF::assembly::riscv::PseudoVSUXSEG6EI16_V_MF4_MF8_MASK = 11090 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M1_M1 = 11091 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M1_M1_MASK = 11092 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M1_MF2 = 11093 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M1_MF2_MASK = 11094 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M1_MF4 = 11095 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M1_MF4_MASK = 11096 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M2_M1 = 11097 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M2_M1_MASK = 11098 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M2_MF2 = 11099 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M2_MF2_MASK = 11100 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M4_M1 = 11101 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_M4_M1_MASK = 11102 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_MF2_M1 = 11103 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_MF2_M1_MASK = 11104 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_MF2_MF2 = 11105 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_MF2_MF2_MASK = 11106 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_MF2_MF4 = 11107 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_MF2_MF4_MASK = 11108 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_MF2_MF8 = 11109 , LIEF::assembly::riscv::PseudoVSUXSEG6EI32_V_MF2_MF8_MASK = 11110 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M1_M1 = 11111 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M1_M1_MASK = 11112 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M1_MF2 = 11113 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M1_MF2_MASK = 11114 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M1_MF4 = 11115 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M1_MF4_MASK = 11116 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M1_MF8 = 11117 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M1_MF8_MASK = 11118 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M2_M1 = 11119 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M2_M1_MASK = 11120 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M2_MF2 = 11121 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M2_MF2_MASK = 11122 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M2_MF4 = 11123 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M2_MF4_MASK = 11124 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M4_M1 = 11125 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M4_M1_MASK = 11126 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M4_MF2 = 11127 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M4_MF2_MASK = 11128 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M8_M1 = 11129 , LIEF::assembly::riscv::PseudoVSUXSEG6EI64_V_M8_M1_MASK = 11130 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_M1_M1 = 11131 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_M1_M1_MASK = 11132 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF2_M1 = 11133 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF2_M1_MASK = 11134 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF2_MF2 = 11135 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF2_MF2_MASK = 11136 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF4_M1 = 11137 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF4_M1_MASK = 11138 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF4_MF2 = 11139 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF4_MF2_MASK = 11140 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF4_MF4 = 11141 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF4_MF4_MASK = 11142 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF8_M1 = 11143 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF8_M1_MASK = 11144 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF8_MF2 = 11145 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF8_MF2_MASK = 11146 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF8_MF4 = 11147 ,
  LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF8_MF4_MASK = 11148 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF8_MF8 = 11149 , LIEF::assembly::riscv::PseudoVSUXSEG6EI8_V_MF8_MF8_MASK = 11150 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_M1_M1 = 11151 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_M1_M1_MASK = 11152 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_M1_MF2 = 11153 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_M1_MF2_MASK = 11154 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_M2_M1 = 11155 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_M2_M1_MASK = 11156 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF2_M1 = 11157 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF2_M1_MASK = 11158 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF2_MF2 = 11159 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF2_MF2_MASK = 11160 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF2_MF4 = 11161 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF2_MF4_MASK = 11162 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF4_M1 = 11163 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF4_M1_MASK = 11164 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF4_MF2 = 11165 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF4_MF2_MASK = 11166 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF4_MF4 = 11167 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF4_MF4_MASK = 11168 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF4_MF8 = 11169 , LIEF::assembly::riscv::PseudoVSUXSEG7EI16_V_MF4_MF8_MASK = 11170 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M1_M1 = 11171 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M1_M1_MASK = 11172 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M1_MF2 = 11173 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M1_MF2_MASK = 11174 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M1_MF4 = 11175 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M1_MF4_MASK = 11176 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M2_M1 = 11177 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M2_M1_MASK = 11178 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M2_MF2 = 11179 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M2_MF2_MASK = 11180 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M4_M1 = 11181 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_M4_M1_MASK = 11182 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_MF2_M1 = 11183 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_MF2_M1_MASK = 11184 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_MF2_MF2 = 11185 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_MF2_MF2_MASK = 11186 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_MF2_MF4 = 11187 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_MF2_MF4_MASK = 11188 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_MF2_MF8 = 11189 , LIEF::assembly::riscv::PseudoVSUXSEG7EI32_V_MF2_MF8_MASK = 11190 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M1_M1 = 11191 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M1_M1_MASK = 11192 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M1_MF2 = 11193 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M1_MF2_MASK = 11194 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M1_MF4 = 11195 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M1_MF4_MASK = 11196 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M1_MF8 = 11197 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M1_MF8_MASK = 11198 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M2_M1 = 11199 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M2_M1_MASK = 11200 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M2_MF2 = 11201 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M2_MF2_MASK = 11202 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M2_MF4 = 11203 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M2_MF4_MASK = 11204 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M4_M1 = 11205 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M4_M1_MASK = 11206 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M4_MF2 = 11207 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M4_MF2_MASK = 11208 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M8_M1 = 11209 , LIEF::assembly::riscv::PseudoVSUXSEG7EI64_V_M8_M1_MASK = 11210 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_M1_M1 = 11211 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_M1_M1_MASK = 11212 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF2_M1 = 11213 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF2_M1_MASK = 11214 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF2_MF2 = 11215 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF2_MF2_MASK = 11216 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF4_M1 = 11217 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF4_M1_MASK = 11218 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF4_MF2 = 11219 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF4_MF2_MASK = 11220 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF4_MF4 = 11221 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF4_MF4_MASK = 11222 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF8_M1 = 11223 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF8_M1_MASK = 11224 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF8_MF2 = 11225 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF8_MF2_MASK = 11226 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF8_MF4 = 11227 ,
  LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF8_MF4_MASK = 11228 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF8_MF8 = 11229 , LIEF::assembly::riscv::PseudoVSUXSEG7EI8_V_MF8_MF8_MASK = 11230 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_M1_M1 = 11231 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_M1_M1_MASK = 11232 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_M1_MF2 = 11233 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_M1_MF2_MASK = 11234 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_M2_M1 = 11235 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_M2_M1_MASK = 11236 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF2_M1 = 11237 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF2_M1_MASK = 11238 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF2_MF2 = 11239 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF2_MF2_MASK = 11240 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF2_MF4 = 11241 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF2_MF4_MASK = 11242 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF4_M1 = 11243 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF4_M1_MASK = 11244 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF4_MF2 = 11245 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF4_MF2_MASK = 11246 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF4_MF4 = 11247 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF4_MF4_MASK = 11248 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF4_MF8 = 11249 , LIEF::assembly::riscv::PseudoVSUXSEG8EI16_V_MF4_MF8_MASK = 11250 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M1_M1 = 11251 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M1_M1_MASK = 11252 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M1_MF2 = 11253 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M1_MF2_MASK = 11254 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M1_MF4 = 11255 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M1_MF4_MASK = 11256 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M2_M1 = 11257 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M2_M1_MASK = 11258 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M2_MF2 = 11259 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M2_MF2_MASK = 11260 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M4_M1 = 11261 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_M4_M1_MASK = 11262 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_MF2_M1 = 11263 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_MF2_M1_MASK = 11264 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_MF2_MF2 = 11265 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_MF2_MF2_MASK = 11266 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_MF2_MF4 = 11267 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_MF2_MF4_MASK = 11268 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_MF2_MF8 = 11269 , LIEF::assembly::riscv::PseudoVSUXSEG8EI32_V_MF2_MF8_MASK = 11270 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M1_M1 = 11271 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M1_M1_MASK = 11272 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M1_MF2 = 11273 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M1_MF2_MASK = 11274 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M1_MF4 = 11275 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M1_MF4_MASK = 11276 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M1_MF8 = 11277 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M1_MF8_MASK = 11278 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M2_M1 = 11279 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M2_M1_MASK = 11280 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M2_MF2 = 11281 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M2_MF2_MASK = 11282 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M2_MF4 = 11283 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M2_MF4_MASK = 11284 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M4_M1 = 11285 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M4_M1_MASK = 11286 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M4_MF2 = 11287 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M4_MF2_MASK = 11288 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M8_M1 = 11289 , LIEF::assembly::riscv::PseudoVSUXSEG8EI64_V_M8_M1_MASK = 11290 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_M1_M1 = 11291 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_M1_M1_MASK = 11292 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF2_M1 = 11293 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF2_M1_MASK = 11294 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF2_MF2 = 11295 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF2_MF2_MASK = 11296 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF4_M1 = 11297 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF4_M1_MASK = 11298 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF4_MF2 = 11299 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF4_MF2_MASK = 11300 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF4_MF4 = 11301 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF4_MF4_MASK = 11302 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF8_M1 = 11303 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF8_M1_MASK = 11304 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF8_MF2 = 11305 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF8_MF2_MASK = 11306 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF8_MF4 = 11307 ,
  LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF8_MF4_MASK = 11308 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF8_MF8 = 11309 , LIEF::assembly::riscv::PseudoVSUXSEG8EI8_V_MF8_MF8_MASK = 11310 , LIEF::assembly::riscv::PseudoVWADDU_VV_M1 = 11311 ,
  LIEF::assembly::riscv::PseudoVWADDU_VV_M1_MASK = 11312 , LIEF::assembly::riscv::PseudoVWADDU_VV_M2 = 11313 , LIEF::assembly::riscv::PseudoVWADDU_VV_M2_MASK = 11314 , LIEF::assembly::riscv::PseudoVWADDU_VV_M4 = 11315 ,
  LIEF::assembly::riscv::PseudoVWADDU_VV_M4_MASK = 11316 , LIEF::assembly::riscv::PseudoVWADDU_VV_MF2 = 11317 , LIEF::assembly::riscv::PseudoVWADDU_VV_MF2_MASK = 11318 , LIEF::assembly::riscv::PseudoVWADDU_VV_MF4 = 11319 ,
  LIEF::assembly::riscv::PseudoVWADDU_VV_MF4_MASK = 11320 , LIEF::assembly::riscv::PseudoVWADDU_VV_MF8 = 11321 , LIEF::assembly::riscv::PseudoVWADDU_VV_MF8_MASK = 11322 , LIEF::assembly::riscv::PseudoVWADDU_VX_M1 = 11323 ,
  LIEF::assembly::riscv::PseudoVWADDU_VX_M1_MASK = 11324 , LIEF::assembly::riscv::PseudoVWADDU_VX_M2 = 11325 , LIEF::assembly::riscv::PseudoVWADDU_VX_M2_MASK = 11326 , LIEF::assembly::riscv::PseudoVWADDU_VX_M4 = 11327 ,
  LIEF::assembly::riscv::PseudoVWADDU_VX_M4_MASK = 11328 , LIEF::assembly::riscv::PseudoVWADDU_VX_MF2 = 11329 , LIEF::assembly::riscv::PseudoVWADDU_VX_MF2_MASK = 11330 , LIEF::assembly::riscv::PseudoVWADDU_VX_MF4 = 11331 ,
  LIEF::assembly::riscv::PseudoVWADDU_VX_MF4_MASK = 11332 , LIEF::assembly::riscv::PseudoVWADDU_VX_MF8 = 11333 , LIEF::assembly::riscv::PseudoVWADDU_VX_MF8_MASK = 11334 , LIEF::assembly::riscv::PseudoVWADDU_WV_M1 = 11335 ,
  LIEF::assembly::riscv::PseudoVWADDU_WV_M1_MASK = 11336 , LIEF::assembly::riscv::PseudoVWADDU_WV_M1_MASK_TIED = 11337 , LIEF::assembly::riscv::PseudoVWADDU_WV_M1_TIED = 11338 , LIEF::assembly::riscv::PseudoVWADDU_WV_M2 = 11339 ,
  LIEF::assembly::riscv::PseudoVWADDU_WV_M2_MASK = 11340 , LIEF::assembly::riscv::PseudoVWADDU_WV_M2_MASK_TIED = 11341 , LIEF::assembly::riscv::PseudoVWADDU_WV_M2_TIED = 11342 , LIEF::assembly::riscv::PseudoVWADDU_WV_M4 = 11343 ,
  LIEF::assembly::riscv::PseudoVWADDU_WV_M4_MASK = 11344 , LIEF::assembly::riscv::PseudoVWADDU_WV_M4_MASK_TIED = 11345 , LIEF::assembly::riscv::PseudoVWADDU_WV_M4_TIED = 11346 , LIEF::assembly::riscv::PseudoVWADDU_WV_MF2 = 11347 ,
  LIEF::assembly::riscv::PseudoVWADDU_WV_MF2_MASK = 11348 , LIEF::assembly::riscv::PseudoVWADDU_WV_MF2_MASK_TIED = 11349 , LIEF::assembly::riscv::PseudoVWADDU_WV_MF2_TIED = 11350 , LIEF::assembly::riscv::PseudoVWADDU_WV_MF4 = 11351 ,
  LIEF::assembly::riscv::PseudoVWADDU_WV_MF4_MASK = 11352 , LIEF::assembly::riscv::PseudoVWADDU_WV_MF4_MASK_TIED = 11353 , LIEF::assembly::riscv::PseudoVWADDU_WV_MF4_TIED = 11354 , LIEF::assembly::riscv::PseudoVWADDU_WV_MF8 = 11355 ,
  LIEF::assembly::riscv::PseudoVWADDU_WV_MF8_MASK = 11356 , LIEF::assembly::riscv::PseudoVWADDU_WV_MF8_MASK_TIED = 11357 , LIEF::assembly::riscv::PseudoVWADDU_WV_MF8_TIED = 11358 , LIEF::assembly::riscv::PseudoVWADDU_WX_M1 = 11359 ,
  LIEF::assembly::riscv::PseudoVWADDU_WX_M1_MASK = 11360 , LIEF::assembly::riscv::PseudoVWADDU_WX_M2 = 11361 , LIEF::assembly::riscv::PseudoVWADDU_WX_M2_MASK = 11362 , LIEF::assembly::riscv::PseudoVWADDU_WX_M4 = 11363 ,
  LIEF::assembly::riscv::PseudoVWADDU_WX_M4_MASK = 11364 , LIEF::assembly::riscv::PseudoVWADDU_WX_MF2 = 11365 , LIEF::assembly::riscv::PseudoVWADDU_WX_MF2_MASK = 11366 , LIEF::assembly::riscv::PseudoVWADDU_WX_MF4 = 11367 ,
  LIEF::assembly::riscv::PseudoVWADDU_WX_MF4_MASK = 11368 , LIEF::assembly::riscv::PseudoVWADDU_WX_MF8 = 11369 , LIEF::assembly::riscv::PseudoVWADDU_WX_MF8_MASK = 11370 , LIEF::assembly::riscv::PseudoVWADD_VV_M1 = 11371 ,
  LIEF::assembly::riscv::PseudoVWADD_VV_M1_MASK = 11372 , LIEF::assembly::riscv::PseudoVWADD_VV_M2 = 11373 , LIEF::assembly::riscv::PseudoVWADD_VV_M2_MASK = 11374 , LIEF::assembly::riscv::PseudoVWADD_VV_M4 = 11375 ,
  LIEF::assembly::riscv::PseudoVWADD_VV_M4_MASK = 11376 , LIEF::assembly::riscv::PseudoVWADD_VV_MF2 = 11377 , LIEF::assembly::riscv::PseudoVWADD_VV_MF2_MASK = 11378 , LIEF::assembly::riscv::PseudoVWADD_VV_MF4 = 11379 ,
  LIEF::assembly::riscv::PseudoVWADD_VV_MF4_MASK = 11380 , LIEF::assembly::riscv::PseudoVWADD_VV_MF8 = 11381 , LIEF::assembly::riscv::PseudoVWADD_VV_MF8_MASK = 11382 , LIEF::assembly::riscv::PseudoVWADD_VX_M1 = 11383 ,
  LIEF::assembly::riscv::PseudoVWADD_VX_M1_MASK = 11384 , LIEF::assembly::riscv::PseudoVWADD_VX_M2 = 11385 , LIEF::assembly::riscv::PseudoVWADD_VX_M2_MASK = 11386 , LIEF::assembly::riscv::PseudoVWADD_VX_M4 = 11387 ,
  LIEF::assembly::riscv::PseudoVWADD_VX_M4_MASK = 11388 , LIEF::assembly::riscv::PseudoVWADD_VX_MF2 = 11389 , LIEF::assembly::riscv::PseudoVWADD_VX_MF2_MASK = 11390 , LIEF::assembly::riscv::PseudoVWADD_VX_MF4 = 11391 ,
  LIEF::assembly::riscv::PseudoVWADD_VX_MF4_MASK = 11392 , LIEF::assembly::riscv::PseudoVWADD_VX_MF8 = 11393 , LIEF::assembly::riscv::PseudoVWADD_VX_MF8_MASK = 11394 , LIEF::assembly::riscv::PseudoVWADD_WV_M1 = 11395 ,
  LIEF::assembly::riscv::PseudoVWADD_WV_M1_MASK = 11396 , LIEF::assembly::riscv::PseudoVWADD_WV_M1_MASK_TIED = 11397 , LIEF::assembly::riscv::PseudoVWADD_WV_M1_TIED = 11398 , LIEF::assembly::riscv::PseudoVWADD_WV_M2 = 11399 ,
  LIEF::assembly::riscv::PseudoVWADD_WV_M2_MASK = 11400 , LIEF::assembly::riscv::PseudoVWADD_WV_M2_MASK_TIED = 11401 , LIEF::assembly::riscv::PseudoVWADD_WV_M2_TIED = 11402 , LIEF::assembly::riscv::PseudoVWADD_WV_M4 = 11403 ,
  LIEF::assembly::riscv::PseudoVWADD_WV_M4_MASK = 11404 , LIEF::assembly::riscv::PseudoVWADD_WV_M4_MASK_TIED = 11405 , LIEF::assembly::riscv::PseudoVWADD_WV_M4_TIED = 11406 , LIEF::assembly::riscv::PseudoVWADD_WV_MF2 = 11407 ,
  LIEF::assembly::riscv::PseudoVWADD_WV_MF2_MASK = 11408 , LIEF::assembly::riscv::PseudoVWADD_WV_MF2_MASK_TIED = 11409 , LIEF::assembly::riscv::PseudoVWADD_WV_MF2_TIED = 11410 , LIEF::assembly::riscv::PseudoVWADD_WV_MF4 = 11411 ,
  LIEF::assembly::riscv::PseudoVWADD_WV_MF4_MASK = 11412 , LIEF::assembly::riscv::PseudoVWADD_WV_MF4_MASK_TIED = 11413 , LIEF::assembly::riscv::PseudoVWADD_WV_MF4_TIED = 11414 , LIEF::assembly::riscv::PseudoVWADD_WV_MF8 = 11415 ,
  LIEF::assembly::riscv::PseudoVWADD_WV_MF8_MASK = 11416 , LIEF::assembly::riscv::PseudoVWADD_WV_MF8_MASK_TIED = 11417 , LIEF::assembly::riscv::PseudoVWADD_WV_MF8_TIED = 11418 , LIEF::assembly::riscv::PseudoVWADD_WX_M1 = 11419 ,
  LIEF::assembly::riscv::PseudoVWADD_WX_M1_MASK = 11420 , LIEF::assembly::riscv::PseudoVWADD_WX_M2 = 11421 , LIEF::assembly::riscv::PseudoVWADD_WX_M2_MASK = 11422 , LIEF::assembly::riscv::PseudoVWADD_WX_M4 = 11423 ,
  LIEF::assembly::riscv::PseudoVWADD_WX_M4_MASK = 11424 , LIEF::assembly::riscv::PseudoVWADD_WX_MF2 = 11425 , LIEF::assembly::riscv::PseudoVWADD_WX_MF2_MASK = 11426 , LIEF::assembly::riscv::PseudoVWADD_WX_MF4 = 11427 ,
  LIEF::assembly::riscv::PseudoVWADD_WX_MF4_MASK = 11428 , LIEF::assembly::riscv::PseudoVWADD_WX_MF8 = 11429 , LIEF::assembly::riscv::PseudoVWADD_WX_MF8_MASK = 11430 , LIEF::assembly::riscv::PseudoVWMACCSU_VV_M1 = 11431 ,
  LIEF::assembly::riscv::PseudoVWMACCSU_VV_M1_MASK = 11432 , LIEF::assembly::riscv::PseudoVWMACCSU_VV_M2 = 11433 , LIEF::assembly::riscv::PseudoVWMACCSU_VV_M2_MASK = 11434 , LIEF::assembly::riscv::PseudoVWMACCSU_VV_M4 = 11435 ,
  LIEF::assembly::riscv::PseudoVWMACCSU_VV_M4_MASK = 11436 , LIEF::assembly::riscv::PseudoVWMACCSU_VV_MF2 = 11437 , LIEF::assembly::riscv::PseudoVWMACCSU_VV_MF2_MASK = 11438 , LIEF::assembly::riscv::PseudoVWMACCSU_VV_MF4 = 11439 ,
  LIEF::assembly::riscv::PseudoVWMACCSU_VV_MF4_MASK = 11440 , LIEF::assembly::riscv::PseudoVWMACCSU_VV_MF8 = 11441 , LIEF::assembly::riscv::PseudoVWMACCSU_VV_MF8_MASK = 11442 , LIEF::assembly::riscv::PseudoVWMACCSU_VX_M1 = 11443 ,
  LIEF::assembly::riscv::PseudoVWMACCSU_VX_M1_MASK = 11444 , LIEF::assembly::riscv::PseudoVWMACCSU_VX_M2 = 11445 , LIEF::assembly::riscv::PseudoVWMACCSU_VX_M2_MASK = 11446 , LIEF::assembly::riscv::PseudoVWMACCSU_VX_M4 = 11447 ,
  LIEF::assembly::riscv::PseudoVWMACCSU_VX_M4_MASK = 11448 , LIEF::assembly::riscv::PseudoVWMACCSU_VX_MF2 = 11449 , LIEF::assembly::riscv::PseudoVWMACCSU_VX_MF2_MASK = 11450 , LIEF::assembly::riscv::PseudoVWMACCSU_VX_MF4 = 11451 ,
  LIEF::assembly::riscv::PseudoVWMACCSU_VX_MF4_MASK = 11452 , LIEF::assembly::riscv::PseudoVWMACCSU_VX_MF8 = 11453 , LIEF::assembly::riscv::PseudoVWMACCSU_VX_MF8_MASK = 11454 , LIEF::assembly::riscv::PseudoVWMACCUS_VX_M1 = 11455 ,
  LIEF::assembly::riscv::PseudoVWMACCUS_VX_M1_MASK = 11456 , LIEF::assembly::riscv::PseudoVWMACCUS_VX_M2 = 11457 , LIEF::assembly::riscv::PseudoVWMACCUS_VX_M2_MASK = 11458 , LIEF::assembly::riscv::PseudoVWMACCUS_VX_M4 = 11459 ,
  LIEF::assembly::riscv::PseudoVWMACCUS_VX_M4_MASK = 11460 , LIEF::assembly::riscv::PseudoVWMACCUS_VX_MF2 = 11461 , LIEF::assembly::riscv::PseudoVWMACCUS_VX_MF2_MASK = 11462 , LIEF::assembly::riscv::PseudoVWMACCUS_VX_MF4 = 11463 ,
  LIEF::assembly::riscv::PseudoVWMACCUS_VX_MF4_MASK = 11464 , LIEF::assembly::riscv::PseudoVWMACCUS_VX_MF8 = 11465 , LIEF::assembly::riscv::PseudoVWMACCUS_VX_MF8_MASK = 11466 , LIEF::assembly::riscv::PseudoVWMACCU_VV_M1 = 11467 ,
  LIEF::assembly::riscv::PseudoVWMACCU_VV_M1_MASK = 11468 , LIEF::assembly::riscv::PseudoVWMACCU_VV_M2 = 11469 , LIEF::assembly::riscv::PseudoVWMACCU_VV_M2_MASK = 11470 , LIEF::assembly::riscv::PseudoVWMACCU_VV_M4 = 11471 ,
  LIEF::assembly::riscv::PseudoVWMACCU_VV_M4_MASK = 11472 , LIEF::assembly::riscv::PseudoVWMACCU_VV_MF2 = 11473 , LIEF::assembly::riscv::PseudoVWMACCU_VV_MF2_MASK = 11474 , LIEF::assembly::riscv::PseudoVWMACCU_VV_MF4 = 11475 ,
  LIEF::assembly::riscv::PseudoVWMACCU_VV_MF4_MASK = 11476 , LIEF::assembly::riscv::PseudoVWMACCU_VV_MF8 = 11477 , LIEF::assembly::riscv::PseudoVWMACCU_VV_MF8_MASK = 11478 , LIEF::assembly::riscv::PseudoVWMACCU_VX_M1 = 11479 ,
  LIEF::assembly::riscv::PseudoVWMACCU_VX_M1_MASK = 11480 , LIEF::assembly::riscv::PseudoVWMACCU_VX_M2 = 11481 , LIEF::assembly::riscv::PseudoVWMACCU_VX_M2_MASK = 11482 , LIEF::assembly::riscv::PseudoVWMACCU_VX_M4 = 11483 ,
  LIEF::assembly::riscv::PseudoVWMACCU_VX_M4_MASK = 11484 , LIEF::assembly::riscv::PseudoVWMACCU_VX_MF2 = 11485 , LIEF::assembly::riscv::PseudoVWMACCU_VX_MF2_MASK = 11486 , LIEF::assembly::riscv::PseudoVWMACCU_VX_MF4 = 11487 ,
  LIEF::assembly::riscv::PseudoVWMACCU_VX_MF4_MASK = 11488 , LIEF::assembly::riscv::PseudoVWMACCU_VX_MF8 = 11489 , LIEF::assembly::riscv::PseudoVWMACCU_VX_MF8_MASK = 11490 , LIEF::assembly::riscv::PseudoVWMACC_VV_M1 = 11491 ,
  LIEF::assembly::riscv::PseudoVWMACC_VV_M1_MASK = 11492 , LIEF::assembly::riscv::PseudoVWMACC_VV_M2 = 11493 , LIEF::assembly::riscv::PseudoVWMACC_VV_M2_MASK = 11494 , LIEF::assembly::riscv::PseudoVWMACC_VV_M4 = 11495 ,
  LIEF::assembly::riscv::PseudoVWMACC_VV_M4_MASK = 11496 , LIEF::assembly::riscv::PseudoVWMACC_VV_MF2 = 11497 , LIEF::assembly::riscv::PseudoVWMACC_VV_MF2_MASK = 11498 , LIEF::assembly::riscv::PseudoVWMACC_VV_MF4 = 11499 ,
  LIEF::assembly::riscv::PseudoVWMACC_VV_MF4_MASK = 11500 , LIEF::assembly::riscv::PseudoVWMACC_VV_MF8 = 11501 , LIEF::assembly::riscv::PseudoVWMACC_VV_MF8_MASK = 11502 , LIEF::assembly::riscv::PseudoVWMACC_VX_M1 = 11503 ,
  LIEF::assembly::riscv::PseudoVWMACC_VX_M1_MASK = 11504 , LIEF::assembly::riscv::PseudoVWMACC_VX_M2 = 11505 , LIEF::assembly::riscv::PseudoVWMACC_VX_M2_MASK = 11506 , LIEF::assembly::riscv::PseudoVWMACC_VX_M4 = 11507 ,
  LIEF::assembly::riscv::PseudoVWMACC_VX_M4_MASK = 11508 , LIEF::assembly::riscv::PseudoVWMACC_VX_MF2 = 11509 , LIEF::assembly::riscv::PseudoVWMACC_VX_MF2_MASK = 11510 , LIEF::assembly::riscv::PseudoVWMACC_VX_MF4 = 11511 ,
  LIEF::assembly::riscv::PseudoVWMACC_VX_MF4_MASK = 11512 , LIEF::assembly::riscv::PseudoVWMACC_VX_MF8 = 11513 , LIEF::assembly::riscv::PseudoVWMACC_VX_MF8_MASK = 11514 , LIEF::assembly::riscv::PseudoVWMULSU_VV_M1 = 11515 ,
  LIEF::assembly::riscv::PseudoVWMULSU_VV_M1_MASK = 11516 , LIEF::assembly::riscv::PseudoVWMULSU_VV_M2 = 11517 , LIEF::assembly::riscv::PseudoVWMULSU_VV_M2_MASK = 11518 , LIEF::assembly::riscv::PseudoVWMULSU_VV_M4 = 11519 ,
  LIEF::assembly::riscv::PseudoVWMULSU_VV_M4_MASK = 11520 , LIEF::assembly::riscv::PseudoVWMULSU_VV_MF2 = 11521 , LIEF::assembly::riscv::PseudoVWMULSU_VV_MF2_MASK = 11522 , LIEF::assembly::riscv::PseudoVWMULSU_VV_MF4 = 11523 ,
  LIEF::assembly::riscv::PseudoVWMULSU_VV_MF4_MASK = 11524 , LIEF::assembly::riscv::PseudoVWMULSU_VV_MF8 = 11525 , LIEF::assembly::riscv::PseudoVWMULSU_VV_MF8_MASK = 11526 , LIEF::assembly::riscv::PseudoVWMULSU_VX_M1 = 11527 ,
  LIEF::assembly::riscv::PseudoVWMULSU_VX_M1_MASK = 11528 , LIEF::assembly::riscv::PseudoVWMULSU_VX_M2 = 11529 , LIEF::assembly::riscv::PseudoVWMULSU_VX_M2_MASK = 11530 , LIEF::assembly::riscv::PseudoVWMULSU_VX_M4 = 11531 ,
  LIEF::assembly::riscv::PseudoVWMULSU_VX_M4_MASK = 11532 , LIEF::assembly::riscv::PseudoVWMULSU_VX_MF2 = 11533 , LIEF::assembly::riscv::PseudoVWMULSU_VX_MF2_MASK = 11534 , LIEF::assembly::riscv::PseudoVWMULSU_VX_MF4 = 11535 ,
  LIEF::assembly::riscv::PseudoVWMULSU_VX_MF4_MASK = 11536 , LIEF::assembly::riscv::PseudoVWMULSU_VX_MF8 = 11537 , LIEF::assembly::riscv::PseudoVWMULSU_VX_MF8_MASK = 11538 , LIEF::assembly::riscv::PseudoVWMULU_VV_M1 = 11539 ,
  LIEF::assembly::riscv::PseudoVWMULU_VV_M1_MASK = 11540 , LIEF::assembly::riscv::PseudoVWMULU_VV_M2 = 11541 , LIEF::assembly::riscv::PseudoVWMULU_VV_M2_MASK = 11542 , LIEF::assembly::riscv::PseudoVWMULU_VV_M4 = 11543 ,
  LIEF::assembly::riscv::PseudoVWMULU_VV_M4_MASK = 11544 , LIEF::assembly::riscv::PseudoVWMULU_VV_MF2 = 11545 , LIEF::assembly::riscv::PseudoVWMULU_VV_MF2_MASK = 11546 , LIEF::assembly::riscv::PseudoVWMULU_VV_MF4 = 11547 ,
  LIEF::assembly::riscv::PseudoVWMULU_VV_MF4_MASK = 11548 , LIEF::assembly::riscv::PseudoVWMULU_VV_MF8 = 11549 , LIEF::assembly::riscv::PseudoVWMULU_VV_MF8_MASK = 11550 , LIEF::assembly::riscv::PseudoVWMULU_VX_M1 = 11551 ,
  LIEF::assembly::riscv::PseudoVWMULU_VX_M1_MASK = 11552 , LIEF::assembly::riscv::PseudoVWMULU_VX_M2 = 11553 , LIEF::assembly::riscv::PseudoVWMULU_VX_M2_MASK = 11554 , LIEF::assembly::riscv::PseudoVWMULU_VX_M4 = 11555 ,
  LIEF::assembly::riscv::PseudoVWMULU_VX_M4_MASK = 11556 , LIEF::assembly::riscv::PseudoVWMULU_VX_MF2 = 11557 , LIEF::assembly::riscv::PseudoVWMULU_VX_MF2_MASK = 11558 , LIEF::assembly::riscv::PseudoVWMULU_VX_MF4 = 11559 ,
  LIEF::assembly::riscv::PseudoVWMULU_VX_MF4_MASK = 11560 , LIEF::assembly::riscv::PseudoVWMULU_VX_MF8 = 11561 , LIEF::assembly::riscv::PseudoVWMULU_VX_MF8_MASK = 11562 , LIEF::assembly::riscv::PseudoVWMUL_VV_M1 = 11563 ,
  LIEF::assembly::riscv::PseudoVWMUL_VV_M1_MASK = 11564 , LIEF::assembly::riscv::PseudoVWMUL_VV_M2 = 11565 , LIEF::assembly::riscv::PseudoVWMUL_VV_M2_MASK = 11566 , LIEF::assembly::riscv::PseudoVWMUL_VV_M4 = 11567 ,
  LIEF::assembly::riscv::PseudoVWMUL_VV_M4_MASK = 11568 , LIEF::assembly::riscv::PseudoVWMUL_VV_MF2 = 11569 , LIEF::assembly::riscv::PseudoVWMUL_VV_MF2_MASK = 11570 , LIEF::assembly::riscv::PseudoVWMUL_VV_MF4 = 11571 ,
  LIEF::assembly::riscv::PseudoVWMUL_VV_MF4_MASK = 11572 , LIEF::assembly::riscv::PseudoVWMUL_VV_MF8 = 11573 , LIEF::assembly::riscv::PseudoVWMUL_VV_MF8_MASK = 11574 , LIEF::assembly::riscv::PseudoVWMUL_VX_M1 = 11575 ,
  LIEF::assembly::riscv::PseudoVWMUL_VX_M1_MASK = 11576 , LIEF::assembly::riscv::PseudoVWMUL_VX_M2 = 11577 , LIEF::assembly::riscv::PseudoVWMUL_VX_M2_MASK = 11578 , LIEF::assembly::riscv::PseudoVWMUL_VX_M4 = 11579 ,
  LIEF::assembly::riscv::PseudoVWMUL_VX_M4_MASK = 11580 , LIEF::assembly::riscv::PseudoVWMUL_VX_MF2 = 11581 , LIEF::assembly::riscv::PseudoVWMUL_VX_MF2_MASK = 11582 , LIEF::assembly::riscv::PseudoVWMUL_VX_MF4 = 11583 ,
  LIEF::assembly::riscv::PseudoVWMUL_VX_MF4_MASK = 11584 , LIEF::assembly::riscv::PseudoVWMUL_VX_MF8 = 11585 , LIEF::assembly::riscv::PseudoVWMUL_VX_MF8_MASK = 11586 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M1_E16 = 11587 ,
  LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M1_E16_MASK = 11588 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M1_E32 = 11589 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M1_E32_MASK = 11590 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M1_E8 = 11591 ,
  LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M1_E8_MASK = 11592 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M2_E16 = 11593 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M2_E16_MASK = 11594 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M2_E32 = 11595 ,
  LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M2_E32_MASK = 11596 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M2_E8 = 11597 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M2_E8_MASK = 11598 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M4_E16 = 11599 ,
  LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M4_E16_MASK = 11600 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M4_E32 = 11601 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M4_E32_MASK = 11602 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M4_E8 = 11603 ,
  LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M4_E8_MASK = 11604 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M8_E16 = 11605 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M8_E16_MASK = 11606 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M8_E32 = 11607 ,
  LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M8_E32_MASK = 11608 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M8_E8 = 11609 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_M8_E8_MASK = 11610 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF2_E16 = 11611 ,
  LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF2_E16_MASK = 11612 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF2_E32 = 11613 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF2_E32_MASK = 11614 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF2_E8 = 11615 ,
  LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF2_E8_MASK = 11616 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF4_E16 = 11617 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF4_E16_MASK = 11618 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF4_E8 = 11619 ,
  LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF4_E8_MASK = 11620 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF8_E8 = 11621 , LIEF::assembly::riscv::PseudoVWREDSUMU_VS_MF8_E8_MASK = 11622 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M1_E16 = 11623 ,
  LIEF::assembly::riscv::PseudoVWREDSUM_VS_M1_E16_MASK = 11624 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M1_E32 = 11625 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M1_E32_MASK = 11626 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M1_E8 = 11627 ,
  LIEF::assembly::riscv::PseudoVWREDSUM_VS_M1_E8_MASK = 11628 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M2_E16 = 11629 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M2_E16_MASK = 11630 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M2_E32 = 11631 ,
  LIEF::assembly::riscv::PseudoVWREDSUM_VS_M2_E32_MASK = 11632 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M2_E8 = 11633 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M2_E8_MASK = 11634 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M4_E16 = 11635 ,
  LIEF::assembly::riscv::PseudoVWREDSUM_VS_M4_E16_MASK = 11636 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M4_E32 = 11637 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M4_E32_MASK = 11638 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M4_E8 = 11639 ,
  LIEF::assembly::riscv::PseudoVWREDSUM_VS_M4_E8_MASK = 11640 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M8_E16 = 11641 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M8_E16_MASK = 11642 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M8_E32 = 11643 ,
  LIEF::assembly::riscv::PseudoVWREDSUM_VS_M8_E32_MASK = 11644 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M8_E8 = 11645 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_M8_E8_MASK = 11646 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF2_E16 = 11647 ,
  LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF2_E16_MASK = 11648 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF2_E32 = 11649 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF2_E32_MASK = 11650 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF2_E8 = 11651 ,
  LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF2_E8_MASK = 11652 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF4_E16 = 11653 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF4_E16_MASK = 11654 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF4_E8 = 11655 ,
  LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF4_E8_MASK = 11656 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF8_E8 = 11657 , LIEF::assembly::riscv::PseudoVWREDSUM_VS_MF8_E8_MASK = 11658 , LIEF::assembly::riscv::PseudoVWSLL_VI_M1 = 11659 ,
  LIEF::assembly::riscv::PseudoVWSLL_VI_M1_MASK = 11660 , LIEF::assembly::riscv::PseudoVWSLL_VI_M2 = 11661 , LIEF::assembly::riscv::PseudoVWSLL_VI_M2_MASK = 11662 , LIEF::assembly::riscv::PseudoVWSLL_VI_M4 = 11663 ,
  LIEF::assembly::riscv::PseudoVWSLL_VI_M4_MASK = 11664 , LIEF::assembly::riscv::PseudoVWSLL_VI_MF2 = 11665 , LIEF::assembly::riscv::PseudoVWSLL_VI_MF2_MASK = 11666 , LIEF::assembly::riscv::PseudoVWSLL_VI_MF4 = 11667 ,
  LIEF::assembly::riscv::PseudoVWSLL_VI_MF4_MASK = 11668 , LIEF::assembly::riscv::PseudoVWSLL_VI_MF8 = 11669 , LIEF::assembly::riscv::PseudoVWSLL_VI_MF8_MASK = 11670 , LIEF::assembly::riscv::PseudoVWSLL_VV_M1 = 11671 ,
  LIEF::assembly::riscv::PseudoVWSLL_VV_M1_MASK = 11672 , LIEF::assembly::riscv::PseudoVWSLL_VV_M2 = 11673 , LIEF::assembly::riscv::PseudoVWSLL_VV_M2_MASK = 11674 , LIEF::assembly::riscv::PseudoVWSLL_VV_M4 = 11675 ,
  LIEF::assembly::riscv::PseudoVWSLL_VV_M4_MASK = 11676 , LIEF::assembly::riscv::PseudoVWSLL_VV_MF2 = 11677 , LIEF::assembly::riscv::PseudoVWSLL_VV_MF2_MASK = 11678 , LIEF::assembly::riscv::PseudoVWSLL_VV_MF4 = 11679 ,
  LIEF::assembly::riscv::PseudoVWSLL_VV_MF4_MASK = 11680 , LIEF::assembly::riscv::PseudoVWSLL_VV_MF8 = 11681 , LIEF::assembly::riscv::PseudoVWSLL_VV_MF8_MASK = 11682 , LIEF::assembly::riscv::PseudoVWSLL_VX_M1 = 11683 ,
  LIEF::assembly::riscv::PseudoVWSLL_VX_M1_MASK = 11684 , LIEF::assembly::riscv::PseudoVWSLL_VX_M2 = 11685 , LIEF::assembly::riscv::PseudoVWSLL_VX_M2_MASK = 11686 , LIEF::assembly::riscv::PseudoVWSLL_VX_M4 = 11687 ,
  LIEF::assembly::riscv::PseudoVWSLL_VX_M4_MASK = 11688 , LIEF::assembly::riscv::PseudoVWSLL_VX_MF2 = 11689 , LIEF::assembly::riscv::PseudoVWSLL_VX_MF2_MASK = 11690 , LIEF::assembly::riscv::PseudoVWSLL_VX_MF4 = 11691 ,
  LIEF::assembly::riscv::PseudoVWSLL_VX_MF4_MASK = 11692 , LIEF::assembly::riscv::PseudoVWSLL_VX_MF8 = 11693 , LIEF::assembly::riscv::PseudoVWSLL_VX_MF8_MASK = 11694 , LIEF::assembly::riscv::PseudoVWSUBU_VV_M1 = 11695 ,
  LIEF::assembly::riscv::PseudoVWSUBU_VV_M1_MASK = 11696 , LIEF::assembly::riscv::PseudoVWSUBU_VV_M2 = 11697 , LIEF::assembly::riscv::PseudoVWSUBU_VV_M2_MASK = 11698 , LIEF::assembly::riscv::PseudoVWSUBU_VV_M4 = 11699 ,
  LIEF::assembly::riscv::PseudoVWSUBU_VV_M4_MASK = 11700 , LIEF::assembly::riscv::PseudoVWSUBU_VV_MF2 = 11701 , LIEF::assembly::riscv::PseudoVWSUBU_VV_MF2_MASK = 11702 , LIEF::assembly::riscv::PseudoVWSUBU_VV_MF4 = 11703 ,
  LIEF::assembly::riscv::PseudoVWSUBU_VV_MF4_MASK = 11704 , LIEF::assembly::riscv::PseudoVWSUBU_VV_MF8 = 11705 , LIEF::assembly::riscv::PseudoVWSUBU_VV_MF8_MASK = 11706 , LIEF::assembly::riscv::PseudoVWSUBU_VX_M1 = 11707 ,
  LIEF::assembly::riscv::PseudoVWSUBU_VX_M1_MASK = 11708 , LIEF::assembly::riscv::PseudoVWSUBU_VX_M2 = 11709 , LIEF::assembly::riscv::PseudoVWSUBU_VX_M2_MASK = 11710 , LIEF::assembly::riscv::PseudoVWSUBU_VX_M4 = 11711 ,
  LIEF::assembly::riscv::PseudoVWSUBU_VX_M4_MASK = 11712 , LIEF::assembly::riscv::PseudoVWSUBU_VX_MF2 = 11713 , LIEF::assembly::riscv::PseudoVWSUBU_VX_MF2_MASK = 11714 , LIEF::assembly::riscv::PseudoVWSUBU_VX_MF4 = 11715 ,
  LIEF::assembly::riscv::PseudoVWSUBU_VX_MF4_MASK = 11716 , LIEF::assembly::riscv::PseudoVWSUBU_VX_MF8 = 11717 , LIEF::assembly::riscv::PseudoVWSUBU_VX_MF8_MASK = 11718 , LIEF::assembly::riscv::PseudoVWSUBU_WV_M1 = 11719 ,
  LIEF::assembly::riscv::PseudoVWSUBU_WV_M1_MASK = 11720 , LIEF::assembly::riscv::PseudoVWSUBU_WV_M1_MASK_TIED = 11721 , LIEF::assembly::riscv::PseudoVWSUBU_WV_M1_TIED = 11722 , LIEF::assembly::riscv::PseudoVWSUBU_WV_M2 = 11723 ,
  LIEF::assembly::riscv::PseudoVWSUBU_WV_M2_MASK = 11724 , LIEF::assembly::riscv::PseudoVWSUBU_WV_M2_MASK_TIED = 11725 , LIEF::assembly::riscv::PseudoVWSUBU_WV_M2_TIED = 11726 , LIEF::assembly::riscv::PseudoVWSUBU_WV_M4 = 11727 ,
  LIEF::assembly::riscv::PseudoVWSUBU_WV_M4_MASK = 11728 , LIEF::assembly::riscv::PseudoVWSUBU_WV_M4_MASK_TIED = 11729 , LIEF::assembly::riscv::PseudoVWSUBU_WV_M4_TIED = 11730 , LIEF::assembly::riscv::PseudoVWSUBU_WV_MF2 = 11731 ,
  LIEF::assembly::riscv::PseudoVWSUBU_WV_MF2_MASK = 11732 , LIEF::assembly::riscv::PseudoVWSUBU_WV_MF2_MASK_TIED = 11733 , LIEF::assembly::riscv::PseudoVWSUBU_WV_MF2_TIED = 11734 , LIEF::assembly::riscv::PseudoVWSUBU_WV_MF4 = 11735 ,
  LIEF::assembly::riscv::PseudoVWSUBU_WV_MF4_MASK = 11736 , LIEF::assembly::riscv::PseudoVWSUBU_WV_MF4_MASK_TIED = 11737 , LIEF::assembly::riscv::PseudoVWSUBU_WV_MF4_TIED = 11738 , LIEF::assembly::riscv::PseudoVWSUBU_WV_MF8 = 11739 ,
  LIEF::assembly::riscv::PseudoVWSUBU_WV_MF8_MASK = 11740 , LIEF::assembly::riscv::PseudoVWSUBU_WV_MF8_MASK_TIED = 11741 , LIEF::assembly::riscv::PseudoVWSUBU_WV_MF8_TIED = 11742 , LIEF::assembly::riscv::PseudoVWSUBU_WX_M1 = 11743 ,
  LIEF::assembly::riscv::PseudoVWSUBU_WX_M1_MASK = 11744 , LIEF::assembly::riscv::PseudoVWSUBU_WX_M2 = 11745 , LIEF::assembly::riscv::PseudoVWSUBU_WX_M2_MASK = 11746 , LIEF::assembly::riscv::PseudoVWSUBU_WX_M4 = 11747 ,
  LIEF::assembly::riscv::PseudoVWSUBU_WX_M4_MASK = 11748 , LIEF::assembly::riscv::PseudoVWSUBU_WX_MF2 = 11749 , LIEF::assembly::riscv::PseudoVWSUBU_WX_MF2_MASK = 11750 , LIEF::assembly::riscv::PseudoVWSUBU_WX_MF4 = 11751 ,
  LIEF::assembly::riscv::PseudoVWSUBU_WX_MF4_MASK = 11752 , LIEF::assembly::riscv::PseudoVWSUBU_WX_MF8 = 11753 , LIEF::assembly::riscv::PseudoVWSUBU_WX_MF8_MASK = 11754 , LIEF::assembly::riscv::PseudoVWSUB_VV_M1 = 11755 ,
  LIEF::assembly::riscv::PseudoVWSUB_VV_M1_MASK = 11756 , LIEF::assembly::riscv::PseudoVWSUB_VV_M2 = 11757 , LIEF::assembly::riscv::PseudoVWSUB_VV_M2_MASK = 11758 , LIEF::assembly::riscv::PseudoVWSUB_VV_M4 = 11759 ,
  LIEF::assembly::riscv::PseudoVWSUB_VV_M4_MASK = 11760 , LIEF::assembly::riscv::PseudoVWSUB_VV_MF2 = 11761 , LIEF::assembly::riscv::PseudoVWSUB_VV_MF2_MASK = 11762 , LIEF::assembly::riscv::PseudoVWSUB_VV_MF4 = 11763 ,
  LIEF::assembly::riscv::PseudoVWSUB_VV_MF4_MASK = 11764 , LIEF::assembly::riscv::PseudoVWSUB_VV_MF8 = 11765 , LIEF::assembly::riscv::PseudoVWSUB_VV_MF8_MASK = 11766 , LIEF::assembly::riscv::PseudoVWSUB_VX_M1 = 11767 ,
  LIEF::assembly::riscv::PseudoVWSUB_VX_M1_MASK = 11768 , LIEF::assembly::riscv::PseudoVWSUB_VX_M2 = 11769 , LIEF::assembly::riscv::PseudoVWSUB_VX_M2_MASK = 11770 , LIEF::assembly::riscv::PseudoVWSUB_VX_M4 = 11771 ,
  LIEF::assembly::riscv::PseudoVWSUB_VX_M4_MASK = 11772 , LIEF::assembly::riscv::PseudoVWSUB_VX_MF2 = 11773 , LIEF::assembly::riscv::PseudoVWSUB_VX_MF2_MASK = 11774 , LIEF::assembly::riscv::PseudoVWSUB_VX_MF4 = 11775 ,
  LIEF::assembly::riscv::PseudoVWSUB_VX_MF4_MASK = 11776 , LIEF::assembly::riscv::PseudoVWSUB_VX_MF8 = 11777 , LIEF::assembly::riscv::PseudoVWSUB_VX_MF8_MASK = 11778 , LIEF::assembly::riscv::PseudoVWSUB_WV_M1 = 11779 ,
  LIEF::assembly::riscv::PseudoVWSUB_WV_M1_MASK = 11780 , LIEF::assembly::riscv::PseudoVWSUB_WV_M1_MASK_TIED = 11781 , LIEF::assembly::riscv::PseudoVWSUB_WV_M1_TIED = 11782 , LIEF::assembly::riscv::PseudoVWSUB_WV_M2 = 11783 ,
  LIEF::assembly::riscv::PseudoVWSUB_WV_M2_MASK = 11784 , LIEF::assembly::riscv::PseudoVWSUB_WV_M2_MASK_TIED = 11785 , LIEF::assembly::riscv::PseudoVWSUB_WV_M2_TIED = 11786 , LIEF::assembly::riscv::PseudoVWSUB_WV_M4 = 11787 ,
  LIEF::assembly::riscv::PseudoVWSUB_WV_M4_MASK = 11788 , LIEF::assembly::riscv::PseudoVWSUB_WV_M4_MASK_TIED = 11789 , LIEF::assembly::riscv::PseudoVWSUB_WV_M4_TIED = 11790 , LIEF::assembly::riscv::PseudoVWSUB_WV_MF2 = 11791 ,
  LIEF::assembly::riscv::PseudoVWSUB_WV_MF2_MASK = 11792 , LIEF::assembly::riscv::PseudoVWSUB_WV_MF2_MASK_TIED = 11793 , LIEF::assembly::riscv::PseudoVWSUB_WV_MF2_TIED = 11794 , LIEF::assembly::riscv::PseudoVWSUB_WV_MF4 = 11795 ,
  LIEF::assembly::riscv::PseudoVWSUB_WV_MF4_MASK = 11796 , LIEF::assembly::riscv::PseudoVWSUB_WV_MF4_MASK_TIED = 11797 , LIEF::assembly::riscv::PseudoVWSUB_WV_MF4_TIED = 11798 , LIEF::assembly::riscv::PseudoVWSUB_WV_MF8 = 11799 ,
  LIEF::assembly::riscv::PseudoVWSUB_WV_MF8_MASK = 11800 , LIEF::assembly::riscv::PseudoVWSUB_WV_MF8_MASK_TIED = 11801 , LIEF::assembly::riscv::PseudoVWSUB_WV_MF8_TIED = 11802 , LIEF::assembly::riscv::PseudoVWSUB_WX_M1 = 11803 ,
  LIEF::assembly::riscv::PseudoVWSUB_WX_M1_MASK = 11804 , LIEF::assembly::riscv::PseudoVWSUB_WX_M2 = 11805 , LIEF::assembly::riscv::PseudoVWSUB_WX_M2_MASK = 11806 , LIEF::assembly::riscv::PseudoVWSUB_WX_M4 = 11807 ,
  LIEF::assembly::riscv::PseudoVWSUB_WX_M4_MASK = 11808 , LIEF::assembly::riscv::PseudoVWSUB_WX_MF2 = 11809 , LIEF::assembly::riscv::PseudoVWSUB_WX_MF2_MASK = 11810 , LIEF::assembly::riscv::PseudoVWSUB_WX_MF4 = 11811 ,
  LIEF::assembly::riscv::PseudoVWSUB_WX_MF4_MASK = 11812 , LIEF::assembly::riscv::PseudoVWSUB_WX_MF8 = 11813 , LIEF::assembly::riscv::PseudoVWSUB_WX_MF8_MASK = 11814 , LIEF::assembly::riscv::PseudoVXOR_VI_M1 = 11815 ,
  LIEF::assembly::riscv::PseudoVXOR_VI_M1_MASK = 11816 , LIEF::assembly::riscv::PseudoVXOR_VI_M2 = 11817 , LIEF::assembly::riscv::PseudoVXOR_VI_M2_MASK = 11818 , LIEF::assembly::riscv::PseudoVXOR_VI_M4 = 11819 ,
  LIEF::assembly::riscv::PseudoVXOR_VI_M4_MASK = 11820 , LIEF::assembly::riscv::PseudoVXOR_VI_M8 = 11821 , LIEF::assembly::riscv::PseudoVXOR_VI_M8_MASK = 11822 , LIEF::assembly::riscv::PseudoVXOR_VI_MF2 = 11823 ,
  LIEF::assembly::riscv::PseudoVXOR_VI_MF2_MASK = 11824 , LIEF::assembly::riscv::PseudoVXOR_VI_MF4 = 11825 , LIEF::assembly::riscv::PseudoVXOR_VI_MF4_MASK = 11826 , LIEF::assembly::riscv::PseudoVXOR_VI_MF8 = 11827 ,
  LIEF::assembly::riscv::PseudoVXOR_VI_MF8_MASK = 11828 , LIEF::assembly::riscv::PseudoVXOR_VV_M1 = 11829 , LIEF::assembly::riscv::PseudoVXOR_VV_M1_MASK = 11830 , LIEF::assembly::riscv::PseudoVXOR_VV_M2 = 11831 ,
  LIEF::assembly::riscv::PseudoVXOR_VV_M2_MASK = 11832 , LIEF::assembly::riscv::PseudoVXOR_VV_M4 = 11833 , LIEF::assembly::riscv::PseudoVXOR_VV_M4_MASK = 11834 , LIEF::assembly::riscv::PseudoVXOR_VV_M8 = 11835 ,
  LIEF::assembly::riscv::PseudoVXOR_VV_M8_MASK = 11836 , LIEF::assembly::riscv::PseudoVXOR_VV_MF2 = 11837 , LIEF::assembly::riscv::PseudoVXOR_VV_MF2_MASK = 11838 , LIEF::assembly::riscv::PseudoVXOR_VV_MF4 = 11839 ,
  LIEF::assembly::riscv::PseudoVXOR_VV_MF4_MASK = 11840 , LIEF::assembly::riscv::PseudoVXOR_VV_MF8 = 11841 , LIEF::assembly::riscv::PseudoVXOR_VV_MF8_MASK = 11842 , LIEF::assembly::riscv::PseudoVXOR_VX_M1 = 11843 ,
  LIEF::assembly::riscv::PseudoVXOR_VX_M1_MASK = 11844 , LIEF::assembly::riscv::PseudoVXOR_VX_M2 = 11845 , LIEF::assembly::riscv::PseudoVXOR_VX_M2_MASK = 11846 , LIEF::assembly::riscv::PseudoVXOR_VX_M4 = 11847 ,
  LIEF::assembly::riscv::PseudoVXOR_VX_M4_MASK = 11848 , LIEF::assembly::riscv::PseudoVXOR_VX_M8 = 11849 , LIEF::assembly::riscv::PseudoVXOR_VX_M8_MASK = 11850 , LIEF::assembly::riscv::PseudoVXOR_VX_MF2 = 11851 ,
  LIEF::assembly::riscv::PseudoVXOR_VX_MF2_MASK = 11852 , LIEF::assembly::riscv::PseudoVXOR_VX_MF4 = 11853 , LIEF::assembly::riscv::PseudoVXOR_VX_MF4_MASK = 11854 , LIEF::assembly::riscv::PseudoVXOR_VX_MF8 = 11855 ,
  LIEF::assembly::riscv::PseudoVXOR_VX_MF8_MASK = 11856 , LIEF::assembly::riscv::PseudoVZEXT_VF2_M1 = 11857 , LIEF::assembly::riscv::PseudoVZEXT_VF2_M1_MASK = 11858 , LIEF::assembly::riscv::PseudoVZEXT_VF2_M2 = 11859 ,
  LIEF::assembly::riscv::PseudoVZEXT_VF2_M2_MASK = 11860 , LIEF::assembly::riscv::PseudoVZEXT_VF2_M4 = 11861 , LIEF::assembly::riscv::PseudoVZEXT_VF2_M4_MASK = 11862 , LIEF::assembly::riscv::PseudoVZEXT_VF2_M8 = 11863 ,
  LIEF::assembly::riscv::PseudoVZEXT_VF2_M8_MASK = 11864 , LIEF::assembly::riscv::PseudoVZEXT_VF2_MF2 = 11865 , LIEF::assembly::riscv::PseudoVZEXT_VF2_MF2_MASK = 11866 , LIEF::assembly::riscv::PseudoVZEXT_VF2_MF4 = 11867 ,
  LIEF::assembly::riscv::PseudoVZEXT_VF2_MF4_MASK = 11868 , LIEF::assembly::riscv::PseudoVZEXT_VF4_M1 = 11869 , LIEF::assembly::riscv::PseudoVZEXT_VF4_M1_MASK = 11870 , LIEF::assembly::riscv::PseudoVZEXT_VF4_M2 = 11871 ,
  LIEF::assembly::riscv::PseudoVZEXT_VF4_M2_MASK = 11872 , LIEF::assembly::riscv::PseudoVZEXT_VF4_M4 = 11873 , LIEF::assembly::riscv::PseudoVZEXT_VF4_M4_MASK = 11874 , LIEF::assembly::riscv::PseudoVZEXT_VF4_M8 = 11875 ,
  LIEF::assembly::riscv::PseudoVZEXT_VF4_M8_MASK = 11876 , LIEF::assembly::riscv::PseudoVZEXT_VF4_MF2 = 11877 , LIEF::assembly::riscv::PseudoVZEXT_VF4_MF2_MASK = 11878 , LIEF::assembly::riscv::PseudoVZEXT_VF8_M1 = 11879 ,
  LIEF::assembly::riscv::PseudoVZEXT_VF8_M1_MASK = 11880 , LIEF::assembly::riscv::PseudoVZEXT_VF8_M2 = 11881 , LIEF::assembly::riscv::PseudoVZEXT_VF8_M2_MASK = 11882 , LIEF::assembly::riscv::PseudoVZEXT_VF8_M4 = 11883 ,
  LIEF::assembly::riscv::PseudoVZEXT_VF8_M4_MASK = 11884 , LIEF::assembly::riscv::PseudoVZEXT_VF8_M8 = 11885 , LIEF::assembly::riscv::PseudoVZEXT_VF8_M8_MASK = 11886 , LIEF::assembly::riscv::PseudoZEXT_H = 11887 ,
  LIEF::assembly::riscv::PseudoZEXT_W = 11888 , LIEF::assembly::riscv::ReadCounterWide = 11889 , LIEF::assembly::riscv::ReadFFLAGS = 11890 , LIEF::assembly::riscv::ReadFRM = 11891 ,
  LIEF::assembly::riscv::Select_FPR16INX_Using_CC_GPR = 11892 , LIEF::assembly::riscv::Select_FPR16_Using_CC_GPR = 11893 , LIEF::assembly::riscv::Select_FPR32INX_Using_CC_GPR = 11894 , LIEF::assembly::riscv::Select_FPR32_Using_CC_GPR = 11895 ,
  LIEF::assembly::riscv::Select_FPR64IN32X_Using_CC_GPR = 11896 , LIEF::assembly::riscv::Select_FPR64INX_Using_CC_GPR = 11897 , LIEF::assembly::riscv::Select_FPR64_Using_CC_GPR = 11898 , LIEF::assembly::riscv::Select_GPR_Using_CC_GPR = 11899 ,
  LIEF::assembly::riscv::Select_GPR_Using_CC_Imm = 11900 , LIEF::assembly::riscv::SplitF64Pseudo = 11901 , LIEF::assembly::riscv::SwapFRMImm = 11902 , LIEF::assembly::riscv::WriteFFLAGS = 11903 ,
  LIEF::assembly::riscv::WriteFRM = 11904 , LIEF::assembly::riscv::WriteFRMImm = 11905 , LIEF::assembly::riscv::WriteVXRMImm = 11906 , LIEF::assembly::riscv::ADD = 11907 ,
  LIEF::assembly::riscv::ADDI = 11908 , LIEF::assembly::riscv::ADDIW = 11909 , LIEF::assembly::riscv::ADDW = 11910 , LIEF::assembly::riscv::ADD_UW = 11911 ,
  LIEF::assembly::riscv::AES32DSI = 11912 , LIEF::assembly::riscv::AES32DSMI = 11913 , LIEF::assembly::riscv::AES32ESI = 11914 , LIEF::assembly::riscv::AES32ESMI = 11915 ,
  LIEF::assembly::riscv::AES64DS = 11916 , LIEF::assembly::riscv::AES64DSM = 11917 , LIEF::assembly::riscv::AES64ES = 11918 , LIEF::assembly::riscv::AES64ESM = 11919 ,
  LIEF::assembly::riscv::AES64IM = 11920 , LIEF::assembly::riscv::AES64KS1I = 11921 , LIEF::assembly::riscv::AES64KS2 = 11922 , LIEF::assembly::riscv::AMOADD_B = 11923 ,
  LIEF::assembly::riscv::AMOADD_B_AQ = 11924 , LIEF::assembly::riscv::AMOADD_B_AQ_RL = 11925 , LIEF::assembly::riscv::AMOADD_B_RL = 11926 , LIEF::assembly::riscv::AMOADD_D = 11927 ,
  LIEF::assembly::riscv::AMOADD_D_AQ = 11928 , LIEF::assembly::riscv::AMOADD_D_AQ_RL = 11929 , LIEF::assembly::riscv::AMOADD_D_RL = 11930 , LIEF::assembly::riscv::AMOADD_H = 11931 ,
  LIEF::assembly::riscv::AMOADD_H_AQ = 11932 , LIEF::assembly::riscv::AMOADD_H_AQ_RL = 11933 , LIEF::assembly::riscv::AMOADD_H_RL = 11934 , LIEF::assembly::riscv::AMOADD_W = 11935 ,
  LIEF::assembly::riscv::AMOADD_W_AQ = 11936 , LIEF::assembly::riscv::AMOADD_W_AQ_RL = 11937 , LIEF::assembly::riscv::AMOADD_W_RL = 11938 , LIEF::assembly::riscv::AMOAND_B = 11939 ,
  LIEF::assembly::riscv::AMOAND_B_AQ = 11940 , LIEF::assembly::riscv::AMOAND_B_AQ_RL = 11941 , LIEF::assembly::riscv::AMOAND_B_RL = 11942 , LIEF::assembly::riscv::AMOAND_D = 11943 ,
  LIEF::assembly::riscv::AMOAND_D_AQ = 11944 , LIEF::assembly::riscv::AMOAND_D_AQ_RL = 11945 , LIEF::assembly::riscv::AMOAND_D_RL = 11946 , LIEF::assembly::riscv::AMOAND_H = 11947 ,
  LIEF::assembly::riscv::AMOAND_H_AQ = 11948 , LIEF::assembly::riscv::AMOAND_H_AQ_RL = 11949 , LIEF::assembly::riscv::AMOAND_H_RL = 11950 , LIEF::assembly::riscv::AMOAND_W = 11951 ,
  LIEF::assembly::riscv::AMOAND_W_AQ = 11952 , LIEF::assembly::riscv::AMOAND_W_AQ_RL = 11953 , LIEF::assembly::riscv::AMOAND_W_RL = 11954 , LIEF::assembly::riscv::AMOCAS_B = 11955 ,
  LIEF::assembly::riscv::AMOCAS_B_AQ = 11956 , LIEF::assembly::riscv::AMOCAS_B_AQ_RL = 11957 , LIEF::assembly::riscv::AMOCAS_B_RL = 11958 , LIEF::assembly::riscv::AMOCAS_D_RV32 = 11959 ,
  LIEF::assembly::riscv::AMOCAS_D_RV32_AQ = 11960 , LIEF::assembly::riscv::AMOCAS_D_RV32_AQ_RL = 11961 , LIEF::assembly::riscv::AMOCAS_D_RV32_RL = 11962 , LIEF::assembly::riscv::AMOCAS_D_RV64 = 11963 ,
  LIEF::assembly::riscv::AMOCAS_D_RV64_AQ = 11964 , LIEF::assembly::riscv::AMOCAS_D_RV64_AQ_RL = 11965 , LIEF::assembly::riscv::AMOCAS_D_RV64_RL = 11966 , LIEF::assembly::riscv::AMOCAS_H = 11967 ,
  LIEF::assembly::riscv::AMOCAS_H_AQ = 11968 , LIEF::assembly::riscv::AMOCAS_H_AQ_RL = 11969 , LIEF::assembly::riscv::AMOCAS_H_RL = 11970 , LIEF::assembly::riscv::AMOCAS_Q = 11971 ,
  LIEF::assembly::riscv::AMOCAS_Q_AQ = 11972 , LIEF::assembly::riscv::AMOCAS_Q_AQ_RL = 11973 , LIEF::assembly::riscv::AMOCAS_Q_RL = 11974 , LIEF::assembly::riscv::AMOCAS_W = 11975 ,
  LIEF::assembly::riscv::AMOCAS_W_AQ = 11976 , LIEF::assembly::riscv::AMOCAS_W_AQ_RL = 11977 , LIEF::assembly::riscv::AMOCAS_W_RL = 11978 , LIEF::assembly::riscv::AMOMAXU_B = 11979 ,
  LIEF::assembly::riscv::AMOMAXU_B_AQ = 11980 , LIEF::assembly::riscv::AMOMAXU_B_AQ_RL = 11981 , LIEF::assembly::riscv::AMOMAXU_B_RL = 11982 , LIEF::assembly::riscv::AMOMAXU_D = 11983 ,
  LIEF::assembly::riscv::AMOMAXU_D_AQ = 11984 , LIEF::assembly::riscv::AMOMAXU_D_AQ_RL = 11985 , LIEF::assembly::riscv::AMOMAXU_D_RL = 11986 , LIEF::assembly::riscv::AMOMAXU_H = 11987 ,
  LIEF::assembly::riscv::AMOMAXU_H_AQ = 11988 , LIEF::assembly::riscv::AMOMAXU_H_AQ_RL = 11989 , LIEF::assembly::riscv::AMOMAXU_H_RL = 11990 , LIEF::assembly::riscv::AMOMAXU_W = 11991 ,
  LIEF::assembly::riscv::AMOMAXU_W_AQ = 11992 , LIEF::assembly::riscv::AMOMAXU_W_AQ_RL = 11993 , LIEF::assembly::riscv::AMOMAXU_W_RL = 11994 , LIEF::assembly::riscv::AMOMAX_B = 11995 ,
  LIEF::assembly::riscv::AMOMAX_B_AQ = 11996 , LIEF::assembly::riscv::AMOMAX_B_AQ_RL = 11997 , LIEF::assembly::riscv::AMOMAX_B_RL = 11998 , LIEF::assembly::riscv::AMOMAX_D = 11999 ,
  LIEF::assembly::riscv::AMOMAX_D_AQ = 12000 , LIEF::assembly::riscv::AMOMAX_D_AQ_RL = 12001 , LIEF::assembly::riscv::AMOMAX_D_RL = 12002 , LIEF::assembly::riscv::AMOMAX_H = 12003 ,
  LIEF::assembly::riscv::AMOMAX_H_AQ = 12004 , LIEF::assembly::riscv::AMOMAX_H_AQ_RL = 12005 , LIEF::assembly::riscv::AMOMAX_H_RL = 12006 , LIEF::assembly::riscv::AMOMAX_W = 12007 ,
  LIEF::assembly::riscv::AMOMAX_W_AQ = 12008 , LIEF::assembly::riscv::AMOMAX_W_AQ_RL = 12009 , LIEF::assembly::riscv::AMOMAX_W_RL = 12010 , LIEF::assembly::riscv::AMOMINU_B = 12011 ,
  LIEF::assembly::riscv::AMOMINU_B_AQ = 12012 , LIEF::assembly::riscv::AMOMINU_B_AQ_RL = 12013 , LIEF::assembly::riscv::AMOMINU_B_RL = 12014 , LIEF::assembly::riscv::AMOMINU_D = 12015 ,
  LIEF::assembly::riscv::AMOMINU_D_AQ = 12016 , LIEF::assembly::riscv::AMOMINU_D_AQ_RL = 12017 , LIEF::assembly::riscv::AMOMINU_D_RL = 12018 , LIEF::assembly::riscv::AMOMINU_H = 12019 ,
  LIEF::assembly::riscv::AMOMINU_H_AQ = 12020 , LIEF::assembly::riscv::AMOMINU_H_AQ_RL = 12021 , LIEF::assembly::riscv::AMOMINU_H_RL = 12022 , LIEF::assembly::riscv::AMOMINU_W = 12023 ,
  LIEF::assembly::riscv::AMOMINU_W_AQ = 12024 , LIEF::assembly::riscv::AMOMINU_W_AQ_RL = 12025 , LIEF::assembly::riscv::AMOMINU_W_RL = 12026 , LIEF::assembly::riscv::AMOMIN_B = 12027 ,
  LIEF::assembly::riscv::AMOMIN_B_AQ = 12028 , LIEF::assembly::riscv::AMOMIN_B_AQ_RL = 12029 , LIEF::assembly::riscv::AMOMIN_B_RL = 12030 , LIEF::assembly::riscv::AMOMIN_D = 12031 ,
  LIEF::assembly::riscv::AMOMIN_D_AQ = 12032 , LIEF::assembly::riscv::AMOMIN_D_AQ_RL = 12033 , LIEF::assembly::riscv::AMOMIN_D_RL = 12034 , LIEF::assembly::riscv::AMOMIN_H = 12035 ,
  LIEF::assembly::riscv::AMOMIN_H_AQ = 12036 , LIEF::assembly::riscv::AMOMIN_H_AQ_RL = 12037 , LIEF::assembly::riscv::AMOMIN_H_RL = 12038 , LIEF::assembly::riscv::AMOMIN_W = 12039 ,
  LIEF::assembly::riscv::AMOMIN_W_AQ = 12040 , LIEF::assembly::riscv::AMOMIN_W_AQ_RL = 12041 , LIEF::assembly::riscv::AMOMIN_W_RL = 12042 , LIEF::assembly::riscv::AMOOR_B = 12043 ,
  LIEF::assembly::riscv::AMOOR_B_AQ = 12044 , LIEF::assembly::riscv::AMOOR_B_AQ_RL = 12045 , LIEF::assembly::riscv::AMOOR_B_RL = 12046 , LIEF::assembly::riscv::AMOOR_D = 12047 ,
  LIEF::assembly::riscv::AMOOR_D_AQ = 12048 , LIEF::assembly::riscv::AMOOR_D_AQ_RL = 12049 , LIEF::assembly::riscv::AMOOR_D_RL = 12050 , LIEF::assembly::riscv::AMOOR_H = 12051 ,
  LIEF::assembly::riscv::AMOOR_H_AQ = 12052 , LIEF::assembly::riscv::AMOOR_H_AQ_RL = 12053 , LIEF::assembly::riscv::AMOOR_H_RL = 12054 , LIEF::assembly::riscv::AMOOR_W = 12055 ,
  LIEF::assembly::riscv::AMOOR_W_AQ = 12056 , LIEF::assembly::riscv::AMOOR_W_AQ_RL = 12057 , LIEF::assembly::riscv::AMOOR_W_RL = 12058 , LIEF::assembly::riscv::AMOSWAP_B = 12059 ,
  LIEF::assembly::riscv::AMOSWAP_B_AQ = 12060 , LIEF::assembly::riscv::AMOSWAP_B_AQ_RL = 12061 , LIEF::assembly::riscv::AMOSWAP_B_RL = 12062 , LIEF::assembly::riscv::AMOSWAP_D = 12063 ,
  LIEF::assembly::riscv::AMOSWAP_D_AQ = 12064 , LIEF::assembly::riscv::AMOSWAP_D_AQ_RL = 12065 , LIEF::assembly::riscv::AMOSWAP_D_RL = 12066 , LIEF::assembly::riscv::AMOSWAP_H = 12067 ,
  LIEF::assembly::riscv::AMOSWAP_H_AQ = 12068 , LIEF::assembly::riscv::AMOSWAP_H_AQ_RL = 12069 , LIEF::assembly::riscv::AMOSWAP_H_RL = 12070 , LIEF::assembly::riscv::AMOSWAP_W = 12071 ,
  LIEF::assembly::riscv::AMOSWAP_W_AQ = 12072 , LIEF::assembly::riscv::AMOSWAP_W_AQ_RL = 12073 , LIEF::assembly::riscv::AMOSWAP_W_RL = 12074 , LIEF::assembly::riscv::AMOXOR_B = 12075 ,
  LIEF::assembly::riscv::AMOXOR_B_AQ = 12076 , LIEF::assembly::riscv::AMOXOR_B_AQ_RL = 12077 , LIEF::assembly::riscv::AMOXOR_B_RL = 12078 , LIEF::assembly::riscv::AMOXOR_D = 12079 ,
  LIEF::assembly::riscv::AMOXOR_D_AQ = 12080 , LIEF::assembly::riscv::AMOXOR_D_AQ_RL = 12081 , LIEF::assembly::riscv::AMOXOR_D_RL = 12082 , LIEF::assembly::riscv::AMOXOR_H = 12083 ,
  LIEF::assembly::riscv::AMOXOR_H_AQ = 12084 , LIEF::assembly::riscv::AMOXOR_H_AQ_RL = 12085 , LIEF::assembly::riscv::AMOXOR_H_RL = 12086 , LIEF::assembly::riscv::AMOXOR_W = 12087 ,
  LIEF::assembly::riscv::AMOXOR_W_AQ = 12088 , LIEF::assembly::riscv::AMOXOR_W_AQ_RL = 12089 , LIEF::assembly::riscv::AMOXOR_W_RL = 12090 , LIEF::assembly::riscv::AND = 12091 ,
  LIEF::assembly::riscv::ANDI = 12092 , LIEF::assembly::riscv::ANDN = 12093 , LIEF::assembly::riscv::AUIPC = 12094 , LIEF::assembly::riscv::BCLR = 12095 ,
  LIEF::assembly::riscv::BCLRI = 12096 , LIEF::assembly::riscv::BEQ = 12097 , LIEF::assembly::riscv::BEXT = 12098 , LIEF::assembly::riscv::BEXTI = 12099 ,
  LIEF::assembly::riscv::BGE = 12100 , LIEF::assembly::riscv::BGEU = 12101 , LIEF::assembly::riscv::BINV = 12102 , LIEF::assembly::riscv::BINVI = 12103 ,
  LIEF::assembly::riscv::BLT = 12104 , LIEF::assembly::riscv::BLTU = 12105 , LIEF::assembly::riscv::BNE = 12106 , LIEF::assembly::riscv::BREV8 = 12107 ,
  LIEF::assembly::riscv::BSET = 12108 , LIEF::assembly::riscv::BSETI = 12109 , LIEF::assembly::riscv::CBO_CLEAN = 12110 , LIEF::assembly::riscv::CBO_FLUSH = 12111 ,
  LIEF::assembly::riscv::CBO_INVAL = 12112 , LIEF::assembly::riscv::CBO_ZERO = 12113 , LIEF::assembly::riscv::CLMUL = 12114 , LIEF::assembly::riscv::CLMULH = 12115 ,
  LIEF::assembly::riscv::CLMULR = 12116 , LIEF::assembly::riscv::CLZ = 12117 , LIEF::assembly::riscv::CLZW = 12118 , LIEF::assembly::riscv::CM_JALT = 12119 ,
  LIEF::assembly::riscv::CM_JT = 12120 , LIEF::assembly::riscv::CM_MVA01S = 12121 , LIEF::assembly::riscv::CM_MVSA01 = 12122 , LIEF::assembly::riscv::CM_POP = 12123 ,
  LIEF::assembly::riscv::CM_POPRET = 12124 , LIEF::assembly::riscv::CM_POPRETZ = 12125 , LIEF::assembly::riscv::CM_PUSH = 12126 , LIEF::assembly::riscv::CPOP = 12127 ,
  LIEF::assembly::riscv::CPOPW = 12128 , LIEF::assembly::riscv::CSRRC = 12129 , LIEF::assembly::riscv::CSRRCI = 12130 , LIEF::assembly::riscv::CSRRS = 12131 ,
  LIEF::assembly::riscv::CSRRSI = 12132 , LIEF::assembly::riscv::CSRRW = 12133 , LIEF::assembly::riscv::CSRRWI = 12134 , LIEF::assembly::riscv::CTZ = 12135 ,
  LIEF::assembly::riscv::CTZW = 12136 , LIEF::assembly::riscv::CV_ABS = 12137 , LIEF::assembly::riscv::CV_ABS_B = 12138 , LIEF::assembly::riscv::CV_ABS_H = 12139 ,
  LIEF::assembly::riscv::CV_ADDN = 12140 , LIEF::assembly::riscv::CV_ADDNR = 12141 , LIEF::assembly::riscv::CV_ADDRN = 12142 , LIEF::assembly::riscv::CV_ADDRNR = 12143 ,
  LIEF::assembly::riscv::CV_ADDUN = 12144 , LIEF::assembly::riscv::CV_ADDUNR = 12145 , LIEF::assembly::riscv::CV_ADDURN = 12146 , LIEF::assembly::riscv::CV_ADDURNR = 12147 ,
  LIEF::assembly::riscv::CV_ADD_B = 12148 , LIEF::assembly::riscv::CV_ADD_DIV2 = 12149 , LIEF::assembly::riscv::CV_ADD_DIV4 = 12150 , LIEF::assembly::riscv::CV_ADD_DIV8 = 12151 ,
  LIEF::assembly::riscv::CV_ADD_H = 12152 , LIEF::assembly::riscv::CV_ADD_SCI_B = 12153 , LIEF::assembly::riscv::CV_ADD_SCI_H = 12154 , LIEF::assembly::riscv::CV_ADD_SC_B = 12155 ,
  LIEF::assembly::riscv::CV_ADD_SC_H = 12156 , LIEF::assembly::riscv::CV_AND_B = 12157 , LIEF::assembly::riscv::CV_AND_H = 12158 , LIEF::assembly::riscv::CV_AND_SCI_B = 12159 ,
  LIEF::assembly::riscv::CV_AND_SCI_H = 12160 , LIEF::assembly::riscv::CV_AND_SC_B = 12161 , LIEF::assembly::riscv::CV_AND_SC_H = 12162 , LIEF::assembly::riscv::CV_AVGU_B = 12163 ,
  LIEF::assembly::riscv::CV_AVGU_H = 12164 , LIEF::assembly::riscv::CV_AVGU_SCI_B = 12165 , LIEF::assembly::riscv::CV_AVGU_SCI_H = 12166 , LIEF::assembly::riscv::CV_AVGU_SC_B = 12167 ,
  LIEF::assembly::riscv::CV_AVGU_SC_H = 12168 , LIEF::assembly::riscv::CV_AVG_B = 12169 , LIEF::assembly::riscv::CV_AVG_H = 12170 , LIEF::assembly::riscv::CV_AVG_SCI_B = 12171 ,
  LIEF::assembly::riscv::CV_AVG_SCI_H = 12172 , LIEF::assembly::riscv::CV_AVG_SC_B = 12173 , LIEF::assembly::riscv::CV_AVG_SC_H = 12174 , LIEF::assembly::riscv::CV_BCLR = 12175 ,
  LIEF::assembly::riscv::CV_BCLRR = 12176 , LIEF::assembly::riscv::CV_BEQIMM = 12177 , LIEF::assembly::riscv::CV_BITREV = 12178 , LIEF::assembly::riscv::CV_BNEIMM = 12179 ,
  LIEF::assembly::riscv::CV_BSET = 12180 , LIEF::assembly::riscv::CV_BSETR = 12181 , LIEF::assembly::riscv::CV_CLB = 12182 , LIEF::assembly::riscv::CV_CLIP = 12183 ,
  LIEF::assembly::riscv::CV_CLIPR = 12184 , LIEF::assembly::riscv::CV_CLIPU = 12185 , LIEF::assembly::riscv::CV_CLIPUR = 12186 , LIEF::assembly::riscv::CV_CMPEQ_B = 12187 ,
  LIEF::assembly::riscv::CV_CMPEQ_H = 12188 , LIEF::assembly::riscv::CV_CMPEQ_SCI_B = 12189 , LIEF::assembly::riscv::CV_CMPEQ_SCI_H = 12190 , LIEF::assembly::riscv::CV_CMPEQ_SC_B = 12191 ,
  LIEF::assembly::riscv::CV_CMPEQ_SC_H = 12192 , LIEF::assembly::riscv::CV_CMPGEU_B = 12193 , LIEF::assembly::riscv::CV_CMPGEU_H = 12194 , LIEF::assembly::riscv::CV_CMPGEU_SCI_B = 12195 ,
  LIEF::assembly::riscv::CV_CMPGEU_SCI_H = 12196 , LIEF::assembly::riscv::CV_CMPGEU_SC_B = 12197 , LIEF::assembly::riscv::CV_CMPGEU_SC_H = 12198 , LIEF::assembly::riscv::CV_CMPGE_B = 12199 ,
  LIEF::assembly::riscv::CV_CMPGE_H = 12200 , LIEF::assembly::riscv::CV_CMPGE_SCI_B = 12201 , LIEF::assembly::riscv::CV_CMPGE_SCI_H = 12202 , LIEF::assembly::riscv::CV_CMPGE_SC_B = 12203 ,
  LIEF::assembly::riscv::CV_CMPGE_SC_H = 12204 , LIEF::assembly::riscv::CV_CMPGTU_B = 12205 , LIEF::assembly::riscv::CV_CMPGTU_H = 12206 , LIEF::assembly::riscv::CV_CMPGTU_SCI_B = 12207 ,
  LIEF::assembly::riscv::CV_CMPGTU_SCI_H = 12208 , LIEF::assembly::riscv::CV_CMPGTU_SC_B = 12209 , LIEF::assembly::riscv::CV_CMPGTU_SC_H = 12210 , LIEF::assembly::riscv::CV_CMPGT_B = 12211 ,
  LIEF::assembly::riscv::CV_CMPGT_H = 12212 , LIEF::assembly::riscv::CV_CMPGT_SCI_B = 12213 , LIEF::assembly::riscv::CV_CMPGT_SCI_H = 12214 , LIEF::assembly::riscv::CV_CMPGT_SC_B = 12215 ,
  LIEF::assembly::riscv::CV_CMPGT_SC_H = 12216 , LIEF::assembly::riscv::CV_CMPLEU_B = 12217 , LIEF::assembly::riscv::CV_CMPLEU_H = 12218 , LIEF::assembly::riscv::CV_CMPLEU_SCI_B = 12219 ,
  LIEF::assembly::riscv::CV_CMPLEU_SCI_H = 12220 , LIEF::assembly::riscv::CV_CMPLEU_SC_B = 12221 , LIEF::assembly::riscv::CV_CMPLEU_SC_H = 12222 , LIEF::assembly::riscv::CV_CMPLE_B = 12223 ,
  LIEF::assembly::riscv::CV_CMPLE_H = 12224 , LIEF::assembly::riscv::CV_CMPLE_SCI_B = 12225 , LIEF::assembly::riscv::CV_CMPLE_SCI_H = 12226 , LIEF::assembly::riscv::CV_CMPLE_SC_B = 12227 ,
  LIEF::assembly::riscv::CV_CMPLE_SC_H = 12228 , LIEF::assembly::riscv::CV_CMPLTU_B = 12229 , LIEF::assembly::riscv::CV_CMPLTU_H = 12230 , LIEF::assembly::riscv::CV_CMPLTU_SCI_B = 12231 ,
  LIEF::assembly::riscv::CV_CMPLTU_SCI_H = 12232 , LIEF::assembly::riscv::CV_CMPLTU_SC_B = 12233 , LIEF::assembly::riscv::CV_CMPLTU_SC_H = 12234 , LIEF::assembly::riscv::CV_CMPLT_B = 12235 ,
  LIEF::assembly::riscv::CV_CMPLT_H = 12236 , LIEF::assembly::riscv::CV_CMPLT_SCI_B = 12237 , LIEF::assembly::riscv::CV_CMPLT_SCI_H = 12238 , LIEF::assembly::riscv::CV_CMPLT_SC_B = 12239 ,
  LIEF::assembly::riscv::CV_CMPLT_SC_H = 12240 , LIEF::assembly::riscv::CV_CMPNE_B = 12241 , LIEF::assembly::riscv::CV_CMPNE_H = 12242 , LIEF::assembly::riscv::CV_CMPNE_SCI_B = 12243 ,
  LIEF::assembly::riscv::CV_CMPNE_SCI_H = 12244 , LIEF::assembly::riscv::CV_CMPNE_SC_B = 12245 , LIEF::assembly::riscv::CV_CMPNE_SC_H = 12246 , LIEF::assembly::riscv::CV_CNT = 12247 ,
  LIEF::assembly::riscv::CV_CPLXCONJ = 12248 , LIEF::assembly::riscv::CV_CPLXMUL_I = 12249 , LIEF::assembly::riscv::CV_CPLXMUL_I_DIV2 = 12250 , LIEF::assembly::riscv::CV_CPLXMUL_I_DIV4 = 12251 ,
  LIEF::assembly::riscv::CV_CPLXMUL_I_DIV8 = 12252 , LIEF::assembly::riscv::CV_CPLXMUL_R = 12253 , LIEF::assembly::riscv::CV_CPLXMUL_R_DIV2 = 12254 , LIEF::assembly::riscv::CV_CPLXMUL_R_DIV4 = 12255 ,
  LIEF::assembly::riscv::CV_CPLXMUL_R_DIV8 = 12256 , LIEF::assembly::riscv::CV_DOTSP_B = 12257 , LIEF::assembly::riscv::CV_DOTSP_H = 12258 , LIEF::assembly::riscv::CV_DOTSP_SCI_B = 12259 ,
  LIEF::assembly::riscv::CV_DOTSP_SCI_H = 12260 , LIEF::assembly::riscv::CV_DOTSP_SC_B = 12261 , LIEF::assembly::riscv::CV_DOTSP_SC_H = 12262 , LIEF::assembly::riscv::CV_DOTUP_B = 12263 ,
  LIEF::assembly::riscv::CV_DOTUP_H = 12264 , LIEF::assembly::riscv::CV_DOTUP_SCI_B = 12265 , LIEF::assembly::riscv::CV_DOTUP_SCI_H = 12266 , LIEF::assembly::riscv::CV_DOTUP_SC_B = 12267 ,
  LIEF::assembly::riscv::CV_DOTUP_SC_H = 12268 , LIEF::assembly::riscv::CV_DOTUSP_B = 12269 , LIEF::assembly::riscv::CV_DOTUSP_H = 12270 , LIEF::assembly::riscv::CV_DOTUSP_SCI_B = 12271 ,
  LIEF::assembly::riscv::CV_DOTUSP_SCI_H = 12272 , LIEF::assembly::riscv::CV_DOTUSP_SC_B = 12273 , LIEF::assembly::riscv::CV_DOTUSP_SC_H = 12274 , LIEF::assembly::riscv::CV_ELW = 12275 ,
  LIEF::assembly::riscv::CV_EXTBS = 12276 , LIEF::assembly::riscv::CV_EXTBZ = 12277 , LIEF::assembly::riscv::CV_EXTHS = 12278 , LIEF::assembly::riscv::CV_EXTHZ = 12279 ,
  LIEF::assembly::riscv::CV_EXTRACT = 12280 , LIEF::assembly::riscv::CV_EXTRACTR = 12281 , LIEF::assembly::riscv::CV_EXTRACTU = 12282 , LIEF::assembly::riscv::CV_EXTRACTUR = 12283 ,
  LIEF::assembly::riscv::CV_EXTRACTU_B = 12284 , LIEF::assembly::riscv::CV_EXTRACTU_H = 12285 , LIEF::assembly::riscv::CV_EXTRACT_B = 12286 , LIEF::assembly::riscv::CV_EXTRACT_H = 12287 ,
  LIEF::assembly::riscv::CV_FF1 = 12288 , LIEF::assembly::riscv::CV_FL1 = 12289 , LIEF::assembly::riscv::CV_INSERT = 12290 , LIEF::assembly::riscv::CV_INSERTR = 12291 ,
  LIEF::assembly::riscv::CV_INSERT_B = 12292 , LIEF::assembly::riscv::CV_INSERT_H = 12293 , LIEF::assembly::riscv::CV_LBU_ri_inc = 12294 , LIEF::assembly::riscv::CV_LBU_rr = 12295 ,
  LIEF::assembly::riscv::CV_LBU_rr_inc = 12296 , LIEF::assembly::riscv::CV_LB_ri_inc = 12297 , LIEF::assembly::riscv::CV_LB_rr = 12298 , LIEF::assembly::riscv::CV_LB_rr_inc = 12299 ,
  LIEF::assembly::riscv::CV_LHU_ri_inc = 12300 , LIEF::assembly::riscv::CV_LHU_rr = 12301 , LIEF::assembly::riscv::CV_LHU_rr_inc = 12302 , LIEF::assembly::riscv::CV_LH_ri_inc = 12303 ,
  LIEF::assembly::riscv::CV_LH_rr = 12304 , LIEF::assembly::riscv::CV_LH_rr_inc = 12305 , LIEF::assembly::riscv::CV_LW_ri_inc = 12306 , LIEF::assembly::riscv::CV_LW_rr = 12307 ,
  LIEF::assembly::riscv::CV_LW_rr_inc = 12308 , LIEF::assembly::riscv::CV_MAC = 12309 , LIEF::assembly::riscv::CV_MACHHSN = 12310 , LIEF::assembly::riscv::CV_MACHHSRN = 12311 ,
  LIEF::assembly::riscv::CV_MACHHUN = 12312 , LIEF::assembly::riscv::CV_MACHHURN = 12313 , LIEF::assembly::riscv::CV_MACSN = 12314 , LIEF::assembly::riscv::CV_MACSRN = 12315 ,
  LIEF::assembly::riscv::CV_MACUN = 12316 , LIEF::assembly::riscv::CV_MACURN = 12317 , LIEF::assembly::riscv::CV_MAX = 12318 , LIEF::assembly::riscv::CV_MAXU = 12319 ,
  LIEF::assembly::riscv::CV_MAXU_B = 12320 , LIEF::assembly::riscv::CV_MAXU_H = 12321 , LIEF::assembly::riscv::CV_MAXU_SCI_B = 12322 , LIEF::assembly::riscv::CV_MAXU_SCI_H = 12323 ,
  LIEF::assembly::riscv::CV_MAXU_SC_B = 12324 , LIEF::assembly::riscv::CV_MAXU_SC_H = 12325 , LIEF::assembly::riscv::CV_MAX_B = 12326 , LIEF::assembly::riscv::CV_MAX_H = 12327 ,
  LIEF::assembly::riscv::CV_MAX_SCI_B = 12328 , LIEF::assembly::riscv::CV_MAX_SCI_H = 12329 , LIEF::assembly::riscv::CV_MAX_SC_B = 12330 , LIEF::assembly::riscv::CV_MAX_SC_H = 12331 ,
  LIEF::assembly::riscv::CV_MIN = 12332 , LIEF::assembly::riscv::CV_MINU = 12333 , LIEF::assembly::riscv::CV_MINU_B = 12334 , LIEF::assembly::riscv::CV_MINU_H = 12335 ,
  LIEF::assembly::riscv::CV_MINU_SCI_B = 12336 , LIEF::assembly::riscv::CV_MINU_SCI_H = 12337 , LIEF::assembly::riscv::CV_MINU_SC_B = 12338 , LIEF::assembly::riscv::CV_MINU_SC_H = 12339 ,
  LIEF::assembly::riscv::CV_MIN_B = 12340 , LIEF::assembly::riscv::CV_MIN_H = 12341 , LIEF::assembly::riscv::CV_MIN_SCI_B = 12342 , LIEF::assembly::riscv::CV_MIN_SCI_H = 12343 ,
  LIEF::assembly::riscv::CV_MIN_SC_B = 12344 , LIEF::assembly::riscv::CV_MIN_SC_H = 12345 , LIEF::assembly::riscv::CV_MSU = 12346 , LIEF::assembly::riscv::CV_MULHHSN = 12347 ,
  LIEF::assembly::riscv::CV_MULHHSRN = 12348 , LIEF::assembly::riscv::CV_MULHHUN = 12349 , LIEF::assembly::riscv::CV_MULHHURN = 12350 , LIEF::assembly::riscv::CV_MULSN = 12351 ,
  LIEF::assembly::riscv::CV_MULSRN = 12352 , LIEF::assembly::riscv::CV_MULUN = 12353 , LIEF::assembly::riscv::CV_MULURN = 12354 , LIEF::assembly::riscv::CV_OR_B = 12355 ,
  LIEF::assembly::riscv::CV_OR_H = 12356 , LIEF::assembly::riscv::CV_OR_SCI_B = 12357 , LIEF::assembly::riscv::CV_OR_SCI_H = 12358 , LIEF::assembly::riscv::CV_OR_SC_B = 12359 ,
  LIEF::assembly::riscv::CV_OR_SC_H = 12360 , LIEF::assembly::riscv::CV_PACK = 12361 , LIEF::assembly::riscv::CV_PACKHI_B = 12362 , LIEF::assembly::riscv::CV_PACKLO_B = 12363 ,
  LIEF::assembly::riscv::CV_PACK_H = 12364 , LIEF::assembly::riscv::CV_ROR = 12365 , LIEF::assembly::riscv::CV_SB_ri_inc = 12366 , LIEF::assembly::riscv::CV_SB_rr = 12367 ,
  LIEF::assembly::riscv::CV_SB_rr_inc = 12368 , LIEF::assembly::riscv::CV_SDOTSP_B = 12369 , LIEF::assembly::riscv::CV_SDOTSP_H = 12370 , LIEF::assembly::riscv::CV_SDOTSP_SCI_B = 12371 ,
  LIEF::assembly::riscv::CV_SDOTSP_SCI_H = 12372 , LIEF::assembly::riscv::CV_SDOTSP_SC_B = 12373 , LIEF::assembly::riscv::CV_SDOTSP_SC_H = 12374 , LIEF::assembly::riscv::CV_SDOTUP_B = 12375 ,
  LIEF::assembly::riscv::CV_SDOTUP_H = 12376 , LIEF::assembly::riscv::CV_SDOTUP_SCI_B = 12377 , LIEF::assembly::riscv::CV_SDOTUP_SCI_H = 12378 , LIEF::assembly::riscv::CV_SDOTUP_SC_B = 12379 ,
  LIEF::assembly::riscv::CV_SDOTUP_SC_H = 12380 , LIEF::assembly::riscv::CV_SDOTUSP_B = 12381 , LIEF::assembly::riscv::CV_SDOTUSP_H = 12382 , LIEF::assembly::riscv::CV_SDOTUSP_SCI_B = 12383 ,
  LIEF::assembly::riscv::CV_SDOTUSP_SCI_H = 12384 , LIEF::assembly::riscv::CV_SDOTUSP_SC_B = 12385 , LIEF::assembly::riscv::CV_SDOTUSP_SC_H = 12386 , LIEF::assembly::riscv::CV_SHUFFLE2_B = 12387 ,
  LIEF::assembly::riscv::CV_SHUFFLE2_H = 12388 , LIEF::assembly::riscv::CV_SHUFFLEI0_SCI_B = 12389 , LIEF::assembly::riscv::CV_SHUFFLEI1_SCI_B = 12390 , LIEF::assembly::riscv::CV_SHUFFLEI2_SCI_B = 12391 ,
  LIEF::assembly::riscv::CV_SHUFFLEI3_SCI_B = 12392 , LIEF::assembly::riscv::CV_SHUFFLE_B = 12393 , LIEF::assembly::riscv::CV_SHUFFLE_H = 12394 , LIEF::assembly::riscv::CV_SHUFFLE_SCI_H = 12395 ,
  LIEF::assembly::riscv::CV_SH_ri_inc = 12396 , LIEF::assembly::riscv::CV_SH_rr = 12397 , LIEF::assembly::riscv::CV_SH_rr_inc = 12398 , LIEF::assembly::riscv::CV_SLET = 12399 ,
  LIEF::assembly::riscv::CV_SLETU = 12400 , LIEF::assembly::riscv::CV_SLL_B = 12401 , LIEF::assembly::riscv::CV_SLL_H = 12402 , LIEF::assembly::riscv::CV_SLL_SCI_B = 12403 ,
  LIEF::assembly::riscv::CV_SLL_SCI_H = 12404 , LIEF::assembly::riscv::CV_SLL_SC_B = 12405 , LIEF::assembly::riscv::CV_SLL_SC_H = 12406 , LIEF::assembly::riscv::CV_SRA_B = 12407 ,
  LIEF::assembly::riscv::CV_SRA_H = 12408 , LIEF::assembly::riscv::CV_SRA_SCI_B = 12409 , LIEF::assembly::riscv::CV_SRA_SCI_H = 12410 , LIEF::assembly::riscv::CV_SRA_SC_B = 12411 ,
  LIEF::assembly::riscv::CV_SRA_SC_H = 12412 , LIEF::assembly::riscv::CV_SRL_B = 12413 , LIEF::assembly::riscv::CV_SRL_H = 12414 , LIEF::assembly::riscv::CV_SRL_SCI_B = 12415 ,
  LIEF::assembly::riscv::CV_SRL_SCI_H = 12416 , LIEF::assembly::riscv::CV_SRL_SC_B = 12417 , LIEF::assembly::riscv::CV_SRL_SC_H = 12418 , LIEF::assembly::riscv::CV_SUBN = 12419 ,
  LIEF::assembly::riscv::CV_SUBNR = 12420 , LIEF::assembly::riscv::CV_SUBRN = 12421 , LIEF::assembly::riscv::CV_SUBRNR = 12422 , LIEF::assembly::riscv::CV_SUBROTMJ = 12423 ,
  LIEF::assembly::riscv::CV_SUBROTMJ_DIV2 = 12424 , LIEF::assembly::riscv::CV_SUBROTMJ_DIV4 = 12425 , LIEF::assembly::riscv::CV_SUBROTMJ_DIV8 = 12426 , LIEF::assembly::riscv::CV_SUBUN = 12427 ,
  LIEF::assembly::riscv::CV_SUBUNR = 12428 , LIEF::assembly::riscv::CV_SUBURN = 12429 , LIEF::assembly::riscv::CV_SUBURNR = 12430 , LIEF::assembly::riscv::CV_SUB_B = 12431 ,
  LIEF::assembly::riscv::CV_SUB_DIV2 = 12432 , LIEF::assembly::riscv::CV_SUB_DIV4 = 12433 , LIEF::assembly::riscv::CV_SUB_DIV8 = 12434 , LIEF::assembly::riscv::CV_SUB_H = 12435 ,
  LIEF::assembly::riscv::CV_SUB_SCI_B = 12436 , LIEF::assembly::riscv::CV_SUB_SCI_H = 12437 , LIEF::assembly::riscv::CV_SUB_SC_B = 12438 , LIEF::assembly::riscv::CV_SUB_SC_H = 12439 ,
  LIEF::assembly::riscv::CV_SW_ri_inc = 12440 , LIEF::assembly::riscv::CV_SW_rr = 12441 , LIEF::assembly::riscv::CV_SW_rr_inc = 12442 , LIEF::assembly::riscv::CV_XOR_B = 12443 ,
  LIEF::assembly::riscv::CV_XOR_H = 12444 , LIEF::assembly::riscv::CV_XOR_SCI_B = 12445 , LIEF::assembly::riscv::CV_XOR_SCI_H = 12446 , LIEF::assembly::riscv::CV_XOR_SC_B = 12447 ,
  LIEF::assembly::riscv::CV_XOR_SC_H = 12448 , LIEF::assembly::riscv::CZERO_EQZ = 12449 , LIEF::assembly::riscv::CZERO_NEZ = 12450 , LIEF::assembly::riscv::C_ADD = 12451 ,
  LIEF::assembly::riscv::C_ADDI = 12452 , LIEF::assembly::riscv::C_ADDI16SP = 12453 , LIEF::assembly::riscv::C_ADDI4SPN = 12454 , LIEF::assembly::riscv::C_ADDIW = 12455 ,
  LIEF::assembly::riscv::C_ADDI_HINT_IMM_ZERO = 12456 , LIEF::assembly::riscv::C_ADDI_NOP = 12457 , LIEF::assembly::riscv::C_ADDW = 12458 , LIEF::assembly::riscv::C_ADD_HINT = 12459 ,
  LIEF::assembly::riscv::C_AND = 12460 , LIEF::assembly::riscv::C_ANDI = 12461 , LIEF::assembly::riscv::C_BEQZ = 12462 , LIEF::assembly::riscv::C_BNEZ = 12463 ,
  LIEF::assembly::riscv::C_EBREAK = 12464 , LIEF::assembly::riscv::C_FLD = 12465 , LIEF::assembly::riscv::C_FLDSP = 12466 , LIEF::assembly::riscv::C_FLW = 12467 ,
  LIEF::assembly::riscv::C_FLWSP = 12468 , LIEF::assembly::riscv::C_FSD = 12469 , LIEF::assembly::riscv::C_FSDSP = 12470 , LIEF::assembly::riscv::C_FSW = 12471 ,
  LIEF::assembly::riscv::C_FSWSP = 12472 , LIEF::assembly::riscv::C_J = 12473 , LIEF::assembly::riscv::C_JAL = 12474 , LIEF::assembly::riscv::C_JALR = 12475 ,
  LIEF::assembly::riscv::C_JR = 12476 , LIEF::assembly::riscv::C_LBU = 12477 , LIEF::assembly::riscv::C_LD = 12478 , LIEF::assembly::riscv::C_LDSP = 12479 ,
  LIEF::assembly::riscv::C_LH = 12480 , LIEF::assembly::riscv::C_LHU = 12481 , LIEF::assembly::riscv::C_LI = 12482 , LIEF::assembly::riscv::C_LI_HINT = 12483 ,
  LIEF::assembly::riscv::C_LUI = 12484 , LIEF::assembly::riscv::C_LUI_HINT = 12485 , LIEF::assembly::riscv::C_LW = 12486 , LIEF::assembly::riscv::C_LWSP = 12487 ,
  LIEF::assembly::riscv::C_MOP1 = 12488 , LIEF::assembly::riscv::C_MOP11 = 12489 , LIEF::assembly::riscv::C_MOP13 = 12490 , LIEF::assembly::riscv::C_MOP15 = 12491 ,
  LIEF::assembly::riscv::C_MOP3 = 12492 , LIEF::assembly::riscv::C_MOP5 = 12493 , LIEF::assembly::riscv::C_MOP7 = 12494 , LIEF::assembly::riscv::C_MOP9 = 12495 ,
  LIEF::assembly::riscv::C_MUL = 12496 , LIEF::assembly::riscv::C_MV = 12497 , LIEF::assembly::riscv::C_MV_HINT = 12498 , LIEF::assembly::riscv::C_NOP = 12499 ,
  LIEF::assembly::riscv::C_NOP_HINT = 12500 , LIEF::assembly::riscv::C_NOT = 12501 , LIEF::assembly::riscv::C_OR = 12502 , LIEF::assembly::riscv::C_SB = 12503 ,
  LIEF::assembly::riscv::C_SD = 12504 , LIEF::assembly::riscv::C_SDSP = 12505 , LIEF::assembly::riscv::C_SEXT_B = 12506 , LIEF::assembly::riscv::C_SEXT_H = 12507 ,
  LIEF::assembly::riscv::C_SH = 12508 , LIEF::assembly::riscv::C_SLLI = 12509 , LIEF::assembly::riscv::C_SLLI64_HINT = 12510 , LIEF::assembly::riscv::C_SLLI_HINT = 12511 ,
  LIEF::assembly::riscv::C_SRAI = 12512 , LIEF::assembly::riscv::C_SRAI64_HINT = 12513 , LIEF::assembly::riscv::C_SRLI = 12514 , LIEF::assembly::riscv::C_SRLI64_HINT = 12515 ,
  LIEF::assembly::riscv::C_SSPOPCHK = 12516 , LIEF::assembly::riscv::C_SSPUSH = 12517 , LIEF::assembly::riscv::C_SUB = 12518 , LIEF::assembly::riscv::C_SUBW = 12519 ,
  LIEF::assembly::riscv::C_SW = 12520 , LIEF::assembly::riscv::C_SWSP = 12521 , LIEF::assembly::riscv::C_UNIMP = 12522 , LIEF::assembly::riscv::C_XOR = 12523 ,
  LIEF::assembly::riscv::C_ZEXT_B = 12524 , LIEF::assembly::riscv::C_ZEXT_H = 12525 , LIEF::assembly::riscv::C_ZEXT_W = 12526 , LIEF::assembly::riscv::DIV = 12527 ,
  LIEF::assembly::riscv::DIVU = 12528 , LIEF::assembly::riscv::DIVUW = 12529 , LIEF::assembly::riscv::DIVW = 12530 , LIEF::assembly::riscv::DRET = 12531 ,
  LIEF::assembly::riscv::EBREAK = 12532 , LIEF::assembly::riscv::ECALL = 12533 , LIEF::assembly::riscv::FADD_D = 12534 , LIEF::assembly::riscv::FADD_D_IN32X = 12535 ,
  LIEF::assembly::riscv::FADD_D_INX = 12536 , LIEF::assembly::riscv::FADD_H = 12537 , LIEF::assembly::riscv::FADD_H_INX = 12538 , LIEF::assembly::riscv::FADD_S = 12539 ,
  LIEF::assembly::riscv::FADD_S_INX = 12540 , LIEF::assembly::riscv::FCLASS_D = 12541 , LIEF::assembly::riscv::FCLASS_D_IN32X = 12542 , LIEF::assembly::riscv::FCLASS_D_INX = 12543 ,
  LIEF::assembly::riscv::FCLASS_H = 12544 , LIEF::assembly::riscv::FCLASS_H_INX = 12545 , LIEF::assembly::riscv::FCLASS_S = 12546 , LIEF::assembly::riscv::FCLASS_S_INX = 12547 ,
  LIEF::assembly::riscv::FCVTMOD_W_D = 12548 , LIEF::assembly::riscv::FCVT_BF16_S = 12549 , LIEF::assembly::riscv::FCVT_D_H = 12550 , LIEF::assembly::riscv::FCVT_D_H_IN32X = 12551 ,
  LIEF::assembly::riscv::FCVT_D_H_INX = 12552 , LIEF::assembly::riscv::FCVT_D_L = 12553 , LIEF::assembly::riscv::FCVT_D_LU = 12554 , LIEF::assembly::riscv::FCVT_D_LU_INX = 12555 ,
  LIEF::assembly::riscv::FCVT_D_L_INX = 12556 , LIEF::assembly::riscv::FCVT_D_S = 12557 , LIEF::assembly::riscv::FCVT_D_S_IN32X = 12558 , LIEF::assembly::riscv::FCVT_D_S_INX = 12559 ,
  LIEF::assembly::riscv::FCVT_D_W = 12560 , LIEF::assembly::riscv::FCVT_D_WU = 12561 , LIEF::assembly::riscv::FCVT_D_WU_IN32X = 12562 , LIEF::assembly::riscv::FCVT_D_WU_INX = 12563 ,
  LIEF::assembly::riscv::FCVT_D_W_IN32X = 12564 , LIEF::assembly::riscv::FCVT_D_W_INX = 12565 , LIEF::assembly::riscv::FCVT_H_D = 12566 , LIEF::assembly::riscv::FCVT_H_D_IN32X = 12567 ,
  LIEF::assembly::riscv::FCVT_H_D_INX = 12568 , LIEF::assembly::riscv::FCVT_H_L = 12569 , LIEF::assembly::riscv::FCVT_H_LU = 12570 , LIEF::assembly::riscv::FCVT_H_LU_INX = 12571 ,
  LIEF::assembly::riscv::FCVT_H_L_INX = 12572 , LIEF::assembly::riscv::FCVT_H_S = 12573 , LIEF::assembly::riscv::FCVT_H_S_INX = 12574 , LIEF::assembly::riscv::FCVT_H_W = 12575 ,
  LIEF::assembly::riscv::FCVT_H_WU = 12576 , LIEF::assembly::riscv::FCVT_H_WU_INX = 12577 , LIEF::assembly::riscv::FCVT_H_W_INX = 12578 , LIEF::assembly::riscv::FCVT_LU_D = 12579 ,
  LIEF::assembly::riscv::FCVT_LU_D_INX = 12580 , LIEF::assembly::riscv::FCVT_LU_H = 12581 , LIEF::assembly::riscv::FCVT_LU_H_INX = 12582 , LIEF::assembly::riscv::FCVT_LU_S = 12583 ,
  LIEF::assembly::riscv::FCVT_LU_S_INX = 12584 , LIEF::assembly::riscv::FCVT_L_D = 12585 , LIEF::assembly::riscv::FCVT_L_D_INX = 12586 , LIEF::assembly::riscv::FCVT_L_H = 12587 ,
  LIEF::assembly::riscv::FCVT_L_H_INX = 12588 , LIEF::assembly::riscv::FCVT_L_S = 12589 , LIEF::assembly::riscv::FCVT_L_S_INX = 12590 , LIEF::assembly::riscv::FCVT_S_BF16 = 12591 ,
  LIEF::assembly::riscv::FCVT_S_D = 12592 , LIEF::assembly::riscv::FCVT_S_D_IN32X = 12593 , LIEF::assembly::riscv::FCVT_S_D_INX = 12594 , LIEF::assembly::riscv::FCVT_S_H = 12595 ,
  LIEF::assembly::riscv::FCVT_S_H_INX = 12596 , LIEF::assembly::riscv::FCVT_S_L = 12597 , LIEF::assembly::riscv::FCVT_S_LU = 12598 , LIEF::assembly::riscv::FCVT_S_LU_INX = 12599 ,
  LIEF::assembly::riscv::FCVT_S_L_INX = 12600 , LIEF::assembly::riscv::FCVT_S_W = 12601 , LIEF::assembly::riscv::FCVT_S_WU = 12602 , LIEF::assembly::riscv::FCVT_S_WU_INX = 12603 ,
  LIEF::assembly::riscv::FCVT_S_W_INX = 12604 , LIEF::assembly::riscv::FCVT_WU_D = 12605 , LIEF::assembly::riscv::FCVT_WU_D_IN32X = 12606 , LIEF::assembly::riscv::FCVT_WU_D_INX = 12607 ,
  LIEF::assembly::riscv::FCVT_WU_H = 12608 , LIEF::assembly::riscv::FCVT_WU_H_INX = 12609 , LIEF::assembly::riscv::FCVT_WU_S = 12610 , LIEF::assembly::riscv::FCVT_WU_S_INX = 12611 ,
  LIEF::assembly::riscv::FCVT_W_D = 12612 , LIEF::assembly::riscv::FCVT_W_D_IN32X = 12613 , LIEF::assembly::riscv::FCVT_W_D_INX = 12614 , LIEF::assembly::riscv::FCVT_W_H = 12615 ,
  LIEF::assembly::riscv::FCVT_W_H_INX = 12616 , LIEF::assembly::riscv::FCVT_W_S = 12617 , LIEF::assembly::riscv::FCVT_W_S_INX = 12618 , LIEF::assembly::riscv::FDIV_D = 12619 ,
  LIEF::assembly::riscv::FDIV_D_IN32X = 12620 , LIEF::assembly::riscv::FDIV_D_INX = 12621 , LIEF::assembly::riscv::FDIV_H = 12622 , LIEF::assembly::riscv::FDIV_H_INX = 12623 ,
  LIEF::assembly::riscv::FDIV_S = 12624 , LIEF::assembly::riscv::FDIV_S_INX = 12625 , LIEF::assembly::riscv::FENCE = 12626 , LIEF::assembly::riscv::FENCE_I = 12627 ,
  LIEF::assembly::riscv::FENCE_TSO = 12628 , LIEF::assembly::riscv::FEQ_D = 12629 , LIEF::assembly::riscv::FEQ_D_IN32X = 12630 , LIEF::assembly::riscv::FEQ_D_INX = 12631 ,
  LIEF::assembly::riscv::FEQ_H = 12632 , LIEF::assembly::riscv::FEQ_H_INX = 12633 , LIEF::assembly::riscv::FEQ_S = 12634 , LIEF::assembly::riscv::FEQ_S_INX = 12635 ,
  LIEF::assembly::riscv::FLD = 12636 , LIEF::assembly::riscv::FLEQ_D = 12637 , LIEF::assembly::riscv::FLEQ_H = 12638 , LIEF::assembly::riscv::FLEQ_S = 12639 ,
  LIEF::assembly::riscv::FLE_D = 12640 , LIEF::assembly::riscv::FLE_D_IN32X = 12641 , LIEF::assembly::riscv::FLE_D_INX = 12642 , LIEF::assembly::riscv::FLE_H = 12643 ,
  LIEF::assembly::riscv::FLE_H_INX = 12644 , LIEF::assembly::riscv::FLE_S = 12645 , LIEF::assembly::riscv::FLE_S_INX = 12646 , LIEF::assembly::riscv::FLH = 12647 ,
  LIEF::assembly::riscv::FLI_D = 12648 , LIEF::assembly::riscv::FLI_H = 12649 , LIEF::assembly::riscv::FLI_S = 12650 , LIEF::assembly::riscv::FLTQ_D = 12651 ,
  LIEF::assembly::riscv::FLTQ_H = 12652 , LIEF::assembly::riscv::FLTQ_S = 12653 , LIEF::assembly::riscv::FLT_D = 12654 , LIEF::assembly::riscv::FLT_D_IN32X = 12655 ,
  LIEF::assembly::riscv::FLT_D_INX = 12656 , LIEF::assembly::riscv::FLT_H = 12657 , LIEF::assembly::riscv::FLT_H_INX = 12658 , LIEF::assembly::riscv::FLT_S = 12659 ,
  LIEF::assembly::riscv::FLT_S_INX = 12660 , LIEF::assembly::riscv::FLW = 12661 , LIEF::assembly::riscv::FMADD_D = 12662 , LIEF::assembly::riscv::FMADD_D_IN32X = 12663 ,
  LIEF::assembly::riscv::FMADD_D_INX = 12664 , LIEF::assembly::riscv::FMADD_H = 12665 , LIEF::assembly::riscv::FMADD_H_INX = 12666 , LIEF::assembly::riscv::FMADD_S = 12667 ,
  LIEF::assembly::riscv::FMADD_S_INX = 12668 , LIEF::assembly::riscv::FMAXM_D = 12669 , LIEF::assembly::riscv::FMAXM_H = 12670 , LIEF::assembly::riscv::FMAXM_S = 12671 ,
  LIEF::assembly::riscv::FMAX_D = 12672 , LIEF::assembly::riscv::FMAX_D_IN32X = 12673 , LIEF::assembly::riscv::FMAX_D_INX = 12674 , LIEF::assembly::riscv::FMAX_H = 12675 ,
  LIEF::assembly::riscv::FMAX_H_INX = 12676 , LIEF::assembly::riscv::FMAX_S = 12677 , LIEF::assembly::riscv::FMAX_S_INX = 12678 , LIEF::assembly::riscv::FMINM_D = 12679 ,
  LIEF::assembly::riscv::FMINM_H = 12680 , LIEF::assembly::riscv::FMINM_S = 12681 , LIEF::assembly::riscv::FMIN_D = 12682 , LIEF::assembly::riscv::FMIN_D_IN32X = 12683 ,
  LIEF::assembly::riscv::FMIN_D_INX = 12684 , LIEF::assembly::riscv::FMIN_H = 12685 , LIEF::assembly::riscv::FMIN_H_INX = 12686 , LIEF::assembly::riscv::FMIN_S = 12687 ,
  LIEF::assembly::riscv::FMIN_S_INX = 12688 , LIEF::assembly::riscv::FMSUB_D = 12689 , LIEF::assembly::riscv::FMSUB_D_IN32X = 12690 , LIEF::assembly::riscv::FMSUB_D_INX = 12691 ,
  LIEF::assembly::riscv::FMSUB_H = 12692 , LIEF::assembly::riscv::FMSUB_H_INX = 12693 , LIEF::assembly::riscv::FMSUB_S = 12694 , LIEF::assembly::riscv::FMSUB_S_INX = 12695 ,
  LIEF::assembly::riscv::FMUL_D = 12696 , LIEF::assembly::riscv::FMUL_D_IN32X = 12697 , LIEF::assembly::riscv::FMUL_D_INX = 12698 , LIEF::assembly::riscv::FMUL_H = 12699 ,
  LIEF::assembly::riscv::FMUL_H_INX = 12700 , LIEF::assembly::riscv::FMUL_S = 12701 , LIEF::assembly::riscv::FMUL_S_INX = 12702 , LIEF::assembly::riscv::FMVH_X_D = 12703 ,
  LIEF::assembly::riscv::FMVP_D_X = 12704 , LIEF::assembly::riscv::FMV_D_X = 12705 , LIEF::assembly::riscv::FMV_H_X = 12706 , LIEF::assembly::riscv::FMV_W_X = 12707 ,
  LIEF::assembly::riscv::FMV_X_D = 12708 , LIEF::assembly::riscv::FMV_X_H = 12709 , LIEF::assembly::riscv::FMV_X_W = 12710 , LIEF::assembly::riscv::FMV_X_W_FPR64 = 12711 ,
  LIEF::assembly::riscv::FNMADD_D = 12712 , LIEF::assembly::riscv::FNMADD_D_IN32X = 12713 , LIEF::assembly::riscv::FNMADD_D_INX = 12714 , LIEF::assembly::riscv::FNMADD_H = 12715 ,
  LIEF::assembly::riscv::FNMADD_H_INX = 12716 , LIEF::assembly::riscv::FNMADD_S = 12717 , LIEF::assembly::riscv::FNMADD_S_INX = 12718 , LIEF::assembly::riscv::FNMSUB_D = 12719 ,
  LIEF::assembly::riscv::FNMSUB_D_IN32X = 12720 , LIEF::assembly::riscv::FNMSUB_D_INX = 12721 , LIEF::assembly::riscv::FNMSUB_H = 12722 , LIEF::assembly::riscv::FNMSUB_H_INX = 12723 ,
  LIEF::assembly::riscv::FNMSUB_S = 12724 , LIEF::assembly::riscv::FNMSUB_S_INX = 12725 , LIEF::assembly::riscv::FROUNDNX_D = 12726 , LIEF::assembly::riscv::FROUNDNX_H = 12727 ,
  LIEF::assembly::riscv::FROUNDNX_S = 12728 , LIEF::assembly::riscv::FROUND_D = 12729 , LIEF::assembly::riscv::FROUND_H = 12730 , LIEF::assembly::riscv::FROUND_S = 12731 ,
  LIEF::assembly::riscv::FSD = 12732 , LIEF::assembly::riscv::FSGNJN_D = 12733 , LIEF::assembly::riscv::FSGNJN_D_IN32X = 12734 , LIEF::assembly::riscv::FSGNJN_D_INX = 12735 ,
  LIEF::assembly::riscv::FSGNJN_H = 12736 , LIEF::assembly::riscv::FSGNJN_H_INX = 12737 , LIEF::assembly::riscv::FSGNJN_S = 12738 , LIEF::assembly::riscv::FSGNJN_S_INX = 12739 ,
  LIEF::assembly::riscv::FSGNJX_D = 12740 , LIEF::assembly::riscv::FSGNJX_D_IN32X = 12741 , LIEF::assembly::riscv::FSGNJX_D_INX = 12742 , LIEF::assembly::riscv::FSGNJX_H = 12743 ,
  LIEF::assembly::riscv::FSGNJX_H_INX = 12744 , LIEF::assembly::riscv::FSGNJX_S = 12745 , LIEF::assembly::riscv::FSGNJX_S_INX = 12746 , LIEF::assembly::riscv::FSGNJ_D = 12747 ,
  LIEF::assembly::riscv::FSGNJ_D_IN32X = 12748 , LIEF::assembly::riscv::FSGNJ_D_INX = 12749 , LIEF::assembly::riscv::FSGNJ_H = 12750 , LIEF::assembly::riscv::FSGNJ_H_INX = 12751 ,
  LIEF::assembly::riscv::FSGNJ_S = 12752 , LIEF::assembly::riscv::FSGNJ_S_INX = 12753 , LIEF::assembly::riscv::FSH = 12754 , LIEF::assembly::riscv::FSQRT_D = 12755 ,
  LIEF::assembly::riscv::FSQRT_D_IN32X = 12756 , LIEF::assembly::riscv::FSQRT_D_INX = 12757 , LIEF::assembly::riscv::FSQRT_H = 12758 , LIEF::assembly::riscv::FSQRT_H_INX = 12759 ,
  LIEF::assembly::riscv::FSQRT_S = 12760 , LIEF::assembly::riscv::FSQRT_S_INX = 12761 , LIEF::assembly::riscv::FSUB_D = 12762 , LIEF::assembly::riscv::FSUB_D_IN32X = 12763 ,
  LIEF::assembly::riscv::FSUB_D_INX = 12764 , LIEF::assembly::riscv::FSUB_H = 12765 , LIEF::assembly::riscv::FSUB_H_INX = 12766 , LIEF::assembly::riscv::FSUB_S = 12767 ,
  LIEF::assembly::riscv::FSUB_S_INX = 12768 , LIEF::assembly::riscv::FSW = 12769 , LIEF::assembly::riscv::HFENCE_GVMA = 12770 , LIEF::assembly::riscv::HFENCE_VVMA = 12771 ,
  LIEF::assembly::riscv::HINVAL_GVMA = 12772 , LIEF::assembly::riscv::HINVAL_VVMA = 12773 , LIEF::assembly::riscv::HLVX_HU = 12774 , LIEF::assembly::riscv::HLVX_WU = 12775 ,
  LIEF::assembly::riscv::HLV_B = 12776 , LIEF::assembly::riscv::HLV_BU = 12777 , LIEF::assembly::riscv::HLV_D = 12778 , LIEF::assembly::riscv::HLV_H = 12779 ,
  LIEF::assembly::riscv::HLV_HU = 12780 , LIEF::assembly::riscv::HLV_W = 12781 , LIEF::assembly::riscv::HLV_WU = 12782 , LIEF::assembly::riscv::HSV_B = 12783 ,
  LIEF::assembly::riscv::HSV_D = 12784 , LIEF::assembly::riscv::HSV_H = 12785 , LIEF::assembly::riscv::HSV_W = 12786 , LIEF::assembly::riscv::Insn16 = 12787 ,
  LIEF::assembly::riscv::Insn32 = 12788 , LIEF::assembly::riscv::InsnB = 12789 , LIEF::assembly::riscv::InsnCA = 12790 , LIEF::assembly::riscv::InsnCB = 12791 ,
  LIEF::assembly::riscv::InsnCI = 12792 , LIEF::assembly::riscv::InsnCIW = 12793 , LIEF::assembly::riscv::InsnCJ = 12794 , LIEF::assembly::riscv::InsnCL = 12795 ,
  LIEF::assembly::riscv::InsnCR = 12796 , LIEF::assembly::riscv::InsnCS = 12797 , LIEF::assembly::riscv::InsnCSS = 12798 , LIEF::assembly::riscv::InsnI = 12799 ,
  LIEF::assembly::riscv::InsnI_Mem = 12800 , LIEF::assembly::riscv::InsnJ = 12801 , LIEF::assembly::riscv::InsnR = 12802 , LIEF::assembly::riscv::InsnR4 = 12803 ,
  LIEF::assembly::riscv::InsnS = 12804 , LIEF::assembly::riscv::InsnU = 12805 , LIEF::assembly::riscv::JAL = 12806 , LIEF::assembly::riscv::JALR = 12807 ,
  LIEF::assembly::riscv::LB = 12808 , LIEF::assembly::riscv::LBU = 12809 , LIEF::assembly::riscv::LB_AQ = 12810 , LIEF::assembly::riscv::LB_AQ_RL = 12811 ,
  LIEF::assembly::riscv::LD = 12812 , LIEF::assembly::riscv::LD_AQ = 12813 , LIEF::assembly::riscv::LD_AQ_RL = 12814 , LIEF::assembly::riscv::LH = 12815 ,
  LIEF::assembly::riscv::LHU = 12816 , LIEF::assembly::riscv::LH_AQ = 12817 , LIEF::assembly::riscv::LH_AQ_RL = 12818 , LIEF::assembly::riscv::LR_D = 12819 ,
  LIEF::assembly::riscv::LR_D_AQ = 12820 , LIEF::assembly::riscv::LR_D_AQ_RL = 12821 , LIEF::assembly::riscv::LR_D_RL = 12822 , LIEF::assembly::riscv::LR_W = 12823 ,
  LIEF::assembly::riscv::LR_W_AQ = 12824 , LIEF::assembly::riscv::LR_W_AQ_RL = 12825 , LIEF::assembly::riscv::LR_W_RL = 12826 , LIEF::assembly::riscv::LUI = 12827 ,
  LIEF::assembly::riscv::LW = 12828 , LIEF::assembly::riscv::LWU = 12829 , LIEF::assembly::riscv::LW_AQ = 12830 , LIEF::assembly::riscv::LW_AQ_RL = 12831 ,
  LIEF::assembly::riscv::MAX = 12832 , LIEF::assembly::riscv::MAXU = 12833 , LIEF::assembly::riscv::MIN = 12834 , LIEF::assembly::riscv::MINU = 12835 ,
  LIEF::assembly::riscv::MOPR0 = 12836 , LIEF::assembly::riscv::MOPR1 = 12837 , LIEF::assembly::riscv::MOPR10 = 12838 , LIEF::assembly::riscv::MOPR11 = 12839 ,
  LIEF::assembly::riscv::MOPR12 = 12840 , LIEF::assembly::riscv::MOPR13 = 12841 , LIEF::assembly::riscv::MOPR14 = 12842 , LIEF::assembly::riscv::MOPR15 = 12843 ,
  LIEF::assembly::riscv::MOPR16 = 12844 , LIEF::assembly::riscv::MOPR17 = 12845 , LIEF::assembly::riscv::MOPR18 = 12846 , LIEF::assembly::riscv::MOPR19 = 12847 ,
  LIEF::assembly::riscv::MOPR2 = 12848 , LIEF::assembly::riscv::MOPR20 = 12849 , LIEF::assembly::riscv::MOPR21 = 12850 , LIEF::assembly::riscv::MOPR22 = 12851 ,
  LIEF::assembly::riscv::MOPR23 = 12852 , LIEF::assembly::riscv::MOPR24 = 12853 , LIEF::assembly::riscv::MOPR25 = 12854 , LIEF::assembly::riscv::MOPR26 = 12855 ,
  LIEF::assembly::riscv::MOPR27 = 12856 , LIEF::assembly::riscv::MOPR28 = 12857 , LIEF::assembly::riscv::MOPR29 = 12858 , LIEF::assembly::riscv::MOPR3 = 12859 ,
  LIEF::assembly::riscv::MOPR30 = 12860 , LIEF::assembly::riscv::MOPR31 = 12861 , LIEF::assembly::riscv::MOPR4 = 12862 , LIEF::assembly::riscv::MOPR5 = 12863 ,
  LIEF::assembly::riscv::MOPR6 = 12864 , LIEF::assembly::riscv::MOPR7 = 12865 , LIEF::assembly::riscv::MOPR8 = 12866 , LIEF::assembly::riscv::MOPR9 = 12867 ,
  LIEF::assembly::riscv::MOPRR0 = 12868 , LIEF::assembly::riscv::MOPRR1 = 12869 , LIEF::assembly::riscv::MOPRR2 = 12870 , LIEF::assembly::riscv::MOPRR3 = 12871 ,
  LIEF::assembly::riscv::MOPRR4 = 12872 , LIEF::assembly::riscv::MOPRR5 = 12873 , LIEF::assembly::riscv::MOPRR6 = 12874 , LIEF::assembly::riscv::MOPRR7 = 12875 ,
  LIEF::assembly::riscv::MRET = 12876 , LIEF::assembly::riscv::MUL = 12877 , LIEF::assembly::riscv::MULH = 12878 , LIEF::assembly::riscv::MULHSU = 12879 ,
  LIEF::assembly::riscv::MULHU = 12880 , LIEF::assembly::riscv::MULW = 12881 , LIEF::assembly::riscv::OR = 12882 , LIEF::assembly::riscv::ORC_B = 12883 ,
  LIEF::assembly::riscv::ORI = 12884 , LIEF::assembly::riscv::ORN = 12885 , LIEF::assembly::riscv::PACK = 12886 , LIEF::assembly::riscv::PACKH = 12887 ,
  LIEF::assembly::riscv::PACKW = 12888 , LIEF::assembly::riscv::PREFETCH_I = 12889 , LIEF::assembly::riscv::PREFETCH_R = 12890 , LIEF::assembly::riscv::PREFETCH_W = 12891 ,
  LIEF::assembly::riscv::QK_C_LBU = 12892 , LIEF::assembly::riscv::QK_C_LBUSP = 12893 , LIEF::assembly::riscv::QK_C_LHU = 12894 , LIEF::assembly::riscv::QK_C_LHUSP = 12895 ,
  LIEF::assembly::riscv::QK_C_SB = 12896 , LIEF::assembly::riscv::QK_C_SBSP = 12897 , LIEF::assembly::riscv::QK_C_SH = 12898 , LIEF::assembly::riscv::QK_C_SHSP = 12899 ,
  LIEF::assembly::riscv::REM = 12900 , LIEF::assembly::riscv::REMU = 12901 , LIEF::assembly::riscv::REMUW = 12902 , LIEF::assembly::riscv::REMW = 12903 ,
  LIEF::assembly::riscv::REV8_RV32 = 12904 , LIEF::assembly::riscv::REV8_RV64 = 12905 , LIEF::assembly::riscv::ROL = 12906 , LIEF::assembly::riscv::ROLW = 12907 ,
  LIEF::assembly::riscv::ROR = 12908 , LIEF::assembly::riscv::RORI = 12909 , LIEF::assembly::riscv::RORIW = 12910 , LIEF::assembly::riscv::RORW = 12911 ,
  LIEF::assembly::riscv::SB = 12912 , LIEF::assembly::riscv::SB_AQ_RL = 12913 , LIEF::assembly::riscv::SB_RL = 12914 , LIEF::assembly::riscv::SC_D = 12915 ,
  LIEF::assembly::riscv::SC_D_AQ = 12916 , LIEF::assembly::riscv::SC_D_AQ_RL = 12917 , LIEF::assembly::riscv::SC_D_RL = 12918 , LIEF::assembly::riscv::SC_W = 12919 ,
  LIEF::assembly::riscv::SC_W_AQ = 12920 , LIEF::assembly::riscv::SC_W_AQ_RL = 12921 , LIEF::assembly::riscv::SC_W_RL = 12922 , LIEF::assembly::riscv::SD = 12923 ,
  LIEF::assembly::riscv::SD_AQ_RL = 12924 , LIEF::assembly::riscv::SD_RL = 12925 , LIEF::assembly::riscv::SEXT_B = 12926 , LIEF::assembly::riscv::SEXT_H = 12927 ,
  LIEF::assembly::riscv::SFENCE_INVAL_IR = 12928 , LIEF::assembly::riscv::SFENCE_VMA = 12929 , LIEF::assembly::riscv::SFENCE_W_INVAL = 12930 , LIEF::assembly::riscv::SF_CDISCARD_D_L1 = 12931 ,
  LIEF::assembly::riscv::SF_CEASE = 12932 , LIEF::assembly::riscv::SF_CFLUSH_D_L1 = 12933 , LIEF::assembly::riscv::SH = 12934 , LIEF::assembly::riscv::SH1ADD = 12935 ,
  LIEF::assembly::riscv::SH1ADD_UW = 12936 , LIEF::assembly::riscv::SH2ADD = 12937 , LIEF::assembly::riscv::SH2ADD_UW = 12938 , LIEF::assembly::riscv::SH3ADD = 12939 ,
  LIEF::assembly::riscv::SH3ADD_UW = 12940 , LIEF::assembly::riscv::SHA256SIG0 = 12941 , LIEF::assembly::riscv::SHA256SIG1 = 12942 , LIEF::assembly::riscv::SHA256SUM0 = 12943 ,
  LIEF::assembly::riscv::SHA256SUM1 = 12944 , LIEF::assembly::riscv::SHA512SIG0 = 12945 , LIEF::assembly::riscv::SHA512SIG0H = 12946 , LIEF::assembly::riscv::SHA512SIG0L = 12947 ,
  LIEF::assembly::riscv::SHA512SIG1 = 12948 , LIEF::assembly::riscv::SHA512SIG1H = 12949 , LIEF::assembly::riscv::SHA512SIG1L = 12950 , LIEF::assembly::riscv::SHA512SUM0 = 12951 ,
  LIEF::assembly::riscv::SHA512SUM0R = 12952 , LIEF::assembly::riscv::SHA512SUM1 = 12953 , LIEF::assembly::riscv::SHA512SUM1R = 12954 , LIEF::assembly::riscv::SH_AQ_RL = 12955 ,
  LIEF::assembly::riscv::SH_RL = 12956 , LIEF::assembly::riscv::SINVAL_VMA = 12957 , LIEF::assembly::riscv::SLL = 12958 , LIEF::assembly::riscv::SLLI = 12959 ,
  LIEF::assembly::riscv::SLLIW = 12960 , LIEF::assembly::riscv::SLLI_UW = 12961 , LIEF::assembly::riscv::SLLW = 12962 , LIEF::assembly::riscv::SLT = 12963 ,
  LIEF::assembly::riscv::SLTI = 12964 , LIEF::assembly::riscv::SLTIU = 12965 , LIEF::assembly::riscv::SLTU = 12966 , LIEF::assembly::riscv::SM3P0 = 12967 ,
  LIEF::assembly::riscv::SM3P1 = 12968 , LIEF::assembly::riscv::SM4ED = 12969 , LIEF::assembly::riscv::SM4KS = 12970 , LIEF::assembly::riscv::SRA = 12971 ,
  LIEF::assembly::riscv::SRAI = 12972 , LIEF::assembly::riscv::SRAIW = 12973 , LIEF::assembly::riscv::SRAW = 12974 , LIEF::assembly::riscv::SRET = 12975 ,
  LIEF::assembly::riscv::SRL = 12976 , LIEF::assembly::riscv::SRLI = 12977 , LIEF::assembly::riscv::SRLIW = 12978 , LIEF::assembly::riscv::SRLW = 12979 ,
  LIEF::assembly::riscv::SSAMOSWAP_D = 12980 , LIEF::assembly::riscv::SSAMOSWAP_D_AQ = 12981 , LIEF::assembly::riscv::SSAMOSWAP_D_AQ_RL = 12982 , LIEF::assembly::riscv::SSAMOSWAP_D_RL = 12983 ,
  LIEF::assembly::riscv::SSAMOSWAP_W = 12984 , LIEF::assembly::riscv::SSAMOSWAP_W_AQ = 12985 , LIEF::assembly::riscv::SSAMOSWAP_W_AQ_RL = 12986 , LIEF::assembly::riscv::SSAMOSWAP_W_RL = 12987 ,
  LIEF::assembly::riscv::SSPOPCHK = 12988 , LIEF::assembly::riscv::SSPUSH = 12989 , LIEF::assembly::riscv::SSRDP = 12990 , LIEF::assembly::riscv::SUB = 12991 ,
  LIEF::assembly::riscv::SUBW = 12992 , LIEF::assembly::riscv::SW = 12993 , LIEF::assembly::riscv::SW_AQ_RL = 12994 , LIEF::assembly::riscv::SW_RL = 12995 ,
  LIEF::assembly::riscv::THVdotVMAQASU_VV = 12996 , LIEF::assembly::riscv::THVdotVMAQASU_VX = 12997 , LIEF::assembly::riscv::THVdotVMAQAUS_VX = 12998 , LIEF::assembly::riscv::THVdotVMAQAU_VV = 12999 ,
  LIEF::assembly::riscv::THVdotVMAQAU_VX = 13000 , LIEF::assembly::riscv::THVdotVMAQA_VV = 13001 , LIEF::assembly::riscv::THVdotVMAQA_VX = 13002 , LIEF::assembly::riscv::TH_ADDSL = 13003 ,
  LIEF::assembly::riscv::TH_DCACHE_CALL = 13004 , LIEF::assembly::riscv::TH_DCACHE_CIALL = 13005 , LIEF::assembly::riscv::TH_DCACHE_CIPA = 13006 , LIEF::assembly::riscv::TH_DCACHE_CISW = 13007 ,
  LIEF::assembly::riscv::TH_DCACHE_CIVA = 13008 , LIEF::assembly::riscv::TH_DCACHE_CPA = 13009 , LIEF::assembly::riscv::TH_DCACHE_CPAL1 = 13010 , LIEF::assembly::riscv::TH_DCACHE_CSW = 13011 ,
  LIEF::assembly::riscv::TH_DCACHE_CVA = 13012 , LIEF::assembly::riscv::TH_DCACHE_CVAL1 = 13013 , LIEF::assembly::riscv::TH_DCACHE_IALL = 13014 , LIEF::assembly::riscv::TH_DCACHE_IPA = 13015 ,
  LIEF::assembly::riscv::TH_DCACHE_ISW = 13016 , LIEF::assembly::riscv::TH_DCACHE_IVA = 13017 , LIEF::assembly::riscv::TH_EXT = 13018 , LIEF::assembly::riscv::TH_EXTU = 13019 ,
  LIEF::assembly::riscv::TH_FF0 = 13020 , LIEF::assembly::riscv::TH_FF1 = 13021 , LIEF::assembly::riscv::TH_FLRD = 13022 , LIEF::assembly::riscv::TH_FLRW = 13023 ,
  LIEF::assembly::riscv::TH_FLURD = 13024 , LIEF::assembly::riscv::TH_FLURW = 13025 , LIEF::assembly::riscv::TH_FSRD = 13026 , LIEF::assembly::riscv::TH_FSRW = 13027 ,
  LIEF::assembly::riscv::TH_FSURD = 13028 , LIEF::assembly::riscv::TH_FSURW = 13029 , LIEF::assembly::riscv::TH_ICACHE_IALL = 13030 , LIEF::assembly::riscv::TH_ICACHE_IALLS = 13031 ,
  LIEF::assembly::riscv::TH_ICACHE_IPA = 13032 , LIEF::assembly::riscv::TH_ICACHE_IVA = 13033 , LIEF::assembly::riscv::TH_L2CACHE_CALL = 13034 , LIEF::assembly::riscv::TH_L2CACHE_CIALL = 13035 ,
  LIEF::assembly::riscv::TH_L2CACHE_IALL = 13036 , LIEF::assembly::riscv::TH_LBIA = 13037 , LIEF::assembly::riscv::TH_LBIB = 13038 , LIEF::assembly::riscv::TH_LBUIA = 13039 ,
  LIEF::assembly::riscv::TH_LBUIB = 13040 , LIEF::assembly::riscv::TH_LDD = 13041 , LIEF::assembly::riscv::TH_LDIA = 13042 , LIEF::assembly::riscv::TH_LDIB = 13043 ,
  LIEF::assembly::riscv::TH_LHIA = 13044 , LIEF::assembly::riscv::TH_LHIB = 13045 , LIEF::assembly::riscv::TH_LHUIA = 13046 , LIEF::assembly::riscv::TH_LHUIB = 13047 ,
  LIEF::assembly::riscv::TH_LRB = 13048 , LIEF::assembly::riscv::TH_LRBU = 13049 , LIEF::assembly::riscv::TH_LRD = 13050 , LIEF::assembly::riscv::TH_LRH = 13051 ,
  LIEF::assembly::riscv::TH_LRHU = 13052 , LIEF::assembly::riscv::TH_LRW = 13053 , LIEF::assembly::riscv::TH_LRWU = 13054 , LIEF::assembly::riscv::TH_LURB = 13055 ,
  LIEF::assembly::riscv::TH_LURBU = 13056 , LIEF::assembly::riscv::TH_LURD = 13057 , LIEF::assembly::riscv::TH_LURH = 13058 , LIEF::assembly::riscv::TH_LURHU = 13059 ,
  LIEF::assembly::riscv::TH_LURW = 13060 , LIEF::assembly::riscv::TH_LURWU = 13061 , LIEF::assembly::riscv::TH_LWD = 13062 , LIEF::assembly::riscv::TH_LWIA = 13063 ,
  LIEF::assembly::riscv::TH_LWIB = 13064 , LIEF::assembly::riscv::TH_LWUD = 13065 , LIEF::assembly::riscv::TH_LWUIA = 13066 , LIEF::assembly::riscv::TH_LWUIB = 13067 ,
  LIEF::assembly::riscv::TH_MULA = 13068 , LIEF::assembly::riscv::TH_MULAH = 13069 , LIEF::assembly::riscv::TH_MULAW = 13070 , LIEF::assembly::riscv::TH_MULS = 13071 ,
  LIEF::assembly::riscv::TH_MULSH = 13072 , LIEF::assembly::riscv::TH_MULSW = 13073 , LIEF::assembly::riscv::TH_MVEQZ = 13074 , LIEF::assembly::riscv::TH_MVNEZ = 13075 ,
  LIEF::assembly::riscv::TH_REV = 13076 , LIEF::assembly::riscv::TH_REVW = 13077 , LIEF::assembly::riscv::TH_SBIA = 13078 , LIEF::assembly::riscv::TH_SBIB = 13079 ,
  LIEF::assembly::riscv::TH_SDD = 13080 , LIEF::assembly::riscv::TH_SDIA = 13081 , LIEF::assembly::riscv::TH_SDIB = 13082 , LIEF::assembly::riscv::TH_SFENCE_VMAS = 13083 ,
  LIEF::assembly::riscv::TH_SHIA = 13084 , LIEF::assembly::riscv::TH_SHIB = 13085 , LIEF::assembly::riscv::TH_SRB = 13086 , LIEF::assembly::riscv::TH_SRD = 13087 ,
  LIEF::assembly::riscv::TH_SRH = 13088 , LIEF::assembly::riscv::TH_SRRI = 13089 , LIEF::assembly::riscv::TH_SRRIW = 13090 , LIEF::assembly::riscv::TH_SRW = 13091 ,
  LIEF::assembly::riscv::TH_SURB = 13092 , LIEF::assembly::riscv::TH_SURD = 13093 , LIEF::assembly::riscv::TH_SURH = 13094 , LIEF::assembly::riscv::TH_SURW = 13095 ,
  LIEF::assembly::riscv::TH_SWD = 13096 , LIEF::assembly::riscv::TH_SWIA = 13097 , LIEF::assembly::riscv::TH_SWIB = 13098 , LIEF::assembly::riscv::TH_SYNC = 13099 ,
  LIEF::assembly::riscv::TH_SYNC_I = 13100 , LIEF::assembly::riscv::TH_SYNC_IS = 13101 , LIEF::assembly::riscv::TH_SYNC_S = 13102 , LIEF::assembly::riscv::TH_TST = 13103 ,
  LIEF::assembly::riscv::TH_TSTNBZ = 13104 , LIEF::assembly::riscv::UNIMP = 13105 , LIEF::assembly::riscv::UNZIP_RV32 = 13106 , LIEF::assembly::riscv::VAADDU_VV = 13107 ,
  LIEF::assembly::riscv::VAADDU_VX = 13108 , LIEF::assembly::riscv::VAADD_VV = 13109 , LIEF::assembly::riscv::VAADD_VX = 13110 , LIEF::assembly::riscv::VADC_VIM = 13111 ,
  LIEF::assembly::riscv::VADC_VVM = 13112 , LIEF::assembly::riscv::VADC_VXM = 13113 , LIEF::assembly::riscv::VADD_VI = 13114 , LIEF::assembly::riscv::VADD_VV = 13115 ,
  LIEF::assembly::riscv::VADD_VX = 13116 , LIEF::assembly::riscv::VAESDF_VS = 13117 , LIEF::assembly::riscv::VAESDF_VV = 13118 , LIEF::assembly::riscv::VAESDM_VS = 13119 ,
  LIEF::assembly::riscv::VAESDM_VV = 13120 , LIEF::assembly::riscv::VAESEF_VS = 13121 , LIEF::assembly::riscv::VAESEF_VV = 13122 , LIEF::assembly::riscv::VAESEM_VS = 13123 ,
  LIEF::assembly::riscv::VAESEM_VV = 13124 , LIEF::assembly::riscv::VAESKF1_VI = 13125 , LIEF::assembly::riscv::VAESKF2_VI = 13126 , LIEF::assembly::riscv::VAESZ_VS = 13127 ,
  LIEF::assembly::riscv::VANDN_VV = 13128 , LIEF::assembly::riscv::VANDN_VX = 13129 , LIEF::assembly::riscv::VAND_VI = 13130 , LIEF::assembly::riscv::VAND_VV = 13131 ,
  LIEF::assembly::riscv::VAND_VX = 13132 , LIEF::assembly::riscv::VASUBU_VV = 13133 , LIEF::assembly::riscv::VASUBU_VX = 13134 , LIEF::assembly::riscv::VASUB_VV = 13135 ,
  LIEF::assembly::riscv::VASUB_VX = 13136 , LIEF::assembly::riscv::VBREV8_V = 13137 , LIEF::assembly::riscv::VBREV_V = 13138 , LIEF::assembly::riscv::VCLMULH_VV = 13139 ,
  LIEF::assembly::riscv::VCLMULH_VX = 13140 , LIEF::assembly::riscv::VCLMUL_VV = 13141 , LIEF::assembly::riscv::VCLMUL_VX = 13142 , LIEF::assembly::riscv::VCLZ_V = 13143 ,
  LIEF::assembly::riscv::VCOMPRESS_VM = 13144 , LIEF::assembly::riscv::VCPOP_M = 13145 , LIEF::assembly::riscv::VCPOP_V = 13146 , LIEF::assembly::riscv::VCTZ_V = 13147 ,
  LIEF::assembly::riscv::VC_FV = 13148 , LIEF::assembly::riscv::VC_FVV = 13149 , LIEF::assembly::riscv::VC_FVW = 13150 , LIEF::assembly::riscv::VC_I = 13151 ,
  LIEF::assembly::riscv::VC_IV = 13152 , LIEF::assembly::riscv::VC_IVV = 13153 , LIEF::assembly::riscv::VC_IVW = 13154 , LIEF::assembly::riscv::VC_VV = 13155 ,
  LIEF::assembly::riscv::VC_VVV = 13156 , LIEF::assembly::riscv::VC_VVW = 13157 , LIEF::assembly::riscv::VC_V_FV = 13158 , LIEF::assembly::riscv::VC_V_FVV = 13159 ,
  LIEF::assembly::riscv::VC_V_FVW = 13160 , LIEF::assembly::riscv::VC_V_I = 13161 , LIEF::assembly::riscv::VC_V_IV = 13162 , LIEF::assembly::riscv::VC_V_IVV = 13163 ,
  LIEF::assembly::riscv::VC_V_IVW = 13164 , LIEF::assembly::riscv::VC_V_VV = 13165 , LIEF::assembly::riscv::VC_V_VVV = 13166 , LIEF::assembly::riscv::VC_V_VVW = 13167 ,
  LIEF::assembly::riscv::VC_V_X = 13168 , LIEF::assembly::riscv::VC_V_XV = 13169 , LIEF::assembly::riscv::VC_V_XVV = 13170 , LIEF::assembly::riscv::VC_V_XVW = 13171 ,
  LIEF::assembly::riscv::VC_X = 13172 , LIEF::assembly::riscv::VC_XV = 13173 , LIEF::assembly::riscv::VC_XVV = 13174 , LIEF::assembly::riscv::VC_XVW = 13175 ,
  LIEF::assembly::riscv::VDIVU_VV = 13176 , LIEF::assembly::riscv::VDIVU_VX = 13177 , LIEF::assembly::riscv::VDIV_VV = 13178 , LIEF::assembly::riscv::VDIV_VX = 13179 ,
  LIEF::assembly::riscv::VFADD_VF = 13180 , LIEF::assembly::riscv::VFADD_VV = 13181 , LIEF::assembly::riscv::VFCLASS_V = 13182 , LIEF::assembly::riscv::VFCVT_F_XU_V = 13183 ,
  LIEF::assembly::riscv::VFCVT_F_X_V = 13184 , LIEF::assembly::riscv::VFCVT_RTZ_XU_F_V = 13185 , LIEF::assembly::riscv::VFCVT_RTZ_X_F_V = 13186 , LIEF::assembly::riscv::VFCVT_XU_F_V = 13187 ,
  LIEF::assembly::riscv::VFCVT_X_F_V = 13188 , LIEF::assembly::riscv::VFDIV_VF = 13189 , LIEF::assembly::riscv::VFDIV_VV = 13190 , LIEF::assembly::riscv::VFIRST_M = 13191 ,
  LIEF::assembly::riscv::VFMACC_VF = 13192 , LIEF::assembly::riscv::VFMACC_VV = 13193 , LIEF::assembly::riscv::VFMADD_VF = 13194 , LIEF::assembly::riscv::VFMADD_VV = 13195 ,
  LIEF::assembly::riscv::VFMAX_VF = 13196 , LIEF::assembly::riscv::VFMAX_VV = 13197 , LIEF::assembly::riscv::VFMERGE_VFM = 13198 , LIEF::assembly::riscv::VFMIN_VF = 13199 ,
  LIEF::assembly::riscv::VFMIN_VV = 13200 , LIEF::assembly::riscv::VFMSAC_VF = 13201 , LIEF::assembly::riscv::VFMSAC_VV = 13202 , LIEF::assembly::riscv::VFMSUB_VF = 13203 ,
  LIEF::assembly::riscv::VFMSUB_VV = 13204 , LIEF::assembly::riscv::VFMUL_VF = 13205 , LIEF::assembly::riscv::VFMUL_VV = 13206 , LIEF::assembly::riscv::VFMV_F_S = 13207 ,
  LIEF::assembly::riscv::VFMV_S_F = 13208 , LIEF::assembly::riscv::VFMV_V_F = 13209 , LIEF::assembly::riscv::VFNCVTBF16_F_F_W = 13210 , LIEF::assembly::riscv::VFNCVT_F_F_W = 13211 ,
  LIEF::assembly::riscv::VFNCVT_F_XU_W = 13212 , LIEF::assembly::riscv::VFNCVT_F_X_W = 13213 , LIEF::assembly::riscv::VFNCVT_ROD_F_F_W = 13214 , LIEF::assembly::riscv::VFNCVT_RTZ_XU_F_W = 13215 ,
  LIEF::assembly::riscv::VFNCVT_RTZ_X_F_W = 13216 , LIEF::assembly::riscv::VFNCVT_XU_F_W = 13217 , LIEF::assembly::riscv::VFNCVT_X_F_W = 13218 , LIEF::assembly::riscv::VFNMACC_VF = 13219 ,
  LIEF::assembly::riscv::VFNMACC_VV = 13220 , LIEF::assembly::riscv::VFNMADD_VF = 13221 , LIEF::assembly::riscv::VFNMADD_VV = 13222 , LIEF::assembly::riscv::VFNMSAC_VF = 13223 ,
  LIEF::assembly::riscv::VFNMSAC_VV = 13224 , LIEF::assembly::riscv::VFNMSUB_VF = 13225 , LIEF::assembly::riscv::VFNMSUB_VV = 13226 , LIEF::assembly::riscv::VFNRCLIP_XU_F_QF = 13227 ,
  LIEF::assembly::riscv::VFNRCLIP_X_F_QF = 13228 , LIEF::assembly::riscv::VFRDIV_VF = 13229 , LIEF::assembly::riscv::VFREC7_V = 13230 , LIEF::assembly::riscv::VFREDMAX_VS = 13231 ,
  LIEF::assembly::riscv::VFREDMIN_VS = 13232 , LIEF::assembly::riscv::VFREDOSUM_VS = 13233 , LIEF::assembly::riscv::VFREDUSUM_VS = 13234 , LIEF::assembly::riscv::VFRSQRT7_V = 13235 ,
  LIEF::assembly::riscv::VFRSUB_VF = 13236 , LIEF::assembly::riscv::VFSGNJN_VF = 13237 , LIEF::assembly::riscv::VFSGNJN_VV = 13238 , LIEF::assembly::riscv::VFSGNJX_VF = 13239 ,
  LIEF::assembly::riscv::VFSGNJX_VV = 13240 , LIEF::assembly::riscv::VFSGNJ_VF = 13241 , LIEF::assembly::riscv::VFSGNJ_VV = 13242 , LIEF::assembly::riscv::VFSLIDE1DOWN_VF = 13243 ,
  LIEF::assembly::riscv::VFSLIDE1UP_VF = 13244 , LIEF::assembly::riscv::VFSQRT_V = 13245 , LIEF::assembly::riscv::VFSUB_VF = 13246 , LIEF::assembly::riscv::VFSUB_VV = 13247 ,
  LIEF::assembly::riscv::VFWADD_VF = 13248 , LIEF::assembly::riscv::VFWADD_VV = 13249 , LIEF::assembly::riscv::VFWADD_WF = 13250 , LIEF::assembly::riscv::VFWADD_WV = 13251 ,
  LIEF::assembly::riscv::VFWCVTBF16_F_F_V = 13252 , LIEF::assembly::riscv::VFWCVT_F_F_V = 13253 , LIEF::assembly::riscv::VFWCVT_F_XU_V = 13254 , LIEF::assembly::riscv::VFWCVT_F_X_V = 13255 ,
  LIEF::assembly::riscv::VFWCVT_RTZ_XU_F_V = 13256 , LIEF::assembly::riscv::VFWCVT_RTZ_X_F_V = 13257 , LIEF::assembly::riscv::VFWCVT_XU_F_V = 13258 , LIEF::assembly::riscv::VFWCVT_X_F_V = 13259 ,
  LIEF::assembly::riscv::VFWMACCBF16_VF = 13260 , LIEF::assembly::riscv::VFWMACCBF16_VV = 13261 , LIEF::assembly::riscv::VFWMACC_4x4x4 = 13262 , LIEF::assembly::riscv::VFWMACC_VF = 13263 ,
  LIEF::assembly::riscv::VFWMACC_VV = 13264 , LIEF::assembly::riscv::VFWMSAC_VF = 13265 , LIEF::assembly::riscv::VFWMSAC_VV = 13266 , LIEF::assembly::riscv::VFWMUL_VF = 13267 ,
  LIEF::assembly::riscv::VFWMUL_VV = 13268 , LIEF::assembly::riscv::VFWNMACC_VF = 13269 , LIEF::assembly::riscv::VFWNMACC_VV = 13270 , LIEF::assembly::riscv::VFWNMSAC_VF = 13271 ,
  LIEF::assembly::riscv::VFWNMSAC_VV = 13272 , LIEF::assembly::riscv::VFWREDOSUM_VS = 13273 , LIEF::assembly::riscv::VFWREDUSUM_VS = 13274 , LIEF::assembly::riscv::VFWSUB_VF = 13275 ,
  LIEF::assembly::riscv::VFWSUB_VV = 13276 , LIEF::assembly::riscv::VFWSUB_WF = 13277 , LIEF::assembly::riscv::VFWSUB_WV = 13278 , LIEF::assembly::riscv::VGHSH_VV = 13279 ,
  LIEF::assembly::riscv::VGMUL_VV = 13280 , LIEF::assembly::riscv::VID_V = 13281 , LIEF::assembly::riscv::VIOTA_M = 13282 , LIEF::assembly::riscv::VL1RE16_V = 13283 ,
  LIEF::assembly::riscv::VL1RE32_V = 13284 , LIEF::assembly::riscv::VL1RE64_V = 13285 , LIEF::assembly::riscv::VL1RE8_V = 13286 , LIEF::assembly::riscv::VL2RE16_V = 13287 ,
  LIEF::assembly::riscv::VL2RE32_V = 13288 , LIEF::assembly::riscv::VL2RE64_V = 13289 , LIEF::assembly::riscv::VL2RE8_V = 13290 , LIEF::assembly::riscv::VL4RE16_V = 13291 ,
  LIEF::assembly::riscv::VL4RE32_V = 13292 , LIEF::assembly::riscv::VL4RE64_V = 13293 , LIEF::assembly::riscv::VL4RE8_V = 13294 , LIEF::assembly::riscv::VL8RE16_V = 13295 ,
  LIEF::assembly::riscv::VL8RE32_V = 13296 , LIEF::assembly::riscv::VL8RE64_V = 13297 , LIEF::assembly::riscv::VL8RE8_V = 13298 , LIEF::assembly::riscv::VLE16FF_V = 13299 ,
  LIEF::assembly::riscv::VLE16_V = 13300 , LIEF::assembly::riscv::VLE32FF_V = 13301 , LIEF::assembly::riscv::VLE32_V = 13302 , LIEF::assembly::riscv::VLE64FF_V = 13303 ,
  LIEF::assembly::riscv::VLE64_V = 13304 , LIEF::assembly::riscv::VLE8FF_V = 13305 , LIEF::assembly::riscv::VLE8_V = 13306 , LIEF::assembly::riscv::VLM_V = 13307 ,
  LIEF::assembly::riscv::VLOXEI16_V = 13308 , LIEF::assembly::riscv::VLOXEI32_V = 13309 , LIEF::assembly::riscv::VLOXEI64_V = 13310 , LIEF::assembly::riscv::VLOXEI8_V = 13311 ,
  LIEF::assembly::riscv::VLOXSEG2EI16_V = 13312 , LIEF::assembly::riscv::VLOXSEG2EI32_V = 13313 , LIEF::assembly::riscv::VLOXSEG2EI64_V = 13314 , LIEF::assembly::riscv::VLOXSEG2EI8_V = 13315 ,
  LIEF::assembly::riscv::VLOXSEG3EI16_V = 13316 , LIEF::assembly::riscv::VLOXSEG3EI32_V = 13317 , LIEF::assembly::riscv::VLOXSEG3EI64_V = 13318 , LIEF::assembly::riscv::VLOXSEG3EI8_V = 13319 ,
  LIEF::assembly::riscv::VLOXSEG4EI16_V = 13320 , LIEF::assembly::riscv::VLOXSEG4EI32_V = 13321 , LIEF::assembly::riscv::VLOXSEG4EI64_V = 13322 , LIEF::assembly::riscv::VLOXSEG4EI8_V = 13323 ,
  LIEF::assembly::riscv::VLOXSEG5EI16_V = 13324 , LIEF::assembly::riscv::VLOXSEG5EI32_V = 13325 , LIEF::assembly::riscv::VLOXSEG5EI64_V = 13326 , LIEF::assembly::riscv::VLOXSEG5EI8_V = 13327 ,
  LIEF::assembly::riscv::VLOXSEG6EI16_V = 13328 , LIEF::assembly::riscv::VLOXSEG6EI32_V = 13329 , LIEF::assembly::riscv::VLOXSEG6EI64_V = 13330 , LIEF::assembly::riscv::VLOXSEG6EI8_V = 13331 ,
  LIEF::assembly::riscv::VLOXSEG7EI16_V = 13332 , LIEF::assembly::riscv::VLOXSEG7EI32_V = 13333 , LIEF::assembly::riscv::VLOXSEG7EI64_V = 13334 , LIEF::assembly::riscv::VLOXSEG7EI8_V = 13335 ,
  LIEF::assembly::riscv::VLOXSEG8EI16_V = 13336 , LIEF::assembly::riscv::VLOXSEG8EI32_V = 13337 , LIEF::assembly::riscv::VLOXSEG8EI64_V = 13338 , LIEF::assembly::riscv::VLOXSEG8EI8_V = 13339 ,
  LIEF::assembly::riscv::VLSE16_V = 13340 , LIEF::assembly::riscv::VLSE32_V = 13341 , LIEF::assembly::riscv::VLSE64_V = 13342 , LIEF::assembly::riscv::VLSE8_V = 13343 ,
  LIEF::assembly::riscv::VLSEG2E16FF_V = 13344 , LIEF::assembly::riscv::VLSEG2E16_V = 13345 , LIEF::assembly::riscv::VLSEG2E32FF_V = 13346 , LIEF::assembly::riscv::VLSEG2E32_V = 13347 ,
  LIEF::assembly::riscv::VLSEG2E64FF_V = 13348 , LIEF::assembly::riscv::VLSEG2E64_V = 13349 , LIEF::assembly::riscv::VLSEG2E8FF_V = 13350 , LIEF::assembly::riscv::VLSEG2E8_V = 13351 ,
  LIEF::assembly::riscv::VLSEG3E16FF_V = 13352 , LIEF::assembly::riscv::VLSEG3E16_V = 13353 , LIEF::assembly::riscv::VLSEG3E32FF_V = 13354 , LIEF::assembly::riscv::VLSEG3E32_V = 13355 ,
  LIEF::assembly::riscv::VLSEG3E64FF_V = 13356 , LIEF::assembly::riscv::VLSEG3E64_V = 13357 , LIEF::assembly::riscv::VLSEG3E8FF_V = 13358 , LIEF::assembly::riscv::VLSEG3E8_V = 13359 ,
  LIEF::assembly::riscv::VLSEG4E16FF_V = 13360 , LIEF::assembly::riscv::VLSEG4E16_V = 13361 , LIEF::assembly::riscv::VLSEG4E32FF_V = 13362 , LIEF::assembly::riscv::VLSEG4E32_V = 13363 ,
  LIEF::assembly::riscv::VLSEG4E64FF_V = 13364 , LIEF::assembly::riscv::VLSEG4E64_V = 13365 , LIEF::assembly::riscv::VLSEG4E8FF_V = 13366 , LIEF::assembly::riscv::VLSEG4E8_V = 13367 ,
  LIEF::assembly::riscv::VLSEG5E16FF_V = 13368 , LIEF::assembly::riscv::VLSEG5E16_V = 13369 , LIEF::assembly::riscv::VLSEG5E32FF_V = 13370 , LIEF::assembly::riscv::VLSEG5E32_V = 13371 ,
  LIEF::assembly::riscv::VLSEG5E64FF_V = 13372 , LIEF::assembly::riscv::VLSEG5E64_V = 13373 , LIEF::assembly::riscv::VLSEG5E8FF_V = 13374 , LIEF::assembly::riscv::VLSEG5E8_V = 13375 ,
  LIEF::assembly::riscv::VLSEG6E16FF_V = 13376 , LIEF::assembly::riscv::VLSEG6E16_V = 13377 , LIEF::assembly::riscv::VLSEG6E32FF_V = 13378 , LIEF::assembly::riscv::VLSEG6E32_V = 13379 ,
  LIEF::assembly::riscv::VLSEG6E64FF_V = 13380 , LIEF::assembly::riscv::VLSEG6E64_V = 13381 , LIEF::assembly::riscv::VLSEG6E8FF_V = 13382 , LIEF::assembly::riscv::VLSEG6E8_V = 13383 ,
  LIEF::assembly::riscv::VLSEG7E16FF_V = 13384 , LIEF::assembly::riscv::VLSEG7E16_V = 13385 , LIEF::assembly::riscv::VLSEG7E32FF_V = 13386 , LIEF::assembly::riscv::VLSEG7E32_V = 13387 ,
  LIEF::assembly::riscv::VLSEG7E64FF_V = 13388 , LIEF::assembly::riscv::VLSEG7E64_V = 13389 , LIEF::assembly::riscv::VLSEG7E8FF_V = 13390 , LIEF::assembly::riscv::VLSEG7E8_V = 13391 ,
  LIEF::assembly::riscv::VLSEG8E16FF_V = 13392 , LIEF::assembly::riscv::VLSEG8E16_V = 13393 , LIEF::assembly::riscv::VLSEG8E32FF_V = 13394 , LIEF::assembly::riscv::VLSEG8E32_V = 13395 ,
  LIEF::assembly::riscv::VLSEG8E64FF_V = 13396 , LIEF::assembly::riscv::VLSEG8E64_V = 13397 , LIEF::assembly::riscv::VLSEG8E8FF_V = 13398 , LIEF::assembly::riscv::VLSEG8E8_V = 13399 ,
  LIEF::assembly::riscv::VLSSEG2E16_V = 13400 , LIEF::assembly::riscv::VLSSEG2E32_V = 13401 , LIEF::assembly::riscv::VLSSEG2E64_V = 13402 , LIEF::assembly::riscv::VLSSEG2E8_V = 13403 ,
  LIEF::assembly::riscv::VLSSEG3E16_V = 13404 , LIEF::assembly::riscv::VLSSEG3E32_V = 13405 , LIEF::assembly::riscv::VLSSEG3E64_V = 13406 , LIEF::assembly::riscv::VLSSEG3E8_V = 13407 ,
  LIEF::assembly::riscv::VLSSEG4E16_V = 13408 , LIEF::assembly::riscv::VLSSEG4E32_V = 13409 , LIEF::assembly::riscv::VLSSEG4E64_V = 13410 , LIEF::assembly::riscv::VLSSEG4E8_V = 13411 ,
  LIEF::assembly::riscv::VLSSEG5E16_V = 13412 , LIEF::assembly::riscv::VLSSEG5E32_V = 13413 , LIEF::assembly::riscv::VLSSEG5E64_V = 13414 , LIEF::assembly::riscv::VLSSEG5E8_V = 13415 ,
  LIEF::assembly::riscv::VLSSEG6E16_V = 13416 , LIEF::assembly::riscv::VLSSEG6E32_V = 13417 , LIEF::assembly::riscv::VLSSEG6E64_V = 13418 , LIEF::assembly::riscv::VLSSEG6E8_V = 13419 ,
  LIEF::assembly::riscv::VLSSEG7E16_V = 13420 , LIEF::assembly::riscv::VLSSEG7E32_V = 13421 , LIEF::assembly::riscv::VLSSEG7E64_V = 13422 , LIEF::assembly::riscv::VLSSEG7E8_V = 13423 ,
  LIEF::assembly::riscv::VLSSEG8E16_V = 13424 , LIEF::assembly::riscv::VLSSEG8E32_V = 13425 , LIEF::assembly::riscv::VLSSEG8E64_V = 13426 , LIEF::assembly::riscv::VLSSEG8E8_V = 13427 ,
  LIEF::assembly::riscv::VLUXEI16_V = 13428 , LIEF::assembly::riscv::VLUXEI32_V = 13429 , LIEF::assembly::riscv::VLUXEI64_V = 13430 , LIEF::assembly::riscv::VLUXEI8_V = 13431 ,
  LIEF::assembly::riscv::VLUXSEG2EI16_V = 13432 , LIEF::assembly::riscv::VLUXSEG2EI32_V = 13433 , LIEF::assembly::riscv::VLUXSEG2EI64_V = 13434 , LIEF::assembly::riscv::VLUXSEG2EI8_V = 13435 ,
  LIEF::assembly::riscv::VLUXSEG3EI16_V = 13436 , LIEF::assembly::riscv::VLUXSEG3EI32_V = 13437 , LIEF::assembly::riscv::VLUXSEG3EI64_V = 13438 , LIEF::assembly::riscv::VLUXSEG3EI8_V = 13439 ,
  LIEF::assembly::riscv::VLUXSEG4EI16_V = 13440 , LIEF::assembly::riscv::VLUXSEG4EI32_V = 13441 , LIEF::assembly::riscv::VLUXSEG4EI64_V = 13442 , LIEF::assembly::riscv::VLUXSEG4EI8_V = 13443 ,
  LIEF::assembly::riscv::VLUXSEG5EI16_V = 13444 , LIEF::assembly::riscv::VLUXSEG5EI32_V = 13445 , LIEF::assembly::riscv::VLUXSEG5EI64_V = 13446 , LIEF::assembly::riscv::VLUXSEG5EI8_V = 13447 ,
  LIEF::assembly::riscv::VLUXSEG6EI16_V = 13448 , LIEF::assembly::riscv::VLUXSEG6EI32_V = 13449 , LIEF::assembly::riscv::VLUXSEG6EI64_V = 13450 , LIEF::assembly::riscv::VLUXSEG6EI8_V = 13451 ,
  LIEF::assembly::riscv::VLUXSEG7EI16_V = 13452 , LIEF::assembly::riscv::VLUXSEG7EI32_V = 13453 , LIEF::assembly::riscv::VLUXSEG7EI64_V = 13454 , LIEF::assembly::riscv::VLUXSEG7EI8_V = 13455 ,
  LIEF::assembly::riscv::VLUXSEG8EI16_V = 13456 , LIEF::assembly::riscv::VLUXSEG8EI32_V = 13457 , LIEF::assembly::riscv::VLUXSEG8EI64_V = 13458 , LIEF::assembly::riscv::VLUXSEG8EI8_V = 13459 ,
  LIEF::assembly::riscv::VMACC_VV = 13460 , LIEF::assembly::riscv::VMACC_VX = 13461 , LIEF::assembly::riscv::VMADC_VI = 13462 , LIEF::assembly::riscv::VMADC_VIM = 13463 ,
  LIEF::assembly::riscv::VMADC_VV = 13464 , LIEF::assembly::riscv::VMADC_VVM = 13465 , LIEF::assembly::riscv::VMADC_VX = 13466 , LIEF::assembly::riscv::VMADC_VXM = 13467 ,
  LIEF::assembly::riscv::VMADD_VV = 13468 , LIEF::assembly::riscv::VMADD_VX = 13469 , LIEF::assembly::riscv::VMANDN_MM = 13470 , LIEF::assembly::riscv::VMAND_MM = 13471 ,
  LIEF::assembly::riscv::VMAXU_VV = 13472 , LIEF::assembly::riscv::VMAXU_VX = 13473 , LIEF::assembly::riscv::VMAX_VV = 13474 , LIEF::assembly::riscv::VMAX_VX = 13475 ,
  LIEF::assembly::riscv::VMERGE_VIM = 13476 , LIEF::assembly::riscv::VMERGE_VVM = 13477 , LIEF::assembly::riscv::VMERGE_VXM = 13478 , LIEF::assembly::riscv::VMFEQ_VF = 13479 ,
  LIEF::assembly::riscv::VMFEQ_VV = 13480 , LIEF::assembly::riscv::VMFGE_VF = 13481 , LIEF::assembly::riscv::VMFGT_VF = 13482 , LIEF::assembly::riscv::VMFLE_VF = 13483 ,
  LIEF::assembly::riscv::VMFLE_VV = 13484 , LIEF::assembly::riscv::VMFLT_VF = 13485 , LIEF::assembly::riscv::VMFLT_VV = 13486 , LIEF::assembly::riscv::VMFNE_VF = 13487 ,
  LIEF::assembly::riscv::VMFNE_VV = 13488 , LIEF::assembly::riscv::VMINU_VV = 13489 , LIEF::assembly::riscv::VMINU_VX = 13490 , LIEF::assembly::riscv::VMIN_VV = 13491 ,
  LIEF::assembly::riscv::VMIN_VX = 13492 , LIEF::assembly::riscv::VMNAND_MM = 13493 , LIEF::assembly::riscv::VMNOR_MM = 13494 , LIEF::assembly::riscv::VMORN_MM = 13495 ,
  LIEF::assembly::riscv::VMOR_MM = 13496 , LIEF::assembly::riscv::VMSBC_VV = 13497 , LIEF::assembly::riscv::VMSBC_VVM = 13498 , LIEF::assembly::riscv::VMSBC_VX = 13499 ,
  LIEF::assembly::riscv::VMSBC_VXM = 13500 , LIEF::assembly::riscv::VMSBF_M = 13501 , LIEF::assembly::riscv::VMSEQ_VI = 13502 , LIEF::assembly::riscv::VMSEQ_VV = 13503 ,
  LIEF::assembly::riscv::VMSEQ_VX = 13504 , LIEF::assembly::riscv::VMSGTU_VI = 13505 , LIEF::assembly::riscv::VMSGTU_VX = 13506 , LIEF::assembly::riscv::VMSGT_VI = 13507 ,
  LIEF::assembly::riscv::VMSGT_VX = 13508 , LIEF::assembly::riscv::VMSIF_M = 13509 , LIEF::assembly::riscv::VMSLEU_VI = 13510 , LIEF::assembly::riscv::VMSLEU_VV = 13511 ,
  LIEF::assembly::riscv::VMSLEU_VX = 13512 , LIEF::assembly::riscv::VMSLE_VI = 13513 , LIEF::assembly::riscv::VMSLE_VV = 13514 , LIEF::assembly::riscv::VMSLE_VX = 13515 ,
  LIEF::assembly::riscv::VMSLTU_VV = 13516 , LIEF::assembly::riscv::VMSLTU_VX = 13517 , LIEF::assembly::riscv::VMSLT_VV = 13518 , LIEF::assembly::riscv::VMSLT_VX = 13519 ,
  LIEF::assembly::riscv::VMSNE_VI = 13520 , LIEF::assembly::riscv::VMSNE_VV = 13521 , LIEF::assembly::riscv::VMSNE_VX = 13522 , LIEF::assembly::riscv::VMSOF_M = 13523 ,
  LIEF::assembly::riscv::VMULHSU_VV = 13524 , LIEF::assembly::riscv::VMULHSU_VX = 13525 , LIEF::assembly::riscv::VMULHU_VV = 13526 , LIEF::assembly::riscv::VMULHU_VX = 13527 ,
  LIEF::assembly::riscv::VMULH_VV = 13528 , LIEF::assembly::riscv::VMULH_VX = 13529 , LIEF::assembly::riscv::VMUL_VV = 13530 , LIEF::assembly::riscv::VMUL_VX = 13531 ,
  LIEF::assembly::riscv::VMV1R_V = 13532 , LIEF::assembly::riscv::VMV2R_V = 13533 , LIEF::assembly::riscv::VMV4R_V = 13534 , LIEF::assembly::riscv::VMV8R_V = 13535 ,
  LIEF::assembly::riscv::VMV_S_X = 13536 , LIEF::assembly::riscv::VMV_V_I = 13537 , LIEF::assembly::riscv::VMV_V_V = 13538 , LIEF::assembly::riscv::VMV_V_X = 13539 ,
  LIEF::assembly::riscv::VMV_X_S = 13540 , LIEF::assembly::riscv::VMXNOR_MM = 13541 , LIEF::assembly::riscv::VMXOR_MM = 13542 , LIEF::assembly::riscv::VNCLIPU_WI = 13543 ,
  LIEF::assembly::riscv::VNCLIPU_WV = 13544 , LIEF::assembly::riscv::VNCLIPU_WX = 13545 , LIEF::assembly::riscv::VNCLIP_WI = 13546 , LIEF::assembly::riscv::VNCLIP_WV = 13547 ,
  LIEF::assembly::riscv::VNCLIP_WX = 13548 , LIEF::assembly::riscv::VNMSAC_VV = 13549 , LIEF::assembly::riscv::VNMSAC_VX = 13550 , LIEF::assembly::riscv::VNMSUB_VV = 13551 ,
  LIEF::assembly::riscv::VNMSUB_VX = 13552 , LIEF::assembly::riscv::VNSRA_WI = 13553 , LIEF::assembly::riscv::VNSRA_WV = 13554 , LIEF::assembly::riscv::VNSRA_WX = 13555 ,
  LIEF::assembly::riscv::VNSRL_WI = 13556 , LIEF::assembly::riscv::VNSRL_WV = 13557 , LIEF::assembly::riscv::VNSRL_WX = 13558 , LIEF::assembly::riscv::VOR_VI = 13559 ,
  LIEF::assembly::riscv::VOR_VV = 13560 , LIEF::assembly::riscv::VOR_VX = 13561 , LIEF::assembly::riscv::VQMACCSU_2x8x2 = 13562 , LIEF::assembly::riscv::VQMACCSU_4x8x4 = 13563 ,
  LIEF::assembly::riscv::VQMACCUS_2x8x2 = 13564 , LIEF::assembly::riscv::VQMACCUS_4x8x4 = 13565 , LIEF::assembly::riscv::VQMACCU_2x8x2 = 13566 , LIEF::assembly::riscv::VQMACCU_4x8x4 = 13567 ,
  LIEF::assembly::riscv::VQMACC_2x8x2 = 13568 , LIEF::assembly::riscv::VQMACC_4x8x4 = 13569 , LIEF::assembly::riscv::VREDAND_VS = 13570 , LIEF::assembly::riscv::VREDMAXU_VS = 13571 ,
  LIEF::assembly::riscv::VREDMAX_VS = 13572 , LIEF::assembly::riscv::VREDMINU_VS = 13573 , LIEF::assembly::riscv::VREDMIN_VS = 13574 , LIEF::assembly::riscv::VREDOR_VS = 13575 ,
  LIEF::assembly::riscv::VREDSUM_VS = 13576 , LIEF::assembly::riscv::VREDXOR_VS = 13577 , LIEF::assembly::riscv::VREMU_VV = 13578 , LIEF::assembly::riscv::VREMU_VX = 13579 ,
  LIEF::assembly::riscv::VREM_VV = 13580 , LIEF::assembly::riscv::VREM_VX = 13581 , LIEF::assembly::riscv::VREV8_V = 13582 , LIEF::assembly::riscv::VRGATHEREI16_VV = 13583 ,
  LIEF::assembly::riscv::VRGATHER_VI = 13584 , LIEF::assembly::riscv::VRGATHER_VV = 13585 , LIEF::assembly::riscv::VRGATHER_VX = 13586 , LIEF::assembly::riscv::VROL_VV = 13587 ,
  LIEF::assembly::riscv::VROL_VX = 13588 , LIEF::assembly::riscv::VROR_VI = 13589 , LIEF::assembly::riscv::VROR_VV = 13590 , LIEF::assembly::riscv::VROR_VX = 13591 ,
  LIEF::assembly::riscv::VRSUB_VI = 13592 , LIEF::assembly::riscv::VRSUB_VX = 13593 , LIEF::assembly::riscv::VS1R_V = 13594 , LIEF::assembly::riscv::VS2R_V = 13595 ,
  LIEF::assembly::riscv::VS4R_V = 13596 , LIEF::assembly::riscv::VS8R_V = 13597 , LIEF::assembly::riscv::VSADDU_VI = 13598 , LIEF::assembly::riscv::VSADDU_VV = 13599 ,
  LIEF::assembly::riscv::VSADDU_VX = 13600 , LIEF::assembly::riscv::VSADD_VI = 13601 , LIEF::assembly::riscv::VSADD_VV = 13602 , LIEF::assembly::riscv::VSADD_VX = 13603 ,
  LIEF::assembly::riscv::VSBC_VVM = 13604 , LIEF::assembly::riscv::VSBC_VXM = 13605 , LIEF::assembly::riscv::VSE16_V = 13606 , LIEF::assembly::riscv::VSE32_V = 13607 ,
  LIEF::assembly::riscv::VSE64_V = 13608 , LIEF::assembly::riscv::VSE8_V = 13609 , LIEF::assembly::riscv::VSETIVLI = 13610 , LIEF::assembly::riscv::VSETVL = 13611 ,
  LIEF::assembly::riscv::VSETVLI = 13612 , LIEF::assembly::riscv::VSEXT_VF2 = 13613 , LIEF::assembly::riscv::VSEXT_VF4 = 13614 , LIEF::assembly::riscv::VSEXT_VF8 = 13615 ,
  LIEF::assembly::riscv::VSHA2CH_VV = 13616 , LIEF::assembly::riscv::VSHA2CL_VV = 13617 , LIEF::assembly::riscv::VSHA2MS_VV = 13618 , LIEF::assembly::riscv::VSLIDE1DOWN_VX = 13619 ,
  LIEF::assembly::riscv::VSLIDE1UP_VX = 13620 , LIEF::assembly::riscv::VSLIDEDOWN_VI = 13621 , LIEF::assembly::riscv::VSLIDEDOWN_VX = 13622 , LIEF::assembly::riscv::VSLIDEUP_VI = 13623 ,
  LIEF::assembly::riscv::VSLIDEUP_VX = 13624 , LIEF::assembly::riscv::VSLL_VI = 13625 , LIEF::assembly::riscv::VSLL_VV = 13626 , LIEF::assembly::riscv::VSLL_VX = 13627 ,
  LIEF::assembly::riscv::VSM3C_VI = 13628 , LIEF::assembly::riscv::VSM3ME_VV = 13629 , LIEF::assembly::riscv::VSM4K_VI = 13630 , LIEF::assembly::riscv::VSM4R_VS = 13631 ,
  LIEF::assembly::riscv::VSM4R_VV = 13632 , LIEF::assembly::riscv::VSMUL_VV = 13633 , LIEF::assembly::riscv::VSMUL_VX = 13634 , LIEF::assembly::riscv::VSM_V = 13635 ,
  LIEF::assembly::riscv::VSOXEI16_V = 13636 , LIEF::assembly::riscv::VSOXEI32_V = 13637 , LIEF::assembly::riscv::VSOXEI64_V = 13638 , LIEF::assembly::riscv::VSOXEI8_V = 13639 ,
  LIEF::assembly::riscv::VSOXSEG2EI16_V = 13640 , LIEF::assembly::riscv::VSOXSEG2EI32_V = 13641 , LIEF::assembly::riscv::VSOXSEG2EI64_V = 13642 , LIEF::assembly::riscv::VSOXSEG2EI8_V = 13643 ,
  LIEF::assembly::riscv::VSOXSEG3EI16_V = 13644 , LIEF::assembly::riscv::VSOXSEG3EI32_V = 13645 , LIEF::assembly::riscv::VSOXSEG3EI64_V = 13646 , LIEF::assembly::riscv::VSOXSEG3EI8_V = 13647 ,
  LIEF::assembly::riscv::VSOXSEG4EI16_V = 13648 , LIEF::assembly::riscv::VSOXSEG4EI32_V = 13649 , LIEF::assembly::riscv::VSOXSEG4EI64_V = 13650 , LIEF::assembly::riscv::VSOXSEG4EI8_V = 13651 ,
  LIEF::assembly::riscv::VSOXSEG5EI16_V = 13652 , LIEF::assembly::riscv::VSOXSEG5EI32_V = 13653 , LIEF::assembly::riscv::VSOXSEG5EI64_V = 13654 , LIEF::assembly::riscv::VSOXSEG5EI8_V = 13655 ,
  LIEF::assembly::riscv::VSOXSEG6EI16_V = 13656 , LIEF::assembly::riscv::VSOXSEG6EI32_V = 13657 , LIEF::assembly::riscv::VSOXSEG6EI64_V = 13658 , LIEF::assembly::riscv::VSOXSEG6EI8_V = 13659 ,
  LIEF::assembly::riscv::VSOXSEG7EI16_V = 13660 , LIEF::assembly::riscv::VSOXSEG7EI32_V = 13661 , LIEF::assembly::riscv::VSOXSEG7EI64_V = 13662 , LIEF::assembly::riscv::VSOXSEG7EI8_V = 13663 ,
  LIEF::assembly::riscv::VSOXSEG8EI16_V = 13664 , LIEF::assembly::riscv::VSOXSEG8EI32_V = 13665 , LIEF::assembly::riscv::VSOXSEG8EI64_V = 13666 , LIEF::assembly::riscv::VSOXSEG8EI8_V = 13667 ,
  LIEF::assembly::riscv::VSRA_VI = 13668 , LIEF::assembly::riscv::VSRA_VV = 13669 , LIEF::assembly::riscv::VSRA_VX = 13670 , LIEF::assembly::riscv::VSRL_VI = 13671 ,
  LIEF::assembly::riscv::VSRL_VV = 13672 , LIEF::assembly::riscv::VSRL_VX = 13673 , LIEF::assembly::riscv::VSSE16_V = 13674 , LIEF::assembly::riscv::VSSE32_V = 13675 ,
  LIEF::assembly::riscv::VSSE64_V = 13676 , LIEF::assembly::riscv::VSSE8_V = 13677 , LIEF::assembly::riscv::VSSEG2E16_V = 13678 , LIEF::assembly::riscv::VSSEG2E32_V = 13679 ,
  LIEF::assembly::riscv::VSSEG2E64_V = 13680 , LIEF::assembly::riscv::VSSEG2E8_V = 13681 , LIEF::assembly::riscv::VSSEG3E16_V = 13682 , LIEF::assembly::riscv::VSSEG3E32_V = 13683 ,
  LIEF::assembly::riscv::VSSEG3E64_V = 13684 , LIEF::assembly::riscv::VSSEG3E8_V = 13685 , LIEF::assembly::riscv::VSSEG4E16_V = 13686 , LIEF::assembly::riscv::VSSEG4E32_V = 13687 ,
  LIEF::assembly::riscv::VSSEG4E64_V = 13688 , LIEF::assembly::riscv::VSSEG4E8_V = 13689 , LIEF::assembly::riscv::VSSEG5E16_V = 13690 , LIEF::assembly::riscv::VSSEG5E32_V = 13691 ,
  LIEF::assembly::riscv::VSSEG5E64_V = 13692 , LIEF::assembly::riscv::VSSEG5E8_V = 13693 , LIEF::assembly::riscv::VSSEG6E16_V = 13694 , LIEF::assembly::riscv::VSSEG6E32_V = 13695 ,
  LIEF::assembly::riscv::VSSEG6E64_V = 13696 , LIEF::assembly::riscv::VSSEG6E8_V = 13697 , LIEF::assembly::riscv::VSSEG7E16_V = 13698 , LIEF::assembly::riscv::VSSEG7E32_V = 13699 ,
  LIEF::assembly::riscv::VSSEG7E64_V = 13700 , LIEF::assembly::riscv::VSSEG7E8_V = 13701 , LIEF::assembly::riscv::VSSEG8E16_V = 13702 , LIEF::assembly::riscv::VSSEG8E32_V = 13703 ,
  LIEF::assembly::riscv::VSSEG8E64_V = 13704 , LIEF::assembly::riscv::VSSEG8E8_V = 13705 , LIEF::assembly::riscv::VSSRA_VI = 13706 , LIEF::assembly::riscv::VSSRA_VV = 13707 ,
  LIEF::assembly::riscv::VSSRA_VX = 13708 , LIEF::assembly::riscv::VSSRL_VI = 13709 , LIEF::assembly::riscv::VSSRL_VV = 13710 , LIEF::assembly::riscv::VSSRL_VX = 13711 ,
  LIEF::assembly::riscv::VSSSEG2E16_V = 13712 , LIEF::assembly::riscv::VSSSEG2E32_V = 13713 , LIEF::assembly::riscv::VSSSEG2E64_V = 13714 , LIEF::assembly::riscv::VSSSEG2E8_V = 13715 ,
  LIEF::assembly::riscv::VSSSEG3E16_V = 13716 , LIEF::assembly::riscv::VSSSEG3E32_V = 13717 , LIEF::assembly::riscv::VSSSEG3E64_V = 13718 , LIEF::assembly::riscv::VSSSEG3E8_V = 13719 ,
  LIEF::assembly::riscv::VSSSEG4E16_V = 13720 , LIEF::assembly::riscv::VSSSEG4E32_V = 13721 , LIEF::assembly::riscv::VSSSEG4E64_V = 13722 , LIEF::assembly::riscv::VSSSEG4E8_V = 13723 ,
  LIEF::assembly::riscv::VSSSEG5E16_V = 13724 , LIEF::assembly::riscv::VSSSEG5E32_V = 13725 , LIEF::assembly::riscv::VSSSEG5E64_V = 13726 , LIEF::assembly::riscv::VSSSEG5E8_V = 13727 ,
  LIEF::assembly::riscv::VSSSEG6E16_V = 13728 , LIEF::assembly::riscv::VSSSEG6E32_V = 13729 , LIEF::assembly::riscv::VSSSEG6E64_V = 13730 , LIEF::assembly::riscv::VSSSEG6E8_V = 13731 ,
  LIEF::assembly::riscv::VSSSEG7E16_V = 13732 , LIEF::assembly::riscv::VSSSEG7E32_V = 13733 , LIEF::assembly::riscv::VSSSEG7E64_V = 13734 , LIEF::assembly::riscv::VSSSEG7E8_V = 13735 ,
  LIEF::assembly::riscv::VSSSEG8E16_V = 13736 , LIEF::assembly::riscv::VSSSEG8E32_V = 13737 , LIEF::assembly::riscv::VSSSEG8E64_V = 13738 , LIEF::assembly::riscv::VSSSEG8E8_V = 13739 ,
  LIEF::assembly::riscv::VSSUBU_VV = 13740 , LIEF::assembly::riscv::VSSUBU_VX = 13741 , LIEF::assembly::riscv::VSSUB_VV = 13742 , LIEF::assembly::riscv::VSSUB_VX = 13743 ,
  LIEF::assembly::riscv::VSUB_VV = 13744 , LIEF::assembly::riscv::VSUB_VX = 13745 , LIEF::assembly::riscv::VSUXEI16_V = 13746 , LIEF::assembly::riscv::VSUXEI32_V = 13747 ,
  LIEF::assembly::riscv::VSUXEI64_V = 13748 , LIEF::assembly::riscv::VSUXEI8_V = 13749 , LIEF::assembly::riscv::VSUXSEG2EI16_V = 13750 , LIEF::assembly::riscv::VSUXSEG2EI32_V = 13751 ,
  LIEF::assembly::riscv::VSUXSEG2EI64_V = 13752 , LIEF::assembly::riscv::VSUXSEG2EI8_V = 13753 , LIEF::assembly::riscv::VSUXSEG3EI16_V = 13754 , LIEF::assembly::riscv::VSUXSEG3EI32_V = 13755 ,
  LIEF::assembly::riscv::VSUXSEG3EI64_V = 13756 , LIEF::assembly::riscv::VSUXSEG3EI8_V = 13757 , LIEF::assembly::riscv::VSUXSEG4EI16_V = 13758 , LIEF::assembly::riscv::VSUXSEG4EI32_V = 13759 ,
  LIEF::assembly::riscv::VSUXSEG4EI64_V = 13760 , LIEF::assembly::riscv::VSUXSEG4EI8_V = 13761 , LIEF::assembly::riscv::VSUXSEG5EI16_V = 13762 , LIEF::assembly::riscv::VSUXSEG5EI32_V = 13763 ,
  LIEF::assembly::riscv::VSUXSEG5EI64_V = 13764 , LIEF::assembly::riscv::VSUXSEG5EI8_V = 13765 , LIEF::assembly::riscv::VSUXSEG6EI16_V = 13766 , LIEF::assembly::riscv::VSUXSEG6EI32_V = 13767 ,
  LIEF::assembly::riscv::VSUXSEG6EI64_V = 13768 , LIEF::assembly::riscv::VSUXSEG6EI8_V = 13769 , LIEF::assembly::riscv::VSUXSEG7EI16_V = 13770 , LIEF::assembly::riscv::VSUXSEG7EI32_V = 13771 ,
  LIEF::assembly::riscv::VSUXSEG7EI64_V = 13772 , LIEF::assembly::riscv::VSUXSEG7EI8_V = 13773 , LIEF::assembly::riscv::VSUXSEG8EI16_V = 13774 , LIEF::assembly::riscv::VSUXSEG8EI32_V = 13775 ,
  LIEF::assembly::riscv::VSUXSEG8EI64_V = 13776 , LIEF::assembly::riscv::VSUXSEG8EI8_V = 13777 , LIEF::assembly::riscv::VT_MASKC = 13778 , LIEF::assembly::riscv::VT_MASKCN = 13779 ,
  LIEF::assembly::riscv::VWADDU_VV = 13780 , LIEF::assembly::riscv::VWADDU_VX = 13781 , LIEF::assembly::riscv::VWADDU_WV = 13782 , LIEF::assembly::riscv::VWADDU_WX = 13783 ,
  LIEF::assembly::riscv::VWADD_VV = 13784 , LIEF::assembly::riscv::VWADD_VX = 13785 , LIEF::assembly::riscv::VWADD_WV = 13786 , LIEF::assembly::riscv::VWADD_WX = 13787 ,
  LIEF::assembly::riscv::VWMACCSU_VV = 13788 , LIEF::assembly::riscv::VWMACCSU_VX = 13789 , LIEF::assembly::riscv::VWMACCUS_VX = 13790 , LIEF::assembly::riscv::VWMACCU_VV = 13791 ,
  LIEF::assembly::riscv::VWMACCU_VX = 13792 , LIEF::assembly::riscv::VWMACC_VV = 13793 , LIEF::assembly::riscv::VWMACC_VX = 13794 , LIEF::assembly::riscv::VWMULSU_VV = 13795 ,
  LIEF::assembly::riscv::VWMULSU_VX = 13796 , LIEF::assembly::riscv::VWMULU_VV = 13797 , LIEF::assembly::riscv::VWMULU_VX = 13798 , LIEF::assembly::riscv::VWMUL_VV = 13799 ,
  LIEF::assembly::riscv::VWMUL_VX = 13800 , LIEF::assembly::riscv::VWREDSUMU_VS = 13801 , LIEF::assembly::riscv::VWREDSUM_VS = 13802 , LIEF::assembly::riscv::VWSLL_VI = 13803 ,
  LIEF::assembly::riscv::VWSLL_VV = 13804 , LIEF::assembly::riscv::VWSLL_VX = 13805 , LIEF::assembly::riscv::VWSUBU_VV = 13806 , LIEF::assembly::riscv::VWSUBU_VX = 13807 ,
  LIEF::assembly::riscv::VWSUBU_WV = 13808 , LIEF::assembly::riscv::VWSUBU_WX = 13809 , LIEF::assembly::riscv::VWSUB_VV = 13810 , LIEF::assembly::riscv::VWSUB_VX = 13811 ,
  LIEF::assembly::riscv::VWSUB_WV = 13812 , LIEF::assembly::riscv::VWSUB_WX = 13813 , LIEF::assembly::riscv::VXOR_VI = 13814 , LIEF::assembly::riscv::VXOR_VV = 13815 ,
  LIEF::assembly::riscv::VXOR_VX = 13816 , LIEF::assembly::riscv::VZEXT_VF2 = 13817 , LIEF::assembly::riscv::VZEXT_VF4 = 13818 , LIEF::assembly::riscv::VZEXT_VF8 = 13819 ,
  LIEF::assembly::riscv::WFI = 13820 , LIEF::assembly::riscv::WRS_NTO = 13821 , LIEF::assembly::riscv::WRS_STO = 13822 , LIEF::assembly::riscv::XNOR = 13823 ,
  LIEF::assembly::riscv::XOR = 13824 , LIEF::assembly::riscv::XORI = 13825 , LIEF::assembly::riscv::XPERM4 = 13826 , LIEF::assembly::riscv::XPERM8 = 13827 ,
  LIEF::assembly::riscv::ZEXT_H_RV32 = 13828 , LIEF::assembly::riscv::ZEXT_H_RV64 = 13829 , LIEF::assembly::riscv::ZIP_RV32 = 13830 , LIEF::assembly::riscv::INSTRUCTION_LIST_END = 13831
}
 
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