LIEF: Library to Instrument Executable Formats Version 0.16.4
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riscv/opcodes.hpp
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1/* Copyright 2022 - 2024 R. Thomas
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15#ifndef LIEF_ASM_RISCV_OPCODE_H
16#define LIEF_ASM_RISCV_OPCODE_H
17
18/* Generated from LLVM: 19.1.2 */
19
20namespace LIEF {
21namespace assembly {
22namespace riscv {
23enum class OPCODE {
24 PHI = 0,
25 INLINEASM = 1,
26 INLINEASM_BR = 2,
27 CFI_INSTRUCTION = 3,
28 EH_LABEL = 4,
29 GC_LABEL = 5,
30 ANNOTATION_LABEL = 6,
31 KILL = 7,
32 EXTRACT_SUBREG = 8,
33 INSERT_SUBREG = 9,
34 IMPLICIT_DEF = 10,
35 SUBREG_TO_REG = 11,
36 COPY_TO_REGCLASS = 12,
37 DBG_VALUE = 13,
38 DBG_VALUE_LIST = 14,
39 DBG_INSTR_REF = 15,
40 DBG_PHI = 16,
41 DBG_LABEL = 17,
42 REG_SEQUENCE = 18,
43 COPY = 19,
44 BUNDLE = 20,
45 LIFETIME_START = 21,
46 LIFETIME_END = 22,
47 PSEUDO_PROBE = 23,
48 ARITH_FENCE = 24,
49 STACKMAP = 25,
50 FENTRY_CALL = 26,
51 PATCHPOINT = 27,
52 LOAD_STACK_GUARD = 28,
53 PREALLOCATED_SETUP = 29,
54 PREALLOCATED_ARG = 30,
55 STATEPOINT = 31,
56 LOCAL_ESCAPE = 32,
57 FAULTING_OP = 33,
58 PATCHABLE_OP = 34,
59 PATCHABLE_FUNCTION_ENTER = 35,
60 PATCHABLE_RET = 36,
61 PATCHABLE_FUNCTION_EXIT = 37,
62 PATCHABLE_TAIL_CALL = 38,
63 PATCHABLE_EVENT_CALL = 39,
64 PATCHABLE_TYPED_EVENT_CALL = 40,
65 ICALL_BRANCH_FUNNEL = 41,
66 MEMBARRIER = 42,
67 JUMP_TABLE_DEBUG_INFO = 43,
68 CONVERGENCECTRL_ENTRY = 44,
69 CONVERGENCECTRL_ANCHOR = 45,
70 CONVERGENCECTRL_LOOP = 46,
71 CONVERGENCECTRL_GLUE = 47,
72 G_ASSERT_SEXT = 48,
73 G_ASSERT_ZEXT = 49,
74 G_ASSERT_ALIGN = 50,
75 G_ADD = 51,
76 G_SUB = 52,
77 G_MUL = 53,
78 G_SDIV = 54,
79 G_UDIV = 55,
80 G_SREM = 56,
81 G_UREM = 57,
82 G_SDIVREM = 58,
83 G_UDIVREM = 59,
84 G_AND = 60,
85 G_OR = 61,
86 G_XOR = 62,
87 G_IMPLICIT_DEF = 63,
88 G_PHI = 64,
89 G_FRAME_INDEX = 65,
90 G_GLOBAL_VALUE = 66,
91 G_PTRAUTH_GLOBAL_VALUE = 67,
92 G_CONSTANT_POOL = 68,
93 G_EXTRACT = 69,
94 G_UNMERGE_VALUES = 70,
95 G_INSERT = 71,
96 G_MERGE_VALUES = 72,
97 G_BUILD_VECTOR = 73,
98 G_BUILD_VECTOR_TRUNC = 74,
99 G_CONCAT_VECTORS = 75,
100 G_PTRTOINT = 76,
101 G_INTTOPTR = 77,
102 G_BITCAST = 78,
103 G_FREEZE = 79,
104 G_CONSTANT_FOLD_BARRIER = 80,
105 G_INTRINSIC_FPTRUNC_ROUND = 81,
106 G_INTRINSIC_TRUNC = 82,
107 G_INTRINSIC_ROUND = 83,
108 G_INTRINSIC_LRINT = 84,
109 G_INTRINSIC_LLRINT = 85,
110 G_INTRINSIC_ROUNDEVEN = 86,
111 G_READCYCLECOUNTER = 87,
112 G_READSTEADYCOUNTER = 88,
113 G_LOAD = 89,
114 G_SEXTLOAD = 90,
115 G_ZEXTLOAD = 91,
116 G_INDEXED_LOAD = 92,
117 G_INDEXED_SEXTLOAD = 93,
118 G_INDEXED_ZEXTLOAD = 94,
119 G_STORE = 95,
120 G_INDEXED_STORE = 96,
121 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
122 G_ATOMIC_CMPXCHG = 98,
123 G_ATOMICRMW_XCHG = 99,
124 G_ATOMICRMW_ADD = 100,
125 G_ATOMICRMW_SUB = 101,
126 G_ATOMICRMW_AND = 102,
127 G_ATOMICRMW_NAND = 103,
128 G_ATOMICRMW_OR = 104,
129 G_ATOMICRMW_XOR = 105,
130 G_ATOMICRMW_MAX = 106,
131 G_ATOMICRMW_MIN = 107,
132 G_ATOMICRMW_UMAX = 108,
133 G_ATOMICRMW_UMIN = 109,
134 G_ATOMICRMW_FADD = 110,
135 G_ATOMICRMW_FSUB = 111,
136 G_ATOMICRMW_FMAX = 112,
137 G_ATOMICRMW_FMIN = 113,
138 G_ATOMICRMW_UINC_WRAP = 114,
139 G_ATOMICRMW_UDEC_WRAP = 115,
140 G_FENCE = 116,
141 G_PREFETCH = 117,
142 G_BRCOND = 118,
143 G_BRINDIRECT = 119,
144 G_INVOKE_REGION_START = 120,
145 G_INTRINSIC = 121,
146 G_INTRINSIC_W_SIDE_EFFECTS = 122,
147 G_INTRINSIC_CONVERGENT = 123,
148 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
149 G_ANYEXT = 125,
150 G_TRUNC = 126,
151 G_CONSTANT = 127,
152 G_FCONSTANT = 128,
153 G_VASTART = 129,
154 G_VAARG = 130,
155 G_SEXT = 131,
156 G_SEXT_INREG = 132,
157 G_ZEXT = 133,
158 G_SHL = 134,
159 G_LSHR = 135,
160 G_ASHR = 136,
161 G_FSHL = 137,
162 G_FSHR = 138,
163 G_ROTR = 139,
164 G_ROTL = 140,
165 G_ICMP = 141,
166 G_FCMP = 142,
167 G_SCMP = 143,
168 G_UCMP = 144,
169 G_SELECT = 145,
170 G_UADDO = 146,
171 G_UADDE = 147,
172 G_USUBO = 148,
173 G_USUBE = 149,
174 G_SADDO = 150,
175 G_SADDE = 151,
176 G_SSUBO = 152,
177 G_SSUBE = 153,
178 G_UMULO = 154,
179 G_SMULO = 155,
180 G_UMULH = 156,
181 G_SMULH = 157,
182 G_UADDSAT = 158,
183 G_SADDSAT = 159,
184 G_USUBSAT = 160,
185 G_SSUBSAT = 161,
186 G_USHLSAT = 162,
187 G_SSHLSAT = 163,
188 G_SMULFIX = 164,
189 G_UMULFIX = 165,
190 G_SMULFIXSAT = 166,
191 G_UMULFIXSAT = 167,
192 G_SDIVFIX = 168,
193 G_UDIVFIX = 169,
194 G_SDIVFIXSAT = 170,
195 G_UDIVFIXSAT = 171,
196 G_FADD = 172,
197 G_FSUB = 173,
198 G_FMUL = 174,
199 G_FMA = 175,
200 G_FMAD = 176,
201 G_FDIV = 177,
202 G_FREM = 178,
203 G_FPOW = 179,
204 G_FPOWI = 180,
205 G_FEXP = 181,
206 G_FEXP2 = 182,
207 G_FEXP10 = 183,
208 G_FLOG = 184,
209 G_FLOG2 = 185,
210 G_FLOG10 = 186,
211 G_FLDEXP = 187,
212 G_FFREXP = 188,
213 G_FNEG = 189,
214 G_FPEXT = 190,
215 G_FPTRUNC = 191,
216 G_FPTOSI = 192,
217 G_FPTOUI = 193,
218 G_SITOFP = 194,
219 G_UITOFP = 195,
220 G_FABS = 196,
221 G_FCOPYSIGN = 197,
222 G_IS_FPCLASS = 198,
223 G_FCANONICALIZE = 199,
224 G_FMINNUM = 200,
225 G_FMAXNUM = 201,
226 G_FMINNUM_IEEE = 202,
227 G_FMAXNUM_IEEE = 203,
228 G_FMINIMUM = 204,
229 G_FMAXIMUM = 205,
230 G_GET_FPENV = 206,
231 G_SET_FPENV = 207,
232 G_RESET_FPENV = 208,
233 G_GET_FPMODE = 209,
234 G_SET_FPMODE = 210,
235 G_RESET_FPMODE = 211,
236 G_PTR_ADD = 212,
237 G_PTRMASK = 213,
238 G_SMIN = 214,
239 G_SMAX = 215,
240 G_UMIN = 216,
241 G_UMAX = 217,
242 G_ABS = 218,
243 G_LROUND = 219,
244 G_LLROUND = 220,
245 G_BR = 221,
246 G_BRJT = 222,
247 G_VSCALE = 223,
248 G_INSERT_SUBVECTOR = 224,
249 G_EXTRACT_SUBVECTOR = 225,
250 G_INSERT_VECTOR_ELT = 226,
251 G_EXTRACT_VECTOR_ELT = 227,
252 G_SHUFFLE_VECTOR = 228,
253 G_SPLAT_VECTOR = 229,
254 G_VECTOR_COMPRESS = 230,
255 G_CTTZ = 231,
256 G_CTTZ_ZERO_UNDEF = 232,
257 G_CTLZ = 233,
258 G_CTLZ_ZERO_UNDEF = 234,
259 G_CTPOP = 235,
260 G_BSWAP = 236,
261 G_BITREVERSE = 237,
262 G_FCEIL = 238,
263 G_FCOS = 239,
264 G_FSIN = 240,
265 G_FTAN = 241,
266 G_FACOS = 242,
267 G_FASIN = 243,
268 G_FATAN = 244,
269 G_FCOSH = 245,
270 G_FSINH = 246,
271 G_FTANH = 247,
272 G_FSQRT = 248,
273 G_FFLOOR = 249,
274 G_FRINT = 250,
275 G_FNEARBYINT = 251,
276 G_ADDRSPACE_CAST = 252,
277 G_BLOCK_ADDR = 253,
278 G_JUMP_TABLE = 254,
279 G_DYN_STACKALLOC = 255,
280 G_STACKSAVE = 256,
281 G_STACKRESTORE = 257,
282 G_STRICT_FADD = 258,
283 G_STRICT_FSUB = 259,
284 G_STRICT_FMUL = 260,
285 G_STRICT_FDIV = 261,
286 G_STRICT_FREM = 262,
287 G_STRICT_FMA = 263,
288 G_STRICT_FSQRT = 264,
289 G_STRICT_FLDEXP = 265,
290 G_READ_REGISTER = 266,
291 G_WRITE_REGISTER = 267,
292 G_MEMCPY = 268,
293 G_MEMCPY_INLINE = 269,
294 G_MEMMOVE = 270,
295 G_MEMSET = 271,
296 G_BZERO = 272,
297 G_TRAP = 273,
298 G_DEBUGTRAP = 274,
299 G_UBSANTRAP = 275,
300 G_VECREDUCE_SEQ_FADD = 276,
301 G_VECREDUCE_SEQ_FMUL = 277,
302 G_VECREDUCE_FADD = 278,
303 G_VECREDUCE_FMUL = 279,
304 G_VECREDUCE_FMAX = 280,
305 G_VECREDUCE_FMIN = 281,
306 G_VECREDUCE_FMAXIMUM = 282,
307 G_VECREDUCE_FMINIMUM = 283,
308 G_VECREDUCE_ADD = 284,
309 G_VECREDUCE_MUL = 285,
310 G_VECREDUCE_AND = 286,
311 G_VECREDUCE_OR = 287,
312 G_VECREDUCE_XOR = 288,
313 G_VECREDUCE_SMAX = 289,
314 G_VECREDUCE_SMIN = 290,
315 G_VECREDUCE_UMAX = 291,
316 G_VECREDUCE_UMIN = 292,
317 G_SBFX = 293,
318 G_UBFX = 294,
319 ADJCALLSTACKDOWN = 295,
320 ADJCALLSTACKUP = 296,
321 BuildPairF64Pseudo = 297,
322 G_FCLASS = 298,
323 G_READ_VLENB = 299,
324 G_SPLAT_VECTOR_SPLIT_I64_VL = 300,
325 G_VMCLR_VL = 301,
326 G_VMSET_VL = 302,
327 HWASAN_CHECK_MEMACCESS_SHORTGRANULES = 303,
328 KCFI_CHECK = 304,
329 PseudoAddTPRel = 305,
330 PseudoAtomicLoadNand32 = 306,
331 PseudoAtomicLoadNand64 = 307,
332 PseudoBR = 308,
333 PseudoBRIND = 309,
334 PseudoBRINDNonX7 = 310,
335 PseudoBRINDX7 = 311,
336 PseudoCALL = 312,
337 PseudoCALLIndirect = 313,
338 PseudoCALLIndirectNonX7 = 314,
339 PseudoCALLReg = 315,
340 PseudoCCADD = 316,
341 PseudoCCADDI = 317,
342 PseudoCCADDIW = 318,
343 PseudoCCADDW = 319,
344 PseudoCCAND = 320,
345 PseudoCCANDI = 321,
346 PseudoCCANDN = 322,
347 PseudoCCMOVGPR = 323,
348 PseudoCCMOVGPRNoX0 = 324,
349 PseudoCCOR = 325,
350 PseudoCCORI = 326,
351 PseudoCCORN = 327,
352 PseudoCCSLL = 328,
353 PseudoCCSLLI = 329,
354 PseudoCCSLLIW = 330,
355 PseudoCCSLLW = 331,
356 PseudoCCSRA = 332,
357 PseudoCCSRAI = 333,
358 PseudoCCSRAIW = 334,
359 PseudoCCSRAW = 335,
360 PseudoCCSRL = 336,
361 PseudoCCSRLI = 337,
362 PseudoCCSRLIW = 338,
363 PseudoCCSRLW = 339,
364 PseudoCCSUB = 340,
365 PseudoCCSUBW = 341,
366 PseudoCCXNOR = 342,
367 PseudoCCXOR = 343,
368 PseudoCCXORI = 344,
369 PseudoCmpXchg32 = 345,
370 PseudoCmpXchg64 = 346,
371 PseudoFLD = 347,
372 PseudoFLH = 348,
373 PseudoFLW = 349,
374 PseudoFROUND_D = 350,
375 PseudoFROUND_D_IN32X = 351,
376 PseudoFROUND_D_INX = 352,
377 PseudoFROUND_H = 353,
378 PseudoFROUND_H_INX = 354,
379 PseudoFROUND_S = 355,
380 PseudoFROUND_S_INX = 356,
381 PseudoFSD = 357,
382 PseudoFSH = 358,
383 PseudoFSW = 359,
384 PseudoJump = 360,
385 PseudoLA = 361,
386 PseudoLAImm = 362,
387 PseudoLA_TLSDESC = 363,
388 PseudoLA_TLS_GD = 364,
389 PseudoLA_TLS_IE = 365,
390 PseudoLB = 366,
391 PseudoLBU = 367,
392 PseudoLD = 368,
393 PseudoLGA = 369,
394 PseudoLH = 370,
395 PseudoLHU = 371,
396 PseudoLI = 372,
397 PseudoLLA = 373,
398 PseudoLLAImm = 374,
399 PseudoLW = 375,
400 PseudoLWU = 376,
401 PseudoLongBEQ = 377,
402 PseudoLongBGE = 378,
403 PseudoLongBGEU = 379,
404 PseudoLongBLT = 380,
405 PseudoLongBLTU = 381,
406 PseudoLongBNE = 382,
407 PseudoMaskedAtomicLoadAdd32 = 383,
408 PseudoMaskedAtomicLoadMax32 = 384,
409 PseudoMaskedAtomicLoadMin32 = 385,
410 PseudoMaskedAtomicLoadNand32 = 386,
411 PseudoMaskedAtomicLoadSub32 = 387,
412 PseudoMaskedAtomicLoadUMax32 = 388,
413 PseudoMaskedAtomicLoadUMin32 = 389,
414 PseudoMaskedAtomicSwap32 = 390,
415 PseudoMaskedCmpXchg32 = 391,
416 PseudoMovAddr = 392,
417 PseudoMovImm = 393,
418 PseudoQuietFLE_D = 394,
419 PseudoQuietFLE_D_IN32X = 395,
420 PseudoQuietFLE_D_INX = 396,
421 PseudoQuietFLE_H = 397,
422 PseudoQuietFLE_H_INX = 398,
423 PseudoQuietFLE_S = 399,
424 PseudoQuietFLE_S_INX = 400,
425 PseudoQuietFLT_D = 401,
426 PseudoQuietFLT_D_IN32X = 402,
427 PseudoQuietFLT_D_INX = 403,
428 PseudoQuietFLT_H = 404,
429 PseudoQuietFLT_H_INX = 405,
430 PseudoQuietFLT_S = 406,
431 PseudoQuietFLT_S_INX = 407,
432 PseudoRET = 408,
433 PseudoRV32ZdinxLD = 409,
434 PseudoRV32ZdinxSD = 410,
435 PseudoRVVInitUndefM1 = 411,
436 PseudoRVVInitUndefM2 = 412,
437 PseudoRVVInitUndefM4 = 413,
438 PseudoRVVInitUndefM8 = 414,
439 PseudoReadVL = 415,
440 PseudoReadVLENB = 416,
441 PseudoSB = 417,
442 PseudoSD = 418,
443 PseudoSEXT_B = 419,
444 PseudoSEXT_H = 420,
445 PseudoSH = 421,
446 PseudoSW = 422,
447 PseudoTAIL = 423,
448 PseudoTAILIndirect = 424,
449 PseudoTAILIndirectNonX7 = 425,
450 PseudoTHVdotVMAQASU_VV_M1 = 426,
451 PseudoTHVdotVMAQASU_VV_M1_MASK = 427,
452 PseudoTHVdotVMAQASU_VV_M2 = 428,
453 PseudoTHVdotVMAQASU_VV_M2_MASK = 429,
454 PseudoTHVdotVMAQASU_VV_M4 = 430,
455 PseudoTHVdotVMAQASU_VV_M4_MASK = 431,
456 PseudoTHVdotVMAQASU_VV_M8 = 432,
457 PseudoTHVdotVMAQASU_VV_M8_MASK = 433,
458 PseudoTHVdotVMAQASU_VV_MF2 = 434,
459 PseudoTHVdotVMAQASU_VV_MF2_MASK = 435,
460 PseudoTHVdotVMAQASU_VX_M1 = 436,
461 PseudoTHVdotVMAQASU_VX_M1_MASK = 437,
462 PseudoTHVdotVMAQASU_VX_M2 = 438,
463 PseudoTHVdotVMAQASU_VX_M2_MASK = 439,
464 PseudoTHVdotVMAQASU_VX_M4 = 440,
465 PseudoTHVdotVMAQASU_VX_M4_MASK = 441,
466 PseudoTHVdotVMAQASU_VX_M8 = 442,
467 PseudoTHVdotVMAQASU_VX_M8_MASK = 443,
468 PseudoTHVdotVMAQASU_VX_MF2 = 444,
469 PseudoTHVdotVMAQASU_VX_MF2_MASK = 445,
470 PseudoTHVdotVMAQAUS_VX_M1 = 446,
471 PseudoTHVdotVMAQAUS_VX_M1_MASK = 447,
472 PseudoTHVdotVMAQAUS_VX_M2 = 448,
473 PseudoTHVdotVMAQAUS_VX_M2_MASK = 449,
474 PseudoTHVdotVMAQAUS_VX_M4 = 450,
475 PseudoTHVdotVMAQAUS_VX_M4_MASK = 451,
476 PseudoTHVdotVMAQAUS_VX_M8 = 452,
477 PseudoTHVdotVMAQAUS_VX_M8_MASK = 453,
478 PseudoTHVdotVMAQAUS_VX_MF2 = 454,
479 PseudoTHVdotVMAQAUS_VX_MF2_MASK = 455,
480 PseudoTHVdotVMAQAU_VV_M1 = 456,
481 PseudoTHVdotVMAQAU_VV_M1_MASK = 457,
482 PseudoTHVdotVMAQAU_VV_M2 = 458,
483 PseudoTHVdotVMAQAU_VV_M2_MASK = 459,
484 PseudoTHVdotVMAQAU_VV_M4 = 460,
485 PseudoTHVdotVMAQAU_VV_M4_MASK = 461,
486 PseudoTHVdotVMAQAU_VV_M8 = 462,
487 PseudoTHVdotVMAQAU_VV_M8_MASK = 463,
488 PseudoTHVdotVMAQAU_VV_MF2 = 464,
489 PseudoTHVdotVMAQAU_VV_MF2_MASK = 465,
490 PseudoTHVdotVMAQAU_VX_M1 = 466,
491 PseudoTHVdotVMAQAU_VX_M1_MASK = 467,
492 PseudoTHVdotVMAQAU_VX_M2 = 468,
493 PseudoTHVdotVMAQAU_VX_M2_MASK = 469,
494 PseudoTHVdotVMAQAU_VX_M4 = 470,
495 PseudoTHVdotVMAQAU_VX_M4_MASK = 471,
496 PseudoTHVdotVMAQAU_VX_M8 = 472,
497 PseudoTHVdotVMAQAU_VX_M8_MASK = 473,
498 PseudoTHVdotVMAQAU_VX_MF2 = 474,
499 PseudoTHVdotVMAQAU_VX_MF2_MASK = 475,
500 PseudoTHVdotVMAQA_VV_M1 = 476,
501 PseudoTHVdotVMAQA_VV_M1_MASK = 477,
502 PseudoTHVdotVMAQA_VV_M2 = 478,
503 PseudoTHVdotVMAQA_VV_M2_MASK = 479,
504 PseudoTHVdotVMAQA_VV_M4 = 480,
505 PseudoTHVdotVMAQA_VV_M4_MASK = 481,
506 PseudoTHVdotVMAQA_VV_M8 = 482,
507 PseudoTHVdotVMAQA_VV_M8_MASK = 483,
508 PseudoTHVdotVMAQA_VV_MF2 = 484,
509 PseudoTHVdotVMAQA_VV_MF2_MASK = 485,
510 PseudoTHVdotVMAQA_VX_M1 = 486,
511 PseudoTHVdotVMAQA_VX_M1_MASK = 487,
512 PseudoTHVdotVMAQA_VX_M2 = 488,
513 PseudoTHVdotVMAQA_VX_M2_MASK = 489,
514 PseudoTHVdotVMAQA_VX_M4 = 490,
515 PseudoTHVdotVMAQA_VX_M4_MASK = 491,
516 PseudoTHVdotVMAQA_VX_M8 = 492,
517 PseudoTHVdotVMAQA_VX_M8_MASK = 493,
518 PseudoTHVdotVMAQA_VX_MF2 = 494,
519 PseudoTHVdotVMAQA_VX_MF2_MASK = 495,
520 PseudoTLSDESCCall = 496,
521 PseudoVAADDU_VV_M1 = 497,
522 PseudoVAADDU_VV_M1_MASK = 498,
523 PseudoVAADDU_VV_M2 = 499,
524 PseudoVAADDU_VV_M2_MASK = 500,
525 PseudoVAADDU_VV_M4 = 501,
526 PseudoVAADDU_VV_M4_MASK = 502,
527 PseudoVAADDU_VV_M8 = 503,
528 PseudoVAADDU_VV_M8_MASK = 504,
529 PseudoVAADDU_VV_MF2 = 505,
530 PseudoVAADDU_VV_MF2_MASK = 506,
531 PseudoVAADDU_VV_MF4 = 507,
532 PseudoVAADDU_VV_MF4_MASK = 508,
533 PseudoVAADDU_VV_MF8 = 509,
534 PseudoVAADDU_VV_MF8_MASK = 510,
535 PseudoVAADDU_VX_M1 = 511,
536 PseudoVAADDU_VX_M1_MASK = 512,
537 PseudoVAADDU_VX_M2 = 513,
538 PseudoVAADDU_VX_M2_MASK = 514,
539 PseudoVAADDU_VX_M4 = 515,
540 PseudoVAADDU_VX_M4_MASK = 516,
541 PseudoVAADDU_VX_M8 = 517,
542 PseudoVAADDU_VX_M8_MASK = 518,
543 PseudoVAADDU_VX_MF2 = 519,
544 PseudoVAADDU_VX_MF2_MASK = 520,
545 PseudoVAADDU_VX_MF4 = 521,
546 PseudoVAADDU_VX_MF4_MASK = 522,
547 PseudoVAADDU_VX_MF8 = 523,
548 PseudoVAADDU_VX_MF8_MASK = 524,
549 PseudoVAADD_VV_M1 = 525,
550 PseudoVAADD_VV_M1_MASK = 526,
551 PseudoVAADD_VV_M2 = 527,
552 PseudoVAADD_VV_M2_MASK = 528,
553 PseudoVAADD_VV_M4 = 529,
554 PseudoVAADD_VV_M4_MASK = 530,
555 PseudoVAADD_VV_M8 = 531,
556 PseudoVAADD_VV_M8_MASK = 532,
557 PseudoVAADD_VV_MF2 = 533,
558 PseudoVAADD_VV_MF2_MASK = 534,
559 PseudoVAADD_VV_MF4 = 535,
560 PseudoVAADD_VV_MF4_MASK = 536,
561 PseudoVAADD_VV_MF8 = 537,
562 PseudoVAADD_VV_MF8_MASK = 538,
563 PseudoVAADD_VX_M1 = 539,
564 PseudoVAADD_VX_M1_MASK = 540,
565 PseudoVAADD_VX_M2 = 541,
566 PseudoVAADD_VX_M2_MASK = 542,
567 PseudoVAADD_VX_M4 = 543,
568 PseudoVAADD_VX_M4_MASK = 544,
569 PseudoVAADD_VX_M8 = 545,
570 PseudoVAADD_VX_M8_MASK = 546,
571 PseudoVAADD_VX_MF2 = 547,
572 PseudoVAADD_VX_MF2_MASK = 548,
573 PseudoVAADD_VX_MF4 = 549,
574 PseudoVAADD_VX_MF4_MASK = 550,
575 PseudoVAADD_VX_MF8 = 551,
576 PseudoVAADD_VX_MF8_MASK = 552,
577 PseudoVADC_VIM_M1 = 553,
578 PseudoVADC_VIM_M2 = 554,
579 PseudoVADC_VIM_M4 = 555,
580 PseudoVADC_VIM_M8 = 556,
581 PseudoVADC_VIM_MF2 = 557,
582 PseudoVADC_VIM_MF4 = 558,
583 PseudoVADC_VIM_MF8 = 559,
584 PseudoVADC_VVM_M1 = 560,
585 PseudoVADC_VVM_M2 = 561,
586 PseudoVADC_VVM_M4 = 562,
587 PseudoVADC_VVM_M8 = 563,
588 PseudoVADC_VVM_MF2 = 564,
589 PseudoVADC_VVM_MF4 = 565,
590 PseudoVADC_VVM_MF8 = 566,
591 PseudoVADC_VXM_M1 = 567,
592 PseudoVADC_VXM_M2 = 568,
593 PseudoVADC_VXM_M4 = 569,
594 PseudoVADC_VXM_M8 = 570,
595 PseudoVADC_VXM_MF2 = 571,
596 PseudoVADC_VXM_MF4 = 572,
597 PseudoVADC_VXM_MF8 = 573,
598 PseudoVADD_VI_M1 = 574,
599 PseudoVADD_VI_M1_MASK = 575,
600 PseudoVADD_VI_M2 = 576,
601 PseudoVADD_VI_M2_MASK = 577,
602 PseudoVADD_VI_M4 = 578,
603 PseudoVADD_VI_M4_MASK = 579,
604 PseudoVADD_VI_M8 = 580,
605 PseudoVADD_VI_M8_MASK = 581,
606 PseudoVADD_VI_MF2 = 582,
607 PseudoVADD_VI_MF2_MASK = 583,
608 PseudoVADD_VI_MF4 = 584,
609 PseudoVADD_VI_MF4_MASK = 585,
610 PseudoVADD_VI_MF8 = 586,
611 PseudoVADD_VI_MF8_MASK = 587,
612 PseudoVADD_VV_M1 = 588,
613 PseudoVADD_VV_M1_MASK = 589,
614 PseudoVADD_VV_M2 = 590,
615 PseudoVADD_VV_M2_MASK = 591,
616 PseudoVADD_VV_M4 = 592,
617 PseudoVADD_VV_M4_MASK = 593,
618 PseudoVADD_VV_M8 = 594,
619 PseudoVADD_VV_M8_MASK = 595,
620 PseudoVADD_VV_MF2 = 596,
621 PseudoVADD_VV_MF2_MASK = 597,
622 PseudoVADD_VV_MF4 = 598,
623 PseudoVADD_VV_MF4_MASK = 599,
624 PseudoVADD_VV_MF8 = 600,
625 PseudoVADD_VV_MF8_MASK = 601,
626 PseudoVADD_VX_M1 = 602,
627 PseudoVADD_VX_M1_MASK = 603,
628 PseudoVADD_VX_M2 = 604,
629 PseudoVADD_VX_M2_MASK = 605,
630 PseudoVADD_VX_M4 = 606,
631 PseudoVADD_VX_M4_MASK = 607,
632 PseudoVADD_VX_M8 = 608,
633 PseudoVADD_VX_M8_MASK = 609,
634 PseudoVADD_VX_MF2 = 610,
635 PseudoVADD_VX_MF2_MASK = 611,
636 PseudoVADD_VX_MF4 = 612,
637 PseudoVADD_VX_MF4_MASK = 613,
638 PseudoVADD_VX_MF8 = 614,
639 PseudoVADD_VX_MF8_MASK = 615,
640 PseudoVAESDF_VS_M1_M1 = 616,
641 PseudoVAESDF_VS_M1_MF2 = 617,
642 PseudoVAESDF_VS_M1_MF4 = 618,
643 PseudoVAESDF_VS_M1_MF8 = 619,
644 PseudoVAESDF_VS_M2_M1 = 620,
645 PseudoVAESDF_VS_M2_M2 = 621,
646 PseudoVAESDF_VS_M2_MF2 = 622,
647 PseudoVAESDF_VS_M2_MF4 = 623,
648 PseudoVAESDF_VS_M2_MF8 = 624,
649 PseudoVAESDF_VS_M4_M1 = 625,
650 PseudoVAESDF_VS_M4_M2 = 626,
651 PseudoVAESDF_VS_M4_M4 = 627,
652 PseudoVAESDF_VS_M4_MF2 = 628,
653 PseudoVAESDF_VS_M4_MF4 = 629,
654 PseudoVAESDF_VS_M4_MF8 = 630,
655 PseudoVAESDF_VS_M8_M1 = 631,
656 PseudoVAESDF_VS_M8_M2 = 632,
657 PseudoVAESDF_VS_M8_M4 = 633,
658 PseudoVAESDF_VS_M8_MF2 = 634,
659 PseudoVAESDF_VS_M8_MF4 = 635,
660 PseudoVAESDF_VS_M8_MF8 = 636,
661 PseudoVAESDF_VS_MF2_MF2 = 637,
662 PseudoVAESDF_VS_MF2_MF4 = 638,
663 PseudoVAESDF_VS_MF2_MF8 = 639,
664 PseudoVAESDF_VV_M1 = 640,
665 PseudoVAESDF_VV_M2 = 641,
666 PseudoVAESDF_VV_M4 = 642,
667 PseudoVAESDF_VV_M8 = 643,
668 PseudoVAESDF_VV_MF2 = 644,
669 PseudoVAESDM_VS_M1_M1 = 645,
670 PseudoVAESDM_VS_M1_MF2 = 646,
671 PseudoVAESDM_VS_M1_MF4 = 647,
672 PseudoVAESDM_VS_M1_MF8 = 648,
673 PseudoVAESDM_VS_M2_M1 = 649,
674 PseudoVAESDM_VS_M2_M2 = 650,
675 PseudoVAESDM_VS_M2_MF2 = 651,
676 PseudoVAESDM_VS_M2_MF4 = 652,
677 PseudoVAESDM_VS_M2_MF8 = 653,
678 PseudoVAESDM_VS_M4_M1 = 654,
679 PseudoVAESDM_VS_M4_M2 = 655,
680 PseudoVAESDM_VS_M4_M4 = 656,
681 PseudoVAESDM_VS_M4_MF2 = 657,
682 PseudoVAESDM_VS_M4_MF4 = 658,
683 PseudoVAESDM_VS_M4_MF8 = 659,
684 PseudoVAESDM_VS_M8_M1 = 660,
685 PseudoVAESDM_VS_M8_M2 = 661,
686 PseudoVAESDM_VS_M8_M4 = 662,
687 PseudoVAESDM_VS_M8_MF2 = 663,
688 PseudoVAESDM_VS_M8_MF4 = 664,
689 PseudoVAESDM_VS_M8_MF8 = 665,
690 PseudoVAESDM_VS_MF2_MF2 = 666,
691 PseudoVAESDM_VS_MF2_MF4 = 667,
692 PseudoVAESDM_VS_MF2_MF8 = 668,
693 PseudoVAESDM_VV_M1 = 669,
694 PseudoVAESDM_VV_M2 = 670,
695 PseudoVAESDM_VV_M4 = 671,
696 PseudoVAESDM_VV_M8 = 672,
697 PseudoVAESDM_VV_MF2 = 673,
698 PseudoVAESEF_VS_M1_M1 = 674,
699 PseudoVAESEF_VS_M1_MF2 = 675,
700 PseudoVAESEF_VS_M1_MF4 = 676,
701 PseudoVAESEF_VS_M1_MF8 = 677,
702 PseudoVAESEF_VS_M2_M1 = 678,
703 PseudoVAESEF_VS_M2_M2 = 679,
704 PseudoVAESEF_VS_M2_MF2 = 680,
705 PseudoVAESEF_VS_M2_MF4 = 681,
706 PseudoVAESEF_VS_M2_MF8 = 682,
707 PseudoVAESEF_VS_M4_M1 = 683,
708 PseudoVAESEF_VS_M4_M2 = 684,
709 PseudoVAESEF_VS_M4_M4 = 685,
710 PseudoVAESEF_VS_M4_MF2 = 686,
711 PseudoVAESEF_VS_M4_MF4 = 687,
712 PseudoVAESEF_VS_M4_MF8 = 688,
713 PseudoVAESEF_VS_M8_M1 = 689,
714 PseudoVAESEF_VS_M8_M2 = 690,
715 PseudoVAESEF_VS_M8_M4 = 691,
716 PseudoVAESEF_VS_M8_MF2 = 692,
717 PseudoVAESEF_VS_M8_MF4 = 693,
718 PseudoVAESEF_VS_M8_MF8 = 694,
719 PseudoVAESEF_VS_MF2_MF2 = 695,
720 PseudoVAESEF_VS_MF2_MF4 = 696,
721 PseudoVAESEF_VS_MF2_MF8 = 697,
722 PseudoVAESEF_VV_M1 = 698,
723 PseudoVAESEF_VV_M2 = 699,
724 PseudoVAESEF_VV_M4 = 700,
725 PseudoVAESEF_VV_M8 = 701,
726 PseudoVAESEF_VV_MF2 = 702,
727 PseudoVAESEM_VS_M1_M1 = 703,
728 PseudoVAESEM_VS_M1_MF2 = 704,
729 PseudoVAESEM_VS_M1_MF4 = 705,
730 PseudoVAESEM_VS_M1_MF8 = 706,
731 PseudoVAESEM_VS_M2_M1 = 707,
732 PseudoVAESEM_VS_M2_M2 = 708,
733 PseudoVAESEM_VS_M2_MF2 = 709,
734 PseudoVAESEM_VS_M2_MF4 = 710,
735 PseudoVAESEM_VS_M2_MF8 = 711,
736 PseudoVAESEM_VS_M4_M1 = 712,
737 PseudoVAESEM_VS_M4_M2 = 713,
738 PseudoVAESEM_VS_M4_M4 = 714,
739 PseudoVAESEM_VS_M4_MF2 = 715,
740 PseudoVAESEM_VS_M4_MF4 = 716,
741 PseudoVAESEM_VS_M4_MF8 = 717,
742 PseudoVAESEM_VS_M8_M1 = 718,
743 PseudoVAESEM_VS_M8_M2 = 719,
744 PseudoVAESEM_VS_M8_M4 = 720,
745 PseudoVAESEM_VS_M8_MF2 = 721,
746 PseudoVAESEM_VS_M8_MF4 = 722,
747 PseudoVAESEM_VS_M8_MF8 = 723,
748 PseudoVAESEM_VS_MF2_MF2 = 724,
749 PseudoVAESEM_VS_MF2_MF4 = 725,
750 PseudoVAESEM_VS_MF2_MF8 = 726,
751 PseudoVAESEM_VV_M1 = 727,
752 PseudoVAESEM_VV_M2 = 728,
753 PseudoVAESEM_VV_M4 = 729,
754 PseudoVAESEM_VV_M8 = 730,
755 PseudoVAESEM_VV_MF2 = 731,
756 PseudoVAESKF1_VI_M1 = 732,
757 PseudoVAESKF1_VI_M2 = 733,
758 PseudoVAESKF1_VI_M4 = 734,
759 PseudoVAESKF1_VI_M8 = 735,
760 PseudoVAESKF1_VI_MF2 = 736,
761 PseudoVAESKF2_VI_M1 = 737,
762 PseudoVAESKF2_VI_M2 = 738,
763 PseudoVAESKF2_VI_M4 = 739,
764 PseudoVAESKF2_VI_M8 = 740,
765 PseudoVAESKF2_VI_MF2 = 741,
766 PseudoVAESZ_VS_M1_M1 = 742,
767 PseudoVAESZ_VS_M1_MF2 = 743,
768 PseudoVAESZ_VS_M1_MF4 = 744,
769 PseudoVAESZ_VS_M1_MF8 = 745,
770 PseudoVAESZ_VS_M2_M1 = 746,
771 PseudoVAESZ_VS_M2_M2 = 747,
772 PseudoVAESZ_VS_M2_MF2 = 748,
773 PseudoVAESZ_VS_M2_MF4 = 749,
774 PseudoVAESZ_VS_M2_MF8 = 750,
775 PseudoVAESZ_VS_M4_M1 = 751,
776 PseudoVAESZ_VS_M4_M2 = 752,
777 PseudoVAESZ_VS_M4_M4 = 753,
778 PseudoVAESZ_VS_M4_MF2 = 754,
779 PseudoVAESZ_VS_M4_MF4 = 755,
780 PseudoVAESZ_VS_M4_MF8 = 756,
781 PseudoVAESZ_VS_M8_M1 = 757,
782 PseudoVAESZ_VS_M8_M2 = 758,
783 PseudoVAESZ_VS_M8_M4 = 759,
784 PseudoVAESZ_VS_M8_MF2 = 760,
785 PseudoVAESZ_VS_M8_MF4 = 761,
786 PseudoVAESZ_VS_M8_MF8 = 762,
787 PseudoVAESZ_VS_MF2_MF2 = 763,
788 PseudoVAESZ_VS_MF2_MF4 = 764,
789 PseudoVAESZ_VS_MF2_MF8 = 765,
790 PseudoVANDN_VV_M1 = 766,
791 PseudoVANDN_VV_M1_MASK = 767,
792 PseudoVANDN_VV_M2 = 768,
793 PseudoVANDN_VV_M2_MASK = 769,
794 PseudoVANDN_VV_M4 = 770,
795 PseudoVANDN_VV_M4_MASK = 771,
796 PseudoVANDN_VV_M8 = 772,
797 PseudoVANDN_VV_M8_MASK = 773,
798 PseudoVANDN_VV_MF2 = 774,
799 PseudoVANDN_VV_MF2_MASK = 775,
800 PseudoVANDN_VV_MF4 = 776,
801 PseudoVANDN_VV_MF4_MASK = 777,
802 PseudoVANDN_VV_MF8 = 778,
803 PseudoVANDN_VV_MF8_MASK = 779,
804 PseudoVANDN_VX_M1 = 780,
805 PseudoVANDN_VX_M1_MASK = 781,
806 PseudoVANDN_VX_M2 = 782,
807 PseudoVANDN_VX_M2_MASK = 783,
808 PseudoVANDN_VX_M4 = 784,
809 PseudoVANDN_VX_M4_MASK = 785,
810 PseudoVANDN_VX_M8 = 786,
811 PseudoVANDN_VX_M8_MASK = 787,
812 PseudoVANDN_VX_MF2 = 788,
813 PseudoVANDN_VX_MF2_MASK = 789,
814 PseudoVANDN_VX_MF4 = 790,
815 PseudoVANDN_VX_MF4_MASK = 791,
816 PseudoVANDN_VX_MF8 = 792,
817 PseudoVANDN_VX_MF8_MASK = 793,
818 PseudoVAND_VI_M1 = 794,
819 PseudoVAND_VI_M1_MASK = 795,
820 PseudoVAND_VI_M2 = 796,
821 PseudoVAND_VI_M2_MASK = 797,
822 PseudoVAND_VI_M4 = 798,
823 PseudoVAND_VI_M4_MASK = 799,
824 PseudoVAND_VI_M8 = 800,
825 PseudoVAND_VI_M8_MASK = 801,
826 PseudoVAND_VI_MF2 = 802,
827 PseudoVAND_VI_MF2_MASK = 803,
828 PseudoVAND_VI_MF4 = 804,
829 PseudoVAND_VI_MF4_MASK = 805,
830 PseudoVAND_VI_MF8 = 806,
831 PseudoVAND_VI_MF8_MASK = 807,
832 PseudoVAND_VV_M1 = 808,
833 PseudoVAND_VV_M1_MASK = 809,
834 PseudoVAND_VV_M2 = 810,
835 PseudoVAND_VV_M2_MASK = 811,
836 PseudoVAND_VV_M4 = 812,
837 PseudoVAND_VV_M4_MASK = 813,
838 PseudoVAND_VV_M8 = 814,
839 PseudoVAND_VV_M8_MASK = 815,
840 PseudoVAND_VV_MF2 = 816,
841 PseudoVAND_VV_MF2_MASK = 817,
842 PseudoVAND_VV_MF4 = 818,
843 PseudoVAND_VV_MF4_MASK = 819,
844 PseudoVAND_VV_MF8 = 820,
845 PseudoVAND_VV_MF8_MASK = 821,
846 PseudoVAND_VX_M1 = 822,
847 PseudoVAND_VX_M1_MASK = 823,
848 PseudoVAND_VX_M2 = 824,
849 PseudoVAND_VX_M2_MASK = 825,
850 PseudoVAND_VX_M4 = 826,
851 PseudoVAND_VX_M4_MASK = 827,
852 PseudoVAND_VX_M8 = 828,
853 PseudoVAND_VX_M8_MASK = 829,
854 PseudoVAND_VX_MF2 = 830,
855 PseudoVAND_VX_MF2_MASK = 831,
856 PseudoVAND_VX_MF4 = 832,
857 PseudoVAND_VX_MF4_MASK = 833,
858 PseudoVAND_VX_MF8 = 834,
859 PseudoVAND_VX_MF8_MASK = 835,
860 PseudoVASUBU_VV_M1 = 836,
861 PseudoVASUBU_VV_M1_MASK = 837,
862 PseudoVASUBU_VV_M2 = 838,
863 PseudoVASUBU_VV_M2_MASK = 839,
864 PseudoVASUBU_VV_M4 = 840,
865 PseudoVASUBU_VV_M4_MASK = 841,
866 PseudoVASUBU_VV_M8 = 842,
867 PseudoVASUBU_VV_M8_MASK = 843,
868 PseudoVASUBU_VV_MF2 = 844,
869 PseudoVASUBU_VV_MF2_MASK = 845,
870 PseudoVASUBU_VV_MF4 = 846,
871 PseudoVASUBU_VV_MF4_MASK = 847,
872 PseudoVASUBU_VV_MF8 = 848,
873 PseudoVASUBU_VV_MF8_MASK = 849,
874 PseudoVASUBU_VX_M1 = 850,
875 PseudoVASUBU_VX_M1_MASK = 851,
876 PseudoVASUBU_VX_M2 = 852,
877 PseudoVASUBU_VX_M2_MASK = 853,
878 PseudoVASUBU_VX_M4 = 854,
879 PseudoVASUBU_VX_M4_MASK = 855,
880 PseudoVASUBU_VX_M8 = 856,
881 PseudoVASUBU_VX_M8_MASK = 857,
882 PseudoVASUBU_VX_MF2 = 858,
883 PseudoVASUBU_VX_MF2_MASK = 859,
884 PseudoVASUBU_VX_MF4 = 860,
885 PseudoVASUBU_VX_MF4_MASK = 861,
886 PseudoVASUBU_VX_MF8 = 862,
887 PseudoVASUBU_VX_MF8_MASK = 863,
888 PseudoVASUB_VV_M1 = 864,
889 PseudoVASUB_VV_M1_MASK = 865,
890 PseudoVASUB_VV_M2 = 866,
891 PseudoVASUB_VV_M2_MASK = 867,
892 PseudoVASUB_VV_M4 = 868,
893 PseudoVASUB_VV_M4_MASK = 869,
894 PseudoVASUB_VV_M8 = 870,
895 PseudoVASUB_VV_M8_MASK = 871,
896 PseudoVASUB_VV_MF2 = 872,
897 PseudoVASUB_VV_MF2_MASK = 873,
898 PseudoVASUB_VV_MF4 = 874,
899 PseudoVASUB_VV_MF4_MASK = 875,
900 PseudoVASUB_VV_MF8 = 876,
901 PseudoVASUB_VV_MF8_MASK = 877,
902 PseudoVASUB_VX_M1 = 878,
903 PseudoVASUB_VX_M1_MASK = 879,
904 PseudoVASUB_VX_M2 = 880,
905 PseudoVASUB_VX_M2_MASK = 881,
906 PseudoVASUB_VX_M4 = 882,
907 PseudoVASUB_VX_M4_MASK = 883,
908 PseudoVASUB_VX_M8 = 884,
909 PseudoVASUB_VX_M8_MASK = 885,
910 PseudoVASUB_VX_MF2 = 886,
911 PseudoVASUB_VX_MF2_MASK = 887,
912 PseudoVASUB_VX_MF4 = 888,
913 PseudoVASUB_VX_MF4_MASK = 889,
914 PseudoVASUB_VX_MF8 = 890,
915 PseudoVASUB_VX_MF8_MASK = 891,
916 PseudoVBREV8_V_M1 = 892,
917 PseudoVBREV8_V_M1_MASK = 893,
918 PseudoVBREV8_V_M2 = 894,
919 PseudoVBREV8_V_M2_MASK = 895,
920 PseudoVBREV8_V_M4 = 896,
921 PseudoVBREV8_V_M4_MASK = 897,
922 PseudoVBREV8_V_M8 = 898,
923 PseudoVBREV8_V_M8_MASK = 899,
924 PseudoVBREV8_V_MF2 = 900,
925 PseudoVBREV8_V_MF2_MASK = 901,
926 PseudoVBREV8_V_MF4 = 902,
927 PseudoVBREV8_V_MF4_MASK = 903,
928 PseudoVBREV8_V_MF8 = 904,
929 PseudoVBREV8_V_MF8_MASK = 905,
930 PseudoVBREV_V_M1 = 906,
931 PseudoVBREV_V_M1_MASK = 907,
932 PseudoVBREV_V_M2 = 908,
933 PseudoVBREV_V_M2_MASK = 909,
934 PseudoVBREV_V_M4 = 910,
935 PseudoVBREV_V_M4_MASK = 911,
936 PseudoVBREV_V_M8 = 912,
937 PseudoVBREV_V_M8_MASK = 913,
938 PseudoVBREV_V_MF2 = 914,
939 PseudoVBREV_V_MF2_MASK = 915,
940 PseudoVBREV_V_MF4 = 916,
941 PseudoVBREV_V_MF4_MASK = 917,
942 PseudoVBREV_V_MF8 = 918,
943 PseudoVBREV_V_MF8_MASK = 919,
944 PseudoVCLMULH_VV_M1 = 920,
945 PseudoVCLMULH_VV_M1_MASK = 921,
946 PseudoVCLMULH_VV_M2 = 922,
947 PseudoVCLMULH_VV_M2_MASK = 923,
948 PseudoVCLMULH_VV_M4 = 924,
949 PseudoVCLMULH_VV_M4_MASK = 925,
950 PseudoVCLMULH_VV_M8 = 926,
951 PseudoVCLMULH_VV_M8_MASK = 927,
952 PseudoVCLMULH_VV_MF2 = 928,
953 PseudoVCLMULH_VV_MF2_MASK = 929,
954 PseudoVCLMULH_VV_MF4 = 930,
955 PseudoVCLMULH_VV_MF4_MASK = 931,
956 PseudoVCLMULH_VV_MF8 = 932,
957 PseudoVCLMULH_VV_MF8_MASK = 933,
958 PseudoVCLMULH_VX_M1 = 934,
959 PseudoVCLMULH_VX_M1_MASK = 935,
960 PseudoVCLMULH_VX_M2 = 936,
961 PseudoVCLMULH_VX_M2_MASK = 937,
962 PseudoVCLMULH_VX_M4 = 938,
963 PseudoVCLMULH_VX_M4_MASK = 939,
964 PseudoVCLMULH_VX_M8 = 940,
965 PseudoVCLMULH_VX_M8_MASK = 941,
966 PseudoVCLMULH_VX_MF2 = 942,
967 PseudoVCLMULH_VX_MF2_MASK = 943,
968 PseudoVCLMULH_VX_MF4 = 944,
969 PseudoVCLMULH_VX_MF4_MASK = 945,
970 PseudoVCLMULH_VX_MF8 = 946,
971 PseudoVCLMULH_VX_MF8_MASK = 947,
972 PseudoVCLMUL_VV_M1 = 948,
973 PseudoVCLMUL_VV_M1_MASK = 949,
974 PseudoVCLMUL_VV_M2 = 950,
975 PseudoVCLMUL_VV_M2_MASK = 951,
976 PseudoVCLMUL_VV_M4 = 952,
977 PseudoVCLMUL_VV_M4_MASK = 953,
978 PseudoVCLMUL_VV_M8 = 954,
979 PseudoVCLMUL_VV_M8_MASK = 955,
980 PseudoVCLMUL_VV_MF2 = 956,
981 PseudoVCLMUL_VV_MF2_MASK = 957,
982 PseudoVCLMUL_VV_MF4 = 958,
983 PseudoVCLMUL_VV_MF4_MASK = 959,
984 PseudoVCLMUL_VV_MF8 = 960,
985 PseudoVCLMUL_VV_MF8_MASK = 961,
986 PseudoVCLMUL_VX_M1 = 962,
987 PseudoVCLMUL_VX_M1_MASK = 963,
988 PseudoVCLMUL_VX_M2 = 964,
989 PseudoVCLMUL_VX_M2_MASK = 965,
990 PseudoVCLMUL_VX_M4 = 966,
991 PseudoVCLMUL_VX_M4_MASK = 967,
992 PseudoVCLMUL_VX_M8 = 968,
993 PseudoVCLMUL_VX_M8_MASK = 969,
994 PseudoVCLMUL_VX_MF2 = 970,
995 PseudoVCLMUL_VX_MF2_MASK = 971,
996 PseudoVCLMUL_VX_MF4 = 972,
997 PseudoVCLMUL_VX_MF4_MASK = 973,
998 PseudoVCLMUL_VX_MF8 = 974,
999 PseudoVCLMUL_VX_MF8_MASK = 975,
1000 PseudoVCLZ_V_M1 = 976,
1001 PseudoVCLZ_V_M1_MASK = 977,
1002 PseudoVCLZ_V_M2 = 978,
1003 PseudoVCLZ_V_M2_MASK = 979,
1004 PseudoVCLZ_V_M4 = 980,
1005 PseudoVCLZ_V_M4_MASK = 981,
1006 PseudoVCLZ_V_M8 = 982,
1007 PseudoVCLZ_V_M8_MASK = 983,
1008 PseudoVCLZ_V_MF2 = 984,
1009 PseudoVCLZ_V_MF2_MASK = 985,
1010 PseudoVCLZ_V_MF4 = 986,
1011 PseudoVCLZ_V_MF4_MASK = 987,
1012 PseudoVCLZ_V_MF8 = 988,
1013 PseudoVCLZ_V_MF8_MASK = 989,
1014 PseudoVCOMPRESS_VM_M1_E16 = 990,
1015 PseudoVCOMPRESS_VM_M1_E32 = 991,
1016 PseudoVCOMPRESS_VM_M1_E64 = 992,
1017 PseudoVCOMPRESS_VM_M1_E8 = 993,
1018 PseudoVCOMPRESS_VM_M2_E16 = 994,
1019 PseudoVCOMPRESS_VM_M2_E32 = 995,
1020 PseudoVCOMPRESS_VM_M2_E64 = 996,
1021 PseudoVCOMPRESS_VM_M2_E8 = 997,
1022 PseudoVCOMPRESS_VM_M4_E16 = 998,
1023 PseudoVCOMPRESS_VM_M4_E32 = 999,
1024 PseudoVCOMPRESS_VM_M4_E64 = 1000,
1025 PseudoVCOMPRESS_VM_M4_E8 = 1001,
1026 PseudoVCOMPRESS_VM_M8_E16 = 1002,
1027 PseudoVCOMPRESS_VM_M8_E32 = 1003,
1028 PseudoVCOMPRESS_VM_M8_E64 = 1004,
1029 PseudoVCOMPRESS_VM_M8_E8 = 1005,
1030 PseudoVCOMPRESS_VM_MF2_E16 = 1006,
1031 PseudoVCOMPRESS_VM_MF2_E32 = 1007,
1032 PseudoVCOMPRESS_VM_MF2_E8 = 1008,
1033 PseudoVCOMPRESS_VM_MF4_E16 = 1009,
1034 PseudoVCOMPRESS_VM_MF4_E8 = 1010,
1035 PseudoVCOMPRESS_VM_MF8_E8 = 1011,
1036 PseudoVCPOP_M_B1 = 1012,
1037 PseudoVCPOP_M_B16 = 1013,
1038 PseudoVCPOP_M_B16_MASK = 1014,
1039 PseudoVCPOP_M_B1_MASK = 1015,
1040 PseudoVCPOP_M_B2 = 1016,
1041 PseudoVCPOP_M_B2_MASK = 1017,
1042 PseudoVCPOP_M_B32 = 1018,
1043 PseudoVCPOP_M_B32_MASK = 1019,
1044 PseudoVCPOP_M_B4 = 1020,
1045 PseudoVCPOP_M_B4_MASK = 1021,
1046 PseudoVCPOP_M_B64 = 1022,
1047 PseudoVCPOP_M_B64_MASK = 1023,
1048 PseudoVCPOP_M_B8 = 1024,
1049 PseudoVCPOP_M_B8_MASK = 1025,
1050 PseudoVCPOP_V_M1 = 1026,
1051 PseudoVCPOP_V_M1_MASK = 1027,
1052 PseudoVCPOP_V_M2 = 1028,
1053 PseudoVCPOP_V_M2_MASK = 1029,
1054 PseudoVCPOP_V_M4 = 1030,
1055 PseudoVCPOP_V_M4_MASK = 1031,
1056 PseudoVCPOP_V_M8 = 1032,
1057 PseudoVCPOP_V_M8_MASK = 1033,
1058 PseudoVCPOP_V_MF2 = 1034,
1059 PseudoVCPOP_V_MF2_MASK = 1035,
1060 PseudoVCPOP_V_MF4 = 1036,
1061 PseudoVCPOP_V_MF4_MASK = 1037,
1062 PseudoVCPOP_V_MF8 = 1038,
1063 PseudoVCPOP_V_MF8_MASK = 1039,
1064 PseudoVCTZ_V_M1 = 1040,
1065 PseudoVCTZ_V_M1_MASK = 1041,
1066 PseudoVCTZ_V_M2 = 1042,
1067 PseudoVCTZ_V_M2_MASK = 1043,
1068 PseudoVCTZ_V_M4 = 1044,
1069 PseudoVCTZ_V_M4_MASK = 1045,
1070 PseudoVCTZ_V_M8 = 1046,
1071 PseudoVCTZ_V_M8_MASK = 1047,
1072 PseudoVCTZ_V_MF2 = 1048,
1073 PseudoVCTZ_V_MF2_MASK = 1049,
1074 PseudoVCTZ_V_MF4 = 1050,
1075 PseudoVCTZ_V_MF4_MASK = 1051,
1076 PseudoVCTZ_V_MF8 = 1052,
1077 PseudoVCTZ_V_MF8_MASK = 1053,
1078 PseudoVC_FPR16VV_SE_M1 = 1054,
1079 PseudoVC_FPR16VV_SE_M2 = 1055,
1080 PseudoVC_FPR16VV_SE_M4 = 1056,
1081 PseudoVC_FPR16VV_SE_M8 = 1057,
1082 PseudoVC_FPR16VV_SE_MF2 = 1058,
1083 PseudoVC_FPR16VV_SE_MF4 = 1059,
1084 PseudoVC_FPR16VW_SE_M1 = 1060,
1085 PseudoVC_FPR16VW_SE_M2 = 1061,
1086 PseudoVC_FPR16VW_SE_M4 = 1062,
1087 PseudoVC_FPR16VW_SE_M8 = 1063,
1088 PseudoVC_FPR16VW_SE_MF2 = 1064,
1089 PseudoVC_FPR16VW_SE_MF4 = 1065,
1090 PseudoVC_FPR16V_SE_M1 = 1066,
1091 PseudoVC_FPR16V_SE_M2 = 1067,
1092 PseudoVC_FPR16V_SE_M4 = 1068,
1093 PseudoVC_FPR16V_SE_M8 = 1069,
1094 PseudoVC_FPR16V_SE_MF2 = 1070,
1095 PseudoVC_FPR16V_SE_MF4 = 1071,
1096 PseudoVC_FPR32VV_SE_M1 = 1072,
1097 PseudoVC_FPR32VV_SE_M2 = 1073,
1098 PseudoVC_FPR32VV_SE_M4 = 1074,
1099 PseudoVC_FPR32VV_SE_M8 = 1075,
1100 PseudoVC_FPR32VV_SE_MF2 = 1076,
1101 PseudoVC_FPR32VW_SE_M1 = 1077,
1102 PseudoVC_FPR32VW_SE_M2 = 1078,
1103 PseudoVC_FPR32VW_SE_M4 = 1079,
1104 PseudoVC_FPR32VW_SE_M8 = 1080,
1105 PseudoVC_FPR32VW_SE_MF2 = 1081,
1106 PseudoVC_FPR32V_SE_M1 = 1082,
1107 PseudoVC_FPR32V_SE_M2 = 1083,
1108 PseudoVC_FPR32V_SE_M4 = 1084,
1109 PseudoVC_FPR32V_SE_M8 = 1085,
1110 PseudoVC_FPR32V_SE_MF2 = 1086,
1111 PseudoVC_FPR64VV_SE_M1 = 1087,
1112 PseudoVC_FPR64VV_SE_M2 = 1088,
1113 PseudoVC_FPR64VV_SE_M4 = 1089,
1114 PseudoVC_FPR64VV_SE_M8 = 1090,
1115 PseudoVC_FPR64V_SE_M1 = 1091,
1116 PseudoVC_FPR64V_SE_M2 = 1092,
1117 PseudoVC_FPR64V_SE_M4 = 1093,
1118 PseudoVC_FPR64V_SE_M8 = 1094,
1119 PseudoVC_IVV_SE_M1 = 1095,
1120 PseudoVC_IVV_SE_M2 = 1096,
1121 PseudoVC_IVV_SE_M4 = 1097,
1122 PseudoVC_IVV_SE_M8 = 1098,
1123 PseudoVC_IVV_SE_MF2 = 1099,
1124 PseudoVC_IVV_SE_MF4 = 1100,
1125 PseudoVC_IVV_SE_MF8 = 1101,
1126 PseudoVC_IVW_SE_M1 = 1102,
1127 PseudoVC_IVW_SE_M2 = 1103,
1128 PseudoVC_IVW_SE_M4 = 1104,
1129 PseudoVC_IVW_SE_MF2 = 1105,
1130 PseudoVC_IVW_SE_MF4 = 1106,
1131 PseudoVC_IVW_SE_MF8 = 1107,
1132 PseudoVC_IV_SE_M1 = 1108,
1133 PseudoVC_IV_SE_M2 = 1109,
1134 PseudoVC_IV_SE_M4 = 1110,
1135 PseudoVC_IV_SE_M8 = 1111,
1136 PseudoVC_IV_SE_MF2 = 1112,
1137 PseudoVC_IV_SE_MF4 = 1113,
1138 PseudoVC_IV_SE_MF8 = 1114,
1139 PseudoVC_I_SE_M1 = 1115,
1140 PseudoVC_I_SE_M2 = 1116,
1141 PseudoVC_I_SE_M4 = 1117,
1142 PseudoVC_I_SE_M8 = 1118,
1143 PseudoVC_I_SE_MF2 = 1119,
1144 PseudoVC_I_SE_MF4 = 1120,
1145 PseudoVC_I_SE_MF8 = 1121,
1146 PseudoVC_VVV_SE_M1 = 1122,
1147 PseudoVC_VVV_SE_M2 = 1123,
1148 PseudoVC_VVV_SE_M4 = 1124,
1149 PseudoVC_VVV_SE_M8 = 1125,
1150 PseudoVC_VVV_SE_MF2 = 1126,
1151 PseudoVC_VVV_SE_MF4 = 1127,
1152 PseudoVC_VVV_SE_MF8 = 1128,
1153 PseudoVC_VVW_SE_M1 = 1129,
1154 PseudoVC_VVW_SE_M2 = 1130,
1155 PseudoVC_VVW_SE_M4 = 1131,
1156 PseudoVC_VVW_SE_MF2 = 1132,
1157 PseudoVC_VVW_SE_MF4 = 1133,
1158 PseudoVC_VVW_SE_MF8 = 1134,
1159 PseudoVC_VV_SE_M1 = 1135,
1160 PseudoVC_VV_SE_M2 = 1136,
1161 PseudoVC_VV_SE_M4 = 1137,
1162 PseudoVC_VV_SE_M8 = 1138,
1163 PseudoVC_VV_SE_MF2 = 1139,
1164 PseudoVC_VV_SE_MF4 = 1140,
1165 PseudoVC_VV_SE_MF8 = 1141,
1166 PseudoVC_V_FPR16VV_M1 = 1142,
1167 PseudoVC_V_FPR16VV_M2 = 1143,
1168 PseudoVC_V_FPR16VV_M4 = 1144,
1169 PseudoVC_V_FPR16VV_M8 = 1145,
1170 PseudoVC_V_FPR16VV_MF2 = 1146,
1171 PseudoVC_V_FPR16VV_MF4 = 1147,
1172 PseudoVC_V_FPR16VV_SE_M1 = 1148,
1173 PseudoVC_V_FPR16VV_SE_M2 = 1149,
1174 PseudoVC_V_FPR16VV_SE_M4 = 1150,
1175 PseudoVC_V_FPR16VV_SE_M8 = 1151,
1176 PseudoVC_V_FPR16VV_SE_MF2 = 1152,
1177 PseudoVC_V_FPR16VV_SE_MF4 = 1153,
1178 PseudoVC_V_FPR16VW_M1 = 1154,
1179 PseudoVC_V_FPR16VW_M2 = 1155,
1180 PseudoVC_V_FPR16VW_M4 = 1156,
1181 PseudoVC_V_FPR16VW_M8 = 1157,
1182 PseudoVC_V_FPR16VW_MF2 = 1158,
1183 PseudoVC_V_FPR16VW_MF4 = 1159,
1184 PseudoVC_V_FPR16VW_SE_M1 = 1160,
1185 PseudoVC_V_FPR16VW_SE_M2 = 1161,
1186 PseudoVC_V_FPR16VW_SE_M4 = 1162,
1187 PseudoVC_V_FPR16VW_SE_M8 = 1163,
1188 PseudoVC_V_FPR16VW_SE_MF2 = 1164,
1189 PseudoVC_V_FPR16VW_SE_MF4 = 1165,
1190 PseudoVC_V_FPR16V_M1 = 1166,
1191 PseudoVC_V_FPR16V_M2 = 1167,
1192 PseudoVC_V_FPR16V_M4 = 1168,
1193 PseudoVC_V_FPR16V_M8 = 1169,
1194 PseudoVC_V_FPR16V_MF2 = 1170,
1195 PseudoVC_V_FPR16V_MF4 = 1171,
1196 PseudoVC_V_FPR16V_SE_M1 = 1172,
1197 PseudoVC_V_FPR16V_SE_M2 = 1173,
1198 PseudoVC_V_FPR16V_SE_M4 = 1174,
1199 PseudoVC_V_FPR16V_SE_M8 = 1175,
1200 PseudoVC_V_FPR16V_SE_MF2 = 1176,
1201 PseudoVC_V_FPR16V_SE_MF4 = 1177,
1202 PseudoVC_V_FPR32VV_M1 = 1178,
1203 PseudoVC_V_FPR32VV_M2 = 1179,
1204 PseudoVC_V_FPR32VV_M4 = 1180,
1205 PseudoVC_V_FPR32VV_M8 = 1181,
1206 PseudoVC_V_FPR32VV_MF2 = 1182,
1207 PseudoVC_V_FPR32VV_SE_M1 = 1183,
1208 PseudoVC_V_FPR32VV_SE_M2 = 1184,
1209 PseudoVC_V_FPR32VV_SE_M4 = 1185,
1210 PseudoVC_V_FPR32VV_SE_M8 = 1186,
1211 PseudoVC_V_FPR32VV_SE_MF2 = 1187,
1212 PseudoVC_V_FPR32VW_M1 = 1188,
1213 PseudoVC_V_FPR32VW_M2 = 1189,
1214 PseudoVC_V_FPR32VW_M4 = 1190,
1215 PseudoVC_V_FPR32VW_M8 = 1191,
1216 PseudoVC_V_FPR32VW_MF2 = 1192,
1217 PseudoVC_V_FPR32VW_SE_M1 = 1193,
1218 PseudoVC_V_FPR32VW_SE_M2 = 1194,
1219 PseudoVC_V_FPR32VW_SE_M4 = 1195,
1220 PseudoVC_V_FPR32VW_SE_M8 = 1196,
1221 PseudoVC_V_FPR32VW_SE_MF2 = 1197,
1222 PseudoVC_V_FPR32V_M1 = 1198,
1223 PseudoVC_V_FPR32V_M2 = 1199,
1224 PseudoVC_V_FPR32V_M4 = 1200,
1225 PseudoVC_V_FPR32V_M8 = 1201,
1226 PseudoVC_V_FPR32V_MF2 = 1202,
1227 PseudoVC_V_FPR32V_SE_M1 = 1203,
1228 PseudoVC_V_FPR32V_SE_M2 = 1204,
1229 PseudoVC_V_FPR32V_SE_M4 = 1205,
1230 PseudoVC_V_FPR32V_SE_M8 = 1206,
1231 PseudoVC_V_FPR32V_SE_MF2 = 1207,
1232 PseudoVC_V_FPR64VV_M1 = 1208,
1233 PseudoVC_V_FPR64VV_M2 = 1209,
1234 PseudoVC_V_FPR64VV_M4 = 1210,
1235 PseudoVC_V_FPR64VV_M8 = 1211,
1236 PseudoVC_V_FPR64VV_SE_M1 = 1212,
1237 PseudoVC_V_FPR64VV_SE_M2 = 1213,
1238 PseudoVC_V_FPR64VV_SE_M4 = 1214,
1239 PseudoVC_V_FPR64VV_SE_M8 = 1215,
1240 PseudoVC_V_FPR64V_M1 = 1216,
1241 PseudoVC_V_FPR64V_M2 = 1217,
1242 PseudoVC_V_FPR64V_M4 = 1218,
1243 PseudoVC_V_FPR64V_M8 = 1219,
1244 PseudoVC_V_FPR64V_SE_M1 = 1220,
1245 PseudoVC_V_FPR64V_SE_M2 = 1221,
1246 PseudoVC_V_FPR64V_SE_M4 = 1222,
1247 PseudoVC_V_FPR64V_SE_M8 = 1223,
1248 PseudoVC_V_IVV_M1 = 1224,
1249 PseudoVC_V_IVV_M2 = 1225,
1250 PseudoVC_V_IVV_M4 = 1226,
1251 PseudoVC_V_IVV_M8 = 1227,
1252 PseudoVC_V_IVV_MF2 = 1228,
1253 PseudoVC_V_IVV_MF4 = 1229,
1254 PseudoVC_V_IVV_MF8 = 1230,
1255 PseudoVC_V_IVV_SE_M1 = 1231,
1256 PseudoVC_V_IVV_SE_M2 = 1232,
1257 PseudoVC_V_IVV_SE_M4 = 1233,
1258 PseudoVC_V_IVV_SE_M8 = 1234,
1259 PseudoVC_V_IVV_SE_MF2 = 1235,
1260 PseudoVC_V_IVV_SE_MF4 = 1236,
1261 PseudoVC_V_IVV_SE_MF8 = 1237,
1262 PseudoVC_V_IVW_M1 = 1238,
1263 PseudoVC_V_IVW_M2 = 1239,
1264 PseudoVC_V_IVW_M4 = 1240,
1265 PseudoVC_V_IVW_MF2 = 1241,
1266 PseudoVC_V_IVW_MF4 = 1242,
1267 PseudoVC_V_IVW_MF8 = 1243,
1268 PseudoVC_V_IVW_SE_M1 = 1244,
1269 PseudoVC_V_IVW_SE_M2 = 1245,
1270 PseudoVC_V_IVW_SE_M4 = 1246,
1271 PseudoVC_V_IVW_SE_MF2 = 1247,
1272 PseudoVC_V_IVW_SE_MF4 = 1248,
1273 PseudoVC_V_IVW_SE_MF8 = 1249,
1274 PseudoVC_V_IV_M1 = 1250,
1275 PseudoVC_V_IV_M2 = 1251,
1276 PseudoVC_V_IV_M4 = 1252,
1277 PseudoVC_V_IV_M8 = 1253,
1278 PseudoVC_V_IV_MF2 = 1254,
1279 PseudoVC_V_IV_MF4 = 1255,
1280 PseudoVC_V_IV_MF8 = 1256,
1281 PseudoVC_V_IV_SE_M1 = 1257,
1282 PseudoVC_V_IV_SE_M2 = 1258,
1283 PseudoVC_V_IV_SE_M4 = 1259,
1284 PseudoVC_V_IV_SE_M8 = 1260,
1285 PseudoVC_V_IV_SE_MF2 = 1261,
1286 PseudoVC_V_IV_SE_MF4 = 1262,
1287 PseudoVC_V_IV_SE_MF8 = 1263,
1288 PseudoVC_V_I_M1 = 1264,
1289 PseudoVC_V_I_M2 = 1265,
1290 PseudoVC_V_I_M4 = 1266,
1291 PseudoVC_V_I_M8 = 1267,
1292 PseudoVC_V_I_MF2 = 1268,
1293 PseudoVC_V_I_MF4 = 1269,
1294 PseudoVC_V_I_MF8 = 1270,
1295 PseudoVC_V_I_SE_M1 = 1271,
1296 PseudoVC_V_I_SE_M2 = 1272,
1297 PseudoVC_V_I_SE_M4 = 1273,
1298 PseudoVC_V_I_SE_M8 = 1274,
1299 PseudoVC_V_I_SE_MF2 = 1275,
1300 PseudoVC_V_I_SE_MF4 = 1276,
1301 PseudoVC_V_I_SE_MF8 = 1277,
1302 PseudoVC_V_VVV_M1 = 1278,
1303 PseudoVC_V_VVV_M2 = 1279,
1304 PseudoVC_V_VVV_M4 = 1280,
1305 PseudoVC_V_VVV_M8 = 1281,
1306 PseudoVC_V_VVV_MF2 = 1282,
1307 PseudoVC_V_VVV_MF4 = 1283,
1308 PseudoVC_V_VVV_MF8 = 1284,
1309 PseudoVC_V_VVV_SE_M1 = 1285,
1310 PseudoVC_V_VVV_SE_M2 = 1286,
1311 PseudoVC_V_VVV_SE_M4 = 1287,
1312 PseudoVC_V_VVV_SE_M8 = 1288,
1313 PseudoVC_V_VVV_SE_MF2 = 1289,
1314 PseudoVC_V_VVV_SE_MF4 = 1290,
1315 PseudoVC_V_VVV_SE_MF8 = 1291,
1316 PseudoVC_V_VVW_M1 = 1292,
1317 PseudoVC_V_VVW_M2 = 1293,
1318 PseudoVC_V_VVW_M4 = 1294,
1319 PseudoVC_V_VVW_MF2 = 1295,
1320 PseudoVC_V_VVW_MF4 = 1296,
1321 PseudoVC_V_VVW_MF8 = 1297,
1322 PseudoVC_V_VVW_SE_M1 = 1298,
1323 PseudoVC_V_VVW_SE_M2 = 1299,
1324 PseudoVC_V_VVW_SE_M4 = 1300,
1325 PseudoVC_V_VVW_SE_MF2 = 1301,
1326 PseudoVC_V_VVW_SE_MF4 = 1302,
1327 PseudoVC_V_VVW_SE_MF8 = 1303,
1328 PseudoVC_V_VV_M1 = 1304,
1329 PseudoVC_V_VV_M2 = 1305,
1330 PseudoVC_V_VV_M4 = 1306,
1331 PseudoVC_V_VV_M8 = 1307,
1332 PseudoVC_V_VV_MF2 = 1308,
1333 PseudoVC_V_VV_MF4 = 1309,
1334 PseudoVC_V_VV_MF8 = 1310,
1335 PseudoVC_V_VV_SE_M1 = 1311,
1336 PseudoVC_V_VV_SE_M2 = 1312,
1337 PseudoVC_V_VV_SE_M4 = 1313,
1338 PseudoVC_V_VV_SE_M8 = 1314,
1339 PseudoVC_V_VV_SE_MF2 = 1315,
1340 PseudoVC_V_VV_SE_MF4 = 1316,
1341 PseudoVC_V_VV_SE_MF8 = 1317,
1342 PseudoVC_V_XVV_M1 = 1318,
1343 PseudoVC_V_XVV_M2 = 1319,
1344 PseudoVC_V_XVV_M4 = 1320,
1345 PseudoVC_V_XVV_M8 = 1321,
1346 PseudoVC_V_XVV_MF2 = 1322,
1347 PseudoVC_V_XVV_MF4 = 1323,
1348 PseudoVC_V_XVV_MF8 = 1324,
1349 PseudoVC_V_XVV_SE_M1 = 1325,
1350 PseudoVC_V_XVV_SE_M2 = 1326,
1351 PseudoVC_V_XVV_SE_M4 = 1327,
1352 PseudoVC_V_XVV_SE_M8 = 1328,
1353 PseudoVC_V_XVV_SE_MF2 = 1329,
1354 PseudoVC_V_XVV_SE_MF4 = 1330,
1355 PseudoVC_V_XVV_SE_MF8 = 1331,
1356 PseudoVC_V_XVW_M1 = 1332,
1357 PseudoVC_V_XVW_M2 = 1333,
1358 PseudoVC_V_XVW_M4 = 1334,
1359 PseudoVC_V_XVW_MF2 = 1335,
1360 PseudoVC_V_XVW_MF4 = 1336,
1361 PseudoVC_V_XVW_MF8 = 1337,
1362 PseudoVC_V_XVW_SE_M1 = 1338,
1363 PseudoVC_V_XVW_SE_M2 = 1339,
1364 PseudoVC_V_XVW_SE_M4 = 1340,
1365 PseudoVC_V_XVW_SE_MF2 = 1341,
1366 PseudoVC_V_XVW_SE_MF4 = 1342,
1367 PseudoVC_V_XVW_SE_MF8 = 1343,
1368 PseudoVC_V_XV_M1 = 1344,
1369 PseudoVC_V_XV_M2 = 1345,
1370 PseudoVC_V_XV_M4 = 1346,
1371 PseudoVC_V_XV_M8 = 1347,
1372 PseudoVC_V_XV_MF2 = 1348,
1373 PseudoVC_V_XV_MF4 = 1349,
1374 PseudoVC_V_XV_MF8 = 1350,
1375 PseudoVC_V_XV_SE_M1 = 1351,
1376 PseudoVC_V_XV_SE_M2 = 1352,
1377 PseudoVC_V_XV_SE_M4 = 1353,
1378 PseudoVC_V_XV_SE_M8 = 1354,
1379 PseudoVC_V_XV_SE_MF2 = 1355,
1380 PseudoVC_V_XV_SE_MF4 = 1356,
1381 PseudoVC_V_XV_SE_MF8 = 1357,
1382 PseudoVC_V_X_M1 = 1358,
1383 PseudoVC_V_X_M2 = 1359,
1384 PseudoVC_V_X_M4 = 1360,
1385 PseudoVC_V_X_M8 = 1361,
1386 PseudoVC_V_X_MF2 = 1362,
1387 PseudoVC_V_X_MF4 = 1363,
1388 PseudoVC_V_X_MF8 = 1364,
1389 PseudoVC_V_X_SE_M1 = 1365,
1390 PseudoVC_V_X_SE_M2 = 1366,
1391 PseudoVC_V_X_SE_M4 = 1367,
1392 PseudoVC_V_X_SE_M8 = 1368,
1393 PseudoVC_V_X_SE_MF2 = 1369,
1394 PseudoVC_V_X_SE_MF4 = 1370,
1395 PseudoVC_V_X_SE_MF8 = 1371,
1396 PseudoVC_XVV_SE_M1 = 1372,
1397 PseudoVC_XVV_SE_M2 = 1373,
1398 PseudoVC_XVV_SE_M4 = 1374,
1399 PseudoVC_XVV_SE_M8 = 1375,
1400 PseudoVC_XVV_SE_MF2 = 1376,
1401 PseudoVC_XVV_SE_MF4 = 1377,
1402 PseudoVC_XVV_SE_MF8 = 1378,
1403 PseudoVC_XVW_SE_M1 = 1379,
1404 PseudoVC_XVW_SE_M2 = 1380,
1405 PseudoVC_XVW_SE_M4 = 1381,
1406 PseudoVC_XVW_SE_MF2 = 1382,
1407 PseudoVC_XVW_SE_MF4 = 1383,
1408 PseudoVC_XVW_SE_MF8 = 1384,
1409 PseudoVC_XV_SE_M1 = 1385,
1410 PseudoVC_XV_SE_M2 = 1386,
1411 PseudoVC_XV_SE_M4 = 1387,
1412 PseudoVC_XV_SE_M8 = 1388,
1413 PseudoVC_XV_SE_MF2 = 1389,
1414 PseudoVC_XV_SE_MF4 = 1390,
1415 PseudoVC_XV_SE_MF8 = 1391,
1416 PseudoVC_X_SE_M1 = 1392,
1417 PseudoVC_X_SE_M2 = 1393,
1418 PseudoVC_X_SE_M4 = 1394,
1419 PseudoVC_X_SE_M8 = 1395,
1420 PseudoVC_X_SE_MF2 = 1396,
1421 PseudoVC_X_SE_MF4 = 1397,
1422 PseudoVC_X_SE_MF8 = 1398,
1423 PseudoVDIVU_VV_M1_E16 = 1399,
1424 PseudoVDIVU_VV_M1_E16_MASK = 1400,
1425 PseudoVDIVU_VV_M1_E32 = 1401,
1426 PseudoVDIVU_VV_M1_E32_MASK = 1402,
1427 PseudoVDIVU_VV_M1_E64 = 1403,
1428 PseudoVDIVU_VV_M1_E64_MASK = 1404,
1429 PseudoVDIVU_VV_M1_E8 = 1405,
1430 PseudoVDIVU_VV_M1_E8_MASK = 1406,
1431 PseudoVDIVU_VV_M2_E16 = 1407,
1432 PseudoVDIVU_VV_M2_E16_MASK = 1408,
1433 PseudoVDIVU_VV_M2_E32 = 1409,
1434 PseudoVDIVU_VV_M2_E32_MASK = 1410,
1435 PseudoVDIVU_VV_M2_E64 = 1411,
1436 PseudoVDIVU_VV_M2_E64_MASK = 1412,
1437 PseudoVDIVU_VV_M2_E8 = 1413,
1438 PseudoVDIVU_VV_M2_E8_MASK = 1414,
1439 PseudoVDIVU_VV_M4_E16 = 1415,
1440 PseudoVDIVU_VV_M4_E16_MASK = 1416,
1441 PseudoVDIVU_VV_M4_E32 = 1417,
1442 PseudoVDIVU_VV_M4_E32_MASK = 1418,
1443 PseudoVDIVU_VV_M4_E64 = 1419,
1444 PseudoVDIVU_VV_M4_E64_MASK = 1420,
1445 PseudoVDIVU_VV_M4_E8 = 1421,
1446 PseudoVDIVU_VV_M4_E8_MASK = 1422,
1447 PseudoVDIVU_VV_M8_E16 = 1423,
1448 PseudoVDIVU_VV_M8_E16_MASK = 1424,
1449 PseudoVDIVU_VV_M8_E32 = 1425,
1450 PseudoVDIVU_VV_M8_E32_MASK = 1426,
1451 PseudoVDIVU_VV_M8_E64 = 1427,
1452 PseudoVDIVU_VV_M8_E64_MASK = 1428,
1453 PseudoVDIVU_VV_M8_E8 = 1429,
1454 PseudoVDIVU_VV_M8_E8_MASK = 1430,
1455 PseudoVDIVU_VV_MF2_E16 = 1431,
1456 PseudoVDIVU_VV_MF2_E16_MASK = 1432,
1457 PseudoVDIVU_VV_MF2_E32 = 1433,
1458 PseudoVDIVU_VV_MF2_E32_MASK = 1434,
1459 PseudoVDIVU_VV_MF2_E8 = 1435,
1460 PseudoVDIVU_VV_MF2_E8_MASK = 1436,
1461 PseudoVDIVU_VV_MF4_E16 = 1437,
1462 PseudoVDIVU_VV_MF4_E16_MASK = 1438,
1463 PseudoVDIVU_VV_MF4_E8 = 1439,
1464 PseudoVDIVU_VV_MF4_E8_MASK = 1440,
1465 PseudoVDIVU_VV_MF8_E8 = 1441,
1466 PseudoVDIVU_VV_MF8_E8_MASK = 1442,
1467 PseudoVDIVU_VX_M1_E16 = 1443,
1468 PseudoVDIVU_VX_M1_E16_MASK = 1444,
1469 PseudoVDIVU_VX_M1_E32 = 1445,
1470 PseudoVDIVU_VX_M1_E32_MASK = 1446,
1471 PseudoVDIVU_VX_M1_E64 = 1447,
1472 PseudoVDIVU_VX_M1_E64_MASK = 1448,
1473 PseudoVDIVU_VX_M1_E8 = 1449,
1474 PseudoVDIVU_VX_M1_E8_MASK = 1450,
1475 PseudoVDIVU_VX_M2_E16 = 1451,
1476 PseudoVDIVU_VX_M2_E16_MASK = 1452,
1477 PseudoVDIVU_VX_M2_E32 = 1453,
1478 PseudoVDIVU_VX_M2_E32_MASK = 1454,
1479 PseudoVDIVU_VX_M2_E64 = 1455,
1480 PseudoVDIVU_VX_M2_E64_MASK = 1456,
1481 PseudoVDIVU_VX_M2_E8 = 1457,
1482 PseudoVDIVU_VX_M2_E8_MASK = 1458,
1483 PseudoVDIVU_VX_M4_E16 = 1459,
1484 PseudoVDIVU_VX_M4_E16_MASK = 1460,
1485 PseudoVDIVU_VX_M4_E32 = 1461,
1486 PseudoVDIVU_VX_M4_E32_MASK = 1462,
1487 PseudoVDIVU_VX_M4_E64 = 1463,
1488 PseudoVDIVU_VX_M4_E64_MASK = 1464,
1489 PseudoVDIVU_VX_M4_E8 = 1465,
1490 PseudoVDIVU_VX_M4_E8_MASK = 1466,
1491 PseudoVDIVU_VX_M8_E16 = 1467,
1492 PseudoVDIVU_VX_M8_E16_MASK = 1468,
1493 PseudoVDIVU_VX_M8_E32 = 1469,
1494 PseudoVDIVU_VX_M8_E32_MASK = 1470,
1495 PseudoVDIVU_VX_M8_E64 = 1471,
1496 PseudoVDIVU_VX_M8_E64_MASK = 1472,
1497 PseudoVDIVU_VX_M8_E8 = 1473,
1498 PseudoVDIVU_VX_M8_E8_MASK = 1474,
1499 PseudoVDIVU_VX_MF2_E16 = 1475,
1500 PseudoVDIVU_VX_MF2_E16_MASK = 1476,
1501 PseudoVDIVU_VX_MF2_E32 = 1477,
1502 PseudoVDIVU_VX_MF2_E32_MASK = 1478,
1503 PseudoVDIVU_VX_MF2_E8 = 1479,
1504 PseudoVDIVU_VX_MF2_E8_MASK = 1480,
1505 PseudoVDIVU_VX_MF4_E16 = 1481,
1506 PseudoVDIVU_VX_MF4_E16_MASK = 1482,
1507 PseudoVDIVU_VX_MF4_E8 = 1483,
1508 PseudoVDIVU_VX_MF4_E8_MASK = 1484,
1509 PseudoVDIVU_VX_MF8_E8 = 1485,
1510 PseudoVDIVU_VX_MF8_E8_MASK = 1486,
1511 PseudoVDIV_VV_M1_E16 = 1487,
1512 PseudoVDIV_VV_M1_E16_MASK = 1488,
1513 PseudoVDIV_VV_M1_E32 = 1489,
1514 PseudoVDIV_VV_M1_E32_MASK = 1490,
1515 PseudoVDIV_VV_M1_E64 = 1491,
1516 PseudoVDIV_VV_M1_E64_MASK = 1492,
1517 PseudoVDIV_VV_M1_E8 = 1493,
1518 PseudoVDIV_VV_M1_E8_MASK = 1494,
1519 PseudoVDIV_VV_M2_E16 = 1495,
1520 PseudoVDIV_VV_M2_E16_MASK = 1496,
1521 PseudoVDIV_VV_M2_E32 = 1497,
1522 PseudoVDIV_VV_M2_E32_MASK = 1498,
1523 PseudoVDIV_VV_M2_E64 = 1499,
1524 PseudoVDIV_VV_M2_E64_MASK = 1500,
1525 PseudoVDIV_VV_M2_E8 = 1501,
1526 PseudoVDIV_VV_M2_E8_MASK = 1502,
1527 PseudoVDIV_VV_M4_E16 = 1503,
1528 PseudoVDIV_VV_M4_E16_MASK = 1504,
1529 PseudoVDIV_VV_M4_E32 = 1505,
1530 PseudoVDIV_VV_M4_E32_MASK = 1506,
1531 PseudoVDIV_VV_M4_E64 = 1507,
1532 PseudoVDIV_VV_M4_E64_MASK = 1508,
1533 PseudoVDIV_VV_M4_E8 = 1509,
1534 PseudoVDIV_VV_M4_E8_MASK = 1510,
1535 PseudoVDIV_VV_M8_E16 = 1511,
1536 PseudoVDIV_VV_M8_E16_MASK = 1512,
1537 PseudoVDIV_VV_M8_E32 = 1513,
1538 PseudoVDIV_VV_M8_E32_MASK = 1514,
1539 PseudoVDIV_VV_M8_E64 = 1515,
1540 PseudoVDIV_VV_M8_E64_MASK = 1516,
1541 PseudoVDIV_VV_M8_E8 = 1517,
1542 PseudoVDIV_VV_M8_E8_MASK = 1518,
1543 PseudoVDIV_VV_MF2_E16 = 1519,
1544 PseudoVDIV_VV_MF2_E16_MASK = 1520,
1545 PseudoVDIV_VV_MF2_E32 = 1521,
1546 PseudoVDIV_VV_MF2_E32_MASK = 1522,
1547 PseudoVDIV_VV_MF2_E8 = 1523,
1548 PseudoVDIV_VV_MF2_E8_MASK = 1524,
1549 PseudoVDIV_VV_MF4_E16 = 1525,
1550 PseudoVDIV_VV_MF4_E16_MASK = 1526,
1551 PseudoVDIV_VV_MF4_E8 = 1527,
1552 PseudoVDIV_VV_MF4_E8_MASK = 1528,
1553 PseudoVDIV_VV_MF8_E8 = 1529,
1554 PseudoVDIV_VV_MF8_E8_MASK = 1530,
1555 PseudoVDIV_VX_M1_E16 = 1531,
1556 PseudoVDIV_VX_M1_E16_MASK = 1532,
1557 PseudoVDIV_VX_M1_E32 = 1533,
1558 PseudoVDIV_VX_M1_E32_MASK = 1534,
1559 PseudoVDIV_VX_M1_E64 = 1535,
1560 PseudoVDIV_VX_M1_E64_MASK = 1536,
1561 PseudoVDIV_VX_M1_E8 = 1537,
1562 PseudoVDIV_VX_M1_E8_MASK = 1538,
1563 PseudoVDIV_VX_M2_E16 = 1539,
1564 PseudoVDIV_VX_M2_E16_MASK = 1540,
1565 PseudoVDIV_VX_M2_E32 = 1541,
1566 PseudoVDIV_VX_M2_E32_MASK = 1542,
1567 PseudoVDIV_VX_M2_E64 = 1543,
1568 PseudoVDIV_VX_M2_E64_MASK = 1544,
1569 PseudoVDIV_VX_M2_E8 = 1545,
1570 PseudoVDIV_VX_M2_E8_MASK = 1546,
1571 PseudoVDIV_VX_M4_E16 = 1547,
1572 PseudoVDIV_VX_M4_E16_MASK = 1548,
1573 PseudoVDIV_VX_M4_E32 = 1549,
1574 PseudoVDIV_VX_M4_E32_MASK = 1550,
1575 PseudoVDIV_VX_M4_E64 = 1551,
1576 PseudoVDIV_VX_M4_E64_MASK = 1552,
1577 PseudoVDIV_VX_M4_E8 = 1553,
1578 PseudoVDIV_VX_M4_E8_MASK = 1554,
1579 PseudoVDIV_VX_M8_E16 = 1555,
1580 PseudoVDIV_VX_M8_E16_MASK = 1556,
1581 PseudoVDIV_VX_M8_E32 = 1557,
1582 PseudoVDIV_VX_M8_E32_MASK = 1558,
1583 PseudoVDIV_VX_M8_E64 = 1559,
1584 PseudoVDIV_VX_M8_E64_MASK = 1560,
1585 PseudoVDIV_VX_M8_E8 = 1561,
1586 PseudoVDIV_VX_M8_E8_MASK = 1562,
1587 PseudoVDIV_VX_MF2_E16 = 1563,
1588 PseudoVDIV_VX_MF2_E16_MASK = 1564,
1589 PseudoVDIV_VX_MF2_E32 = 1565,
1590 PseudoVDIV_VX_MF2_E32_MASK = 1566,
1591 PseudoVDIV_VX_MF2_E8 = 1567,
1592 PseudoVDIV_VX_MF2_E8_MASK = 1568,
1593 PseudoVDIV_VX_MF4_E16 = 1569,
1594 PseudoVDIV_VX_MF4_E16_MASK = 1570,
1595 PseudoVDIV_VX_MF4_E8 = 1571,
1596 PseudoVDIV_VX_MF4_E8_MASK = 1572,
1597 PseudoVDIV_VX_MF8_E8 = 1573,
1598 PseudoVDIV_VX_MF8_E8_MASK = 1574,
1599 PseudoVFADD_VFPR16_M1_E16 = 1575,
1600 PseudoVFADD_VFPR16_M1_E16_MASK = 1576,
1601 PseudoVFADD_VFPR16_M2_E16 = 1577,
1602 PseudoVFADD_VFPR16_M2_E16_MASK = 1578,
1603 PseudoVFADD_VFPR16_M4_E16 = 1579,
1604 PseudoVFADD_VFPR16_M4_E16_MASK = 1580,
1605 PseudoVFADD_VFPR16_M8_E16 = 1581,
1606 PseudoVFADD_VFPR16_M8_E16_MASK = 1582,
1607 PseudoVFADD_VFPR16_MF2_E16 = 1583,
1608 PseudoVFADD_VFPR16_MF2_E16_MASK = 1584,
1609 PseudoVFADD_VFPR16_MF4_E16 = 1585,
1610 PseudoVFADD_VFPR16_MF4_E16_MASK = 1586,
1611 PseudoVFADD_VFPR32_M1_E32 = 1587,
1612 PseudoVFADD_VFPR32_M1_E32_MASK = 1588,
1613 PseudoVFADD_VFPR32_M2_E32 = 1589,
1614 PseudoVFADD_VFPR32_M2_E32_MASK = 1590,
1615 PseudoVFADD_VFPR32_M4_E32 = 1591,
1616 PseudoVFADD_VFPR32_M4_E32_MASK = 1592,
1617 PseudoVFADD_VFPR32_M8_E32 = 1593,
1618 PseudoVFADD_VFPR32_M8_E32_MASK = 1594,
1619 PseudoVFADD_VFPR32_MF2_E32 = 1595,
1620 PseudoVFADD_VFPR32_MF2_E32_MASK = 1596,
1621 PseudoVFADD_VFPR64_M1_E64 = 1597,
1622 PseudoVFADD_VFPR64_M1_E64_MASK = 1598,
1623 PseudoVFADD_VFPR64_M2_E64 = 1599,
1624 PseudoVFADD_VFPR64_M2_E64_MASK = 1600,
1625 PseudoVFADD_VFPR64_M4_E64 = 1601,
1626 PseudoVFADD_VFPR64_M4_E64_MASK = 1602,
1627 PseudoVFADD_VFPR64_M8_E64 = 1603,
1628 PseudoVFADD_VFPR64_M8_E64_MASK = 1604,
1629 PseudoVFADD_VV_M1_E16 = 1605,
1630 PseudoVFADD_VV_M1_E16_MASK = 1606,
1631 PseudoVFADD_VV_M1_E32 = 1607,
1632 PseudoVFADD_VV_M1_E32_MASK = 1608,
1633 PseudoVFADD_VV_M1_E64 = 1609,
1634 PseudoVFADD_VV_M1_E64_MASK = 1610,
1635 PseudoVFADD_VV_M2_E16 = 1611,
1636 PseudoVFADD_VV_M2_E16_MASK = 1612,
1637 PseudoVFADD_VV_M2_E32 = 1613,
1638 PseudoVFADD_VV_M2_E32_MASK = 1614,
1639 PseudoVFADD_VV_M2_E64 = 1615,
1640 PseudoVFADD_VV_M2_E64_MASK = 1616,
1641 PseudoVFADD_VV_M4_E16 = 1617,
1642 PseudoVFADD_VV_M4_E16_MASK = 1618,
1643 PseudoVFADD_VV_M4_E32 = 1619,
1644 PseudoVFADD_VV_M4_E32_MASK = 1620,
1645 PseudoVFADD_VV_M4_E64 = 1621,
1646 PseudoVFADD_VV_M4_E64_MASK = 1622,
1647 PseudoVFADD_VV_M8_E16 = 1623,
1648 PseudoVFADD_VV_M8_E16_MASK = 1624,
1649 PseudoVFADD_VV_M8_E32 = 1625,
1650 PseudoVFADD_VV_M8_E32_MASK = 1626,
1651 PseudoVFADD_VV_M8_E64 = 1627,
1652 PseudoVFADD_VV_M8_E64_MASK = 1628,
1653 PseudoVFADD_VV_MF2_E16 = 1629,
1654 PseudoVFADD_VV_MF2_E16_MASK = 1630,
1655 PseudoVFADD_VV_MF2_E32 = 1631,
1656 PseudoVFADD_VV_MF2_E32_MASK = 1632,
1657 PseudoVFADD_VV_MF4_E16 = 1633,
1658 PseudoVFADD_VV_MF4_E16_MASK = 1634,
1659 PseudoVFCLASS_V_M1 = 1635,
1660 PseudoVFCLASS_V_M1_MASK = 1636,
1661 PseudoVFCLASS_V_M2 = 1637,
1662 PseudoVFCLASS_V_M2_MASK = 1638,
1663 PseudoVFCLASS_V_M4 = 1639,
1664 PseudoVFCLASS_V_M4_MASK = 1640,
1665 PseudoVFCLASS_V_M8 = 1641,
1666 PseudoVFCLASS_V_M8_MASK = 1642,
1667 PseudoVFCLASS_V_MF2 = 1643,
1668 PseudoVFCLASS_V_MF2_MASK = 1644,
1669 PseudoVFCLASS_V_MF4 = 1645,
1670 PseudoVFCLASS_V_MF4_MASK = 1646,
1671 PseudoVFCVT_F_XU_V_M1_E16 = 1647,
1672 PseudoVFCVT_F_XU_V_M1_E16_MASK = 1648,
1673 PseudoVFCVT_F_XU_V_M1_E32 = 1649,
1674 PseudoVFCVT_F_XU_V_M1_E32_MASK = 1650,
1675 PseudoVFCVT_F_XU_V_M1_E64 = 1651,
1676 PseudoVFCVT_F_XU_V_M1_E64_MASK = 1652,
1677 PseudoVFCVT_F_XU_V_M2_E16 = 1653,
1678 PseudoVFCVT_F_XU_V_M2_E16_MASK = 1654,
1679 PseudoVFCVT_F_XU_V_M2_E32 = 1655,
1680 PseudoVFCVT_F_XU_V_M2_E32_MASK = 1656,
1681 PseudoVFCVT_F_XU_V_M2_E64 = 1657,
1682 PseudoVFCVT_F_XU_V_M2_E64_MASK = 1658,
1683 PseudoVFCVT_F_XU_V_M4_E16 = 1659,
1684 PseudoVFCVT_F_XU_V_M4_E16_MASK = 1660,
1685 PseudoVFCVT_F_XU_V_M4_E32 = 1661,
1686 PseudoVFCVT_F_XU_V_M4_E32_MASK = 1662,
1687 PseudoVFCVT_F_XU_V_M4_E64 = 1663,
1688 PseudoVFCVT_F_XU_V_M4_E64_MASK = 1664,
1689 PseudoVFCVT_F_XU_V_M8_E16 = 1665,
1690 PseudoVFCVT_F_XU_V_M8_E16_MASK = 1666,
1691 PseudoVFCVT_F_XU_V_M8_E32 = 1667,
1692 PseudoVFCVT_F_XU_V_M8_E32_MASK = 1668,
1693 PseudoVFCVT_F_XU_V_M8_E64 = 1669,
1694 PseudoVFCVT_F_XU_V_M8_E64_MASK = 1670,
1695 PseudoVFCVT_F_XU_V_MF2_E16 = 1671,
1696 PseudoVFCVT_F_XU_V_MF2_E16_MASK = 1672,
1697 PseudoVFCVT_F_XU_V_MF2_E32 = 1673,
1698 PseudoVFCVT_F_XU_V_MF2_E32_MASK = 1674,
1699 PseudoVFCVT_F_XU_V_MF4_E16 = 1675,
1700 PseudoVFCVT_F_XU_V_MF4_E16_MASK = 1676,
1701 PseudoVFCVT_F_X_V_M1_E16 = 1677,
1702 PseudoVFCVT_F_X_V_M1_E16_MASK = 1678,
1703 PseudoVFCVT_F_X_V_M1_E32 = 1679,
1704 PseudoVFCVT_F_X_V_M1_E32_MASK = 1680,
1705 PseudoVFCVT_F_X_V_M1_E64 = 1681,
1706 PseudoVFCVT_F_X_V_M1_E64_MASK = 1682,
1707 PseudoVFCVT_F_X_V_M2_E16 = 1683,
1708 PseudoVFCVT_F_X_V_M2_E16_MASK = 1684,
1709 PseudoVFCVT_F_X_V_M2_E32 = 1685,
1710 PseudoVFCVT_F_X_V_M2_E32_MASK = 1686,
1711 PseudoVFCVT_F_X_V_M2_E64 = 1687,
1712 PseudoVFCVT_F_X_V_M2_E64_MASK = 1688,
1713 PseudoVFCVT_F_X_V_M4_E16 = 1689,
1714 PseudoVFCVT_F_X_V_M4_E16_MASK = 1690,
1715 PseudoVFCVT_F_X_V_M4_E32 = 1691,
1716 PseudoVFCVT_F_X_V_M4_E32_MASK = 1692,
1717 PseudoVFCVT_F_X_V_M4_E64 = 1693,
1718 PseudoVFCVT_F_X_V_M4_E64_MASK = 1694,
1719 PseudoVFCVT_F_X_V_M8_E16 = 1695,
1720 PseudoVFCVT_F_X_V_M8_E16_MASK = 1696,
1721 PseudoVFCVT_F_X_V_M8_E32 = 1697,
1722 PseudoVFCVT_F_X_V_M8_E32_MASK = 1698,
1723 PseudoVFCVT_F_X_V_M8_E64 = 1699,
1724 PseudoVFCVT_F_X_V_M8_E64_MASK = 1700,
1725 PseudoVFCVT_F_X_V_MF2_E16 = 1701,
1726 PseudoVFCVT_F_X_V_MF2_E16_MASK = 1702,
1727 PseudoVFCVT_F_X_V_MF2_E32 = 1703,
1728 PseudoVFCVT_F_X_V_MF2_E32_MASK = 1704,
1729 PseudoVFCVT_F_X_V_MF4_E16 = 1705,
1730 PseudoVFCVT_F_X_V_MF4_E16_MASK = 1706,
1731 PseudoVFCVT_RM_F_XU_V_M1_E16 = 1707,
1732 PseudoVFCVT_RM_F_XU_V_M1_E16_MASK = 1708,
1733 PseudoVFCVT_RM_F_XU_V_M1_E32 = 1709,
1734 PseudoVFCVT_RM_F_XU_V_M1_E32_MASK = 1710,
1735 PseudoVFCVT_RM_F_XU_V_M1_E64 = 1711,
1736 PseudoVFCVT_RM_F_XU_V_M1_E64_MASK = 1712,
1737 PseudoVFCVT_RM_F_XU_V_M2_E16 = 1713,
1738 PseudoVFCVT_RM_F_XU_V_M2_E16_MASK = 1714,
1739 PseudoVFCVT_RM_F_XU_V_M2_E32 = 1715,
1740 PseudoVFCVT_RM_F_XU_V_M2_E32_MASK = 1716,
1741 PseudoVFCVT_RM_F_XU_V_M2_E64 = 1717,
1742 PseudoVFCVT_RM_F_XU_V_M2_E64_MASK = 1718,
1743 PseudoVFCVT_RM_F_XU_V_M4_E16 = 1719,
1744 PseudoVFCVT_RM_F_XU_V_M4_E16_MASK = 1720,
1745 PseudoVFCVT_RM_F_XU_V_M4_E32 = 1721,
1746 PseudoVFCVT_RM_F_XU_V_M4_E32_MASK = 1722,
1747 PseudoVFCVT_RM_F_XU_V_M4_E64 = 1723,
1748 PseudoVFCVT_RM_F_XU_V_M4_E64_MASK = 1724,
1749 PseudoVFCVT_RM_F_XU_V_M8_E16 = 1725,
1750 PseudoVFCVT_RM_F_XU_V_M8_E16_MASK = 1726,
1751 PseudoVFCVT_RM_F_XU_V_M8_E32 = 1727,
1752 PseudoVFCVT_RM_F_XU_V_M8_E32_MASK = 1728,
1753 PseudoVFCVT_RM_F_XU_V_M8_E64 = 1729,
1754 PseudoVFCVT_RM_F_XU_V_M8_E64_MASK = 1730,
1755 PseudoVFCVT_RM_F_XU_V_MF2_E16 = 1731,
1756 PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK = 1732,
1757 PseudoVFCVT_RM_F_XU_V_MF2_E32 = 1733,
1758 PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK = 1734,
1759 PseudoVFCVT_RM_F_XU_V_MF4_E16 = 1735,
1760 PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK = 1736,
1761 PseudoVFCVT_RM_F_X_V_M1_E16 = 1737,
1762 PseudoVFCVT_RM_F_X_V_M1_E16_MASK = 1738,
1763 PseudoVFCVT_RM_F_X_V_M1_E32 = 1739,
1764 PseudoVFCVT_RM_F_X_V_M1_E32_MASK = 1740,
1765 PseudoVFCVT_RM_F_X_V_M1_E64 = 1741,
1766 PseudoVFCVT_RM_F_X_V_M1_E64_MASK = 1742,
1767 PseudoVFCVT_RM_F_X_V_M2_E16 = 1743,
1768 PseudoVFCVT_RM_F_X_V_M2_E16_MASK = 1744,
1769 PseudoVFCVT_RM_F_X_V_M2_E32 = 1745,
1770 PseudoVFCVT_RM_F_X_V_M2_E32_MASK = 1746,
1771 PseudoVFCVT_RM_F_X_V_M2_E64 = 1747,
1772 PseudoVFCVT_RM_F_X_V_M2_E64_MASK = 1748,
1773 PseudoVFCVT_RM_F_X_V_M4_E16 = 1749,
1774 PseudoVFCVT_RM_F_X_V_M4_E16_MASK = 1750,
1775 PseudoVFCVT_RM_F_X_V_M4_E32 = 1751,
1776 PseudoVFCVT_RM_F_X_V_M4_E32_MASK = 1752,
1777 PseudoVFCVT_RM_F_X_V_M4_E64 = 1753,
1778 PseudoVFCVT_RM_F_X_V_M4_E64_MASK = 1754,
1779 PseudoVFCVT_RM_F_X_V_M8_E16 = 1755,
1780 PseudoVFCVT_RM_F_X_V_M8_E16_MASK = 1756,
1781 PseudoVFCVT_RM_F_X_V_M8_E32 = 1757,
1782 PseudoVFCVT_RM_F_X_V_M8_E32_MASK = 1758,
1783 PseudoVFCVT_RM_F_X_V_M8_E64 = 1759,
1784 PseudoVFCVT_RM_F_X_V_M8_E64_MASK = 1760,
1785 PseudoVFCVT_RM_F_X_V_MF2_E16 = 1761,
1786 PseudoVFCVT_RM_F_X_V_MF2_E16_MASK = 1762,
1787 PseudoVFCVT_RM_F_X_V_MF2_E32 = 1763,
1788 PseudoVFCVT_RM_F_X_V_MF2_E32_MASK = 1764,
1789 PseudoVFCVT_RM_F_X_V_MF4_E16 = 1765,
1790 PseudoVFCVT_RM_F_X_V_MF4_E16_MASK = 1766,
1791 PseudoVFCVT_RM_XU_F_V_M1 = 1767,
1792 PseudoVFCVT_RM_XU_F_V_M1_MASK = 1768,
1793 PseudoVFCVT_RM_XU_F_V_M2 = 1769,
1794 PseudoVFCVT_RM_XU_F_V_M2_MASK = 1770,
1795 PseudoVFCVT_RM_XU_F_V_M4 = 1771,
1796 PseudoVFCVT_RM_XU_F_V_M4_MASK = 1772,
1797 PseudoVFCVT_RM_XU_F_V_M8 = 1773,
1798 PseudoVFCVT_RM_XU_F_V_M8_MASK = 1774,
1799 PseudoVFCVT_RM_XU_F_V_MF2 = 1775,
1800 PseudoVFCVT_RM_XU_F_V_MF2_MASK = 1776,
1801 PseudoVFCVT_RM_XU_F_V_MF4 = 1777,
1802 PseudoVFCVT_RM_XU_F_V_MF4_MASK = 1778,
1803 PseudoVFCVT_RM_X_F_V_M1 = 1779,
1804 PseudoVFCVT_RM_X_F_V_M1_MASK = 1780,
1805 PseudoVFCVT_RM_X_F_V_M2 = 1781,
1806 PseudoVFCVT_RM_X_F_V_M2_MASK = 1782,
1807 PseudoVFCVT_RM_X_F_V_M4 = 1783,
1808 PseudoVFCVT_RM_X_F_V_M4_MASK = 1784,
1809 PseudoVFCVT_RM_X_F_V_M8 = 1785,
1810 PseudoVFCVT_RM_X_F_V_M8_MASK = 1786,
1811 PseudoVFCVT_RM_X_F_V_MF2 = 1787,
1812 PseudoVFCVT_RM_X_F_V_MF2_MASK = 1788,
1813 PseudoVFCVT_RM_X_F_V_MF4 = 1789,
1814 PseudoVFCVT_RM_X_F_V_MF4_MASK = 1790,
1815 PseudoVFCVT_RTZ_XU_F_V_M1 = 1791,
1816 PseudoVFCVT_RTZ_XU_F_V_M1_MASK = 1792,
1817 PseudoVFCVT_RTZ_XU_F_V_M2 = 1793,
1818 PseudoVFCVT_RTZ_XU_F_V_M2_MASK = 1794,
1819 PseudoVFCVT_RTZ_XU_F_V_M4 = 1795,
1820 PseudoVFCVT_RTZ_XU_F_V_M4_MASK = 1796,
1821 PseudoVFCVT_RTZ_XU_F_V_M8 = 1797,
1822 PseudoVFCVT_RTZ_XU_F_V_M8_MASK = 1798,
1823 PseudoVFCVT_RTZ_XU_F_V_MF2 = 1799,
1824 PseudoVFCVT_RTZ_XU_F_V_MF2_MASK = 1800,
1825 PseudoVFCVT_RTZ_XU_F_V_MF4 = 1801,
1826 PseudoVFCVT_RTZ_XU_F_V_MF4_MASK = 1802,
1827 PseudoVFCVT_RTZ_X_F_V_M1 = 1803,
1828 PseudoVFCVT_RTZ_X_F_V_M1_MASK = 1804,
1829 PseudoVFCVT_RTZ_X_F_V_M2 = 1805,
1830 PseudoVFCVT_RTZ_X_F_V_M2_MASK = 1806,
1831 PseudoVFCVT_RTZ_X_F_V_M4 = 1807,
1832 PseudoVFCVT_RTZ_X_F_V_M4_MASK = 1808,
1833 PseudoVFCVT_RTZ_X_F_V_M8 = 1809,
1834 PseudoVFCVT_RTZ_X_F_V_M8_MASK = 1810,
1835 PseudoVFCVT_RTZ_X_F_V_MF2 = 1811,
1836 PseudoVFCVT_RTZ_X_F_V_MF2_MASK = 1812,
1837 PseudoVFCVT_RTZ_X_F_V_MF4 = 1813,
1838 PseudoVFCVT_RTZ_X_F_V_MF4_MASK = 1814,
1839 PseudoVFCVT_XU_F_V_M1 = 1815,
1840 PseudoVFCVT_XU_F_V_M1_MASK = 1816,
1841 PseudoVFCVT_XU_F_V_M2 = 1817,
1842 PseudoVFCVT_XU_F_V_M2_MASK = 1818,
1843 PseudoVFCVT_XU_F_V_M4 = 1819,
1844 PseudoVFCVT_XU_F_V_M4_MASK = 1820,
1845 PseudoVFCVT_XU_F_V_M8 = 1821,
1846 PseudoVFCVT_XU_F_V_M8_MASK = 1822,
1847 PseudoVFCVT_XU_F_V_MF2 = 1823,
1848 PseudoVFCVT_XU_F_V_MF2_MASK = 1824,
1849 PseudoVFCVT_XU_F_V_MF4 = 1825,
1850 PseudoVFCVT_XU_F_V_MF4_MASK = 1826,
1851 PseudoVFCVT_X_F_V_M1 = 1827,
1852 PseudoVFCVT_X_F_V_M1_MASK = 1828,
1853 PseudoVFCVT_X_F_V_M2 = 1829,
1854 PseudoVFCVT_X_F_V_M2_MASK = 1830,
1855 PseudoVFCVT_X_F_V_M4 = 1831,
1856 PseudoVFCVT_X_F_V_M4_MASK = 1832,
1857 PseudoVFCVT_X_F_V_M8 = 1833,
1858 PseudoVFCVT_X_F_V_M8_MASK = 1834,
1859 PseudoVFCVT_X_F_V_MF2 = 1835,
1860 PseudoVFCVT_X_F_V_MF2_MASK = 1836,
1861 PseudoVFCVT_X_F_V_MF4 = 1837,
1862 PseudoVFCVT_X_F_V_MF4_MASK = 1838,
1863 PseudoVFDIV_VFPR16_M1_E16 = 1839,
1864 PseudoVFDIV_VFPR16_M1_E16_MASK = 1840,
1865 PseudoVFDIV_VFPR16_M2_E16 = 1841,
1866 PseudoVFDIV_VFPR16_M2_E16_MASK = 1842,
1867 PseudoVFDIV_VFPR16_M4_E16 = 1843,
1868 PseudoVFDIV_VFPR16_M4_E16_MASK = 1844,
1869 PseudoVFDIV_VFPR16_M8_E16 = 1845,
1870 PseudoVFDIV_VFPR16_M8_E16_MASK = 1846,
1871 PseudoVFDIV_VFPR16_MF2_E16 = 1847,
1872 PseudoVFDIV_VFPR16_MF2_E16_MASK = 1848,
1873 PseudoVFDIV_VFPR16_MF4_E16 = 1849,
1874 PseudoVFDIV_VFPR16_MF4_E16_MASK = 1850,
1875 PseudoVFDIV_VFPR32_M1_E32 = 1851,
1876 PseudoVFDIV_VFPR32_M1_E32_MASK = 1852,
1877 PseudoVFDIV_VFPR32_M2_E32 = 1853,
1878 PseudoVFDIV_VFPR32_M2_E32_MASK = 1854,
1879 PseudoVFDIV_VFPR32_M4_E32 = 1855,
1880 PseudoVFDIV_VFPR32_M4_E32_MASK = 1856,
1881 PseudoVFDIV_VFPR32_M8_E32 = 1857,
1882 PseudoVFDIV_VFPR32_M8_E32_MASK = 1858,
1883 PseudoVFDIV_VFPR32_MF2_E32 = 1859,
1884 PseudoVFDIV_VFPR32_MF2_E32_MASK = 1860,
1885 PseudoVFDIV_VFPR64_M1_E64 = 1861,
1886 PseudoVFDIV_VFPR64_M1_E64_MASK = 1862,
1887 PseudoVFDIV_VFPR64_M2_E64 = 1863,
1888 PseudoVFDIV_VFPR64_M2_E64_MASK = 1864,
1889 PseudoVFDIV_VFPR64_M4_E64 = 1865,
1890 PseudoVFDIV_VFPR64_M4_E64_MASK = 1866,
1891 PseudoVFDIV_VFPR64_M8_E64 = 1867,
1892 PseudoVFDIV_VFPR64_M8_E64_MASK = 1868,
1893 PseudoVFDIV_VV_M1_E16 = 1869,
1894 PseudoVFDIV_VV_M1_E16_MASK = 1870,
1895 PseudoVFDIV_VV_M1_E32 = 1871,
1896 PseudoVFDIV_VV_M1_E32_MASK = 1872,
1897 PseudoVFDIV_VV_M1_E64 = 1873,
1898 PseudoVFDIV_VV_M1_E64_MASK = 1874,
1899 PseudoVFDIV_VV_M2_E16 = 1875,
1900 PseudoVFDIV_VV_M2_E16_MASK = 1876,
1901 PseudoVFDIV_VV_M2_E32 = 1877,
1902 PseudoVFDIV_VV_M2_E32_MASK = 1878,
1903 PseudoVFDIV_VV_M2_E64 = 1879,
1904 PseudoVFDIV_VV_M2_E64_MASK = 1880,
1905 PseudoVFDIV_VV_M4_E16 = 1881,
1906 PseudoVFDIV_VV_M4_E16_MASK = 1882,
1907 PseudoVFDIV_VV_M4_E32 = 1883,
1908 PseudoVFDIV_VV_M4_E32_MASK = 1884,
1909 PseudoVFDIV_VV_M4_E64 = 1885,
1910 PseudoVFDIV_VV_M4_E64_MASK = 1886,
1911 PseudoVFDIV_VV_M8_E16 = 1887,
1912 PseudoVFDIV_VV_M8_E16_MASK = 1888,
1913 PseudoVFDIV_VV_M8_E32 = 1889,
1914 PseudoVFDIV_VV_M8_E32_MASK = 1890,
1915 PseudoVFDIV_VV_M8_E64 = 1891,
1916 PseudoVFDIV_VV_M8_E64_MASK = 1892,
1917 PseudoVFDIV_VV_MF2_E16 = 1893,
1918 PseudoVFDIV_VV_MF2_E16_MASK = 1894,
1919 PseudoVFDIV_VV_MF2_E32 = 1895,
1920 PseudoVFDIV_VV_MF2_E32_MASK = 1896,
1921 PseudoVFDIV_VV_MF4_E16 = 1897,
1922 PseudoVFDIV_VV_MF4_E16_MASK = 1898,
1923 PseudoVFIRST_M_B1 = 1899,
1924 PseudoVFIRST_M_B16 = 1900,
1925 PseudoVFIRST_M_B16_MASK = 1901,
1926 PseudoVFIRST_M_B1_MASK = 1902,
1927 PseudoVFIRST_M_B2 = 1903,
1928 PseudoVFIRST_M_B2_MASK = 1904,
1929 PseudoVFIRST_M_B32 = 1905,
1930 PseudoVFIRST_M_B32_MASK = 1906,
1931 PseudoVFIRST_M_B4 = 1907,
1932 PseudoVFIRST_M_B4_MASK = 1908,
1933 PseudoVFIRST_M_B64 = 1909,
1934 PseudoVFIRST_M_B64_MASK = 1910,
1935 PseudoVFIRST_M_B8 = 1911,
1936 PseudoVFIRST_M_B8_MASK = 1912,
1937 PseudoVFMACC_VFPR16_M1_E16 = 1913,
1938 PseudoVFMACC_VFPR16_M1_E16_MASK = 1914,
1939 PseudoVFMACC_VFPR16_M2_E16 = 1915,
1940 PseudoVFMACC_VFPR16_M2_E16_MASK = 1916,
1941 PseudoVFMACC_VFPR16_M4_E16 = 1917,
1942 PseudoVFMACC_VFPR16_M4_E16_MASK = 1918,
1943 PseudoVFMACC_VFPR16_M8_E16 = 1919,
1944 PseudoVFMACC_VFPR16_M8_E16_MASK = 1920,
1945 PseudoVFMACC_VFPR16_MF2_E16 = 1921,
1946 PseudoVFMACC_VFPR16_MF2_E16_MASK = 1922,
1947 PseudoVFMACC_VFPR16_MF4_E16 = 1923,
1948 PseudoVFMACC_VFPR16_MF4_E16_MASK = 1924,
1949 PseudoVFMACC_VFPR32_M1_E32 = 1925,
1950 PseudoVFMACC_VFPR32_M1_E32_MASK = 1926,
1951 PseudoVFMACC_VFPR32_M2_E32 = 1927,
1952 PseudoVFMACC_VFPR32_M2_E32_MASK = 1928,
1953 PseudoVFMACC_VFPR32_M4_E32 = 1929,
1954 PseudoVFMACC_VFPR32_M4_E32_MASK = 1930,
1955 PseudoVFMACC_VFPR32_M8_E32 = 1931,
1956 PseudoVFMACC_VFPR32_M8_E32_MASK = 1932,
1957 PseudoVFMACC_VFPR32_MF2_E32 = 1933,
1958 PseudoVFMACC_VFPR32_MF2_E32_MASK = 1934,
1959 PseudoVFMACC_VFPR64_M1_E64 = 1935,
1960 PseudoVFMACC_VFPR64_M1_E64_MASK = 1936,
1961 PseudoVFMACC_VFPR64_M2_E64 = 1937,
1962 PseudoVFMACC_VFPR64_M2_E64_MASK = 1938,
1963 PseudoVFMACC_VFPR64_M4_E64 = 1939,
1964 PseudoVFMACC_VFPR64_M4_E64_MASK = 1940,
1965 PseudoVFMACC_VFPR64_M8_E64 = 1941,
1966 PseudoVFMACC_VFPR64_M8_E64_MASK = 1942,
1967 PseudoVFMACC_VV_M1_E16 = 1943,
1968 PseudoVFMACC_VV_M1_E16_MASK = 1944,
1969 PseudoVFMACC_VV_M1_E32 = 1945,
1970 PseudoVFMACC_VV_M1_E32_MASK = 1946,
1971 PseudoVFMACC_VV_M1_E64 = 1947,
1972 PseudoVFMACC_VV_M1_E64_MASK = 1948,
1973 PseudoVFMACC_VV_M2_E16 = 1949,
1974 PseudoVFMACC_VV_M2_E16_MASK = 1950,
1975 PseudoVFMACC_VV_M2_E32 = 1951,
1976 PseudoVFMACC_VV_M2_E32_MASK = 1952,
1977 PseudoVFMACC_VV_M2_E64 = 1953,
1978 PseudoVFMACC_VV_M2_E64_MASK = 1954,
1979 PseudoVFMACC_VV_M4_E16 = 1955,
1980 PseudoVFMACC_VV_M4_E16_MASK = 1956,
1981 PseudoVFMACC_VV_M4_E32 = 1957,
1982 PseudoVFMACC_VV_M4_E32_MASK = 1958,
1983 PseudoVFMACC_VV_M4_E64 = 1959,
1984 PseudoVFMACC_VV_M4_E64_MASK = 1960,
1985 PseudoVFMACC_VV_M8_E16 = 1961,
1986 PseudoVFMACC_VV_M8_E16_MASK = 1962,
1987 PseudoVFMACC_VV_M8_E32 = 1963,
1988 PseudoVFMACC_VV_M8_E32_MASK = 1964,
1989 PseudoVFMACC_VV_M8_E64 = 1965,
1990 PseudoVFMACC_VV_M8_E64_MASK = 1966,
1991 PseudoVFMACC_VV_MF2_E16 = 1967,
1992 PseudoVFMACC_VV_MF2_E16_MASK = 1968,
1993 PseudoVFMACC_VV_MF2_E32 = 1969,
1994 PseudoVFMACC_VV_MF2_E32_MASK = 1970,
1995 PseudoVFMACC_VV_MF4_E16 = 1971,
1996 PseudoVFMACC_VV_MF4_E16_MASK = 1972,
1997 PseudoVFMADD_VFPR16_M1_E16 = 1973,
1998 PseudoVFMADD_VFPR16_M1_E16_MASK = 1974,
1999 PseudoVFMADD_VFPR16_M2_E16 = 1975,
2000 PseudoVFMADD_VFPR16_M2_E16_MASK = 1976,
2001 PseudoVFMADD_VFPR16_M4_E16 = 1977,
2002 PseudoVFMADD_VFPR16_M4_E16_MASK = 1978,
2003 PseudoVFMADD_VFPR16_M8_E16 = 1979,
2004 PseudoVFMADD_VFPR16_M8_E16_MASK = 1980,
2005 PseudoVFMADD_VFPR16_MF2_E16 = 1981,
2006 PseudoVFMADD_VFPR16_MF2_E16_MASK = 1982,
2007 PseudoVFMADD_VFPR16_MF4_E16 = 1983,
2008 PseudoVFMADD_VFPR16_MF4_E16_MASK = 1984,
2009 PseudoVFMADD_VFPR32_M1_E32 = 1985,
2010 PseudoVFMADD_VFPR32_M1_E32_MASK = 1986,
2011 PseudoVFMADD_VFPR32_M2_E32 = 1987,
2012 PseudoVFMADD_VFPR32_M2_E32_MASK = 1988,
2013 PseudoVFMADD_VFPR32_M4_E32 = 1989,
2014 PseudoVFMADD_VFPR32_M4_E32_MASK = 1990,
2015 PseudoVFMADD_VFPR32_M8_E32 = 1991,
2016 PseudoVFMADD_VFPR32_M8_E32_MASK = 1992,
2017 PseudoVFMADD_VFPR32_MF2_E32 = 1993,
2018 PseudoVFMADD_VFPR32_MF2_E32_MASK = 1994,
2019 PseudoVFMADD_VFPR64_M1_E64 = 1995,
2020 PseudoVFMADD_VFPR64_M1_E64_MASK = 1996,
2021 PseudoVFMADD_VFPR64_M2_E64 = 1997,
2022 PseudoVFMADD_VFPR64_M2_E64_MASK = 1998,
2023 PseudoVFMADD_VFPR64_M4_E64 = 1999,
2024 PseudoVFMADD_VFPR64_M4_E64_MASK = 2000,
2025 PseudoVFMADD_VFPR64_M8_E64 = 2001,
2026 PseudoVFMADD_VFPR64_M8_E64_MASK = 2002,
2027 PseudoVFMADD_VV_M1_E16 = 2003,
2028 PseudoVFMADD_VV_M1_E16_MASK = 2004,
2029 PseudoVFMADD_VV_M1_E32 = 2005,
2030 PseudoVFMADD_VV_M1_E32_MASK = 2006,
2031 PseudoVFMADD_VV_M1_E64 = 2007,
2032 PseudoVFMADD_VV_M1_E64_MASK = 2008,
2033 PseudoVFMADD_VV_M2_E16 = 2009,
2034 PseudoVFMADD_VV_M2_E16_MASK = 2010,
2035 PseudoVFMADD_VV_M2_E32 = 2011,
2036 PseudoVFMADD_VV_M2_E32_MASK = 2012,
2037 PseudoVFMADD_VV_M2_E64 = 2013,
2038 PseudoVFMADD_VV_M2_E64_MASK = 2014,
2039 PseudoVFMADD_VV_M4_E16 = 2015,
2040 PseudoVFMADD_VV_M4_E16_MASK = 2016,
2041 PseudoVFMADD_VV_M4_E32 = 2017,
2042 PseudoVFMADD_VV_M4_E32_MASK = 2018,
2043 PseudoVFMADD_VV_M4_E64 = 2019,
2044 PseudoVFMADD_VV_M4_E64_MASK = 2020,
2045 PseudoVFMADD_VV_M8_E16 = 2021,
2046 PseudoVFMADD_VV_M8_E16_MASK = 2022,
2047 PseudoVFMADD_VV_M8_E32 = 2023,
2048 PseudoVFMADD_VV_M8_E32_MASK = 2024,
2049 PseudoVFMADD_VV_M8_E64 = 2025,
2050 PseudoVFMADD_VV_M8_E64_MASK = 2026,
2051 PseudoVFMADD_VV_MF2_E16 = 2027,
2052 PseudoVFMADD_VV_MF2_E16_MASK = 2028,
2053 PseudoVFMADD_VV_MF2_E32 = 2029,
2054 PseudoVFMADD_VV_MF2_E32_MASK = 2030,
2055 PseudoVFMADD_VV_MF4_E16 = 2031,
2056 PseudoVFMADD_VV_MF4_E16_MASK = 2032,
2057 PseudoVFMAX_VFPR16_M1_E16 = 2033,
2058 PseudoVFMAX_VFPR16_M1_E16_MASK = 2034,
2059 PseudoVFMAX_VFPR16_M2_E16 = 2035,
2060 PseudoVFMAX_VFPR16_M2_E16_MASK = 2036,
2061 PseudoVFMAX_VFPR16_M4_E16 = 2037,
2062 PseudoVFMAX_VFPR16_M4_E16_MASK = 2038,
2063 PseudoVFMAX_VFPR16_M8_E16 = 2039,
2064 PseudoVFMAX_VFPR16_M8_E16_MASK = 2040,
2065 PseudoVFMAX_VFPR16_MF2_E16 = 2041,
2066 PseudoVFMAX_VFPR16_MF2_E16_MASK = 2042,
2067 PseudoVFMAX_VFPR16_MF4_E16 = 2043,
2068 PseudoVFMAX_VFPR16_MF4_E16_MASK = 2044,
2069 PseudoVFMAX_VFPR32_M1_E32 = 2045,
2070 PseudoVFMAX_VFPR32_M1_E32_MASK = 2046,
2071 PseudoVFMAX_VFPR32_M2_E32 = 2047,
2072 PseudoVFMAX_VFPR32_M2_E32_MASK = 2048,
2073 PseudoVFMAX_VFPR32_M4_E32 = 2049,
2074 PseudoVFMAX_VFPR32_M4_E32_MASK = 2050,
2075 PseudoVFMAX_VFPR32_M8_E32 = 2051,
2076 PseudoVFMAX_VFPR32_M8_E32_MASK = 2052,
2077 PseudoVFMAX_VFPR32_MF2_E32 = 2053,
2078 PseudoVFMAX_VFPR32_MF2_E32_MASK = 2054,
2079 PseudoVFMAX_VFPR64_M1_E64 = 2055,
2080 PseudoVFMAX_VFPR64_M1_E64_MASK = 2056,
2081 PseudoVFMAX_VFPR64_M2_E64 = 2057,
2082 PseudoVFMAX_VFPR64_M2_E64_MASK = 2058,
2083 PseudoVFMAX_VFPR64_M4_E64 = 2059,
2084 PseudoVFMAX_VFPR64_M4_E64_MASK = 2060,
2085 PseudoVFMAX_VFPR64_M8_E64 = 2061,
2086 PseudoVFMAX_VFPR64_M8_E64_MASK = 2062,
2087 PseudoVFMAX_VV_M1_E16 = 2063,
2088 PseudoVFMAX_VV_M1_E16_MASK = 2064,
2089 PseudoVFMAX_VV_M1_E32 = 2065,
2090 PseudoVFMAX_VV_M1_E32_MASK = 2066,
2091 PseudoVFMAX_VV_M1_E64 = 2067,
2092 PseudoVFMAX_VV_M1_E64_MASK = 2068,
2093 PseudoVFMAX_VV_M2_E16 = 2069,
2094 PseudoVFMAX_VV_M2_E16_MASK = 2070,
2095 PseudoVFMAX_VV_M2_E32 = 2071,
2096 PseudoVFMAX_VV_M2_E32_MASK = 2072,
2097 PseudoVFMAX_VV_M2_E64 = 2073,
2098 PseudoVFMAX_VV_M2_E64_MASK = 2074,
2099 PseudoVFMAX_VV_M4_E16 = 2075,
2100 PseudoVFMAX_VV_M4_E16_MASK = 2076,
2101 PseudoVFMAX_VV_M4_E32 = 2077,
2102 PseudoVFMAX_VV_M4_E32_MASK = 2078,
2103 PseudoVFMAX_VV_M4_E64 = 2079,
2104 PseudoVFMAX_VV_M4_E64_MASK = 2080,
2105 PseudoVFMAX_VV_M8_E16 = 2081,
2106 PseudoVFMAX_VV_M8_E16_MASK = 2082,
2107 PseudoVFMAX_VV_M8_E32 = 2083,
2108 PseudoVFMAX_VV_M8_E32_MASK = 2084,
2109 PseudoVFMAX_VV_M8_E64 = 2085,
2110 PseudoVFMAX_VV_M8_E64_MASK = 2086,
2111 PseudoVFMAX_VV_MF2_E16 = 2087,
2112 PseudoVFMAX_VV_MF2_E16_MASK = 2088,
2113 PseudoVFMAX_VV_MF2_E32 = 2089,
2114 PseudoVFMAX_VV_MF2_E32_MASK = 2090,
2115 PseudoVFMAX_VV_MF4_E16 = 2091,
2116 PseudoVFMAX_VV_MF4_E16_MASK = 2092,
2117 PseudoVFMERGE_VFPR16M_M1 = 2093,
2118 PseudoVFMERGE_VFPR16M_M2 = 2094,
2119 PseudoVFMERGE_VFPR16M_M4 = 2095,
2120 PseudoVFMERGE_VFPR16M_M8 = 2096,
2121 PseudoVFMERGE_VFPR16M_MF2 = 2097,
2122 PseudoVFMERGE_VFPR16M_MF4 = 2098,
2123 PseudoVFMERGE_VFPR32M_M1 = 2099,
2124 PseudoVFMERGE_VFPR32M_M2 = 2100,
2125 PseudoVFMERGE_VFPR32M_M4 = 2101,
2126 PseudoVFMERGE_VFPR32M_M8 = 2102,
2127 PseudoVFMERGE_VFPR32M_MF2 = 2103,
2128 PseudoVFMERGE_VFPR64M_M1 = 2104,
2129 PseudoVFMERGE_VFPR64M_M2 = 2105,
2130 PseudoVFMERGE_VFPR64M_M4 = 2106,
2131 PseudoVFMERGE_VFPR64M_M8 = 2107,
2132 PseudoVFMIN_VFPR16_M1_E16 = 2108,
2133 PseudoVFMIN_VFPR16_M1_E16_MASK = 2109,
2134 PseudoVFMIN_VFPR16_M2_E16 = 2110,
2135 PseudoVFMIN_VFPR16_M2_E16_MASK = 2111,
2136 PseudoVFMIN_VFPR16_M4_E16 = 2112,
2137 PseudoVFMIN_VFPR16_M4_E16_MASK = 2113,
2138 PseudoVFMIN_VFPR16_M8_E16 = 2114,
2139 PseudoVFMIN_VFPR16_M8_E16_MASK = 2115,
2140 PseudoVFMIN_VFPR16_MF2_E16 = 2116,
2141 PseudoVFMIN_VFPR16_MF2_E16_MASK = 2117,
2142 PseudoVFMIN_VFPR16_MF4_E16 = 2118,
2143 PseudoVFMIN_VFPR16_MF4_E16_MASK = 2119,
2144 PseudoVFMIN_VFPR32_M1_E32 = 2120,
2145 PseudoVFMIN_VFPR32_M1_E32_MASK = 2121,
2146 PseudoVFMIN_VFPR32_M2_E32 = 2122,
2147 PseudoVFMIN_VFPR32_M2_E32_MASK = 2123,
2148 PseudoVFMIN_VFPR32_M4_E32 = 2124,
2149 PseudoVFMIN_VFPR32_M4_E32_MASK = 2125,
2150 PseudoVFMIN_VFPR32_M8_E32 = 2126,
2151 PseudoVFMIN_VFPR32_M8_E32_MASK = 2127,
2152 PseudoVFMIN_VFPR32_MF2_E32 = 2128,
2153 PseudoVFMIN_VFPR32_MF2_E32_MASK = 2129,
2154 PseudoVFMIN_VFPR64_M1_E64 = 2130,
2155 PseudoVFMIN_VFPR64_M1_E64_MASK = 2131,
2156 PseudoVFMIN_VFPR64_M2_E64 = 2132,
2157 PseudoVFMIN_VFPR64_M2_E64_MASK = 2133,
2158 PseudoVFMIN_VFPR64_M4_E64 = 2134,
2159 PseudoVFMIN_VFPR64_M4_E64_MASK = 2135,
2160 PseudoVFMIN_VFPR64_M8_E64 = 2136,
2161 PseudoVFMIN_VFPR64_M8_E64_MASK = 2137,
2162 PseudoVFMIN_VV_M1_E16 = 2138,
2163 PseudoVFMIN_VV_M1_E16_MASK = 2139,
2164 PseudoVFMIN_VV_M1_E32 = 2140,
2165 PseudoVFMIN_VV_M1_E32_MASK = 2141,
2166 PseudoVFMIN_VV_M1_E64 = 2142,
2167 PseudoVFMIN_VV_M1_E64_MASK = 2143,
2168 PseudoVFMIN_VV_M2_E16 = 2144,
2169 PseudoVFMIN_VV_M2_E16_MASK = 2145,
2170 PseudoVFMIN_VV_M2_E32 = 2146,
2171 PseudoVFMIN_VV_M2_E32_MASK = 2147,
2172 PseudoVFMIN_VV_M2_E64 = 2148,
2173 PseudoVFMIN_VV_M2_E64_MASK = 2149,
2174 PseudoVFMIN_VV_M4_E16 = 2150,
2175 PseudoVFMIN_VV_M4_E16_MASK = 2151,
2176 PseudoVFMIN_VV_M4_E32 = 2152,
2177 PseudoVFMIN_VV_M4_E32_MASK = 2153,
2178 PseudoVFMIN_VV_M4_E64 = 2154,
2179 PseudoVFMIN_VV_M4_E64_MASK = 2155,
2180 PseudoVFMIN_VV_M8_E16 = 2156,
2181 PseudoVFMIN_VV_M8_E16_MASK = 2157,
2182 PseudoVFMIN_VV_M8_E32 = 2158,
2183 PseudoVFMIN_VV_M8_E32_MASK = 2159,
2184 PseudoVFMIN_VV_M8_E64 = 2160,
2185 PseudoVFMIN_VV_M8_E64_MASK = 2161,
2186 PseudoVFMIN_VV_MF2_E16 = 2162,
2187 PseudoVFMIN_VV_MF2_E16_MASK = 2163,
2188 PseudoVFMIN_VV_MF2_E32 = 2164,
2189 PseudoVFMIN_VV_MF2_E32_MASK = 2165,
2190 PseudoVFMIN_VV_MF4_E16 = 2166,
2191 PseudoVFMIN_VV_MF4_E16_MASK = 2167,
2192 PseudoVFMSAC_VFPR16_M1_E16 = 2168,
2193 PseudoVFMSAC_VFPR16_M1_E16_MASK = 2169,
2194 PseudoVFMSAC_VFPR16_M2_E16 = 2170,
2195 PseudoVFMSAC_VFPR16_M2_E16_MASK = 2171,
2196 PseudoVFMSAC_VFPR16_M4_E16 = 2172,
2197 PseudoVFMSAC_VFPR16_M4_E16_MASK = 2173,
2198 PseudoVFMSAC_VFPR16_M8_E16 = 2174,
2199 PseudoVFMSAC_VFPR16_M8_E16_MASK = 2175,
2200 PseudoVFMSAC_VFPR16_MF2_E16 = 2176,
2201 PseudoVFMSAC_VFPR16_MF2_E16_MASK = 2177,
2202 PseudoVFMSAC_VFPR16_MF4_E16 = 2178,
2203 PseudoVFMSAC_VFPR16_MF4_E16_MASK = 2179,
2204 PseudoVFMSAC_VFPR32_M1_E32 = 2180,
2205 PseudoVFMSAC_VFPR32_M1_E32_MASK = 2181,
2206 PseudoVFMSAC_VFPR32_M2_E32 = 2182,
2207 PseudoVFMSAC_VFPR32_M2_E32_MASK = 2183,
2208 PseudoVFMSAC_VFPR32_M4_E32 = 2184,
2209 PseudoVFMSAC_VFPR32_M4_E32_MASK = 2185,
2210 PseudoVFMSAC_VFPR32_M8_E32 = 2186,
2211 PseudoVFMSAC_VFPR32_M8_E32_MASK = 2187,
2212 PseudoVFMSAC_VFPR32_MF2_E32 = 2188,
2213 PseudoVFMSAC_VFPR32_MF2_E32_MASK = 2189,
2214 PseudoVFMSAC_VFPR64_M1_E64 = 2190,
2215 PseudoVFMSAC_VFPR64_M1_E64_MASK = 2191,
2216 PseudoVFMSAC_VFPR64_M2_E64 = 2192,
2217 PseudoVFMSAC_VFPR64_M2_E64_MASK = 2193,
2218 PseudoVFMSAC_VFPR64_M4_E64 = 2194,
2219 PseudoVFMSAC_VFPR64_M4_E64_MASK = 2195,
2220 PseudoVFMSAC_VFPR64_M8_E64 = 2196,
2221 PseudoVFMSAC_VFPR64_M8_E64_MASK = 2197,
2222 PseudoVFMSAC_VV_M1_E16 = 2198,
2223 PseudoVFMSAC_VV_M1_E16_MASK = 2199,
2224 PseudoVFMSAC_VV_M1_E32 = 2200,
2225 PseudoVFMSAC_VV_M1_E32_MASK = 2201,
2226 PseudoVFMSAC_VV_M1_E64 = 2202,
2227 PseudoVFMSAC_VV_M1_E64_MASK = 2203,
2228 PseudoVFMSAC_VV_M2_E16 = 2204,
2229 PseudoVFMSAC_VV_M2_E16_MASK = 2205,
2230 PseudoVFMSAC_VV_M2_E32 = 2206,
2231 PseudoVFMSAC_VV_M2_E32_MASK = 2207,
2232 PseudoVFMSAC_VV_M2_E64 = 2208,
2233 PseudoVFMSAC_VV_M2_E64_MASK = 2209,
2234 PseudoVFMSAC_VV_M4_E16 = 2210,
2235 PseudoVFMSAC_VV_M4_E16_MASK = 2211,
2236 PseudoVFMSAC_VV_M4_E32 = 2212,
2237 PseudoVFMSAC_VV_M4_E32_MASK = 2213,
2238 PseudoVFMSAC_VV_M4_E64 = 2214,
2239 PseudoVFMSAC_VV_M4_E64_MASK = 2215,
2240 PseudoVFMSAC_VV_M8_E16 = 2216,
2241 PseudoVFMSAC_VV_M8_E16_MASK = 2217,
2242 PseudoVFMSAC_VV_M8_E32 = 2218,
2243 PseudoVFMSAC_VV_M8_E32_MASK = 2219,
2244 PseudoVFMSAC_VV_M8_E64 = 2220,
2245 PseudoVFMSAC_VV_M8_E64_MASK = 2221,
2246 PseudoVFMSAC_VV_MF2_E16 = 2222,
2247 PseudoVFMSAC_VV_MF2_E16_MASK = 2223,
2248 PseudoVFMSAC_VV_MF2_E32 = 2224,
2249 PseudoVFMSAC_VV_MF2_E32_MASK = 2225,
2250 PseudoVFMSAC_VV_MF4_E16 = 2226,
2251 PseudoVFMSAC_VV_MF4_E16_MASK = 2227,
2252 PseudoVFMSUB_VFPR16_M1_E16 = 2228,
2253 PseudoVFMSUB_VFPR16_M1_E16_MASK = 2229,
2254 PseudoVFMSUB_VFPR16_M2_E16 = 2230,
2255 PseudoVFMSUB_VFPR16_M2_E16_MASK = 2231,
2256 PseudoVFMSUB_VFPR16_M4_E16 = 2232,
2257 PseudoVFMSUB_VFPR16_M4_E16_MASK = 2233,
2258 PseudoVFMSUB_VFPR16_M8_E16 = 2234,
2259 PseudoVFMSUB_VFPR16_M8_E16_MASK = 2235,
2260 PseudoVFMSUB_VFPR16_MF2_E16 = 2236,
2261 PseudoVFMSUB_VFPR16_MF2_E16_MASK = 2237,
2262 PseudoVFMSUB_VFPR16_MF4_E16 = 2238,
2263 PseudoVFMSUB_VFPR16_MF4_E16_MASK = 2239,
2264 PseudoVFMSUB_VFPR32_M1_E32 = 2240,
2265 PseudoVFMSUB_VFPR32_M1_E32_MASK = 2241,
2266 PseudoVFMSUB_VFPR32_M2_E32 = 2242,
2267 PseudoVFMSUB_VFPR32_M2_E32_MASK = 2243,
2268 PseudoVFMSUB_VFPR32_M4_E32 = 2244,
2269 PseudoVFMSUB_VFPR32_M4_E32_MASK = 2245,
2270 PseudoVFMSUB_VFPR32_M8_E32 = 2246,
2271 PseudoVFMSUB_VFPR32_M8_E32_MASK = 2247,
2272 PseudoVFMSUB_VFPR32_MF2_E32 = 2248,
2273 PseudoVFMSUB_VFPR32_MF2_E32_MASK = 2249,
2274 PseudoVFMSUB_VFPR64_M1_E64 = 2250,
2275 PseudoVFMSUB_VFPR64_M1_E64_MASK = 2251,
2276 PseudoVFMSUB_VFPR64_M2_E64 = 2252,
2277 PseudoVFMSUB_VFPR64_M2_E64_MASK = 2253,
2278 PseudoVFMSUB_VFPR64_M4_E64 = 2254,
2279 PseudoVFMSUB_VFPR64_M4_E64_MASK = 2255,
2280 PseudoVFMSUB_VFPR64_M8_E64 = 2256,
2281 PseudoVFMSUB_VFPR64_M8_E64_MASK = 2257,
2282 PseudoVFMSUB_VV_M1_E16 = 2258,
2283 PseudoVFMSUB_VV_M1_E16_MASK = 2259,
2284 PseudoVFMSUB_VV_M1_E32 = 2260,
2285 PseudoVFMSUB_VV_M1_E32_MASK = 2261,
2286 PseudoVFMSUB_VV_M1_E64 = 2262,
2287 PseudoVFMSUB_VV_M1_E64_MASK = 2263,
2288 PseudoVFMSUB_VV_M2_E16 = 2264,
2289 PseudoVFMSUB_VV_M2_E16_MASK = 2265,
2290 PseudoVFMSUB_VV_M2_E32 = 2266,
2291 PseudoVFMSUB_VV_M2_E32_MASK = 2267,
2292 PseudoVFMSUB_VV_M2_E64 = 2268,
2293 PseudoVFMSUB_VV_M2_E64_MASK = 2269,
2294 PseudoVFMSUB_VV_M4_E16 = 2270,
2295 PseudoVFMSUB_VV_M4_E16_MASK = 2271,
2296 PseudoVFMSUB_VV_M4_E32 = 2272,
2297 PseudoVFMSUB_VV_M4_E32_MASK = 2273,
2298 PseudoVFMSUB_VV_M4_E64 = 2274,
2299 PseudoVFMSUB_VV_M4_E64_MASK = 2275,
2300 PseudoVFMSUB_VV_M8_E16 = 2276,
2301 PseudoVFMSUB_VV_M8_E16_MASK = 2277,
2302 PseudoVFMSUB_VV_M8_E32 = 2278,
2303 PseudoVFMSUB_VV_M8_E32_MASK = 2279,
2304 PseudoVFMSUB_VV_M8_E64 = 2280,
2305 PseudoVFMSUB_VV_M8_E64_MASK = 2281,
2306 PseudoVFMSUB_VV_MF2_E16 = 2282,
2307 PseudoVFMSUB_VV_MF2_E16_MASK = 2283,
2308 PseudoVFMSUB_VV_MF2_E32 = 2284,
2309 PseudoVFMSUB_VV_MF2_E32_MASK = 2285,
2310 PseudoVFMSUB_VV_MF4_E16 = 2286,
2311 PseudoVFMSUB_VV_MF4_E16_MASK = 2287,
2312 PseudoVFMUL_VFPR16_M1_E16 = 2288,
2313 PseudoVFMUL_VFPR16_M1_E16_MASK = 2289,
2314 PseudoVFMUL_VFPR16_M2_E16 = 2290,
2315 PseudoVFMUL_VFPR16_M2_E16_MASK = 2291,
2316 PseudoVFMUL_VFPR16_M4_E16 = 2292,
2317 PseudoVFMUL_VFPR16_M4_E16_MASK = 2293,
2318 PseudoVFMUL_VFPR16_M8_E16 = 2294,
2319 PseudoVFMUL_VFPR16_M8_E16_MASK = 2295,
2320 PseudoVFMUL_VFPR16_MF2_E16 = 2296,
2321 PseudoVFMUL_VFPR16_MF2_E16_MASK = 2297,
2322 PseudoVFMUL_VFPR16_MF4_E16 = 2298,
2323 PseudoVFMUL_VFPR16_MF4_E16_MASK = 2299,
2324 PseudoVFMUL_VFPR32_M1_E32 = 2300,
2325 PseudoVFMUL_VFPR32_M1_E32_MASK = 2301,
2326 PseudoVFMUL_VFPR32_M2_E32 = 2302,
2327 PseudoVFMUL_VFPR32_M2_E32_MASK = 2303,
2328 PseudoVFMUL_VFPR32_M4_E32 = 2304,
2329 PseudoVFMUL_VFPR32_M4_E32_MASK = 2305,
2330 PseudoVFMUL_VFPR32_M8_E32 = 2306,
2331 PseudoVFMUL_VFPR32_M8_E32_MASK = 2307,
2332 PseudoVFMUL_VFPR32_MF2_E32 = 2308,
2333 PseudoVFMUL_VFPR32_MF2_E32_MASK = 2309,
2334 PseudoVFMUL_VFPR64_M1_E64 = 2310,
2335 PseudoVFMUL_VFPR64_M1_E64_MASK = 2311,
2336 PseudoVFMUL_VFPR64_M2_E64 = 2312,
2337 PseudoVFMUL_VFPR64_M2_E64_MASK = 2313,
2338 PseudoVFMUL_VFPR64_M4_E64 = 2314,
2339 PseudoVFMUL_VFPR64_M4_E64_MASK = 2315,
2340 PseudoVFMUL_VFPR64_M8_E64 = 2316,
2341 PseudoVFMUL_VFPR64_M8_E64_MASK = 2317,
2342 PseudoVFMUL_VV_M1_E16 = 2318,
2343 PseudoVFMUL_VV_M1_E16_MASK = 2319,
2344 PseudoVFMUL_VV_M1_E32 = 2320,
2345 PseudoVFMUL_VV_M1_E32_MASK = 2321,
2346 PseudoVFMUL_VV_M1_E64 = 2322,
2347 PseudoVFMUL_VV_M1_E64_MASK = 2323,
2348 PseudoVFMUL_VV_M2_E16 = 2324,
2349 PseudoVFMUL_VV_M2_E16_MASK = 2325,
2350 PseudoVFMUL_VV_M2_E32 = 2326,
2351 PseudoVFMUL_VV_M2_E32_MASK = 2327,
2352 PseudoVFMUL_VV_M2_E64 = 2328,
2353 PseudoVFMUL_VV_M2_E64_MASK = 2329,
2354 PseudoVFMUL_VV_M4_E16 = 2330,
2355 PseudoVFMUL_VV_M4_E16_MASK = 2331,
2356 PseudoVFMUL_VV_M4_E32 = 2332,
2357 PseudoVFMUL_VV_M4_E32_MASK = 2333,
2358 PseudoVFMUL_VV_M4_E64 = 2334,
2359 PseudoVFMUL_VV_M4_E64_MASK = 2335,
2360 PseudoVFMUL_VV_M8_E16 = 2336,
2361 PseudoVFMUL_VV_M8_E16_MASK = 2337,
2362 PseudoVFMUL_VV_M8_E32 = 2338,
2363 PseudoVFMUL_VV_M8_E32_MASK = 2339,
2364 PseudoVFMUL_VV_M8_E64 = 2340,
2365 PseudoVFMUL_VV_M8_E64_MASK = 2341,
2366 PseudoVFMUL_VV_MF2_E16 = 2342,
2367 PseudoVFMUL_VV_MF2_E16_MASK = 2343,
2368 PseudoVFMUL_VV_MF2_E32 = 2344,
2369 PseudoVFMUL_VV_MF2_E32_MASK = 2345,
2370 PseudoVFMUL_VV_MF4_E16 = 2346,
2371 PseudoVFMUL_VV_MF4_E16_MASK = 2347,
2372 PseudoVFMV_FPR16_S_M1 = 2348,
2373 PseudoVFMV_FPR16_S_M2 = 2349,
2374 PseudoVFMV_FPR16_S_M4 = 2350,
2375 PseudoVFMV_FPR16_S_M8 = 2351,
2376 PseudoVFMV_FPR16_S_MF2 = 2352,
2377 PseudoVFMV_FPR16_S_MF4 = 2353,
2378 PseudoVFMV_FPR32_S_M1 = 2354,
2379 PseudoVFMV_FPR32_S_M2 = 2355,
2380 PseudoVFMV_FPR32_S_M4 = 2356,
2381 PseudoVFMV_FPR32_S_M8 = 2357,
2382 PseudoVFMV_FPR32_S_MF2 = 2358,
2383 PseudoVFMV_FPR64_S_M1 = 2359,
2384 PseudoVFMV_FPR64_S_M2 = 2360,
2385 PseudoVFMV_FPR64_S_M4 = 2361,
2386 PseudoVFMV_FPR64_S_M8 = 2362,
2387 PseudoVFMV_S_FPR16_M1 = 2363,
2388 PseudoVFMV_S_FPR16_M2 = 2364,
2389 PseudoVFMV_S_FPR16_M4 = 2365,
2390 PseudoVFMV_S_FPR16_M8 = 2366,
2391 PseudoVFMV_S_FPR16_MF2 = 2367,
2392 PseudoVFMV_S_FPR16_MF4 = 2368,
2393 PseudoVFMV_S_FPR32_M1 = 2369,
2394 PseudoVFMV_S_FPR32_M2 = 2370,
2395 PseudoVFMV_S_FPR32_M4 = 2371,
2396 PseudoVFMV_S_FPR32_M8 = 2372,
2397 PseudoVFMV_S_FPR32_MF2 = 2373,
2398 PseudoVFMV_S_FPR64_M1 = 2374,
2399 PseudoVFMV_S_FPR64_M2 = 2375,
2400 PseudoVFMV_S_FPR64_M4 = 2376,
2401 PseudoVFMV_S_FPR64_M8 = 2377,
2402 PseudoVFMV_V_FPR16_M1 = 2378,
2403 PseudoVFMV_V_FPR16_M2 = 2379,
2404 PseudoVFMV_V_FPR16_M4 = 2380,
2405 PseudoVFMV_V_FPR16_M8 = 2381,
2406 PseudoVFMV_V_FPR16_MF2 = 2382,
2407 PseudoVFMV_V_FPR16_MF4 = 2383,
2408 PseudoVFMV_V_FPR32_M1 = 2384,
2409 PseudoVFMV_V_FPR32_M2 = 2385,
2410 PseudoVFMV_V_FPR32_M4 = 2386,
2411 PseudoVFMV_V_FPR32_M8 = 2387,
2412 PseudoVFMV_V_FPR32_MF2 = 2388,
2413 PseudoVFMV_V_FPR64_M1 = 2389,
2414 PseudoVFMV_V_FPR64_M2 = 2390,
2415 PseudoVFMV_V_FPR64_M4 = 2391,
2416 PseudoVFMV_V_FPR64_M8 = 2392,
2417 PseudoVFNCVTBF16_F_F_W_M1_E16 = 2393,
2418 PseudoVFNCVTBF16_F_F_W_M1_E16_MASK = 2394,
2419 PseudoVFNCVTBF16_F_F_W_M1_E32 = 2395,
2420 PseudoVFNCVTBF16_F_F_W_M1_E32_MASK = 2396,
2421 PseudoVFNCVTBF16_F_F_W_M2_E16 = 2397,
2422 PseudoVFNCVTBF16_F_F_W_M2_E16_MASK = 2398,
2423 PseudoVFNCVTBF16_F_F_W_M2_E32 = 2399,
2424 PseudoVFNCVTBF16_F_F_W_M2_E32_MASK = 2400,
2425 PseudoVFNCVTBF16_F_F_W_M4_E16 = 2401,
2426 PseudoVFNCVTBF16_F_F_W_M4_E16_MASK = 2402,
2427 PseudoVFNCVTBF16_F_F_W_M4_E32 = 2403,
2428 PseudoVFNCVTBF16_F_F_W_M4_E32_MASK = 2404,
2429 PseudoVFNCVTBF16_F_F_W_MF2_E16 = 2405,
2430 PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK = 2406,
2431 PseudoVFNCVTBF16_F_F_W_MF2_E32 = 2407,
2432 PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK = 2408,
2433 PseudoVFNCVTBF16_F_F_W_MF4_E16 = 2409,
2434 PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK = 2410,
2435 PseudoVFNCVT_F_F_W_M1_E16 = 2411,
2436 PseudoVFNCVT_F_F_W_M1_E16_MASK = 2412,
2437 PseudoVFNCVT_F_F_W_M1_E32 = 2413,
2438 PseudoVFNCVT_F_F_W_M1_E32_MASK = 2414,
2439 PseudoVFNCVT_F_F_W_M2_E16 = 2415,
2440 PseudoVFNCVT_F_F_W_M2_E16_MASK = 2416,
2441 PseudoVFNCVT_F_F_W_M2_E32 = 2417,
2442 PseudoVFNCVT_F_F_W_M2_E32_MASK = 2418,
2443 PseudoVFNCVT_F_F_W_M4_E16 = 2419,
2444 PseudoVFNCVT_F_F_W_M4_E16_MASK = 2420,
2445 PseudoVFNCVT_F_F_W_M4_E32 = 2421,
2446 PseudoVFNCVT_F_F_W_M4_E32_MASK = 2422,
2447 PseudoVFNCVT_F_F_W_MF2_E16 = 2423,
2448 PseudoVFNCVT_F_F_W_MF2_E16_MASK = 2424,
2449 PseudoVFNCVT_F_F_W_MF2_E32 = 2425,
2450 PseudoVFNCVT_F_F_W_MF2_E32_MASK = 2426,
2451 PseudoVFNCVT_F_F_W_MF4_E16 = 2427,
2452 PseudoVFNCVT_F_F_W_MF4_E16_MASK = 2428,
2453 PseudoVFNCVT_F_XU_W_M1_E16 = 2429,
2454 PseudoVFNCVT_F_XU_W_M1_E16_MASK = 2430,
2455 PseudoVFNCVT_F_XU_W_M1_E32 = 2431,
2456 PseudoVFNCVT_F_XU_W_M1_E32_MASK = 2432,
2457 PseudoVFNCVT_F_XU_W_M2_E16 = 2433,
2458 PseudoVFNCVT_F_XU_W_M2_E16_MASK = 2434,
2459 PseudoVFNCVT_F_XU_W_M2_E32 = 2435,
2460 PseudoVFNCVT_F_XU_W_M2_E32_MASK = 2436,
2461 PseudoVFNCVT_F_XU_W_M4_E16 = 2437,
2462 PseudoVFNCVT_F_XU_W_M4_E16_MASK = 2438,
2463 PseudoVFNCVT_F_XU_W_M4_E32 = 2439,
2464 PseudoVFNCVT_F_XU_W_M4_E32_MASK = 2440,
2465 PseudoVFNCVT_F_XU_W_MF2_E16 = 2441,
2466 PseudoVFNCVT_F_XU_W_MF2_E16_MASK = 2442,
2467 PseudoVFNCVT_F_XU_W_MF2_E32 = 2443,
2468 PseudoVFNCVT_F_XU_W_MF2_E32_MASK = 2444,
2469 PseudoVFNCVT_F_XU_W_MF4_E16 = 2445,
2470 PseudoVFNCVT_F_XU_W_MF4_E16_MASK = 2446,
2471 PseudoVFNCVT_F_X_W_M1_E16 = 2447,
2472 PseudoVFNCVT_F_X_W_M1_E16_MASK = 2448,
2473 PseudoVFNCVT_F_X_W_M1_E32 = 2449,
2474 PseudoVFNCVT_F_X_W_M1_E32_MASK = 2450,
2475 PseudoVFNCVT_F_X_W_M2_E16 = 2451,
2476 PseudoVFNCVT_F_X_W_M2_E16_MASK = 2452,
2477 PseudoVFNCVT_F_X_W_M2_E32 = 2453,
2478 PseudoVFNCVT_F_X_W_M2_E32_MASK = 2454,
2479 PseudoVFNCVT_F_X_W_M4_E16 = 2455,
2480 PseudoVFNCVT_F_X_W_M4_E16_MASK = 2456,
2481 PseudoVFNCVT_F_X_W_M4_E32 = 2457,
2482 PseudoVFNCVT_F_X_W_M4_E32_MASK = 2458,
2483 PseudoVFNCVT_F_X_W_MF2_E16 = 2459,
2484 PseudoVFNCVT_F_X_W_MF2_E16_MASK = 2460,
2485 PseudoVFNCVT_F_X_W_MF2_E32 = 2461,
2486 PseudoVFNCVT_F_X_W_MF2_E32_MASK = 2462,
2487 PseudoVFNCVT_F_X_W_MF4_E16 = 2463,
2488 PseudoVFNCVT_F_X_W_MF4_E16_MASK = 2464,
2489 PseudoVFNCVT_RM_F_XU_W_M1_E16 = 2465,
2490 PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK = 2466,
2491 PseudoVFNCVT_RM_F_XU_W_M1_E32 = 2467,
2492 PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK = 2468,
2493 PseudoVFNCVT_RM_F_XU_W_M2_E16 = 2469,
2494 PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK = 2470,
2495 PseudoVFNCVT_RM_F_XU_W_M2_E32 = 2471,
2496 PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK = 2472,
2497 PseudoVFNCVT_RM_F_XU_W_M4_E16 = 2473,
2498 PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK = 2474,
2499 PseudoVFNCVT_RM_F_XU_W_M4_E32 = 2475,
2500 PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK = 2476,
2501 PseudoVFNCVT_RM_F_XU_W_MF2_E16 = 2477,
2502 PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK = 2478,
2503 PseudoVFNCVT_RM_F_XU_W_MF2_E32 = 2479,
2504 PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK = 2480,
2505 PseudoVFNCVT_RM_F_XU_W_MF4_E16 = 2481,
2506 PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK = 2482,
2507 PseudoVFNCVT_RM_F_X_W_M1_E16 = 2483,
2508 PseudoVFNCVT_RM_F_X_W_M1_E16_MASK = 2484,
2509 PseudoVFNCVT_RM_F_X_W_M1_E32 = 2485,
2510 PseudoVFNCVT_RM_F_X_W_M1_E32_MASK = 2486,
2511 PseudoVFNCVT_RM_F_X_W_M2_E16 = 2487,
2512 PseudoVFNCVT_RM_F_X_W_M2_E16_MASK = 2488,
2513 PseudoVFNCVT_RM_F_X_W_M2_E32 = 2489,
2514 PseudoVFNCVT_RM_F_X_W_M2_E32_MASK = 2490,
2515 PseudoVFNCVT_RM_F_X_W_M4_E16 = 2491,
2516 PseudoVFNCVT_RM_F_X_W_M4_E16_MASK = 2492,
2517 PseudoVFNCVT_RM_F_X_W_M4_E32 = 2493,
2518 PseudoVFNCVT_RM_F_X_W_M4_E32_MASK = 2494,
2519 PseudoVFNCVT_RM_F_X_W_MF2_E16 = 2495,
2520 PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK = 2496,
2521 PseudoVFNCVT_RM_F_X_W_MF2_E32 = 2497,
2522 PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK = 2498,
2523 PseudoVFNCVT_RM_F_X_W_MF4_E16 = 2499,
2524 PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK = 2500,
2525 PseudoVFNCVT_RM_XU_F_W_M1 = 2501,
2526 PseudoVFNCVT_RM_XU_F_W_M1_MASK = 2502,
2527 PseudoVFNCVT_RM_XU_F_W_M2 = 2503,
2528 PseudoVFNCVT_RM_XU_F_W_M2_MASK = 2504,
2529 PseudoVFNCVT_RM_XU_F_W_M4 = 2505,
2530 PseudoVFNCVT_RM_XU_F_W_M4_MASK = 2506,
2531 PseudoVFNCVT_RM_XU_F_W_MF2 = 2507,
2532 PseudoVFNCVT_RM_XU_F_W_MF2_MASK = 2508,
2533 PseudoVFNCVT_RM_XU_F_W_MF4 = 2509,
2534 PseudoVFNCVT_RM_XU_F_W_MF4_MASK = 2510,
2535 PseudoVFNCVT_RM_XU_F_W_MF8 = 2511,
2536 PseudoVFNCVT_RM_XU_F_W_MF8_MASK = 2512,
2537 PseudoVFNCVT_RM_X_F_W_M1 = 2513,
2538 PseudoVFNCVT_RM_X_F_W_M1_MASK = 2514,
2539 PseudoVFNCVT_RM_X_F_W_M2 = 2515,
2540 PseudoVFNCVT_RM_X_F_W_M2_MASK = 2516,
2541 PseudoVFNCVT_RM_X_F_W_M4 = 2517,
2542 PseudoVFNCVT_RM_X_F_W_M4_MASK = 2518,
2543 PseudoVFNCVT_RM_X_F_W_MF2 = 2519,
2544 PseudoVFNCVT_RM_X_F_W_MF2_MASK = 2520,
2545 PseudoVFNCVT_RM_X_F_W_MF4 = 2521,
2546 PseudoVFNCVT_RM_X_F_W_MF4_MASK = 2522,
2547 PseudoVFNCVT_RM_X_F_W_MF8 = 2523,
2548 PseudoVFNCVT_RM_X_F_W_MF8_MASK = 2524,
2549 PseudoVFNCVT_ROD_F_F_W_M1_E16 = 2525,
2550 PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK = 2526,
2551 PseudoVFNCVT_ROD_F_F_W_M1_E32 = 2527,
2552 PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK = 2528,
2553 PseudoVFNCVT_ROD_F_F_W_M2_E16 = 2529,
2554 PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK = 2530,
2555 PseudoVFNCVT_ROD_F_F_W_M2_E32 = 2531,
2556 PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK = 2532,
2557 PseudoVFNCVT_ROD_F_F_W_M4_E16 = 2533,
2558 PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK = 2534,
2559 PseudoVFNCVT_ROD_F_F_W_M4_E32 = 2535,
2560 PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK = 2536,
2561 PseudoVFNCVT_ROD_F_F_W_MF2_E16 = 2537,
2562 PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK = 2538,
2563 PseudoVFNCVT_ROD_F_F_W_MF2_E32 = 2539,
2564 PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK = 2540,
2565 PseudoVFNCVT_ROD_F_F_W_MF4_E16 = 2541,
2566 PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK = 2542,
2567 PseudoVFNCVT_RTZ_XU_F_W_M1 = 2543,
2568 PseudoVFNCVT_RTZ_XU_F_W_M1_MASK = 2544,
2569 PseudoVFNCVT_RTZ_XU_F_W_M2 = 2545,
2570 PseudoVFNCVT_RTZ_XU_F_W_M2_MASK = 2546,
2571 PseudoVFNCVT_RTZ_XU_F_W_M4 = 2547,
2572 PseudoVFNCVT_RTZ_XU_F_W_M4_MASK = 2548,
2573 PseudoVFNCVT_RTZ_XU_F_W_MF2 = 2549,
2574 PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK = 2550,
2575 PseudoVFNCVT_RTZ_XU_F_W_MF4 = 2551,
2576 PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK = 2552,
2577 PseudoVFNCVT_RTZ_XU_F_W_MF8 = 2553,
2578 PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK = 2554,
2579 PseudoVFNCVT_RTZ_X_F_W_M1 = 2555,
2580 PseudoVFNCVT_RTZ_X_F_W_M1_MASK = 2556,
2581 PseudoVFNCVT_RTZ_X_F_W_M2 = 2557,
2582 PseudoVFNCVT_RTZ_X_F_W_M2_MASK = 2558,
2583 PseudoVFNCVT_RTZ_X_F_W_M4 = 2559,
2584 PseudoVFNCVT_RTZ_X_F_W_M4_MASK = 2560,
2585 PseudoVFNCVT_RTZ_X_F_W_MF2 = 2561,
2586 PseudoVFNCVT_RTZ_X_F_W_MF2_MASK = 2562,
2587 PseudoVFNCVT_RTZ_X_F_W_MF4 = 2563,
2588 PseudoVFNCVT_RTZ_X_F_W_MF4_MASK = 2564,
2589 PseudoVFNCVT_RTZ_X_F_W_MF8 = 2565,
2590 PseudoVFNCVT_RTZ_X_F_W_MF8_MASK = 2566,
2591 PseudoVFNCVT_XU_F_W_M1 = 2567,
2592 PseudoVFNCVT_XU_F_W_M1_MASK = 2568,
2593 PseudoVFNCVT_XU_F_W_M2 = 2569,
2594 PseudoVFNCVT_XU_F_W_M2_MASK = 2570,
2595 PseudoVFNCVT_XU_F_W_M4 = 2571,
2596 PseudoVFNCVT_XU_F_W_M4_MASK = 2572,
2597 PseudoVFNCVT_XU_F_W_MF2 = 2573,
2598 PseudoVFNCVT_XU_F_W_MF2_MASK = 2574,
2599 PseudoVFNCVT_XU_F_W_MF4 = 2575,
2600 PseudoVFNCVT_XU_F_W_MF4_MASK = 2576,
2601 PseudoVFNCVT_XU_F_W_MF8 = 2577,
2602 PseudoVFNCVT_XU_F_W_MF8_MASK = 2578,
2603 PseudoVFNCVT_X_F_W_M1 = 2579,
2604 PseudoVFNCVT_X_F_W_M1_MASK = 2580,
2605 PseudoVFNCVT_X_F_W_M2 = 2581,
2606 PseudoVFNCVT_X_F_W_M2_MASK = 2582,
2607 PseudoVFNCVT_X_F_W_M4 = 2583,
2608 PseudoVFNCVT_X_F_W_M4_MASK = 2584,
2609 PseudoVFNCVT_X_F_W_MF2 = 2585,
2610 PseudoVFNCVT_X_F_W_MF2_MASK = 2586,
2611 PseudoVFNCVT_X_F_W_MF4 = 2587,
2612 PseudoVFNCVT_X_F_W_MF4_MASK = 2588,
2613 PseudoVFNCVT_X_F_W_MF8 = 2589,
2614 PseudoVFNCVT_X_F_W_MF8_MASK = 2590,
2615 PseudoVFNMACC_VFPR16_M1_E16 = 2591,
2616 PseudoVFNMACC_VFPR16_M1_E16_MASK = 2592,
2617 PseudoVFNMACC_VFPR16_M2_E16 = 2593,
2618 PseudoVFNMACC_VFPR16_M2_E16_MASK = 2594,
2619 PseudoVFNMACC_VFPR16_M4_E16 = 2595,
2620 PseudoVFNMACC_VFPR16_M4_E16_MASK = 2596,
2621 PseudoVFNMACC_VFPR16_M8_E16 = 2597,
2622 PseudoVFNMACC_VFPR16_M8_E16_MASK = 2598,
2623 PseudoVFNMACC_VFPR16_MF2_E16 = 2599,
2624 PseudoVFNMACC_VFPR16_MF2_E16_MASK = 2600,
2625 PseudoVFNMACC_VFPR16_MF4_E16 = 2601,
2626 PseudoVFNMACC_VFPR16_MF4_E16_MASK = 2602,
2627 PseudoVFNMACC_VFPR32_M1_E32 = 2603,
2628 PseudoVFNMACC_VFPR32_M1_E32_MASK = 2604,
2629 PseudoVFNMACC_VFPR32_M2_E32 = 2605,
2630 PseudoVFNMACC_VFPR32_M2_E32_MASK = 2606,
2631 PseudoVFNMACC_VFPR32_M4_E32 = 2607,
2632 PseudoVFNMACC_VFPR32_M4_E32_MASK = 2608,
2633 PseudoVFNMACC_VFPR32_M8_E32 = 2609,
2634 PseudoVFNMACC_VFPR32_M8_E32_MASK = 2610,
2635 PseudoVFNMACC_VFPR32_MF2_E32 = 2611,
2636 PseudoVFNMACC_VFPR32_MF2_E32_MASK = 2612,
2637 PseudoVFNMACC_VFPR64_M1_E64 = 2613,
2638 PseudoVFNMACC_VFPR64_M1_E64_MASK = 2614,
2639 PseudoVFNMACC_VFPR64_M2_E64 = 2615,
2640 PseudoVFNMACC_VFPR64_M2_E64_MASK = 2616,
2641 PseudoVFNMACC_VFPR64_M4_E64 = 2617,
2642 PseudoVFNMACC_VFPR64_M4_E64_MASK = 2618,
2643 PseudoVFNMACC_VFPR64_M8_E64 = 2619,
2644 PseudoVFNMACC_VFPR64_M8_E64_MASK = 2620,
2645 PseudoVFNMACC_VV_M1_E16 = 2621,
2646 PseudoVFNMACC_VV_M1_E16_MASK = 2622,
2647 PseudoVFNMACC_VV_M1_E32 = 2623,
2648 PseudoVFNMACC_VV_M1_E32_MASK = 2624,
2649 PseudoVFNMACC_VV_M1_E64 = 2625,
2650 PseudoVFNMACC_VV_M1_E64_MASK = 2626,
2651 PseudoVFNMACC_VV_M2_E16 = 2627,
2652 PseudoVFNMACC_VV_M2_E16_MASK = 2628,
2653 PseudoVFNMACC_VV_M2_E32 = 2629,
2654 PseudoVFNMACC_VV_M2_E32_MASK = 2630,
2655 PseudoVFNMACC_VV_M2_E64 = 2631,
2656 PseudoVFNMACC_VV_M2_E64_MASK = 2632,
2657 PseudoVFNMACC_VV_M4_E16 = 2633,
2658 PseudoVFNMACC_VV_M4_E16_MASK = 2634,
2659 PseudoVFNMACC_VV_M4_E32 = 2635,
2660 PseudoVFNMACC_VV_M4_E32_MASK = 2636,
2661 PseudoVFNMACC_VV_M4_E64 = 2637,
2662 PseudoVFNMACC_VV_M4_E64_MASK = 2638,
2663 PseudoVFNMACC_VV_M8_E16 = 2639,
2664 PseudoVFNMACC_VV_M8_E16_MASK = 2640,
2665 PseudoVFNMACC_VV_M8_E32 = 2641,
2666 PseudoVFNMACC_VV_M8_E32_MASK = 2642,
2667 PseudoVFNMACC_VV_M8_E64 = 2643,
2668 PseudoVFNMACC_VV_M8_E64_MASK = 2644,
2669 PseudoVFNMACC_VV_MF2_E16 = 2645,
2670 PseudoVFNMACC_VV_MF2_E16_MASK = 2646,
2671 PseudoVFNMACC_VV_MF2_E32 = 2647,
2672 PseudoVFNMACC_VV_MF2_E32_MASK = 2648,
2673 PseudoVFNMACC_VV_MF4_E16 = 2649,
2674 PseudoVFNMACC_VV_MF4_E16_MASK = 2650,
2675 PseudoVFNMADD_VFPR16_M1_E16 = 2651,
2676 PseudoVFNMADD_VFPR16_M1_E16_MASK = 2652,
2677 PseudoVFNMADD_VFPR16_M2_E16 = 2653,
2678 PseudoVFNMADD_VFPR16_M2_E16_MASK = 2654,
2679 PseudoVFNMADD_VFPR16_M4_E16 = 2655,
2680 PseudoVFNMADD_VFPR16_M4_E16_MASK = 2656,
2681 PseudoVFNMADD_VFPR16_M8_E16 = 2657,
2682 PseudoVFNMADD_VFPR16_M8_E16_MASK = 2658,
2683 PseudoVFNMADD_VFPR16_MF2_E16 = 2659,
2684 PseudoVFNMADD_VFPR16_MF2_E16_MASK = 2660,
2685 PseudoVFNMADD_VFPR16_MF4_E16 = 2661,
2686 PseudoVFNMADD_VFPR16_MF4_E16_MASK = 2662,
2687 PseudoVFNMADD_VFPR32_M1_E32 = 2663,
2688 PseudoVFNMADD_VFPR32_M1_E32_MASK = 2664,
2689 PseudoVFNMADD_VFPR32_M2_E32 = 2665,
2690 PseudoVFNMADD_VFPR32_M2_E32_MASK = 2666,
2691 PseudoVFNMADD_VFPR32_M4_E32 = 2667,
2692 PseudoVFNMADD_VFPR32_M4_E32_MASK = 2668,
2693 PseudoVFNMADD_VFPR32_M8_E32 = 2669,
2694 PseudoVFNMADD_VFPR32_M8_E32_MASK = 2670,
2695 PseudoVFNMADD_VFPR32_MF2_E32 = 2671,
2696 PseudoVFNMADD_VFPR32_MF2_E32_MASK = 2672,
2697 PseudoVFNMADD_VFPR64_M1_E64 = 2673,
2698 PseudoVFNMADD_VFPR64_M1_E64_MASK = 2674,
2699 PseudoVFNMADD_VFPR64_M2_E64 = 2675,
2700 PseudoVFNMADD_VFPR64_M2_E64_MASK = 2676,
2701 PseudoVFNMADD_VFPR64_M4_E64 = 2677,
2702 PseudoVFNMADD_VFPR64_M4_E64_MASK = 2678,
2703 PseudoVFNMADD_VFPR64_M8_E64 = 2679,
2704 PseudoVFNMADD_VFPR64_M8_E64_MASK = 2680,
2705 PseudoVFNMADD_VV_M1_E16 = 2681,
2706 PseudoVFNMADD_VV_M1_E16_MASK = 2682,
2707 PseudoVFNMADD_VV_M1_E32 = 2683,
2708 PseudoVFNMADD_VV_M1_E32_MASK = 2684,
2709 PseudoVFNMADD_VV_M1_E64 = 2685,
2710 PseudoVFNMADD_VV_M1_E64_MASK = 2686,
2711 PseudoVFNMADD_VV_M2_E16 = 2687,
2712 PseudoVFNMADD_VV_M2_E16_MASK = 2688,
2713 PseudoVFNMADD_VV_M2_E32 = 2689,
2714 PseudoVFNMADD_VV_M2_E32_MASK = 2690,
2715 PseudoVFNMADD_VV_M2_E64 = 2691,
2716 PseudoVFNMADD_VV_M2_E64_MASK = 2692,
2717 PseudoVFNMADD_VV_M4_E16 = 2693,
2718 PseudoVFNMADD_VV_M4_E16_MASK = 2694,
2719 PseudoVFNMADD_VV_M4_E32 = 2695,
2720 PseudoVFNMADD_VV_M4_E32_MASK = 2696,
2721 PseudoVFNMADD_VV_M4_E64 = 2697,
2722 PseudoVFNMADD_VV_M4_E64_MASK = 2698,
2723 PseudoVFNMADD_VV_M8_E16 = 2699,
2724 PseudoVFNMADD_VV_M8_E16_MASK = 2700,
2725 PseudoVFNMADD_VV_M8_E32 = 2701,
2726 PseudoVFNMADD_VV_M8_E32_MASK = 2702,
2727 PseudoVFNMADD_VV_M8_E64 = 2703,
2728 PseudoVFNMADD_VV_M8_E64_MASK = 2704,
2729 PseudoVFNMADD_VV_MF2_E16 = 2705,
2730 PseudoVFNMADD_VV_MF2_E16_MASK = 2706,
2731 PseudoVFNMADD_VV_MF2_E32 = 2707,
2732 PseudoVFNMADD_VV_MF2_E32_MASK = 2708,
2733 PseudoVFNMADD_VV_MF4_E16 = 2709,
2734 PseudoVFNMADD_VV_MF4_E16_MASK = 2710,
2735 PseudoVFNMSAC_VFPR16_M1_E16 = 2711,
2736 PseudoVFNMSAC_VFPR16_M1_E16_MASK = 2712,
2737 PseudoVFNMSAC_VFPR16_M2_E16 = 2713,
2738 PseudoVFNMSAC_VFPR16_M2_E16_MASK = 2714,
2739 PseudoVFNMSAC_VFPR16_M4_E16 = 2715,
2740 PseudoVFNMSAC_VFPR16_M4_E16_MASK = 2716,
2741 PseudoVFNMSAC_VFPR16_M8_E16 = 2717,
2742 PseudoVFNMSAC_VFPR16_M8_E16_MASK = 2718,
2743 PseudoVFNMSAC_VFPR16_MF2_E16 = 2719,
2744 PseudoVFNMSAC_VFPR16_MF2_E16_MASK = 2720,
2745 PseudoVFNMSAC_VFPR16_MF4_E16 = 2721,
2746 PseudoVFNMSAC_VFPR16_MF4_E16_MASK = 2722,
2747 PseudoVFNMSAC_VFPR32_M1_E32 = 2723,
2748 PseudoVFNMSAC_VFPR32_M1_E32_MASK = 2724,
2749 PseudoVFNMSAC_VFPR32_M2_E32 = 2725,
2750 PseudoVFNMSAC_VFPR32_M2_E32_MASK = 2726,
2751 PseudoVFNMSAC_VFPR32_M4_E32 = 2727,
2752 PseudoVFNMSAC_VFPR32_M4_E32_MASK = 2728,
2753 PseudoVFNMSAC_VFPR32_M8_E32 = 2729,
2754 PseudoVFNMSAC_VFPR32_M8_E32_MASK = 2730,
2755 PseudoVFNMSAC_VFPR32_MF2_E32 = 2731,
2756 PseudoVFNMSAC_VFPR32_MF2_E32_MASK = 2732,
2757 PseudoVFNMSAC_VFPR64_M1_E64 = 2733,
2758 PseudoVFNMSAC_VFPR64_M1_E64_MASK = 2734,
2759 PseudoVFNMSAC_VFPR64_M2_E64 = 2735,
2760 PseudoVFNMSAC_VFPR64_M2_E64_MASK = 2736,
2761 PseudoVFNMSAC_VFPR64_M4_E64 = 2737,
2762 PseudoVFNMSAC_VFPR64_M4_E64_MASK = 2738,
2763 PseudoVFNMSAC_VFPR64_M8_E64 = 2739,
2764 PseudoVFNMSAC_VFPR64_M8_E64_MASK = 2740,
2765 PseudoVFNMSAC_VV_M1_E16 = 2741,
2766 PseudoVFNMSAC_VV_M1_E16_MASK = 2742,
2767 PseudoVFNMSAC_VV_M1_E32 = 2743,
2768 PseudoVFNMSAC_VV_M1_E32_MASK = 2744,
2769 PseudoVFNMSAC_VV_M1_E64 = 2745,
2770 PseudoVFNMSAC_VV_M1_E64_MASK = 2746,
2771 PseudoVFNMSAC_VV_M2_E16 = 2747,
2772 PseudoVFNMSAC_VV_M2_E16_MASK = 2748,
2773 PseudoVFNMSAC_VV_M2_E32 = 2749,
2774 PseudoVFNMSAC_VV_M2_E32_MASK = 2750,
2775 PseudoVFNMSAC_VV_M2_E64 = 2751,
2776 PseudoVFNMSAC_VV_M2_E64_MASK = 2752,
2777 PseudoVFNMSAC_VV_M4_E16 = 2753,
2778 PseudoVFNMSAC_VV_M4_E16_MASK = 2754,
2779 PseudoVFNMSAC_VV_M4_E32 = 2755,
2780 PseudoVFNMSAC_VV_M4_E32_MASK = 2756,
2781 PseudoVFNMSAC_VV_M4_E64 = 2757,
2782 PseudoVFNMSAC_VV_M4_E64_MASK = 2758,
2783 PseudoVFNMSAC_VV_M8_E16 = 2759,
2784 PseudoVFNMSAC_VV_M8_E16_MASK = 2760,
2785 PseudoVFNMSAC_VV_M8_E32 = 2761,
2786 PseudoVFNMSAC_VV_M8_E32_MASK = 2762,
2787 PseudoVFNMSAC_VV_M8_E64 = 2763,
2788 PseudoVFNMSAC_VV_M8_E64_MASK = 2764,
2789 PseudoVFNMSAC_VV_MF2_E16 = 2765,
2790 PseudoVFNMSAC_VV_MF2_E16_MASK = 2766,
2791 PseudoVFNMSAC_VV_MF2_E32 = 2767,
2792 PseudoVFNMSAC_VV_MF2_E32_MASK = 2768,
2793 PseudoVFNMSAC_VV_MF4_E16 = 2769,
2794 PseudoVFNMSAC_VV_MF4_E16_MASK = 2770,
2795 PseudoVFNMSUB_VFPR16_M1_E16 = 2771,
2796 PseudoVFNMSUB_VFPR16_M1_E16_MASK = 2772,
2797 PseudoVFNMSUB_VFPR16_M2_E16 = 2773,
2798 PseudoVFNMSUB_VFPR16_M2_E16_MASK = 2774,
2799 PseudoVFNMSUB_VFPR16_M4_E16 = 2775,
2800 PseudoVFNMSUB_VFPR16_M4_E16_MASK = 2776,
2801 PseudoVFNMSUB_VFPR16_M8_E16 = 2777,
2802 PseudoVFNMSUB_VFPR16_M8_E16_MASK = 2778,
2803 PseudoVFNMSUB_VFPR16_MF2_E16 = 2779,
2804 PseudoVFNMSUB_VFPR16_MF2_E16_MASK = 2780,
2805 PseudoVFNMSUB_VFPR16_MF4_E16 = 2781,
2806 PseudoVFNMSUB_VFPR16_MF4_E16_MASK = 2782,
2807 PseudoVFNMSUB_VFPR32_M1_E32 = 2783,
2808 PseudoVFNMSUB_VFPR32_M1_E32_MASK = 2784,
2809 PseudoVFNMSUB_VFPR32_M2_E32 = 2785,
2810 PseudoVFNMSUB_VFPR32_M2_E32_MASK = 2786,
2811 PseudoVFNMSUB_VFPR32_M4_E32 = 2787,
2812 PseudoVFNMSUB_VFPR32_M4_E32_MASK = 2788,
2813 PseudoVFNMSUB_VFPR32_M8_E32 = 2789,
2814 PseudoVFNMSUB_VFPR32_M8_E32_MASK = 2790,
2815 PseudoVFNMSUB_VFPR32_MF2_E32 = 2791,
2816 PseudoVFNMSUB_VFPR32_MF2_E32_MASK = 2792,
2817 PseudoVFNMSUB_VFPR64_M1_E64 = 2793,
2818 PseudoVFNMSUB_VFPR64_M1_E64_MASK = 2794,
2819 PseudoVFNMSUB_VFPR64_M2_E64 = 2795,
2820 PseudoVFNMSUB_VFPR64_M2_E64_MASK = 2796,
2821 PseudoVFNMSUB_VFPR64_M4_E64 = 2797,
2822 PseudoVFNMSUB_VFPR64_M4_E64_MASK = 2798,
2823 PseudoVFNMSUB_VFPR64_M8_E64 = 2799,
2824 PseudoVFNMSUB_VFPR64_M8_E64_MASK = 2800,
2825 PseudoVFNMSUB_VV_M1_E16 = 2801,
2826 PseudoVFNMSUB_VV_M1_E16_MASK = 2802,
2827 PseudoVFNMSUB_VV_M1_E32 = 2803,
2828 PseudoVFNMSUB_VV_M1_E32_MASK = 2804,
2829 PseudoVFNMSUB_VV_M1_E64 = 2805,
2830 PseudoVFNMSUB_VV_M1_E64_MASK = 2806,
2831 PseudoVFNMSUB_VV_M2_E16 = 2807,
2832 PseudoVFNMSUB_VV_M2_E16_MASK = 2808,
2833 PseudoVFNMSUB_VV_M2_E32 = 2809,
2834 PseudoVFNMSUB_VV_M2_E32_MASK = 2810,
2835 PseudoVFNMSUB_VV_M2_E64 = 2811,
2836 PseudoVFNMSUB_VV_M2_E64_MASK = 2812,
2837 PseudoVFNMSUB_VV_M4_E16 = 2813,
2838 PseudoVFNMSUB_VV_M4_E16_MASK = 2814,
2839 PseudoVFNMSUB_VV_M4_E32 = 2815,
2840 PseudoVFNMSUB_VV_M4_E32_MASK = 2816,
2841 PseudoVFNMSUB_VV_M4_E64 = 2817,
2842 PseudoVFNMSUB_VV_M4_E64_MASK = 2818,
2843 PseudoVFNMSUB_VV_M8_E16 = 2819,
2844 PseudoVFNMSUB_VV_M8_E16_MASK = 2820,
2845 PseudoVFNMSUB_VV_M8_E32 = 2821,
2846 PseudoVFNMSUB_VV_M8_E32_MASK = 2822,
2847 PseudoVFNMSUB_VV_M8_E64 = 2823,
2848 PseudoVFNMSUB_VV_M8_E64_MASK = 2824,
2849 PseudoVFNMSUB_VV_MF2_E16 = 2825,
2850 PseudoVFNMSUB_VV_MF2_E16_MASK = 2826,
2851 PseudoVFNMSUB_VV_MF2_E32 = 2827,
2852 PseudoVFNMSUB_VV_MF2_E32_MASK = 2828,
2853 PseudoVFNMSUB_VV_MF4_E16 = 2829,
2854 PseudoVFNMSUB_VV_MF4_E16_MASK = 2830,
2855 PseudoVFNRCLIP_XU_F_QF_M1 = 2831,
2856 PseudoVFNRCLIP_XU_F_QF_M1_MASK = 2832,
2857 PseudoVFNRCLIP_XU_F_QF_M2 = 2833,
2858 PseudoVFNRCLIP_XU_F_QF_M2_MASK = 2834,
2859 PseudoVFNRCLIP_XU_F_QF_MF2 = 2835,
2860 PseudoVFNRCLIP_XU_F_QF_MF2_MASK = 2836,
2861 PseudoVFNRCLIP_XU_F_QF_MF4 = 2837,
2862 PseudoVFNRCLIP_XU_F_QF_MF4_MASK = 2838,
2863 PseudoVFNRCLIP_XU_F_QF_MF8 = 2839,
2864 PseudoVFNRCLIP_XU_F_QF_MF8_MASK = 2840,
2865 PseudoVFNRCLIP_X_F_QF_M1 = 2841,
2866 PseudoVFNRCLIP_X_F_QF_M1_MASK = 2842,
2867 PseudoVFNRCLIP_X_F_QF_M2 = 2843,
2868 PseudoVFNRCLIP_X_F_QF_M2_MASK = 2844,
2869 PseudoVFNRCLIP_X_F_QF_MF2 = 2845,
2870 PseudoVFNRCLIP_X_F_QF_MF2_MASK = 2846,
2871 PseudoVFNRCLIP_X_F_QF_MF4 = 2847,
2872 PseudoVFNRCLIP_X_F_QF_MF4_MASK = 2848,
2873 PseudoVFNRCLIP_X_F_QF_MF8 = 2849,
2874 PseudoVFNRCLIP_X_F_QF_MF8_MASK = 2850,
2875 PseudoVFRDIV_VFPR16_M1_E16 = 2851,
2876 PseudoVFRDIV_VFPR16_M1_E16_MASK = 2852,
2877 PseudoVFRDIV_VFPR16_M2_E16 = 2853,
2878 PseudoVFRDIV_VFPR16_M2_E16_MASK = 2854,
2879 PseudoVFRDIV_VFPR16_M4_E16 = 2855,
2880 PseudoVFRDIV_VFPR16_M4_E16_MASK = 2856,
2881 PseudoVFRDIV_VFPR16_M8_E16 = 2857,
2882 PseudoVFRDIV_VFPR16_M8_E16_MASK = 2858,
2883 PseudoVFRDIV_VFPR16_MF2_E16 = 2859,
2884 PseudoVFRDIV_VFPR16_MF2_E16_MASK = 2860,
2885 PseudoVFRDIV_VFPR16_MF4_E16 = 2861,
2886 PseudoVFRDIV_VFPR16_MF4_E16_MASK = 2862,
2887 PseudoVFRDIV_VFPR32_M1_E32 = 2863,
2888 PseudoVFRDIV_VFPR32_M1_E32_MASK = 2864,
2889 PseudoVFRDIV_VFPR32_M2_E32 = 2865,
2890 PseudoVFRDIV_VFPR32_M2_E32_MASK = 2866,
2891 PseudoVFRDIV_VFPR32_M4_E32 = 2867,
2892 PseudoVFRDIV_VFPR32_M4_E32_MASK = 2868,
2893 PseudoVFRDIV_VFPR32_M8_E32 = 2869,
2894 PseudoVFRDIV_VFPR32_M8_E32_MASK = 2870,
2895 PseudoVFRDIV_VFPR32_MF2_E32 = 2871,
2896 PseudoVFRDIV_VFPR32_MF2_E32_MASK = 2872,
2897 PseudoVFRDIV_VFPR64_M1_E64 = 2873,
2898 PseudoVFRDIV_VFPR64_M1_E64_MASK = 2874,
2899 PseudoVFRDIV_VFPR64_M2_E64 = 2875,
2900 PseudoVFRDIV_VFPR64_M2_E64_MASK = 2876,
2901 PseudoVFRDIV_VFPR64_M4_E64 = 2877,
2902 PseudoVFRDIV_VFPR64_M4_E64_MASK = 2878,
2903 PseudoVFRDIV_VFPR64_M8_E64 = 2879,
2904 PseudoVFRDIV_VFPR64_M8_E64_MASK = 2880,
2905 PseudoVFREC7_V_M1_E16 = 2881,
2906 PseudoVFREC7_V_M1_E16_MASK = 2882,
2907 PseudoVFREC7_V_M1_E32 = 2883,
2908 PseudoVFREC7_V_M1_E32_MASK = 2884,
2909 PseudoVFREC7_V_M1_E64 = 2885,
2910 PseudoVFREC7_V_M1_E64_MASK = 2886,
2911 PseudoVFREC7_V_M2_E16 = 2887,
2912 PseudoVFREC7_V_M2_E16_MASK = 2888,
2913 PseudoVFREC7_V_M2_E32 = 2889,
2914 PseudoVFREC7_V_M2_E32_MASK = 2890,
2915 PseudoVFREC7_V_M2_E64 = 2891,
2916 PseudoVFREC7_V_M2_E64_MASK = 2892,
2917 PseudoVFREC7_V_M4_E16 = 2893,
2918 PseudoVFREC7_V_M4_E16_MASK = 2894,
2919 PseudoVFREC7_V_M4_E32 = 2895,
2920 PseudoVFREC7_V_M4_E32_MASK = 2896,
2921 PseudoVFREC7_V_M4_E64 = 2897,
2922 PseudoVFREC7_V_M4_E64_MASK = 2898,
2923 PseudoVFREC7_V_M8_E16 = 2899,
2924 PseudoVFREC7_V_M8_E16_MASK = 2900,
2925 PseudoVFREC7_V_M8_E32 = 2901,
2926 PseudoVFREC7_V_M8_E32_MASK = 2902,
2927 PseudoVFREC7_V_M8_E64 = 2903,
2928 PseudoVFREC7_V_M8_E64_MASK = 2904,
2929 PseudoVFREC7_V_MF2_E16 = 2905,
2930 PseudoVFREC7_V_MF2_E16_MASK = 2906,
2931 PseudoVFREC7_V_MF2_E32 = 2907,
2932 PseudoVFREC7_V_MF2_E32_MASK = 2908,
2933 PseudoVFREC7_V_MF4_E16 = 2909,
2934 PseudoVFREC7_V_MF4_E16_MASK = 2910,
2935 PseudoVFREDMAX_VS_M1_E16 = 2911,
2936 PseudoVFREDMAX_VS_M1_E16_MASK = 2912,
2937 PseudoVFREDMAX_VS_M1_E32 = 2913,
2938 PseudoVFREDMAX_VS_M1_E32_MASK = 2914,
2939 PseudoVFREDMAX_VS_M1_E64 = 2915,
2940 PseudoVFREDMAX_VS_M1_E64_MASK = 2916,
2941 PseudoVFREDMAX_VS_M2_E16 = 2917,
2942 PseudoVFREDMAX_VS_M2_E16_MASK = 2918,
2943 PseudoVFREDMAX_VS_M2_E32 = 2919,
2944 PseudoVFREDMAX_VS_M2_E32_MASK = 2920,
2945 PseudoVFREDMAX_VS_M2_E64 = 2921,
2946 PseudoVFREDMAX_VS_M2_E64_MASK = 2922,
2947 PseudoVFREDMAX_VS_M4_E16 = 2923,
2948 PseudoVFREDMAX_VS_M4_E16_MASK = 2924,
2949 PseudoVFREDMAX_VS_M4_E32 = 2925,
2950 PseudoVFREDMAX_VS_M4_E32_MASK = 2926,
2951 PseudoVFREDMAX_VS_M4_E64 = 2927,
2952 PseudoVFREDMAX_VS_M4_E64_MASK = 2928,
2953 PseudoVFREDMAX_VS_M8_E16 = 2929,
2954 PseudoVFREDMAX_VS_M8_E16_MASK = 2930,
2955 PseudoVFREDMAX_VS_M8_E32 = 2931,
2956 PseudoVFREDMAX_VS_M8_E32_MASK = 2932,
2957 PseudoVFREDMAX_VS_M8_E64 = 2933,
2958 PseudoVFREDMAX_VS_M8_E64_MASK = 2934,
2959 PseudoVFREDMAX_VS_MF2_E16 = 2935,
2960 PseudoVFREDMAX_VS_MF2_E16_MASK = 2936,
2961 PseudoVFREDMAX_VS_MF2_E32 = 2937,
2962 PseudoVFREDMAX_VS_MF2_E32_MASK = 2938,
2963 PseudoVFREDMAX_VS_MF4_E16 = 2939,
2964 PseudoVFREDMAX_VS_MF4_E16_MASK = 2940,
2965 PseudoVFREDMIN_VS_M1_E16 = 2941,
2966 PseudoVFREDMIN_VS_M1_E16_MASK = 2942,
2967 PseudoVFREDMIN_VS_M1_E32 = 2943,
2968 PseudoVFREDMIN_VS_M1_E32_MASK = 2944,
2969 PseudoVFREDMIN_VS_M1_E64 = 2945,
2970 PseudoVFREDMIN_VS_M1_E64_MASK = 2946,
2971 PseudoVFREDMIN_VS_M2_E16 = 2947,
2972 PseudoVFREDMIN_VS_M2_E16_MASK = 2948,
2973 PseudoVFREDMIN_VS_M2_E32 = 2949,
2974 PseudoVFREDMIN_VS_M2_E32_MASK = 2950,
2975 PseudoVFREDMIN_VS_M2_E64 = 2951,
2976 PseudoVFREDMIN_VS_M2_E64_MASK = 2952,
2977 PseudoVFREDMIN_VS_M4_E16 = 2953,
2978 PseudoVFREDMIN_VS_M4_E16_MASK = 2954,
2979 PseudoVFREDMIN_VS_M4_E32 = 2955,
2980 PseudoVFREDMIN_VS_M4_E32_MASK = 2956,
2981 PseudoVFREDMIN_VS_M4_E64 = 2957,
2982 PseudoVFREDMIN_VS_M4_E64_MASK = 2958,
2983 PseudoVFREDMIN_VS_M8_E16 = 2959,
2984 PseudoVFREDMIN_VS_M8_E16_MASK = 2960,
2985 PseudoVFREDMIN_VS_M8_E32 = 2961,
2986 PseudoVFREDMIN_VS_M8_E32_MASK = 2962,
2987 PseudoVFREDMIN_VS_M8_E64 = 2963,
2988 PseudoVFREDMIN_VS_M8_E64_MASK = 2964,
2989 PseudoVFREDMIN_VS_MF2_E16 = 2965,
2990 PseudoVFREDMIN_VS_MF2_E16_MASK = 2966,
2991 PseudoVFREDMIN_VS_MF2_E32 = 2967,
2992 PseudoVFREDMIN_VS_MF2_E32_MASK = 2968,
2993 PseudoVFREDMIN_VS_MF4_E16 = 2969,
2994 PseudoVFREDMIN_VS_MF4_E16_MASK = 2970,
2995 PseudoVFREDOSUM_VS_M1_E16 = 2971,
2996 PseudoVFREDOSUM_VS_M1_E16_MASK = 2972,
2997 PseudoVFREDOSUM_VS_M1_E32 = 2973,
2998 PseudoVFREDOSUM_VS_M1_E32_MASK = 2974,
2999 PseudoVFREDOSUM_VS_M1_E64 = 2975,
3000 PseudoVFREDOSUM_VS_M1_E64_MASK = 2976,
3001 PseudoVFREDOSUM_VS_M2_E16 = 2977,
3002 PseudoVFREDOSUM_VS_M2_E16_MASK = 2978,
3003 PseudoVFREDOSUM_VS_M2_E32 = 2979,
3004 PseudoVFREDOSUM_VS_M2_E32_MASK = 2980,
3005 PseudoVFREDOSUM_VS_M2_E64 = 2981,
3006 PseudoVFREDOSUM_VS_M2_E64_MASK = 2982,
3007 PseudoVFREDOSUM_VS_M4_E16 = 2983,
3008 PseudoVFREDOSUM_VS_M4_E16_MASK = 2984,
3009 PseudoVFREDOSUM_VS_M4_E32 = 2985,
3010 PseudoVFREDOSUM_VS_M4_E32_MASK = 2986,
3011 PseudoVFREDOSUM_VS_M4_E64 = 2987,
3012 PseudoVFREDOSUM_VS_M4_E64_MASK = 2988,
3013 PseudoVFREDOSUM_VS_M8_E16 = 2989,
3014 PseudoVFREDOSUM_VS_M8_E16_MASK = 2990,
3015 PseudoVFREDOSUM_VS_M8_E32 = 2991,
3016 PseudoVFREDOSUM_VS_M8_E32_MASK = 2992,
3017 PseudoVFREDOSUM_VS_M8_E64 = 2993,
3018 PseudoVFREDOSUM_VS_M8_E64_MASK = 2994,
3019 PseudoVFREDOSUM_VS_MF2_E16 = 2995,
3020 PseudoVFREDOSUM_VS_MF2_E16_MASK = 2996,
3021 PseudoVFREDOSUM_VS_MF2_E32 = 2997,
3022 PseudoVFREDOSUM_VS_MF2_E32_MASK = 2998,
3023 PseudoVFREDOSUM_VS_MF4_E16 = 2999,
3024 PseudoVFREDOSUM_VS_MF4_E16_MASK = 3000,
3025 PseudoVFREDUSUM_VS_M1_E16 = 3001,
3026 PseudoVFREDUSUM_VS_M1_E16_MASK = 3002,
3027 PseudoVFREDUSUM_VS_M1_E32 = 3003,
3028 PseudoVFREDUSUM_VS_M1_E32_MASK = 3004,
3029 PseudoVFREDUSUM_VS_M1_E64 = 3005,
3030 PseudoVFREDUSUM_VS_M1_E64_MASK = 3006,
3031 PseudoVFREDUSUM_VS_M2_E16 = 3007,
3032 PseudoVFREDUSUM_VS_M2_E16_MASK = 3008,
3033 PseudoVFREDUSUM_VS_M2_E32 = 3009,
3034 PseudoVFREDUSUM_VS_M2_E32_MASK = 3010,
3035 PseudoVFREDUSUM_VS_M2_E64 = 3011,
3036 PseudoVFREDUSUM_VS_M2_E64_MASK = 3012,
3037 PseudoVFREDUSUM_VS_M4_E16 = 3013,
3038 PseudoVFREDUSUM_VS_M4_E16_MASK = 3014,
3039 PseudoVFREDUSUM_VS_M4_E32 = 3015,
3040 PseudoVFREDUSUM_VS_M4_E32_MASK = 3016,
3041 PseudoVFREDUSUM_VS_M4_E64 = 3017,
3042 PseudoVFREDUSUM_VS_M4_E64_MASK = 3018,
3043 PseudoVFREDUSUM_VS_M8_E16 = 3019,
3044 PseudoVFREDUSUM_VS_M8_E16_MASK = 3020,
3045 PseudoVFREDUSUM_VS_M8_E32 = 3021,
3046 PseudoVFREDUSUM_VS_M8_E32_MASK = 3022,
3047 PseudoVFREDUSUM_VS_M8_E64 = 3023,
3048 PseudoVFREDUSUM_VS_M8_E64_MASK = 3024,
3049 PseudoVFREDUSUM_VS_MF2_E16 = 3025,
3050 PseudoVFREDUSUM_VS_MF2_E16_MASK = 3026,
3051 PseudoVFREDUSUM_VS_MF2_E32 = 3027,
3052 PseudoVFREDUSUM_VS_MF2_E32_MASK = 3028,
3053 PseudoVFREDUSUM_VS_MF4_E16 = 3029,
3054 PseudoVFREDUSUM_VS_MF4_E16_MASK = 3030,
3055 PseudoVFROUND_NOEXCEPT_V_M1_MASK = 3031,
3056 PseudoVFROUND_NOEXCEPT_V_M2_MASK = 3032,
3057 PseudoVFROUND_NOEXCEPT_V_M4_MASK = 3033,
3058 PseudoVFROUND_NOEXCEPT_V_M8_MASK = 3034,
3059 PseudoVFROUND_NOEXCEPT_V_MF2_MASK = 3035,
3060 PseudoVFROUND_NOEXCEPT_V_MF4_MASK = 3036,
3061 PseudoVFRSQRT7_V_M1_E16 = 3037,
3062 PseudoVFRSQRT7_V_M1_E16_MASK = 3038,
3063 PseudoVFRSQRT7_V_M1_E32 = 3039,
3064 PseudoVFRSQRT7_V_M1_E32_MASK = 3040,
3065 PseudoVFRSQRT7_V_M1_E64 = 3041,
3066 PseudoVFRSQRT7_V_M1_E64_MASK = 3042,
3067 PseudoVFRSQRT7_V_M2_E16 = 3043,
3068 PseudoVFRSQRT7_V_M2_E16_MASK = 3044,
3069 PseudoVFRSQRT7_V_M2_E32 = 3045,
3070 PseudoVFRSQRT7_V_M2_E32_MASK = 3046,
3071 PseudoVFRSQRT7_V_M2_E64 = 3047,
3072 PseudoVFRSQRT7_V_M2_E64_MASK = 3048,
3073 PseudoVFRSQRT7_V_M4_E16 = 3049,
3074 PseudoVFRSQRT7_V_M4_E16_MASK = 3050,
3075 PseudoVFRSQRT7_V_M4_E32 = 3051,
3076 PseudoVFRSQRT7_V_M4_E32_MASK = 3052,
3077 PseudoVFRSQRT7_V_M4_E64 = 3053,
3078 PseudoVFRSQRT7_V_M4_E64_MASK = 3054,
3079 PseudoVFRSQRT7_V_M8_E16 = 3055,
3080 PseudoVFRSQRT7_V_M8_E16_MASK = 3056,
3081 PseudoVFRSQRT7_V_M8_E32 = 3057,
3082 PseudoVFRSQRT7_V_M8_E32_MASK = 3058,
3083 PseudoVFRSQRT7_V_M8_E64 = 3059,
3084 PseudoVFRSQRT7_V_M8_E64_MASK = 3060,
3085 PseudoVFRSQRT7_V_MF2_E16 = 3061,
3086 PseudoVFRSQRT7_V_MF2_E16_MASK = 3062,
3087 PseudoVFRSQRT7_V_MF2_E32 = 3063,
3088 PseudoVFRSQRT7_V_MF2_E32_MASK = 3064,
3089 PseudoVFRSQRT7_V_MF4_E16 = 3065,
3090 PseudoVFRSQRT7_V_MF4_E16_MASK = 3066,
3091 PseudoVFRSUB_VFPR16_M1_E16 = 3067,
3092 PseudoVFRSUB_VFPR16_M1_E16_MASK = 3068,
3093 PseudoVFRSUB_VFPR16_M2_E16 = 3069,
3094 PseudoVFRSUB_VFPR16_M2_E16_MASK = 3070,
3095 PseudoVFRSUB_VFPR16_M4_E16 = 3071,
3096 PseudoVFRSUB_VFPR16_M4_E16_MASK = 3072,
3097 PseudoVFRSUB_VFPR16_M8_E16 = 3073,
3098 PseudoVFRSUB_VFPR16_M8_E16_MASK = 3074,
3099 PseudoVFRSUB_VFPR16_MF2_E16 = 3075,
3100 PseudoVFRSUB_VFPR16_MF2_E16_MASK = 3076,
3101 PseudoVFRSUB_VFPR16_MF4_E16 = 3077,
3102 PseudoVFRSUB_VFPR16_MF4_E16_MASK = 3078,
3103 PseudoVFRSUB_VFPR32_M1_E32 = 3079,
3104 PseudoVFRSUB_VFPR32_M1_E32_MASK = 3080,
3105 PseudoVFRSUB_VFPR32_M2_E32 = 3081,
3106 PseudoVFRSUB_VFPR32_M2_E32_MASK = 3082,
3107 PseudoVFRSUB_VFPR32_M4_E32 = 3083,
3108 PseudoVFRSUB_VFPR32_M4_E32_MASK = 3084,
3109 PseudoVFRSUB_VFPR32_M8_E32 = 3085,
3110 PseudoVFRSUB_VFPR32_M8_E32_MASK = 3086,
3111 PseudoVFRSUB_VFPR32_MF2_E32 = 3087,
3112 PseudoVFRSUB_VFPR32_MF2_E32_MASK = 3088,
3113 PseudoVFRSUB_VFPR64_M1_E64 = 3089,
3114 PseudoVFRSUB_VFPR64_M1_E64_MASK = 3090,
3115 PseudoVFRSUB_VFPR64_M2_E64 = 3091,
3116 PseudoVFRSUB_VFPR64_M2_E64_MASK = 3092,
3117 PseudoVFRSUB_VFPR64_M4_E64 = 3093,
3118 PseudoVFRSUB_VFPR64_M4_E64_MASK = 3094,
3119 PseudoVFRSUB_VFPR64_M8_E64 = 3095,
3120 PseudoVFRSUB_VFPR64_M8_E64_MASK = 3096,
3121 PseudoVFSGNJN_VFPR16_M1_E16 = 3097,
3122 PseudoVFSGNJN_VFPR16_M1_E16_MASK = 3098,
3123 PseudoVFSGNJN_VFPR16_M2_E16 = 3099,
3124 PseudoVFSGNJN_VFPR16_M2_E16_MASK = 3100,
3125 PseudoVFSGNJN_VFPR16_M4_E16 = 3101,
3126 PseudoVFSGNJN_VFPR16_M4_E16_MASK = 3102,
3127 PseudoVFSGNJN_VFPR16_M8_E16 = 3103,
3128 PseudoVFSGNJN_VFPR16_M8_E16_MASK = 3104,
3129 PseudoVFSGNJN_VFPR16_MF2_E16 = 3105,
3130 PseudoVFSGNJN_VFPR16_MF2_E16_MASK = 3106,
3131 PseudoVFSGNJN_VFPR16_MF4_E16 = 3107,
3132 PseudoVFSGNJN_VFPR16_MF4_E16_MASK = 3108,
3133 PseudoVFSGNJN_VFPR32_M1_E32 = 3109,
3134 PseudoVFSGNJN_VFPR32_M1_E32_MASK = 3110,
3135 PseudoVFSGNJN_VFPR32_M2_E32 = 3111,
3136 PseudoVFSGNJN_VFPR32_M2_E32_MASK = 3112,
3137 PseudoVFSGNJN_VFPR32_M4_E32 = 3113,
3138 PseudoVFSGNJN_VFPR32_M4_E32_MASK = 3114,
3139 PseudoVFSGNJN_VFPR32_M8_E32 = 3115,
3140 PseudoVFSGNJN_VFPR32_M8_E32_MASK = 3116,
3141 PseudoVFSGNJN_VFPR32_MF2_E32 = 3117,
3142 PseudoVFSGNJN_VFPR32_MF2_E32_MASK = 3118,
3143 PseudoVFSGNJN_VFPR64_M1_E64 = 3119,
3144 PseudoVFSGNJN_VFPR64_M1_E64_MASK = 3120,
3145 PseudoVFSGNJN_VFPR64_M2_E64 = 3121,
3146 PseudoVFSGNJN_VFPR64_M2_E64_MASK = 3122,
3147 PseudoVFSGNJN_VFPR64_M4_E64 = 3123,
3148 PseudoVFSGNJN_VFPR64_M4_E64_MASK = 3124,
3149 PseudoVFSGNJN_VFPR64_M8_E64 = 3125,
3150 PseudoVFSGNJN_VFPR64_M8_E64_MASK = 3126,
3151 PseudoVFSGNJN_VV_M1_E16 = 3127,
3152 PseudoVFSGNJN_VV_M1_E16_MASK = 3128,
3153 PseudoVFSGNJN_VV_M1_E32 = 3129,
3154 PseudoVFSGNJN_VV_M1_E32_MASK = 3130,
3155 PseudoVFSGNJN_VV_M1_E64 = 3131,
3156 PseudoVFSGNJN_VV_M1_E64_MASK = 3132,
3157 PseudoVFSGNJN_VV_M2_E16 = 3133,
3158 PseudoVFSGNJN_VV_M2_E16_MASK = 3134,
3159 PseudoVFSGNJN_VV_M2_E32 = 3135,
3160 PseudoVFSGNJN_VV_M2_E32_MASK = 3136,
3161 PseudoVFSGNJN_VV_M2_E64 = 3137,
3162 PseudoVFSGNJN_VV_M2_E64_MASK = 3138,
3163 PseudoVFSGNJN_VV_M4_E16 = 3139,
3164 PseudoVFSGNJN_VV_M4_E16_MASK = 3140,
3165 PseudoVFSGNJN_VV_M4_E32 = 3141,
3166 PseudoVFSGNJN_VV_M4_E32_MASK = 3142,
3167 PseudoVFSGNJN_VV_M4_E64 = 3143,
3168 PseudoVFSGNJN_VV_M4_E64_MASK = 3144,
3169 PseudoVFSGNJN_VV_M8_E16 = 3145,
3170 PseudoVFSGNJN_VV_M8_E16_MASK = 3146,
3171 PseudoVFSGNJN_VV_M8_E32 = 3147,
3172 PseudoVFSGNJN_VV_M8_E32_MASK = 3148,
3173 PseudoVFSGNJN_VV_M8_E64 = 3149,
3174 PseudoVFSGNJN_VV_M8_E64_MASK = 3150,
3175 PseudoVFSGNJN_VV_MF2_E16 = 3151,
3176 PseudoVFSGNJN_VV_MF2_E16_MASK = 3152,
3177 PseudoVFSGNJN_VV_MF2_E32 = 3153,
3178 PseudoVFSGNJN_VV_MF2_E32_MASK = 3154,
3179 PseudoVFSGNJN_VV_MF4_E16 = 3155,
3180 PseudoVFSGNJN_VV_MF4_E16_MASK = 3156,
3181 PseudoVFSGNJX_VFPR16_M1_E16 = 3157,
3182 PseudoVFSGNJX_VFPR16_M1_E16_MASK = 3158,
3183 PseudoVFSGNJX_VFPR16_M2_E16 = 3159,
3184 PseudoVFSGNJX_VFPR16_M2_E16_MASK = 3160,
3185 PseudoVFSGNJX_VFPR16_M4_E16 = 3161,
3186 PseudoVFSGNJX_VFPR16_M4_E16_MASK = 3162,
3187 PseudoVFSGNJX_VFPR16_M8_E16 = 3163,
3188 PseudoVFSGNJX_VFPR16_M8_E16_MASK = 3164,
3189 PseudoVFSGNJX_VFPR16_MF2_E16 = 3165,
3190 PseudoVFSGNJX_VFPR16_MF2_E16_MASK = 3166,
3191 PseudoVFSGNJX_VFPR16_MF4_E16 = 3167,
3192 PseudoVFSGNJX_VFPR16_MF4_E16_MASK = 3168,
3193 PseudoVFSGNJX_VFPR32_M1_E32 = 3169,
3194 PseudoVFSGNJX_VFPR32_M1_E32_MASK = 3170,
3195 PseudoVFSGNJX_VFPR32_M2_E32 = 3171,
3196 PseudoVFSGNJX_VFPR32_M2_E32_MASK = 3172,
3197 PseudoVFSGNJX_VFPR32_M4_E32 = 3173,
3198 PseudoVFSGNJX_VFPR32_M4_E32_MASK = 3174,
3199 PseudoVFSGNJX_VFPR32_M8_E32 = 3175,
3200 PseudoVFSGNJX_VFPR32_M8_E32_MASK = 3176,
3201 PseudoVFSGNJX_VFPR32_MF2_E32 = 3177,
3202 PseudoVFSGNJX_VFPR32_MF2_E32_MASK = 3178,
3203 PseudoVFSGNJX_VFPR64_M1_E64 = 3179,
3204 PseudoVFSGNJX_VFPR64_M1_E64_MASK = 3180,
3205 PseudoVFSGNJX_VFPR64_M2_E64 = 3181,
3206 PseudoVFSGNJX_VFPR64_M2_E64_MASK = 3182,
3207 PseudoVFSGNJX_VFPR64_M4_E64 = 3183,
3208 PseudoVFSGNJX_VFPR64_M4_E64_MASK = 3184,
3209 PseudoVFSGNJX_VFPR64_M8_E64 = 3185,
3210 PseudoVFSGNJX_VFPR64_M8_E64_MASK = 3186,
3211 PseudoVFSGNJX_VV_M1_E16 = 3187,
3212 PseudoVFSGNJX_VV_M1_E16_MASK = 3188,
3213 PseudoVFSGNJX_VV_M1_E32 = 3189,
3214 PseudoVFSGNJX_VV_M1_E32_MASK = 3190,
3215 PseudoVFSGNJX_VV_M1_E64 = 3191,
3216 PseudoVFSGNJX_VV_M1_E64_MASK = 3192,
3217 PseudoVFSGNJX_VV_M2_E16 = 3193,
3218 PseudoVFSGNJX_VV_M2_E16_MASK = 3194,
3219 PseudoVFSGNJX_VV_M2_E32 = 3195,
3220 PseudoVFSGNJX_VV_M2_E32_MASK = 3196,
3221 PseudoVFSGNJX_VV_M2_E64 = 3197,
3222 PseudoVFSGNJX_VV_M2_E64_MASK = 3198,
3223 PseudoVFSGNJX_VV_M4_E16 = 3199,
3224 PseudoVFSGNJX_VV_M4_E16_MASK = 3200,
3225 PseudoVFSGNJX_VV_M4_E32 = 3201,
3226 PseudoVFSGNJX_VV_M4_E32_MASK = 3202,
3227 PseudoVFSGNJX_VV_M4_E64 = 3203,
3228 PseudoVFSGNJX_VV_M4_E64_MASK = 3204,
3229 PseudoVFSGNJX_VV_M8_E16 = 3205,
3230 PseudoVFSGNJX_VV_M8_E16_MASK = 3206,
3231 PseudoVFSGNJX_VV_M8_E32 = 3207,
3232 PseudoVFSGNJX_VV_M8_E32_MASK = 3208,
3233 PseudoVFSGNJX_VV_M8_E64 = 3209,
3234 PseudoVFSGNJX_VV_M8_E64_MASK = 3210,
3235 PseudoVFSGNJX_VV_MF2_E16 = 3211,
3236 PseudoVFSGNJX_VV_MF2_E16_MASK = 3212,
3237 PseudoVFSGNJX_VV_MF2_E32 = 3213,
3238 PseudoVFSGNJX_VV_MF2_E32_MASK = 3214,
3239 PseudoVFSGNJX_VV_MF4_E16 = 3215,
3240 PseudoVFSGNJX_VV_MF4_E16_MASK = 3216,
3241 PseudoVFSGNJ_VFPR16_M1_E16 = 3217,
3242 PseudoVFSGNJ_VFPR16_M1_E16_MASK = 3218,
3243 PseudoVFSGNJ_VFPR16_M2_E16 = 3219,
3244 PseudoVFSGNJ_VFPR16_M2_E16_MASK = 3220,
3245 PseudoVFSGNJ_VFPR16_M4_E16 = 3221,
3246 PseudoVFSGNJ_VFPR16_M4_E16_MASK = 3222,
3247 PseudoVFSGNJ_VFPR16_M8_E16 = 3223,
3248 PseudoVFSGNJ_VFPR16_M8_E16_MASK = 3224,
3249 PseudoVFSGNJ_VFPR16_MF2_E16 = 3225,
3250 PseudoVFSGNJ_VFPR16_MF2_E16_MASK = 3226,
3251 PseudoVFSGNJ_VFPR16_MF4_E16 = 3227,
3252 PseudoVFSGNJ_VFPR16_MF4_E16_MASK = 3228,
3253 PseudoVFSGNJ_VFPR32_M1_E32 = 3229,
3254 PseudoVFSGNJ_VFPR32_M1_E32_MASK = 3230,
3255 PseudoVFSGNJ_VFPR32_M2_E32 = 3231,
3256 PseudoVFSGNJ_VFPR32_M2_E32_MASK = 3232,
3257 PseudoVFSGNJ_VFPR32_M4_E32 = 3233,
3258 PseudoVFSGNJ_VFPR32_M4_E32_MASK = 3234,
3259 PseudoVFSGNJ_VFPR32_M8_E32 = 3235,
3260 PseudoVFSGNJ_VFPR32_M8_E32_MASK = 3236,
3261 PseudoVFSGNJ_VFPR32_MF2_E32 = 3237,
3262 PseudoVFSGNJ_VFPR32_MF2_E32_MASK = 3238,
3263 PseudoVFSGNJ_VFPR64_M1_E64 = 3239,
3264 PseudoVFSGNJ_VFPR64_M1_E64_MASK = 3240,
3265 PseudoVFSGNJ_VFPR64_M2_E64 = 3241,
3266 PseudoVFSGNJ_VFPR64_M2_E64_MASK = 3242,
3267 PseudoVFSGNJ_VFPR64_M4_E64 = 3243,
3268 PseudoVFSGNJ_VFPR64_M4_E64_MASK = 3244,
3269 PseudoVFSGNJ_VFPR64_M8_E64 = 3245,
3270 PseudoVFSGNJ_VFPR64_M8_E64_MASK = 3246,
3271 PseudoVFSGNJ_VV_M1_E16 = 3247,
3272 PseudoVFSGNJ_VV_M1_E16_MASK = 3248,
3273 PseudoVFSGNJ_VV_M1_E32 = 3249,
3274 PseudoVFSGNJ_VV_M1_E32_MASK = 3250,
3275 PseudoVFSGNJ_VV_M1_E64 = 3251,
3276 PseudoVFSGNJ_VV_M1_E64_MASK = 3252,
3277 PseudoVFSGNJ_VV_M2_E16 = 3253,
3278 PseudoVFSGNJ_VV_M2_E16_MASK = 3254,
3279 PseudoVFSGNJ_VV_M2_E32 = 3255,
3280 PseudoVFSGNJ_VV_M2_E32_MASK = 3256,
3281 PseudoVFSGNJ_VV_M2_E64 = 3257,
3282 PseudoVFSGNJ_VV_M2_E64_MASK = 3258,
3283 PseudoVFSGNJ_VV_M4_E16 = 3259,
3284 PseudoVFSGNJ_VV_M4_E16_MASK = 3260,
3285 PseudoVFSGNJ_VV_M4_E32 = 3261,
3286 PseudoVFSGNJ_VV_M4_E32_MASK = 3262,
3287 PseudoVFSGNJ_VV_M4_E64 = 3263,
3288 PseudoVFSGNJ_VV_M4_E64_MASK = 3264,
3289 PseudoVFSGNJ_VV_M8_E16 = 3265,
3290 PseudoVFSGNJ_VV_M8_E16_MASK = 3266,
3291 PseudoVFSGNJ_VV_M8_E32 = 3267,
3292 PseudoVFSGNJ_VV_M8_E32_MASK = 3268,
3293 PseudoVFSGNJ_VV_M8_E64 = 3269,
3294 PseudoVFSGNJ_VV_M8_E64_MASK = 3270,
3295 PseudoVFSGNJ_VV_MF2_E16 = 3271,
3296 PseudoVFSGNJ_VV_MF2_E16_MASK = 3272,
3297 PseudoVFSGNJ_VV_MF2_E32 = 3273,
3298 PseudoVFSGNJ_VV_MF2_E32_MASK = 3274,
3299 PseudoVFSGNJ_VV_MF4_E16 = 3275,
3300 PseudoVFSGNJ_VV_MF4_E16_MASK = 3276,
3301 PseudoVFSLIDE1DOWN_VFPR16_M1 = 3277,
3302 PseudoVFSLIDE1DOWN_VFPR16_M1_MASK = 3278,
3303 PseudoVFSLIDE1DOWN_VFPR16_M2 = 3279,
3304 PseudoVFSLIDE1DOWN_VFPR16_M2_MASK = 3280,
3305 PseudoVFSLIDE1DOWN_VFPR16_M4 = 3281,
3306 PseudoVFSLIDE1DOWN_VFPR16_M4_MASK = 3282,
3307 PseudoVFSLIDE1DOWN_VFPR16_M8 = 3283,
3308 PseudoVFSLIDE1DOWN_VFPR16_M8_MASK = 3284,
3309 PseudoVFSLIDE1DOWN_VFPR16_MF2 = 3285,
3310 PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK = 3286,
3311 PseudoVFSLIDE1DOWN_VFPR16_MF4 = 3287,
3312 PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK = 3288,
3313 PseudoVFSLIDE1DOWN_VFPR32_M1 = 3289,
3314 PseudoVFSLIDE1DOWN_VFPR32_M1_MASK = 3290,
3315 PseudoVFSLIDE1DOWN_VFPR32_M2 = 3291,
3316 PseudoVFSLIDE1DOWN_VFPR32_M2_MASK = 3292,
3317 PseudoVFSLIDE1DOWN_VFPR32_M4 = 3293,
3318 PseudoVFSLIDE1DOWN_VFPR32_M4_MASK = 3294,
3319 PseudoVFSLIDE1DOWN_VFPR32_M8 = 3295,
3320 PseudoVFSLIDE1DOWN_VFPR32_M8_MASK = 3296,
3321 PseudoVFSLIDE1DOWN_VFPR32_MF2 = 3297,
3322 PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK = 3298,
3323 PseudoVFSLIDE1DOWN_VFPR64_M1 = 3299,
3324 PseudoVFSLIDE1DOWN_VFPR64_M1_MASK = 3300,
3325 PseudoVFSLIDE1DOWN_VFPR64_M2 = 3301,
3326 PseudoVFSLIDE1DOWN_VFPR64_M2_MASK = 3302,
3327 PseudoVFSLIDE1DOWN_VFPR64_M4 = 3303,
3328 PseudoVFSLIDE1DOWN_VFPR64_M4_MASK = 3304,
3329 PseudoVFSLIDE1DOWN_VFPR64_M8 = 3305,
3330 PseudoVFSLIDE1DOWN_VFPR64_M8_MASK = 3306,
3331 PseudoVFSLIDE1UP_VFPR16_M1 = 3307,
3332 PseudoVFSLIDE1UP_VFPR16_M1_MASK = 3308,
3333 PseudoVFSLIDE1UP_VFPR16_M2 = 3309,
3334 PseudoVFSLIDE1UP_VFPR16_M2_MASK = 3310,
3335 PseudoVFSLIDE1UP_VFPR16_M4 = 3311,
3336 PseudoVFSLIDE1UP_VFPR16_M4_MASK = 3312,
3337 PseudoVFSLIDE1UP_VFPR16_M8 = 3313,
3338 PseudoVFSLIDE1UP_VFPR16_M8_MASK = 3314,
3339 PseudoVFSLIDE1UP_VFPR16_MF2 = 3315,
3340 PseudoVFSLIDE1UP_VFPR16_MF2_MASK = 3316,
3341 PseudoVFSLIDE1UP_VFPR16_MF4 = 3317,
3342 PseudoVFSLIDE1UP_VFPR16_MF4_MASK = 3318,
3343 PseudoVFSLIDE1UP_VFPR32_M1 = 3319,
3344 PseudoVFSLIDE1UP_VFPR32_M1_MASK = 3320,
3345 PseudoVFSLIDE1UP_VFPR32_M2 = 3321,
3346 PseudoVFSLIDE1UP_VFPR32_M2_MASK = 3322,
3347 PseudoVFSLIDE1UP_VFPR32_M4 = 3323,
3348 PseudoVFSLIDE1UP_VFPR32_M4_MASK = 3324,
3349 PseudoVFSLIDE1UP_VFPR32_M8 = 3325,
3350 PseudoVFSLIDE1UP_VFPR32_M8_MASK = 3326,
3351 PseudoVFSLIDE1UP_VFPR32_MF2 = 3327,
3352 PseudoVFSLIDE1UP_VFPR32_MF2_MASK = 3328,
3353 PseudoVFSLIDE1UP_VFPR64_M1 = 3329,
3354 PseudoVFSLIDE1UP_VFPR64_M1_MASK = 3330,
3355 PseudoVFSLIDE1UP_VFPR64_M2 = 3331,
3356 PseudoVFSLIDE1UP_VFPR64_M2_MASK = 3332,
3357 PseudoVFSLIDE1UP_VFPR64_M4 = 3333,
3358 PseudoVFSLIDE1UP_VFPR64_M4_MASK = 3334,
3359 PseudoVFSLIDE1UP_VFPR64_M8 = 3335,
3360 PseudoVFSLIDE1UP_VFPR64_M8_MASK = 3336,
3361 PseudoVFSQRT_V_M1_E16 = 3337,
3362 PseudoVFSQRT_V_M1_E16_MASK = 3338,
3363 PseudoVFSQRT_V_M1_E32 = 3339,
3364 PseudoVFSQRT_V_M1_E32_MASK = 3340,
3365 PseudoVFSQRT_V_M1_E64 = 3341,
3366 PseudoVFSQRT_V_M1_E64_MASK = 3342,
3367 PseudoVFSQRT_V_M2_E16 = 3343,
3368 PseudoVFSQRT_V_M2_E16_MASK = 3344,
3369 PseudoVFSQRT_V_M2_E32 = 3345,
3370 PseudoVFSQRT_V_M2_E32_MASK = 3346,
3371 PseudoVFSQRT_V_M2_E64 = 3347,
3372 PseudoVFSQRT_V_M2_E64_MASK = 3348,
3373 PseudoVFSQRT_V_M4_E16 = 3349,
3374 PseudoVFSQRT_V_M4_E16_MASK = 3350,
3375 PseudoVFSQRT_V_M4_E32 = 3351,
3376 PseudoVFSQRT_V_M4_E32_MASK = 3352,
3377 PseudoVFSQRT_V_M4_E64 = 3353,
3378 PseudoVFSQRT_V_M4_E64_MASK = 3354,
3379 PseudoVFSQRT_V_M8_E16 = 3355,
3380 PseudoVFSQRT_V_M8_E16_MASK = 3356,
3381 PseudoVFSQRT_V_M8_E32 = 3357,
3382 PseudoVFSQRT_V_M8_E32_MASK = 3358,
3383 PseudoVFSQRT_V_M8_E64 = 3359,
3384 PseudoVFSQRT_V_M8_E64_MASK = 3360,
3385 PseudoVFSQRT_V_MF2_E16 = 3361,
3386 PseudoVFSQRT_V_MF2_E16_MASK = 3362,
3387 PseudoVFSQRT_V_MF2_E32 = 3363,
3388 PseudoVFSQRT_V_MF2_E32_MASK = 3364,
3389 PseudoVFSQRT_V_MF4_E16 = 3365,
3390 PseudoVFSQRT_V_MF4_E16_MASK = 3366,
3391 PseudoVFSUB_VFPR16_M1_E16 = 3367,
3392 PseudoVFSUB_VFPR16_M1_E16_MASK = 3368,
3393 PseudoVFSUB_VFPR16_M2_E16 = 3369,
3394 PseudoVFSUB_VFPR16_M2_E16_MASK = 3370,
3395 PseudoVFSUB_VFPR16_M4_E16 = 3371,
3396 PseudoVFSUB_VFPR16_M4_E16_MASK = 3372,
3397 PseudoVFSUB_VFPR16_M8_E16 = 3373,
3398 PseudoVFSUB_VFPR16_M8_E16_MASK = 3374,
3399 PseudoVFSUB_VFPR16_MF2_E16 = 3375,
3400 PseudoVFSUB_VFPR16_MF2_E16_MASK = 3376,
3401 PseudoVFSUB_VFPR16_MF4_E16 = 3377,
3402 PseudoVFSUB_VFPR16_MF4_E16_MASK = 3378,
3403 PseudoVFSUB_VFPR32_M1_E32 = 3379,
3404 PseudoVFSUB_VFPR32_M1_E32_MASK = 3380,
3405 PseudoVFSUB_VFPR32_M2_E32 = 3381,
3406 PseudoVFSUB_VFPR32_M2_E32_MASK = 3382,
3407 PseudoVFSUB_VFPR32_M4_E32 = 3383,
3408 PseudoVFSUB_VFPR32_M4_E32_MASK = 3384,
3409 PseudoVFSUB_VFPR32_M8_E32 = 3385,
3410 PseudoVFSUB_VFPR32_M8_E32_MASK = 3386,
3411 PseudoVFSUB_VFPR32_MF2_E32 = 3387,
3412 PseudoVFSUB_VFPR32_MF2_E32_MASK = 3388,
3413 PseudoVFSUB_VFPR64_M1_E64 = 3389,
3414 PseudoVFSUB_VFPR64_M1_E64_MASK = 3390,
3415 PseudoVFSUB_VFPR64_M2_E64 = 3391,
3416 PseudoVFSUB_VFPR64_M2_E64_MASK = 3392,
3417 PseudoVFSUB_VFPR64_M4_E64 = 3393,
3418 PseudoVFSUB_VFPR64_M4_E64_MASK = 3394,
3419 PseudoVFSUB_VFPR64_M8_E64 = 3395,
3420 PseudoVFSUB_VFPR64_M8_E64_MASK = 3396,
3421 PseudoVFSUB_VV_M1_E16 = 3397,
3422 PseudoVFSUB_VV_M1_E16_MASK = 3398,
3423 PseudoVFSUB_VV_M1_E32 = 3399,
3424 PseudoVFSUB_VV_M1_E32_MASK = 3400,
3425 PseudoVFSUB_VV_M1_E64 = 3401,
3426 PseudoVFSUB_VV_M1_E64_MASK = 3402,
3427 PseudoVFSUB_VV_M2_E16 = 3403,
3428 PseudoVFSUB_VV_M2_E16_MASK = 3404,
3429 PseudoVFSUB_VV_M2_E32 = 3405,
3430 PseudoVFSUB_VV_M2_E32_MASK = 3406,
3431 PseudoVFSUB_VV_M2_E64 = 3407,
3432 PseudoVFSUB_VV_M2_E64_MASK = 3408,
3433 PseudoVFSUB_VV_M4_E16 = 3409,
3434 PseudoVFSUB_VV_M4_E16_MASK = 3410,
3435 PseudoVFSUB_VV_M4_E32 = 3411,
3436 PseudoVFSUB_VV_M4_E32_MASK = 3412,
3437 PseudoVFSUB_VV_M4_E64 = 3413,
3438 PseudoVFSUB_VV_M4_E64_MASK = 3414,
3439 PseudoVFSUB_VV_M8_E16 = 3415,
3440 PseudoVFSUB_VV_M8_E16_MASK = 3416,
3441 PseudoVFSUB_VV_M8_E32 = 3417,
3442 PseudoVFSUB_VV_M8_E32_MASK = 3418,
3443 PseudoVFSUB_VV_M8_E64 = 3419,
3444 PseudoVFSUB_VV_M8_E64_MASK = 3420,
3445 PseudoVFSUB_VV_MF2_E16 = 3421,
3446 PseudoVFSUB_VV_MF2_E16_MASK = 3422,
3447 PseudoVFSUB_VV_MF2_E32 = 3423,
3448 PseudoVFSUB_VV_MF2_E32_MASK = 3424,
3449 PseudoVFSUB_VV_MF4_E16 = 3425,
3450 PseudoVFSUB_VV_MF4_E16_MASK = 3426,
3451 PseudoVFWADD_VFPR16_M1_E16 = 3427,
3452 PseudoVFWADD_VFPR16_M1_E16_MASK = 3428,
3453 PseudoVFWADD_VFPR16_M2_E16 = 3429,
3454 PseudoVFWADD_VFPR16_M2_E16_MASK = 3430,
3455 PseudoVFWADD_VFPR16_M4_E16 = 3431,
3456 PseudoVFWADD_VFPR16_M4_E16_MASK = 3432,
3457 PseudoVFWADD_VFPR16_MF2_E16 = 3433,
3458 PseudoVFWADD_VFPR16_MF2_E16_MASK = 3434,
3459 PseudoVFWADD_VFPR16_MF4_E16 = 3435,
3460 PseudoVFWADD_VFPR16_MF4_E16_MASK = 3436,
3461 PseudoVFWADD_VFPR32_M1_E32 = 3437,
3462 PseudoVFWADD_VFPR32_M1_E32_MASK = 3438,
3463 PseudoVFWADD_VFPR32_M2_E32 = 3439,
3464 PseudoVFWADD_VFPR32_M2_E32_MASK = 3440,
3465 PseudoVFWADD_VFPR32_M4_E32 = 3441,
3466 PseudoVFWADD_VFPR32_M4_E32_MASK = 3442,
3467 PseudoVFWADD_VFPR32_MF2_E32 = 3443,
3468 PseudoVFWADD_VFPR32_MF2_E32_MASK = 3444,
3469 PseudoVFWADD_VV_M1_E16 = 3445,
3470 PseudoVFWADD_VV_M1_E16_MASK = 3446,
3471 PseudoVFWADD_VV_M1_E32 = 3447,
3472 PseudoVFWADD_VV_M1_E32_MASK = 3448,
3473 PseudoVFWADD_VV_M2_E16 = 3449,
3474 PseudoVFWADD_VV_M2_E16_MASK = 3450,
3475 PseudoVFWADD_VV_M2_E32 = 3451,
3476 PseudoVFWADD_VV_M2_E32_MASK = 3452,
3477 PseudoVFWADD_VV_M4_E16 = 3453,
3478 PseudoVFWADD_VV_M4_E16_MASK = 3454,
3479 PseudoVFWADD_VV_M4_E32 = 3455,
3480 PseudoVFWADD_VV_M4_E32_MASK = 3456,
3481 PseudoVFWADD_VV_MF2_E16 = 3457,
3482 PseudoVFWADD_VV_MF2_E16_MASK = 3458,
3483 PseudoVFWADD_VV_MF2_E32 = 3459,
3484 PseudoVFWADD_VV_MF2_E32_MASK = 3460,
3485 PseudoVFWADD_VV_MF4_E16 = 3461,
3486 PseudoVFWADD_VV_MF4_E16_MASK = 3462,
3487 PseudoVFWADD_WFPR16_M1_E16 = 3463,
3488 PseudoVFWADD_WFPR16_M1_E16_MASK = 3464,
3489 PseudoVFWADD_WFPR16_M2_E16 = 3465,
3490 PseudoVFWADD_WFPR16_M2_E16_MASK = 3466,
3491 PseudoVFWADD_WFPR16_M4_E16 = 3467,
3492 PseudoVFWADD_WFPR16_M4_E16_MASK = 3468,
3493 PseudoVFWADD_WFPR16_MF2_E16 = 3469,
3494 PseudoVFWADD_WFPR16_MF2_E16_MASK = 3470,
3495 PseudoVFWADD_WFPR16_MF4_E16 = 3471,
3496 PseudoVFWADD_WFPR16_MF4_E16_MASK = 3472,
3497 PseudoVFWADD_WFPR32_M1_E32 = 3473,
3498 PseudoVFWADD_WFPR32_M1_E32_MASK = 3474,
3499 PseudoVFWADD_WFPR32_M2_E32 = 3475,
3500 PseudoVFWADD_WFPR32_M2_E32_MASK = 3476,
3501 PseudoVFWADD_WFPR32_M4_E32 = 3477,
3502 PseudoVFWADD_WFPR32_M4_E32_MASK = 3478,
3503 PseudoVFWADD_WFPR32_MF2_E32 = 3479,
3504 PseudoVFWADD_WFPR32_MF2_E32_MASK = 3480,
3505 PseudoVFWADD_WV_M1_E16 = 3481,
3506 PseudoVFWADD_WV_M1_E16_MASK = 3482,
3507 PseudoVFWADD_WV_M1_E16_MASK_TIED = 3483,
3508 PseudoVFWADD_WV_M1_E16_TIED = 3484,
3509 PseudoVFWADD_WV_M1_E32 = 3485,
3510 PseudoVFWADD_WV_M1_E32_MASK = 3486,
3511 PseudoVFWADD_WV_M1_E32_MASK_TIED = 3487,
3512 PseudoVFWADD_WV_M1_E32_TIED = 3488,
3513 PseudoVFWADD_WV_M2_E16 = 3489,
3514 PseudoVFWADD_WV_M2_E16_MASK = 3490,
3515 PseudoVFWADD_WV_M2_E16_MASK_TIED = 3491,
3516 PseudoVFWADD_WV_M2_E16_TIED = 3492,
3517 PseudoVFWADD_WV_M2_E32 = 3493,
3518 PseudoVFWADD_WV_M2_E32_MASK = 3494,
3519 PseudoVFWADD_WV_M2_E32_MASK_TIED = 3495,
3520 PseudoVFWADD_WV_M2_E32_TIED = 3496,
3521 PseudoVFWADD_WV_M4_E16 = 3497,
3522 PseudoVFWADD_WV_M4_E16_MASK = 3498,
3523 PseudoVFWADD_WV_M4_E16_MASK_TIED = 3499,
3524 PseudoVFWADD_WV_M4_E16_TIED = 3500,
3525 PseudoVFWADD_WV_M4_E32 = 3501,
3526 PseudoVFWADD_WV_M4_E32_MASK = 3502,
3527 PseudoVFWADD_WV_M4_E32_MASK_TIED = 3503,
3528 PseudoVFWADD_WV_M4_E32_TIED = 3504,
3529 PseudoVFWADD_WV_MF2_E16 = 3505,
3530 PseudoVFWADD_WV_MF2_E16_MASK = 3506,
3531 PseudoVFWADD_WV_MF2_E16_MASK_TIED = 3507,
3532 PseudoVFWADD_WV_MF2_E16_TIED = 3508,
3533 PseudoVFWADD_WV_MF2_E32 = 3509,
3534 PseudoVFWADD_WV_MF2_E32_MASK = 3510,
3535 PseudoVFWADD_WV_MF2_E32_MASK_TIED = 3511,
3536 PseudoVFWADD_WV_MF2_E32_TIED = 3512,
3537 PseudoVFWADD_WV_MF4_E16 = 3513,
3538 PseudoVFWADD_WV_MF4_E16_MASK = 3514,
3539 PseudoVFWADD_WV_MF4_E16_MASK_TIED = 3515,
3540 PseudoVFWADD_WV_MF4_E16_TIED = 3516,
3541 PseudoVFWCVTBF16_F_F_V_M1_E16 = 3517,
3542 PseudoVFWCVTBF16_F_F_V_M1_E16_MASK = 3518,
3543 PseudoVFWCVTBF16_F_F_V_M1_E32 = 3519,
3544 PseudoVFWCVTBF16_F_F_V_M1_E32_MASK = 3520,
3545 PseudoVFWCVTBF16_F_F_V_M2_E16 = 3521,
3546 PseudoVFWCVTBF16_F_F_V_M2_E16_MASK = 3522,
3547 PseudoVFWCVTBF16_F_F_V_M2_E32 = 3523,
3548 PseudoVFWCVTBF16_F_F_V_M2_E32_MASK = 3524,
3549 PseudoVFWCVTBF16_F_F_V_M4_E16 = 3525,
3550 PseudoVFWCVTBF16_F_F_V_M4_E16_MASK = 3526,
3551 PseudoVFWCVTBF16_F_F_V_M4_E32 = 3527,
3552 PseudoVFWCVTBF16_F_F_V_M4_E32_MASK = 3528,
3553 PseudoVFWCVTBF16_F_F_V_MF2_E16 = 3529,
3554 PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK = 3530,
3555 PseudoVFWCVTBF16_F_F_V_MF2_E32 = 3531,
3556 PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK = 3532,
3557 PseudoVFWCVTBF16_F_F_V_MF4_E16 = 3533,
3558 PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK = 3534,
3559 PseudoVFWCVT_F_F_V_M1_E16 = 3535,
3560 PseudoVFWCVT_F_F_V_M1_E16_MASK = 3536,
3561 PseudoVFWCVT_F_F_V_M1_E32 = 3537,
3562 PseudoVFWCVT_F_F_V_M1_E32_MASK = 3538,
3563 PseudoVFWCVT_F_F_V_M2_E16 = 3539,
3564 PseudoVFWCVT_F_F_V_M2_E16_MASK = 3540,
3565 PseudoVFWCVT_F_F_V_M2_E32 = 3541,
3566 PseudoVFWCVT_F_F_V_M2_E32_MASK = 3542,
3567 PseudoVFWCVT_F_F_V_M4_E16 = 3543,
3568 PseudoVFWCVT_F_F_V_M4_E16_MASK = 3544,
3569 PseudoVFWCVT_F_F_V_M4_E32 = 3545,
3570 PseudoVFWCVT_F_F_V_M4_E32_MASK = 3546,
3571 PseudoVFWCVT_F_F_V_MF2_E16 = 3547,
3572 PseudoVFWCVT_F_F_V_MF2_E16_MASK = 3548,
3573 PseudoVFWCVT_F_F_V_MF2_E32 = 3549,
3574 PseudoVFWCVT_F_F_V_MF2_E32_MASK = 3550,
3575 PseudoVFWCVT_F_F_V_MF4_E16 = 3551,
3576 PseudoVFWCVT_F_F_V_MF4_E16_MASK = 3552,
3577 PseudoVFWCVT_F_XU_V_M1_E16 = 3553,
3578 PseudoVFWCVT_F_XU_V_M1_E16_MASK = 3554,
3579 PseudoVFWCVT_F_XU_V_M1_E32 = 3555,
3580 PseudoVFWCVT_F_XU_V_M1_E32_MASK = 3556,
3581 PseudoVFWCVT_F_XU_V_M1_E8 = 3557,
3582 PseudoVFWCVT_F_XU_V_M1_E8_MASK = 3558,
3583 PseudoVFWCVT_F_XU_V_M2_E16 = 3559,
3584 PseudoVFWCVT_F_XU_V_M2_E16_MASK = 3560,
3585 PseudoVFWCVT_F_XU_V_M2_E32 = 3561,
3586 PseudoVFWCVT_F_XU_V_M2_E32_MASK = 3562,
3587 PseudoVFWCVT_F_XU_V_M2_E8 = 3563,
3588 PseudoVFWCVT_F_XU_V_M2_E8_MASK = 3564,
3589 PseudoVFWCVT_F_XU_V_M4_E16 = 3565,
3590 PseudoVFWCVT_F_XU_V_M4_E16_MASK = 3566,
3591 PseudoVFWCVT_F_XU_V_M4_E32 = 3567,
3592 PseudoVFWCVT_F_XU_V_M4_E32_MASK = 3568,
3593 PseudoVFWCVT_F_XU_V_M4_E8 = 3569,
3594 PseudoVFWCVT_F_XU_V_M4_E8_MASK = 3570,
3595 PseudoVFWCVT_F_XU_V_MF2_E16 = 3571,
3596 PseudoVFWCVT_F_XU_V_MF2_E16_MASK = 3572,
3597 PseudoVFWCVT_F_XU_V_MF2_E32 = 3573,
3598 PseudoVFWCVT_F_XU_V_MF2_E32_MASK = 3574,
3599 PseudoVFWCVT_F_XU_V_MF2_E8 = 3575,
3600 PseudoVFWCVT_F_XU_V_MF2_E8_MASK = 3576,
3601 PseudoVFWCVT_F_XU_V_MF4_E16 = 3577,
3602 PseudoVFWCVT_F_XU_V_MF4_E16_MASK = 3578,
3603 PseudoVFWCVT_F_XU_V_MF4_E8 = 3579,
3604 PseudoVFWCVT_F_XU_V_MF4_E8_MASK = 3580,
3605 PseudoVFWCVT_F_XU_V_MF8_E8 = 3581,
3606 PseudoVFWCVT_F_XU_V_MF8_E8_MASK = 3582,
3607 PseudoVFWCVT_F_X_V_M1_E16 = 3583,
3608 PseudoVFWCVT_F_X_V_M1_E16_MASK = 3584,
3609 PseudoVFWCVT_F_X_V_M1_E32 = 3585,
3610 PseudoVFWCVT_F_X_V_M1_E32_MASK = 3586,
3611 PseudoVFWCVT_F_X_V_M1_E8 = 3587,
3612 PseudoVFWCVT_F_X_V_M1_E8_MASK = 3588,
3613 PseudoVFWCVT_F_X_V_M2_E16 = 3589,
3614 PseudoVFWCVT_F_X_V_M2_E16_MASK = 3590,
3615 PseudoVFWCVT_F_X_V_M2_E32 = 3591,
3616 PseudoVFWCVT_F_X_V_M2_E32_MASK = 3592,
3617 PseudoVFWCVT_F_X_V_M2_E8 = 3593,
3618 PseudoVFWCVT_F_X_V_M2_E8_MASK = 3594,
3619 PseudoVFWCVT_F_X_V_M4_E16 = 3595,
3620 PseudoVFWCVT_F_X_V_M4_E16_MASK = 3596,
3621 PseudoVFWCVT_F_X_V_M4_E32 = 3597,
3622 PseudoVFWCVT_F_X_V_M4_E32_MASK = 3598,
3623 PseudoVFWCVT_F_X_V_M4_E8 = 3599,
3624 PseudoVFWCVT_F_X_V_M4_E8_MASK = 3600,
3625 PseudoVFWCVT_F_X_V_MF2_E16 = 3601,
3626 PseudoVFWCVT_F_X_V_MF2_E16_MASK = 3602,
3627 PseudoVFWCVT_F_X_V_MF2_E32 = 3603,
3628 PseudoVFWCVT_F_X_V_MF2_E32_MASK = 3604,
3629 PseudoVFWCVT_F_X_V_MF2_E8 = 3605,
3630 PseudoVFWCVT_F_X_V_MF2_E8_MASK = 3606,
3631 PseudoVFWCVT_F_X_V_MF4_E16 = 3607,
3632 PseudoVFWCVT_F_X_V_MF4_E16_MASK = 3608,
3633 PseudoVFWCVT_F_X_V_MF4_E8 = 3609,
3634 PseudoVFWCVT_F_X_V_MF4_E8_MASK = 3610,
3635 PseudoVFWCVT_F_X_V_MF8_E8 = 3611,
3636 PseudoVFWCVT_F_X_V_MF8_E8_MASK = 3612,
3637 PseudoVFWCVT_RM_XU_F_V_M1 = 3613,
3638 PseudoVFWCVT_RM_XU_F_V_M1_MASK = 3614,
3639 PseudoVFWCVT_RM_XU_F_V_M2 = 3615,
3640 PseudoVFWCVT_RM_XU_F_V_M2_MASK = 3616,
3641 PseudoVFWCVT_RM_XU_F_V_M4 = 3617,
3642 PseudoVFWCVT_RM_XU_F_V_M4_MASK = 3618,
3643 PseudoVFWCVT_RM_XU_F_V_MF2 = 3619,
3644 PseudoVFWCVT_RM_XU_F_V_MF2_MASK = 3620,
3645 PseudoVFWCVT_RM_XU_F_V_MF4 = 3621,
3646 PseudoVFWCVT_RM_XU_F_V_MF4_MASK = 3622,
3647 PseudoVFWCVT_RM_X_F_V_M1 = 3623,
3648 PseudoVFWCVT_RM_X_F_V_M1_MASK = 3624,
3649 PseudoVFWCVT_RM_X_F_V_M2 = 3625,
3650 PseudoVFWCVT_RM_X_F_V_M2_MASK = 3626,
3651 PseudoVFWCVT_RM_X_F_V_M4 = 3627,
3652 PseudoVFWCVT_RM_X_F_V_M4_MASK = 3628,
3653 PseudoVFWCVT_RM_X_F_V_MF2 = 3629,
3654 PseudoVFWCVT_RM_X_F_V_MF2_MASK = 3630,
3655 PseudoVFWCVT_RM_X_F_V_MF4 = 3631,
3656 PseudoVFWCVT_RM_X_F_V_MF4_MASK = 3632,
3657 PseudoVFWCVT_RTZ_XU_F_V_M1 = 3633,
3658 PseudoVFWCVT_RTZ_XU_F_V_M1_MASK = 3634,
3659 PseudoVFWCVT_RTZ_XU_F_V_M2 = 3635,
3660 PseudoVFWCVT_RTZ_XU_F_V_M2_MASK = 3636,
3661 PseudoVFWCVT_RTZ_XU_F_V_M4 = 3637,
3662 PseudoVFWCVT_RTZ_XU_F_V_M4_MASK = 3638,
3663 PseudoVFWCVT_RTZ_XU_F_V_MF2 = 3639,
3664 PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK = 3640,
3665 PseudoVFWCVT_RTZ_XU_F_V_MF4 = 3641,
3666 PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK = 3642,
3667 PseudoVFWCVT_RTZ_X_F_V_M1 = 3643,
3668 PseudoVFWCVT_RTZ_X_F_V_M1_MASK = 3644,
3669 PseudoVFWCVT_RTZ_X_F_V_M2 = 3645,
3670 PseudoVFWCVT_RTZ_X_F_V_M2_MASK = 3646,
3671 PseudoVFWCVT_RTZ_X_F_V_M4 = 3647,
3672 PseudoVFWCVT_RTZ_X_F_V_M4_MASK = 3648,
3673 PseudoVFWCVT_RTZ_X_F_V_MF2 = 3649,
3674 PseudoVFWCVT_RTZ_X_F_V_MF2_MASK = 3650,
3675 PseudoVFWCVT_RTZ_X_F_V_MF4 = 3651,
3676 PseudoVFWCVT_RTZ_X_F_V_MF4_MASK = 3652,
3677 PseudoVFWCVT_XU_F_V_M1 = 3653,
3678 PseudoVFWCVT_XU_F_V_M1_MASK = 3654,
3679 PseudoVFWCVT_XU_F_V_M2 = 3655,
3680 PseudoVFWCVT_XU_F_V_M2_MASK = 3656,
3681 PseudoVFWCVT_XU_F_V_M4 = 3657,
3682 PseudoVFWCVT_XU_F_V_M4_MASK = 3658,
3683 PseudoVFWCVT_XU_F_V_MF2 = 3659,
3684 PseudoVFWCVT_XU_F_V_MF2_MASK = 3660,
3685 PseudoVFWCVT_XU_F_V_MF4 = 3661,
3686 PseudoVFWCVT_XU_F_V_MF4_MASK = 3662,
3687 PseudoVFWCVT_X_F_V_M1 = 3663,
3688 PseudoVFWCVT_X_F_V_M1_MASK = 3664,
3689 PseudoVFWCVT_X_F_V_M2 = 3665,
3690 PseudoVFWCVT_X_F_V_M2_MASK = 3666,
3691 PseudoVFWCVT_X_F_V_M4 = 3667,
3692 PseudoVFWCVT_X_F_V_M4_MASK = 3668,
3693 PseudoVFWCVT_X_F_V_MF2 = 3669,
3694 PseudoVFWCVT_X_F_V_MF2_MASK = 3670,
3695 PseudoVFWCVT_X_F_V_MF4 = 3671,
3696 PseudoVFWCVT_X_F_V_MF4_MASK = 3672,
3697 PseudoVFWMACCBF16_VFPR16_M1_E16 = 3673,
3698 PseudoVFWMACCBF16_VFPR16_M1_E16_MASK = 3674,
3699 PseudoVFWMACCBF16_VFPR16_M2_E16 = 3675,
3700 PseudoVFWMACCBF16_VFPR16_M2_E16_MASK = 3676,
3701 PseudoVFWMACCBF16_VFPR16_M4_E16 = 3677,
3702 PseudoVFWMACCBF16_VFPR16_M4_E16_MASK = 3678,
3703 PseudoVFWMACCBF16_VFPR16_MF2_E16 = 3679,
3704 PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK = 3680,
3705 PseudoVFWMACCBF16_VFPR16_MF4_E16 = 3681,
3706 PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK = 3682,
3707 PseudoVFWMACCBF16_VV_M1_E16 = 3683,
3708 PseudoVFWMACCBF16_VV_M1_E16_MASK = 3684,
3709 PseudoVFWMACCBF16_VV_M1_E32 = 3685,
3710 PseudoVFWMACCBF16_VV_M1_E32_MASK = 3686,
3711 PseudoVFWMACCBF16_VV_M2_E16 = 3687,
3712 PseudoVFWMACCBF16_VV_M2_E16_MASK = 3688,
3713 PseudoVFWMACCBF16_VV_M2_E32 = 3689,
3714 PseudoVFWMACCBF16_VV_M2_E32_MASK = 3690,
3715 PseudoVFWMACCBF16_VV_M4_E16 = 3691,
3716 PseudoVFWMACCBF16_VV_M4_E16_MASK = 3692,
3717 PseudoVFWMACCBF16_VV_M4_E32 = 3693,
3718 PseudoVFWMACCBF16_VV_M4_E32_MASK = 3694,
3719 PseudoVFWMACCBF16_VV_MF2_E16 = 3695,
3720 PseudoVFWMACCBF16_VV_MF2_E16_MASK = 3696,
3721 PseudoVFWMACCBF16_VV_MF2_E32 = 3697,
3722 PseudoVFWMACCBF16_VV_MF2_E32_MASK = 3698,
3723 PseudoVFWMACCBF16_VV_MF4_E16 = 3699,
3724 PseudoVFWMACCBF16_VV_MF4_E16_MASK = 3700,
3725 PseudoVFWMACC_4x4x4_M1 = 3701,
3726 PseudoVFWMACC_4x4x4_M2 = 3702,
3727 PseudoVFWMACC_4x4x4_M4 = 3703,
3728 PseudoVFWMACC_4x4x4_M8 = 3704,
3729 PseudoVFWMACC_4x4x4_MF2 = 3705,
3730 PseudoVFWMACC_4x4x4_MF4 = 3706,
3731 PseudoVFWMACC_VFPR16_M1_E16 = 3707,
3732 PseudoVFWMACC_VFPR16_M1_E16_MASK = 3708,
3733 PseudoVFWMACC_VFPR16_M2_E16 = 3709,
3734 PseudoVFWMACC_VFPR16_M2_E16_MASK = 3710,
3735 PseudoVFWMACC_VFPR16_M4_E16 = 3711,
3736 PseudoVFWMACC_VFPR16_M4_E16_MASK = 3712,
3737 PseudoVFWMACC_VFPR16_MF2_E16 = 3713,
3738 PseudoVFWMACC_VFPR16_MF2_E16_MASK = 3714,
3739 PseudoVFWMACC_VFPR16_MF4_E16 = 3715,
3740 PseudoVFWMACC_VFPR16_MF4_E16_MASK = 3716,
3741 PseudoVFWMACC_VFPR32_M1_E32 = 3717,
3742 PseudoVFWMACC_VFPR32_M1_E32_MASK = 3718,
3743 PseudoVFWMACC_VFPR32_M2_E32 = 3719,
3744 PseudoVFWMACC_VFPR32_M2_E32_MASK = 3720,
3745 PseudoVFWMACC_VFPR32_M4_E32 = 3721,
3746 PseudoVFWMACC_VFPR32_M4_E32_MASK = 3722,
3747 PseudoVFWMACC_VFPR32_MF2_E32 = 3723,
3748 PseudoVFWMACC_VFPR32_MF2_E32_MASK = 3724,
3749 PseudoVFWMACC_VV_M1_E16 = 3725,
3750 PseudoVFWMACC_VV_M1_E16_MASK = 3726,
3751 PseudoVFWMACC_VV_M1_E32 = 3727,
3752 PseudoVFWMACC_VV_M1_E32_MASK = 3728,
3753 PseudoVFWMACC_VV_M2_E16 = 3729,
3754 PseudoVFWMACC_VV_M2_E16_MASK = 3730,
3755 PseudoVFWMACC_VV_M2_E32 = 3731,
3756 PseudoVFWMACC_VV_M2_E32_MASK = 3732,
3757 PseudoVFWMACC_VV_M4_E16 = 3733,
3758 PseudoVFWMACC_VV_M4_E16_MASK = 3734,
3759 PseudoVFWMACC_VV_M4_E32 = 3735,
3760 PseudoVFWMACC_VV_M4_E32_MASK = 3736,
3761 PseudoVFWMACC_VV_MF2_E16 = 3737,
3762 PseudoVFWMACC_VV_MF2_E16_MASK = 3738,
3763 PseudoVFWMACC_VV_MF2_E32 = 3739,
3764 PseudoVFWMACC_VV_MF2_E32_MASK = 3740,
3765 PseudoVFWMACC_VV_MF4_E16 = 3741,
3766 PseudoVFWMACC_VV_MF4_E16_MASK = 3742,
3767 PseudoVFWMSAC_VFPR16_M1_E16 = 3743,
3768 PseudoVFWMSAC_VFPR16_M1_E16_MASK = 3744,
3769 PseudoVFWMSAC_VFPR16_M2_E16 = 3745,
3770 PseudoVFWMSAC_VFPR16_M2_E16_MASK = 3746,
3771 PseudoVFWMSAC_VFPR16_M4_E16 = 3747,
3772 PseudoVFWMSAC_VFPR16_M4_E16_MASK = 3748,
3773 PseudoVFWMSAC_VFPR16_MF2_E16 = 3749,
3774 PseudoVFWMSAC_VFPR16_MF2_E16_MASK = 3750,
3775 PseudoVFWMSAC_VFPR16_MF4_E16 = 3751,
3776 PseudoVFWMSAC_VFPR16_MF4_E16_MASK = 3752,
3777 PseudoVFWMSAC_VFPR32_M1_E32 = 3753,
3778 PseudoVFWMSAC_VFPR32_M1_E32_MASK = 3754,
3779 PseudoVFWMSAC_VFPR32_M2_E32 = 3755,
3780 PseudoVFWMSAC_VFPR32_M2_E32_MASK = 3756,
3781 PseudoVFWMSAC_VFPR32_M4_E32 = 3757,
3782 PseudoVFWMSAC_VFPR32_M4_E32_MASK = 3758,
3783 PseudoVFWMSAC_VFPR32_MF2_E32 = 3759,
3784 PseudoVFWMSAC_VFPR32_MF2_E32_MASK = 3760,
3785 PseudoVFWMSAC_VV_M1_E16 = 3761,
3786 PseudoVFWMSAC_VV_M1_E16_MASK = 3762,
3787 PseudoVFWMSAC_VV_M1_E32 = 3763,
3788 PseudoVFWMSAC_VV_M1_E32_MASK = 3764,
3789 PseudoVFWMSAC_VV_M2_E16 = 3765,
3790 PseudoVFWMSAC_VV_M2_E16_MASK = 3766,
3791 PseudoVFWMSAC_VV_M2_E32 = 3767,
3792 PseudoVFWMSAC_VV_M2_E32_MASK = 3768,
3793 PseudoVFWMSAC_VV_M4_E16 = 3769,
3794 PseudoVFWMSAC_VV_M4_E16_MASK = 3770,
3795 PseudoVFWMSAC_VV_M4_E32 = 3771,
3796 PseudoVFWMSAC_VV_M4_E32_MASK = 3772,
3797 PseudoVFWMSAC_VV_MF2_E16 = 3773,
3798 PseudoVFWMSAC_VV_MF2_E16_MASK = 3774,
3799 PseudoVFWMSAC_VV_MF2_E32 = 3775,
3800 PseudoVFWMSAC_VV_MF2_E32_MASK = 3776,
3801 PseudoVFWMSAC_VV_MF4_E16 = 3777,
3802 PseudoVFWMSAC_VV_MF4_E16_MASK = 3778,
3803 PseudoVFWMUL_VFPR16_M1_E16 = 3779,
3804 PseudoVFWMUL_VFPR16_M1_E16_MASK = 3780,
3805 PseudoVFWMUL_VFPR16_M2_E16 = 3781,
3806 PseudoVFWMUL_VFPR16_M2_E16_MASK = 3782,
3807 PseudoVFWMUL_VFPR16_M4_E16 = 3783,
3808 PseudoVFWMUL_VFPR16_M4_E16_MASK = 3784,
3809 PseudoVFWMUL_VFPR16_MF2_E16 = 3785,
3810 PseudoVFWMUL_VFPR16_MF2_E16_MASK = 3786,
3811 PseudoVFWMUL_VFPR16_MF4_E16 = 3787,
3812 PseudoVFWMUL_VFPR16_MF4_E16_MASK = 3788,
3813 PseudoVFWMUL_VFPR32_M1_E32 = 3789,
3814 PseudoVFWMUL_VFPR32_M1_E32_MASK = 3790,
3815 PseudoVFWMUL_VFPR32_M2_E32 = 3791,
3816 PseudoVFWMUL_VFPR32_M2_E32_MASK = 3792,
3817 PseudoVFWMUL_VFPR32_M4_E32 = 3793,
3818 PseudoVFWMUL_VFPR32_M4_E32_MASK = 3794,
3819 PseudoVFWMUL_VFPR32_MF2_E32 = 3795,
3820 PseudoVFWMUL_VFPR32_MF2_E32_MASK = 3796,
3821 PseudoVFWMUL_VV_M1_E16 = 3797,
3822 PseudoVFWMUL_VV_M1_E16_MASK = 3798,
3823 PseudoVFWMUL_VV_M1_E32 = 3799,
3824 PseudoVFWMUL_VV_M1_E32_MASK = 3800,
3825 PseudoVFWMUL_VV_M2_E16 = 3801,
3826 PseudoVFWMUL_VV_M2_E16_MASK = 3802,
3827 PseudoVFWMUL_VV_M2_E32 = 3803,
3828 PseudoVFWMUL_VV_M2_E32_MASK = 3804,
3829 PseudoVFWMUL_VV_M4_E16 = 3805,
3830 PseudoVFWMUL_VV_M4_E16_MASK = 3806,
3831 PseudoVFWMUL_VV_M4_E32 = 3807,
3832 PseudoVFWMUL_VV_M4_E32_MASK = 3808,
3833 PseudoVFWMUL_VV_MF2_E16 = 3809,
3834 PseudoVFWMUL_VV_MF2_E16_MASK = 3810,
3835 PseudoVFWMUL_VV_MF2_E32 = 3811,
3836 PseudoVFWMUL_VV_MF2_E32_MASK = 3812,
3837 PseudoVFWMUL_VV_MF4_E16 = 3813,
3838 PseudoVFWMUL_VV_MF4_E16_MASK = 3814,
3839 PseudoVFWNMACC_VFPR16_M1_E16 = 3815,
3840 PseudoVFWNMACC_VFPR16_M1_E16_MASK = 3816,
3841 PseudoVFWNMACC_VFPR16_M2_E16 = 3817,
3842 PseudoVFWNMACC_VFPR16_M2_E16_MASK = 3818,
3843 PseudoVFWNMACC_VFPR16_M4_E16 = 3819,
3844 PseudoVFWNMACC_VFPR16_M4_E16_MASK = 3820,
3845 PseudoVFWNMACC_VFPR16_MF2_E16 = 3821,
3846 PseudoVFWNMACC_VFPR16_MF2_E16_MASK = 3822,
3847 PseudoVFWNMACC_VFPR16_MF4_E16 = 3823,
3848 PseudoVFWNMACC_VFPR16_MF4_E16_MASK = 3824,
3849 PseudoVFWNMACC_VFPR32_M1_E32 = 3825,
3850 PseudoVFWNMACC_VFPR32_M1_E32_MASK = 3826,
3851 PseudoVFWNMACC_VFPR32_M2_E32 = 3827,
3852 PseudoVFWNMACC_VFPR32_M2_E32_MASK = 3828,
3853 PseudoVFWNMACC_VFPR32_M4_E32 = 3829,
3854 PseudoVFWNMACC_VFPR32_M4_E32_MASK = 3830,
3855 PseudoVFWNMACC_VFPR32_MF2_E32 = 3831,
3856 PseudoVFWNMACC_VFPR32_MF2_E32_MASK = 3832,
3857 PseudoVFWNMACC_VV_M1_E16 = 3833,
3858 PseudoVFWNMACC_VV_M1_E16_MASK = 3834,
3859 PseudoVFWNMACC_VV_M1_E32 = 3835,
3860 PseudoVFWNMACC_VV_M1_E32_MASK = 3836,
3861 PseudoVFWNMACC_VV_M2_E16 = 3837,
3862 PseudoVFWNMACC_VV_M2_E16_MASK = 3838,
3863 PseudoVFWNMACC_VV_M2_E32 = 3839,
3864 PseudoVFWNMACC_VV_M2_E32_MASK = 3840,
3865 PseudoVFWNMACC_VV_M4_E16 = 3841,
3866 PseudoVFWNMACC_VV_M4_E16_MASK = 3842,
3867 PseudoVFWNMACC_VV_M4_E32 = 3843,
3868 PseudoVFWNMACC_VV_M4_E32_MASK = 3844,
3869 PseudoVFWNMACC_VV_MF2_E16 = 3845,
3870 PseudoVFWNMACC_VV_MF2_E16_MASK = 3846,
3871 PseudoVFWNMACC_VV_MF2_E32 = 3847,
3872 PseudoVFWNMACC_VV_MF2_E32_MASK = 3848,
3873 PseudoVFWNMACC_VV_MF4_E16 = 3849,
3874 PseudoVFWNMACC_VV_MF4_E16_MASK = 3850,
3875 PseudoVFWNMSAC_VFPR16_M1_E16 = 3851,
3876 PseudoVFWNMSAC_VFPR16_M1_E16_MASK = 3852,
3877 PseudoVFWNMSAC_VFPR16_M2_E16 = 3853,
3878 PseudoVFWNMSAC_VFPR16_M2_E16_MASK = 3854,
3879 PseudoVFWNMSAC_VFPR16_M4_E16 = 3855,
3880 PseudoVFWNMSAC_VFPR16_M4_E16_MASK = 3856,
3881 PseudoVFWNMSAC_VFPR16_MF2_E16 = 3857,
3882 PseudoVFWNMSAC_VFPR16_MF2_E16_MASK = 3858,
3883 PseudoVFWNMSAC_VFPR16_MF4_E16 = 3859,
3884 PseudoVFWNMSAC_VFPR16_MF4_E16_MASK = 3860,
3885 PseudoVFWNMSAC_VFPR32_M1_E32 = 3861,
3886 PseudoVFWNMSAC_VFPR32_M1_E32_MASK = 3862,
3887 PseudoVFWNMSAC_VFPR32_M2_E32 = 3863,
3888 PseudoVFWNMSAC_VFPR32_M2_E32_MASK = 3864,
3889 PseudoVFWNMSAC_VFPR32_M4_E32 = 3865,
3890 PseudoVFWNMSAC_VFPR32_M4_E32_MASK = 3866,
3891 PseudoVFWNMSAC_VFPR32_MF2_E32 = 3867,
3892 PseudoVFWNMSAC_VFPR32_MF2_E32_MASK = 3868,
3893 PseudoVFWNMSAC_VV_M1_E16 = 3869,
3894 PseudoVFWNMSAC_VV_M1_E16_MASK = 3870,
3895 PseudoVFWNMSAC_VV_M1_E32 = 3871,
3896 PseudoVFWNMSAC_VV_M1_E32_MASK = 3872,
3897 PseudoVFWNMSAC_VV_M2_E16 = 3873,
3898 PseudoVFWNMSAC_VV_M2_E16_MASK = 3874,
3899 PseudoVFWNMSAC_VV_M2_E32 = 3875,
3900 PseudoVFWNMSAC_VV_M2_E32_MASK = 3876,
3901 PseudoVFWNMSAC_VV_M4_E16 = 3877,
3902 PseudoVFWNMSAC_VV_M4_E16_MASK = 3878,
3903 PseudoVFWNMSAC_VV_M4_E32 = 3879,
3904 PseudoVFWNMSAC_VV_M4_E32_MASK = 3880,
3905 PseudoVFWNMSAC_VV_MF2_E16 = 3881,
3906 PseudoVFWNMSAC_VV_MF2_E16_MASK = 3882,
3907 PseudoVFWNMSAC_VV_MF2_E32 = 3883,
3908 PseudoVFWNMSAC_VV_MF2_E32_MASK = 3884,
3909 PseudoVFWNMSAC_VV_MF4_E16 = 3885,
3910 PseudoVFWNMSAC_VV_MF4_E16_MASK = 3886,
3911 PseudoVFWREDOSUM_VS_M1_E16 = 3887,
3912 PseudoVFWREDOSUM_VS_M1_E16_MASK = 3888,
3913 PseudoVFWREDOSUM_VS_M1_E32 = 3889,
3914 PseudoVFWREDOSUM_VS_M1_E32_MASK = 3890,
3915 PseudoVFWREDOSUM_VS_M2_E16 = 3891,
3916 PseudoVFWREDOSUM_VS_M2_E16_MASK = 3892,
3917 PseudoVFWREDOSUM_VS_M2_E32 = 3893,
3918 PseudoVFWREDOSUM_VS_M2_E32_MASK = 3894,
3919 PseudoVFWREDOSUM_VS_M4_E16 = 3895,
3920 PseudoVFWREDOSUM_VS_M4_E16_MASK = 3896,
3921 PseudoVFWREDOSUM_VS_M4_E32 = 3897,
3922 PseudoVFWREDOSUM_VS_M4_E32_MASK = 3898,
3923 PseudoVFWREDOSUM_VS_M8_E16 = 3899,
3924 PseudoVFWREDOSUM_VS_M8_E16_MASK = 3900,
3925 PseudoVFWREDOSUM_VS_M8_E32 = 3901,
3926 PseudoVFWREDOSUM_VS_M8_E32_MASK = 3902,
3927 PseudoVFWREDOSUM_VS_MF2_E16 = 3903,
3928 PseudoVFWREDOSUM_VS_MF2_E16_MASK = 3904,
3929 PseudoVFWREDOSUM_VS_MF2_E32 = 3905,
3930 PseudoVFWREDOSUM_VS_MF2_E32_MASK = 3906,
3931 PseudoVFWREDOSUM_VS_MF4_E16 = 3907,
3932 PseudoVFWREDOSUM_VS_MF4_E16_MASK = 3908,
3933 PseudoVFWREDUSUM_VS_M1_E16 = 3909,
3934 PseudoVFWREDUSUM_VS_M1_E16_MASK = 3910,
3935 PseudoVFWREDUSUM_VS_M1_E32 = 3911,
3936 PseudoVFWREDUSUM_VS_M1_E32_MASK = 3912,
3937 PseudoVFWREDUSUM_VS_M2_E16 = 3913,
3938 PseudoVFWREDUSUM_VS_M2_E16_MASK = 3914,
3939 PseudoVFWREDUSUM_VS_M2_E32 = 3915,
3940 PseudoVFWREDUSUM_VS_M2_E32_MASK = 3916,
3941 PseudoVFWREDUSUM_VS_M4_E16 = 3917,
3942 PseudoVFWREDUSUM_VS_M4_E16_MASK = 3918,
3943 PseudoVFWREDUSUM_VS_M4_E32 = 3919,
3944 PseudoVFWREDUSUM_VS_M4_E32_MASK = 3920,
3945 PseudoVFWREDUSUM_VS_M8_E16 = 3921,
3946 PseudoVFWREDUSUM_VS_M8_E16_MASK = 3922,
3947 PseudoVFWREDUSUM_VS_M8_E32 = 3923,
3948 PseudoVFWREDUSUM_VS_M8_E32_MASK = 3924,
3949 PseudoVFWREDUSUM_VS_MF2_E16 = 3925,
3950 PseudoVFWREDUSUM_VS_MF2_E16_MASK = 3926,
3951 PseudoVFWREDUSUM_VS_MF2_E32 = 3927,
3952 PseudoVFWREDUSUM_VS_MF2_E32_MASK = 3928,
3953 PseudoVFWREDUSUM_VS_MF4_E16 = 3929,
3954 PseudoVFWREDUSUM_VS_MF4_E16_MASK = 3930,
3955 PseudoVFWSUB_VFPR16_M1_E16 = 3931,
3956 PseudoVFWSUB_VFPR16_M1_E16_MASK = 3932,
3957 PseudoVFWSUB_VFPR16_M2_E16 = 3933,
3958 PseudoVFWSUB_VFPR16_M2_E16_MASK = 3934,
3959 PseudoVFWSUB_VFPR16_M4_E16 = 3935,
3960 PseudoVFWSUB_VFPR16_M4_E16_MASK = 3936,
3961 PseudoVFWSUB_VFPR16_MF2_E16 = 3937,
3962 PseudoVFWSUB_VFPR16_MF2_E16_MASK = 3938,
3963 PseudoVFWSUB_VFPR16_MF4_E16 = 3939,
3964 PseudoVFWSUB_VFPR16_MF4_E16_MASK = 3940,
3965 PseudoVFWSUB_VFPR32_M1_E32 = 3941,
3966 PseudoVFWSUB_VFPR32_M1_E32_MASK = 3942,
3967 PseudoVFWSUB_VFPR32_M2_E32 = 3943,
3968 PseudoVFWSUB_VFPR32_M2_E32_MASK = 3944,
3969 PseudoVFWSUB_VFPR32_M4_E32 = 3945,
3970 PseudoVFWSUB_VFPR32_M4_E32_MASK = 3946,
3971 PseudoVFWSUB_VFPR32_MF2_E32 = 3947,
3972 PseudoVFWSUB_VFPR32_MF2_E32_MASK = 3948,
3973 PseudoVFWSUB_VV_M1_E16 = 3949,
3974 PseudoVFWSUB_VV_M1_E16_MASK = 3950,
3975 PseudoVFWSUB_VV_M1_E32 = 3951,
3976 PseudoVFWSUB_VV_M1_E32_MASK = 3952,
3977 PseudoVFWSUB_VV_M2_E16 = 3953,
3978 PseudoVFWSUB_VV_M2_E16_MASK = 3954,
3979 PseudoVFWSUB_VV_M2_E32 = 3955,
3980 PseudoVFWSUB_VV_M2_E32_MASK = 3956,
3981 PseudoVFWSUB_VV_M4_E16 = 3957,
3982 PseudoVFWSUB_VV_M4_E16_MASK = 3958,
3983 PseudoVFWSUB_VV_M4_E32 = 3959,
3984 PseudoVFWSUB_VV_M4_E32_MASK = 3960,
3985 PseudoVFWSUB_VV_MF2_E16 = 3961,
3986 PseudoVFWSUB_VV_MF2_E16_MASK = 3962,
3987 PseudoVFWSUB_VV_MF2_E32 = 3963,
3988 PseudoVFWSUB_VV_MF2_E32_MASK = 3964,
3989 PseudoVFWSUB_VV_MF4_E16 = 3965,
3990 PseudoVFWSUB_VV_MF4_E16_MASK = 3966,
3991 PseudoVFWSUB_WFPR16_M1_E16 = 3967,
3992 PseudoVFWSUB_WFPR16_M1_E16_MASK = 3968,
3993 PseudoVFWSUB_WFPR16_M2_E16 = 3969,
3994 PseudoVFWSUB_WFPR16_M2_E16_MASK = 3970,
3995 PseudoVFWSUB_WFPR16_M4_E16 = 3971,
3996 PseudoVFWSUB_WFPR16_M4_E16_MASK = 3972,
3997 PseudoVFWSUB_WFPR16_MF2_E16 = 3973,
3998 PseudoVFWSUB_WFPR16_MF2_E16_MASK = 3974,
3999 PseudoVFWSUB_WFPR16_MF4_E16 = 3975,
4000 PseudoVFWSUB_WFPR16_MF4_E16_MASK = 3976,
4001 PseudoVFWSUB_WFPR32_M1_E32 = 3977,
4002 PseudoVFWSUB_WFPR32_M1_E32_MASK = 3978,
4003 PseudoVFWSUB_WFPR32_M2_E32 = 3979,
4004 PseudoVFWSUB_WFPR32_M2_E32_MASK = 3980,
4005 PseudoVFWSUB_WFPR32_M4_E32 = 3981,
4006 PseudoVFWSUB_WFPR32_M4_E32_MASK = 3982,
4007 PseudoVFWSUB_WFPR32_MF2_E32 = 3983,
4008 PseudoVFWSUB_WFPR32_MF2_E32_MASK = 3984,
4009 PseudoVFWSUB_WV_M1_E16 = 3985,
4010 PseudoVFWSUB_WV_M1_E16_MASK = 3986,
4011 PseudoVFWSUB_WV_M1_E16_MASK_TIED = 3987,
4012 PseudoVFWSUB_WV_M1_E16_TIED = 3988,
4013 PseudoVFWSUB_WV_M1_E32 = 3989,
4014 PseudoVFWSUB_WV_M1_E32_MASK = 3990,
4015 PseudoVFWSUB_WV_M1_E32_MASK_TIED = 3991,
4016 PseudoVFWSUB_WV_M1_E32_TIED = 3992,
4017 PseudoVFWSUB_WV_M2_E16 = 3993,
4018 PseudoVFWSUB_WV_M2_E16_MASK = 3994,
4019 PseudoVFWSUB_WV_M2_E16_MASK_TIED = 3995,
4020 PseudoVFWSUB_WV_M2_E16_TIED = 3996,
4021 PseudoVFWSUB_WV_M2_E32 = 3997,
4022 PseudoVFWSUB_WV_M2_E32_MASK = 3998,
4023 PseudoVFWSUB_WV_M2_E32_MASK_TIED = 3999,
4024 PseudoVFWSUB_WV_M2_E32_TIED = 4000,
4025 PseudoVFWSUB_WV_M4_E16 = 4001,
4026 PseudoVFWSUB_WV_M4_E16_MASK = 4002,
4027 PseudoVFWSUB_WV_M4_E16_MASK_TIED = 4003,
4028 PseudoVFWSUB_WV_M4_E16_TIED = 4004,
4029 PseudoVFWSUB_WV_M4_E32 = 4005,
4030 PseudoVFWSUB_WV_M4_E32_MASK = 4006,
4031 PseudoVFWSUB_WV_M4_E32_MASK_TIED = 4007,
4032 PseudoVFWSUB_WV_M4_E32_TIED = 4008,
4033 PseudoVFWSUB_WV_MF2_E16 = 4009,
4034 PseudoVFWSUB_WV_MF2_E16_MASK = 4010,
4035 PseudoVFWSUB_WV_MF2_E16_MASK_TIED = 4011,
4036 PseudoVFWSUB_WV_MF2_E16_TIED = 4012,
4037 PseudoVFWSUB_WV_MF2_E32 = 4013,
4038 PseudoVFWSUB_WV_MF2_E32_MASK = 4014,
4039 PseudoVFWSUB_WV_MF2_E32_MASK_TIED = 4015,
4040 PseudoVFWSUB_WV_MF2_E32_TIED = 4016,
4041 PseudoVFWSUB_WV_MF4_E16 = 4017,
4042 PseudoVFWSUB_WV_MF4_E16_MASK = 4018,
4043 PseudoVFWSUB_WV_MF4_E16_MASK_TIED = 4019,
4044 PseudoVFWSUB_WV_MF4_E16_TIED = 4020,
4045 PseudoVGHSH_VV_M1 = 4021,
4046 PseudoVGHSH_VV_M2 = 4022,
4047 PseudoVGHSH_VV_M4 = 4023,
4048 PseudoVGHSH_VV_M8 = 4024,
4049 PseudoVGHSH_VV_MF2 = 4025,
4050 PseudoVGMUL_VV_M1 = 4026,
4051 PseudoVGMUL_VV_M2 = 4027,
4052 PseudoVGMUL_VV_M4 = 4028,
4053 PseudoVGMUL_VV_M8 = 4029,
4054 PseudoVGMUL_VV_MF2 = 4030,
4055 PseudoVID_V_M1 = 4031,
4056 PseudoVID_V_M1_MASK = 4032,
4057 PseudoVID_V_M2 = 4033,
4058 PseudoVID_V_M2_MASK = 4034,
4059 PseudoVID_V_M4 = 4035,
4060 PseudoVID_V_M4_MASK = 4036,
4061 PseudoVID_V_M8 = 4037,
4062 PseudoVID_V_M8_MASK = 4038,
4063 PseudoVID_V_MF2 = 4039,
4064 PseudoVID_V_MF2_MASK = 4040,
4065 PseudoVID_V_MF4 = 4041,
4066 PseudoVID_V_MF4_MASK = 4042,
4067 PseudoVID_V_MF8 = 4043,
4068 PseudoVID_V_MF8_MASK = 4044,
4069 PseudoVIOTA_M_M1 = 4045,
4070 PseudoVIOTA_M_M1_MASK = 4046,
4071 PseudoVIOTA_M_M2 = 4047,
4072 PseudoVIOTA_M_M2_MASK = 4048,
4073 PseudoVIOTA_M_M4 = 4049,
4074 PseudoVIOTA_M_M4_MASK = 4050,
4075 PseudoVIOTA_M_M8 = 4051,
4076 PseudoVIOTA_M_M8_MASK = 4052,
4077 PseudoVIOTA_M_MF2 = 4053,
4078 PseudoVIOTA_M_MF2_MASK = 4054,
4079 PseudoVIOTA_M_MF4 = 4055,
4080 PseudoVIOTA_M_MF4_MASK = 4056,
4081 PseudoVIOTA_M_MF8 = 4057,
4082 PseudoVIOTA_M_MF8_MASK = 4058,
4083 PseudoVLE16FF_V_M1 = 4059,
4084 PseudoVLE16FF_V_M1_MASK = 4060,
4085 PseudoVLE16FF_V_M2 = 4061,
4086 PseudoVLE16FF_V_M2_MASK = 4062,
4087 PseudoVLE16FF_V_M4 = 4063,
4088 PseudoVLE16FF_V_M4_MASK = 4064,
4089 PseudoVLE16FF_V_M8 = 4065,
4090 PseudoVLE16FF_V_M8_MASK = 4066,
4091 PseudoVLE16FF_V_MF2 = 4067,
4092 PseudoVLE16FF_V_MF2_MASK = 4068,
4093 PseudoVLE16FF_V_MF4 = 4069,
4094 PseudoVLE16FF_V_MF4_MASK = 4070,
4095 PseudoVLE16_V_M1 = 4071,
4096 PseudoVLE16_V_M1_MASK = 4072,
4097 PseudoVLE16_V_M2 = 4073,
4098 PseudoVLE16_V_M2_MASK = 4074,
4099 PseudoVLE16_V_M4 = 4075,
4100 PseudoVLE16_V_M4_MASK = 4076,
4101 PseudoVLE16_V_M8 = 4077,
4102 PseudoVLE16_V_M8_MASK = 4078,
4103 PseudoVLE16_V_MF2 = 4079,
4104 PseudoVLE16_V_MF2_MASK = 4080,
4105 PseudoVLE16_V_MF4 = 4081,
4106 PseudoVLE16_V_MF4_MASK = 4082,
4107 PseudoVLE32FF_V_M1 = 4083,
4108 PseudoVLE32FF_V_M1_MASK = 4084,
4109 PseudoVLE32FF_V_M2 = 4085,
4110 PseudoVLE32FF_V_M2_MASK = 4086,
4111 PseudoVLE32FF_V_M4 = 4087,
4112 PseudoVLE32FF_V_M4_MASK = 4088,
4113 PseudoVLE32FF_V_M8 = 4089,
4114 PseudoVLE32FF_V_M8_MASK = 4090,
4115 PseudoVLE32FF_V_MF2 = 4091,
4116 PseudoVLE32FF_V_MF2_MASK = 4092,
4117 PseudoVLE32_V_M1 = 4093,
4118 PseudoVLE32_V_M1_MASK = 4094,
4119 PseudoVLE32_V_M2 = 4095,
4120 PseudoVLE32_V_M2_MASK = 4096,
4121 PseudoVLE32_V_M4 = 4097,
4122 PseudoVLE32_V_M4_MASK = 4098,
4123 PseudoVLE32_V_M8 = 4099,
4124 PseudoVLE32_V_M8_MASK = 4100,
4125 PseudoVLE32_V_MF2 = 4101,
4126 PseudoVLE32_V_MF2_MASK = 4102,
4127 PseudoVLE64FF_V_M1 = 4103,
4128 PseudoVLE64FF_V_M1_MASK = 4104,
4129 PseudoVLE64FF_V_M2 = 4105,
4130 PseudoVLE64FF_V_M2_MASK = 4106,
4131 PseudoVLE64FF_V_M4 = 4107,
4132 PseudoVLE64FF_V_M4_MASK = 4108,
4133 PseudoVLE64FF_V_M8 = 4109,
4134 PseudoVLE64FF_V_M8_MASK = 4110,
4135 PseudoVLE64_V_M1 = 4111,
4136 PseudoVLE64_V_M1_MASK = 4112,
4137 PseudoVLE64_V_M2 = 4113,
4138 PseudoVLE64_V_M2_MASK = 4114,
4139 PseudoVLE64_V_M4 = 4115,
4140 PseudoVLE64_V_M4_MASK = 4116,
4141 PseudoVLE64_V_M8 = 4117,
4142 PseudoVLE64_V_M8_MASK = 4118,
4143 PseudoVLE8FF_V_M1 = 4119,
4144 PseudoVLE8FF_V_M1_MASK = 4120,
4145 PseudoVLE8FF_V_M2 = 4121,
4146 PseudoVLE8FF_V_M2_MASK = 4122,
4147 PseudoVLE8FF_V_M4 = 4123,
4148 PseudoVLE8FF_V_M4_MASK = 4124,
4149 PseudoVLE8FF_V_M8 = 4125,
4150 PseudoVLE8FF_V_M8_MASK = 4126,
4151 PseudoVLE8FF_V_MF2 = 4127,
4152 PseudoVLE8FF_V_MF2_MASK = 4128,
4153 PseudoVLE8FF_V_MF4 = 4129,
4154 PseudoVLE8FF_V_MF4_MASK = 4130,
4155 PseudoVLE8FF_V_MF8 = 4131,
4156 PseudoVLE8FF_V_MF8_MASK = 4132,
4157 PseudoVLE8_V_M1 = 4133,
4158 PseudoVLE8_V_M1_MASK = 4134,
4159 PseudoVLE8_V_M2 = 4135,
4160 PseudoVLE8_V_M2_MASK = 4136,
4161 PseudoVLE8_V_M4 = 4137,
4162 PseudoVLE8_V_M4_MASK = 4138,
4163 PseudoVLE8_V_M8 = 4139,
4164 PseudoVLE8_V_M8_MASK = 4140,
4165 PseudoVLE8_V_MF2 = 4141,
4166 PseudoVLE8_V_MF2_MASK = 4142,
4167 PseudoVLE8_V_MF4 = 4143,
4168 PseudoVLE8_V_MF4_MASK = 4144,
4169 PseudoVLE8_V_MF8 = 4145,
4170 PseudoVLE8_V_MF8_MASK = 4146,
4171 PseudoVLM_V_B1 = 4147,
4172 PseudoVLM_V_B16 = 4148,
4173 PseudoVLM_V_B2 = 4149,
4174 PseudoVLM_V_B32 = 4150,
4175 PseudoVLM_V_B4 = 4151,
4176 PseudoVLM_V_B64 = 4152,
4177 PseudoVLM_V_B8 = 4153,
4178 PseudoVLOXEI16_V_M1_M1 = 4154,
4179 PseudoVLOXEI16_V_M1_M1_MASK = 4155,
4180 PseudoVLOXEI16_V_M1_M2 = 4156,
4181 PseudoVLOXEI16_V_M1_M2_MASK = 4157,
4182 PseudoVLOXEI16_V_M1_M4 = 4158,
4183 PseudoVLOXEI16_V_M1_M4_MASK = 4159,
4184 PseudoVLOXEI16_V_M1_MF2 = 4160,
4185 PseudoVLOXEI16_V_M1_MF2_MASK = 4161,
4186 PseudoVLOXEI16_V_M2_M1 = 4162,
4187 PseudoVLOXEI16_V_M2_M1_MASK = 4163,
4188 PseudoVLOXEI16_V_M2_M2 = 4164,
4189 PseudoVLOXEI16_V_M2_M2_MASK = 4165,
4190 PseudoVLOXEI16_V_M2_M4 = 4166,
4191 PseudoVLOXEI16_V_M2_M4_MASK = 4167,
4192 PseudoVLOXEI16_V_M2_M8 = 4168,
4193 PseudoVLOXEI16_V_M2_M8_MASK = 4169,
4194 PseudoVLOXEI16_V_M4_M2 = 4170,
4195 PseudoVLOXEI16_V_M4_M2_MASK = 4171,
4196 PseudoVLOXEI16_V_M4_M4 = 4172,
4197 PseudoVLOXEI16_V_M4_M4_MASK = 4173,
4198 PseudoVLOXEI16_V_M4_M8 = 4174,
4199 PseudoVLOXEI16_V_M4_M8_MASK = 4175,
4200 PseudoVLOXEI16_V_M8_M4 = 4176,
4201 PseudoVLOXEI16_V_M8_M4_MASK = 4177,
4202 PseudoVLOXEI16_V_M8_M8 = 4178,
4203 PseudoVLOXEI16_V_M8_M8_MASK = 4179,
4204 PseudoVLOXEI16_V_MF2_M1 = 4180,
4205 PseudoVLOXEI16_V_MF2_M1_MASK = 4181,
4206 PseudoVLOXEI16_V_MF2_M2 = 4182,
4207 PseudoVLOXEI16_V_MF2_M2_MASK = 4183,
4208 PseudoVLOXEI16_V_MF2_MF2 = 4184,
4209 PseudoVLOXEI16_V_MF2_MF2_MASK = 4185,
4210 PseudoVLOXEI16_V_MF2_MF4 = 4186,
4211 PseudoVLOXEI16_V_MF2_MF4_MASK = 4187,
4212 PseudoVLOXEI16_V_MF4_M1 = 4188,
4213 PseudoVLOXEI16_V_MF4_M1_MASK = 4189,
4214 PseudoVLOXEI16_V_MF4_MF2 = 4190,
4215 PseudoVLOXEI16_V_MF4_MF2_MASK = 4191,
4216 PseudoVLOXEI16_V_MF4_MF4 = 4192,
4217 PseudoVLOXEI16_V_MF4_MF4_MASK = 4193,
4218 PseudoVLOXEI16_V_MF4_MF8 = 4194,
4219 PseudoVLOXEI16_V_MF4_MF8_MASK = 4195,
4220 PseudoVLOXEI32_V_M1_M1 = 4196,
4221 PseudoVLOXEI32_V_M1_M1_MASK = 4197,
4222 PseudoVLOXEI32_V_M1_M2 = 4198,
4223 PseudoVLOXEI32_V_M1_M2_MASK = 4199,
4224 PseudoVLOXEI32_V_M1_MF2 = 4200,
4225 PseudoVLOXEI32_V_M1_MF2_MASK = 4201,
4226 PseudoVLOXEI32_V_M1_MF4 = 4202,
4227 PseudoVLOXEI32_V_M1_MF4_MASK = 4203,
4228 PseudoVLOXEI32_V_M2_M1 = 4204,
4229 PseudoVLOXEI32_V_M2_M1_MASK = 4205,
4230 PseudoVLOXEI32_V_M2_M2 = 4206,
4231 PseudoVLOXEI32_V_M2_M2_MASK = 4207,
4232 PseudoVLOXEI32_V_M2_M4 = 4208,
4233 PseudoVLOXEI32_V_M2_M4_MASK = 4209,
4234 PseudoVLOXEI32_V_M2_MF2 = 4210,
4235 PseudoVLOXEI32_V_M2_MF2_MASK = 4211,
4236 PseudoVLOXEI32_V_M4_M1 = 4212,
4237 PseudoVLOXEI32_V_M4_M1_MASK = 4213,
4238 PseudoVLOXEI32_V_M4_M2 = 4214,
4239 PseudoVLOXEI32_V_M4_M2_MASK = 4215,
4240 PseudoVLOXEI32_V_M4_M4 = 4216,
4241 PseudoVLOXEI32_V_M4_M4_MASK = 4217,
4242 PseudoVLOXEI32_V_M4_M8 = 4218,
4243 PseudoVLOXEI32_V_M4_M8_MASK = 4219,
4244 PseudoVLOXEI32_V_M8_M2 = 4220,
4245 PseudoVLOXEI32_V_M8_M2_MASK = 4221,
4246 PseudoVLOXEI32_V_M8_M4 = 4222,
4247 PseudoVLOXEI32_V_M8_M4_MASK = 4223,
4248 PseudoVLOXEI32_V_M8_M8 = 4224,
4249 PseudoVLOXEI32_V_M8_M8_MASK = 4225,
4250 PseudoVLOXEI32_V_MF2_M1 = 4226,
4251 PseudoVLOXEI32_V_MF2_M1_MASK = 4227,
4252 PseudoVLOXEI32_V_MF2_MF2 = 4228,
4253 PseudoVLOXEI32_V_MF2_MF2_MASK = 4229,
4254 PseudoVLOXEI32_V_MF2_MF4 = 4230,
4255 PseudoVLOXEI32_V_MF2_MF4_MASK = 4231,
4256 PseudoVLOXEI32_V_MF2_MF8 = 4232,
4257 PseudoVLOXEI32_V_MF2_MF8_MASK = 4233,
4258 PseudoVLOXEI64_V_M1_M1 = 4234,
4259 PseudoVLOXEI64_V_M1_M1_MASK = 4235,
4260 PseudoVLOXEI64_V_M1_MF2 = 4236,
4261 PseudoVLOXEI64_V_M1_MF2_MASK = 4237,
4262 PseudoVLOXEI64_V_M1_MF4 = 4238,
4263 PseudoVLOXEI64_V_M1_MF4_MASK = 4239,
4264 PseudoVLOXEI64_V_M1_MF8 = 4240,
4265 PseudoVLOXEI64_V_M1_MF8_MASK = 4241,
4266 PseudoVLOXEI64_V_M2_M1 = 4242,
4267 PseudoVLOXEI64_V_M2_M1_MASK = 4243,
4268 PseudoVLOXEI64_V_M2_M2 = 4244,
4269 PseudoVLOXEI64_V_M2_M2_MASK = 4245,
4270 PseudoVLOXEI64_V_M2_MF2 = 4246,
4271 PseudoVLOXEI64_V_M2_MF2_MASK = 4247,
4272 PseudoVLOXEI64_V_M2_MF4 = 4248,
4273 PseudoVLOXEI64_V_M2_MF4_MASK = 4249,
4274 PseudoVLOXEI64_V_M4_M1 = 4250,
4275 PseudoVLOXEI64_V_M4_M1_MASK = 4251,
4276 PseudoVLOXEI64_V_M4_M2 = 4252,
4277 PseudoVLOXEI64_V_M4_M2_MASK = 4253,
4278 PseudoVLOXEI64_V_M4_M4 = 4254,
4279 PseudoVLOXEI64_V_M4_M4_MASK = 4255,
4280 PseudoVLOXEI64_V_M4_MF2 = 4256,
4281 PseudoVLOXEI64_V_M4_MF2_MASK = 4257,
4282 PseudoVLOXEI64_V_M8_M1 = 4258,
4283 PseudoVLOXEI64_V_M8_M1_MASK = 4259,
4284 PseudoVLOXEI64_V_M8_M2 = 4260,
4285 PseudoVLOXEI64_V_M8_M2_MASK = 4261,
4286 PseudoVLOXEI64_V_M8_M4 = 4262,
4287 PseudoVLOXEI64_V_M8_M4_MASK = 4263,
4288 PseudoVLOXEI64_V_M8_M8 = 4264,
4289 PseudoVLOXEI64_V_M8_M8_MASK = 4265,
4290 PseudoVLOXEI8_V_M1_M1 = 4266,
4291 PseudoVLOXEI8_V_M1_M1_MASK = 4267,
4292 PseudoVLOXEI8_V_M1_M2 = 4268,
4293 PseudoVLOXEI8_V_M1_M2_MASK = 4269,
4294 PseudoVLOXEI8_V_M1_M4 = 4270,
4295 PseudoVLOXEI8_V_M1_M4_MASK = 4271,
4296 PseudoVLOXEI8_V_M1_M8 = 4272,
4297 PseudoVLOXEI8_V_M1_M8_MASK = 4273,
4298 PseudoVLOXEI8_V_M2_M2 = 4274,
4299 PseudoVLOXEI8_V_M2_M2_MASK = 4275,
4300 PseudoVLOXEI8_V_M2_M4 = 4276,
4301 PseudoVLOXEI8_V_M2_M4_MASK = 4277,
4302 PseudoVLOXEI8_V_M2_M8 = 4278,
4303 PseudoVLOXEI8_V_M2_M8_MASK = 4279,
4304 PseudoVLOXEI8_V_M4_M4 = 4280,
4305 PseudoVLOXEI8_V_M4_M4_MASK = 4281,
4306 PseudoVLOXEI8_V_M4_M8 = 4282,
4307 PseudoVLOXEI8_V_M4_M8_MASK = 4283,
4308 PseudoVLOXEI8_V_M8_M8 = 4284,
4309 PseudoVLOXEI8_V_M8_M8_MASK = 4285,
4310 PseudoVLOXEI8_V_MF2_M1 = 4286,
4311 PseudoVLOXEI8_V_MF2_M1_MASK = 4287,
4312 PseudoVLOXEI8_V_MF2_M2 = 4288,
4313 PseudoVLOXEI8_V_MF2_M2_MASK = 4289,
4314 PseudoVLOXEI8_V_MF2_M4 = 4290,
4315 PseudoVLOXEI8_V_MF2_M4_MASK = 4291,
4316 PseudoVLOXEI8_V_MF2_MF2 = 4292,
4317 PseudoVLOXEI8_V_MF2_MF2_MASK = 4293,
4318 PseudoVLOXEI8_V_MF4_M1 = 4294,
4319 PseudoVLOXEI8_V_MF4_M1_MASK = 4295,
4320 PseudoVLOXEI8_V_MF4_M2 = 4296,
4321 PseudoVLOXEI8_V_MF4_M2_MASK = 4297,
4322 PseudoVLOXEI8_V_MF4_MF2 = 4298,
4323 PseudoVLOXEI8_V_MF4_MF2_MASK = 4299,
4324 PseudoVLOXEI8_V_MF4_MF4 = 4300,
4325 PseudoVLOXEI8_V_MF4_MF4_MASK = 4301,
4326 PseudoVLOXEI8_V_MF8_M1 = 4302,
4327 PseudoVLOXEI8_V_MF8_M1_MASK = 4303,
4328 PseudoVLOXEI8_V_MF8_MF2 = 4304,
4329 PseudoVLOXEI8_V_MF8_MF2_MASK = 4305,
4330 PseudoVLOXEI8_V_MF8_MF4 = 4306,
4331 PseudoVLOXEI8_V_MF8_MF4_MASK = 4307,
4332 PseudoVLOXEI8_V_MF8_MF8 = 4308,
4333 PseudoVLOXEI8_V_MF8_MF8_MASK = 4309,
4334 PseudoVLOXSEG2EI16_V_M1_M1 = 4310,
4335 PseudoVLOXSEG2EI16_V_M1_M1_MASK = 4311,
4336 PseudoVLOXSEG2EI16_V_M1_M2 = 4312,
4337 PseudoVLOXSEG2EI16_V_M1_M2_MASK = 4313,
4338 PseudoVLOXSEG2EI16_V_M1_M4 = 4314,
4339 PseudoVLOXSEG2EI16_V_M1_M4_MASK = 4315,
4340 PseudoVLOXSEG2EI16_V_M1_MF2 = 4316,
4341 PseudoVLOXSEG2EI16_V_M1_MF2_MASK = 4317,
4342 PseudoVLOXSEG2EI16_V_M2_M1 = 4318,
4343 PseudoVLOXSEG2EI16_V_M2_M1_MASK = 4319,
4344 PseudoVLOXSEG2EI16_V_M2_M2 = 4320,
4345 PseudoVLOXSEG2EI16_V_M2_M2_MASK = 4321,
4346 PseudoVLOXSEG2EI16_V_M2_M4 = 4322,
4347 PseudoVLOXSEG2EI16_V_M2_M4_MASK = 4323,
4348 PseudoVLOXSEG2EI16_V_M4_M2 = 4324,
4349 PseudoVLOXSEG2EI16_V_M4_M2_MASK = 4325,
4350 PseudoVLOXSEG2EI16_V_M4_M4 = 4326,
4351 PseudoVLOXSEG2EI16_V_M4_M4_MASK = 4327,
4352 PseudoVLOXSEG2EI16_V_M8_M4 = 4328,
4353 PseudoVLOXSEG2EI16_V_M8_M4_MASK = 4329,
4354 PseudoVLOXSEG2EI16_V_MF2_M1 = 4330,
4355 PseudoVLOXSEG2EI16_V_MF2_M1_MASK = 4331,
4356 PseudoVLOXSEG2EI16_V_MF2_M2 = 4332,
4357 PseudoVLOXSEG2EI16_V_MF2_M2_MASK = 4333,
4358 PseudoVLOXSEG2EI16_V_MF2_MF2 = 4334,
4359 PseudoVLOXSEG2EI16_V_MF2_MF2_MASK = 4335,
4360 PseudoVLOXSEG2EI16_V_MF2_MF4 = 4336,
4361 PseudoVLOXSEG2EI16_V_MF2_MF4_MASK = 4337,
4362 PseudoVLOXSEG2EI16_V_MF4_M1 = 4338,
4363 PseudoVLOXSEG2EI16_V_MF4_M1_MASK = 4339,
4364 PseudoVLOXSEG2EI16_V_MF4_MF2 = 4340,
4365 PseudoVLOXSEG2EI16_V_MF4_MF2_MASK = 4341,
4366 PseudoVLOXSEG2EI16_V_MF4_MF4 = 4342,
4367 PseudoVLOXSEG2EI16_V_MF4_MF4_MASK = 4343,
4368 PseudoVLOXSEG2EI16_V_MF4_MF8 = 4344,
4369 PseudoVLOXSEG2EI16_V_MF4_MF8_MASK = 4345,
4370 PseudoVLOXSEG2EI32_V_M1_M1 = 4346,
4371 PseudoVLOXSEG2EI32_V_M1_M1_MASK = 4347,
4372 PseudoVLOXSEG2EI32_V_M1_M2 = 4348,
4373 PseudoVLOXSEG2EI32_V_M1_M2_MASK = 4349,
4374 PseudoVLOXSEG2EI32_V_M1_MF2 = 4350,
4375 PseudoVLOXSEG2EI32_V_M1_MF2_MASK = 4351,
4376 PseudoVLOXSEG2EI32_V_M1_MF4 = 4352,
4377 PseudoVLOXSEG2EI32_V_M1_MF4_MASK = 4353,
4378 PseudoVLOXSEG2EI32_V_M2_M1 = 4354,
4379 PseudoVLOXSEG2EI32_V_M2_M1_MASK = 4355,
4380 PseudoVLOXSEG2EI32_V_M2_M2 = 4356,
4381 PseudoVLOXSEG2EI32_V_M2_M2_MASK = 4357,
4382 PseudoVLOXSEG2EI32_V_M2_M4 = 4358,
4383 PseudoVLOXSEG2EI32_V_M2_M4_MASK = 4359,
4384 PseudoVLOXSEG2EI32_V_M2_MF2 = 4360,
4385 PseudoVLOXSEG2EI32_V_M2_MF2_MASK = 4361,
4386 PseudoVLOXSEG2EI32_V_M4_M1 = 4362,
4387 PseudoVLOXSEG2EI32_V_M4_M1_MASK = 4363,
4388 PseudoVLOXSEG2EI32_V_M4_M2 = 4364,
4389 PseudoVLOXSEG2EI32_V_M4_M2_MASK = 4365,
4390 PseudoVLOXSEG2EI32_V_M4_M4 = 4366,
4391 PseudoVLOXSEG2EI32_V_M4_M4_MASK = 4367,
4392 PseudoVLOXSEG2EI32_V_M8_M2 = 4368,
4393 PseudoVLOXSEG2EI32_V_M8_M2_MASK = 4369,
4394 PseudoVLOXSEG2EI32_V_M8_M4 = 4370,
4395 PseudoVLOXSEG2EI32_V_M8_M4_MASK = 4371,
4396 PseudoVLOXSEG2EI32_V_MF2_M1 = 4372,
4397 PseudoVLOXSEG2EI32_V_MF2_M1_MASK = 4373,
4398 PseudoVLOXSEG2EI32_V_MF2_MF2 = 4374,
4399 PseudoVLOXSEG2EI32_V_MF2_MF2_MASK = 4375,
4400 PseudoVLOXSEG2EI32_V_MF2_MF4 = 4376,
4401 PseudoVLOXSEG2EI32_V_MF2_MF4_MASK = 4377,
4402 PseudoVLOXSEG2EI32_V_MF2_MF8 = 4378,
4403 PseudoVLOXSEG2EI32_V_MF2_MF8_MASK = 4379,
4404 PseudoVLOXSEG2EI64_V_M1_M1 = 4380,
4405 PseudoVLOXSEG2EI64_V_M1_M1_MASK = 4381,
4406 PseudoVLOXSEG2EI64_V_M1_MF2 = 4382,
4407 PseudoVLOXSEG2EI64_V_M1_MF2_MASK = 4383,
4408 PseudoVLOXSEG2EI64_V_M1_MF4 = 4384,
4409 PseudoVLOXSEG2EI64_V_M1_MF4_MASK = 4385,
4410 PseudoVLOXSEG2EI64_V_M1_MF8 = 4386,
4411 PseudoVLOXSEG2EI64_V_M1_MF8_MASK = 4387,
4412 PseudoVLOXSEG2EI64_V_M2_M1 = 4388,
4413 PseudoVLOXSEG2EI64_V_M2_M1_MASK = 4389,
4414 PseudoVLOXSEG2EI64_V_M2_M2 = 4390,
4415 PseudoVLOXSEG2EI64_V_M2_M2_MASK = 4391,
4416 PseudoVLOXSEG2EI64_V_M2_MF2 = 4392,
4417 PseudoVLOXSEG2EI64_V_M2_MF2_MASK = 4393,
4418 PseudoVLOXSEG2EI64_V_M2_MF4 = 4394,
4419 PseudoVLOXSEG2EI64_V_M2_MF4_MASK = 4395,
4420 PseudoVLOXSEG2EI64_V_M4_M1 = 4396,
4421 PseudoVLOXSEG2EI64_V_M4_M1_MASK = 4397,
4422 PseudoVLOXSEG2EI64_V_M4_M2 = 4398,
4423 PseudoVLOXSEG2EI64_V_M4_M2_MASK = 4399,
4424 PseudoVLOXSEG2EI64_V_M4_M4 = 4400,
4425 PseudoVLOXSEG2EI64_V_M4_M4_MASK = 4401,
4426 PseudoVLOXSEG2EI64_V_M4_MF2 = 4402,
4427 PseudoVLOXSEG2EI64_V_M4_MF2_MASK = 4403,
4428 PseudoVLOXSEG2EI64_V_M8_M1 = 4404,
4429 PseudoVLOXSEG2EI64_V_M8_M1_MASK = 4405,
4430 PseudoVLOXSEG2EI64_V_M8_M2 = 4406,
4431 PseudoVLOXSEG2EI64_V_M8_M2_MASK = 4407,
4432 PseudoVLOXSEG2EI64_V_M8_M4 = 4408,
4433 PseudoVLOXSEG2EI64_V_M8_M4_MASK = 4409,
4434 PseudoVLOXSEG2EI8_V_M1_M1 = 4410,
4435 PseudoVLOXSEG2EI8_V_M1_M1_MASK = 4411,
4436 PseudoVLOXSEG2EI8_V_M1_M2 = 4412,
4437 PseudoVLOXSEG2EI8_V_M1_M2_MASK = 4413,
4438 PseudoVLOXSEG2EI8_V_M1_M4 = 4414,
4439 PseudoVLOXSEG2EI8_V_M1_M4_MASK = 4415,
4440 PseudoVLOXSEG2EI8_V_M2_M2 = 4416,
4441 PseudoVLOXSEG2EI8_V_M2_M2_MASK = 4417,
4442 PseudoVLOXSEG2EI8_V_M2_M4 = 4418,
4443 PseudoVLOXSEG2EI8_V_M2_M4_MASK = 4419,
4444 PseudoVLOXSEG2EI8_V_M4_M4 = 4420,
4445 PseudoVLOXSEG2EI8_V_M4_M4_MASK = 4421,
4446 PseudoVLOXSEG2EI8_V_MF2_M1 = 4422,
4447 PseudoVLOXSEG2EI8_V_MF2_M1_MASK = 4423,
4448 PseudoVLOXSEG2EI8_V_MF2_M2 = 4424,
4449 PseudoVLOXSEG2EI8_V_MF2_M2_MASK = 4425,
4450 PseudoVLOXSEG2EI8_V_MF2_M4 = 4426,
4451 PseudoVLOXSEG2EI8_V_MF2_M4_MASK = 4427,
4452 PseudoVLOXSEG2EI8_V_MF2_MF2 = 4428,
4453 PseudoVLOXSEG2EI8_V_MF2_MF2_MASK = 4429,
4454 PseudoVLOXSEG2EI8_V_MF4_M1 = 4430,
4455 PseudoVLOXSEG2EI8_V_MF4_M1_MASK = 4431,
4456 PseudoVLOXSEG2EI8_V_MF4_M2 = 4432,
4457 PseudoVLOXSEG2EI8_V_MF4_M2_MASK = 4433,
4458 PseudoVLOXSEG2EI8_V_MF4_MF2 = 4434,
4459 PseudoVLOXSEG2EI8_V_MF4_MF2_MASK = 4435,
4460 PseudoVLOXSEG2EI8_V_MF4_MF4 = 4436,
4461 PseudoVLOXSEG2EI8_V_MF4_MF4_MASK = 4437,
4462 PseudoVLOXSEG2EI8_V_MF8_M1 = 4438,
4463 PseudoVLOXSEG2EI8_V_MF8_M1_MASK = 4439,
4464 PseudoVLOXSEG2EI8_V_MF8_MF2 = 4440,
4465 PseudoVLOXSEG2EI8_V_MF8_MF2_MASK = 4441,
4466 PseudoVLOXSEG2EI8_V_MF8_MF4 = 4442,
4467 PseudoVLOXSEG2EI8_V_MF8_MF4_MASK = 4443,
4468 PseudoVLOXSEG2EI8_V_MF8_MF8 = 4444,
4469 PseudoVLOXSEG2EI8_V_MF8_MF8_MASK = 4445,
4470 PseudoVLOXSEG3EI16_V_M1_M1 = 4446,
4471 PseudoVLOXSEG3EI16_V_M1_M1_MASK = 4447,
4472 PseudoVLOXSEG3EI16_V_M1_M2 = 4448,
4473 PseudoVLOXSEG3EI16_V_M1_M2_MASK = 4449,
4474 PseudoVLOXSEG3EI16_V_M1_MF2 = 4450,
4475 PseudoVLOXSEG3EI16_V_M1_MF2_MASK = 4451,
4476 PseudoVLOXSEG3EI16_V_M2_M1 = 4452,
4477 PseudoVLOXSEG3EI16_V_M2_M1_MASK = 4453,
4478 PseudoVLOXSEG3EI16_V_M2_M2 = 4454,
4479 PseudoVLOXSEG3EI16_V_M2_M2_MASK = 4455,
4480 PseudoVLOXSEG3EI16_V_M4_M2 = 4456,
4481 PseudoVLOXSEG3EI16_V_M4_M2_MASK = 4457,
4482 PseudoVLOXSEG3EI16_V_MF2_M1 = 4458,
4483 PseudoVLOXSEG3EI16_V_MF2_M1_MASK = 4459,
4484 PseudoVLOXSEG3EI16_V_MF2_M2 = 4460,
4485 PseudoVLOXSEG3EI16_V_MF2_M2_MASK = 4461,
4486 PseudoVLOXSEG3EI16_V_MF2_MF2 = 4462,
4487 PseudoVLOXSEG3EI16_V_MF2_MF2_MASK = 4463,
4488 PseudoVLOXSEG3EI16_V_MF2_MF4 = 4464,
4489 PseudoVLOXSEG3EI16_V_MF2_MF4_MASK = 4465,
4490 PseudoVLOXSEG3EI16_V_MF4_M1 = 4466,
4491 PseudoVLOXSEG3EI16_V_MF4_M1_MASK = 4467,
4492 PseudoVLOXSEG3EI16_V_MF4_MF2 = 4468,
4493 PseudoVLOXSEG3EI16_V_MF4_MF2_MASK = 4469,
4494 PseudoVLOXSEG3EI16_V_MF4_MF4 = 4470,
4495 PseudoVLOXSEG3EI16_V_MF4_MF4_MASK = 4471,
4496 PseudoVLOXSEG3EI16_V_MF4_MF8 = 4472,
4497 PseudoVLOXSEG3EI16_V_MF4_MF8_MASK = 4473,
4498 PseudoVLOXSEG3EI32_V_M1_M1 = 4474,
4499 PseudoVLOXSEG3EI32_V_M1_M1_MASK = 4475,
4500 PseudoVLOXSEG3EI32_V_M1_M2 = 4476,
4501 PseudoVLOXSEG3EI32_V_M1_M2_MASK = 4477,
4502 PseudoVLOXSEG3EI32_V_M1_MF2 = 4478,
4503 PseudoVLOXSEG3EI32_V_M1_MF2_MASK = 4479,
4504 PseudoVLOXSEG3EI32_V_M1_MF4 = 4480,
4505 PseudoVLOXSEG3EI32_V_M1_MF4_MASK = 4481,
4506 PseudoVLOXSEG3EI32_V_M2_M1 = 4482,
4507 PseudoVLOXSEG3EI32_V_M2_M1_MASK = 4483,
4508 PseudoVLOXSEG3EI32_V_M2_M2 = 4484,
4509 PseudoVLOXSEG3EI32_V_M2_M2_MASK = 4485,
4510 PseudoVLOXSEG3EI32_V_M2_MF2 = 4486,
4511 PseudoVLOXSEG3EI32_V_M2_MF2_MASK = 4487,
4512 PseudoVLOXSEG3EI32_V_M4_M1 = 4488,
4513 PseudoVLOXSEG3EI32_V_M4_M1_MASK = 4489,
4514 PseudoVLOXSEG3EI32_V_M4_M2 = 4490,
4515 PseudoVLOXSEG3EI32_V_M4_M2_MASK = 4491,
4516 PseudoVLOXSEG3EI32_V_M8_M2 = 4492,
4517 PseudoVLOXSEG3EI32_V_M8_M2_MASK = 4493,
4518 PseudoVLOXSEG3EI32_V_MF2_M1 = 4494,
4519 PseudoVLOXSEG3EI32_V_MF2_M1_MASK = 4495,
4520 PseudoVLOXSEG3EI32_V_MF2_MF2 = 4496,
4521 PseudoVLOXSEG3EI32_V_MF2_MF2_MASK = 4497,
4522 PseudoVLOXSEG3EI32_V_MF2_MF4 = 4498,
4523 PseudoVLOXSEG3EI32_V_MF2_MF4_MASK = 4499,
4524 PseudoVLOXSEG3EI32_V_MF2_MF8 = 4500,
4525 PseudoVLOXSEG3EI32_V_MF2_MF8_MASK = 4501,
4526 PseudoVLOXSEG3EI64_V_M1_M1 = 4502,
4527 PseudoVLOXSEG3EI64_V_M1_M1_MASK = 4503,
4528 PseudoVLOXSEG3EI64_V_M1_MF2 = 4504,
4529 PseudoVLOXSEG3EI64_V_M1_MF2_MASK = 4505,
4530 PseudoVLOXSEG3EI64_V_M1_MF4 = 4506,
4531 PseudoVLOXSEG3EI64_V_M1_MF4_MASK = 4507,
4532 PseudoVLOXSEG3EI64_V_M1_MF8 = 4508,
4533 PseudoVLOXSEG3EI64_V_M1_MF8_MASK = 4509,
4534 PseudoVLOXSEG3EI64_V_M2_M1 = 4510,
4535 PseudoVLOXSEG3EI64_V_M2_M1_MASK = 4511,
4536 PseudoVLOXSEG3EI64_V_M2_M2 = 4512,
4537 PseudoVLOXSEG3EI64_V_M2_M2_MASK = 4513,
4538 PseudoVLOXSEG3EI64_V_M2_MF2 = 4514,
4539 PseudoVLOXSEG3EI64_V_M2_MF2_MASK = 4515,
4540 PseudoVLOXSEG3EI64_V_M2_MF4 = 4516,
4541 PseudoVLOXSEG3EI64_V_M2_MF4_MASK = 4517,
4542 PseudoVLOXSEG3EI64_V_M4_M1 = 4518,
4543 PseudoVLOXSEG3EI64_V_M4_M1_MASK = 4519,
4544 PseudoVLOXSEG3EI64_V_M4_M2 = 4520,
4545 PseudoVLOXSEG3EI64_V_M4_M2_MASK = 4521,
4546 PseudoVLOXSEG3EI64_V_M4_MF2 = 4522,
4547 PseudoVLOXSEG3EI64_V_M4_MF2_MASK = 4523,
4548 PseudoVLOXSEG3EI64_V_M8_M1 = 4524,
4549 PseudoVLOXSEG3EI64_V_M8_M1_MASK = 4525,
4550 PseudoVLOXSEG3EI64_V_M8_M2 = 4526,
4551 PseudoVLOXSEG3EI64_V_M8_M2_MASK = 4527,
4552 PseudoVLOXSEG3EI8_V_M1_M1 = 4528,
4553 PseudoVLOXSEG3EI8_V_M1_M1_MASK = 4529,
4554 PseudoVLOXSEG3EI8_V_M1_M2 = 4530,
4555 PseudoVLOXSEG3EI8_V_M1_M2_MASK = 4531,
4556 PseudoVLOXSEG3EI8_V_M2_M2 = 4532,
4557 PseudoVLOXSEG3EI8_V_M2_M2_MASK = 4533,
4558 PseudoVLOXSEG3EI8_V_MF2_M1 = 4534,
4559 PseudoVLOXSEG3EI8_V_MF2_M1_MASK = 4535,
4560 PseudoVLOXSEG3EI8_V_MF2_M2 = 4536,
4561 PseudoVLOXSEG3EI8_V_MF2_M2_MASK = 4537,
4562 PseudoVLOXSEG3EI8_V_MF2_MF2 = 4538,
4563 PseudoVLOXSEG3EI8_V_MF2_MF2_MASK = 4539,
4564 PseudoVLOXSEG3EI8_V_MF4_M1 = 4540,
4565 PseudoVLOXSEG3EI8_V_MF4_M1_MASK = 4541,
4566 PseudoVLOXSEG3EI8_V_MF4_M2 = 4542,
4567 PseudoVLOXSEG3EI8_V_MF4_M2_MASK = 4543,
4568 PseudoVLOXSEG3EI8_V_MF4_MF2 = 4544,
4569 PseudoVLOXSEG3EI8_V_MF4_MF2_MASK = 4545,
4570 PseudoVLOXSEG3EI8_V_MF4_MF4 = 4546,
4571 PseudoVLOXSEG3EI8_V_MF4_MF4_MASK = 4547,
4572 PseudoVLOXSEG3EI8_V_MF8_M1 = 4548,
4573 PseudoVLOXSEG3EI8_V_MF8_M1_MASK = 4549,
4574 PseudoVLOXSEG3EI8_V_MF8_MF2 = 4550,
4575 PseudoVLOXSEG3EI8_V_MF8_MF2_MASK = 4551,
4576 PseudoVLOXSEG3EI8_V_MF8_MF4 = 4552,
4577 PseudoVLOXSEG3EI8_V_MF8_MF4_MASK = 4553,
4578 PseudoVLOXSEG3EI8_V_MF8_MF8 = 4554,
4579 PseudoVLOXSEG3EI8_V_MF8_MF8_MASK = 4555,
4580 PseudoVLOXSEG4EI16_V_M1_M1 = 4556,
4581 PseudoVLOXSEG4EI16_V_M1_M1_MASK = 4557,
4582 PseudoVLOXSEG4EI16_V_M1_M2 = 4558,
4583 PseudoVLOXSEG4EI16_V_M1_M2_MASK = 4559,
4584 PseudoVLOXSEG4EI16_V_M1_MF2 = 4560,
4585 PseudoVLOXSEG4EI16_V_M1_MF2_MASK = 4561,
4586 PseudoVLOXSEG4EI16_V_M2_M1 = 4562,
4587 PseudoVLOXSEG4EI16_V_M2_M1_MASK = 4563,
4588 PseudoVLOXSEG4EI16_V_M2_M2 = 4564,
4589 PseudoVLOXSEG4EI16_V_M2_M2_MASK = 4565,
4590 PseudoVLOXSEG4EI16_V_M4_M2 = 4566,
4591 PseudoVLOXSEG4EI16_V_M4_M2_MASK = 4567,
4592 PseudoVLOXSEG4EI16_V_MF2_M1 = 4568,
4593 PseudoVLOXSEG4EI16_V_MF2_M1_MASK = 4569,
4594 PseudoVLOXSEG4EI16_V_MF2_M2 = 4570,
4595 PseudoVLOXSEG4EI16_V_MF2_M2_MASK = 4571,
4596 PseudoVLOXSEG4EI16_V_MF2_MF2 = 4572,
4597 PseudoVLOXSEG4EI16_V_MF2_MF2_MASK = 4573,
4598 PseudoVLOXSEG4EI16_V_MF2_MF4 = 4574,
4599 PseudoVLOXSEG4EI16_V_MF2_MF4_MASK = 4575,
4600 PseudoVLOXSEG4EI16_V_MF4_M1 = 4576,
4601 PseudoVLOXSEG4EI16_V_MF4_M1_MASK = 4577,
4602 PseudoVLOXSEG4EI16_V_MF4_MF2 = 4578,
4603 PseudoVLOXSEG4EI16_V_MF4_MF2_MASK = 4579,
4604 PseudoVLOXSEG4EI16_V_MF4_MF4 = 4580,
4605 PseudoVLOXSEG4EI16_V_MF4_MF4_MASK = 4581,
4606 PseudoVLOXSEG4EI16_V_MF4_MF8 = 4582,
4607 PseudoVLOXSEG4EI16_V_MF4_MF8_MASK = 4583,
4608 PseudoVLOXSEG4EI32_V_M1_M1 = 4584,
4609 PseudoVLOXSEG4EI32_V_M1_M1_MASK = 4585,
4610 PseudoVLOXSEG4EI32_V_M1_M2 = 4586,
4611 PseudoVLOXSEG4EI32_V_M1_M2_MASK = 4587,
4612 PseudoVLOXSEG4EI32_V_M1_MF2 = 4588,
4613 PseudoVLOXSEG4EI32_V_M1_MF2_MASK = 4589,
4614 PseudoVLOXSEG4EI32_V_M1_MF4 = 4590,
4615 PseudoVLOXSEG4EI32_V_M1_MF4_MASK = 4591,
4616 PseudoVLOXSEG4EI32_V_M2_M1 = 4592,
4617 PseudoVLOXSEG4EI32_V_M2_M1_MASK = 4593,
4618 PseudoVLOXSEG4EI32_V_M2_M2 = 4594,
4619 PseudoVLOXSEG4EI32_V_M2_M2_MASK = 4595,
4620 PseudoVLOXSEG4EI32_V_M2_MF2 = 4596,
4621 PseudoVLOXSEG4EI32_V_M2_MF2_MASK = 4597,
4622 PseudoVLOXSEG4EI32_V_M4_M1 = 4598,
4623 PseudoVLOXSEG4EI32_V_M4_M1_MASK = 4599,
4624 PseudoVLOXSEG4EI32_V_M4_M2 = 4600,
4625 PseudoVLOXSEG4EI32_V_M4_M2_MASK = 4601,
4626 PseudoVLOXSEG4EI32_V_M8_M2 = 4602,
4627 PseudoVLOXSEG4EI32_V_M8_M2_MASK = 4603,
4628 PseudoVLOXSEG4EI32_V_MF2_M1 = 4604,
4629 PseudoVLOXSEG4EI32_V_MF2_M1_MASK = 4605,
4630 PseudoVLOXSEG4EI32_V_MF2_MF2 = 4606,
4631 PseudoVLOXSEG4EI32_V_MF2_MF2_MASK = 4607,
4632 PseudoVLOXSEG4EI32_V_MF2_MF4 = 4608,
4633 PseudoVLOXSEG4EI32_V_MF2_MF4_MASK = 4609,
4634 PseudoVLOXSEG4EI32_V_MF2_MF8 = 4610,
4635 PseudoVLOXSEG4EI32_V_MF2_MF8_MASK = 4611,
4636 PseudoVLOXSEG4EI64_V_M1_M1 = 4612,
4637 PseudoVLOXSEG4EI64_V_M1_M1_MASK = 4613,
4638 PseudoVLOXSEG4EI64_V_M1_MF2 = 4614,
4639 PseudoVLOXSEG4EI64_V_M1_MF2_MASK = 4615,
4640 PseudoVLOXSEG4EI64_V_M1_MF4 = 4616,
4641 PseudoVLOXSEG4EI64_V_M1_MF4_MASK = 4617,
4642 PseudoVLOXSEG4EI64_V_M1_MF8 = 4618,
4643 PseudoVLOXSEG4EI64_V_M1_MF8_MASK = 4619,
4644 PseudoVLOXSEG4EI64_V_M2_M1 = 4620,
4645 PseudoVLOXSEG4EI64_V_M2_M1_MASK = 4621,
4646 PseudoVLOXSEG4EI64_V_M2_M2 = 4622,
4647 PseudoVLOXSEG4EI64_V_M2_M2_MASK = 4623,
4648 PseudoVLOXSEG4EI64_V_M2_MF2 = 4624,
4649 PseudoVLOXSEG4EI64_V_M2_MF2_MASK = 4625,
4650 PseudoVLOXSEG4EI64_V_M2_MF4 = 4626,
4651 PseudoVLOXSEG4EI64_V_M2_MF4_MASK = 4627,
4652 PseudoVLOXSEG4EI64_V_M4_M1 = 4628,
4653 PseudoVLOXSEG4EI64_V_M4_M1_MASK = 4629,
4654 PseudoVLOXSEG4EI64_V_M4_M2 = 4630,
4655 PseudoVLOXSEG4EI64_V_M4_M2_MASK = 4631,
4656 PseudoVLOXSEG4EI64_V_M4_MF2 = 4632,
4657 PseudoVLOXSEG4EI64_V_M4_MF2_MASK = 4633,
4658 PseudoVLOXSEG4EI64_V_M8_M1 = 4634,
4659 PseudoVLOXSEG4EI64_V_M8_M1_MASK = 4635,
4660 PseudoVLOXSEG4EI64_V_M8_M2 = 4636,
4661 PseudoVLOXSEG4EI64_V_M8_M2_MASK = 4637,
4662 PseudoVLOXSEG4EI8_V_M1_M1 = 4638,
4663 PseudoVLOXSEG4EI8_V_M1_M1_MASK = 4639,
4664 PseudoVLOXSEG4EI8_V_M1_M2 = 4640,
4665 PseudoVLOXSEG4EI8_V_M1_M2_MASK = 4641,
4666 PseudoVLOXSEG4EI8_V_M2_M2 = 4642,
4667 PseudoVLOXSEG4EI8_V_M2_M2_MASK = 4643,
4668 PseudoVLOXSEG4EI8_V_MF2_M1 = 4644,
4669 PseudoVLOXSEG4EI8_V_MF2_M1_MASK = 4645,
4670 PseudoVLOXSEG4EI8_V_MF2_M2 = 4646,
4671 PseudoVLOXSEG4EI8_V_MF2_M2_MASK = 4647,
4672 PseudoVLOXSEG4EI8_V_MF2_MF2 = 4648,
4673 PseudoVLOXSEG4EI8_V_MF2_MF2_MASK = 4649,
4674 PseudoVLOXSEG4EI8_V_MF4_M1 = 4650,
4675 PseudoVLOXSEG4EI8_V_MF4_M1_MASK = 4651,
4676 PseudoVLOXSEG4EI8_V_MF4_M2 = 4652,
4677 PseudoVLOXSEG4EI8_V_MF4_M2_MASK = 4653,
4678 PseudoVLOXSEG4EI8_V_MF4_MF2 = 4654,
4679 PseudoVLOXSEG4EI8_V_MF4_MF2_MASK = 4655,
4680 PseudoVLOXSEG4EI8_V_MF4_MF4 = 4656,
4681 PseudoVLOXSEG4EI8_V_MF4_MF4_MASK = 4657,
4682 PseudoVLOXSEG4EI8_V_MF8_M1 = 4658,
4683 PseudoVLOXSEG4EI8_V_MF8_M1_MASK = 4659,
4684 PseudoVLOXSEG4EI8_V_MF8_MF2 = 4660,
4685 PseudoVLOXSEG4EI8_V_MF8_MF2_MASK = 4661,
4686 PseudoVLOXSEG4EI8_V_MF8_MF4 = 4662,
4687 PseudoVLOXSEG4EI8_V_MF8_MF4_MASK = 4663,
4688 PseudoVLOXSEG4EI8_V_MF8_MF8 = 4664,
4689 PseudoVLOXSEG4EI8_V_MF8_MF8_MASK = 4665,
4690 PseudoVLOXSEG5EI16_V_M1_M1 = 4666,
4691 PseudoVLOXSEG5EI16_V_M1_M1_MASK = 4667,
4692 PseudoVLOXSEG5EI16_V_M1_MF2 = 4668,
4693 PseudoVLOXSEG5EI16_V_M1_MF2_MASK = 4669,
4694 PseudoVLOXSEG5EI16_V_M2_M1 = 4670,
4695 PseudoVLOXSEG5EI16_V_M2_M1_MASK = 4671,
4696 PseudoVLOXSEG5EI16_V_MF2_M1 = 4672,
4697 PseudoVLOXSEG5EI16_V_MF2_M1_MASK = 4673,
4698 PseudoVLOXSEG5EI16_V_MF2_MF2 = 4674,
4699 PseudoVLOXSEG5EI16_V_MF2_MF2_MASK = 4675,
4700 PseudoVLOXSEG5EI16_V_MF2_MF4 = 4676,
4701 PseudoVLOXSEG5EI16_V_MF2_MF4_MASK = 4677,
4702 PseudoVLOXSEG5EI16_V_MF4_M1 = 4678,
4703 PseudoVLOXSEG5EI16_V_MF4_M1_MASK = 4679,
4704 PseudoVLOXSEG5EI16_V_MF4_MF2 = 4680,
4705 PseudoVLOXSEG5EI16_V_MF4_MF2_MASK = 4681,
4706 PseudoVLOXSEG5EI16_V_MF4_MF4 = 4682,
4707 PseudoVLOXSEG5EI16_V_MF4_MF4_MASK = 4683,
4708 PseudoVLOXSEG5EI16_V_MF4_MF8 = 4684,
4709 PseudoVLOXSEG5EI16_V_MF4_MF8_MASK = 4685,
4710 PseudoVLOXSEG5EI32_V_M1_M1 = 4686,
4711 PseudoVLOXSEG5EI32_V_M1_M1_MASK = 4687,
4712 PseudoVLOXSEG5EI32_V_M1_MF2 = 4688,
4713 PseudoVLOXSEG5EI32_V_M1_MF2_MASK = 4689,
4714 PseudoVLOXSEG5EI32_V_M1_MF4 = 4690,
4715 PseudoVLOXSEG5EI32_V_M1_MF4_MASK = 4691,
4716 PseudoVLOXSEG5EI32_V_M2_M1 = 4692,
4717 PseudoVLOXSEG5EI32_V_M2_M1_MASK = 4693,
4718 PseudoVLOXSEG5EI32_V_M2_MF2 = 4694,
4719 PseudoVLOXSEG5EI32_V_M2_MF2_MASK = 4695,
4720 PseudoVLOXSEG5EI32_V_M4_M1 = 4696,
4721 PseudoVLOXSEG5EI32_V_M4_M1_MASK = 4697,
4722 PseudoVLOXSEG5EI32_V_MF2_M1 = 4698,
4723 PseudoVLOXSEG5EI32_V_MF2_M1_MASK = 4699,
4724 PseudoVLOXSEG5EI32_V_MF2_MF2 = 4700,
4725 PseudoVLOXSEG5EI32_V_MF2_MF2_MASK = 4701,
4726 PseudoVLOXSEG5EI32_V_MF2_MF4 = 4702,
4727 PseudoVLOXSEG5EI32_V_MF2_MF4_MASK = 4703,
4728 PseudoVLOXSEG5EI32_V_MF2_MF8 = 4704,
4729 PseudoVLOXSEG5EI32_V_MF2_MF8_MASK = 4705,
4730 PseudoVLOXSEG5EI64_V_M1_M1 = 4706,
4731 PseudoVLOXSEG5EI64_V_M1_M1_MASK = 4707,
4732 PseudoVLOXSEG5EI64_V_M1_MF2 = 4708,
4733 PseudoVLOXSEG5EI64_V_M1_MF2_MASK = 4709,
4734 PseudoVLOXSEG5EI64_V_M1_MF4 = 4710,
4735 PseudoVLOXSEG5EI64_V_M1_MF4_MASK = 4711,
4736 PseudoVLOXSEG5EI64_V_M1_MF8 = 4712,
4737 PseudoVLOXSEG5EI64_V_M1_MF8_MASK = 4713,
4738 PseudoVLOXSEG5EI64_V_M2_M1 = 4714,
4739 PseudoVLOXSEG5EI64_V_M2_M1_MASK = 4715,
4740 PseudoVLOXSEG5EI64_V_M2_MF2 = 4716,
4741 PseudoVLOXSEG5EI64_V_M2_MF2_MASK = 4717,
4742 PseudoVLOXSEG5EI64_V_M2_MF4 = 4718,
4743 PseudoVLOXSEG5EI64_V_M2_MF4_MASK = 4719,
4744 PseudoVLOXSEG5EI64_V_M4_M1 = 4720,
4745 PseudoVLOXSEG5EI64_V_M4_M1_MASK = 4721,
4746 PseudoVLOXSEG5EI64_V_M4_MF2 = 4722,
4747 PseudoVLOXSEG5EI64_V_M4_MF2_MASK = 4723,
4748 PseudoVLOXSEG5EI64_V_M8_M1 = 4724,
4749 PseudoVLOXSEG5EI64_V_M8_M1_MASK = 4725,
4750 PseudoVLOXSEG5EI8_V_M1_M1 = 4726,
4751 PseudoVLOXSEG5EI8_V_M1_M1_MASK = 4727,
4752 PseudoVLOXSEG5EI8_V_MF2_M1 = 4728,
4753 PseudoVLOXSEG5EI8_V_MF2_M1_MASK = 4729,
4754 PseudoVLOXSEG5EI8_V_MF2_MF2 = 4730,
4755 PseudoVLOXSEG5EI8_V_MF2_MF2_MASK = 4731,
4756 PseudoVLOXSEG5EI8_V_MF4_M1 = 4732,
4757 PseudoVLOXSEG5EI8_V_MF4_M1_MASK = 4733,
4758 PseudoVLOXSEG5EI8_V_MF4_MF2 = 4734,
4759 PseudoVLOXSEG5EI8_V_MF4_MF2_MASK = 4735,
4760 PseudoVLOXSEG5EI8_V_MF4_MF4 = 4736,
4761 PseudoVLOXSEG5EI8_V_MF4_MF4_MASK = 4737,
4762 PseudoVLOXSEG5EI8_V_MF8_M1 = 4738,
4763 PseudoVLOXSEG5EI8_V_MF8_M1_MASK = 4739,
4764 PseudoVLOXSEG5EI8_V_MF8_MF2 = 4740,
4765 PseudoVLOXSEG5EI8_V_MF8_MF2_MASK = 4741,
4766 PseudoVLOXSEG5EI8_V_MF8_MF4 = 4742,
4767 PseudoVLOXSEG5EI8_V_MF8_MF4_MASK = 4743,
4768 PseudoVLOXSEG5EI8_V_MF8_MF8 = 4744,
4769 PseudoVLOXSEG5EI8_V_MF8_MF8_MASK = 4745,
4770 PseudoVLOXSEG6EI16_V_M1_M1 = 4746,
4771 PseudoVLOXSEG6EI16_V_M1_M1_MASK = 4747,
4772 PseudoVLOXSEG6EI16_V_M1_MF2 = 4748,
4773 PseudoVLOXSEG6EI16_V_M1_MF2_MASK = 4749,
4774 PseudoVLOXSEG6EI16_V_M2_M1 = 4750,
4775 PseudoVLOXSEG6EI16_V_M2_M1_MASK = 4751,
4776 PseudoVLOXSEG6EI16_V_MF2_M1 = 4752,
4777 PseudoVLOXSEG6EI16_V_MF2_M1_MASK = 4753,
4778 PseudoVLOXSEG6EI16_V_MF2_MF2 = 4754,
4779 PseudoVLOXSEG6EI16_V_MF2_MF2_MASK = 4755,
4780 PseudoVLOXSEG6EI16_V_MF2_MF4 = 4756,
4781 PseudoVLOXSEG6EI16_V_MF2_MF4_MASK = 4757,
4782 PseudoVLOXSEG6EI16_V_MF4_M1 = 4758,
4783 PseudoVLOXSEG6EI16_V_MF4_M1_MASK = 4759,
4784 PseudoVLOXSEG6EI16_V_MF4_MF2 = 4760,
4785 PseudoVLOXSEG6EI16_V_MF4_MF2_MASK = 4761,
4786 PseudoVLOXSEG6EI16_V_MF4_MF4 = 4762,
4787 PseudoVLOXSEG6EI16_V_MF4_MF4_MASK = 4763,
4788 PseudoVLOXSEG6EI16_V_MF4_MF8 = 4764,
4789 PseudoVLOXSEG6EI16_V_MF4_MF8_MASK = 4765,
4790 PseudoVLOXSEG6EI32_V_M1_M1 = 4766,
4791 PseudoVLOXSEG6EI32_V_M1_M1_MASK = 4767,
4792 PseudoVLOXSEG6EI32_V_M1_MF2 = 4768,
4793 PseudoVLOXSEG6EI32_V_M1_MF2_MASK = 4769,
4794 PseudoVLOXSEG6EI32_V_M1_MF4 = 4770,
4795 PseudoVLOXSEG6EI32_V_M1_MF4_MASK = 4771,
4796 PseudoVLOXSEG6EI32_V_M2_M1 = 4772,
4797 PseudoVLOXSEG6EI32_V_M2_M1_MASK = 4773,
4798 PseudoVLOXSEG6EI32_V_M2_MF2 = 4774,
4799 PseudoVLOXSEG6EI32_V_M2_MF2_MASK = 4775,
4800 PseudoVLOXSEG6EI32_V_M4_M1 = 4776,
4801 PseudoVLOXSEG6EI32_V_M4_M1_MASK = 4777,
4802 PseudoVLOXSEG6EI32_V_MF2_M1 = 4778,
4803 PseudoVLOXSEG6EI32_V_MF2_M1_MASK = 4779,
4804 PseudoVLOXSEG6EI32_V_MF2_MF2 = 4780,
4805 PseudoVLOXSEG6EI32_V_MF2_MF2_MASK = 4781,
4806 PseudoVLOXSEG6EI32_V_MF2_MF4 = 4782,
4807 PseudoVLOXSEG6EI32_V_MF2_MF4_MASK = 4783,
4808 PseudoVLOXSEG6EI32_V_MF2_MF8 = 4784,
4809 PseudoVLOXSEG6EI32_V_MF2_MF8_MASK = 4785,
4810 PseudoVLOXSEG6EI64_V_M1_M1 = 4786,
4811 PseudoVLOXSEG6EI64_V_M1_M1_MASK = 4787,
4812 PseudoVLOXSEG6EI64_V_M1_MF2 = 4788,
4813 PseudoVLOXSEG6EI64_V_M1_MF2_MASK = 4789,
4814 PseudoVLOXSEG6EI64_V_M1_MF4 = 4790,
4815 PseudoVLOXSEG6EI64_V_M1_MF4_MASK = 4791,
4816 PseudoVLOXSEG6EI64_V_M1_MF8 = 4792,
4817 PseudoVLOXSEG6EI64_V_M1_MF8_MASK = 4793,
4818 PseudoVLOXSEG6EI64_V_M2_M1 = 4794,
4819 PseudoVLOXSEG6EI64_V_M2_M1_MASK = 4795,
4820 PseudoVLOXSEG6EI64_V_M2_MF2 = 4796,
4821 PseudoVLOXSEG6EI64_V_M2_MF2_MASK = 4797,
4822 PseudoVLOXSEG6EI64_V_M2_MF4 = 4798,
4823 PseudoVLOXSEG6EI64_V_M2_MF4_MASK = 4799,
4824 PseudoVLOXSEG6EI64_V_M4_M1 = 4800,
4825 PseudoVLOXSEG6EI64_V_M4_M1_MASK = 4801,
4826 PseudoVLOXSEG6EI64_V_M4_MF2 = 4802,
4827 PseudoVLOXSEG6EI64_V_M4_MF2_MASK = 4803,
4828 PseudoVLOXSEG6EI64_V_M8_M1 = 4804,
4829 PseudoVLOXSEG6EI64_V_M8_M1_MASK = 4805,
4830 PseudoVLOXSEG6EI8_V_M1_M1 = 4806,
4831 PseudoVLOXSEG6EI8_V_M1_M1_MASK = 4807,
4832 PseudoVLOXSEG6EI8_V_MF2_M1 = 4808,
4833 PseudoVLOXSEG6EI8_V_MF2_M1_MASK = 4809,
4834 PseudoVLOXSEG6EI8_V_MF2_MF2 = 4810,
4835 PseudoVLOXSEG6EI8_V_MF2_MF2_MASK = 4811,
4836 PseudoVLOXSEG6EI8_V_MF4_M1 = 4812,
4837 PseudoVLOXSEG6EI8_V_MF4_M1_MASK = 4813,
4838 PseudoVLOXSEG6EI8_V_MF4_MF2 = 4814,
4839 PseudoVLOXSEG6EI8_V_MF4_MF2_MASK = 4815,
4840 PseudoVLOXSEG6EI8_V_MF4_MF4 = 4816,
4841 PseudoVLOXSEG6EI8_V_MF4_MF4_MASK = 4817,
4842 PseudoVLOXSEG6EI8_V_MF8_M1 = 4818,
4843 PseudoVLOXSEG6EI8_V_MF8_M1_MASK = 4819,
4844 PseudoVLOXSEG6EI8_V_MF8_MF2 = 4820,
4845 PseudoVLOXSEG6EI8_V_MF8_MF2_MASK = 4821,
4846 PseudoVLOXSEG6EI8_V_MF8_MF4 = 4822,
4847 PseudoVLOXSEG6EI8_V_MF8_MF4_MASK = 4823,
4848 PseudoVLOXSEG6EI8_V_MF8_MF8 = 4824,
4849 PseudoVLOXSEG6EI8_V_MF8_MF8_MASK = 4825,
4850 PseudoVLOXSEG7EI16_V_M1_M1 = 4826,
4851 PseudoVLOXSEG7EI16_V_M1_M1_MASK = 4827,
4852 PseudoVLOXSEG7EI16_V_M1_MF2 = 4828,
4853 PseudoVLOXSEG7EI16_V_M1_MF2_MASK = 4829,
4854 PseudoVLOXSEG7EI16_V_M2_M1 = 4830,
4855 PseudoVLOXSEG7EI16_V_M2_M1_MASK = 4831,
4856 PseudoVLOXSEG7EI16_V_MF2_M1 = 4832,
4857 PseudoVLOXSEG7EI16_V_MF2_M1_MASK = 4833,
4858 PseudoVLOXSEG7EI16_V_MF2_MF2 = 4834,
4859 PseudoVLOXSEG7EI16_V_MF2_MF2_MASK = 4835,
4860 PseudoVLOXSEG7EI16_V_MF2_MF4 = 4836,
4861 PseudoVLOXSEG7EI16_V_MF2_MF4_MASK = 4837,
4862 PseudoVLOXSEG7EI16_V_MF4_M1 = 4838,
4863 PseudoVLOXSEG7EI16_V_MF4_M1_MASK = 4839,
4864 PseudoVLOXSEG7EI16_V_MF4_MF2 = 4840,
4865 PseudoVLOXSEG7EI16_V_MF4_MF2_MASK = 4841,
4866 PseudoVLOXSEG7EI16_V_MF4_MF4 = 4842,
4867 PseudoVLOXSEG7EI16_V_MF4_MF4_MASK = 4843,
4868 PseudoVLOXSEG7EI16_V_MF4_MF8 = 4844,
4869 PseudoVLOXSEG7EI16_V_MF4_MF8_MASK = 4845,
4870 PseudoVLOXSEG7EI32_V_M1_M1 = 4846,
4871 PseudoVLOXSEG7EI32_V_M1_M1_MASK = 4847,
4872 PseudoVLOXSEG7EI32_V_M1_MF2 = 4848,
4873 PseudoVLOXSEG7EI32_V_M1_MF2_MASK = 4849,
4874 PseudoVLOXSEG7EI32_V_M1_MF4 = 4850,
4875 PseudoVLOXSEG7EI32_V_M1_MF4_MASK = 4851,
4876 PseudoVLOXSEG7EI32_V_M2_M1 = 4852,
4877 PseudoVLOXSEG7EI32_V_M2_M1_MASK = 4853,
4878 PseudoVLOXSEG7EI32_V_M2_MF2 = 4854,
4879 PseudoVLOXSEG7EI32_V_M2_MF2_MASK = 4855,
4880 PseudoVLOXSEG7EI32_V_M4_M1 = 4856,
4881 PseudoVLOXSEG7EI32_V_M4_M1_MASK = 4857,
4882 PseudoVLOXSEG7EI32_V_MF2_M1 = 4858,
4883 PseudoVLOXSEG7EI32_V_MF2_M1_MASK = 4859,
4884 PseudoVLOXSEG7EI32_V_MF2_MF2 = 4860,
4885 PseudoVLOXSEG7EI32_V_MF2_MF2_MASK = 4861,
4886 PseudoVLOXSEG7EI32_V_MF2_MF4 = 4862,
4887 PseudoVLOXSEG7EI32_V_MF2_MF4_MASK = 4863,
4888 PseudoVLOXSEG7EI32_V_MF2_MF8 = 4864,
4889 PseudoVLOXSEG7EI32_V_MF2_MF8_MASK = 4865,
4890 PseudoVLOXSEG7EI64_V_M1_M1 = 4866,
4891 PseudoVLOXSEG7EI64_V_M1_M1_MASK = 4867,
4892 PseudoVLOXSEG7EI64_V_M1_MF2 = 4868,
4893 PseudoVLOXSEG7EI64_V_M1_MF2_MASK = 4869,
4894 PseudoVLOXSEG7EI64_V_M1_MF4 = 4870,
4895 PseudoVLOXSEG7EI64_V_M1_MF4_MASK = 4871,
4896 PseudoVLOXSEG7EI64_V_M1_MF8 = 4872,
4897 PseudoVLOXSEG7EI64_V_M1_MF8_MASK = 4873,
4898 PseudoVLOXSEG7EI64_V_M2_M1 = 4874,
4899 PseudoVLOXSEG7EI64_V_M2_M1_MASK = 4875,
4900 PseudoVLOXSEG7EI64_V_M2_MF2 = 4876,
4901 PseudoVLOXSEG7EI64_V_M2_MF2_MASK = 4877,
4902 PseudoVLOXSEG7EI64_V_M2_MF4 = 4878,
4903 PseudoVLOXSEG7EI64_V_M2_MF4_MASK = 4879,
4904 PseudoVLOXSEG7EI64_V_M4_M1 = 4880,
4905 PseudoVLOXSEG7EI64_V_M4_M1_MASK = 4881,
4906 PseudoVLOXSEG7EI64_V_M4_MF2 = 4882,
4907 PseudoVLOXSEG7EI64_V_M4_MF2_MASK = 4883,
4908 PseudoVLOXSEG7EI64_V_M8_M1 = 4884,
4909 PseudoVLOXSEG7EI64_V_M8_M1_MASK = 4885,
4910 PseudoVLOXSEG7EI8_V_M1_M1 = 4886,
4911 PseudoVLOXSEG7EI8_V_M1_M1_MASK = 4887,
4912 PseudoVLOXSEG7EI8_V_MF2_M1 = 4888,
4913 PseudoVLOXSEG7EI8_V_MF2_M1_MASK = 4889,
4914 PseudoVLOXSEG7EI8_V_MF2_MF2 = 4890,
4915 PseudoVLOXSEG7EI8_V_MF2_MF2_MASK = 4891,
4916 PseudoVLOXSEG7EI8_V_MF4_M1 = 4892,
4917 PseudoVLOXSEG7EI8_V_MF4_M1_MASK = 4893,
4918 PseudoVLOXSEG7EI8_V_MF4_MF2 = 4894,
4919 PseudoVLOXSEG7EI8_V_MF4_MF2_MASK = 4895,
4920 PseudoVLOXSEG7EI8_V_MF4_MF4 = 4896,
4921 PseudoVLOXSEG7EI8_V_MF4_MF4_MASK = 4897,
4922 PseudoVLOXSEG7EI8_V_MF8_M1 = 4898,
4923 PseudoVLOXSEG7EI8_V_MF8_M1_MASK = 4899,
4924 PseudoVLOXSEG7EI8_V_MF8_MF2 = 4900,
4925 PseudoVLOXSEG7EI8_V_MF8_MF2_MASK = 4901,
4926 PseudoVLOXSEG7EI8_V_MF8_MF4 = 4902,
4927 PseudoVLOXSEG7EI8_V_MF8_MF4_MASK = 4903,
4928 PseudoVLOXSEG7EI8_V_MF8_MF8 = 4904,
4929 PseudoVLOXSEG7EI8_V_MF8_MF8_MASK = 4905,
4930 PseudoVLOXSEG8EI16_V_M1_M1 = 4906,
4931 PseudoVLOXSEG8EI16_V_M1_M1_MASK = 4907,
4932 PseudoVLOXSEG8EI16_V_M1_MF2 = 4908,
4933 PseudoVLOXSEG8EI16_V_M1_MF2_MASK = 4909,
4934 PseudoVLOXSEG8EI16_V_M2_M1 = 4910,
4935 PseudoVLOXSEG8EI16_V_M2_M1_MASK = 4911,
4936 PseudoVLOXSEG8EI16_V_MF2_M1 = 4912,
4937 PseudoVLOXSEG8EI16_V_MF2_M1_MASK = 4913,
4938 PseudoVLOXSEG8EI16_V_MF2_MF2 = 4914,
4939 PseudoVLOXSEG8EI16_V_MF2_MF2_MASK = 4915,
4940 PseudoVLOXSEG8EI16_V_MF2_MF4 = 4916,
4941 PseudoVLOXSEG8EI16_V_MF2_MF4_MASK = 4917,
4942 PseudoVLOXSEG8EI16_V_MF4_M1 = 4918,
4943 PseudoVLOXSEG8EI16_V_MF4_M1_MASK = 4919,
4944 PseudoVLOXSEG8EI16_V_MF4_MF2 = 4920,
4945 PseudoVLOXSEG8EI16_V_MF4_MF2_MASK = 4921,
4946 PseudoVLOXSEG8EI16_V_MF4_MF4 = 4922,
4947 PseudoVLOXSEG8EI16_V_MF4_MF4_MASK = 4923,
4948 PseudoVLOXSEG8EI16_V_MF4_MF8 = 4924,
4949 PseudoVLOXSEG8EI16_V_MF4_MF8_MASK = 4925,
4950 PseudoVLOXSEG8EI32_V_M1_M1 = 4926,
4951 PseudoVLOXSEG8EI32_V_M1_M1_MASK = 4927,
4952 PseudoVLOXSEG8EI32_V_M1_MF2 = 4928,
4953 PseudoVLOXSEG8EI32_V_M1_MF2_MASK = 4929,
4954 PseudoVLOXSEG8EI32_V_M1_MF4 = 4930,
4955 PseudoVLOXSEG8EI32_V_M1_MF4_MASK = 4931,
4956 PseudoVLOXSEG8EI32_V_M2_M1 = 4932,
4957 PseudoVLOXSEG8EI32_V_M2_M1_MASK = 4933,
4958 PseudoVLOXSEG8EI32_V_M2_MF2 = 4934,
4959 PseudoVLOXSEG8EI32_V_M2_MF2_MASK = 4935,
4960 PseudoVLOXSEG8EI32_V_M4_M1 = 4936,
4961 PseudoVLOXSEG8EI32_V_M4_M1_MASK = 4937,
4962 PseudoVLOXSEG8EI32_V_MF2_M1 = 4938,
4963 PseudoVLOXSEG8EI32_V_MF2_M1_MASK = 4939,
4964 PseudoVLOXSEG8EI32_V_MF2_MF2 = 4940,
4965 PseudoVLOXSEG8EI32_V_MF2_MF2_MASK = 4941,
4966 PseudoVLOXSEG8EI32_V_MF2_MF4 = 4942,
4967 PseudoVLOXSEG8EI32_V_MF2_MF4_MASK = 4943,
4968 PseudoVLOXSEG8EI32_V_MF2_MF8 = 4944,
4969 PseudoVLOXSEG8EI32_V_MF2_MF8_MASK = 4945,
4970 PseudoVLOXSEG8EI64_V_M1_M1 = 4946,
4971 PseudoVLOXSEG8EI64_V_M1_M1_MASK = 4947,
4972 PseudoVLOXSEG8EI64_V_M1_MF2 = 4948,
4973 PseudoVLOXSEG8EI64_V_M1_MF2_MASK = 4949,
4974 PseudoVLOXSEG8EI64_V_M1_MF4 = 4950,
4975 PseudoVLOXSEG8EI64_V_M1_MF4_MASK = 4951,
4976 PseudoVLOXSEG8EI64_V_M1_MF8 = 4952,
4977 PseudoVLOXSEG8EI64_V_M1_MF8_MASK = 4953,
4978 PseudoVLOXSEG8EI64_V_M2_M1 = 4954,
4979 PseudoVLOXSEG8EI64_V_M2_M1_MASK = 4955,
4980 PseudoVLOXSEG8EI64_V_M2_MF2 = 4956,
4981 PseudoVLOXSEG8EI64_V_M2_MF2_MASK = 4957,
4982 PseudoVLOXSEG8EI64_V_M2_MF4 = 4958,
4983 PseudoVLOXSEG8EI64_V_M2_MF4_MASK = 4959,
4984 PseudoVLOXSEG8EI64_V_M4_M1 = 4960,
4985 PseudoVLOXSEG8EI64_V_M4_M1_MASK = 4961,
4986 PseudoVLOXSEG8EI64_V_M4_MF2 = 4962,
4987 PseudoVLOXSEG8EI64_V_M4_MF2_MASK = 4963,
4988 PseudoVLOXSEG8EI64_V_M8_M1 = 4964,
4989 PseudoVLOXSEG8EI64_V_M8_M1_MASK = 4965,
4990 PseudoVLOXSEG8EI8_V_M1_M1 = 4966,
4991 PseudoVLOXSEG8EI8_V_M1_M1_MASK = 4967,
4992 PseudoVLOXSEG8EI8_V_MF2_M1 = 4968,
4993 PseudoVLOXSEG8EI8_V_MF2_M1_MASK = 4969,
4994 PseudoVLOXSEG8EI8_V_MF2_MF2 = 4970,
4995 PseudoVLOXSEG8EI8_V_MF2_MF2_MASK = 4971,
4996 PseudoVLOXSEG8EI8_V_MF4_M1 = 4972,
4997 PseudoVLOXSEG8EI8_V_MF4_M1_MASK = 4973,
4998 PseudoVLOXSEG8EI8_V_MF4_MF2 = 4974,
4999 PseudoVLOXSEG8EI8_V_MF4_MF2_MASK = 4975,
5000 PseudoVLOXSEG8EI8_V_MF4_MF4 = 4976,
5001 PseudoVLOXSEG8EI8_V_MF4_MF4_MASK = 4977,
5002 PseudoVLOXSEG8EI8_V_MF8_M1 = 4978,
5003 PseudoVLOXSEG8EI8_V_MF8_M1_MASK = 4979,
5004 PseudoVLOXSEG8EI8_V_MF8_MF2 = 4980,
5005 PseudoVLOXSEG8EI8_V_MF8_MF2_MASK = 4981,
5006 PseudoVLOXSEG8EI8_V_MF8_MF4 = 4982,
5007 PseudoVLOXSEG8EI8_V_MF8_MF4_MASK = 4983,
5008 PseudoVLOXSEG8EI8_V_MF8_MF8 = 4984,
5009 PseudoVLOXSEG8EI8_V_MF8_MF8_MASK = 4985,
5010 PseudoVLSE16_V_M1 = 4986,
5011 PseudoVLSE16_V_M1_MASK = 4987,
5012 PseudoVLSE16_V_M2 = 4988,
5013 PseudoVLSE16_V_M2_MASK = 4989,
5014 PseudoVLSE16_V_M4 = 4990,
5015 PseudoVLSE16_V_M4_MASK = 4991,
5016 PseudoVLSE16_V_M8 = 4992,
5017 PseudoVLSE16_V_M8_MASK = 4993,
5018 PseudoVLSE16_V_MF2 = 4994,
5019 PseudoVLSE16_V_MF2_MASK = 4995,
5020 PseudoVLSE16_V_MF4 = 4996,
5021 PseudoVLSE16_V_MF4_MASK = 4997,
5022 PseudoVLSE32_V_M1 = 4998,
5023 PseudoVLSE32_V_M1_MASK = 4999,
5024 PseudoVLSE32_V_M2 = 5000,
5025 PseudoVLSE32_V_M2_MASK = 5001,
5026 PseudoVLSE32_V_M4 = 5002,
5027 PseudoVLSE32_V_M4_MASK = 5003,
5028 PseudoVLSE32_V_M8 = 5004,
5029 PseudoVLSE32_V_M8_MASK = 5005,
5030 PseudoVLSE32_V_MF2 = 5006,
5031 PseudoVLSE32_V_MF2_MASK = 5007,
5032 PseudoVLSE64_V_M1 = 5008,
5033 PseudoVLSE64_V_M1_MASK = 5009,
5034 PseudoVLSE64_V_M2 = 5010,
5035 PseudoVLSE64_V_M2_MASK = 5011,
5036 PseudoVLSE64_V_M4 = 5012,
5037 PseudoVLSE64_V_M4_MASK = 5013,
5038 PseudoVLSE64_V_M8 = 5014,
5039 PseudoVLSE64_V_M8_MASK = 5015,
5040 PseudoVLSE8_V_M1 = 5016,
5041 PseudoVLSE8_V_M1_MASK = 5017,
5042 PseudoVLSE8_V_M2 = 5018,
5043 PseudoVLSE8_V_M2_MASK = 5019,
5044 PseudoVLSE8_V_M4 = 5020,
5045 PseudoVLSE8_V_M4_MASK = 5021,
5046 PseudoVLSE8_V_M8 = 5022,
5047 PseudoVLSE8_V_M8_MASK = 5023,
5048 PseudoVLSE8_V_MF2 = 5024,
5049 PseudoVLSE8_V_MF2_MASK = 5025,
5050 PseudoVLSE8_V_MF4 = 5026,
5051 PseudoVLSE8_V_MF4_MASK = 5027,
5052 PseudoVLSE8_V_MF8 = 5028,
5053 PseudoVLSE8_V_MF8_MASK = 5029,
5054 PseudoVLSEG2E16FF_V_M1 = 5030,
5055 PseudoVLSEG2E16FF_V_M1_MASK = 5031,
5056 PseudoVLSEG2E16FF_V_M2 = 5032,
5057 PseudoVLSEG2E16FF_V_M2_MASK = 5033,
5058 PseudoVLSEG2E16FF_V_M4 = 5034,
5059 PseudoVLSEG2E16FF_V_M4_MASK = 5035,
5060 PseudoVLSEG2E16FF_V_MF2 = 5036,
5061 PseudoVLSEG2E16FF_V_MF2_MASK = 5037,
5062 PseudoVLSEG2E16FF_V_MF4 = 5038,
5063 PseudoVLSEG2E16FF_V_MF4_MASK = 5039,
5064 PseudoVLSEG2E16_V_M1 = 5040,
5065 PseudoVLSEG2E16_V_M1_MASK = 5041,
5066 PseudoVLSEG2E16_V_M2 = 5042,
5067 PseudoVLSEG2E16_V_M2_MASK = 5043,
5068 PseudoVLSEG2E16_V_M4 = 5044,
5069 PseudoVLSEG2E16_V_M4_MASK = 5045,
5070 PseudoVLSEG2E16_V_MF2 = 5046,
5071 PseudoVLSEG2E16_V_MF2_MASK = 5047,
5072 PseudoVLSEG2E16_V_MF4 = 5048,
5073 PseudoVLSEG2E16_V_MF4_MASK = 5049,
5074 PseudoVLSEG2E32FF_V_M1 = 5050,
5075 PseudoVLSEG2E32FF_V_M1_MASK = 5051,
5076 PseudoVLSEG2E32FF_V_M2 = 5052,
5077 PseudoVLSEG2E32FF_V_M2_MASK = 5053,
5078 PseudoVLSEG2E32FF_V_M4 = 5054,
5079 PseudoVLSEG2E32FF_V_M4_MASK = 5055,
5080 PseudoVLSEG2E32FF_V_MF2 = 5056,
5081 PseudoVLSEG2E32FF_V_MF2_MASK = 5057,
5082 PseudoVLSEG2E32_V_M1 = 5058,
5083 PseudoVLSEG2E32_V_M1_MASK = 5059,
5084 PseudoVLSEG2E32_V_M2 = 5060,
5085 PseudoVLSEG2E32_V_M2_MASK = 5061,
5086 PseudoVLSEG2E32_V_M4 = 5062,
5087 PseudoVLSEG2E32_V_M4_MASK = 5063,
5088 PseudoVLSEG2E32_V_MF2 = 5064,
5089 PseudoVLSEG2E32_V_MF2_MASK = 5065,
5090 PseudoVLSEG2E64FF_V_M1 = 5066,
5091 PseudoVLSEG2E64FF_V_M1_MASK = 5067,
5092 PseudoVLSEG2E64FF_V_M2 = 5068,
5093 PseudoVLSEG2E64FF_V_M2_MASK = 5069,
5094 PseudoVLSEG2E64FF_V_M4 = 5070,
5095 PseudoVLSEG2E64FF_V_M4_MASK = 5071,
5096 PseudoVLSEG2E64_V_M1 = 5072,
5097 PseudoVLSEG2E64_V_M1_MASK = 5073,
5098 PseudoVLSEG2E64_V_M2 = 5074,
5099 PseudoVLSEG2E64_V_M2_MASK = 5075,
5100 PseudoVLSEG2E64_V_M4 = 5076,
5101 PseudoVLSEG2E64_V_M4_MASK = 5077,
5102 PseudoVLSEG2E8FF_V_M1 = 5078,
5103 PseudoVLSEG2E8FF_V_M1_MASK = 5079,
5104 PseudoVLSEG2E8FF_V_M2 = 5080,
5105 PseudoVLSEG2E8FF_V_M2_MASK = 5081,
5106 PseudoVLSEG2E8FF_V_M4 = 5082,
5107 PseudoVLSEG2E8FF_V_M4_MASK = 5083,
5108 PseudoVLSEG2E8FF_V_MF2 = 5084,
5109 PseudoVLSEG2E8FF_V_MF2_MASK = 5085,
5110 PseudoVLSEG2E8FF_V_MF4 = 5086,
5111 PseudoVLSEG2E8FF_V_MF4_MASK = 5087,
5112 PseudoVLSEG2E8FF_V_MF8 = 5088,
5113 PseudoVLSEG2E8FF_V_MF8_MASK = 5089,
5114 PseudoVLSEG2E8_V_M1 = 5090,
5115 PseudoVLSEG2E8_V_M1_MASK = 5091,
5116 PseudoVLSEG2E8_V_M2 = 5092,
5117 PseudoVLSEG2E8_V_M2_MASK = 5093,
5118 PseudoVLSEG2E8_V_M4 = 5094,
5119 PseudoVLSEG2E8_V_M4_MASK = 5095,
5120 PseudoVLSEG2E8_V_MF2 = 5096,
5121 PseudoVLSEG2E8_V_MF2_MASK = 5097,
5122 PseudoVLSEG2E8_V_MF4 = 5098,
5123 PseudoVLSEG2E8_V_MF4_MASK = 5099,
5124 PseudoVLSEG2E8_V_MF8 = 5100,
5125 PseudoVLSEG2E8_V_MF8_MASK = 5101,
5126 PseudoVLSEG3E16FF_V_M1 = 5102,
5127 PseudoVLSEG3E16FF_V_M1_MASK = 5103,
5128 PseudoVLSEG3E16FF_V_M2 = 5104,
5129 PseudoVLSEG3E16FF_V_M2_MASK = 5105,
5130 PseudoVLSEG3E16FF_V_MF2 = 5106,
5131 PseudoVLSEG3E16FF_V_MF2_MASK = 5107,
5132 PseudoVLSEG3E16FF_V_MF4 = 5108,
5133 PseudoVLSEG3E16FF_V_MF4_MASK = 5109,
5134 PseudoVLSEG3E16_V_M1 = 5110,
5135 PseudoVLSEG3E16_V_M1_MASK = 5111,
5136 PseudoVLSEG3E16_V_M2 = 5112,
5137 PseudoVLSEG3E16_V_M2_MASK = 5113,
5138 PseudoVLSEG3E16_V_MF2 = 5114,
5139 PseudoVLSEG3E16_V_MF2_MASK = 5115,
5140 PseudoVLSEG3E16_V_MF4 = 5116,
5141 PseudoVLSEG3E16_V_MF4_MASK = 5117,
5142 PseudoVLSEG3E32FF_V_M1 = 5118,
5143 PseudoVLSEG3E32FF_V_M1_MASK = 5119,
5144 PseudoVLSEG3E32FF_V_M2 = 5120,
5145 PseudoVLSEG3E32FF_V_M2_MASK = 5121,
5146 PseudoVLSEG3E32FF_V_MF2 = 5122,
5147 PseudoVLSEG3E32FF_V_MF2_MASK = 5123,
5148 PseudoVLSEG3E32_V_M1 = 5124,
5149 PseudoVLSEG3E32_V_M1_MASK = 5125,
5150 PseudoVLSEG3E32_V_M2 = 5126,
5151 PseudoVLSEG3E32_V_M2_MASK = 5127,
5152 PseudoVLSEG3E32_V_MF2 = 5128,
5153 PseudoVLSEG3E32_V_MF2_MASK = 5129,
5154 PseudoVLSEG3E64FF_V_M1 = 5130,
5155 PseudoVLSEG3E64FF_V_M1_MASK = 5131,
5156 PseudoVLSEG3E64FF_V_M2 = 5132,
5157 PseudoVLSEG3E64FF_V_M2_MASK = 5133,
5158 PseudoVLSEG3E64_V_M1 = 5134,
5159 PseudoVLSEG3E64_V_M1_MASK = 5135,
5160 PseudoVLSEG3E64_V_M2 = 5136,
5161 PseudoVLSEG3E64_V_M2_MASK = 5137,
5162 PseudoVLSEG3E8FF_V_M1 = 5138,
5163 PseudoVLSEG3E8FF_V_M1_MASK = 5139,
5164 PseudoVLSEG3E8FF_V_M2 = 5140,
5165 PseudoVLSEG3E8FF_V_M2_MASK = 5141,
5166 PseudoVLSEG3E8FF_V_MF2 = 5142,
5167 PseudoVLSEG3E8FF_V_MF2_MASK = 5143,
5168 PseudoVLSEG3E8FF_V_MF4 = 5144,
5169 PseudoVLSEG3E8FF_V_MF4_MASK = 5145,
5170 PseudoVLSEG3E8FF_V_MF8 = 5146,
5171 PseudoVLSEG3E8FF_V_MF8_MASK = 5147,
5172 PseudoVLSEG3E8_V_M1 = 5148,
5173 PseudoVLSEG3E8_V_M1_MASK = 5149,
5174 PseudoVLSEG3E8_V_M2 = 5150,
5175 PseudoVLSEG3E8_V_M2_MASK = 5151,
5176 PseudoVLSEG3E8_V_MF2 = 5152,
5177 PseudoVLSEG3E8_V_MF2_MASK = 5153,
5178 PseudoVLSEG3E8_V_MF4 = 5154,
5179 PseudoVLSEG3E8_V_MF4_MASK = 5155,
5180 PseudoVLSEG3E8_V_MF8 = 5156,
5181 PseudoVLSEG3E8_V_MF8_MASK = 5157,
5182 PseudoVLSEG4E16FF_V_M1 = 5158,
5183 PseudoVLSEG4E16FF_V_M1_MASK = 5159,
5184 PseudoVLSEG4E16FF_V_M2 = 5160,
5185 PseudoVLSEG4E16FF_V_M2_MASK = 5161,
5186 PseudoVLSEG4E16FF_V_MF2 = 5162,
5187 PseudoVLSEG4E16FF_V_MF2_MASK = 5163,
5188 PseudoVLSEG4E16FF_V_MF4 = 5164,
5189 PseudoVLSEG4E16FF_V_MF4_MASK = 5165,
5190 PseudoVLSEG4E16_V_M1 = 5166,
5191 PseudoVLSEG4E16_V_M1_MASK = 5167,
5192 PseudoVLSEG4E16_V_M2 = 5168,
5193 PseudoVLSEG4E16_V_M2_MASK = 5169,
5194 PseudoVLSEG4E16_V_MF2 = 5170,
5195 PseudoVLSEG4E16_V_MF2_MASK = 5171,
5196 PseudoVLSEG4E16_V_MF4 = 5172,
5197 PseudoVLSEG4E16_V_MF4_MASK = 5173,
5198 PseudoVLSEG4E32FF_V_M1 = 5174,
5199 PseudoVLSEG4E32FF_V_M1_MASK = 5175,
5200 PseudoVLSEG4E32FF_V_M2 = 5176,
5201 PseudoVLSEG4E32FF_V_M2_MASK = 5177,
5202 PseudoVLSEG4E32FF_V_MF2 = 5178,
5203 PseudoVLSEG4E32FF_V_MF2_MASK = 5179,
5204 PseudoVLSEG4E32_V_M1 = 5180,
5205 PseudoVLSEG4E32_V_M1_MASK = 5181,
5206 PseudoVLSEG4E32_V_M2 = 5182,
5207 PseudoVLSEG4E32_V_M2_MASK = 5183,
5208 PseudoVLSEG4E32_V_MF2 = 5184,
5209 PseudoVLSEG4E32_V_MF2_MASK = 5185,
5210 PseudoVLSEG4E64FF_V_M1 = 5186,
5211 PseudoVLSEG4E64FF_V_M1_MASK = 5187,
5212 PseudoVLSEG4E64FF_V_M2 = 5188,
5213 PseudoVLSEG4E64FF_V_M2_MASK = 5189,
5214 PseudoVLSEG4E64_V_M1 = 5190,
5215 PseudoVLSEG4E64_V_M1_MASK = 5191,
5216 PseudoVLSEG4E64_V_M2 = 5192,
5217 PseudoVLSEG4E64_V_M2_MASK = 5193,
5218 PseudoVLSEG4E8FF_V_M1 = 5194,
5219 PseudoVLSEG4E8FF_V_M1_MASK = 5195,
5220 PseudoVLSEG4E8FF_V_M2 = 5196,
5221 PseudoVLSEG4E8FF_V_M2_MASK = 5197,
5222 PseudoVLSEG4E8FF_V_MF2 = 5198,
5223 PseudoVLSEG4E8FF_V_MF2_MASK = 5199,
5224 PseudoVLSEG4E8FF_V_MF4 = 5200,
5225 PseudoVLSEG4E8FF_V_MF4_MASK = 5201,
5226 PseudoVLSEG4E8FF_V_MF8 = 5202,
5227 PseudoVLSEG4E8FF_V_MF8_MASK = 5203,
5228 PseudoVLSEG4E8_V_M1 = 5204,
5229 PseudoVLSEG4E8_V_M1_MASK = 5205,
5230 PseudoVLSEG4E8_V_M2 = 5206,
5231 PseudoVLSEG4E8_V_M2_MASK = 5207,
5232 PseudoVLSEG4E8_V_MF2 = 5208,
5233 PseudoVLSEG4E8_V_MF2_MASK = 5209,
5234 PseudoVLSEG4E8_V_MF4 = 5210,
5235 PseudoVLSEG4E8_V_MF4_MASK = 5211,
5236 PseudoVLSEG4E8_V_MF8 = 5212,
5237 PseudoVLSEG4E8_V_MF8_MASK = 5213,
5238 PseudoVLSEG5E16FF_V_M1 = 5214,
5239 PseudoVLSEG5E16FF_V_M1_MASK = 5215,
5240 PseudoVLSEG5E16FF_V_MF2 = 5216,
5241 PseudoVLSEG5E16FF_V_MF2_MASK = 5217,
5242 PseudoVLSEG5E16FF_V_MF4 = 5218,
5243 PseudoVLSEG5E16FF_V_MF4_MASK = 5219,
5244 PseudoVLSEG5E16_V_M1 = 5220,
5245 PseudoVLSEG5E16_V_M1_MASK = 5221,
5246 PseudoVLSEG5E16_V_MF2 = 5222,
5247 PseudoVLSEG5E16_V_MF2_MASK = 5223,
5248 PseudoVLSEG5E16_V_MF4 = 5224,
5249 PseudoVLSEG5E16_V_MF4_MASK = 5225,
5250 PseudoVLSEG5E32FF_V_M1 = 5226,
5251 PseudoVLSEG5E32FF_V_M1_MASK = 5227,
5252 PseudoVLSEG5E32FF_V_MF2 = 5228,
5253 PseudoVLSEG5E32FF_V_MF2_MASK = 5229,
5254 PseudoVLSEG5E32_V_M1 = 5230,
5255 PseudoVLSEG5E32_V_M1_MASK = 5231,
5256 PseudoVLSEG5E32_V_MF2 = 5232,
5257 PseudoVLSEG5E32_V_MF2_MASK = 5233,
5258 PseudoVLSEG5E64FF_V_M1 = 5234,
5259 PseudoVLSEG5E64FF_V_M1_MASK = 5235,
5260 PseudoVLSEG5E64_V_M1 = 5236,
5261 PseudoVLSEG5E64_V_M1_MASK = 5237,
5262 PseudoVLSEG5E8FF_V_M1 = 5238,
5263 PseudoVLSEG5E8FF_V_M1_MASK = 5239,
5264 PseudoVLSEG5E8FF_V_MF2 = 5240,
5265 PseudoVLSEG5E8FF_V_MF2_MASK = 5241,
5266 PseudoVLSEG5E8FF_V_MF4 = 5242,
5267 PseudoVLSEG5E8FF_V_MF4_MASK = 5243,
5268 PseudoVLSEG5E8FF_V_MF8 = 5244,
5269 PseudoVLSEG5E8FF_V_MF8_MASK = 5245,
5270 PseudoVLSEG5E8_V_M1 = 5246,
5271 PseudoVLSEG5E8_V_M1_MASK = 5247,
5272 PseudoVLSEG5E8_V_MF2 = 5248,
5273 PseudoVLSEG5E8_V_MF2_MASK = 5249,
5274 PseudoVLSEG5E8_V_MF4 = 5250,
5275 PseudoVLSEG5E8_V_MF4_MASK = 5251,
5276 PseudoVLSEG5E8_V_MF8 = 5252,
5277 PseudoVLSEG5E8_V_MF8_MASK = 5253,
5278 PseudoVLSEG6E16FF_V_M1 = 5254,
5279 PseudoVLSEG6E16FF_V_M1_MASK = 5255,
5280 PseudoVLSEG6E16FF_V_MF2 = 5256,
5281 PseudoVLSEG6E16FF_V_MF2_MASK = 5257,
5282 PseudoVLSEG6E16FF_V_MF4 = 5258,
5283 PseudoVLSEG6E16FF_V_MF4_MASK = 5259,
5284 PseudoVLSEG6E16_V_M1 = 5260,
5285 PseudoVLSEG6E16_V_M1_MASK = 5261,
5286 PseudoVLSEG6E16_V_MF2 = 5262,
5287 PseudoVLSEG6E16_V_MF2_MASK = 5263,
5288 PseudoVLSEG6E16_V_MF4 = 5264,
5289 PseudoVLSEG6E16_V_MF4_MASK = 5265,
5290 PseudoVLSEG6E32FF_V_M1 = 5266,
5291 PseudoVLSEG6E32FF_V_M1_MASK = 5267,
5292 PseudoVLSEG6E32FF_V_MF2 = 5268,
5293 PseudoVLSEG6E32FF_V_MF2_MASK = 5269,
5294 PseudoVLSEG6E32_V_M1 = 5270,
5295 PseudoVLSEG6E32_V_M1_MASK = 5271,
5296 PseudoVLSEG6E32_V_MF2 = 5272,
5297 PseudoVLSEG6E32_V_MF2_MASK = 5273,
5298 PseudoVLSEG6E64FF_V_M1 = 5274,
5299 PseudoVLSEG6E64FF_V_M1_MASK = 5275,
5300 PseudoVLSEG6E64_V_M1 = 5276,
5301 PseudoVLSEG6E64_V_M1_MASK = 5277,
5302 PseudoVLSEG6E8FF_V_M1 = 5278,
5303 PseudoVLSEG6E8FF_V_M1_MASK = 5279,
5304 PseudoVLSEG6E8FF_V_MF2 = 5280,
5305 PseudoVLSEG6E8FF_V_MF2_MASK = 5281,
5306 PseudoVLSEG6E8FF_V_MF4 = 5282,
5307 PseudoVLSEG6E8FF_V_MF4_MASK = 5283,
5308 PseudoVLSEG6E8FF_V_MF8 = 5284,
5309 PseudoVLSEG6E8FF_V_MF8_MASK = 5285,
5310 PseudoVLSEG6E8_V_M1 = 5286,
5311 PseudoVLSEG6E8_V_M1_MASK = 5287,
5312 PseudoVLSEG6E8_V_MF2 = 5288,
5313 PseudoVLSEG6E8_V_MF2_MASK = 5289,
5314 PseudoVLSEG6E8_V_MF4 = 5290,
5315 PseudoVLSEG6E8_V_MF4_MASK = 5291,
5316 PseudoVLSEG6E8_V_MF8 = 5292,
5317 PseudoVLSEG6E8_V_MF8_MASK = 5293,
5318 PseudoVLSEG7E16FF_V_M1 = 5294,
5319 PseudoVLSEG7E16FF_V_M1_MASK = 5295,
5320 PseudoVLSEG7E16FF_V_MF2 = 5296,
5321 PseudoVLSEG7E16FF_V_MF2_MASK = 5297,
5322 PseudoVLSEG7E16FF_V_MF4 = 5298,
5323 PseudoVLSEG7E16FF_V_MF4_MASK = 5299,
5324 PseudoVLSEG7E16_V_M1 = 5300,
5325 PseudoVLSEG7E16_V_M1_MASK = 5301,
5326 PseudoVLSEG7E16_V_MF2 = 5302,
5327 PseudoVLSEG7E16_V_MF2_MASK = 5303,
5328 PseudoVLSEG7E16_V_MF4 = 5304,
5329 PseudoVLSEG7E16_V_MF4_MASK = 5305,
5330 PseudoVLSEG7E32FF_V_M1 = 5306,
5331 PseudoVLSEG7E32FF_V_M1_MASK = 5307,
5332 PseudoVLSEG7E32FF_V_MF2 = 5308,
5333 PseudoVLSEG7E32FF_V_MF2_MASK = 5309,
5334 PseudoVLSEG7E32_V_M1 = 5310,
5335 PseudoVLSEG7E32_V_M1_MASK = 5311,
5336 PseudoVLSEG7E32_V_MF2 = 5312,
5337 PseudoVLSEG7E32_V_MF2_MASK = 5313,
5338 PseudoVLSEG7E64FF_V_M1 = 5314,
5339 PseudoVLSEG7E64FF_V_M1_MASK = 5315,
5340 PseudoVLSEG7E64_V_M1 = 5316,
5341 PseudoVLSEG7E64_V_M1_MASK = 5317,
5342 PseudoVLSEG7E8FF_V_M1 = 5318,
5343 PseudoVLSEG7E8FF_V_M1_MASK = 5319,
5344 PseudoVLSEG7E8FF_V_MF2 = 5320,
5345 PseudoVLSEG7E8FF_V_MF2_MASK = 5321,
5346 PseudoVLSEG7E8FF_V_MF4 = 5322,
5347 PseudoVLSEG7E8FF_V_MF4_MASK = 5323,
5348 PseudoVLSEG7E8FF_V_MF8 = 5324,
5349 PseudoVLSEG7E8FF_V_MF8_MASK = 5325,
5350 PseudoVLSEG7E8_V_M1 = 5326,
5351 PseudoVLSEG7E8_V_M1_MASK = 5327,
5352 PseudoVLSEG7E8_V_MF2 = 5328,
5353 PseudoVLSEG7E8_V_MF2_MASK = 5329,
5354 PseudoVLSEG7E8_V_MF4 = 5330,
5355 PseudoVLSEG7E8_V_MF4_MASK = 5331,
5356 PseudoVLSEG7E8_V_MF8 = 5332,
5357 PseudoVLSEG7E8_V_MF8_MASK = 5333,
5358 PseudoVLSEG8E16FF_V_M1 = 5334,
5359 PseudoVLSEG8E16FF_V_M1_MASK = 5335,
5360 PseudoVLSEG8E16FF_V_MF2 = 5336,
5361 PseudoVLSEG8E16FF_V_MF2_MASK = 5337,
5362 PseudoVLSEG8E16FF_V_MF4 = 5338,
5363 PseudoVLSEG8E16FF_V_MF4_MASK = 5339,
5364 PseudoVLSEG8E16_V_M1 = 5340,
5365 PseudoVLSEG8E16_V_M1_MASK = 5341,
5366 PseudoVLSEG8E16_V_MF2 = 5342,
5367 PseudoVLSEG8E16_V_MF2_MASK = 5343,
5368 PseudoVLSEG8E16_V_MF4 = 5344,
5369 PseudoVLSEG8E16_V_MF4_MASK = 5345,
5370 PseudoVLSEG8E32FF_V_M1 = 5346,
5371 PseudoVLSEG8E32FF_V_M1_MASK = 5347,
5372 PseudoVLSEG8E32FF_V_MF2 = 5348,
5373 PseudoVLSEG8E32FF_V_MF2_MASK = 5349,
5374 PseudoVLSEG8E32_V_M1 = 5350,
5375 PseudoVLSEG8E32_V_M1_MASK = 5351,
5376 PseudoVLSEG8E32_V_MF2 = 5352,
5377 PseudoVLSEG8E32_V_MF2_MASK = 5353,
5378 PseudoVLSEG8E64FF_V_M1 = 5354,
5379 PseudoVLSEG8E64FF_V_M1_MASK = 5355,
5380 PseudoVLSEG8E64_V_M1 = 5356,
5381 PseudoVLSEG8E64_V_M1_MASK = 5357,
5382 PseudoVLSEG8E8FF_V_M1 = 5358,
5383 PseudoVLSEG8E8FF_V_M1_MASK = 5359,
5384 PseudoVLSEG8E8FF_V_MF2 = 5360,
5385 PseudoVLSEG8E8FF_V_MF2_MASK = 5361,
5386 PseudoVLSEG8E8FF_V_MF4 = 5362,
5387 PseudoVLSEG8E8FF_V_MF4_MASK = 5363,
5388 PseudoVLSEG8E8FF_V_MF8 = 5364,
5389 PseudoVLSEG8E8FF_V_MF8_MASK = 5365,
5390 PseudoVLSEG8E8_V_M1 = 5366,
5391 PseudoVLSEG8E8_V_M1_MASK = 5367,
5392 PseudoVLSEG8E8_V_MF2 = 5368,
5393 PseudoVLSEG8E8_V_MF2_MASK = 5369,
5394 PseudoVLSEG8E8_V_MF4 = 5370,
5395 PseudoVLSEG8E8_V_MF4_MASK = 5371,
5396 PseudoVLSEG8E8_V_MF8 = 5372,
5397 PseudoVLSEG8E8_V_MF8_MASK = 5373,
5398 PseudoVLSSEG2E16_V_M1 = 5374,
5399 PseudoVLSSEG2E16_V_M1_MASK = 5375,
5400 PseudoVLSSEG2E16_V_M2 = 5376,
5401 PseudoVLSSEG2E16_V_M2_MASK = 5377,
5402 PseudoVLSSEG2E16_V_M4 = 5378,
5403 PseudoVLSSEG2E16_V_M4_MASK = 5379,
5404 PseudoVLSSEG2E16_V_MF2 = 5380,
5405 PseudoVLSSEG2E16_V_MF2_MASK = 5381,
5406 PseudoVLSSEG2E16_V_MF4 = 5382,
5407 PseudoVLSSEG2E16_V_MF4_MASK = 5383,
5408 PseudoVLSSEG2E32_V_M1 = 5384,
5409 PseudoVLSSEG2E32_V_M1_MASK = 5385,
5410 PseudoVLSSEG2E32_V_M2 = 5386,
5411 PseudoVLSSEG2E32_V_M2_MASK = 5387,
5412 PseudoVLSSEG2E32_V_M4 = 5388,
5413 PseudoVLSSEG2E32_V_M4_MASK = 5389,
5414 PseudoVLSSEG2E32_V_MF2 = 5390,
5415 PseudoVLSSEG2E32_V_MF2_MASK = 5391,
5416 PseudoVLSSEG2E64_V_M1 = 5392,
5417 PseudoVLSSEG2E64_V_M1_MASK = 5393,
5418 PseudoVLSSEG2E64_V_M2 = 5394,
5419 PseudoVLSSEG2E64_V_M2_MASK = 5395,
5420 PseudoVLSSEG2E64_V_M4 = 5396,
5421 PseudoVLSSEG2E64_V_M4_MASK = 5397,
5422 PseudoVLSSEG2E8_V_M1 = 5398,
5423 PseudoVLSSEG2E8_V_M1_MASK = 5399,
5424 PseudoVLSSEG2E8_V_M2 = 5400,
5425 PseudoVLSSEG2E8_V_M2_MASK = 5401,
5426 PseudoVLSSEG2E8_V_M4 = 5402,
5427 PseudoVLSSEG2E8_V_M4_MASK = 5403,
5428 PseudoVLSSEG2E8_V_MF2 = 5404,
5429 PseudoVLSSEG2E8_V_MF2_MASK = 5405,
5430 PseudoVLSSEG2E8_V_MF4 = 5406,
5431 PseudoVLSSEG2E8_V_MF4_MASK = 5407,
5432 PseudoVLSSEG2E8_V_MF8 = 5408,
5433 PseudoVLSSEG2E8_V_MF8_MASK = 5409,
5434 PseudoVLSSEG3E16_V_M1 = 5410,
5435 PseudoVLSSEG3E16_V_M1_MASK = 5411,
5436 PseudoVLSSEG3E16_V_M2 = 5412,
5437 PseudoVLSSEG3E16_V_M2_MASK = 5413,
5438 PseudoVLSSEG3E16_V_MF2 = 5414,
5439 PseudoVLSSEG3E16_V_MF2_MASK = 5415,
5440 PseudoVLSSEG3E16_V_MF4 = 5416,
5441 PseudoVLSSEG3E16_V_MF4_MASK = 5417,
5442 PseudoVLSSEG3E32_V_M1 = 5418,
5443 PseudoVLSSEG3E32_V_M1_MASK = 5419,
5444 PseudoVLSSEG3E32_V_M2 = 5420,
5445 PseudoVLSSEG3E32_V_M2_MASK = 5421,
5446 PseudoVLSSEG3E32_V_MF2 = 5422,
5447 PseudoVLSSEG3E32_V_MF2_MASK = 5423,
5448 PseudoVLSSEG3E64_V_M1 = 5424,
5449 PseudoVLSSEG3E64_V_M1_MASK = 5425,
5450 PseudoVLSSEG3E64_V_M2 = 5426,
5451 PseudoVLSSEG3E64_V_M2_MASK = 5427,
5452 PseudoVLSSEG3E8_V_M1 = 5428,
5453 PseudoVLSSEG3E8_V_M1_MASK = 5429,
5454 PseudoVLSSEG3E8_V_M2 = 5430,
5455 PseudoVLSSEG3E8_V_M2_MASK = 5431,
5456 PseudoVLSSEG3E8_V_MF2 = 5432,
5457 PseudoVLSSEG3E8_V_MF2_MASK = 5433,
5458 PseudoVLSSEG3E8_V_MF4 = 5434,
5459 PseudoVLSSEG3E8_V_MF4_MASK = 5435,
5460 PseudoVLSSEG3E8_V_MF8 = 5436,
5461 PseudoVLSSEG3E8_V_MF8_MASK = 5437,
5462 PseudoVLSSEG4E16_V_M1 = 5438,
5463 PseudoVLSSEG4E16_V_M1_MASK = 5439,
5464 PseudoVLSSEG4E16_V_M2 = 5440,
5465 PseudoVLSSEG4E16_V_M2_MASK = 5441,
5466 PseudoVLSSEG4E16_V_MF2 = 5442,
5467 PseudoVLSSEG4E16_V_MF2_MASK = 5443,
5468 PseudoVLSSEG4E16_V_MF4 = 5444,
5469 PseudoVLSSEG4E16_V_MF4_MASK = 5445,
5470 PseudoVLSSEG4E32_V_M1 = 5446,
5471 PseudoVLSSEG4E32_V_M1_MASK = 5447,
5472 PseudoVLSSEG4E32_V_M2 = 5448,
5473 PseudoVLSSEG4E32_V_M2_MASK = 5449,
5474 PseudoVLSSEG4E32_V_MF2 = 5450,
5475 PseudoVLSSEG4E32_V_MF2_MASK = 5451,
5476 PseudoVLSSEG4E64_V_M1 = 5452,
5477 PseudoVLSSEG4E64_V_M1_MASK = 5453,
5478 PseudoVLSSEG4E64_V_M2 = 5454,
5479 PseudoVLSSEG4E64_V_M2_MASK = 5455,
5480 PseudoVLSSEG4E8_V_M1 = 5456,
5481 PseudoVLSSEG4E8_V_M1_MASK = 5457,
5482 PseudoVLSSEG4E8_V_M2 = 5458,
5483 PseudoVLSSEG4E8_V_M2_MASK = 5459,
5484 PseudoVLSSEG4E8_V_MF2 = 5460,
5485 PseudoVLSSEG4E8_V_MF2_MASK = 5461,
5486 PseudoVLSSEG4E8_V_MF4 = 5462,
5487 PseudoVLSSEG4E8_V_MF4_MASK = 5463,
5488 PseudoVLSSEG4E8_V_MF8 = 5464,
5489 PseudoVLSSEG4E8_V_MF8_MASK = 5465,
5490 PseudoVLSSEG5E16_V_M1 = 5466,
5491 PseudoVLSSEG5E16_V_M1_MASK = 5467,
5492 PseudoVLSSEG5E16_V_MF2 = 5468,
5493 PseudoVLSSEG5E16_V_MF2_MASK = 5469,
5494 PseudoVLSSEG5E16_V_MF4 = 5470,
5495 PseudoVLSSEG5E16_V_MF4_MASK = 5471,
5496 PseudoVLSSEG5E32_V_M1 = 5472,
5497 PseudoVLSSEG5E32_V_M1_MASK = 5473,
5498 PseudoVLSSEG5E32_V_MF2 = 5474,
5499 PseudoVLSSEG5E32_V_MF2_MASK = 5475,
5500 PseudoVLSSEG5E64_V_M1 = 5476,
5501 PseudoVLSSEG5E64_V_M1_MASK = 5477,
5502 PseudoVLSSEG5E8_V_M1 = 5478,
5503 PseudoVLSSEG5E8_V_M1_MASK = 5479,
5504 PseudoVLSSEG5E8_V_MF2 = 5480,
5505 PseudoVLSSEG5E8_V_MF2_MASK = 5481,
5506 PseudoVLSSEG5E8_V_MF4 = 5482,
5507 PseudoVLSSEG5E8_V_MF4_MASK = 5483,
5508 PseudoVLSSEG5E8_V_MF8 = 5484,
5509 PseudoVLSSEG5E8_V_MF8_MASK = 5485,
5510 PseudoVLSSEG6E16_V_M1 = 5486,
5511 PseudoVLSSEG6E16_V_M1_MASK = 5487,
5512 PseudoVLSSEG6E16_V_MF2 = 5488,
5513 PseudoVLSSEG6E16_V_MF2_MASK = 5489,
5514 PseudoVLSSEG6E16_V_MF4 = 5490,
5515 PseudoVLSSEG6E16_V_MF4_MASK = 5491,
5516 PseudoVLSSEG6E32_V_M1 = 5492,
5517 PseudoVLSSEG6E32_V_M1_MASK = 5493,
5518 PseudoVLSSEG6E32_V_MF2 = 5494,
5519 PseudoVLSSEG6E32_V_MF2_MASK = 5495,
5520 PseudoVLSSEG6E64_V_M1 = 5496,
5521 PseudoVLSSEG6E64_V_M1_MASK = 5497,
5522 PseudoVLSSEG6E8_V_M1 = 5498,
5523 PseudoVLSSEG6E8_V_M1_MASK = 5499,
5524 PseudoVLSSEG6E8_V_MF2 = 5500,
5525 PseudoVLSSEG6E8_V_MF2_MASK = 5501,
5526 PseudoVLSSEG6E8_V_MF4 = 5502,
5527 PseudoVLSSEG6E8_V_MF4_MASK = 5503,
5528 PseudoVLSSEG6E8_V_MF8 = 5504,
5529 PseudoVLSSEG6E8_V_MF8_MASK = 5505,
5530 PseudoVLSSEG7E16_V_M1 = 5506,
5531 PseudoVLSSEG7E16_V_M1_MASK = 5507,
5532 PseudoVLSSEG7E16_V_MF2 = 5508,
5533 PseudoVLSSEG7E16_V_MF2_MASK = 5509,
5534 PseudoVLSSEG7E16_V_MF4 = 5510,
5535 PseudoVLSSEG7E16_V_MF4_MASK = 5511,
5536 PseudoVLSSEG7E32_V_M1 = 5512,
5537 PseudoVLSSEG7E32_V_M1_MASK = 5513,
5538 PseudoVLSSEG7E32_V_MF2 = 5514,
5539 PseudoVLSSEG7E32_V_MF2_MASK = 5515,
5540 PseudoVLSSEG7E64_V_M1 = 5516,
5541 PseudoVLSSEG7E64_V_M1_MASK = 5517,
5542 PseudoVLSSEG7E8_V_M1 = 5518,
5543 PseudoVLSSEG7E8_V_M1_MASK = 5519,
5544 PseudoVLSSEG7E8_V_MF2 = 5520,
5545 PseudoVLSSEG7E8_V_MF2_MASK = 5521,
5546 PseudoVLSSEG7E8_V_MF4 = 5522,
5547 PseudoVLSSEG7E8_V_MF4_MASK = 5523,
5548 PseudoVLSSEG7E8_V_MF8 = 5524,
5549 PseudoVLSSEG7E8_V_MF8_MASK = 5525,
5550 PseudoVLSSEG8E16_V_M1 = 5526,
5551 PseudoVLSSEG8E16_V_M1_MASK = 5527,
5552 PseudoVLSSEG8E16_V_MF2 = 5528,
5553 PseudoVLSSEG8E16_V_MF2_MASK = 5529,
5554 PseudoVLSSEG8E16_V_MF4 = 5530,
5555 PseudoVLSSEG8E16_V_MF4_MASK = 5531,
5556 PseudoVLSSEG8E32_V_M1 = 5532,
5557 PseudoVLSSEG8E32_V_M1_MASK = 5533,
5558 PseudoVLSSEG8E32_V_MF2 = 5534,
5559 PseudoVLSSEG8E32_V_MF2_MASK = 5535,
5560 PseudoVLSSEG8E64_V_M1 = 5536,
5561 PseudoVLSSEG8E64_V_M1_MASK = 5537,
5562 PseudoVLSSEG8E8_V_M1 = 5538,
5563 PseudoVLSSEG8E8_V_M1_MASK = 5539,
5564 PseudoVLSSEG8E8_V_MF2 = 5540,
5565 PseudoVLSSEG8E8_V_MF2_MASK = 5541,
5566 PseudoVLSSEG8E8_V_MF4 = 5542,
5567 PseudoVLSSEG8E8_V_MF4_MASK = 5543,
5568 PseudoVLSSEG8E8_V_MF8 = 5544,
5569 PseudoVLSSEG8E8_V_MF8_MASK = 5545,
5570 PseudoVLUXEI16_V_M1_M1 = 5546,
5571 PseudoVLUXEI16_V_M1_M1_MASK = 5547,
5572 PseudoVLUXEI16_V_M1_M2 = 5548,
5573 PseudoVLUXEI16_V_M1_M2_MASK = 5549,
5574 PseudoVLUXEI16_V_M1_M4 = 5550,
5575 PseudoVLUXEI16_V_M1_M4_MASK = 5551,
5576 PseudoVLUXEI16_V_M1_MF2 = 5552,
5577 PseudoVLUXEI16_V_M1_MF2_MASK = 5553,
5578 PseudoVLUXEI16_V_M2_M1 = 5554,
5579 PseudoVLUXEI16_V_M2_M1_MASK = 5555,
5580 PseudoVLUXEI16_V_M2_M2 = 5556,
5581 PseudoVLUXEI16_V_M2_M2_MASK = 5557,
5582 PseudoVLUXEI16_V_M2_M4 = 5558,
5583 PseudoVLUXEI16_V_M2_M4_MASK = 5559,
5584 PseudoVLUXEI16_V_M2_M8 = 5560,
5585 PseudoVLUXEI16_V_M2_M8_MASK = 5561,
5586 PseudoVLUXEI16_V_M4_M2 = 5562,
5587 PseudoVLUXEI16_V_M4_M2_MASK = 5563,
5588 PseudoVLUXEI16_V_M4_M4 = 5564,
5589 PseudoVLUXEI16_V_M4_M4_MASK = 5565,
5590 PseudoVLUXEI16_V_M4_M8 = 5566,
5591 PseudoVLUXEI16_V_M4_M8_MASK = 5567,
5592 PseudoVLUXEI16_V_M8_M4 = 5568,
5593 PseudoVLUXEI16_V_M8_M4_MASK = 5569,
5594 PseudoVLUXEI16_V_M8_M8 = 5570,
5595 PseudoVLUXEI16_V_M8_M8_MASK = 5571,
5596 PseudoVLUXEI16_V_MF2_M1 = 5572,
5597 PseudoVLUXEI16_V_MF2_M1_MASK = 5573,
5598 PseudoVLUXEI16_V_MF2_M2 = 5574,
5599 PseudoVLUXEI16_V_MF2_M2_MASK = 5575,
5600 PseudoVLUXEI16_V_MF2_MF2 = 5576,
5601 PseudoVLUXEI16_V_MF2_MF2_MASK = 5577,
5602 PseudoVLUXEI16_V_MF2_MF4 = 5578,
5603 PseudoVLUXEI16_V_MF2_MF4_MASK = 5579,
5604 PseudoVLUXEI16_V_MF4_M1 = 5580,
5605 PseudoVLUXEI16_V_MF4_M1_MASK = 5581,
5606 PseudoVLUXEI16_V_MF4_MF2 = 5582,
5607 PseudoVLUXEI16_V_MF4_MF2_MASK = 5583,
5608 PseudoVLUXEI16_V_MF4_MF4 = 5584,
5609 PseudoVLUXEI16_V_MF4_MF4_MASK = 5585,
5610 PseudoVLUXEI16_V_MF4_MF8 = 5586,
5611 PseudoVLUXEI16_V_MF4_MF8_MASK = 5587,
5612 PseudoVLUXEI32_V_M1_M1 = 5588,
5613 PseudoVLUXEI32_V_M1_M1_MASK = 5589,
5614 PseudoVLUXEI32_V_M1_M2 = 5590,
5615 PseudoVLUXEI32_V_M1_M2_MASK = 5591,
5616 PseudoVLUXEI32_V_M1_MF2 = 5592,
5617 PseudoVLUXEI32_V_M1_MF2_MASK = 5593,
5618 PseudoVLUXEI32_V_M1_MF4 = 5594,
5619 PseudoVLUXEI32_V_M1_MF4_MASK = 5595,
5620 PseudoVLUXEI32_V_M2_M1 = 5596,
5621 PseudoVLUXEI32_V_M2_M1_MASK = 5597,
5622 PseudoVLUXEI32_V_M2_M2 = 5598,
5623 PseudoVLUXEI32_V_M2_M2_MASK = 5599,
5624 PseudoVLUXEI32_V_M2_M4 = 5600,
5625 PseudoVLUXEI32_V_M2_M4_MASK = 5601,
5626 PseudoVLUXEI32_V_M2_MF2 = 5602,
5627 PseudoVLUXEI32_V_M2_MF2_MASK = 5603,
5628 PseudoVLUXEI32_V_M4_M1 = 5604,
5629 PseudoVLUXEI32_V_M4_M1_MASK = 5605,
5630 PseudoVLUXEI32_V_M4_M2 = 5606,
5631 PseudoVLUXEI32_V_M4_M2_MASK = 5607,
5632 PseudoVLUXEI32_V_M4_M4 = 5608,
5633 PseudoVLUXEI32_V_M4_M4_MASK = 5609,
5634 PseudoVLUXEI32_V_M4_M8 = 5610,
5635 PseudoVLUXEI32_V_M4_M8_MASK = 5611,
5636 PseudoVLUXEI32_V_M8_M2 = 5612,
5637 PseudoVLUXEI32_V_M8_M2_MASK = 5613,
5638 PseudoVLUXEI32_V_M8_M4 = 5614,
5639 PseudoVLUXEI32_V_M8_M4_MASK = 5615,
5640 PseudoVLUXEI32_V_M8_M8 = 5616,
5641 PseudoVLUXEI32_V_M8_M8_MASK = 5617,
5642 PseudoVLUXEI32_V_MF2_M1 = 5618,
5643 PseudoVLUXEI32_V_MF2_M1_MASK = 5619,
5644 PseudoVLUXEI32_V_MF2_MF2 = 5620,
5645 PseudoVLUXEI32_V_MF2_MF2_MASK = 5621,
5646 PseudoVLUXEI32_V_MF2_MF4 = 5622,
5647 PseudoVLUXEI32_V_MF2_MF4_MASK = 5623,
5648 PseudoVLUXEI32_V_MF2_MF8 = 5624,
5649 PseudoVLUXEI32_V_MF2_MF8_MASK = 5625,
5650 PseudoVLUXEI64_V_M1_M1 = 5626,
5651 PseudoVLUXEI64_V_M1_M1_MASK = 5627,
5652 PseudoVLUXEI64_V_M1_MF2 = 5628,
5653 PseudoVLUXEI64_V_M1_MF2_MASK = 5629,
5654 PseudoVLUXEI64_V_M1_MF4 = 5630,
5655 PseudoVLUXEI64_V_M1_MF4_MASK = 5631,
5656 PseudoVLUXEI64_V_M1_MF8 = 5632,
5657 PseudoVLUXEI64_V_M1_MF8_MASK = 5633,
5658 PseudoVLUXEI64_V_M2_M1 = 5634,
5659 PseudoVLUXEI64_V_M2_M1_MASK = 5635,
5660 PseudoVLUXEI64_V_M2_M2 = 5636,
5661 PseudoVLUXEI64_V_M2_M2_MASK = 5637,
5662 PseudoVLUXEI64_V_M2_MF2 = 5638,
5663 PseudoVLUXEI64_V_M2_MF2_MASK = 5639,
5664 PseudoVLUXEI64_V_M2_MF4 = 5640,
5665 PseudoVLUXEI64_V_M2_MF4_MASK = 5641,
5666 PseudoVLUXEI64_V_M4_M1 = 5642,
5667 PseudoVLUXEI64_V_M4_M1_MASK = 5643,
5668 PseudoVLUXEI64_V_M4_M2 = 5644,
5669 PseudoVLUXEI64_V_M4_M2_MASK = 5645,
5670 PseudoVLUXEI64_V_M4_M4 = 5646,
5671 PseudoVLUXEI64_V_M4_M4_MASK = 5647,
5672 PseudoVLUXEI64_V_M4_MF2 = 5648,
5673 PseudoVLUXEI64_V_M4_MF2_MASK = 5649,
5674 PseudoVLUXEI64_V_M8_M1 = 5650,
5675 PseudoVLUXEI64_V_M8_M1_MASK = 5651,
5676 PseudoVLUXEI64_V_M8_M2 = 5652,
5677 PseudoVLUXEI64_V_M8_M2_MASK = 5653,
5678 PseudoVLUXEI64_V_M8_M4 = 5654,
5679 PseudoVLUXEI64_V_M8_M4_MASK = 5655,
5680 PseudoVLUXEI64_V_M8_M8 = 5656,
5681 PseudoVLUXEI64_V_M8_M8_MASK = 5657,
5682 PseudoVLUXEI8_V_M1_M1 = 5658,
5683 PseudoVLUXEI8_V_M1_M1_MASK = 5659,
5684 PseudoVLUXEI8_V_M1_M2 = 5660,
5685 PseudoVLUXEI8_V_M1_M2_MASK = 5661,
5686 PseudoVLUXEI8_V_M1_M4 = 5662,
5687 PseudoVLUXEI8_V_M1_M4_MASK = 5663,
5688 PseudoVLUXEI8_V_M1_M8 = 5664,
5689 PseudoVLUXEI8_V_M1_M8_MASK = 5665,
5690 PseudoVLUXEI8_V_M2_M2 = 5666,
5691 PseudoVLUXEI8_V_M2_M2_MASK = 5667,
5692 PseudoVLUXEI8_V_M2_M4 = 5668,
5693 PseudoVLUXEI8_V_M2_M4_MASK = 5669,
5694 PseudoVLUXEI8_V_M2_M8 = 5670,
5695 PseudoVLUXEI8_V_M2_M8_MASK = 5671,
5696 PseudoVLUXEI8_V_M4_M4 = 5672,
5697 PseudoVLUXEI8_V_M4_M4_MASK = 5673,
5698 PseudoVLUXEI8_V_M4_M8 = 5674,
5699 PseudoVLUXEI8_V_M4_M8_MASK = 5675,
5700 PseudoVLUXEI8_V_M8_M8 = 5676,
5701 PseudoVLUXEI8_V_M8_M8_MASK = 5677,
5702 PseudoVLUXEI8_V_MF2_M1 = 5678,
5703 PseudoVLUXEI8_V_MF2_M1_MASK = 5679,
5704 PseudoVLUXEI8_V_MF2_M2 = 5680,
5705 PseudoVLUXEI8_V_MF2_M2_MASK = 5681,
5706 PseudoVLUXEI8_V_MF2_M4 = 5682,
5707 PseudoVLUXEI8_V_MF2_M4_MASK = 5683,
5708 PseudoVLUXEI8_V_MF2_MF2 = 5684,
5709 PseudoVLUXEI8_V_MF2_MF2_MASK = 5685,
5710 PseudoVLUXEI8_V_MF4_M1 = 5686,
5711 PseudoVLUXEI8_V_MF4_M1_MASK = 5687,
5712 PseudoVLUXEI8_V_MF4_M2 = 5688,
5713 PseudoVLUXEI8_V_MF4_M2_MASK = 5689,
5714 PseudoVLUXEI8_V_MF4_MF2 = 5690,
5715 PseudoVLUXEI8_V_MF4_MF2_MASK = 5691,
5716 PseudoVLUXEI8_V_MF4_MF4 = 5692,
5717 PseudoVLUXEI8_V_MF4_MF4_MASK = 5693,
5718 PseudoVLUXEI8_V_MF8_M1 = 5694,
5719 PseudoVLUXEI8_V_MF8_M1_MASK = 5695,
5720 PseudoVLUXEI8_V_MF8_MF2 = 5696,
5721 PseudoVLUXEI8_V_MF8_MF2_MASK = 5697,
5722 PseudoVLUXEI8_V_MF8_MF4 = 5698,
5723 PseudoVLUXEI8_V_MF8_MF4_MASK = 5699,
5724 PseudoVLUXEI8_V_MF8_MF8 = 5700,
5725 PseudoVLUXEI8_V_MF8_MF8_MASK = 5701,
5726 PseudoVLUXSEG2EI16_V_M1_M1 = 5702,
5727 PseudoVLUXSEG2EI16_V_M1_M1_MASK = 5703,
5728 PseudoVLUXSEG2EI16_V_M1_M2 = 5704,
5729 PseudoVLUXSEG2EI16_V_M1_M2_MASK = 5705,
5730 PseudoVLUXSEG2EI16_V_M1_M4 = 5706,
5731 PseudoVLUXSEG2EI16_V_M1_M4_MASK = 5707,
5732 PseudoVLUXSEG2EI16_V_M1_MF2 = 5708,
5733 PseudoVLUXSEG2EI16_V_M1_MF2_MASK = 5709,
5734 PseudoVLUXSEG2EI16_V_M2_M1 = 5710,
5735 PseudoVLUXSEG2EI16_V_M2_M1_MASK = 5711,
5736 PseudoVLUXSEG2EI16_V_M2_M2 = 5712,
5737 PseudoVLUXSEG2EI16_V_M2_M2_MASK = 5713,
5738 PseudoVLUXSEG2EI16_V_M2_M4 = 5714,
5739 PseudoVLUXSEG2EI16_V_M2_M4_MASK = 5715,
5740 PseudoVLUXSEG2EI16_V_M4_M2 = 5716,
5741 PseudoVLUXSEG2EI16_V_M4_M2_MASK = 5717,
5742 PseudoVLUXSEG2EI16_V_M4_M4 = 5718,
5743 PseudoVLUXSEG2EI16_V_M4_M4_MASK = 5719,
5744 PseudoVLUXSEG2EI16_V_M8_M4 = 5720,
5745 PseudoVLUXSEG2EI16_V_M8_M4_MASK = 5721,
5746 PseudoVLUXSEG2EI16_V_MF2_M1 = 5722,
5747 PseudoVLUXSEG2EI16_V_MF2_M1_MASK = 5723,
5748 PseudoVLUXSEG2EI16_V_MF2_M2 = 5724,
5749 PseudoVLUXSEG2EI16_V_MF2_M2_MASK = 5725,
5750 PseudoVLUXSEG2EI16_V_MF2_MF2 = 5726,
5751 PseudoVLUXSEG2EI16_V_MF2_MF2_MASK = 5727,
5752 PseudoVLUXSEG2EI16_V_MF2_MF4 = 5728,
5753 PseudoVLUXSEG2EI16_V_MF2_MF4_MASK = 5729,
5754 PseudoVLUXSEG2EI16_V_MF4_M1 = 5730,
5755 PseudoVLUXSEG2EI16_V_MF4_M1_MASK = 5731,
5756 PseudoVLUXSEG2EI16_V_MF4_MF2 = 5732,
5757 PseudoVLUXSEG2EI16_V_MF4_MF2_MASK = 5733,
5758 PseudoVLUXSEG2EI16_V_MF4_MF4 = 5734,
5759 PseudoVLUXSEG2EI16_V_MF4_MF4_MASK = 5735,
5760 PseudoVLUXSEG2EI16_V_MF4_MF8 = 5736,
5761 PseudoVLUXSEG2EI16_V_MF4_MF8_MASK = 5737,
5762 PseudoVLUXSEG2EI32_V_M1_M1 = 5738,
5763 PseudoVLUXSEG2EI32_V_M1_M1_MASK = 5739,
5764 PseudoVLUXSEG2EI32_V_M1_M2 = 5740,
5765 PseudoVLUXSEG2EI32_V_M1_M2_MASK = 5741,
5766 PseudoVLUXSEG2EI32_V_M1_MF2 = 5742,
5767 PseudoVLUXSEG2EI32_V_M1_MF2_MASK = 5743,
5768 PseudoVLUXSEG2EI32_V_M1_MF4 = 5744,
5769 PseudoVLUXSEG2EI32_V_M1_MF4_MASK = 5745,
5770 PseudoVLUXSEG2EI32_V_M2_M1 = 5746,
5771 PseudoVLUXSEG2EI32_V_M2_M1_MASK = 5747,
5772 PseudoVLUXSEG2EI32_V_M2_M2 = 5748,
5773 PseudoVLUXSEG2EI32_V_M2_M2_MASK = 5749,
5774 PseudoVLUXSEG2EI32_V_M2_M4 = 5750,
5775 PseudoVLUXSEG2EI32_V_M2_M4_MASK = 5751,
5776 PseudoVLUXSEG2EI32_V_M2_MF2 = 5752,
5777 PseudoVLUXSEG2EI32_V_M2_MF2_MASK = 5753,
5778 PseudoVLUXSEG2EI32_V_M4_M1 = 5754,
5779 PseudoVLUXSEG2EI32_V_M4_M1_MASK = 5755,
5780 PseudoVLUXSEG2EI32_V_M4_M2 = 5756,
5781 PseudoVLUXSEG2EI32_V_M4_M2_MASK = 5757,
5782 PseudoVLUXSEG2EI32_V_M4_M4 = 5758,
5783 PseudoVLUXSEG2EI32_V_M4_M4_MASK = 5759,
5784 PseudoVLUXSEG2EI32_V_M8_M2 = 5760,
5785 PseudoVLUXSEG2EI32_V_M8_M2_MASK = 5761,
5786 PseudoVLUXSEG2EI32_V_M8_M4 = 5762,
5787 PseudoVLUXSEG2EI32_V_M8_M4_MASK = 5763,
5788 PseudoVLUXSEG2EI32_V_MF2_M1 = 5764,
5789 PseudoVLUXSEG2EI32_V_MF2_M1_MASK = 5765,
5790 PseudoVLUXSEG2EI32_V_MF2_MF2 = 5766,
5791 PseudoVLUXSEG2EI32_V_MF2_MF2_MASK = 5767,
5792 PseudoVLUXSEG2EI32_V_MF2_MF4 = 5768,
5793 PseudoVLUXSEG2EI32_V_MF2_MF4_MASK = 5769,
5794 PseudoVLUXSEG2EI32_V_MF2_MF8 = 5770,
5795 PseudoVLUXSEG2EI32_V_MF2_MF8_MASK = 5771,
5796 PseudoVLUXSEG2EI64_V_M1_M1 = 5772,
5797 PseudoVLUXSEG2EI64_V_M1_M1_MASK = 5773,
5798 PseudoVLUXSEG2EI64_V_M1_MF2 = 5774,
5799 PseudoVLUXSEG2EI64_V_M1_MF2_MASK = 5775,
5800 PseudoVLUXSEG2EI64_V_M1_MF4 = 5776,
5801 PseudoVLUXSEG2EI64_V_M1_MF4_MASK = 5777,
5802 PseudoVLUXSEG2EI64_V_M1_MF8 = 5778,
5803 PseudoVLUXSEG2EI64_V_M1_MF8_MASK = 5779,
5804 PseudoVLUXSEG2EI64_V_M2_M1 = 5780,
5805 PseudoVLUXSEG2EI64_V_M2_M1_MASK = 5781,
5806 PseudoVLUXSEG2EI64_V_M2_M2 = 5782,
5807 PseudoVLUXSEG2EI64_V_M2_M2_MASK = 5783,
5808 PseudoVLUXSEG2EI64_V_M2_MF2 = 5784,
5809 PseudoVLUXSEG2EI64_V_M2_MF2_MASK = 5785,
5810 PseudoVLUXSEG2EI64_V_M2_MF4 = 5786,
5811 PseudoVLUXSEG2EI64_V_M2_MF4_MASK = 5787,
5812 PseudoVLUXSEG2EI64_V_M4_M1 = 5788,
5813 PseudoVLUXSEG2EI64_V_M4_M1_MASK = 5789,
5814 PseudoVLUXSEG2EI64_V_M4_M2 = 5790,
5815 PseudoVLUXSEG2EI64_V_M4_M2_MASK = 5791,
5816 PseudoVLUXSEG2EI64_V_M4_M4 = 5792,
5817 PseudoVLUXSEG2EI64_V_M4_M4_MASK = 5793,
5818 PseudoVLUXSEG2EI64_V_M4_MF2 = 5794,
5819 PseudoVLUXSEG2EI64_V_M4_MF2_MASK = 5795,
5820 PseudoVLUXSEG2EI64_V_M8_M1 = 5796,
5821 PseudoVLUXSEG2EI64_V_M8_M1_MASK = 5797,
5822 PseudoVLUXSEG2EI64_V_M8_M2 = 5798,
5823 PseudoVLUXSEG2EI64_V_M8_M2_MASK = 5799,
5824 PseudoVLUXSEG2EI64_V_M8_M4 = 5800,
5825 PseudoVLUXSEG2EI64_V_M8_M4_MASK = 5801,
5826 PseudoVLUXSEG2EI8_V_M1_M1 = 5802,
5827 PseudoVLUXSEG2EI8_V_M1_M1_MASK = 5803,
5828 PseudoVLUXSEG2EI8_V_M1_M2 = 5804,
5829 PseudoVLUXSEG2EI8_V_M1_M2_MASK = 5805,
5830 PseudoVLUXSEG2EI8_V_M1_M4 = 5806,
5831 PseudoVLUXSEG2EI8_V_M1_M4_MASK = 5807,
5832 PseudoVLUXSEG2EI8_V_M2_M2 = 5808,
5833 PseudoVLUXSEG2EI8_V_M2_M2_MASK = 5809,
5834 PseudoVLUXSEG2EI8_V_M2_M4 = 5810,
5835 PseudoVLUXSEG2EI8_V_M2_M4_MASK = 5811,
5836 PseudoVLUXSEG2EI8_V_M4_M4 = 5812,
5837 PseudoVLUXSEG2EI8_V_M4_M4_MASK = 5813,
5838 PseudoVLUXSEG2EI8_V_MF2_M1 = 5814,
5839 PseudoVLUXSEG2EI8_V_MF2_M1_MASK = 5815,
5840 PseudoVLUXSEG2EI8_V_MF2_M2 = 5816,
5841 PseudoVLUXSEG2EI8_V_MF2_M2_MASK = 5817,
5842 PseudoVLUXSEG2EI8_V_MF2_M4 = 5818,
5843 PseudoVLUXSEG2EI8_V_MF2_M4_MASK = 5819,
5844 PseudoVLUXSEG2EI8_V_MF2_MF2 = 5820,
5845 PseudoVLUXSEG2EI8_V_MF2_MF2_MASK = 5821,
5846 PseudoVLUXSEG2EI8_V_MF4_M1 = 5822,
5847 PseudoVLUXSEG2EI8_V_MF4_M1_MASK = 5823,
5848 PseudoVLUXSEG2EI8_V_MF4_M2 = 5824,
5849 PseudoVLUXSEG2EI8_V_MF4_M2_MASK = 5825,
5850 PseudoVLUXSEG2EI8_V_MF4_MF2 = 5826,
5851 PseudoVLUXSEG2EI8_V_MF4_MF2_MASK = 5827,
5852 PseudoVLUXSEG2EI8_V_MF4_MF4 = 5828,
5853 PseudoVLUXSEG2EI8_V_MF4_MF4_MASK = 5829,
5854 PseudoVLUXSEG2EI8_V_MF8_M1 = 5830,
5855 PseudoVLUXSEG2EI8_V_MF8_M1_MASK = 5831,
5856 PseudoVLUXSEG2EI8_V_MF8_MF2 = 5832,
5857 PseudoVLUXSEG2EI8_V_MF8_MF2_MASK = 5833,
5858 PseudoVLUXSEG2EI8_V_MF8_MF4 = 5834,
5859 PseudoVLUXSEG2EI8_V_MF8_MF4_MASK = 5835,
5860 PseudoVLUXSEG2EI8_V_MF8_MF8 = 5836,
5861 PseudoVLUXSEG2EI8_V_MF8_MF8_MASK = 5837,
5862 PseudoVLUXSEG3EI16_V_M1_M1 = 5838,
5863 PseudoVLUXSEG3EI16_V_M1_M1_MASK = 5839,
5864 PseudoVLUXSEG3EI16_V_M1_M2 = 5840,
5865 PseudoVLUXSEG3EI16_V_M1_M2_MASK = 5841,
5866 PseudoVLUXSEG3EI16_V_M1_MF2 = 5842,
5867 PseudoVLUXSEG3EI16_V_M1_MF2_MASK = 5843,
5868 PseudoVLUXSEG3EI16_V_M2_M1 = 5844,
5869 PseudoVLUXSEG3EI16_V_M2_M1_MASK = 5845,
5870 PseudoVLUXSEG3EI16_V_M2_M2 = 5846,
5871 PseudoVLUXSEG3EI16_V_M2_M2_MASK = 5847,
5872 PseudoVLUXSEG3EI16_V_M4_M2 = 5848,
5873 PseudoVLUXSEG3EI16_V_M4_M2_MASK = 5849,
5874 PseudoVLUXSEG3EI16_V_MF2_M1 = 5850,
5875 PseudoVLUXSEG3EI16_V_MF2_M1_MASK = 5851,
5876 PseudoVLUXSEG3EI16_V_MF2_M2 = 5852,
5877 PseudoVLUXSEG3EI16_V_MF2_M2_MASK = 5853,
5878 PseudoVLUXSEG3EI16_V_MF2_MF2 = 5854,
5879 PseudoVLUXSEG3EI16_V_MF2_MF2_MASK = 5855,
5880 PseudoVLUXSEG3EI16_V_MF2_MF4 = 5856,
5881 PseudoVLUXSEG3EI16_V_MF2_MF4_MASK = 5857,
5882 PseudoVLUXSEG3EI16_V_MF4_M1 = 5858,
5883 PseudoVLUXSEG3EI16_V_MF4_M1_MASK = 5859,
5884 PseudoVLUXSEG3EI16_V_MF4_MF2 = 5860,
5885 PseudoVLUXSEG3EI16_V_MF4_MF2_MASK = 5861,
5886 PseudoVLUXSEG3EI16_V_MF4_MF4 = 5862,
5887 PseudoVLUXSEG3EI16_V_MF4_MF4_MASK = 5863,
5888 PseudoVLUXSEG3EI16_V_MF4_MF8 = 5864,
5889 PseudoVLUXSEG3EI16_V_MF4_MF8_MASK = 5865,
5890 PseudoVLUXSEG3EI32_V_M1_M1 = 5866,
5891 PseudoVLUXSEG3EI32_V_M1_M1_MASK = 5867,
5892 PseudoVLUXSEG3EI32_V_M1_M2 = 5868,
5893 PseudoVLUXSEG3EI32_V_M1_M2_MASK = 5869,
5894 PseudoVLUXSEG3EI32_V_M1_MF2 = 5870,
5895 PseudoVLUXSEG3EI32_V_M1_MF2_MASK = 5871,
5896 PseudoVLUXSEG3EI32_V_M1_MF4 = 5872,
5897 PseudoVLUXSEG3EI32_V_M1_MF4_MASK = 5873,
5898 PseudoVLUXSEG3EI32_V_M2_M1 = 5874,
5899 PseudoVLUXSEG3EI32_V_M2_M1_MASK = 5875,
5900 PseudoVLUXSEG3EI32_V_M2_M2 = 5876,
5901 PseudoVLUXSEG3EI32_V_M2_M2_MASK = 5877,
5902 PseudoVLUXSEG3EI32_V_M2_MF2 = 5878,
5903 PseudoVLUXSEG3EI32_V_M2_MF2_MASK = 5879,
5904 PseudoVLUXSEG3EI32_V_M4_M1 = 5880,
5905 PseudoVLUXSEG3EI32_V_M4_M1_MASK = 5881,
5906 PseudoVLUXSEG3EI32_V_M4_M2 = 5882,
5907 PseudoVLUXSEG3EI32_V_M4_M2_MASK = 5883,
5908 PseudoVLUXSEG3EI32_V_M8_M2 = 5884,
5909 PseudoVLUXSEG3EI32_V_M8_M2_MASK = 5885,
5910 PseudoVLUXSEG3EI32_V_MF2_M1 = 5886,
5911 PseudoVLUXSEG3EI32_V_MF2_M1_MASK = 5887,
5912 PseudoVLUXSEG3EI32_V_MF2_MF2 = 5888,
5913 PseudoVLUXSEG3EI32_V_MF2_MF2_MASK = 5889,
5914 PseudoVLUXSEG3EI32_V_MF2_MF4 = 5890,
5915 PseudoVLUXSEG3EI32_V_MF2_MF4_MASK = 5891,
5916 PseudoVLUXSEG3EI32_V_MF2_MF8 = 5892,
5917 PseudoVLUXSEG3EI32_V_MF2_MF8_MASK = 5893,
5918 PseudoVLUXSEG3EI64_V_M1_M1 = 5894,
5919 PseudoVLUXSEG3EI64_V_M1_M1_MASK = 5895,
5920 PseudoVLUXSEG3EI64_V_M1_MF2 = 5896,
5921 PseudoVLUXSEG3EI64_V_M1_MF2_MASK = 5897,
5922 PseudoVLUXSEG3EI64_V_M1_MF4 = 5898,
5923 PseudoVLUXSEG3EI64_V_M1_MF4_MASK = 5899,
5924 PseudoVLUXSEG3EI64_V_M1_MF8 = 5900,
5925 PseudoVLUXSEG3EI64_V_M1_MF8_MASK = 5901,
5926 PseudoVLUXSEG3EI64_V_M2_M1 = 5902,
5927 PseudoVLUXSEG3EI64_V_M2_M1_MASK = 5903,
5928 PseudoVLUXSEG3EI64_V_M2_M2 = 5904,
5929 PseudoVLUXSEG3EI64_V_M2_M2_MASK = 5905,
5930 PseudoVLUXSEG3EI64_V_M2_MF2 = 5906,
5931 PseudoVLUXSEG3EI64_V_M2_MF2_MASK = 5907,
5932 PseudoVLUXSEG3EI64_V_M2_MF4 = 5908,
5933 PseudoVLUXSEG3EI64_V_M2_MF4_MASK = 5909,
5934 PseudoVLUXSEG3EI64_V_M4_M1 = 5910,
5935 PseudoVLUXSEG3EI64_V_M4_M1_MASK = 5911,
5936 PseudoVLUXSEG3EI64_V_M4_M2 = 5912,
5937 PseudoVLUXSEG3EI64_V_M4_M2_MASK = 5913,
5938 PseudoVLUXSEG3EI64_V_M4_MF2 = 5914,
5939 PseudoVLUXSEG3EI64_V_M4_MF2_MASK = 5915,
5940 PseudoVLUXSEG3EI64_V_M8_M1 = 5916,
5941 PseudoVLUXSEG3EI64_V_M8_M1_MASK = 5917,
5942 PseudoVLUXSEG3EI64_V_M8_M2 = 5918,
5943 PseudoVLUXSEG3EI64_V_M8_M2_MASK = 5919,
5944 PseudoVLUXSEG3EI8_V_M1_M1 = 5920,
5945 PseudoVLUXSEG3EI8_V_M1_M1_MASK = 5921,
5946 PseudoVLUXSEG3EI8_V_M1_M2 = 5922,
5947 PseudoVLUXSEG3EI8_V_M1_M2_MASK = 5923,
5948 PseudoVLUXSEG3EI8_V_M2_M2 = 5924,
5949 PseudoVLUXSEG3EI8_V_M2_M2_MASK = 5925,
5950 PseudoVLUXSEG3EI8_V_MF2_M1 = 5926,
5951 PseudoVLUXSEG3EI8_V_MF2_M1_MASK = 5927,
5952 PseudoVLUXSEG3EI8_V_MF2_M2 = 5928,
5953 PseudoVLUXSEG3EI8_V_MF2_M2_MASK = 5929,
5954 PseudoVLUXSEG3EI8_V_MF2_MF2 = 5930,
5955 PseudoVLUXSEG3EI8_V_MF2_MF2_MASK = 5931,
5956 PseudoVLUXSEG3EI8_V_MF4_M1 = 5932,
5957 PseudoVLUXSEG3EI8_V_MF4_M1_MASK = 5933,
5958 PseudoVLUXSEG3EI8_V_MF4_M2 = 5934,
5959 PseudoVLUXSEG3EI8_V_MF4_M2_MASK = 5935,
5960 PseudoVLUXSEG3EI8_V_MF4_MF2 = 5936,
5961 PseudoVLUXSEG3EI8_V_MF4_MF2_MASK = 5937,
5962 PseudoVLUXSEG3EI8_V_MF4_MF4 = 5938,
5963 PseudoVLUXSEG3EI8_V_MF4_MF4_MASK = 5939,
5964 PseudoVLUXSEG3EI8_V_MF8_M1 = 5940,
5965 PseudoVLUXSEG3EI8_V_MF8_M1_MASK = 5941,
5966 PseudoVLUXSEG3EI8_V_MF8_MF2 = 5942,
5967 PseudoVLUXSEG3EI8_V_MF8_MF2_MASK = 5943,
5968 PseudoVLUXSEG3EI8_V_MF8_MF4 = 5944,
5969 PseudoVLUXSEG3EI8_V_MF8_MF4_MASK = 5945,
5970 PseudoVLUXSEG3EI8_V_MF8_MF8 = 5946,
5971 PseudoVLUXSEG3EI8_V_MF8_MF8_MASK = 5947,
5972 PseudoVLUXSEG4EI16_V_M1_M1 = 5948,
5973 PseudoVLUXSEG4EI16_V_M1_M1_MASK = 5949,
5974 PseudoVLUXSEG4EI16_V_M1_M2 = 5950,
5975 PseudoVLUXSEG4EI16_V_M1_M2_MASK = 5951,
5976 PseudoVLUXSEG4EI16_V_M1_MF2 = 5952,
5977 PseudoVLUXSEG4EI16_V_M1_MF2_MASK = 5953,
5978 PseudoVLUXSEG4EI16_V_M2_M1 = 5954,
5979 PseudoVLUXSEG4EI16_V_M2_M1_MASK = 5955,
5980 PseudoVLUXSEG4EI16_V_M2_M2 = 5956,
5981 PseudoVLUXSEG4EI16_V_M2_M2_MASK = 5957,
5982 PseudoVLUXSEG4EI16_V_M4_M2 = 5958,
5983 PseudoVLUXSEG4EI16_V_M4_M2_MASK = 5959,
5984 PseudoVLUXSEG4EI16_V_MF2_M1 = 5960,
5985 PseudoVLUXSEG4EI16_V_MF2_M1_MASK = 5961,
5986 PseudoVLUXSEG4EI16_V_MF2_M2 = 5962,
5987 PseudoVLUXSEG4EI16_V_MF2_M2_MASK = 5963,
5988 PseudoVLUXSEG4EI16_V_MF2_MF2 = 5964,
5989 PseudoVLUXSEG4EI16_V_MF2_MF2_MASK = 5965,
5990 PseudoVLUXSEG4EI16_V_MF2_MF4 = 5966,
5991 PseudoVLUXSEG4EI16_V_MF2_MF4_MASK = 5967,
5992 PseudoVLUXSEG4EI16_V_MF4_M1 = 5968,
5993 PseudoVLUXSEG4EI16_V_MF4_M1_MASK = 5969,
5994 PseudoVLUXSEG4EI16_V_MF4_MF2 = 5970,
5995 PseudoVLUXSEG4EI16_V_MF4_MF2_MASK = 5971,
5996 PseudoVLUXSEG4EI16_V_MF4_MF4 = 5972,
5997 PseudoVLUXSEG4EI16_V_MF4_MF4_MASK = 5973,
5998 PseudoVLUXSEG4EI16_V_MF4_MF8 = 5974,
5999 PseudoVLUXSEG4EI16_V_MF4_MF8_MASK = 5975,
6000 PseudoVLUXSEG4EI32_V_M1_M1 = 5976,
6001 PseudoVLUXSEG4EI32_V_M1_M1_MASK = 5977,
6002 PseudoVLUXSEG4EI32_V_M1_M2 = 5978,
6003 PseudoVLUXSEG4EI32_V_M1_M2_MASK = 5979,
6004 PseudoVLUXSEG4EI32_V_M1_MF2 = 5980,
6005 PseudoVLUXSEG4EI32_V_M1_MF2_MASK = 5981,
6006 PseudoVLUXSEG4EI32_V_M1_MF4 = 5982,
6007 PseudoVLUXSEG4EI32_V_M1_MF4_MASK = 5983,
6008 PseudoVLUXSEG4EI32_V_M2_M1 = 5984,
6009 PseudoVLUXSEG4EI32_V_M2_M1_MASK = 5985,
6010 PseudoVLUXSEG4EI32_V_M2_M2 = 5986,
6011 PseudoVLUXSEG4EI32_V_M2_M2_MASK = 5987,
6012 PseudoVLUXSEG4EI32_V_M2_MF2 = 5988,
6013 PseudoVLUXSEG4EI32_V_M2_MF2_MASK = 5989,
6014 PseudoVLUXSEG4EI32_V_M4_M1 = 5990,
6015 PseudoVLUXSEG4EI32_V_M4_M1_MASK = 5991,
6016 PseudoVLUXSEG4EI32_V_M4_M2 = 5992,
6017 PseudoVLUXSEG4EI32_V_M4_M2_MASK = 5993,
6018 PseudoVLUXSEG4EI32_V_M8_M2 = 5994,
6019 PseudoVLUXSEG4EI32_V_M8_M2_MASK = 5995,
6020 PseudoVLUXSEG4EI32_V_MF2_M1 = 5996,
6021 PseudoVLUXSEG4EI32_V_MF2_M1_MASK = 5997,
6022 PseudoVLUXSEG4EI32_V_MF2_MF2 = 5998,
6023 PseudoVLUXSEG4EI32_V_MF2_MF2_MASK = 5999,
6024 PseudoVLUXSEG4EI32_V_MF2_MF4 = 6000,
6025 PseudoVLUXSEG4EI32_V_MF2_MF4_MASK = 6001,
6026 PseudoVLUXSEG4EI32_V_MF2_MF8 = 6002,
6027 PseudoVLUXSEG4EI32_V_MF2_MF8_MASK = 6003,
6028 PseudoVLUXSEG4EI64_V_M1_M1 = 6004,
6029 PseudoVLUXSEG4EI64_V_M1_M1_MASK = 6005,
6030 PseudoVLUXSEG4EI64_V_M1_MF2 = 6006,
6031 PseudoVLUXSEG4EI64_V_M1_MF2_MASK = 6007,
6032 PseudoVLUXSEG4EI64_V_M1_MF4 = 6008,
6033 PseudoVLUXSEG4EI64_V_M1_MF4_MASK = 6009,
6034 PseudoVLUXSEG4EI64_V_M1_MF8 = 6010,
6035 PseudoVLUXSEG4EI64_V_M1_MF8_MASK = 6011,
6036 PseudoVLUXSEG4EI64_V_M2_M1 = 6012,
6037 PseudoVLUXSEG4EI64_V_M2_M1_MASK = 6013,
6038 PseudoVLUXSEG4EI64_V_M2_M2 = 6014,
6039 PseudoVLUXSEG4EI64_V_M2_M2_MASK = 6015,
6040 PseudoVLUXSEG4EI64_V_M2_MF2 = 6016,
6041 PseudoVLUXSEG4EI64_V_M2_MF2_MASK = 6017,
6042 PseudoVLUXSEG4EI64_V_M2_MF4 = 6018,
6043 PseudoVLUXSEG4EI64_V_M2_MF4_MASK = 6019,
6044 PseudoVLUXSEG4EI64_V_M4_M1 = 6020,
6045 PseudoVLUXSEG4EI64_V_M4_M1_MASK = 6021,
6046 PseudoVLUXSEG4EI64_V_M4_M2 = 6022,
6047 PseudoVLUXSEG4EI64_V_M4_M2_MASK = 6023,
6048 PseudoVLUXSEG4EI64_V_M4_MF2 = 6024,
6049 PseudoVLUXSEG4EI64_V_M4_MF2_MASK = 6025,
6050 PseudoVLUXSEG4EI64_V_M8_M1 = 6026,
6051 PseudoVLUXSEG4EI64_V_M8_M1_MASK = 6027,
6052 PseudoVLUXSEG4EI64_V_M8_M2 = 6028,
6053 PseudoVLUXSEG4EI64_V_M8_M2_MASK = 6029,
6054 PseudoVLUXSEG4EI8_V_M1_M1 = 6030,
6055 PseudoVLUXSEG4EI8_V_M1_M1_MASK = 6031,
6056 PseudoVLUXSEG4EI8_V_M1_M2 = 6032,
6057 PseudoVLUXSEG4EI8_V_M1_M2_MASK = 6033,
6058 PseudoVLUXSEG4EI8_V_M2_M2 = 6034,
6059 PseudoVLUXSEG4EI8_V_M2_M2_MASK = 6035,
6060 PseudoVLUXSEG4EI8_V_MF2_M1 = 6036,
6061 PseudoVLUXSEG4EI8_V_MF2_M1_MASK = 6037,
6062 PseudoVLUXSEG4EI8_V_MF2_M2 = 6038,
6063 PseudoVLUXSEG4EI8_V_MF2_M2_MASK = 6039,
6064 PseudoVLUXSEG4EI8_V_MF2_MF2 = 6040,
6065 PseudoVLUXSEG4EI8_V_MF2_MF2_MASK = 6041,
6066 PseudoVLUXSEG4EI8_V_MF4_M1 = 6042,
6067 PseudoVLUXSEG4EI8_V_MF4_M1_MASK = 6043,
6068 PseudoVLUXSEG4EI8_V_MF4_M2 = 6044,
6069 PseudoVLUXSEG4EI8_V_MF4_M2_MASK = 6045,
6070 PseudoVLUXSEG4EI8_V_MF4_MF2 = 6046,
6071 PseudoVLUXSEG4EI8_V_MF4_MF2_MASK = 6047,
6072 PseudoVLUXSEG4EI8_V_MF4_MF4 = 6048,
6073 PseudoVLUXSEG4EI8_V_MF4_MF4_MASK = 6049,
6074 PseudoVLUXSEG4EI8_V_MF8_M1 = 6050,
6075 PseudoVLUXSEG4EI8_V_MF8_M1_MASK = 6051,
6076 PseudoVLUXSEG4EI8_V_MF8_MF2 = 6052,
6077 PseudoVLUXSEG4EI8_V_MF8_MF2_MASK = 6053,
6078 PseudoVLUXSEG4EI8_V_MF8_MF4 = 6054,
6079 PseudoVLUXSEG4EI8_V_MF8_MF4_MASK = 6055,
6080 PseudoVLUXSEG4EI8_V_MF8_MF8 = 6056,
6081 PseudoVLUXSEG4EI8_V_MF8_MF8_MASK = 6057,
6082 PseudoVLUXSEG5EI16_V_M1_M1 = 6058,
6083 PseudoVLUXSEG5EI16_V_M1_M1_MASK = 6059,
6084 PseudoVLUXSEG5EI16_V_M1_MF2 = 6060,
6085 PseudoVLUXSEG5EI16_V_M1_MF2_MASK = 6061,
6086 PseudoVLUXSEG5EI16_V_M2_M1 = 6062,
6087 PseudoVLUXSEG5EI16_V_M2_M1_MASK = 6063,
6088 PseudoVLUXSEG5EI16_V_MF2_M1 = 6064,
6089 PseudoVLUXSEG5EI16_V_MF2_M1_MASK = 6065,
6090 PseudoVLUXSEG5EI16_V_MF2_MF2 = 6066,
6091 PseudoVLUXSEG5EI16_V_MF2_MF2_MASK = 6067,
6092 PseudoVLUXSEG5EI16_V_MF2_MF4 = 6068,
6093 PseudoVLUXSEG5EI16_V_MF2_MF4_MASK = 6069,
6094 PseudoVLUXSEG5EI16_V_MF4_M1 = 6070,
6095 PseudoVLUXSEG5EI16_V_MF4_M1_MASK = 6071,
6096 PseudoVLUXSEG5EI16_V_MF4_MF2 = 6072,
6097 PseudoVLUXSEG5EI16_V_MF4_MF2_MASK = 6073,
6098 PseudoVLUXSEG5EI16_V_MF4_MF4 = 6074,
6099 PseudoVLUXSEG5EI16_V_MF4_MF4_MASK = 6075,
6100 PseudoVLUXSEG5EI16_V_MF4_MF8 = 6076,
6101 PseudoVLUXSEG5EI16_V_MF4_MF8_MASK = 6077,
6102 PseudoVLUXSEG5EI32_V_M1_M1 = 6078,
6103 PseudoVLUXSEG5EI32_V_M1_M1_MASK = 6079,
6104 PseudoVLUXSEG5EI32_V_M1_MF2 = 6080,
6105 PseudoVLUXSEG5EI32_V_M1_MF2_MASK = 6081,
6106 PseudoVLUXSEG5EI32_V_M1_MF4 = 6082,
6107 PseudoVLUXSEG5EI32_V_M1_MF4_MASK = 6083,
6108 PseudoVLUXSEG5EI32_V_M2_M1 = 6084,
6109 PseudoVLUXSEG5EI32_V_M2_M1_MASK = 6085,
6110 PseudoVLUXSEG5EI32_V_M2_MF2 = 6086,
6111 PseudoVLUXSEG5EI32_V_M2_MF2_MASK = 6087,
6112 PseudoVLUXSEG5EI32_V_M4_M1 = 6088,
6113 PseudoVLUXSEG5EI32_V_M4_M1_MASK = 6089,
6114 PseudoVLUXSEG5EI32_V_MF2_M1 = 6090,
6115 PseudoVLUXSEG5EI32_V_MF2_M1_MASK = 6091,
6116 PseudoVLUXSEG5EI32_V_MF2_MF2 = 6092,
6117 PseudoVLUXSEG5EI32_V_MF2_MF2_MASK = 6093,
6118 PseudoVLUXSEG5EI32_V_MF2_MF4 = 6094,
6119 PseudoVLUXSEG5EI32_V_MF2_MF4_MASK = 6095,
6120 PseudoVLUXSEG5EI32_V_MF2_MF8 = 6096,
6121 PseudoVLUXSEG5EI32_V_MF2_MF8_MASK = 6097,
6122 PseudoVLUXSEG5EI64_V_M1_M1 = 6098,
6123 PseudoVLUXSEG5EI64_V_M1_M1_MASK = 6099,
6124 PseudoVLUXSEG5EI64_V_M1_MF2 = 6100,
6125 PseudoVLUXSEG5EI64_V_M1_MF2_MASK = 6101,
6126 PseudoVLUXSEG5EI64_V_M1_MF4 = 6102,
6127 PseudoVLUXSEG5EI64_V_M1_MF4_MASK = 6103,
6128 PseudoVLUXSEG5EI64_V_M1_MF8 = 6104,
6129 PseudoVLUXSEG5EI64_V_M1_MF8_MASK = 6105,
6130 PseudoVLUXSEG5EI64_V_M2_M1 = 6106,
6131 PseudoVLUXSEG5EI64_V_M2_M1_MASK = 6107,
6132 PseudoVLUXSEG5EI64_V_M2_MF2 = 6108,
6133 PseudoVLUXSEG5EI64_V_M2_MF2_MASK = 6109,
6134 PseudoVLUXSEG5EI64_V_M2_MF4 = 6110,
6135 PseudoVLUXSEG5EI64_V_M2_MF4_MASK = 6111,
6136 PseudoVLUXSEG5EI64_V_M4_M1 = 6112,
6137 PseudoVLUXSEG5EI64_V_M4_M1_MASK = 6113,
6138 PseudoVLUXSEG5EI64_V_M4_MF2 = 6114,
6139 PseudoVLUXSEG5EI64_V_M4_MF2_MASK = 6115,
6140 PseudoVLUXSEG5EI64_V_M8_M1 = 6116,
6141 PseudoVLUXSEG5EI64_V_M8_M1_MASK = 6117,
6142 PseudoVLUXSEG5EI8_V_M1_M1 = 6118,
6143 PseudoVLUXSEG5EI8_V_M1_M1_MASK = 6119,
6144 PseudoVLUXSEG5EI8_V_MF2_M1 = 6120,
6145 PseudoVLUXSEG5EI8_V_MF2_M1_MASK = 6121,
6146 PseudoVLUXSEG5EI8_V_MF2_MF2 = 6122,
6147 PseudoVLUXSEG5EI8_V_MF2_MF2_MASK = 6123,
6148 PseudoVLUXSEG5EI8_V_MF4_M1 = 6124,
6149 PseudoVLUXSEG5EI8_V_MF4_M1_MASK = 6125,
6150 PseudoVLUXSEG5EI8_V_MF4_MF2 = 6126,
6151 PseudoVLUXSEG5EI8_V_MF4_MF2_MASK = 6127,
6152 PseudoVLUXSEG5EI8_V_MF4_MF4 = 6128,
6153 PseudoVLUXSEG5EI8_V_MF4_MF4_MASK = 6129,
6154 PseudoVLUXSEG5EI8_V_MF8_M1 = 6130,
6155 PseudoVLUXSEG5EI8_V_MF8_M1_MASK = 6131,
6156 PseudoVLUXSEG5EI8_V_MF8_MF2 = 6132,
6157 PseudoVLUXSEG5EI8_V_MF8_MF2_MASK = 6133,
6158 PseudoVLUXSEG5EI8_V_MF8_MF4 = 6134,
6159 PseudoVLUXSEG5EI8_V_MF8_MF4_MASK = 6135,
6160 PseudoVLUXSEG5EI8_V_MF8_MF8 = 6136,
6161 PseudoVLUXSEG5EI8_V_MF8_MF8_MASK = 6137,
6162 PseudoVLUXSEG6EI16_V_M1_M1 = 6138,
6163 PseudoVLUXSEG6EI16_V_M1_M1_MASK = 6139,
6164 PseudoVLUXSEG6EI16_V_M1_MF2 = 6140,
6165 PseudoVLUXSEG6EI16_V_M1_MF2_MASK = 6141,
6166 PseudoVLUXSEG6EI16_V_M2_M1 = 6142,
6167 PseudoVLUXSEG6EI16_V_M2_M1_MASK = 6143,
6168 PseudoVLUXSEG6EI16_V_MF2_M1 = 6144,
6169 PseudoVLUXSEG6EI16_V_MF2_M1_MASK = 6145,
6170 PseudoVLUXSEG6EI16_V_MF2_MF2 = 6146,
6171 PseudoVLUXSEG6EI16_V_MF2_MF2_MASK = 6147,
6172 PseudoVLUXSEG6EI16_V_MF2_MF4 = 6148,
6173 PseudoVLUXSEG6EI16_V_MF2_MF4_MASK = 6149,
6174 PseudoVLUXSEG6EI16_V_MF4_M1 = 6150,
6175 PseudoVLUXSEG6EI16_V_MF4_M1_MASK = 6151,
6176 PseudoVLUXSEG6EI16_V_MF4_MF2 = 6152,
6177 PseudoVLUXSEG6EI16_V_MF4_MF2_MASK = 6153,
6178 PseudoVLUXSEG6EI16_V_MF4_MF4 = 6154,
6179 PseudoVLUXSEG6EI16_V_MF4_MF4_MASK = 6155,
6180 PseudoVLUXSEG6EI16_V_MF4_MF8 = 6156,
6181 PseudoVLUXSEG6EI16_V_MF4_MF8_MASK = 6157,
6182 PseudoVLUXSEG6EI32_V_M1_M1 = 6158,
6183 PseudoVLUXSEG6EI32_V_M1_M1_MASK = 6159,
6184 PseudoVLUXSEG6EI32_V_M1_MF2 = 6160,
6185 PseudoVLUXSEG6EI32_V_M1_MF2_MASK = 6161,
6186 PseudoVLUXSEG6EI32_V_M1_MF4 = 6162,
6187 PseudoVLUXSEG6EI32_V_M1_MF4_MASK = 6163,
6188 PseudoVLUXSEG6EI32_V_M2_M1 = 6164,
6189 PseudoVLUXSEG6EI32_V_M2_M1_MASK = 6165,
6190 PseudoVLUXSEG6EI32_V_M2_MF2 = 6166,
6191 PseudoVLUXSEG6EI32_V_M2_MF2_MASK = 6167,
6192 PseudoVLUXSEG6EI32_V_M4_M1 = 6168,
6193 PseudoVLUXSEG6EI32_V_M4_M1_MASK = 6169,
6194 PseudoVLUXSEG6EI32_V_MF2_M1 = 6170,
6195 PseudoVLUXSEG6EI32_V_MF2_M1_MASK = 6171,
6196 PseudoVLUXSEG6EI32_V_MF2_MF2 = 6172,
6197 PseudoVLUXSEG6EI32_V_MF2_MF2_MASK = 6173,
6198 PseudoVLUXSEG6EI32_V_MF2_MF4 = 6174,
6199 PseudoVLUXSEG6EI32_V_MF2_MF4_MASK = 6175,
6200 PseudoVLUXSEG6EI32_V_MF2_MF8 = 6176,
6201 PseudoVLUXSEG6EI32_V_MF2_MF8_MASK = 6177,
6202 PseudoVLUXSEG6EI64_V_M1_M1 = 6178,
6203 PseudoVLUXSEG6EI64_V_M1_M1_MASK = 6179,
6204 PseudoVLUXSEG6EI64_V_M1_MF2 = 6180,
6205 PseudoVLUXSEG6EI64_V_M1_MF2_MASK = 6181,
6206 PseudoVLUXSEG6EI64_V_M1_MF4 = 6182,
6207 PseudoVLUXSEG6EI64_V_M1_MF4_MASK = 6183,
6208 PseudoVLUXSEG6EI64_V_M1_MF8 = 6184,
6209 PseudoVLUXSEG6EI64_V_M1_MF8_MASK = 6185,
6210 PseudoVLUXSEG6EI64_V_M2_M1 = 6186,
6211 PseudoVLUXSEG6EI64_V_M2_M1_MASK = 6187,
6212 PseudoVLUXSEG6EI64_V_M2_MF2 = 6188,
6213 PseudoVLUXSEG6EI64_V_M2_MF2_MASK = 6189,
6214 PseudoVLUXSEG6EI64_V_M2_MF4 = 6190,
6215 PseudoVLUXSEG6EI64_V_M2_MF4_MASK = 6191,
6216 PseudoVLUXSEG6EI64_V_M4_M1 = 6192,
6217 PseudoVLUXSEG6EI64_V_M4_M1_MASK = 6193,
6218 PseudoVLUXSEG6EI64_V_M4_MF2 = 6194,
6219 PseudoVLUXSEG6EI64_V_M4_MF2_MASK = 6195,
6220 PseudoVLUXSEG6EI64_V_M8_M1 = 6196,
6221 PseudoVLUXSEG6EI64_V_M8_M1_MASK = 6197,
6222 PseudoVLUXSEG6EI8_V_M1_M1 = 6198,
6223 PseudoVLUXSEG6EI8_V_M1_M1_MASK = 6199,
6224 PseudoVLUXSEG6EI8_V_MF2_M1 = 6200,
6225 PseudoVLUXSEG6EI8_V_MF2_M1_MASK = 6201,
6226 PseudoVLUXSEG6EI8_V_MF2_MF2 = 6202,
6227 PseudoVLUXSEG6EI8_V_MF2_MF2_MASK = 6203,
6228 PseudoVLUXSEG6EI8_V_MF4_M1 = 6204,
6229 PseudoVLUXSEG6EI8_V_MF4_M1_MASK = 6205,
6230 PseudoVLUXSEG6EI8_V_MF4_MF2 = 6206,
6231 PseudoVLUXSEG6EI8_V_MF4_MF2_MASK = 6207,
6232 PseudoVLUXSEG6EI8_V_MF4_MF4 = 6208,
6233 PseudoVLUXSEG6EI8_V_MF4_MF4_MASK = 6209,
6234 PseudoVLUXSEG6EI8_V_MF8_M1 = 6210,
6235 PseudoVLUXSEG6EI8_V_MF8_M1_MASK = 6211,
6236 PseudoVLUXSEG6EI8_V_MF8_MF2 = 6212,
6237 PseudoVLUXSEG6EI8_V_MF8_MF2_MASK = 6213,
6238 PseudoVLUXSEG6EI8_V_MF8_MF4 = 6214,
6239 PseudoVLUXSEG6EI8_V_MF8_MF4_MASK = 6215,
6240 PseudoVLUXSEG6EI8_V_MF8_MF8 = 6216,
6241 PseudoVLUXSEG6EI8_V_MF8_MF8_MASK = 6217,
6242 PseudoVLUXSEG7EI16_V_M1_M1 = 6218,
6243 PseudoVLUXSEG7EI16_V_M1_M1_MASK = 6219,
6244 PseudoVLUXSEG7EI16_V_M1_MF2 = 6220,
6245 PseudoVLUXSEG7EI16_V_M1_MF2_MASK = 6221,
6246 PseudoVLUXSEG7EI16_V_M2_M1 = 6222,
6247 PseudoVLUXSEG7EI16_V_M2_M1_MASK = 6223,
6248 PseudoVLUXSEG7EI16_V_MF2_M1 = 6224,
6249 PseudoVLUXSEG7EI16_V_MF2_M1_MASK = 6225,
6250 PseudoVLUXSEG7EI16_V_MF2_MF2 = 6226,
6251 PseudoVLUXSEG7EI16_V_MF2_MF2_MASK = 6227,
6252 PseudoVLUXSEG7EI16_V_MF2_MF4 = 6228,
6253 PseudoVLUXSEG7EI16_V_MF2_MF4_MASK = 6229,
6254 PseudoVLUXSEG7EI16_V_MF4_M1 = 6230,
6255 PseudoVLUXSEG7EI16_V_MF4_M1_MASK = 6231,
6256 PseudoVLUXSEG7EI16_V_MF4_MF2 = 6232,
6257 PseudoVLUXSEG7EI16_V_MF4_MF2_MASK = 6233,
6258 PseudoVLUXSEG7EI16_V_MF4_MF4 = 6234,
6259 PseudoVLUXSEG7EI16_V_MF4_MF4_MASK = 6235,
6260 PseudoVLUXSEG7EI16_V_MF4_MF8 = 6236,
6261 PseudoVLUXSEG7EI16_V_MF4_MF8_MASK = 6237,
6262 PseudoVLUXSEG7EI32_V_M1_M1 = 6238,
6263 PseudoVLUXSEG7EI32_V_M1_M1_MASK = 6239,
6264 PseudoVLUXSEG7EI32_V_M1_MF2 = 6240,
6265 PseudoVLUXSEG7EI32_V_M1_MF2_MASK = 6241,
6266 PseudoVLUXSEG7EI32_V_M1_MF4 = 6242,
6267 PseudoVLUXSEG7EI32_V_M1_MF4_MASK = 6243,
6268 PseudoVLUXSEG7EI32_V_M2_M1 = 6244,
6269 PseudoVLUXSEG7EI32_V_M2_M1_MASK = 6245,
6270 PseudoVLUXSEG7EI32_V_M2_MF2 = 6246,
6271 PseudoVLUXSEG7EI32_V_M2_MF2_MASK = 6247,
6272 PseudoVLUXSEG7EI32_V_M4_M1 = 6248,
6273 PseudoVLUXSEG7EI32_V_M4_M1_MASK = 6249,
6274 PseudoVLUXSEG7EI32_V_MF2_M1 = 6250,
6275 PseudoVLUXSEG7EI32_V_MF2_M1_MASK = 6251,
6276 PseudoVLUXSEG7EI32_V_MF2_MF2 = 6252,
6277 PseudoVLUXSEG7EI32_V_MF2_MF2_MASK = 6253,
6278 PseudoVLUXSEG7EI32_V_MF2_MF4 = 6254,
6279 PseudoVLUXSEG7EI32_V_MF2_MF4_MASK = 6255,
6280 PseudoVLUXSEG7EI32_V_MF2_MF8 = 6256,
6281 PseudoVLUXSEG7EI32_V_MF2_MF8_MASK = 6257,
6282 PseudoVLUXSEG7EI64_V_M1_M1 = 6258,
6283 PseudoVLUXSEG7EI64_V_M1_M1_MASK = 6259,
6284 PseudoVLUXSEG7EI64_V_M1_MF2 = 6260,
6285 PseudoVLUXSEG7EI64_V_M1_MF2_MASK = 6261,
6286 PseudoVLUXSEG7EI64_V_M1_MF4 = 6262,
6287 PseudoVLUXSEG7EI64_V_M1_MF4_MASK = 6263,
6288 PseudoVLUXSEG7EI64_V_M1_MF8 = 6264,
6289 PseudoVLUXSEG7EI64_V_M1_MF8_MASK = 6265,
6290 PseudoVLUXSEG7EI64_V_M2_M1 = 6266,
6291 PseudoVLUXSEG7EI64_V_M2_M1_MASK = 6267,
6292 PseudoVLUXSEG7EI64_V_M2_MF2 = 6268,
6293 PseudoVLUXSEG7EI64_V_M2_MF2_MASK = 6269,
6294 PseudoVLUXSEG7EI64_V_M2_MF4 = 6270,
6295 PseudoVLUXSEG7EI64_V_M2_MF4_MASK = 6271,
6296 PseudoVLUXSEG7EI64_V_M4_M1 = 6272,
6297 PseudoVLUXSEG7EI64_V_M4_M1_MASK = 6273,
6298 PseudoVLUXSEG7EI64_V_M4_MF2 = 6274,
6299 PseudoVLUXSEG7EI64_V_M4_MF2_MASK = 6275,
6300 PseudoVLUXSEG7EI64_V_M8_M1 = 6276,
6301 PseudoVLUXSEG7EI64_V_M8_M1_MASK = 6277,
6302 PseudoVLUXSEG7EI8_V_M1_M1 = 6278,
6303 PseudoVLUXSEG7EI8_V_M1_M1_MASK = 6279,
6304 PseudoVLUXSEG7EI8_V_MF2_M1 = 6280,
6305 PseudoVLUXSEG7EI8_V_MF2_M1_MASK = 6281,
6306 PseudoVLUXSEG7EI8_V_MF2_MF2 = 6282,
6307 PseudoVLUXSEG7EI8_V_MF2_MF2_MASK = 6283,
6308 PseudoVLUXSEG7EI8_V_MF4_M1 = 6284,
6309 PseudoVLUXSEG7EI8_V_MF4_M1_MASK = 6285,
6310 PseudoVLUXSEG7EI8_V_MF4_MF2 = 6286,
6311 PseudoVLUXSEG7EI8_V_MF4_MF2_MASK = 6287,
6312 PseudoVLUXSEG7EI8_V_MF4_MF4 = 6288,
6313 PseudoVLUXSEG7EI8_V_MF4_MF4_MASK = 6289,
6314 PseudoVLUXSEG7EI8_V_MF8_M1 = 6290,
6315 PseudoVLUXSEG7EI8_V_MF8_M1_MASK = 6291,
6316 PseudoVLUXSEG7EI8_V_MF8_MF2 = 6292,
6317 PseudoVLUXSEG7EI8_V_MF8_MF2_MASK = 6293,
6318 PseudoVLUXSEG7EI8_V_MF8_MF4 = 6294,
6319 PseudoVLUXSEG7EI8_V_MF8_MF4_MASK = 6295,
6320 PseudoVLUXSEG7EI8_V_MF8_MF8 = 6296,
6321 PseudoVLUXSEG7EI8_V_MF8_MF8_MASK = 6297,
6322 PseudoVLUXSEG8EI16_V_M1_M1 = 6298,
6323 PseudoVLUXSEG8EI16_V_M1_M1_MASK = 6299,
6324 PseudoVLUXSEG8EI16_V_M1_MF2 = 6300,
6325 PseudoVLUXSEG8EI16_V_M1_MF2_MASK = 6301,
6326 PseudoVLUXSEG8EI16_V_M2_M1 = 6302,
6327 PseudoVLUXSEG8EI16_V_M2_M1_MASK = 6303,
6328 PseudoVLUXSEG8EI16_V_MF2_M1 = 6304,
6329 PseudoVLUXSEG8EI16_V_MF2_M1_MASK = 6305,
6330 PseudoVLUXSEG8EI16_V_MF2_MF2 = 6306,
6331 PseudoVLUXSEG8EI16_V_MF2_MF2_MASK = 6307,
6332 PseudoVLUXSEG8EI16_V_MF2_MF4 = 6308,
6333 PseudoVLUXSEG8EI16_V_MF2_MF4_MASK = 6309,
6334 PseudoVLUXSEG8EI16_V_MF4_M1 = 6310,
6335 PseudoVLUXSEG8EI16_V_MF4_M1_MASK = 6311,
6336 PseudoVLUXSEG8EI16_V_MF4_MF2 = 6312,
6337 PseudoVLUXSEG8EI16_V_MF4_MF2_MASK = 6313,
6338 PseudoVLUXSEG8EI16_V_MF4_MF4 = 6314,
6339 PseudoVLUXSEG8EI16_V_MF4_MF4_MASK = 6315,
6340 PseudoVLUXSEG8EI16_V_MF4_MF8 = 6316,
6341 PseudoVLUXSEG8EI16_V_MF4_MF8_MASK = 6317,
6342 PseudoVLUXSEG8EI32_V_M1_M1 = 6318,
6343 PseudoVLUXSEG8EI32_V_M1_M1_MASK = 6319,
6344 PseudoVLUXSEG8EI32_V_M1_MF2 = 6320,
6345 PseudoVLUXSEG8EI32_V_M1_MF2_MASK = 6321,
6346 PseudoVLUXSEG8EI32_V_M1_MF4 = 6322,
6347 PseudoVLUXSEG8EI32_V_M1_MF4_MASK = 6323,
6348 PseudoVLUXSEG8EI32_V_M2_M1 = 6324,
6349 PseudoVLUXSEG8EI32_V_M2_M1_MASK = 6325,
6350 PseudoVLUXSEG8EI32_V_M2_MF2 = 6326,
6351 PseudoVLUXSEG8EI32_V_M2_MF2_MASK = 6327,
6352 PseudoVLUXSEG8EI32_V_M4_M1 = 6328,
6353 PseudoVLUXSEG8EI32_V_M4_M1_MASK = 6329,
6354 PseudoVLUXSEG8EI32_V_MF2_M1 = 6330,
6355 PseudoVLUXSEG8EI32_V_MF2_M1_MASK = 6331,
6356 PseudoVLUXSEG8EI32_V_MF2_MF2 = 6332,
6357 PseudoVLUXSEG8EI32_V_MF2_MF2_MASK = 6333,
6358 PseudoVLUXSEG8EI32_V_MF2_MF4 = 6334,
6359 PseudoVLUXSEG8EI32_V_MF2_MF4_MASK = 6335,
6360 PseudoVLUXSEG8EI32_V_MF2_MF8 = 6336,
6361 PseudoVLUXSEG8EI32_V_MF2_MF8_MASK = 6337,
6362 PseudoVLUXSEG8EI64_V_M1_M1 = 6338,
6363 PseudoVLUXSEG8EI64_V_M1_M1_MASK = 6339,
6364 PseudoVLUXSEG8EI64_V_M1_MF2 = 6340,
6365 PseudoVLUXSEG8EI64_V_M1_MF2_MASK = 6341,
6366 PseudoVLUXSEG8EI64_V_M1_MF4 = 6342,
6367 PseudoVLUXSEG8EI64_V_M1_MF4_MASK = 6343,
6368 PseudoVLUXSEG8EI64_V_M1_MF8 = 6344,
6369 PseudoVLUXSEG8EI64_V_M1_MF8_MASK = 6345,
6370 PseudoVLUXSEG8EI64_V_M2_M1 = 6346,
6371 PseudoVLUXSEG8EI64_V_M2_M1_MASK = 6347,
6372 PseudoVLUXSEG8EI64_V_M2_MF2 = 6348,
6373 PseudoVLUXSEG8EI64_V_M2_MF2_MASK = 6349,
6374 PseudoVLUXSEG8EI64_V_M2_MF4 = 6350,
6375 PseudoVLUXSEG8EI64_V_M2_MF4_MASK = 6351,
6376 PseudoVLUXSEG8EI64_V_M4_M1 = 6352,
6377 PseudoVLUXSEG8EI64_V_M4_M1_MASK = 6353,
6378 PseudoVLUXSEG8EI64_V_M4_MF2 = 6354,
6379 PseudoVLUXSEG8EI64_V_M4_MF2_MASK = 6355,
6380 PseudoVLUXSEG8EI64_V_M8_M1 = 6356,
6381 PseudoVLUXSEG8EI64_V_M8_M1_MASK = 6357,
6382 PseudoVLUXSEG8EI8_V_M1_M1 = 6358,
6383 PseudoVLUXSEG8EI8_V_M1_M1_MASK = 6359,
6384 PseudoVLUXSEG8EI8_V_MF2_M1 = 6360,
6385 PseudoVLUXSEG8EI8_V_MF2_M1_MASK = 6361,
6386 PseudoVLUXSEG8EI8_V_MF2_MF2 = 6362,
6387 PseudoVLUXSEG8EI8_V_MF2_MF2_MASK = 6363,
6388 PseudoVLUXSEG8EI8_V_MF4_M1 = 6364,
6389 PseudoVLUXSEG8EI8_V_MF4_M1_MASK = 6365,
6390 PseudoVLUXSEG8EI8_V_MF4_MF2 = 6366,
6391 PseudoVLUXSEG8EI8_V_MF4_MF2_MASK = 6367,
6392 PseudoVLUXSEG8EI8_V_MF4_MF4 = 6368,
6393 PseudoVLUXSEG8EI8_V_MF4_MF4_MASK = 6369,
6394 PseudoVLUXSEG8EI8_V_MF8_M1 = 6370,
6395 PseudoVLUXSEG8EI8_V_MF8_M1_MASK = 6371,
6396 PseudoVLUXSEG8EI8_V_MF8_MF2 = 6372,
6397 PseudoVLUXSEG8EI8_V_MF8_MF2_MASK = 6373,
6398 PseudoVLUXSEG8EI8_V_MF8_MF4 = 6374,
6399 PseudoVLUXSEG8EI8_V_MF8_MF4_MASK = 6375,
6400 PseudoVLUXSEG8EI8_V_MF8_MF8 = 6376,
6401 PseudoVLUXSEG8EI8_V_MF8_MF8_MASK = 6377,
6402 PseudoVMACC_VV_M1 = 6378,
6403 PseudoVMACC_VV_M1_MASK = 6379,
6404 PseudoVMACC_VV_M2 = 6380,
6405 PseudoVMACC_VV_M2_MASK = 6381,
6406 PseudoVMACC_VV_M4 = 6382,
6407 PseudoVMACC_VV_M4_MASK = 6383,
6408 PseudoVMACC_VV_M8 = 6384,
6409 PseudoVMACC_VV_M8_MASK = 6385,
6410 PseudoVMACC_VV_MF2 = 6386,
6411 PseudoVMACC_VV_MF2_MASK = 6387,
6412 PseudoVMACC_VV_MF4 = 6388,
6413 PseudoVMACC_VV_MF4_MASK = 6389,
6414 PseudoVMACC_VV_MF8 = 6390,
6415 PseudoVMACC_VV_MF8_MASK = 6391,
6416 PseudoVMACC_VX_M1 = 6392,
6417 PseudoVMACC_VX_M1_MASK = 6393,
6418 PseudoVMACC_VX_M2 = 6394,
6419 PseudoVMACC_VX_M2_MASK = 6395,
6420 PseudoVMACC_VX_M4 = 6396,
6421 PseudoVMACC_VX_M4_MASK = 6397,
6422 PseudoVMACC_VX_M8 = 6398,
6423 PseudoVMACC_VX_M8_MASK = 6399,
6424 PseudoVMACC_VX_MF2 = 6400,
6425 PseudoVMACC_VX_MF2_MASK = 6401,
6426 PseudoVMACC_VX_MF4 = 6402,
6427 PseudoVMACC_VX_MF4_MASK = 6403,
6428 PseudoVMACC_VX_MF8 = 6404,
6429 PseudoVMACC_VX_MF8_MASK = 6405,
6430 PseudoVMADC_VIM_M1 = 6406,
6431 PseudoVMADC_VIM_M2 = 6407,
6432 PseudoVMADC_VIM_M4 = 6408,
6433 PseudoVMADC_VIM_M8 = 6409,
6434 PseudoVMADC_VIM_MF2 = 6410,
6435 PseudoVMADC_VIM_MF4 = 6411,
6436 PseudoVMADC_VIM_MF8 = 6412,
6437 PseudoVMADC_VI_M1 = 6413,
6438 PseudoVMADC_VI_M2 = 6414,
6439 PseudoVMADC_VI_M4 = 6415,
6440 PseudoVMADC_VI_M8 = 6416,
6441 PseudoVMADC_VI_MF2 = 6417,
6442 PseudoVMADC_VI_MF4 = 6418,
6443 PseudoVMADC_VI_MF8 = 6419,
6444 PseudoVMADC_VVM_M1 = 6420,
6445 PseudoVMADC_VVM_M2 = 6421,
6446 PseudoVMADC_VVM_M4 = 6422,
6447 PseudoVMADC_VVM_M8 = 6423,
6448 PseudoVMADC_VVM_MF2 = 6424,
6449 PseudoVMADC_VVM_MF4 = 6425,
6450 PseudoVMADC_VVM_MF8 = 6426,
6451 PseudoVMADC_VV_M1 = 6427,
6452 PseudoVMADC_VV_M2 = 6428,
6453 PseudoVMADC_VV_M4 = 6429,
6454 PseudoVMADC_VV_M8 = 6430,
6455 PseudoVMADC_VV_MF2 = 6431,
6456 PseudoVMADC_VV_MF4 = 6432,
6457 PseudoVMADC_VV_MF8 = 6433,
6458 PseudoVMADC_VXM_M1 = 6434,
6459 PseudoVMADC_VXM_M2 = 6435,
6460 PseudoVMADC_VXM_M4 = 6436,
6461 PseudoVMADC_VXM_M8 = 6437,
6462 PseudoVMADC_VXM_MF2 = 6438,
6463 PseudoVMADC_VXM_MF4 = 6439,
6464 PseudoVMADC_VXM_MF8 = 6440,
6465 PseudoVMADC_VX_M1 = 6441,
6466 PseudoVMADC_VX_M2 = 6442,
6467 PseudoVMADC_VX_M4 = 6443,
6468 PseudoVMADC_VX_M8 = 6444,
6469 PseudoVMADC_VX_MF2 = 6445,
6470 PseudoVMADC_VX_MF4 = 6446,
6471 PseudoVMADC_VX_MF8 = 6447,
6472 PseudoVMADD_VV_M1 = 6448,
6473 PseudoVMADD_VV_M1_MASK = 6449,
6474 PseudoVMADD_VV_M2 = 6450,
6475 PseudoVMADD_VV_M2_MASK = 6451,
6476 PseudoVMADD_VV_M4 = 6452,
6477 PseudoVMADD_VV_M4_MASK = 6453,
6478 PseudoVMADD_VV_M8 = 6454,
6479 PseudoVMADD_VV_M8_MASK = 6455,
6480 PseudoVMADD_VV_MF2 = 6456,
6481 PseudoVMADD_VV_MF2_MASK = 6457,
6482 PseudoVMADD_VV_MF4 = 6458,
6483 PseudoVMADD_VV_MF4_MASK = 6459,
6484 PseudoVMADD_VV_MF8 = 6460,
6485 PseudoVMADD_VV_MF8_MASK = 6461,
6486 PseudoVMADD_VX_M1 = 6462,
6487 PseudoVMADD_VX_M1_MASK = 6463,
6488 PseudoVMADD_VX_M2 = 6464,
6489 PseudoVMADD_VX_M2_MASK = 6465,
6490 PseudoVMADD_VX_M4 = 6466,
6491 PseudoVMADD_VX_M4_MASK = 6467,
6492 PseudoVMADD_VX_M8 = 6468,
6493 PseudoVMADD_VX_M8_MASK = 6469,
6494 PseudoVMADD_VX_MF2 = 6470,
6495 PseudoVMADD_VX_MF2_MASK = 6471,
6496 PseudoVMADD_VX_MF4 = 6472,
6497 PseudoVMADD_VX_MF4_MASK = 6473,
6498 PseudoVMADD_VX_MF8 = 6474,
6499 PseudoVMADD_VX_MF8_MASK = 6475,
6500 PseudoVMANDN_MM_M1 = 6476,
6501 PseudoVMANDN_MM_M2 = 6477,
6502 PseudoVMANDN_MM_M4 = 6478,
6503 PseudoVMANDN_MM_M8 = 6479,
6504 PseudoVMANDN_MM_MF2 = 6480,
6505 PseudoVMANDN_MM_MF4 = 6481,
6506 PseudoVMANDN_MM_MF8 = 6482,
6507 PseudoVMAND_MM_M1 = 6483,
6508 PseudoVMAND_MM_M2 = 6484,
6509 PseudoVMAND_MM_M4 = 6485,
6510 PseudoVMAND_MM_M8 = 6486,
6511 PseudoVMAND_MM_MF2 = 6487,
6512 PseudoVMAND_MM_MF4 = 6488,
6513 PseudoVMAND_MM_MF8 = 6489,
6514 PseudoVMAXU_VV_M1 = 6490,
6515 PseudoVMAXU_VV_M1_MASK = 6491,
6516 PseudoVMAXU_VV_M2 = 6492,
6517 PseudoVMAXU_VV_M2_MASK = 6493,
6518 PseudoVMAXU_VV_M4 = 6494,
6519 PseudoVMAXU_VV_M4_MASK = 6495,
6520 PseudoVMAXU_VV_M8 = 6496,
6521 PseudoVMAXU_VV_M8_MASK = 6497,
6522 PseudoVMAXU_VV_MF2 = 6498,
6523 PseudoVMAXU_VV_MF2_MASK = 6499,
6524 PseudoVMAXU_VV_MF4 = 6500,
6525 PseudoVMAXU_VV_MF4_MASK = 6501,
6526 PseudoVMAXU_VV_MF8 = 6502,
6527 PseudoVMAXU_VV_MF8_MASK = 6503,
6528 PseudoVMAXU_VX_M1 = 6504,
6529 PseudoVMAXU_VX_M1_MASK = 6505,
6530 PseudoVMAXU_VX_M2 = 6506,
6531 PseudoVMAXU_VX_M2_MASK = 6507,
6532 PseudoVMAXU_VX_M4 = 6508,
6533 PseudoVMAXU_VX_M4_MASK = 6509,
6534 PseudoVMAXU_VX_M8 = 6510,
6535 PseudoVMAXU_VX_M8_MASK = 6511,
6536 PseudoVMAXU_VX_MF2 = 6512,
6537 PseudoVMAXU_VX_MF2_MASK = 6513,
6538 PseudoVMAXU_VX_MF4 = 6514,
6539 PseudoVMAXU_VX_MF4_MASK = 6515,
6540 PseudoVMAXU_VX_MF8 = 6516,
6541 PseudoVMAXU_VX_MF8_MASK = 6517,
6542 PseudoVMAX_VV_M1 = 6518,
6543 PseudoVMAX_VV_M1_MASK = 6519,
6544 PseudoVMAX_VV_M2 = 6520,
6545 PseudoVMAX_VV_M2_MASK = 6521,
6546 PseudoVMAX_VV_M4 = 6522,
6547 PseudoVMAX_VV_M4_MASK = 6523,
6548 PseudoVMAX_VV_M8 = 6524,
6549 PseudoVMAX_VV_M8_MASK = 6525,
6550 PseudoVMAX_VV_MF2 = 6526,
6551 PseudoVMAX_VV_MF2_MASK = 6527,
6552 PseudoVMAX_VV_MF4 = 6528,
6553 PseudoVMAX_VV_MF4_MASK = 6529,
6554 PseudoVMAX_VV_MF8 = 6530,
6555 PseudoVMAX_VV_MF8_MASK = 6531,
6556 PseudoVMAX_VX_M1 = 6532,
6557 PseudoVMAX_VX_M1_MASK = 6533,
6558 PseudoVMAX_VX_M2 = 6534,
6559 PseudoVMAX_VX_M2_MASK = 6535,
6560 PseudoVMAX_VX_M4 = 6536,
6561 PseudoVMAX_VX_M4_MASK = 6537,
6562 PseudoVMAX_VX_M8 = 6538,
6563 PseudoVMAX_VX_M8_MASK = 6539,
6564 PseudoVMAX_VX_MF2 = 6540,
6565 PseudoVMAX_VX_MF2_MASK = 6541,
6566 PseudoVMAX_VX_MF4 = 6542,
6567 PseudoVMAX_VX_MF4_MASK = 6543,
6568 PseudoVMAX_VX_MF8 = 6544,
6569 PseudoVMAX_VX_MF8_MASK = 6545,
6570 PseudoVMCLR_M_B1 = 6546,
6571 PseudoVMCLR_M_B16 = 6547,
6572 PseudoVMCLR_M_B2 = 6548,
6573 PseudoVMCLR_M_B32 = 6549,
6574 PseudoVMCLR_M_B4 = 6550,
6575 PseudoVMCLR_M_B64 = 6551,
6576 PseudoVMCLR_M_B8 = 6552,
6577 PseudoVMERGE_VIM_M1 = 6553,
6578 PseudoVMERGE_VIM_M2 = 6554,
6579 PseudoVMERGE_VIM_M4 = 6555,
6580 PseudoVMERGE_VIM_M8 = 6556,
6581 PseudoVMERGE_VIM_MF2 = 6557,
6582 PseudoVMERGE_VIM_MF4 = 6558,
6583 PseudoVMERGE_VIM_MF8 = 6559,
6584 PseudoVMERGE_VVM_M1 = 6560,
6585 PseudoVMERGE_VVM_M2 = 6561,
6586 PseudoVMERGE_VVM_M4 = 6562,
6587 PseudoVMERGE_VVM_M8 = 6563,
6588 PseudoVMERGE_VVM_MF2 = 6564,
6589 PseudoVMERGE_VVM_MF4 = 6565,
6590 PseudoVMERGE_VVM_MF8 = 6566,
6591 PseudoVMERGE_VXM_M1 = 6567,
6592 PseudoVMERGE_VXM_M2 = 6568,
6593 PseudoVMERGE_VXM_M4 = 6569,
6594 PseudoVMERGE_VXM_M8 = 6570,
6595 PseudoVMERGE_VXM_MF2 = 6571,
6596 PseudoVMERGE_VXM_MF4 = 6572,
6597 PseudoVMERGE_VXM_MF8 = 6573,
6598 PseudoVMFEQ_VFPR16_M1 = 6574,
6599 PseudoVMFEQ_VFPR16_M1_MASK = 6575,
6600 PseudoVMFEQ_VFPR16_M2 = 6576,
6601 PseudoVMFEQ_VFPR16_M2_MASK = 6577,
6602 PseudoVMFEQ_VFPR16_M4 = 6578,
6603 PseudoVMFEQ_VFPR16_M4_MASK = 6579,
6604 PseudoVMFEQ_VFPR16_M8 = 6580,
6605 PseudoVMFEQ_VFPR16_M8_MASK = 6581,
6606 PseudoVMFEQ_VFPR16_MF2 = 6582,
6607 PseudoVMFEQ_VFPR16_MF2_MASK = 6583,
6608 PseudoVMFEQ_VFPR16_MF4 = 6584,
6609 PseudoVMFEQ_VFPR16_MF4_MASK = 6585,
6610 PseudoVMFEQ_VFPR32_M1 = 6586,
6611 PseudoVMFEQ_VFPR32_M1_MASK = 6587,
6612 PseudoVMFEQ_VFPR32_M2 = 6588,
6613 PseudoVMFEQ_VFPR32_M2_MASK = 6589,
6614 PseudoVMFEQ_VFPR32_M4 = 6590,
6615 PseudoVMFEQ_VFPR32_M4_MASK = 6591,
6616 PseudoVMFEQ_VFPR32_M8 = 6592,
6617 PseudoVMFEQ_VFPR32_M8_MASK = 6593,
6618 PseudoVMFEQ_VFPR32_MF2 = 6594,
6619 PseudoVMFEQ_VFPR32_MF2_MASK = 6595,
6620 PseudoVMFEQ_VFPR64_M1 = 6596,
6621 PseudoVMFEQ_VFPR64_M1_MASK = 6597,
6622 PseudoVMFEQ_VFPR64_M2 = 6598,
6623 PseudoVMFEQ_VFPR64_M2_MASK = 6599,
6624 PseudoVMFEQ_VFPR64_M4 = 6600,
6625 PseudoVMFEQ_VFPR64_M4_MASK = 6601,
6626 PseudoVMFEQ_VFPR64_M8 = 6602,
6627 PseudoVMFEQ_VFPR64_M8_MASK = 6603,
6628 PseudoVMFEQ_VV_M1 = 6604,
6629 PseudoVMFEQ_VV_M1_MASK = 6605,
6630 PseudoVMFEQ_VV_M2 = 6606,
6631 PseudoVMFEQ_VV_M2_MASK = 6607,
6632 PseudoVMFEQ_VV_M4 = 6608,
6633 PseudoVMFEQ_VV_M4_MASK = 6609,
6634 PseudoVMFEQ_VV_M8 = 6610,
6635 PseudoVMFEQ_VV_M8_MASK = 6611,
6636 PseudoVMFEQ_VV_MF2 = 6612,
6637 PseudoVMFEQ_VV_MF2_MASK = 6613,
6638 PseudoVMFEQ_VV_MF4 = 6614,
6639 PseudoVMFEQ_VV_MF4_MASK = 6615,
6640 PseudoVMFGE_VFPR16_M1 = 6616,
6641 PseudoVMFGE_VFPR16_M1_MASK = 6617,
6642 PseudoVMFGE_VFPR16_M2 = 6618,
6643 PseudoVMFGE_VFPR16_M2_MASK = 6619,
6644 PseudoVMFGE_VFPR16_M4 = 6620,
6645 PseudoVMFGE_VFPR16_M4_MASK = 6621,
6646 PseudoVMFGE_VFPR16_M8 = 6622,
6647 PseudoVMFGE_VFPR16_M8_MASK = 6623,
6648 PseudoVMFGE_VFPR16_MF2 = 6624,
6649 PseudoVMFGE_VFPR16_MF2_MASK = 6625,
6650 PseudoVMFGE_VFPR16_MF4 = 6626,
6651 PseudoVMFGE_VFPR16_MF4_MASK = 6627,
6652 PseudoVMFGE_VFPR32_M1 = 6628,
6653 PseudoVMFGE_VFPR32_M1_MASK = 6629,
6654 PseudoVMFGE_VFPR32_M2 = 6630,
6655 PseudoVMFGE_VFPR32_M2_MASK = 6631,
6656 PseudoVMFGE_VFPR32_M4 = 6632,
6657 PseudoVMFGE_VFPR32_M4_MASK = 6633,
6658 PseudoVMFGE_VFPR32_M8 = 6634,
6659 PseudoVMFGE_VFPR32_M8_MASK = 6635,
6660 PseudoVMFGE_VFPR32_MF2 = 6636,
6661 PseudoVMFGE_VFPR32_MF2_MASK = 6637,
6662 PseudoVMFGE_VFPR64_M1 = 6638,
6663 PseudoVMFGE_VFPR64_M1_MASK = 6639,
6664 PseudoVMFGE_VFPR64_M2 = 6640,
6665 PseudoVMFGE_VFPR64_M2_MASK = 6641,
6666 PseudoVMFGE_VFPR64_M4 = 6642,
6667 PseudoVMFGE_VFPR64_M4_MASK = 6643,
6668 PseudoVMFGE_VFPR64_M8 = 6644,
6669 PseudoVMFGE_VFPR64_M8_MASK = 6645,
6670 PseudoVMFGT_VFPR16_M1 = 6646,
6671 PseudoVMFGT_VFPR16_M1_MASK = 6647,
6672 PseudoVMFGT_VFPR16_M2 = 6648,
6673 PseudoVMFGT_VFPR16_M2_MASK = 6649,
6674 PseudoVMFGT_VFPR16_M4 = 6650,
6675 PseudoVMFGT_VFPR16_M4_MASK = 6651,
6676 PseudoVMFGT_VFPR16_M8 = 6652,
6677 PseudoVMFGT_VFPR16_M8_MASK = 6653,
6678 PseudoVMFGT_VFPR16_MF2 = 6654,
6679 PseudoVMFGT_VFPR16_MF2_MASK = 6655,
6680 PseudoVMFGT_VFPR16_MF4 = 6656,
6681 PseudoVMFGT_VFPR16_MF4_MASK = 6657,
6682 PseudoVMFGT_VFPR32_M1 = 6658,
6683 PseudoVMFGT_VFPR32_M1_MASK = 6659,
6684 PseudoVMFGT_VFPR32_M2 = 6660,
6685 PseudoVMFGT_VFPR32_M2_MASK = 6661,
6686 PseudoVMFGT_VFPR32_M4 = 6662,
6687 PseudoVMFGT_VFPR32_M4_MASK = 6663,
6688 PseudoVMFGT_VFPR32_M8 = 6664,
6689 PseudoVMFGT_VFPR32_M8_MASK = 6665,
6690 PseudoVMFGT_VFPR32_MF2 = 6666,
6691 PseudoVMFGT_VFPR32_MF2_MASK = 6667,
6692 PseudoVMFGT_VFPR64_M1 = 6668,
6693 PseudoVMFGT_VFPR64_M1_MASK = 6669,
6694 PseudoVMFGT_VFPR64_M2 = 6670,
6695 PseudoVMFGT_VFPR64_M2_MASK = 6671,
6696 PseudoVMFGT_VFPR64_M4 = 6672,
6697 PseudoVMFGT_VFPR64_M4_MASK = 6673,
6698 PseudoVMFGT_VFPR64_M8 = 6674,
6699 PseudoVMFGT_VFPR64_M8_MASK = 6675,
6700 PseudoVMFLE_VFPR16_M1 = 6676,
6701 PseudoVMFLE_VFPR16_M1_MASK = 6677,
6702 PseudoVMFLE_VFPR16_M2 = 6678,
6703 PseudoVMFLE_VFPR16_M2_MASK = 6679,
6704 PseudoVMFLE_VFPR16_M4 = 6680,
6705 PseudoVMFLE_VFPR16_M4_MASK = 6681,
6706 PseudoVMFLE_VFPR16_M8 = 6682,
6707 PseudoVMFLE_VFPR16_M8_MASK = 6683,
6708 PseudoVMFLE_VFPR16_MF2 = 6684,
6709 PseudoVMFLE_VFPR16_MF2_MASK = 6685,
6710 PseudoVMFLE_VFPR16_MF4 = 6686,
6711 PseudoVMFLE_VFPR16_MF4_MASK = 6687,
6712 PseudoVMFLE_VFPR32_M1 = 6688,
6713 PseudoVMFLE_VFPR32_M1_MASK = 6689,
6714 PseudoVMFLE_VFPR32_M2 = 6690,
6715 PseudoVMFLE_VFPR32_M2_MASK = 6691,
6716 PseudoVMFLE_VFPR32_M4 = 6692,
6717 PseudoVMFLE_VFPR32_M4_MASK = 6693,
6718 PseudoVMFLE_VFPR32_M8 = 6694,
6719 PseudoVMFLE_VFPR32_M8_MASK = 6695,
6720 PseudoVMFLE_VFPR32_MF2 = 6696,
6721 PseudoVMFLE_VFPR32_MF2_MASK = 6697,
6722 PseudoVMFLE_VFPR64_M1 = 6698,
6723 PseudoVMFLE_VFPR64_M1_MASK = 6699,
6724 PseudoVMFLE_VFPR64_M2 = 6700,
6725 PseudoVMFLE_VFPR64_M2_MASK = 6701,
6726 PseudoVMFLE_VFPR64_M4 = 6702,
6727 PseudoVMFLE_VFPR64_M4_MASK = 6703,
6728 PseudoVMFLE_VFPR64_M8 = 6704,
6729 PseudoVMFLE_VFPR64_M8_MASK = 6705,
6730 PseudoVMFLE_VV_M1 = 6706,
6731 PseudoVMFLE_VV_M1_MASK = 6707,
6732 PseudoVMFLE_VV_M2 = 6708,
6733 PseudoVMFLE_VV_M2_MASK = 6709,
6734 PseudoVMFLE_VV_M4 = 6710,
6735 PseudoVMFLE_VV_M4_MASK = 6711,
6736 PseudoVMFLE_VV_M8 = 6712,
6737 PseudoVMFLE_VV_M8_MASK = 6713,
6738 PseudoVMFLE_VV_MF2 = 6714,
6739 PseudoVMFLE_VV_MF2_MASK = 6715,
6740 PseudoVMFLE_VV_MF4 = 6716,
6741 PseudoVMFLE_VV_MF4_MASK = 6717,
6742 PseudoVMFLT_VFPR16_M1 = 6718,
6743 PseudoVMFLT_VFPR16_M1_MASK = 6719,
6744 PseudoVMFLT_VFPR16_M2 = 6720,
6745 PseudoVMFLT_VFPR16_M2_MASK = 6721,
6746 PseudoVMFLT_VFPR16_M4 = 6722,
6747 PseudoVMFLT_VFPR16_M4_MASK = 6723,
6748 PseudoVMFLT_VFPR16_M8 = 6724,
6749 PseudoVMFLT_VFPR16_M8_MASK = 6725,
6750 PseudoVMFLT_VFPR16_MF2 = 6726,
6751 PseudoVMFLT_VFPR16_MF2_MASK = 6727,
6752 PseudoVMFLT_VFPR16_MF4 = 6728,
6753 PseudoVMFLT_VFPR16_MF4_MASK = 6729,
6754 PseudoVMFLT_VFPR32_M1 = 6730,
6755 PseudoVMFLT_VFPR32_M1_MASK = 6731,
6756 PseudoVMFLT_VFPR32_M2 = 6732,
6757 PseudoVMFLT_VFPR32_M2_MASK = 6733,
6758 PseudoVMFLT_VFPR32_M4 = 6734,
6759 PseudoVMFLT_VFPR32_M4_MASK = 6735,
6760 PseudoVMFLT_VFPR32_M8 = 6736,
6761 PseudoVMFLT_VFPR32_M8_MASK = 6737,
6762 PseudoVMFLT_VFPR32_MF2 = 6738,
6763 PseudoVMFLT_VFPR32_MF2_MASK = 6739,
6764 PseudoVMFLT_VFPR64_M1 = 6740,
6765 PseudoVMFLT_VFPR64_M1_MASK = 6741,
6766 PseudoVMFLT_VFPR64_M2 = 6742,
6767 PseudoVMFLT_VFPR64_M2_MASK = 6743,
6768 PseudoVMFLT_VFPR64_M4 = 6744,
6769 PseudoVMFLT_VFPR64_M4_MASK = 6745,
6770 PseudoVMFLT_VFPR64_M8 = 6746,
6771 PseudoVMFLT_VFPR64_M8_MASK = 6747,
6772 PseudoVMFLT_VV_M1 = 6748,
6773 PseudoVMFLT_VV_M1_MASK = 6749,
6774 PseudoVMFLT_VV_M2 = 6750,
6775 PseudoVMFLT_VV_M2_MASK = 6751,
6776 PseudoVMFLT_VV_M4 = 6752,
6777 PseudoVMFLT_VV_M4_MASK = 6753,
6778 PseudoVMFLT_VV_M8 = 6754,
6779 PseudoVMFLT_VV_M8_MASK = 6755,
6780 PseudoVMFLT_VV_MF2 = 6756,
6781 PseudoVMFLT_VV_MF2_MASK = 6757,
6782 PseudoVMFLT_VV_MF4 = 6758,
6783 PseudoVMFLT_VV_MF4_MASK = 6759,
6784 PseudoVMFNE_VFPR16_M1 = 6760,
6785 PseudoVMFNE_VFPR16_M1_MASK = 6761,
6786 PseudoVMFNE_VFPR16_M2 = 6762,
6787 PseudoVMFNE_VFPR16_M2_MASK = 6763,
6788 PseudoVMFNE_VFPR16_M4 = 6764,
6789 PseudoVMFNE_VFPR16_M4_MASK = 6765,
6790 PseudoVMFNE_VFPR16_M8 = 6766,
6791 PseudoVMFNE_VFPR16_M8_MASK = 6767,
6792 PseudoVMFNE_VFPR16_MF2 = 6768,
6793 PseudoVMFNE_VFPR16_MF2_MASK = 6769,
6794 PseudoVMFNE_VFPR16_MF4 = 6770,
6795 PseudoVMFNE_VFPR16_MF4_MASK = 6771,
6796 PseudoVMFNE_VFPR32_M1 = 6772,
6797 PseudoVMFNE_VFPR32_M1_MASK = 6773,
6798 PseudoVMFNE_VFPR32_M2 = 6774,
6799 PseudoVMFNE_VFPR32_M2_MASK = 6775,
6800 PseudoVMFNE_VFPR32_M4 = 6776,
6801 PseudoVMFNE_VFPR32_M4_MASK = 6777,
6802 PseudoVMFNE_VFPR32_M8 = 6778,
6803 PseudoVMFNE_VFPR32_M8_MASK = 6779,
6804 PseudoVMFNE_VFPR32_MF2 = 6780,
6805 PseudoVMFNE_VFPR32_MF2_MASK = 6781,
6806 PseudoVMFNE_VFPR64_M1 = 6782,
6807 PseudoVMFNE_VFPR64_M1_MASK = 6783,
6808 PseudoVMFNE_VFPR64_M2 = 6784,
6809 PseudoVMFNE_VFPR64_M2_MASK = 6785,
6810 PseudoVMFNE_VFPR64_M4 = 6786,
6811 PseudoVMFNE_VFPR64_M4_MASK = 6787,
6812 PseudoVMFNE_VFPR64_M8 = 6788,
6813 PseudoVMFNE_VFPR64_M8_MASK = 6789,
6814 PseudoVMFNE_VV_M1 = 6790,
6815 PseudoVMFNE_VV_M1_MASK = 6791,
6816 PseudoVMFNE_VV_M2 = 6792,
6817 PseudoVMFNE_VV_M2_MASK = 6793,
6818 PseudoVMFNE_VV_M4 = 6794,
6819 PseudoVMFNE_VV_M4_MASK = 6795,
6820 PseudoVMFNE_VV_M8 = 6796,
6821 PseudoVMFNE_VV_M8_MASK = 6797,
6822 PseudoVMFNE_VV_MF2 = 6798,
6823 PseudoVMFNE_VV_MF2_MASK = 6799,
6824 PseudoVMFNE_VV_MF4 = 6800,
6825 PseudoVMFNE_VV_MF4_MASK = 6801,
6826 PseudoVMINU_VV_M1 = 6802,
6827 PseudoVMINU_VV_M1_MASK = 6803,
6828 PseudoVMINU_VV_M2 = 6804,
6829 PseudoVMINU_VV_M2_MASK = 6805,
6830 PseudoVMINU_VV_M4 = 6806,
6831 PseudoVMINU_VV_M4_MASK = 6807,
6832 PseudoVMINU_VV_M8 = 6808,
6833 PseudoVMINU_VV_M8_MASK = 6809,
6834 PseudoVMINU_VV_MF2 = 6810,
6835 PseudoVMINU_VV_MF2_MASK = 6811,
6836 PseudoVMINU_VV_MF4 = 6812,
6837 PseudoVMINU_VV_MF4_MASK = 6813,
6838 PseudoVMINU_VV_MF8 = 6814,
6839 PseudoVMINU_VV_MF8_MASK = 6815,
6840 PseudoVMINU_VX_M1 = 6816,
6841 PseudoVMINU_VX_M1_MASK = 6817,
6842 PseudoVMINU_VX_M2 = 6818,
6843 PseudoVMINU_VX_M2_MASK = 6819,
6844 PseudoVMINU_VX_M4 = 6820,
6845 PseudoVMINU_VX_M4_MASK = 6821,
6846 PseudoVMINU_VX_M8 = 6822,
6847 PseudoVMINU_VX_M8_MASK = 6823,
6848 PseudoVMINU_VX_MF2 = 6824,
6849 PseudoVMINU_VX_MF2_MASK = 6825,
6850 PseudoVMINU_VX_MF4 = 6826,
6851 PseudoVMINU_VX_MF4_MASK = 6827,
6852 PseudoVMINU_VX_MF8 = 6828,
6853 PseudoVMINU_VX_MF8_MASK = 6829,
6854 PseudoVMIN_VV_M1 = 6830,
6855 PseudoVMIN_VV_M1_MASK = 6831,
6856 PseudoVMIN_VV_M2 = 6832,
6857 PseudoVMIN_VV_M2_MASK = 6833,
6858 PseudoVMIN_VV_M4 = 6834,
6859 PseudoVMIN_VV_M4_MASK = 6835,
6860 PseudoVMIN_VV_M8 = 6836,
6861 PseudoVMIN_VV_M8_MASK = 6837,
6862 PseudoVMIN_VV_MF2 = 6838,
6863 PseudoVMIN_VV_MF2_MASK = 6839,
6864 PseudoVMIN_VV_MF4 = 6840,
6865 PseudoVMIN_VV_MF4_MASK = 6841,
6866 PseudoVMIN_VV_MF8 = 6842,
6867 PseudoVMIN_VV_MF8_MASK = 6843,
6868 PseudoVMIN_VX_M1 = 6844,
6869 PseudoVMIN_VX_M1_MASK = 6845,
6870 PseudoVMIN_VX_M2 = 6846,
6871 PseudoVMIN_VX_M2_MASK = 6847,
6872 PseudoVMIN_VX_M4 = 6848,
6873 PseudoVMIN_VX_M4_MASK = 6849,
6874 PseudoVMIN_VX_M8 = 6850,
6875 PseudoVMIN_VX_M8_MASK = 6851,
6876 PseudoVMIN_VX_MF2 = 6852,
6877 PseudoVMIN_VX_MF2_MASK = 6853,
6878 PseudoVMIN_VX_MF4 = 6854,
6879 PseudoVMIN_VX_MF4_MASK = 6855,
6880 PseudoVMIN_VX_MF8 = 6856,
6881 PseudoVMIN_VX_MF8_MASK = 6857,
6882 PseudoVMNAND_MM_M1 = 6858,
6883 PseudoVMNAND_MM_M2 = 6859,
6884 PseudoVMNAND_MM_M4 = 6860,
6885 PseudoVMNAND_MM_M8 = 6861,
6886 PseudoVMNAND_MM_MF2 = 6862,
6887 PseudoVMNAND_MM_MF4 = 6863,
6888 PseudoVMNAND_MM_MF8 = 6864,
6889 PseudoVMNOR_MM_M1 = 6865,
6890 PseudoVMNOR_MM_M2 = 6866,
6891 PseudoVMNOR_MM_M4 = 6867,
6892 PseudoVMNOR_MM_M8 = 6868,
6893 PseudoVMNOR_MM_MF2 = 6869,
6894 PseudoVMNOR_MM_MF4 = 6870,
6895 PseudoVMNOR_MM_MF8 = 6871,
6896 PseudoVMORN_MM_M1 = 6872,
6897 PseudoVMORN_MM_M2 = 6873,
6898 PseudoVMORN_MM_M4 = 6874,
6899 PseudoVMORN_MM_M8 = 6875,
6900 PseudoVMORN_MM_MF2 = 6876,
6901 PseudoVMORN_MM_MF4 = 6877,
6902 PseudoVMORN_MM_MF8 = 6878,
6903 PseudoVMOR_MM_M1 = 6879,
6904 PseudoVMOR_MM_M2 = 6880,
6905 PseudoVMOR_MM_M4 = 6881,
6906 PseudoVMOR_MM_M8 = 6882,
6907 PseudoVMOR_MM_MF2 = 6883,
6908 PseudoVMOR_MM_MF4 = 6884,
6909 PseudoVMOR_MM_MF8 = 6885,
6910 PseudoVMSBC_VVM_M1 = 6886,
6911 PseudoVMSBC_VVM_M2 = 6887,
6912 PseudoVMSBC_VVM_M4 = 6888,
6913 PseudoVMSBC_VVM_M8 = 6889,
6914 PseudoVMSBC_VVM_MF2 = 6890,
6915 PseudoVMSBC_VVM_MF4 = 6891,
6916 PseudoVMSBC_VVM_MF8 = 6892,
6917 PseudoVMSBC_VV_M1 = 6893,
6918 PseudoVMSBC_VV_M2 = 6894,
6919 PseudoVMSBC_VV_M4 = 6895,
6920 PseudoVMSBC_VV_M8 = 6896,
6921 PseudoVMSBC_VV_MF2 = 6897,
6922 PseudoVMSBC_VV_MF4 = 6898,
6923 PseudoVMSBC_VV_MF8 = 6899,
6924 PseudoVMSBC_VXM_M1 = 6900,
6925 PseudoVMSBC_VXM_M2 = 6901,
6926 PseudoVMSBC_VXM_M4 = 6902,
6927 PseudoVMSBC_VXM_M8 = 6903,
6928 PseudoVMSBC_VXM_MF2 = 6904,
6929 PseudoVMSBC_VXM_MF4 = 6905,
6930 PseudoVMSBC_VXM_MF8 = 6906,
6931 PseudoVMSBC_VX_M1 = 6907,
6932 PseudoVMSBC_VX_M2 = 6908,
6933 PseudoVMSBC_VX_M4 = 6909,
6934 PseudoVMSBC_VX_M8 = 6910,
6935 PseudoVMSBC_VX_MF2 = 6911,
6936 PseudoVMSBC_VX_MF4 = 6912,
6937 PseudoVMSBC_VX_MF8 = 6913,
6938 PseudoVMSBF_M_B1 = 6914,
6939 PseudoVMSBF_M_B16 = 6915,
6940 PseudoVMSBF_M_B16_MASK = 6916,
6941 PseudoVMSBF_M_B1_MASK = 6917,
6942 PseudoVMSBF_M_B2 = 6918,
6943 PseudoVMSBF_M_B2_MASK = 6919,
6944 PseudoVMSBF_M_B32 = 6920,
6945 PseudoVMSBF_M_B32_MASK = 6921,
6946 PseudoVMSBF_M_B4 = 6922,
6947 PseudoVMSBF_M_B4_MASK = 6923,
6948 PseudoVMSBF_M_B64 = 6924,
6949 PseudoVMSBF_M_B64_MASK = 6925,
6950 PseudoVMSBF_M_B8 = 6926,
6951 PseudoVMSBF_M_B8_MASK = 6927,
6952 PseudoVMSEQ_VI_M1 = 6928,
6953 PseudoVMSEQ_VI_M1_MASK = 6929,
6954 PseudoVMSEQ_VI_M2 = 6930,
6955 PseudoVMSEQ_VI_M2_MASK = 6931,
6956 PseudoVMSEQ_VI_M4 = 6932,
6957 PseudoVMSEQ_VI_M4_MASK = 6933,
6958 PseudoVMSEQ_VI_M8 = 6934,
6959 PseudoVMSEQ_VI_M8_MASK = 6935,
6960 PseudoVMSEQ_VI_MF2 = 6936,
6961 PseudoVMSEQ_VI_MF2_MASK = 6937,
6962 PseudoVMSEQ_VI_MF4 = 6938,
6963 PseudoVMSEQ_VI_MF4_MASK = 6939,
6964 PseudoVMSEQ_VI_MF8 = 6940,
6965 PseudoVMSEQ_VI_MF8_MASK = 6941,
6966 PseudoVMSEQ_VV_M1 = 6942,
6967 PseudoVMSEQ_VV_M1_MASK = 6943,
6968 PseudoVMSEQ_VV_M2 = 6944,
6969 PseudoVMSEQ_VV_M2_MASK = 6945,
6970 PseudoVMSEQ_VV_M4 = 6946,
6971 PseudoVMSEQ_VV_M4_MASK = 6947,
6972 PseudoVMSEQ_VV_M8 = 6948,
6973 PseudoVMSEQ_VV_M8_MASK = 6949,
6974 PseudoVMSEQ_VV_MF2 = 6950,
6975 PseudoVMSEQ_VV_MF2_MASK = 6951,
6976 PseudoVMSEQ_VV_MF4 = 6952,
6977 PseudoVMSEQ_VV_MF4_MASK = 6953,
6978 PseudoVMSEQ_VV_MF8 = 6954,
6979 PseudoVMSEQ_VV_MF8_MASK = 6955,
6980 PseudoVMSEQ_VX_M1 = 6956,
6981 PseudoVMSEQ_VX_M1_MASK = 6957,
6982 PseudoVMSEQ_VX_M2 = 6958,
6983 PseudoVMSEQ_VX_M2_MASK = 6959,
6984 PseudoVMSEQ_VX_M4 = 6960,
6985 PseudoVMSEQ_VX_M4_MASK = 6961,
6986 PseudoVMSEQ_VX_M8 = 6962,
6987 PseudoVMSEQ_VX_M8_MASK = 6963,
6988 PseudoVMSEQ_VX_MF2 = 6964,
6989 PseudoVMSEQ_VX_MF2_MASK = 6965,
6990 PseudoVMSEQ_VX_MF4 = 6966,
6991 PseudoVMSEQ_VX_MF4_MASK = 6967,
6992 PseudoVMSEQ_VX_MF8 = 6968,
6993 PseudoVMSEQ_VX_MF8_MASK = 6969,
6994 PseudoVMSET_M_B1 = 6970,
6995 PseudoVMSET_M_B16 = 6971,
6996 PseudoVMSET_M_B2 = 6972,
6997 PseudoVMSET_M_B32 = 6973,
6998 PseudoVMSET_M_B4 = 6974,
6999 PseudoVMSET_M_B64 = 6975,
7000 PseudoVMSET_M_B8 = 6976,
7001 PseudoVMSGEU_VI = 6977,
7002 PseudoVMSGEU_VX = 6978,
7003 PseudoVMSGEU_VX_M = 6979,
7004 PseudoVMSGEU_VX_M_T = 6980,
7005 PseudoVMSGE_VI = 6981,
7006 PseudoVMSGE_VX = 6982,
7007 PseudoVMSGE_VX_M = 6983,
7008 PseudoVMSGE_VX_M_T = 6984,
7009 PseudoVMSGTU_VI_M1 = 6985,
7010 PseudoVMSGTU_VI_M1_MASK = 6986,
7011 PseudoVMSGTU_VI_M2 = 6987,
7012 PseudoVMSGTU_VI_M2_MASK = 6988,
7013 PseudoVMSGTU_VI_M4 = 6989,
7014 PseudoVMSGTU_VI_M4_MASK = 6990,
7015 PseudoVMSGTU_VI_M8 = 6991,
7016 PseudoVMSGTU_VI_M8_MASK = 6992,
7017 PseudoVMSGTU_VI_MF2 = 6993,
7018 PseudoVMSGTU_VI_MF2_MASK = 6994,
7019 PseudoVMSGTU_VI_MF4 = 6995,
7020 PseudoVMSGTU_VI_MF4_MASK = 6996,
7021 PseudoVMSGTU_VI_MF8 = 6997,
7022 PseudoVMSGTU_VI_MF8_MASK = 6998,
7023 PseudoVMSGTU_VX_M1 = 6999,
7024 PseudoVMSGTU_VX_M1_MASK = 7000,
7025 PseudoVMSGTU_VX_M2 = 7001,
7026 PseudoVMSGTU_VX_M2_MASK = 7002,
7027 PseudoVMSGTU_VX_M4 = 7003,
7028 PseudoVMSGTU_VX_M4_MASK = 7004,
7029 PseudoVMSGTU_VX_M8 = 7005,
7030 PseudoVMSGTU_VX_M8_MASK = 7006,
7031 PseudoVMSGTU_VX_MF2 = 7007,
7032 PseudoVMSGTU_VX_MF2_MASK = 7008,
7033 PseudoVMSGTU_VX_MF4 = 7009,
7034 PseudoVMSGTU_VX_MF4_MASK = 7010,
7035 PseudoVMSGTU_VX_MF8 = 7011,
7036 PseudoVMSGTU_VX_MF8_MASK = 7012,
7037 PseudoVMSGT_VI_M1 = 7013,
7038 PseudoVMSGT_VI_M1_MASK = 7014,
7039 PseudoVMSGT_VI_M2 = 7015,
7040 PseudoVMSGT_VI_M2_MASK = 7016,
7041 PseudoVMSGT_VI_M4 = 7017,
7042 PseudoVMSGT_VI_M4_MASK = 7018,
7043 PseudoVMSGT_VI_M8 = 7019,
7044 PseudoVMSGT_VI_M8_MASK = 7020,
7045 PseudoVMSGT_VI_MF2 = 7021,
7046 PseudoVMSGT_VI_MF2_MASK = 7022,
7047 PseudoVMSGT_VI_MF4 = 7023,
7048 PseudoVMSGT_VI_MF4_MASK = 7024,
7049 PseudoVMSGT_VI_MF8 = 7025,
7050 PseudoVMSGT_VI_MF8_MASK = 7026,
7051 PseudoVMSGT_VX_M1 = 7027,
7052 PseudoVMSGT_VX_M1_MASK = 7028,
7053 PseudoVMSGT_VX_M2 = 7029,
7054 PseudoVMSGT_VX_M2_MASK = 7030,
7055 PseudoVMSGT_VX_M4 = 7031,
7056 PseudoVMSGT_VX_M4_MASK = 7032,
7057 PseudoVMSGT_VX_M8 = 7033,
7058 PseudoVMSGT_VX_M8_MASK = 7034,
7059 PseudoVMSGT_VX_MF2 = 7035,
7060 PseudoVMSGT_VX_MF2_MASK = 7036,
7061 PseudoVMSGT_VX_MF4 = 7037,
7062 PseudoVMSGT_VX_MF4_MASK = 7038,
7063 PseudoVMSGT_VX_MF8 = 7039,
7064 PseudoVMSGT_VX_MF8_MASK = 7040,
7065 PseudoVMSIF_M_B1 = 7041,
7066 PseudoVMSIF_M_B16 = 7042,
7067 PseudoVMSIF_M_B16_MASK = 7043,
7068 PseudoVMSIF_M_B1_MASK = 7044,
7069 PseudoVMSIF_M_B2 = 7045,
7070 PseudoVMSIF_M_B2_MASK = 7046,
7071 PseudoVMSIF_M_B32 = 7047,
7072 PseudoVMSIF_M_B32_MASK = 7048,
7073 PseudoVMSIF_M_B4 = 7049,
7074 PseudoVMSIF_M_B4_MASK = 7050,
7075 PseudoVMSIF_M_B64 = 7051,
7076 PseudoVMSIF_M_B64_MASK = 7052,
7077 PseudoVMSIF_M_B8 = 7053,
7078 PseudoVMSIF_M_B8_MASK = 7054,
7079 PseudoVMSLEU_VI_M1 = 7055,
7080 PseudoVMSLEU_VI_M1_MASK = 7056,
7081 PseudoVMSLEU_VI_M2 = 7057,
7082 PseudoVMSLEU_VI_M2_MASK = 7058,
7083 PseudoVMSLEU_VI_M4 = 7059,
7084 PseudoVMSLEU_VI_M4_MASK = 7060,
7085 PseudoVMSLEU_VI_M8 = 7061,
7086 PseudoVMSLEU_VI_M8_MASK = 7062,
7087 PseudoVMSLEU_VI_MF2 = 7063,
7088 PseudoVMSLEU_VI_MF2_MASK = 7064,
7089 PseudoVMSLEU_VI_MF4 = 7065,
7090 PseudoVMSLEU_VI_MF4_MASK = 7066,
7091 PseudoVMSLEU_VI_MF8 = 7067,
7092 PseudoVMSLEU_VI_MF8_MASK = 7068,
7093 PseudoVMSLEU_VV_M1 = 7069,
7094 PseudoVMSLEU_VV_M1_MASK = 7070,
7095 PseudoVMSLEU_VV_M2 = 7071,
7096 PseudoVMSLEU_VV_M2_MASK = 7072,
7097 PseudoVMSLEU_VV_M4 = 7073,
7098 PseudoVMSLEU_VV_M4_MASK = 7074,
7099 PseudoVMSLEU_VV_M8 = 7075,
7100 PseudoVMSLEU_VV_M8_MASK = 7076,
7101 PseudoVMSLEU_VV_MF2 = 7077,
7102 PseudoVMSLEU_VV_MF2_MASK = 7078,
7103 PseudoVMSLEU_VV_MF4 = 7079,
7104 PseudoVMSLEU_VV_MF4_MASK = 7080,
7105 PseudoVMSLEU_VV_MF8 = 7081,
7106 PseudoVMSLEU_VV_MF8_MASK = 7082,
7107 PseudoVMSLEU_VX_M1 = 7083,
7108 PseudoVMSLEU_VX_M1_MASK = 7084,
7109 PseudoVMSLEU_VX_M2 = 7085,
7110 PseudoVMSLEU_VX_M2_MASK = 7086,
7111 PseudoVMSLEU_VX_M4 = 7087,
7112 PseudoVMSLEU_VX_M4_MASK = 7088,
7113 PseudoVMSLEU_VX_M8 = 7089,
7114 PseudoVMSLEU_VX_M8_MASK = 7090,
7115 PseudoVMSLEU_VX_MF2 = 7091,
7116 PseudoVMSLEU_VX_MF2_MASK = 7092,
7117 PseudoVMSLEU_VX_MF4 = 7093,
7118 PseudoVMSLEU_VX_MF4_MASK = 7094,
7119 PseudoVMSLEU_VX_MF8 = 7095,
7120 PseudoVMSLEU_VX_MF8_MASK = 7096,
7121 PseudoVMSLE_VI_M1 = 7097,
7122 PseudoVMSLE_VI_M1_MASK = 7098,
7123 PseudoVMSLE_VI_M2 = 7099,
7124 PseudoVMSLE_VI_M2_MASK = 7100,
7125 PseudoVMSLE_VI_M4 = 7101,
7126 PseudoVMSLE_VI_M4_MASK = 7102,
7127 PseudoVMSLE_VI_M8 = 7103,
7128 PseudoVMSLE_VI_M8_MASK = 7104,
7129 PseudoVMSLE_VI_MF2 = 7105,
7130 PseudoVMSLE_VI_MF2_MASK = 7106,
7131 PseudoVMSLE_VI_MF4 = 7107,
7132 PseudoVMSLE_VI_MF4_MASK = 7108,
7133 PseudoVMSLE_VI_MF8 = 7109,
7134 PseudoVMSLE_VI_MF8_MASK = 7110,
7135 PseudoVMSLE_VV_M1 = 7111,
7136 PseudoVMSLE_VV_M1_MASK = 7112,
7137 PseudoVMSLE_VV_M2 = 7113,
7138 PseudoVMSLE_VV_M2_MASK = 7114,
7139 PseudoVMSLE_VV_M4 = 7115,
7140 PseudoVMSLE_VV_M4_MASK = 7116,
7141 PseudoVMSLE_VV_M8 = 7117,
7142 PseudoVMSLE_VV_M8_MASK = 7118,
7143 PseudoVMSLE_VV_MF2 = 7119,
7144 PseudoVMSLE_VV_MF2_MASK = 7120,
7145 PseudoVMSLE_VV_MF4 = 7121,
7146 PseudoVMSLE_VV_MF4_MASK = 7122,
7147 PseudoVMSLE_VV_MF8 = 7123,
7148 PseudoVMSLE_VV_MF8_MASK = 7124,
7149 PseudoVMSLE_VX_M1 = 7125,
7150 PseudoVMSLE_VX_M1_MASK = 7126,
7151 PseudoVMSLE_VX_M2 = 7127,
7152 PseudoVMSLE_VX_M2_MASK = 7128,
7153 PseudoVMSLE_VX_M4 = 7129,
7154 PseudoVMSLE_VX_M4_MASK = 7130,
7155 PseudoVMSLE_VX_M8 = 7131,
7156 PseudoVMSLE_VX_M8_MASK = 7132,
7157 PseudoVMSLE_VX_MF2 = 7133,
7158 PseudoVMSLE_VX_MF2_MASK = 7134,
7159 PseudoVMSLE_VX_MF4 = 7135,
7160 PseudoVMSLE_VX_MF4_MASK = 7136,
7161 PseudoVMSLE_VX_MF8 = 7137,
7162 PseudoVMSLE_VX_MF8_MASK = 7138,
7163 PseudoVMSLTU_VI = 7139,
7164 PseudoVMSLTU_VV_M1 = 7140,
7165 PseudoVMSLTU_VV_M1_MASK = 7141,
7166 PseudoVMSLTU_VV_M2 = 7142,
7167 PseudoVMSLTU_VV_M2_MASK = 7143,
7168 PseudoVMSLTU_VV_M4 = 7144,
7169 PseudoVMSLTU_VV_M4_MASK = 7145,
7170 PseudoVMSLTU_VV_M8 = 7146,
7171 PseudoVMSLTU_VV_M8_MASK = 7147,
7172 PseudoVMSLTU_VV_MF2 = 7148,
7173 PseudoVMSLTU_VV_MF2_MASK = 7149,
7174 PseudoVMSLTU_VV_MF4 = 7150,
7175 PseudoVMSLTU_VV_MF4_MASK = 7151,
7176 PseudoVMSLTU_VV_MF8 = 7152,
7177 PseudoVMSLTU_VV_MF8_MASK = 7153,
7178 PseudoVMSLTU_VX_M1 = 7154,
7179 PseudoVMSLTU_VX_M1_MASK = 7155,
7180 PseudoVMSLTU_VX_M2 = 7156,
7181 PseudoVMSLTU_VX_M2_MASK = 7157,
7182 PseudoVMSLTU_VX_M4 = 7158,
7183 PseudoVMSLTU_VX_M4_MASK = 7159,
7184 PseudoVMSLTU_VX_M8 = 7160,
7185 PseudoVMSLTU_VX_M8_MASK = 7161,
7186 PseudoVMSLTU_VX_MF2 = 7162,
7187 PseudoVMSLTU_VX_MF2_MASK = 7163,
7188 PseudoVMSLTU_VX_MF4 = 7164,
7189 PseudoVMSLTU_VX_MF4_MASK = 7165,
7190 PseudoVMSLTU_VX_MF8 = 7166,
7191 PseudoVMSLTU_VX_MF8_MASK = 7167,
7192 PseudoVMSLT_VI = 7168,
7193 PseudoVMSLT_VV_M1 = 7169,
7194 PseudoVMSLT_VV_M1_MASK = 7170,
7195 PseudoVMSLT_VV_M2 = 7171,
7196 PseudoVMSLT_VV_M2_MASK = 7172,
7197 PseudoVMSLT_VV_M4 = 7173,
7198 PseudoVMSLT_VV_M4_MASK = 7174,
7199 PseudoVMSLT_VV_M8 = 7175,
7200 PseudoVMSLT_VV_M8_MASK = 7176,
7201 PseudoVMSLT_VV_MF2 = 7177,
7202 PseudoVMSLT_VV_MF2_MASK = 7178,
7203 PseudoVMSLT_VV_MF4 = 7179,
7204 PseudoVMSLT_VV_MF4_MASK = 7180,
7205 PseudoVMSLT_VV_MF8 = 7181,
7206 PseudoVMSLT_VV_MF8_MASK = 7182,
7207 PseudoVMSLT_VX_M1 = 7183,
7208 PseudoVMSLT_VX_M1_MASK = 7184,
7209 PseudoVMSLT_VX_M2 = 7185,
7210 PseudoVMSLT_VX_M2_MASK = 7186,
7211 PseudoVMSLT_VX_M4 = 7187,
7212 PseudoVMSLT_VX_M4_MASK = 7188,
7213 PseudoVMSLT_VX_M8 = 7189,
7214 PseudoVMSLT_VX_M8_MASK = 7190,
7215 PseudoVMSLT_VX_MF2 = 7191,
7216 PseudoVMSLT_VX_MF2_MASK = 7192,
7217 PseudoVMSLT_VX_MF4 = 7193,
7218 PseudoVMSLT_VX_MF4_MASK = 7194,
7219 PseudoVMSLT_VX_MF8 = 7195,
7220 PseudoVMSLT_VX_MF8_MASK = 7196,
7221 PseudoVMSNE_VI_M1 = 7197,
7222 PseudoVMSNE_VI_M1_MASK = 7198,
7223 PseudoVMSNE_VI_M2 = 7199,
7224 PseudoVMSNE_VI_M2_MASK = 7200,
7225 PseudoVMSNE_VI_M4 = 7201,
7226 PseudoVMSNE_VI_M4_MASK = 7202,
7227 PseudoVMSNE_VI_M8 = 7203,
7228 PseudoVMSNE_VI_M8_MASK = 7204,
7229 PseudoVMSNE_VI_MF2 = 7205,
7230 PseudoVMSNE_VI_MF2_MASK = 7206,
7231 PseudoVMSNE_VI_MF4 = 7207,
7232 PseudoVMSNE_VI_MF4_MASK = 7208,
7233 PseudoVMSNE_VI_MF8 = 7209,
7234 PseudoVMSNE_VI_MF8_MASK = 7210,
7235 PseudoVMSNE_VV_M1 = 7211,
7236 PseudoVMSNE_VV_M1_MASK = 7212,
7237 PseudoVMSNE_VV_M2 = 7213,
7238 PseudoVMSNE_VV_M2_MASK = 7214,
7239 PseudoVMSNE_VV_M4 = 7215,
7240 PseudoVMSNE_VV_M4_MASK = 7216,
7241 PseudoVMSNE_VV_M8 = 7217,
7242 PseudoVMSNE_VV_M8_MASK = 7218,
7243 PseudoVMSNE_VV_MF2 = 7219,
7244 PseudoVMSNE_VV_MF2_MASK = 7220,
7245 PseudoVMSNE_VV_MF4 = 7221,
7246 PseudoVMSNE_VV_MF4_MASK = 7222,
7247 PseudoVMSNE_VV_MF8 = 7223,
7248 PseudoVMSNE_VV_MF8_MASK = 7224,
7249 PseudoVMSNE_VX_M1 = 7225,
7250 PseudoVMSNE_VX_M1_MASK = 7226,
7251 PseudoVMSNE_VX_M2 = 7227,
7252 PseudoVMSNE_VX_M2_MASK = 7228,
7253 PseudoVMSNE_VX_M4 = 7229,
7254 PseudoVMSNE_VX_M4_MASK = 7230,
7255 PseudoVMSNE_VX_M8 = 7231,
7256 PseudoVMSNE_VX_M8_MASK = 7232,
7257 PseudoVMSNE_VX_MF2 = 7233,
7258 PseudoVMSNE_VX_MF2_MASK = 7234,
7259 PseudoVMSNE_VX_MF4 = 7235,
7260 PseudoVMSNE_VX_MF4_MASK = 7236,
7261 PseudoVMSNE_VX_MF8 = 7237,
7262 PseudoVMSNE_VX_MF8_MASK = 7238,
7263 PseudoVMSOF_M_B1 = 7239,
7264 PseudoVMSOF_M_B16 = 7240,
7265 PseudoVMSOF_M_B16_MASK = 7241,
7266 PseudoVMSOF_M_B1_MASK = 7242,
7267 PseudoVMSOF_M_B2 = 7243,
7268 PseudoVMSOF_M_B2_MASK = 7244,
7269 PseudoVMSOF_M_B32 = 7245,
7270 PseudoVMSOF_M_B32_MASK = 7246,
7271 PseudoVMSOF_M_B4 = 7247,
7272 PseudoVMSOF_M_B4_MASK = 7248,
7273 PseudoVMSOF_M_B64 = 7249,
7274 PseudoVMSOF_M_B64_MASK = 7250,
7275 PseudoVMSOF_M_B8 = 7251,
7276 PseudoVMSOF_M_B8_MASK = 7252,
7277 PseudoVMULHSU_VV_M1 = 7253,
7278 PseudoVMULHSU_VV_M1_MASK = 7254,
7279 PseudoVMULHSU_VV_M2 = 7255,
7280 PseudoVMULHSU_VV_M2_MASK = 7256,
7281 PseudoVMULHSU_VV_M4 = 7257,
7282 PseudoVMULHSU_VV_M4_MASK = 7258,
7283 PseudoVMULHSU_VV_M8 = 7259,
7284 PseudoVMULHSU_VV_M8_MASK = 7260,
7285 PseudoVMULHSU_VV_MF2 = 7261,
7286 PseudoVMULHSU_VV_MF2_MASK = 7262,
7287 PseudoVMULHSU_VV_MF4 = 7263,
7288 PseudoVMULHSU_VV_MF4_MASK = 7264,
7289 PseudoVMULHSU_VV_MF8 = 7265,
7290 PseudoVMULHSU_VV_MF8_MASK = 7266,
7291 PseudoVMULHSU_VX_M1 = 7267,
7292 PseudoVMULHSU_VX_M1_MASK = 7268,
7293 PseudoVMULHSU_VX_M2 = 7269,
7294 PseudoVMULHSU_VX_M2_MASK = 7270,
7295 PseudoVMULHSU_VX_M4 = 7271,
7296 PseudoVMULHSU_VX_M4_MASK = 7272,
7297 PseudoVMULHSU_VX_M8 = 7273,
7298 PseudoVMULHSU_VX_M8_MASK = 7274,
7299 PseudoVMULHSU_VX_MF2 = 7275,
7300 PseudoVMULHSU_VX_MF2_MASK = 7276,
7301 PseudoVMULHSU_VX_MF4 = 7277,
7302 PseudoVMULHSU_VX_MF4_MASK = 7278,
7303 PseudoVMULHSU_VX_MF8 = 7279,
7304 PseudoVMULHSU_VX_MF8_MASK = 7280,
7305 PseudoVMULHU_VV_M1 = 7281,
7306 PseudoVMULHU_VV_M1_MASK = 7282,
7307 PseudoVMULHU_VV_M2 = 7283,
7308 PseudoVMULHU_VV_M2_MASK = 7284,
7309 PseudoVMULHU_VV_M4 = 7285,
7310 PseudoVMULHU_VV_M4_MASK = 7286,
7311 PseudoVMULHU_VV_M8 = 7287,
7312 PseudoVMULHU_VV_M8_MASK = 7288,
7313 PseudoVMULHU_VV_MF2 = 7289,
7314 PseudoVMULHU_VV_MF2_MASK = 7290,
7315 PseudoVMULHU_VV_MF4 = 7291,
7316 PseudoVMULHU_VV_MF4_MASK = 7292,
7317 PseudoVMULHU_VV_MF8 = 7293,
7318 PseudoVMULHU_VV_MF8_MASK = 7294,
7319 PseudoVMULHU_VX_M1 = 7295,
7320 PseudoVMULHU_VX_M1_MASK = 7296,
7321 PseudoVMULHU_VX_M2 = 7297,
7322 PseudoVMULHU_VX_M2_MASK = 7298,
7323 PseudoVMULHU_VX_M4 = 7299,
7324 PseudoVMULHU_VX_M4_MASK = 7300,
7325 PseudoVMULHU_VX_M8 = 7301,
7326 PseudoVMULHU_VX_M8_MASK = 7302,
7327 PseudoVMULHU_VX_MF2 = 7303,
7328 PseudoVMULHU_VX_MF2_MASK = 7304,
7329 PseudoVMULHU_VX_MF4 = 7305,
7330 PseudoVMULHU_VX_MF4_MASK = 7306,
7331 PseudoVMULHU_VX_MF8 = 7307,
7332 PseudoVMULHU_VX_MF8_MASK = 7308,
7333 PseudoVMULH_VV_M1 = 7309,
7334 PseudoVMULH_VV_M1_MASK = 7310,
7335 PseudoVMULH_VV_M2 = 7311,
7336 PseudoVMULH_VV_M2_MASK = 7312,
7337 PseudoVMULH_VV_M4 = 7313,
7338 PseudoVMULH_VV_M4_MASK = 7314,
7339 PseudoVMULH_VV_M8 = 7315,
7340 PseudoVMULH_VV_M8_MASK = 7316,
7341 PseudoVMULH_VV_MF2 = 7317,
7342 PseudoVMULH_VV_MF2_MASK = 7318,
7343 PseudoVMULH_VV_MF4 = 7319,
7344 PseudoVMULH_VV_MF4_MASK = 7320,
7345 PseudoVMULH_VV_MF8 = 7321,
7346 PseudoVMULH_VV_MF8_MASK = 7322,
7347 PseudoVMULH_VX_M1 = 7323,
7348 PseudoVMULH_VX_M1_MASK = 7324,
7349 PseudoVMULH_VX_M2 = 7325,
7350 PseudoVMULH_VX_M2_MASK = 7326,
7351 PseudoVMULH_VX_M4 = 7327,
7352 PseudoVMULH_VX_M4_MASK = 7328,
7353 PseudoVMULH_VX_M8 = 7329,
7354 PseudoVMULH_VX_M8_MASK = 7330,
7355 PseudoVMULH_VX_MF2 = 7331,
7356 PseudoVMULH_VX_MF2_MASK = 7332,
7357 PseudoVMULH_VX_MF4 = 7333,
7358 PseudoVMULH_VX_MF4_MASK = 7334,
7359 PseudoVMULH_VX_MF8 = 7335,
7360 PseudoVMULH_VX_MF8_MASK = 7336,
7361 PseudoVMUL_VV_M1 = 7337,
7362 PseudoVMUL_VV_M1_MASK = 7338,
7363 PseudoVMUL_VV_M2 = 7339,
7364 PseudoVMUL_VV_M2_MASK = 7340,
7365 PseudoVMUL_VV_M4 = 7341,
7366 PseudoVMUL_VV_M4_MASK = 7342,
7367 PseudoVMUL_VV_M8 = 7343,
7368 PseudoVMUL_VV_M8_MASK = 7344,
7369 PseudoVMUL_VV_MF2 = 7345,
7370 PseudoVMUL_VV_MF2_MASK = 7346,
7371 PseudoVMUL_VV_MF4 = 7347,
7372 PseudoVMUL_VV_MF4_MASK = 7348,
7373 PseudoVMUL_VV_MF8 = 7349,
7374 PseudoVMUL_VV_MF8_MASK = 7350,
7375 PseudoVMUL_VX_M1 = 7351,
7376 PseudoVMUL_VX_M1_MASK = 7352,
7377 PseudoVMUL_VX_M2 = 7353,
7378 PseudoVMUL_VX_M2_MASK = 7354,
7379 PseudoVMUL_VX_M4 = 7355,
7380 PseudoVMUL_VX_M4_MASK = 7356,
7381 PseudoVMUL_VX_M8 = 7357,
7382 PseudoVMUL_VX_M8_MASK = 7358,
7383 PseudoVMUL_VX_MF2 = 7359,
7384 PseudoVMUL_VX_MF2_MASK = 7360,
7385 PseudoVMUL_VX_MF4 = 7361,
7386 PseudoVMUL_VX_MF4_MASK = 7362,
7387 PseudoVMUL_VX_MF8 = 7363,
7388 PseudoVMUL_VX_MF8_MASK = 7364,
7389 PseudoVMV_S_X = 7365,
7390 PseudoVMV_V_I_M1 = 7366,
7391 PseudoVMV_V_I_M2 = 7367,
7392 PseudoVMV_V_I_M4 = 7368,
7393 PseudoVMV_V_I_M8 = 7369,
7394 PseudoVMV_V_I_MF2 = 7370,
7395 PseudoVMV_V_I_MF4 = 7371,
7396 PseudoVMV_V_I_MF8 = 7372,
7397 PseudoVMV_V_V_M1 = 7373,
7398 PseudoVMV_V_V_M2 = 7374,
7399 PseudoVMV_V_V_M4 = 7375,
7400 PseudoVMV_V_V_M8 = 7376,
7401 PseudoVMV_V_V_MF2 = 7377,
7402 PseudoVMV_V_V_MF4 = 7378,
7403 PseudoVMV_V_V_MF8 = 7379,
7404 PseudoVMV_V_X_M1 = 7380,
7405 PseudoVMV_V_X_M2 = 7381,
7406 PseudoVMV_V_X_M4 = 7382,
7407 PseudoVMV_V_X_M8 = 7383,
7408 PseudoVMV_V_X_MF2 = 7384,
7409 PseudoVMV_V_X_MF4 = 7385,
7410 PseudoVMV_V_X_MF8 = 7386,
7411 PseudoVMV_X_S = 7387,
7412 PseudoVMXNOR_MM_M1 = 7388,
7413 PseudoVMXNOR_MM_M2 = 7389,
7414 PseudoVMXNOR_MM_M4 = 7390,
7415 PseudoVMXNOR_MM_M8 = 7391,
7416 PseudoVMXNOR_MM_MF2 = 7392,
7417 PseudoVMXNOR_MM_MF4 = 7393,
7418 PseudoVMXNOR_MM_MF8 = 7394,
7419 PseudoVMXOR_MM_M1 = 7395,
7420 PseudoVMXOR_MM_M2 = 7396,
7421 PseudoVMXOR_MM_M4 = 7397,
7422 PseudoVMXOR_MM_M8 = 7398,
7423 PseudoVMXOR_MM_MF2 = 7399,
7424 PseudoVMXOR_MM_MF4 = 7400,
7425 PseudoVMXOR_MM_MF8 = 7401,
7426 PseudoVNCLIPU_WI_M1 = 7402,
7427 PseudoVNCLIPU_WI_M1_MASK = 7403,
7428 PseudoVNCLIPU_WI_M2 = 7404,
7429 PseudoVNCLIPU_WI_M2_MASK = 7405,
7430 PseudoVNCLIPU_WI_M4 = 7406,
7431 PseudoVNCLIPU_WI_M4_MASK = 7407,
7432 PseudoVNCLIPU_WI_MF2 = 7408,
7433 PseudoVNCLIPU_WI_MF2_MASK = 7409,
7434 PseudoVNCLIPU_WI_MF4 = 7410,
7435 PseudoVNCLIPU_WI_MF4_MASK = 7411,
7436 PseudoVNCLIPU_WI_MF8 = 7412,
7437 PseudoVNCLIPU_WI_MF8_MASK = 7413,
7438 PseudoVNCLIPU_WV_M1 = 7414,
7439 PseudoVNCLIPU_WV_M1_MASK = 7415,
7440 PseudoVNCLIPU_WV_M2 = 7416,
7441 PseudoVNCLIPU_WV_M2_MASK = 7417,
7442 PseudoVNCLIPU_WV_M4 = 7418,
7443 PseudoVNCLIPU_WV_M4_MASK = 7419,
7444 PseudoVNCLIPU_WV_MF2 = 7420,
7445 PseudoVNCLIPU_WV_MF2_MASK = 7421,
7446 PseudoVNCLIPU_WV_MF4 = 7422,
7447 PseudoVNCLIPU_WV_MF4_MASK = 7423,
7448 PseudoVNCLIPU_WV_MF8 = 7424,
7449 PseudoVNCLIPU_WV_MF8_MASK = 7425,
7450 PseudoVNCLIPU_WX_M1 = 7426,
7451 PseudoVNCLIPU_WX_M1_MASK = 7427,
7452 PseudoVNCLIPU_WX_M2 = 7428,
7453 PseudoVNCLIPU_WX_M2_MASK = 7429,
7454 PseudoVNCLIPU_WX_M4 = 7430,
7455 PseudoVNCLIPU_WX_M4_MASK = 7431,
7456 PseudoVNCLIPU_WX_MF2 = 7432,
7457 PseudoVNCLIPU_WX_MF2_MASK = 7433,
7458 PseudoVNCLIPU_WX_MF4 = 7434,
7459 PseudoVNCLIPU_WX_MF4_MASK = 7435,
7460 PseudoVNCLIPU_WX_MF8 = 7436,
7461 PseudoVNCLIPU_WX_MF8_MASK = 7437,
7462 PseudoVNCLIP_WI_M1 = 7438,
7463 PseudoVNCLIP_WI_M1_MASK = 7439,
7464 PseudoVNCLIP_WI_M2 = 7440,
7465 PseudoVNCLIP_WI_M2_MASK = 7441,
7466 PseudoVNCLIP_WI_M4 = 7442,
7467 PseudoVNCLIP_WI_M4_MASK = 7443,
7468 PseudoVNCLIP_WI_MF2 = 7444,
7469 PseudoVNCLIP_WI_MF2_MASK = 7445,
7470 PseudoVNCLIP_WI_MF4 = 7446,
7471 PseudoVNCLIP_WI_MF4_MASK = 7447,
7472 PseudoVNCLIP_WI_MF8 = 7448,
7473 PseudoVNCLIP_WI_MF8_MASK = 7449,
7474 PseudoVNCLIP_WV_M1 = 7450,
7475 PseudoVNCLIP_WV_M1_MASK = 7451,
7476 PseudoVNCLIP_WV_M2 = 7452,
7477 PseudoVNCLIP_WV_M2_MASK = 7453,
7478 PseudoVNCLIP_WV_M4 = 7454,
7479 PseudoVNCLIP_WV_M4_MASK = 7455,
7480 PseudoVNCLIP_WV_MF2 = 7456,
7481 PseudoVNCLIP_WV_MF2_MASK = 7457,
7482 PseudoVNCLIP_WV_MF4 = 7458,
7483 PseudoVNCLIP_WV_MF4_MASK = 7459,
7484 PseudoVNCLIP_WV_MF8 = 7460,
7485 PseudoVNCLIP_WV_MF8_MASK = 7461,
7486 PseudoVNCLIP_WX_M1 = 7462,
7487 PseudoVNCLIP_WX_M1_MASK = 7463,
7488 PseudoVNCLIP_WX_M2 = 7464,
7489 PseudoVNCLIP_WX_M2_MASK = 7465,
7490 PseudoVNCLIP_WX_M4 = 7466,
7491 PseudoVNCLIP_WX_M4_MASK = 7467,
7492 PseudoVNCLIP_WX_MF2 = 7468,
7493 PseudoVNCLIP_WX_MF2_MASK = 7469,
7494 PseudoVNCLIP_WX_MF4 = 7470,
7495 PseudoVNCLIP_WX_MF4_MASK = 7471,
7496 PseudoVNCLIP_WX_MF8 = 7472,
7497 PseudoVNCLIP_WX_MF8_MASK = 7473,
7498 PseudoVNMSAC_VV_M1 = 7474,
7499 PseudoVNMSAC_VV_M1_MASK = 7475,
7500 PseudoVNMSAC_VV_M2 = 7476,
7501 PseudoVNMSAC_VV_M2_MASK = 7477,
7502 PseudoVNMSAC_VV_M4 = 7478,
7503 PseudoVNMSAC_VV_M4_MASK = 7479,
7504 PseudoVNMSAC_VV_M8 = 7480,
7505 PseudoVNMSAC_VV_M8_MASK = 7481,
7506 PseudoVNMSAC_VV_MF2 = 7482,
7507 PseudoVNMSAC_VV_MF2_MASK = 7483,
7508 PseudoVNMSAC_VV_MF4 = 7484,
7509 PseudoVNMSAC_VV_MF4_MASK = 7485,
7510 PseudoVNMSAC_VV_MF8 = 7486,
7511 PseudoVNMSAC_VV_MF8_MASK = 7487,
7512 PseudoVNMSAC_VX_M1 = 7488,
7513 PseudoVNMSAC_VX_M1_MASK = 7489,
7514 PseudoVNMSAC_VX_M2 = 7490,
7515 PseudoVNMSAC_VX_M2_MASK = 7491,
7516 PseudoVNMSAC_VX_M4 = 7492,
7517 PseudoVNMSAC_VX_M4_MASK = 7493,
7518 PseudoVNMSAC_VX_M8 = 7494,
7519 PseudoVNMSAC_VX_M8_MASK = 7495,
7520 PseudoVNMSAC_VX_MF2 = 7496,
7521 PseudoVNMSAC_VX_MF2_MASK = 7497,
7522 PseudoVNMSAC_VX_MF4 = 7498,
7523 PseudoVNMSAC_VX_MF4_MASK = 7499,
7524 PseudoVNMSAC_VX_MF8 = 7500,
7525 PseudoVNMSAC_VX_MF8_MASK = 7501,
7526 PseudoVNMSUB_VV_M1 = 7502,
7527 PseudoVNMSUB_VV_M1_MASK = 7503,
7528 PseudoVNMSUB_VV_M2 = 7504,
7529 PseudoVNMSUB_VV_M2_MASK = 7505,
7530 PseudoVNMSUB_VV_M4 = 7506,
7531 PseudoVNMSUB_VV_M4_MASK = 7507,
7532 PseudoVNMSUB_VV_M8 = 7508,
7533 PseudoVNMSUB_VV_M8_MASK = 7509,
7534 PseudoVNMSUB_VV_MF2 = 7510,
7535 PseudoVNMSUB_VV_MF2_MASK = 7511,
7536 PseudoVNMSUB_VV_MF4 = 7512,
7537 PseudoVNMSUB_VV_MF4_MASK = 7513,
7538 PseudoVNMSUB_VV_MF8 = 7514,
7539 PseudoVNMSUB_VV_MF8_MASK = 7515,
7540 PseudoVNMSUB_VX_M1 = 7516,
7541 PseudoVNMSUB_VX_M1_MASK = 7517,
7542 PseudoVNMSUB_VX_M2 = 7518,
7543 PseudoVNMSUB_VX_M2_MASK = 7519,
7544 PseudoVNMSUB_VX_M4 = 7520,
7545 PseudoVNMSUB_VX_M4_MASK = 7521,
7546 PseudoVNMSUB_VX_M8 = 7522,
7547 PseudoVNMSUB_VX_M8_MASK = 7523,
7548 PseudoVNMSUB_VX_MF2 = 7524,
7549 PseudoVNMSUB_VX_MF2_MASK = 7525,
7550 PseudoVNMSUB_VX_MF4 = 7526,
7551 PseudoVNMSUB_VX_MF4_MASK = 7527,
7552 PseudoVNMSUB_VX_MF8 = 7528,
7553 PseudoVNMSUB_VX_MF8_MASK = 7529,
7554 PseudoVNSRA_WI_M1 = 7530,
7555 PseudoVNSRA_WI_M1_MASK = 7531,
7556 PseudoVNSRA_WI_M2 = 7532,
7557 PseudoVNSRA_WI_M2_MASK = 7533,
7558 PseudoVNSRA_WI_M4 = 7534,
7559 PseudoVNSRA_WI_M4_MASK = 7535,
7560 PseudoVNSRA_WI_MF2 = 7536,
7561 PseudoVNSRA_WI_MF2_MASK = 7537,
7562 PseudoVNSRA_WI_MF4 = 7538,
7563 PseudoVNSRA_WI_MF4_MASK = 7539,
7564 PseudoVNSRA_WI_MF8 = 7540,
7565 PseudoVNSRA_WI_MF8_MASK = 7541,
7566 PseudoVNSRA_WV_M1 = 7542,
7567 PseudoVNSRA_WV_M1_MASK = 7543,
7568 PseudoVNSRA_WV_M2 = 7544,
7569 PseudoVNSRA_WV_M2_MASK = 7545,
7570 PseudoVNSRA_WV_M4 = 7546,
7571 PseudoVNSRA_WV_M4_MASK = 7547,
7572 PseudoVNSRA_WV_MF2 = 7548,
7573 PseudoVNSRA_WV_MF2_MASK = 7549,
7574 PseudoVNSRA_WV_MF4 = 7550,
7575 PseudoVNSRA_WV_MF4_MASK = 7551,
7576 PseudoVNSRA_WV_MF8 = 7552,
7577 PseudoVNSRA_WV_MF8_MASK = 7553,
7578 PseudoVNSRA_WX_M1 = 7554,
7579 PseudoVNSRA_WX_M1_MASK = 7555,
7580 PseudoVNSRA_WX_M2 = 7556,
7581 PseudoVNSRA_WX_M2_MASK = 7557,
7582 PseudoVNSRA_WX_M4 = 7558,
7583 PseudoVNSRA_WX_M4_MASK = 7559,
7584 PseudoVNSRA_WX_MF2 = 7560,
7585 PseudoVNSRA_WX_MF2_MASK = 7561,
7586 PseudoVNSRA_WX_MF4 = 7562,
7587 PseudoVNSRA_WX_MF4_MASK = 7563,
7588 PseudoVNSRA_WX_MF8 = 7564,
7589 PseudoVNSRA_WX_MF8_MASK = 7565,
7590 PseudoVNSRL_WI_M1 = 7566,
7591 PseudoVNSRL_WI_M1_MASK = 7567,
7592 PseudoVNSRL_WI_M2 = 7568,
7593 PseudoVNSRL_WI_M2_MASK = 7569,
7594 PseudoVNSRL_WI_M4 = 7570,
7595 PseudoVNSRL_WI_M4_MASK = 7571,
7596 PseudoVNSRL_WI_MF2 = 7572,
7597 PseudoVNSRL_WI_MF2_MASK = 7573,
7598 PseudoVNSRL_WI_MF4 = 7574,
7599 PseudoVNSRL_WI_MF4_MASK = 7575,
7600 PseudoVNSRL_WI_MF8 = 7576,
7601 PseudoVNSRL_WI_MF8_MASK = 7577,
7602 PseudoVNSRL_WV_M1 = 7578,
7603 PseudoVNSRL_WV_M1_MASK = 7579,
7604 PseudoVNSRL_WV_M2 = 7580,
7605 PseudoVNSRL_WV_M2_MASK = 7581,
7606 PseudoVNSRL_WV_M4 = 7582,
7607 PseudoVNSRL_WV_M4_MASK = 7583,
7608 PseudoVNSRL_WV_MF2 = 7584,
7609 PseudoVNSRL_WV_MF2_MASK = 7585,
7610 PseudoVNSRL_WV_MF4 = 7586,
7611 PseudoVNSRL_WV_MF4_MASK = 7587,
7612 PseudoVNSRL_WV_MF8 = 7588,
7613 PseudoVNSRL_WV_MF8_MASK = 7589,
7614 PseudoVNSRL_WX_M1 = 7590,
7615 PseudoVNSRL_WX_M1_MASK = 7591,
7616 PseudoVNSRL_WX_M2 = 7592,
7617 PseudoVNSRL_WX_M2_MASK = 7593,
7618 PseudoVNSRL_WX_M4 = 7594,
7619 PseudoVNSRL_WX_M4_MASK = 7595,
7620 PseudoVNSRL_WX_MF2 = 7596,
7621 PseudoVNSRL_WX_MF2_MASK = 7597,
7622 PseudoVNSRL_WX_MF4 = 7598,
7623 PseudoVNSRL_WX_MF4_MASK = 7599,
7624 PseudoVNSRL_WX_MF8 = 7600,
7625 PseudoVNSRL_WX_MF8_MASK = 7601,
7626 PseudoVOR_VI_M1 = 7602,
7627 PseudoVOR_VI_M1_MASK = 7603,
7628 PseudoVOR_VI_M2 = 7604,
7629 PseudoVOR_VI_M2_MASK = 7605,
7630 PseudoVOR_VI_M4 = 7606,
7631 PseudoVOR_VI_M4_MASK = 7607,
7632 PseudoVOR_VI_M8 = 7608,
7633 PseudoVOR_VI_M8_MASK = 7609,
7634 PseudoVOR_VI_MF2 = 7610,
7635 PseudoVOR_VI_MF2_MASK = 7611,
7636 PseudoVOR_VI_MF4 = 7612,
7637 PseudoVOR_VI_MF4_MASK = 7613,
7638 PseudoVOR_VI_MF8 = 7614,
7639 PseudoVOR_VI_MF8_MASK = 7615,
7640 PseudoVOR_VV_M1 = 7616,
7641 PseudoVOR_VV_M1_MASK = 7617,
7642 PseudoVOR_VV_M2 = 7618,
7643 PseudoVOR_VV_M2_MASK = 7619,
7644 PseudoVOR_VV_M4 = 7620,
7645 PseudoVOR_VV_M4_MASK = 7621,
7646 PseudoVOR_VV_M8 = 7622,
7647 PseudoVOR_VV_M8_MASK = 7623,
7648 PseudoVOR_VV_MF2 = 7624,
7649 PseudoVOR_VV_MF2_MASK = 7625,
7650 PseudoVOR_VV_MF4 = 7626,
7651 PseudoVOR_VV_MF4_MASK = 7627,
7652 PseudoVOR_VV_MF8 = 7628,
7653 PseudoVOR_VV_MF8_MASK = 7629,
7654 PseudoVOR_VX_M1 = 7630,
7655 PseudoVOR_VX_M1_MASK = 7631,
7656 PseudoVOR_VX_M2 = 7632,
7657 PseudoVOR_VX_M2_MASK = 7633,
7658 PseudoVOR_VX_M4 = 7634,
7659 PseudoVOR_VX_M4_MASK = 7635,
7660 PseudoVOR_VX_M8 = 7636,
7661 PseudoVOR_VX_M8_MASK = 7637,
7662 PseudoVOR_VX_MF2 = 7638,
7663 PseudoVOR_VX_MF2_MASK = 7639,
7664 PseudoVOR_VX_MF4 = 7640,
7665 PseudoVOR_VX_MF4_MASK = 7641,
7666 PseudoVOR_VX_MF8 = 7642,
7667 PseudoVOR_VX_MF8_MASK = 7643,
7668 PseudoVQMACCSU_2x8x2_M1 = 7644,
7669 PseudoVQMACCSU_2x8x2_M2 = 7645,
7670 PseudoVQMACCSU_2x8x2_M4 = 7646,
7671 PseudoVQMACCSU_2x8x2_M8 = 7647,
7672 PseudoVQMACCSU_4x8x4_M1 = 7648,
7673 PseudoVQMACCSU_4x8x4_M2 = 7649,
7674 PseudoVQMACCSU_4x8x4_M4 = 7650,
7675 PseudoVQMACCSU_4x8x4_MF2 = 7651,
7676 PseudoVQMACCUS_2x8x2_M1 = 7652,
7677 PseudoVQMACCUS_2x8x2_M2 = 7653,
7678 PseudoVQMACCUS_2x8x2_M4 = 7654,
7679 PseudoVQMACCUS_2x8x2_M8 = 7655,
7680 PseudoVQMACCUS_4x8x4_M1 = 7656,
7681 PseudoVQMACCUS_4x8x4_M2 = 7657,
7682 PseudoVQMACCUS_4x8x4_M4 = 7658,
7683 PseudoVQMACCUS_4x8x4_MF2 = 7659,
7684 PseudoVQMACCU_2x8x2_M1 = 7660,
7685 PseudoVQMACCU_2x8x2_M2 = 7661,
7686 PseudoVQMACCU_2x8x2_M4 = 7662,
7687 PseudoVQMACCU_2x8x2_M8 = 7663,
7688 PseudoVQMACCU_4x8x4_M1 = 7664,
7689 PseudoVQMACCU_4x8x4_M2 = 7665,
7690 PseudoVQMACCU_4x8x4_M4 = 7666,
7691 PseudoVQMACCU_4x8x4_MF2 = 7667,
7692 PseudoVQMACC_2x8x2_M1 = 7668,
7693 PseudoVQMACC_2x8x2_M2 = 7669,
7694 PseudoVQMACC_2x8x2_M4 = 7670,
7695 PseudoVQMACC_2x8x2_M8 = 7671,
7696 PseudoVQMACC_4x8x4_M1 = 7672,
7697 PseudoVQMACC_4x8x4_M2 = 7673,
7698 PseudoVQMACC_4x8x4_M4 = 7674,
7699 PseudoVQMACC_4x8x4_MF2 = 7675,
7700 PseudoVREDAND_VS_M1_E16 = 7676,
7701 PseudoVREDAND_VS_M1_E16_MASK = 7677,
7702 PseudoVREDAND_VS_M1_E32 = 7678,
7703 PseudoVREDAND_VS_M1_E32_MASK = 7679,
7704 PseudoVREDAND_VS_M1_E64 = 7680,
7705 PseudoVREDAND_VS_M1_E64_MASK = 7681,
7706 PseudoVREDAND_VS_M1_E8 = 7682,
7707 PseudoVREDAND_VS_M1_E8_MASK = 7683,
7708 PseudoVREDAND_VS_M2_E16 = 7684,
7709 PseudoVREDAND_VS_M2_E16_MASK = 7685,
7710 PseudoVREDAND_VS_M2_E32 = 7686,
7711 PseudoVREDAND_VS_M2_E32_MASK = 7687,
7712 PseudoVREDAND_VS_M2_E64 = 7688,
7713 PseudoVREDAND_VS_M2_E64_MASK = 7689,
7714 PseudoVREDAND_VS_M2_E8 = 7690,
7715 PseudoVREDAND_VS_M2_E8_MASK = 7691,
7716 PseudoVREDAND_VS_M4_E16 = 7692,
7717 PseudoVREDAND_VS_M4_E16_MASK = 7693,
7718 PseudoVREDAND_VS_M4_E32 = 7694,
7719 PseudoVREDAND_VS_M4_E32_MASK = 7695,
7720 PseudoVREDAND_VS_M4_E64 = 7696,
7721 PseudoVREDAND_VS_M4_E64_MASK = 7697,
7722 PseudoVREDAND_VS_M4_E8 = 7698,
7723 PseudoVREDAND_VS_M4_E8_MASK = 7699,
7724 PseudoVREDAND_VS_M8_E16 = 7700,
7725 PseudoVREDAND_VS_M8_E16_MASK = 7701,
7726 PseudoVREDAND_VS_M8_E32 = 7702,
7727 PseudoVREDAND_VS_M8_E32_MASK = 7703,
7728 PseudoVREDAND_VS_M8_E64 = 7704,
7729 PseudoVREDAND_VS_M8_E64_MASK = 7705,
7730 PseudoVREDAND_VS_M8_E8 = 7706,
7731 PseudoVREDAND_VS_M8_E8_MASK = 7707,
7732 PseudoVREDAND_VS_MF2_E16 = 7708,
7733 PseudoVREDAND_VS_MF2_E16_MASK = 7709,
7734 PseudoVREDAND_VS_MF2_E32 = 7710,
7735 PseudoVREDAND_VS_MF2_E32_MASK = 7711,
7736 PseudoVREDAND_VS_MF2_E8 = 7712,
7737 PseudoVREDAND_VS_MF2_E8_MASK = 7713,
7738 PseudoVREDAND_VS_MF4_E16 = 7714,
7739 PseudoVREDAND_VS_MF4_E16_MASK = 7715,
7740 PseudoVREDAND_VS_MF4_E8 = 7716,
7741 PseudoVREDAND_VS_MF4_E8_MASK = 7717,
7742 PseudoVREDAND_VS_MF8_E8 = 7718,
7743 PseudoVREDAND_VS_MF8_E8_MASK = 7719,
7744 PseudoVREDMAXU_VS_M1_E16 = 7720,
7745 PseudoVREDMAXU_VS_M1_E16_MASK = 7721,
7746 PseudoVREDMAXU_VS_M1_E32 = 7722,
7747 PseudoVREDMAXU_VS_M1_E32_MASK = 7723,
7748 PseudoVREDMAXU_VS_M1_E64 = 7724,
7749 PseudoVREDMAXU_VS_M1_E64_MASK = 7725,
7750 PseudoVREDMAXU_VS_M1_E8 = 7726,
7751 PseudoVREDMAXU_VS_M1_E8_MASK = 7727,
7752 PseudoVREDMAXU_VS_M2_E16 = 7728,
7753 PseudoVREDMAXU_VS_M2_E16_MASK = 7729,
7754 PseudoVREDMAXU_VS_M2_E32 = 7730,
7755 PseudoVREDMAXU_VS_M2_E32_MASK = 7731,
7756 PseudoVREDMAXU_VS_M2_E64 = 7732,
7757 PseudoVREDMAXU_VS_M2_E64_MASK = 7733,
7758 PseudoVREDMAXU_VS_M2_E8 = 7734,
7759 PseudoVREDMAXU_VS_M2_E8_MASK = 7735,
7760 PseudoVREDMAXU_VS_M4_E16 = 7736,
7761 PseudoVREDMAXU_VS_M4_E16_MASK = 7737,
7762 PseudoVREDMAXU_VS_M4_E32 = 7738,
7763 PseudoVREDMAXU_VS_M4_E32_MASK = 7739,
7764 PseudoVREDMAXU_VS_M4_E64 = 7740,
7765 PseudoVREDMAXU_VS_M4_E64_MASK = 7741,
7766 PseudoVREDMAXU_VS_M4_E8 = 7742,
7767 PseudoVREDMAXU_VS_M4_E8_MASK = 7743,
7768 PseudoVREDMAXU_VS_M8_E16 = 7744,
7769 PseudoVREDMAXU_VS_M8_E16_MASK = 7745,
7770 PseudoVREDMAXU_VS_M8_E32 = 7746,
7771 PseudoVREDMAXU_VS_M8_E32_MASK = 7747,
7772 PseudoVREDMAXU_VS_M8_E64 = 7748,
7773 PseudoVREDMAXU_VS_M8_E64_MASK = 7749,
7774 PseudoVREDMAXU_VS_M8_E8 = 7750,
7775 PseudoVREDMAXU_VS_M8_E8_MASK = 7751,
7776 PseudoVREDMAXU_VS_MF2_E16 = 7752,
7777 PseudoVREDMAXU_VS_MF2_E16_MASK = 7753,
7778 PseudoVREDMAXU_VS_MF2_E32 = 7754,
7779 PseudoVREDMAXU_VS_MF2_E32_MASK = 7755,
7780 PseudoVREDMAXU_VS_MF2_E8 = 7756,
7781 PseudoVREDMAXU_VS_MF2_E8_MASK = 7757,
7782 PseudoVREDMAXU_VS_MF4_E16 = 7758,
7783 PseudoVREDMAXU_VS_MF4_E16_MASK = 7759,
7784 PseudoVREDMAXU_VS_MF4_E8 = 7760,
7785 PseudoVREDMAXU_VS_MF4_E8_MASK = 7761,
7786 PseudoVREDMAXU_VS_MF8_E8 = 7762,
7787 PseudoVREDMAXU_VS_MF8_E8_MASK = 7763,
7788 PseudoVREDMAX_VS_M1_E16 = 7764,
7789 PseudoVREDMAX_VS_M1_E16_MASK = 7765,
7790 PseudoVREDMAX_VS_M1_E32 = 7766,
7791 PseudoVREDMAX_VS_M1_E32_MASK = 7767,
7792 PseudoVREDMAX_VS_M1_E64 = 7768,
7793 PseudoVREDMAX_VS_M1_E64_MASK = 7769,
7794 PseudoVREDMAX_VS_M1_E8 = 7770,
7795 PseudoVREDMAX_VS_M1_E8_MASK = 7771,
7796 PseudoVREDMAX_VS_M2_E16 = 7772,
7797 PseudoVREDMAX_VS_M2_E16_MASK = 7773,
7798 PseudoVREDMAX_VS_M2_E32 = 7774,
7799 PseudoVREDMAX_VS_M2_E32_MASK = 7775,
7800 PseudoVREDMAX_VS_M2_E64 = 7776,
7801 PseudoVREDMAX_VS_M2_E64_MASK = 7777,
7802 PseudoVREDMAX_VS_M2_E8 = 7778,
7803 PseudoVREDMAX_VS_M2_E8_MASK = 7779,
7804 PseudoVREDMAX_VS_M4_E16 = 7780,
7805 PseudoVREDMAX_VS_M4_E16_MASK = 7781,
7806 PseudoVREDMAX_VS_M4_E32 = 7782,
7807 PseudoVREDMAX_VS_M4_E32_MASK = 7783,
7808 PseudoVREDMAX_VS_M4_E64 = 7784,
7809 PseudoVREDMAX_VS_M4_E64_MASK = 7785,
7810 PseudoVREDMAX_VS_M4_E8 = 7786,
7811 PseudoVREDMAX_VS_M4_E8_MASK = 7787,
7812 PseudoVREDMAX_VS_M8_E16 = 7788,
7813 PseudoVREDMAX_VS_M8_E16_MASK = 7789,
7814 PseudoVREDMAX_VS_M8_E32 = 7790,
7815 PseudoVREDMAX_VS_M8_E32_MASK = 7791,
7816 PseudoVREDMAX_VS_M8_E64 = 7792,
7817 PseudoVREDMAX_VS_M8_E64_MASK = 7793,
7818 PseudoVREDMAX_VS_M8_E8 = 7794,
7819 PseudoVREDMAX_VS_M8_E8_MASK = 7795,
7820 PseudoVREDMAX_VS_MF2_E16 = 7796,
7821 PseudoVREDMAX_VS_MF2_E16_MASK = 7797,
7822 PseudoVREDMAX_VS_MF2_E32 = 7798,
7823 PseudoVREDMAX_VS_MF2_E32_MASK = 7799,
7824 PseudoVREDMAX_VS_MF2_E8 = 7800,
7825 PseudoVREDMAX_VS_MF2_E8_MASK = 7801,
7826 PseudoVREDMAX_VS_MF4_E16 = 7802,
7827 PseudoVREDMAX_VS_MF4_E16_MASK = 7803,
7828 PseudoVREDMAX_VS_MF4_E8 = 7804,
7829 PseudoVREDMAX_VS_MF4_E8_MASK = 7805,
7830 PseudoVREDMAX_VS_MF8_E8 = 7806,
7831 PseudoVREDMAX_VS_MF8_E8_MASK = 7807,
7832 PseudoVREDMINU_VS_M1_E16 = 7808,
7833 PseudoVREDMINU_VS_M1_E16_MASK = 7809,
7834 PseudoVREDMINU_VS_M1_E32 = 7810,
7835 PseudoVREDMINU_VS_M1_E32_MASK = 7811,
7836 PseudoVREDMINU_VS_M1_E64 = 7812,
7837 PseudoVREDMINU_VS_M1_E64_MASK = 7813,
7838 PseudoVREDMINU_VS_M1_E8 = 7814,
7839 PseudoVREDMINU_VS_M1_E8_MASK = 7815,
7840 PseudoVREDMINU_VS_M2_E16 = 7816,
7841 PseudoVREDMINU_VS_M2_E16_MASK = 7817,
7842 PseudoVREDMINU_VS_M2_E32 = 7818,
7843 PseudoVREDMINU_VS_M2_E32_MASK = 7819,
7844 PseudoVREDMINU_VS_M2_E64 = 7820,
7845 PseudoVREDMINU_VS_M2_E64_MASK = 7821,
7846 PseudoVREDMINU_VS_M2_E8 = 7822,
7847 PseudoVREDMINU_VS_M2_E8_MASK = 7823,
7848 PseudoVREDMINU_VS_M4_E16 = 7824,
7849 PseudoVREDMINU_VS_M4_E16_MASK = 7825,
7850 PseudoVREDMINU_VS_M4_E32 = 7826,
7851 PseudoVREDMINU_VS_M4_E32_MASK = 7827,
7852 PseudoVREDMINU_VS_M4_E64 = 7828,
7853 PseudoVREDMINU_VS_M4_E64_MASK = 7829,
7854 PseudoVREDMINU_VS_M4_E8 = 7830,
7855 PseudoVREDMINU_VS_M4_E8_MASK = 7831,
7856 PseudoVREDMINU_VS_M8_E16 = 7832,
7857 PseudoVREDMINU_VS_M8_E16_MASK = 7833,
7858 PseudoVREDMINU_VS_M8_E32 = 7834,
7859 PseudoVREDMINU_VS_M8_E32_MASK = 7835,
7860 PseudoVREDMINU_VS_M8_E64 = 7836,
7861 PseudoVREDMINU_VS_M8_E64_MASK = 7837,
7862 PseudoVREDMINU_VS_M8_E8 = 7838,
7863 PseudoVREDMINU_VS_M8_E8_MASK = 7839,
7864 PseudoVREDMINU_VS_MF2_E16 = 7840,
7865 PseudoVREDMINU_VS_MF2_E16_MASK = 7841,
7866 PseudoVREDMINU_VS_MF2_E32 = 7842,
7867 PseudoVREDMINU_VS_MF2_E32_MASK = 7843,
7868 PseudoVREDMINU_VS_MF2_E8 = 7844,
7869 PseudoVREDMINU_VS_MF2_E8_MASK = 7845,
7870 PseudoVREDMINU_VS_MF4_E16 = 7846,
7871 PseudoVREDMINU_VS_MF4_E16_MASK = 7847,
7872 PseudoVREDMINU_VS_MF4_E8 = 7848,
7873 PseudoVREDMINU_VS_MF4_E8_MASK = 7849,
7874 PseudoVREDMINU_VS_MF8_E8 = 7850,
7875 PseudoVREDMINU_VS_MF8_E8_MASK = 7851,
7876 PseudoVREDMIN_VS_M1_E16 = 7852,
7877 PseudoVREDMIN_VS_M1_E16_MASK = 7853,
7878 PseudoVREDMIN_VS_M1_E32 = 7854,
7879 PseudoVREDMIN_VS_M1_E32_MASK = 7855,
7880 PseudoVREDMIN_VS_M1_E64 = 7856,
7881 PseudoVREDMIN_VS_M1_E64_MASK = 7857,
7882 PseudoVREDMIN_VS_M1_E8 = 7858,
7883 PseudoVREDMIN_VS_M1_E8_MASK = 7859,
7884 PseudoVREDMIN_VS_M2_E16 = 7860,
7885 PseudoVREDMIN_VS_M2_E16_MASK = 7861,
7886 PseudoVREDMIN_VS_M2_E32 = 7862,
7887 PseudoVREDMIN_VS_M2_E32_MASK = 7863,
7888 PseudoVREDMIN_VS_M2_E64 = 7864,
7889 PseudoVREDMIN_VS_M2_E64_MASK = 7865,
7890 PseudoVREDMIN_VS_M2_E8 = 7866,
7891 PseudoVREDMIN_VS_M2_E8_MASK = 7867,
7892 PseudoVREDMIN_VS_M4_E16 = 7868,
7893 PseudoVREDMIN_VS_M4_E16_MASK = 7869,
7894 PseudoVREDMIN_VS_M4_E32 = 7870,
7895 PseudoVREDMIN_VS_M4_E32_MASK = 7871,
7896 PseudoVREDMIN_VS_M4_E64 = 7872,
7897 PseudoVREDMIN_VS_M4_E64_MASK = 7873,
7898 PseudoVREDMIN_VS_M4_E8 = 7874,
7899 PseudoVREDMIN_VS_M4_E8_MASK = 7875,
7900 PseudoVREDMIN_VS_M8_E16 = 7876,
7901 PseudoVREDMIN_VS_M8_E16_MASK = 7877,
7902 PseudoVREDMIN_VS_M8_E32 = 7878,
7903 PseudoVREDMIN_VS_M8_E32_MASK = 7879,
7904 PseudoVREDMIN_VS_M8_E64 = 7880,
7905 PseudoVREDMIN_VS_M8_E64_MASK = 7881,
7906 PseudoVREDMIN_VS_M8_E8 = 7882,
7907 PseudoVREDMIN_VS_M8_E8_MASK = 7883,
7908 PseudoVREDMIN_VS_MF2_E16 = 7884,
7909 PseudoVREDMIN_VS_MF2_E16_MASK = 7885,
7910 PseudoVREDMIN_VS_MF2_E32 = 7886,
7911 PseudoVREDMIN_VS_MF2_E32_MASK = 7887,
7912 PseudoVREDMIN_VS_MF2_E8 = 7888,
7913 PseudoVREDMIN_VS_MF2_E8_MASK = 7889,
7914 PseudoVREDMIN_VS_MF4_E16 = 7890,
7915 PseudoVREDMIN_VS_MF4_E16_MASK = 7891,
7916 PseudoVREDMIN_VS_MF4_E8 = 7892,
7917 PseudoVREDMIN_VS_MF4_E8_MASK = 7893,
7918 PseudoVREDMIN_VS_MF8_E8 = 7894,
7919 PseudoVREDMIN_VS_MF8_E8_MASK = 7895,
7920 PseudoVREDOR_VS_M1_E16 = 7896,
7921 PseudoVREDOR_VS_M1_E16_MASK = 7897,
7922 PseudoVREDOR_VS_M1_E32 = 7898,
7923 PseudoVREDOR_VS_M1_E32_MASK = 7899,
7924 PseudoVREDOR_VS_M1_E64 = 7900,
7925 PseudoVREDOR_VS_M1_E64_MASK = 7901,
7926 PseudoVREDOR_VS_M1_E8 = 7902,
7927 PseudoVREDOR_VS_M1_E8_MASK = 7903,
7928 PseudoVREDOR_VS_M2_E16 = 7904,
7929 PseudoVREDOR_VS_M2_E16_MASK = 7905,
7930 PseudoVREDOR_VS_M2_E32 = 7906,
7931 PseudoVREDOR_VS_M2_E32_MASK = 7907,
7932 PseudoVREDOR_VS_M2_E64 = 7908,
7933 PseudoVREDOR_VS_M2_E64_MASK = 7909,
7934 PseudoVREDOR_VS_M2_E8 = 7910,
7935 PseudoVREDOR_VS_M2_E8_MASK = 7911,
7936 PseudoVREDOR_VS_M4_E16 = 7912,
7937 PseudoVREDOR_VS_M4_E16_MASK = 7913,
7938 PseudoVREDOR_VS_M4_E32 = 7914,
7939 PseudoVREDOR_VS_M4_E32_MASK = 7915,
7940 PseudoVREDOR_VS_M4_E64 = 7916,
7941 PseudoVREDOR_VS_M4_E64_MASK = 7917,
7942 PseudoVREDOR_VS_M4_E8 = 7918,
7943 PseudoVREDOR_VS_M4_E8_MASK = 7919,
7944 PseudoVREDOR_VS_M8_E16 = 7920,
7945 PseudoVREDOR_VS_M8_E16_MASK = 7921,
7946 PseudoVREDOR_VS_M8_E32 = 7922,
7947 PseudoVREDOR_VS_M8_E32_MASK = 7923,
7948 PseudoVREDOR_VS_M8_E64 = 7924,
7949 PseudoVREDOR_VS_M8_E64_MASK = 7925,
7950 PseudoVREDOR_VS_M8_E8 = 7926,
7951 PseudoVREDOR_VS_M8_E8_MASK = 7927,
7952 PseudoVREDOR_VS_MF2_E16 = 7928,
7953 PseudoVREDOR_VS_MF2_E16_MASK = 7929,
7954 PseudoVREDOR_VS_MF2_E32 = 7930,
7955 PseudoVREDOR_VS_MF2_E32_MASK = 7931,
7956 PseudoVREDOR_VS_MF2_E8 = 7932,
7957 PseudoVREDOR_VS_MF2_E8_MASK = 7933,
7958 PseudoVREDOR_VS_MF4_E16 = 7934,
7959 PseudoVREDOR_VS_MF4_E16_MASK = 7935,
7960 PseudoVREDOR_VS_MF4_E8 = 7936,
7961 PseudoVREDOR_VS_MF4_E8_MASK = 7937,
7962 PseudoVREDOR_VS_MF8_E8 = 7938,
7963 PseudoVREDOR_VS_MF8_E8_MASK = 7939,
7964 PseudoVREDSUM_VS_M1_E16 = 7940,
7965 PseudoVREDSUM_VS_M1_E16_MASK = 7941,
7966 PseudoVREDSUM_VS_M1_E32 = 7942,
7967 PseudoVREDSUM_VS_M1_E32_MASK = 7943,
7968 PseudoVREDSUM_VS_M1_E64 = 7944,
7969 PseudoVREDSUM_VS_M1_E64_MASK = 7945,
7970 PseudoVREDSUM_VS_M1_E8 = 7946,
7971 PseudoVREDSUM_VS_M1_E8_MASK = 7947,
7972 PseudoVREDSUM_VS_M2_E16 = 7948,
7973 PseudoVREDSUM_VS_M2_E16_MASK = 7949,
7974 PseudoVREDSUM_VS_M2_E32 = 7950,
7975 PseudoVREDSUM_VS_M2_E32_MASK = 7951,
7976 PseudoVREDSUM_VS_M2_E64 = 7952,
7977 PseudoVREDSUM_VS_M2_E64_MASK = 7953,
7978 PseudoVREDSUM_VS_M2_E8 = 7954,
7979 PseudoVREDSUM_VS_M2_E8_MASK = 7955,
7980 PseudoVREDSUM_VS_M4_E16 = 7956,
7981 PseudoVREDSUM_VS_M4_E16_MASK = 7957,
7982 PseudoVREDSUM_VS_M4_E32 = 7958,
7983 PseudoVREDSUM_VS_M4_E32_MASK = 7959,
7984 PseudoVREDSUM_VS_M4_E64 = 7960,
7985 PseudoVREDSUM_VS_M4_E64_MASK = 7961,
7986 PseudoVREDSUM_VS_M4_E8 = 7962,
7987 PseudoVREDSUM_VS_M4_E8_MASK = 7963,
7988 PseudoVREDSUM_VS_M8_E16 = 7964,
7989 PseudoVREDSUM_VS_M8_E16_MASK = 7965,
7990 PseudoVREDSUM_VS_M8_E32 = 7966,
7991 PseudoVREDSUM_VS_M8_E32_MASK = 7967,
7992 PseudoVREDSUM_VS_M8_E64 = 7968,
7993 PseudoVREDSUM_VS_M8_E64_MASK = 7969,
7994 PseudoVREDSUM_VS_M8_E8 = 7970,
7995 PseudoVREDSUM_VS_M8_E8_MASK = 7971,
7996 PseudoVREDSUM_VS_MF2_E16 = 7972,
7997 PseudoVREDSUM_VS_MF2_E16_MASK = 7973,
7998 PseudoVREDSUM_VS_MF2_E32 = 7974,
7999 PseudoVREDSUM_VS_MF2_E32_MASK = 7975,
8000 PseudoVREDSUM_VS_MF2_E8 = 7976,
8001 PseudoVREDSUM_VS_MF2_E8_MASK = 7977,
8002 PseudoVREDSUM_VS_MF4_E16 = 7978,
8003 PseudoVREDSUM_VS_MF4_E16_MASK = 7979,
8004 PseudoVREDSUM_VS_MF4_E8 = 7980,
8005 PseudoVREDSUM_VS_MF4_E8_MASK = 7981,
8006 PseudoVREDSUM_VS_MF8_E8 = 7982,
8007 PseudoVREDSUM_VS_MF8_E8_MASK = 7983,
8008 PseudoVREDXOR_VS_M1_E16 = 7984,
8009 PseudoVREDXOR_VS_M1_E16_MASK = 7985,
8010 PseudoVREDXOR_VS_M1_E32 = 7986,
8011 PseudoVREDXOR_VS_M1_E32_MASK = 7987,
8012 PseudoVREDXOR_VS_M1_E64 = 7988,
8013 PseudoVREDXOR_VS_M1_E64_MASK = 7989,
8014 PseudoVREDXOR_VS_M1_E8 = 7990,
8015 PseudoVREDXOR_VS_M1_E8_MASK = 7991,
8016 PseudoVREDXOR_VS_M2_E16 = 7992,
8017 PseudoVREDXOR_VS_M2_E16_MASK = 7993,
8018 PseudoVREDXOR_VS_M2_E32 = 7994,
8019 PseudoVREDXOR_VS_M2_E32_MASK = 7995,
8020 PseudoVREDXOR_VS_M2_E64 = 7996,
8021 PseudoVREDXOR_VS_M2_E64_MASK = 7997,
8022 PseudoVREDXOR_VS_M2_E8 = 7998,
8023 PseudoVREDXOR_VS_M2_E8_MASK = 7999,
8024 PseudoVREDXOR_VS_M4_E16 = 8000,
8025 PseudoVREDXOR_VS_M4_E16_MASK = 8001,
8026 PseudoVREDXOR_VS_M4_E32 = 8002,
8027 PseudoVREDXOR_VS_M4_E32_MASK = 8003,
8028 PseudoVREDXOR_VS_M4_E64 = 8004,
8029 PseudoVREDXOR_VS_M4_E64_MASK = 8005,
8030 PseudoVREDXOR_VS_M4_E8 = 8006,
8031 PseudoVREDXOR_VS_M4_E8_MASK = 8007,
8032 PseudoVREDXOR_VS_M8_E16 = 8008,
8033 PseudoVREDXOR_VS_M8_E16_MASK = 8009,
8034 PseudoVREDXOR_VS_M8_E32 = 8010,
8035 PseudoVREDXOR_VS_M8_E32_MASK = 8011,
8036 PseudoVREDXOR_VS_M8_E64 = 8012,
8037 PseudoVREDXOR_VS_M8_E64_MASK = 8013,
8038 PseudoVREDXOR_VS_M8_E8 = 8014,
8039 PseudoVREDXOR_VS_M8_E8_MASK = 8015,
8040 PseudoVREDXOR_VS_MF2_E16 = 8016,
8041 PseudoVREDXOR_VS_MF2_E16_MASK = 8017,
8042 PseudoVREDXOR_VS_MF2_E32 = 8018,
8043 PseudoVREDXOR_VS_MF2_E32_MASK = 8019,
8044 PseudoVREDXOR_VS_MF2_E8 = 8020,
8045 PseudoVREDXOR_VS_MF2_E8_MASK = 8021,
8046 PseudoVREDXOR_VS_MF4_E16 = 8022,
8047 PseudoVREDXOR_VS_MF4_E16_MASK = 8023,
8048 PseudoVREDXOR_VS_MF4_E8 = 8024,
8049 PseudoVREDXOR_VS_MF4_E8_MASK = 8025,
8050 PseudoVREDXOR_VS_MF8_E8 = 8026,
8051 PseudoVREDXOR_VS_MF8_E8_MASK = 8027,
8052 PseudoVRELOAD2_M1 = 8028,
8053 PseudoVRELOAD2_M2 = 8029,
8054 PseudoVRELOAD2_M4 = 8030,
8055 PseudoVRELOAD2_MF2 = 8031,
8056 PseudoVRELOAD2_MF4 = 8032,
8057 PseudoVRELOAD2_MF8 = 8033,
8058 PseudoVRELOAD3_M1 = 8034,
8059 PseudoVRELOAD3_M2 = 8035,
8060 PseudoVRELOAD3_MF2 = 8036,
8061 PseudoVRELOAD3_MF4 = 8037,
8062 PseudoVRELOAD3_MF8 = 8038,
8063 PseudoVRELOAD4_M1 = 8039,
8064 PseudoVRELOAD4_M2 = 8040,
8065 PseudoVRELOAD4_MF2 = 8041,
8066 PseudoVRELOAD4_MF4 = 8042,
8067 PseudoVRELOAD4_MF8 = 8043,
8068 PseudoVRELOAD5_M1 = 8044,
8069 PseudoVRELOAD5_MF2 = 8045,
8070 PseudoVRELOAD5_MF4 = 8046,
8071 PseudoVRELOAD5_MF8 = 8047,
8072 PseudoVRELOAD6_M1 = 8048,
8073 PseudoVRELOAD6_MF2 = 8049,
8074 PseudoVRELOAD6_MF4 = 8050,
8075 PseudoVRELOAD6_MF8 = 8051,
8076 PseudoVRELOAD7_M1 = 8052,
8077 PseudoVRELOAD7_MF2 = 8053,
8078 PseudoVRELOAD7_MF4 = 8054,
8079 PseudoVRELOAD7_MF8 = 8055,
8080 PseudoVRELOAD8_M1 = 8056,
8081 PseudoVRELOAD8_MF2 = 8057,
8082 PseudoVRELOAD8_MF4 = 8058,
8083 PseudoVRELOAD8_MF8 = 8059,
8084 PseudoVREMU_VV_M1_E16 = 8060,
8085 PseudoVREMU_VV_M1_E16_MASK = 8061,
8086 PseudoVREMU_VV_M1_E32 = 8062,
8087 PseudoVREMU_VV_M1_E32_MASK = 8063,
8088 PseudoVREMU_VV_M1_E64 = 8064,
8089 PseudoVREMU_VV_M1_E64_MASK = 8065,
8090 PseudoVREMU_VV_M1_E8 = 8066,
8091 PseudoVREMU_VV_M1_E8_MASK = 8067,
8092 PseudoVREMU_VV_M2_E16 = 8068,
8093 PseudoVREMU_VV_M2_E16_MASK = 8069,
8094 PseudoVREMU_VV_M2_E32 = 8070,
8095 PseudoVREMU_VV_M2_E32_MASK = 8071,
8096 PseudoVREMU_VV_M2_E64 = 8072,
8097 PseudoVREMU_VV_M2_E64_MASK = 8073,
8098 PseudoVREMU_VV_M2_E8 = 8074,
8099 PseudoVREMU_VV_M2_E8_MASK = 8075,
8100 PseudoVREMU_VV_M4_E16 = 8076,
8101 PseudoVREMU_VV_M4_E16_MASK = 8077,
8102 PseudoVREMU_VV_M4_E32 = 8078,
8103 PseudoVREMU_VV_M4_E32_MASK = 8079,
8104 PseudoVREMU_VV_M4_E64 = 8080,
8105 PseudoVREMU_VV_M4_E64_MASK = 8081,
8106 PseudoVREMU_VV_M4_E8 = 8082,
8107 PseudoVREMU_VV_M4_E8_MASK = 8083,
8108 PseudoVREMU_VV_M8_E16 = 8084,
8109 PseudoVREMU_VV_M8_E16_MASK = 8085,
8110 PseudoVREMU_VV_M8_E32 = 8086,
8111 PseudoVREMU_VV_M8_E32_MASK = 8087,
8112 PseudoVREMU_VV_M8_E64 = 8088,
8113 PseudoVREMU_VV_M8_E64_MASK = 8089,
8114 PseudoVREMU_VV_M8_E8 = 8090,
8115 PseudoVREMU_VV_M8_E8_MASK = 8091,
8116 PseudoVREMU_VV_MF2_E16 = 8092,
8117 PseudoVREMU_VV_MF2_E16_MASK = 8093,
8118 PseudoVREMU_VV_MF2_E32 = 8094,
8119 PseudoVREMU_VV_MF2_E32_MASK = 8095,
8120 PseudoVREMU_VV_MF2_E8 = 8096,
8121 PseudoVREMU_VV_MF2_E8_MASK = 8097,
8122 PseudoVREMU_VV_MF4_E16 = 8098,
8123 PseudoVREMU_VV_MF4_E16_MASK = 8099,
8124 PseudoVREMU_VV_MF4_E8 = 8100,
8125 PseudoVREMU_VV_MF4_E8_MASK = 8101,
8126 PseudoVREMU_VV_MF8_E8 = 8102,
8127 PseudoVREMU_VV_MF8_E8_MASK = 8103,
8128 PseudoVREMU_VX_M1_E16 = 8104,
8129 PseudoVREMU_VX_M1_E16_MASK = 8105,
8130 PseudoVREMU_VX_M1_E32 = 8106,
8131 PseudoVREMU_VX_M1_E32_MASK = 8107,
8132 PseudoVREMU_VX_M1_E64 = 8108,
8133 PseudoVREMU_VX_M1_E64_MASK = 8109,
8134 PseudoVREMU_VX_M1_E8 = 8110,
8135 PseudoVREMU_VX_M1_E8_MASK = 8111,
8136 PseudoVREMU_VX_M2_E16 = 8112,
8137 PseudoVREMU_VX_M2_E16_MASK = 8113,
8138 PseudoVREMU_VX_M2_E32 = 8114,
8139 PseudoVREMU_VX_M2_E32_MASK = 8115,
8140 PseudoVREMU_VX_M2_E64 = 8116,
8141 PseudoVREMU_VX_M2_E64_MASK = 8117,
8142 PseudoVREMU_VX_M2_E8 = 8118,
8143 PseudoVREMU_VX_M2_E8_MASK = 8119,
8144 PseudoVREMU_VX_M4_E16 = 8120,
8145 PseudoVREMU_VX_M4_E16_MASK = 8121,
8146 PseudoVREMU_VX_M4_E32 = 8122,
8147 PseudoVREMU_VX_M4_E32_MASK = 8123,
8148 PseudoVREMU_VX_M4_E64 = 8124,
8149 PseudoVREMU_VX_M4_E64_MASK = 8125,
8150 PseudoVREMU_VX_M4_E8 = 8126,
8151 PseudoVREMU_VX_M4_E8_MASK = 8127,
8152 PseudoVREMU_VX_M8_E16 = 8128,
8153 PseudoVREMU_VX_M8_E16_MASK = 8129,
8154 PseudoVREMU_VX_M8_E32 = 8130,
8155 PseudoVREMU_VX_M8_E32_MASK = 8131,
8156 PseudoVREMU_VX_M8_E64 = 8132,
8157 PseudoVREMU_VX_M8_E64_MASK = 8133,
8158 PseudoVREMU_VX_M8_E8 = 8134,
8159 PseudoVREMU_VX_M8_E8_MASK = 8135,
8160 PseudoVREMU_VX_MF2_E16 = 8136,
8161 PseudoVREMU_VX_MF2_E16_MASK = 8137,
8162 PseudoVREMU_VX_MF2_E32 = 8138,
8163 PseudoVREMU_VX_MF2_E32_MASK = 8139,
8164 PseudoVREMU_VX_MF2_E8 = 8140,
8165 PseudoVREMU_VX_MF2_E8_MASK = 8141,
8166 PseudoVREMU_VX_MF4_E16 = 8142,
8167 PseudoVREMU_VX_MF4_E16_MASK = 8143,
8168 PseudoVREMU_VX_MF4_E8 = 8144,
8169 PseudoVREMU_VX_MF4_E8_MASK = 8145,
8170 PseudoVREMU_VX_MF8_E8 = 8146,
8171 PseudoVREMU_VX_MF8_E8_MASK = 8147,
8172 PseudoVREM_VV_M1_E16 = 8148,
8173 PseudoVREM_VV_M1_E16_MASK = 8149,
8174 PseudoVREM_VV_M1_E32 = 8150,
8175 PseudoVREM_VV_M1_E32_MASK = 8151,
8176 PseudoVREM_VV_M1_E64 = 8152,
8177 PseudoVREM_VV_M1_E64_MASK = 8153,
8178 PseudoVREM_VV_M1_E8 = 8154,
8179 PseudoVREM_VV_M1_E8_MASK = 8155,
8180 PseudoVREM_VV_M2_E16 = 8156,
8181 PseudoVREM_VV_M2_E16_MASK = 8157,
8182 PseudoVREM_VV_M2_E32 = 8158,
8183 PseudoVREM_VV_M2_E32_MASK = 8159,
8184 PseudoVREM_VV_M2_E64 = 8160,
8185 PseudoVREM_VV_M2_E64_MASK = 8161,
8186 PseudoVREM_VV_M2_E8 = 8162,
8187 PseudoVREM_VV_M2_E8_MASK = 8163,
8188 PseudoVREM_VV_M4_E16 = 8164,
8189 PseudoVREM_VV_M4_E16_MASK = 8165,
8190 PseudoVREM_VV_M4_E32 = 8166,
8191 PseudoVREM_VV_M4_E32_MASK = 8167,
8192 PseudoVREM_VV_M4_E64 = 8168,
8193 PseudoVREM_VV_M4_E64_MASK = 8169,
8194 PseudoVREM_VV_M4_E8 = 8170,
8195 PseudoVREM_VV_M4_E8_MASK = 8171,
8196 PseudoVREM_VV_M8_E16 = 8172,
8197 PseudoVREM_VV_M8_E16_MASK = 8173,
8198 PseudoVREM_VV_M8_E32 = 8174,
8199 PseudoVREM_VV_M8_E32_MASK = 8175,
8200 PseudoVREM_VV_M8_E64 = 8176,
8201 PseudoVREM_VV_M8_E64_MASK = 8177,
8202 PseudoVREM_VV_M8_E8 = 8178,
8203 PseudoVREM_VV_M8_E8_MASK = 8179,
8204 PseudoVREM_VV_MF2_E16 = 8180,
8205 PseudoVREM_VV_MF2_E16_MASK = 8181,
8206 PseudoVREM_VV_MF2_E32 = 8182,
8207 PseudoVREM_VV_MF2_E32_MASK = 8183,
8208 PseudoVREM_VV_MF2_E8 = 8184,
8209 PseudoVREM_VV_MF2_E8_MASK = 8185,
8210 PseudoVREM_VV_MF4_E16 = 8186,
8211 PseudoVREM_VV_MF4_E16_MASK = 8187,
8212 PseudoVREM_VV_MF4_E8 = 8188,
8213 PseudoVREM_VV_MF4_E8_MASK = 8189,
8214 PseudoVREM_VV_MF8_E8 = 8190,
8215 PseudoVREM_VV_MF8_E8_MASK = 8191,
8216 PseudoVREM_VX_M1_E16 = 8192,
8217 PseudoVREM_VX_M1_E16_MASK = 8193,
8218 PseudoVREM_VX_M1_E32 = 8194,
8219 PseudoVREM_VX_M1_E32_MASK = 8195,
8220 PseudoVREM_VX_M1_E64 = 8196,
8221 PseudoVREM_VX_M1_E64_MASK = 8197,
8222 PseudoVREM_VX_M1_E8 = 8198,
8223 PseudoVREM_VX_M1_E8_MASK = 8199,
8224 PseudoVREM_VX_M2_E16 = 8200,
8225 PseudoVREM_VX_M2_E16_MASK = 8201,
8226 PseudoVREM_VX_M2_E32 = 8202,
8227 PseudoVREM_VX_M2_E32_MASK = 8203,
8228 PseudoVREM_VX_M2_E64 = 8204,
8229 PseudoVREM_VX_M2_E64_MASK = 8205,
8230 PseudoVREM_VX_M2_E8 = 8206,
8231 PseudoVREM_VX_M2_E8_MASK = 8207,
8232 PseudoVREM_VX_M4_E16 = 8208,
8233 PseudoVREM_VX_M4_E16_MASK = 8209,
8234 PseudoVREM_VX_M4_E32 = 8210,
8235 PseudoVREM_VX_M4_E32_MASK = 8211,
8236 PseudoVREM_VX_M4_E64 = 8212,
8237 PseudoVREM_VX_M4_E64_MASK = 8213,
8238 PseudoVREM_VX_M4_E8 = 8214,
8239 PseudoVREM_VX_M4_E8_MASK = 8215,
8240 PseudoVREM_VX_M8_E16 = 8216,
8241 PseudoVREM_VX_M8_E16_MASK = 8217,
8242 PseudoVREM_VX_M8_E32 = 8218,
8243 PseudoVREM_VX_M8_E32_MASK = 8219,
8244 PseudoVREM_VX_M8_E64 = 8220,
8245 PseudoVREM_VX_M8_E64_MASK = 8221,
8246 PseudoVREM_VX_M8_E8 = 8222,
8247 PseudoVREM_VX_M8_E8_MASK = 8223,
8248 PseudoVREM_VX_MF2_E16 = 8224,
8249 PseudoVREM_VX_MF2_E16_MASK = 8225,
8250 PseudoVREM_VX_MF2_E32 = 8226,
8251 PseudoVREM_VX_MF2_E32_MASK = 8227,
8252 PseudoVREM_VX_MF2_E8 = 8228,
8253 PseudoVREM_VX_MF2_E8_MASK = 8229,
8254 PseudoVREM_VX_MF4_E16 = 8230,
8255 PseudoVREM_VX_MF4_E16_MASK = 8231,
8256 PseudoVREM_VX_MF4_E8 = 8232,
8257 PseudoVREM_VX_MF4_E8_MASK = 8233,
8258 PseudoVREM_VX_MF8_E8 = 8234,
8259 PseudoVREM_VX_MF8_E8_MASK = 8235,
8260 PseudoVREV8_V_M1 = 8236,
8261 PseudoVREV8_V_M1_MASK = 8237,
8262 PseudoVREV8_V_M2 = 8238,
8263 PseudoVREV8_V_M2_MASK = 8239,
8264 PseudoVREV8_V_M4 = 8240,
8265 PseudoVREV8_V_M4_MASK = 8241,
8266 PseudoVREV8_V_M8 = 8242,
8267 PseudoVREV8_V_M8_MASK = 8243,
8268 PseudoVREV8_V_MF2 = 8244,
8269 PseudoVREV8_V_MF2_MASK = 8245,
8270 PseudoVREV8_V_MF4 = 8246,
8271 PseudoVREV8_V_MF4_MASK = 8247,
8272 PseudoVREV8_V_MF8 = 8248,
8273 PseudoVREV8_V_MF8_MASK = 8249,
8274 PseudoVRGATHEREI16_VV_M1_E16_M1 = 8250,
8275 PseudoVRGATHEREI16_VV_M1_E16_M1_MASK = 8251,
8276 PseudoVRGATHEREI16_VV_M1_E16_M2 = 8252,
8277 PseudoVRGATHEREI16_VV_M1_E16_M2_MASK = 8253,
8278 PseudoVRGATHEREI16_VV_M1_E16_MF2 = 8254,
8279 PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK = 8255,
8280 PseudoVRGATHEREI16_VV_M1_E16_MF4 = 8256,
8281 PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK = 8257,
8282 PseudoVRGATHEREI16_VV_M1_E32_M1 = 8258,
8283 PseudoVRGATHEREI16_VV_M1_E32_M1_MASK = 8259,
8284 PseudoVRGATHEREI16_VV_M1_E32_M2 = 8260,
8285 PseudoVRGATHEREI16_VV_M1_E32_M2_MASK = 8261,
8286 PseudoVRGATHEREI16_VV_M1_E32_MF2 = 8262,
8287 PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK = 8263,
8288 PseudoVRGATHEREI16_VV_M1_E32_MF4 = 8264,
8289 PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK = 8265,
8290 PseudoVRGATHEREI16_VV_M1_E64_M1 = 8266,
8291 PseudoVRGATHEREI16_VV_M1_E64_M1_MASK = 8267,
8292 PseudoVRGATHEREI16_VV_M1_E64_M2 = 8268,
8293 PseudoVRGATHEREI16_VV_M1_E64_M2_MASK = 8269,
8294 PseudoVRGATHEREI16_VV_M1_E64_MF2 = 8270,
8295 PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK = 8271,
8296 PseudoVRGATHEREI16_VV_M1_E64_MF4 = 8272,
8297 PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK = 8273,
8298 PseudoVRGATHEREI16_VV_M1_E8_M1 = 8274,
8299 PseudoVRGATHEREI16_VV_M1_E8_M1_MASK = 8275,
8300 PseudoVRGATHEREI16_VV_M1_E8_M2 = 8276,
8301 PseudoVRGATHEREI16_VV_M1_E8_M2_MASK = 8277,
8302 PseudoVRGATHEREI16_VV_M1_E8_MF2 = 8278,
8303 PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK = 8279,
8304 PseudoVRGATHEREI16_VV_M1_E8_MF4 = 8280,
8305 PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK = 8281,
8306 PseudoVRGATHEREI16_VV_M2_E16_M1 = 8282,
8307 PseudoVRGATHEREI16_VV_M2_E16_M1_MASK = 8283,
8308 PseudoVRGATHEREI16_VV_M2_E16_M2 = 8284,
8309 PseudoVRGATHEREI16_VV_M2_E16_M2_MASK = 8285,
8310 PseudoVRGATHEREI16_VV_M2_E16_M4 = 8286,
8311 PseudoVRGATHEREI16_VV_M2_E16_M4_MASK = 8287,
8312 PseudoVRGATHEREI16_VV_M2_E16_MF2 = 8288,
8313 PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK = 8289,
8314 PseudoVRGATHEREI16_VV_M2_E32_M1 = 8290,
8315 PseudoVRGATHEREI16_VV_M2_E32_M1_MASK = 8291,
8316 PseudoVRGATHEREI16_VV_M2_E32_M2 = 8292,
8317 PseudoVRGATHEREI16_VV_M2_E32_M2_MASK = 8293,
8318 PseudoVRGATHEREI16_VV_M2_E32_M4 = 8294,
8319 PseudoVRGATHEREI16_VV_M2_E32_M4_MASK = 8295,
8320 PseudoVRGATHEREI16_VV_M2_E32_MF2 = 8296,
8321 PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK = 8297,
8322 PseudoVRGATHEREI16_VV_M2_E64_M1 = 8298,
8323 PseudoVRGATHEREI16_VV_M2_E64_M1_MASK = 8299,
8324 PseudoVRGATHEREI16_VV_M2_E64_M2 = 8300,
8325 PseudoVRGATHEREI16_VV_M2_E64_M2_MASK = 8301,
8326 PseudoVRGATHEREI16_VV_M2_E64_M4 = 8302,
8327 PseudoVRGATHEREI16_VV_M2_E64_M4_MASK = 8303,
8328 PseudoVRGATHEREI16_VV_M2_E64_MF2 = 8304,
8329 PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK = 8305,
8330 PseudoVRGATHEREI16_VV_M2_E8_M1 = 8306,
8331 PseudoVRGATHEREI16_VV_M2_E8_M1_MASK = 8307,
8332 PseudoVRGATHEREI16_VV_M2_E8_M2 = 8308,
8333 PseudoVRGATHEREI16_VV_M2_E8_M2_MASK = 8309,
8334 PseudoVRGATHEREI16_VV_M2_E8_M4 = 8310,
8335 PseudoVRGATHEREI16_VV_M2_E8_M4_MASK = 8311,
8336 PseudoVRGATHEREI16_VV_M2_E8_MF2 = 8312,
8337 PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK = 8313,
8338 PseudoVRGATHEREI16_VV_M4_E16_M1 = 8314,
8339 PseudoVRGATHEREI16_VV_M4_E16_M1_MASK = 8315,
8340 PseudoVRGATHEREI16_VV_M4_E16_M2 = 8316,
8341 PseudoVRGATHEREI16_VV_M4_E16_M2_MASK = 8317,
8342 PseudoVRGATHEREI16_VV_M4_E16_M4 = 8318,
8343 PseudoVRGATHEREI16_VV_M4_E16_M4_MASK = 8319,
8344 PseudoVRGATHEREI16_VV_M4_E16_M8 = 8320,
8345 PseudoVRGATHEREI16_VV_M4_E16_M8_MASK = 8321,
8346 PseudoVRGATHEREI16_VV_M4_E32_M1 = 8322,
8347 PseudoVRGATHEREI16_VV_M4_E32_M1_MASK = 8323,
8348 PseudoVRGATHEREI16_VV_M4_E32_M2 = 8324,
8349 PseudoVRGATHEREI16_VV_M4_E32_M2_MASK = 8325,
8350 PseudoVRGATHEREI16_VV_M4_E32_M4 = 8326,
8351 PseudoVRGATHEREI16_VV_M4_E32_M4_MASK = 8327,
8352 PseudoVRGATHEREI16_VV_M4_E32_M8 = 8328,
8353 PseudoVRGATHEREI16_VV_M4_E32_M8_MASK = 8329,
8354 PseudoVRGATHEREI16_VV_M4_E64_M1 = 8330,
8355 PseudoVRGATHEREI16_VV_M4_E64_M1_MASK = 8331,
8356 PseudoVRGATHEREI16_VV_M4_E64_M2 = 8332,
8357 PseudoVRGATHEREI16_VV_M4_E64_M2_MASK = 8333,
8358 PseudoVRGATHEREI16_VV_M4_E64_M4 = 8334,
8359 PseudoVRGATHEREI16_VV_M4_E64_M4_MASK = 8335,
8360 PseudoVRGATHEREI16_VV_M4_E64_M8 = 8336,
8361 PseudoVRGATHEREI16_VV_M4_E64_M8_MASK = 8337,
8362 PseudoVRGATHEREI16_VV_M4_E8_M1 = 8338,
8363 PseudoVRGATHEREI16_VV_M4_E8_M1_MASK = 8339,
8364 PseudoVRGATHEREI16_VV_M4_E8_M2 = 8340,
8365 PseudoVRGATHEREI16_VV_M4_E8_M2_MASK = 8341,
8366 PseudoVRGATHEREI16_VV_M4_E8_M4 = 8342,
8367 PseudoVRGATHEREI16_VV_M4_E8_M4_MASK = 8343,
8368 PseudoVRGATHEREI16_VV_M4_E8_M8 = 8344,
8369 PseudoVRGATHEREI16_VV_M4_E8_M8_MASK = 8345,
8370 PseudoVRGATHEREI16_VV_M8_E16_M2 = 8346,
8371 PseudoVRGATHEREI16_VV_M8_E16_M2_MASK = 8347,
8372 PseudoVRGATHEREI16_VV_M8_E16_M4 = 8348,
8373 PseudoVRGATHEREI16_VV_M8_E16_M4_MASK = 8349,
8374 PseudoVRGATHEREI16_VV_M8_E16_M8 = 8350,
8375 PseudoVRGATHEREI16_VV_M8_E16_M8_MASK = 8351,
8376 PseudoVRGATHEREI16_VV_M8_E32_M2 = 8352,
8377 PseudoVRGATHEREI16_VV_M8_E32_M2_MASK = 8353,
8378 PseudoVRGATHEREI16_VV_M8_E32_M4 = 8354,
8379 PseudoVRGATHEREI16_VV_M8_E32_M4_MASK = 8355,
8380 PseudoVRGATHEREI16_VV_M8_E32_M8 = 8356,
8381 PseudoVRGATHEREI16_VV_M8_E32_M8_MASK = 8357,
8382 PseudoVRGATHEREI16_VV_M8_E64_M2 = 8358,
8383 PseudoVRGATHEREI16_VV_M8_E64_M2_MASK = 8359,
8384 PseudoVRGATHEREI16_VV_M8_E64_M4 = 8360,
8385 PseudoVRGATHEREI16_VV_M8_E64_M4_MASK = 8361,
8386 PseudoVRGATHEREI16_VV_M8_E64_M8 = 8362,
8387 PseudoVRGATHEREI16_VV_M8_E64_M8_MASK = 8363,
8388 PseudoVRGATHEREI16_VV_M8_E8_M2 = 8364,
8389 PseudoVRGATHEREI16_VV_M8_E8_M2_MASK = 8365,
8390 PseudoVRGATHEREI16_VV_M8_E8_M4 = 8366,
8391 PseudoVRGATHEREI16_VV_M8_E8_M4_MASK = 8367,
8392 PseudoVRGATHEREI16_VV_M8_E8_M8 = 8368,
8393 PseudoVRGATHEREI16_VV_M8_E8_M8_MASK = 8369,
8394 PseudoVRGATHEREI16_VV_MF2_E16_M1 = 8370,
8395 PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK = 8371,
8396 PseudoVRGATHEREI16_VV_MF2_E16_MF2 = 8372,
8397 PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK = 8373,
8398 PseudoVRGATHEREI16_VV_MF2_E16_MF4 = 8374,
8399 PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK = 8375,
8400 PseudoVRGATHEREI16_VV_MF2_E16_MF8 = 8376,
8401 PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK = 8377,
8402 PseudoVRGATHEREI16_VV_MF2_E32_M1 = 8378,
8403 PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK = 8379,
8404 PseudoVRGATHEREI16_VV_MF2_E32_MF2 = 8380,
8405 PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK = 8381,
8406 PseudoVRGATHEREI16_VV_MF2_E32_MF4 = 8382,
8407 PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK = 8383,
8408 PseudoVRGATHEREI16_VV_MF2_E32_MF8 = 8384,
8409 PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK = 8385,
8410 PseudoVRGATHEREI16_VV_MF2_E8_M1 = 8386,
8411 PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK = 8387,
8412 PseudoVRGATHEREI16_VV_MF2_E8_MF2 = 8388,
8413 PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK = 8389,
8414 PseudoVRGATHEREI16_VV_MF2_E8_MF4 = 8390,
8415 PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK = 8391,
8416 PseudoVRGATHEREI16_VV_MF2_E8_MF8 = 8392,
8417 PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK = 8393,
8418 PseudoVRGATHEREI16_VV_MF4_E16_MF2 = 8394,
8419 PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK = 8395,
8420 PseudoVRGATHEREI16_VV_MF4_E16_MF4 = 8396,
8421 PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK = 8397,
8422 PseudoVRGATHEREI16_VV_MF4_E16_MF8 = 8398,
8423 PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK = 8399,
8424 PseudoVRGATHEREI16_VV_MF4_E8_MF2 = 8400,
8425 PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK = 8401,
8426 PseudoVRGATHEREI16_VV_MF4_E8_MF4 = 8402,
8427 PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK = 8403,
8428 PseudoVRGATHEREI16_VV_MF4_E8_MF8 = 8404,
8429 PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK = 8405,
8430 PseudoVRGATHEREI16_VV_MF8_E8_MF4 = 8406,
8431 PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK = 8407,
8432 PseudoVRGATHEREI16_VV_MF8_E8_MF8 = 8408,
8433 PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK = 8409,
8434 PseudoVRGATHER_VI_M1 = 8410,
8435 PseudoVRGATHER_VI_M1_MASK = 8411,
8436 PseudoVRGATHER_VI_M2 = 8412,
8437 PseudoVRGATHER_VI_M2_MASK = 8413,
8438 PseudoVRGATHER_VI_M4 = 8414,
8439 PseudoVRGATHER_VI_M4_MASK = 8415,
8440 PseudoVRGATHER_VI_M8 = 8416,
8441 PseudoVRGATHER_VI_M8_MASK = 8417,
8442 PseudoVRGATHER_VI_MF2 = 8418,
8443 PseudoVRGATHER_VI_MF2_MASK = 8419,
8444 PseudoVRGATHER_VI_MF4 = 8420,
8445 PseudoVRGATHER_VI_MF4_MASK = 8421,
8446 PseudoVRGATHER_VI_MF8 = 8422,
8447 PseudoVRGATHER_VI_MF8_MASK = 8423,
8448 PseudoVRGATHER_VV_M1_E16 = 8424,
8449 PseudoVRGATHER_VV_M1_E16_MASK = 8425,
8450 PseudoVRGATHER_VV_M1_E32 = 8426,
8451 PseudoVRGATHER_VV_M1_E32_MASK = 8427,
8452 PseudoVRGATHER_VV_M1_E64 = 8428,
8453 PseudoVRGATHER_VV_M1_E64_MASK = 8429,
8454 PseudoVRGATHER_VV_M1_E8 = 8430,
8455 PseudoVRGATHER_VV_M1_E8_MASK = 8431,
8456 PseudoVRGATHER_VV_M2_E16 = 8432,
8457 PseudoVRGATHER_VV_M2_E16_MASK = 8433,
8458 PseudoVRGATHER_VV_M2_E32 = 8434,
8459 PseudoVRGATHER_VV_M2_E32_MASK = 8435,
8460 PseudoVRGATHER_VV_M2_E64 = 8436,
8461 PseudoVRGATHER_VV_M2_E64_MASK = 8437,
8462 PseudoVRGATHER_VV_M2_E8 = 8438,
8463 PseudoVRGATHER_VV_M2_E8_MASK = 8439,
8464 PseudoVRGATHER_VV_M4_E16 = 8440,
8465 PseudoVRGATHER_VV_M4_E16_MASK = 8441,
8466 PseudoVRGATHER_VV_M4_E32 = 8442,
8467 PseudoVRGATHER_VV_M4_E32_MASK = 8443,
8468 PseudoVRGATHER_VV_M4_E64 = 8444,
8469 PseudoVRGATHER_VV_M4_E64_MASK = 8445,
8470 PseudoVRGATHER_VV_M4_E8 = 8446,
8471 PseudoVRGATHER_VV_M4_E8_MASK = 8447,
8472 PseudoVRGATHER_VV_M8_E16 = 8448,
8473 PseudoVRGATHER_VV_M8_E16_MASK = 8449,
8474 PseudoVRGATHER_VV_M8_E32 = 8450,
8475 PseudoVRGATHER_VV_M8_E32_MASK = 8451,
8476 PseudoVRGATHER_VV_M8_E64 = 8452,
8477 PseudoVRGATHER_VV_M8_E64_MASK = 8453,
8478 PseudoVRGATHER_VV_M8_E8 = 8454,
8479 PseudoVRGATHER_VV_M8_E8_MASK = 8455,
8480 PseudoVRGATHER_VV_MF2_E16 = 8456,
8481 PseudoVRGATHER_VV_MF2_E16_MASK = 8457,
8482 PseudoVRGATHER_VV_MF2_E32 = 8458,
8483 PseudoVRGATHER_VV_MF2_E32_MASK = 8459,
8484 PseudoVRGATHER_VV_MF2_E8 = 8460,
8485 PseudoVRGATHER_VV_MF2_E8_MASK = 8461,
8486 PseudoVRGATHER_VV_MF4_E16 = 8462,
8487 PseudoVRGATHER_VV_MF4_E16_MASK = 8463,
8488 PseudoVRGATHER_VV_MF4_E8 = 8464,
8489 PseudoVRGATHER_VV_MF4_E8_MASK = 8465,
8490 PseudoVRGATHER_VV_MF8_E8 = 8466,
8491 PseudoVRGATHER_VV_MF8_E8_MASK = 8467,
8492 PseudoVRGATHER_VX_M1 = 8468,
8493 PseudoVRGATHER_VX_M1_MASK = 8469,
8494 PseudoVRGATHER_VX_M2 = 8470,
8495 PseudoVRGATHER_VX_M2_MASK = 8471,
8496 PseudoVRGATHER_VX_M4 = 8472,
8497 PseudoVRGATHER_VX_M4_MASK = 8473,
8498 PseudoVRGATHER_VX_M8 = 8474,
8499 PseudoVRGATHER_VX_M8_MASK = 8475,
8500 PseudoVRGATHER_VX_MF2 = 8476,
8501 PseudoVRGATHER_VX_MF2_MASK = 8477,
8502 PseudoVRGATHER_VX_MF4 = 8478,
8503 PseudoVRGATHER_VX_MF4_MASK = 8479,
8504 PseudoVRGATHER_VX_MF8 = 8480,
8505 PseudoVRGATHER_VX_MF8_MASK = 8481,
8506 PseudoVROL_VV_M1 = 8482,
8507 PseudoVROL_VV_M1_MASK = 8483,
8508 PseudoVROL_VV_M2 = 8484,
8509 PseudoVROL_VV_M2_MASK = 8485,
8510 PseudoVROL_VV_M4 = 8486,
8511 PseudoVROL_VV_M4_MASK = 8487,
8512 PseudoVROL_VV_M8 = 8488,
8513 PseudoVROL_VV_M8_MASK = 8489,
8514 PseudoVROL_VV_MF2 = 8490,
8515 PseudoVROL_VV_MF2_MASK = 8491,
8516 PseudoVROL_VV_MF4 = 8492,
8517 PseudoVROL_VV_MF4_MASK = 8493,
8518 PseudoVROL_VV_MF8 = 8494,
8519 PseudoVROL_VV_MF8_MASK = 8495,
8520 PseudoVROL_VX_M1 = 8496,
8521 PseudoVROL_VX_M1_MASK = 8497,
8522 PseudoVROL_VX_M2 = 8498,
8523 PseudoVROL_VX_M2_MASK = 8499,
8524 PseudoVROL_VX_M4 = 8500,
8525 PseudoVROL_VX_M4_MASK = 8501,
8526 PseudoVROL_VX_M8 = 8502,
8527 PseudoVROL_VX_M8_MASK = 8503,
8528 PseudoVROL_VX_MF2 = 8504,
8529 PseudoVROL_VX_MF2_MASK = 8505,
8530 PseudoVROL_VX_MF4 = 8506,
8531 PseudoVROL_VX_MF4_MASK = 8507,
8532 PseudoVROL_VX_MF8 = 8508,
8533 PseudoVROL_VX_MF8_MASK = 8509,
8534 PseudoVROR_VI_M1 = 8510,
8535 PseudoVROR_VI_M1_MASK = 8511,
8536 PseudoVROR_VI_M2 = 8512,
8537 PseudoVROR_VI_M2_MASK = 8513,
8538 PseudoVROR_VI_M4 = 8514,
8539 PseudoVROR_VI_M4_MASK = 8515,
8540 PseudoVROR_VI_M8 = 8516,
8541 PseudoVROR_VI_M8_MASK = 8517,
8542 PseudoVROR_VI_MF2 = 8518,
8543 PseudoVROR_VI_MF2_MASK = 8519,
8544 PseudoVROR_VI_MF4 = 8520,
8545 PseudoVROR_VI_MF4_MASK = 8521,
8546 PseudoVROR_VI_MF8 = 8522,
8547 PseudoVROR_VI_MF8_MASK = 8523,
8548 PseudoVROR_VV_M1 = 8524,
8549 PseudoVROR_VV_M1_MASK = 8525,
8550 PseudoVROR_VV_M2 = 8526,
8551 PseudoVROR_VV_M2_MASK = 8527,
8552 PseudoVROR_VV_M4 = 8528,
8553 PseudoVROR_VV_M4_MASK = 8529,
8554 PseudoVROR_VV_M8 = 8530,
8555 PseudoVROR_VV_M8_MASK = 8531,
8556 PseudoVROR_VV_MF2 = 8532,
8557 PseudoVROR_VV_MF2_MASK = 8533,
8558 PseudoVROR_VV_MF4 = 8534,
8559 PseudoVROR_VV_MF4_MASK = 8535,
8560 PseudoVROR_VV_MF8 = 8536,
8561 PseudoVROR_VV_MF8_MASK = 8537,
8562 PseudoVROR_VX_M1 = 8538,
8563 PseudoVROR_VX_M1_MASK = 8539,
8564 PseudoVROR_VX_M2 = 8540,
8565 PseudoVROR_VX_M2_MASK = 8541,
8566 PseudoVROR_VX_M4 = 8542,
8567 PseudoVROR_VX_M4_MASK = 8543,
8568 PseudoVROR_VX_M8 = 8544,
8569 PseudoVROR_VX_M8_MASK = 8545,
8570 PseudoVROR_VX_MF2 = 8546,
8571 PseudoVROR_VX_MF2_MASK = 8547,
8572 PseudoVROR_VX_MF4 = 8548,
8573 PseudoVROR_VX_MF4_MASK = 8549,
8574 PseudoVROR_VX_MF8 = 8550,
8575 PseudoVROR_VX_MF8_MASK = 8551,
8576 PseudoVRSUB_VI_M1 = 8552,
8577 PseudoVRSUB_VI_M1_MASK = 8553,
8578 PseudoVRSUB_VI_M2 = 8554,
8579 PseudoVRSUB_VI_M2_MASK = 8555,
8580 PseudoVRSUB_VI_M4 = 8556,
8581 PseudoVRSUB_VI_M4_MASK = 8557,
8582 PseudoVRSUB_VI_M8 = 8558,
8583 PseudoVRSUB_VI_M8_MASK = 8559,
8584 PseudoVRSUB_VI_MF2 = 8560,
8585 PseudoVRSUB_VI_MF2_MASK = 8561,
8586 PseudoVRSUB_VI_MF4 = 8562,
8587 PseudoVRSUB_VI_MF4_MASK = 8563,
8588 PseudoVRSUB_VI_MF8 = 8564,
8589 PseudoVRSUB_VI_MF8_MASK = 8565,
8590 PseudoVRSUB_VX_M1 = 8566,
8591 PseudoVRSUB_VX_M1_MASK = 8567,
8592 PseudoVRSUB_VX_M2 = 8568,
8593 PseudoVRSUB_VX_M2_MASK = 8569,
8594 PseudoVRSUB_VX_M4 = 8570,
8595 PseudoVRSUB_VX_M4_MASK = 8571,
8596 PseudoVRSUB_VX_M8 = 8572,
8597 PseudoVRSUB_VX_M8_MASK = 8573,
8598 PseudoVRSUB_VX_MF2 = 8574,
8599 PseudoVRSUB_VX_MF2_MASK = 8575,
8600 PseudoVRSUB_VX_MF4 = 8576,
8601 PseudoVRSUB_VX_MF4_MASK = 8577,
8602 PseudoVRSUB_VX_MF8 = 8578,
8603 PseudoVRSUB_VX_MF8_MASK = 8579,
8604 PseudoVSADDU_VI_M1 = 8580,
8605 PseudoVSADDU_VI_M1_MASK = 8581,
8606 PseudoVSADDU_VI_M2 = 8582,
8607 PseudoVSADDU_VI_M2_MASK = 8583,
8608 PseudoVSADDU_VI_M4 = 8584,
8609 PseudoVSADDU_VI_M4_MASK = 8585,
8610 PseudoVSADDU_VI_M8 = 8586,
8611 PseudoVSADDU_VI_M8_MASK = 8587,
8612 PseudoVSADDU_VI_MF2 = 8588,
8613 PseudoVSADDU_VI_MF2_MASK = 8589,
8614 PseudoVSADDU_VI_MF4 = 8590,
8615 PseudoVSADDU_VI_MF4_MASK = 8591,
8616 PseudoVSADDU_VI_MF8 = 8592,
8617 PseudoVSADDU_VI_MF8_MASK = 8593,
8618 PseudoVSADDU_VV_M1 = 8594,
8619 PseudoVSADDU_VV_M1_MASK = 8595,
8620 PseudoVSADDU_VV_M2 = 8596,
8621 PseudoVSADDU_VV_M2_MASK = 8597,
8622 PseudoVSADDU_VV_M4 = 8598,
8623 PseudoVSADDU_VV_M4_MASK = 8599,
8624 PseudoVSADDU_VV_M8 = 8600,
8625 PseudoVSADDU_VV_M8_MASK = 8601,
8626 PseudoVSADDU_VV_MF2 = 8602,
8627 PseudoVSADDU_VV_MF2_MASK = 8603,
8628 PseudoVSADDU_VV_MF4 = 8604,
8629 PseudoVSADDU_VV_MF4_MASK = 8605,
8630 PseudoVSADDU_VV_MF8 = 8606,
8631 PseudoVSADDU_VV_MF8_MASK = 8607,
8632 PseudoVSADDU_VX_M1 = 8608,
8633 PseudoVSADDU_VX_M1_MASK = 8609,
8634 PseudoVSADDU_VX_M2 = 8610,
8635 PseudoVSADDU_VX_M2_MASK = 8611,
8636 PseudoVSADDU_VX_M4 = 8612,
8637 PseudoVSADDU_VX_M4_MASK = 8613,
8638 PseudoVSADDU_VX_M8 = 8614,
8639 PseudoVSADDU_VX_M8_MASK = 8615,
8640 PseudoVSADDU_VX_MF2 = 8616,
8641 PseudoVSADDU_VX_MF2_MASK = 8617,
8642 PseudoVSADDU_VX_MF4 = 8618,
8643 PseudoVSADDU_VX_MF4_MASK = 8619,
8644 PseudoVSADDU_VX_MF8 = 8620,
8645 PseudoVSADDU_VX_MF8_MASK = 8621,
8646 PseudoVSADD_VI_M1 = 8622,
8647 PseudoVSADD_VI_M1_MASK = 8623,
8648 PseudoVSADD_VI_M2 = 8624,
8649 PseudoVSADD_VI_M2_MASK = 8625,
8650 PseudoVSADD_VI_M4 = 8626,
8651 PseudoVSADD_VI_M4_MASK = 8627,
8652 PseudoVSADD_VI_M8 = 8628,
8653 PseudoVSADD_VI_M8_MASK = 8629,
8654 PseudoVSADD_VI_MF2 = 8630,
8655 PseudoVSADD_VI_MF2_MASK = 8631,
8656 PseudoVSADD_VI_MF4 = 8632,
8657 PseudoVSADD_VI_MF4_MASK = 8633,
8658 PseudoVSADD_VI_MF8 = 8634,
8659 PseudoVSADD_VI_MF8_MASK = 8635,
8660 PseudoVSADD_VV_M1 = 8636,
8661 PseudoVSADD_VV_M1_MASK = 8637,
8662 PseudoVSADD_VV_M2 = 8638,
8663 PseudoVSADD_VV_M2_MASK = 8639,
8664 PseudoVSADD_VV_M4 = 8640,
8665 PseudoVSADD_VV_M4_MASK = 8641,
8666 PseudoVSADD_VV_M8 = 8642,
8667 PseudoVSADD_VV_M8_MASK = 8643,
8668 PseudoVSADD_VV_MF2 = 8644,
8669 PseudoVSADD_VV_MF2_MASK = 8645,
8670 PseudoVSADD_VV_MF4 = 8646,
8671 PseudoVSADD_VV_MF4_MASK = 8647,
8672 PseudoVSADD_VV_MF8 = 8648,
8673 PseudoVSADD_VV_MF8_MASK = 8649,
8674 PseudoVSADD_VX_M1 = 8650,
8675 PseudoVSADD_VX_M1_MASK = 8651,
8676 PseudoVSADD_VX_M2 = 8652,
8677 PseudoVSADD_VX_M2_MASK = 8653,
8678 PseudoVSADD_VX_M4 = 8654,
8679 PseudoVSADD_VX_M4_MASK = 8655,
8680 PseudoVSADD_VX_M8 = 8656,
8681 PseudoVSADD_VX_M8_MASK = 8657,
8682 PseudoVSADD_VX_MF2 = 8658,
8683 PseudoVSADD_VX_MF2_MASK = 8659,
8684 PseudoVSADD_VX_MF4 = 8660,
8685 PseudoVSADD_VX_MF4_MASK = 8661,
8686 PseudoVSADD_VX_MF8 = 8662,
8687 PseudoVSADD_VX_MF8_MASK = 8663,
8688 PseudoVSBC_VVM_M1 = 8664,
8689 PseudoVSBC_VVM_M2 = 8665,
8690 PseudoVSBC_VVM_M4 = 8666,
8691 PseudoVSBC_VVM_M8 = 8667,
8692 PseudoVSBC_VVM_MF2 = 8668,
8693 PseudoVSBC_VVM_MF4 = 8669,
8694 PseudoVSBC_VVM_MF8 = 8670,
8695 PseudoVSBC_VXM_M1 = 8671,
8696 PseudoVSBC_VXM_M2 = 8672,
8697 PseudoVSBC_VXM_M4 = 8673,
8698 PseudoVSBC_VXM_M8 = 8674,
8699 PseudoVSBC_VXM_MF2 = 8675,
8700 PseudoVSBC_VXM_MF4 = 8676,
8701 PseudoVSBC_VXM_MF8 = 8677,
8702 PseudoVSE16_V_M1 = 8678,
8703 PseudoVSE16_V_M1_MASK = 8679,
8704 PseudoVSE16_V_M2 = 8680,
8705 PseudoVSE16_V_M2_MASK = 8681,
8706 PseudoVSE16_V_M4 = 8682,
8707 PseudoVSE16_V_M4_MASK = 8683,
8708 PseudoVSE16_V_M8 = 8684,
8709 PseudoVSE16_V_M8_MASK = 8685,
8710 PseudoVSE16_V_MF2 = 8686,
8711 PseudoVSE16_V_MF2_MASK = 8687,
8712 PseudoVSE16_V_MF4 = 8688,
8713 PseudoVSE16_V_MF4_MASK = 8689,
8714 PseudoVSE32_V_M1 = 8690,
8715 PseudoVSE32_V_M1_MASK = 8691,
8716 PseudoVSE32_V_M2 = 8692,
8717 PseudoVSE32_V_M2_MASK = 8693,
8718 PseudoVSE32_V_M4 = 8694,
8719 PseudoVSE32_V_M4_MASK = 8695,
8720 PseudoVSE32_V_M8 = 8696,
8721 PseudoVSE32_V_M8_MASK = 8697,
8722 PseudoVSE32_V_MF2 = 8698,
8723 PseudoVSE32_V_MF2_MASK = 8699,
8724 PseudoVSE64_V_M1 = 8700,
8725 PseudoVSE64_V_M1_MASK = 8701,
8726 PseudoVSE64_V_M2 = 8702,
8727 PseudoVSE64_V_M2_MASK = 8703,
8728 PseudoVSE64_V_M4 = 8704,
8729 PseudoVSE64_V_M4_MASK = 8705,
8730 PseudoVSE64_V_M8 = 8706,
8731 PseudoVSE64_V_M8_MASK = 8707,
8732 PseudoVSE8_V_M1 = 8708,
8733 PseudoVSE8_V_M1_MASK = 8709,
8734 PseudoVSE8_V_M2 = 8710,
8735 PseudoVSE8_V_M2_MASK = 8711,
8736 PseudoVSE8_V_M4 = 8712,
8737 PseudoVSE8_V_M4_MASK = 8713,
8738 PseudoVSE8_V_M8 = 8714,
8739 PseudoVSE8_V_M8_MASK = 8715,
8740 PseudoVSE8_V_MF2 = 8716,
8741 PseudoVSE8_V_MF2_MASK = 8717,
8742 PseudoVSE8_V_MF4 = 8718,
8743 PseudoVSE8_V_MF4_MASK = 8719,
8744 PseudoVSE8_V_MF8 = 8720,
8745 PseudoVSE8_V_MF8_MASK = 8721,
8746 PseudoVSETIVLI = 8722,
8747 PseudoVSETVLI = 8723,
8748 PseudoVSETVLIX0 = 8724,
8749 PseudoVSEXT_VF2_M1 = 8725,
8750 PseudoVSEXT_VF2_M1_MASK = 8726,
8751 PseudoVSEXT_VF2_M2 = 8727,
8752 PseudoVSEXT_VF2_M2_MASK = 8728,
8753 PseudoVSEXT_VF2_M4 = 8729,
8754 PseudoVSEXT_VF2_M4_MASK = 8730,
8755 PseudoVSEXT_VF2_M8 = 8731,
8756 PseudoVSEXT_VF2_M8_MASK = 8732,
8757 PseudoVSEXT_VF2_MF2 = 8733,
8758 PseudoVSEXT_VF2_MF2_MASK = 8734,
8759 PseudoVSEXT_VF2_MF4 = 8735,
8760 PseudoVSEXT_VF2_MF4_MASK = 8736,
8761 PseudoVSEXT_VF4_M1 = 8737,
8762 PseudoVSEXT_VF4_M1_MASK = 8738,
8763 PseudoVSEXT_VF4_M2 = 8739,
8764 PseudoVSEXT_VF4_M2_MASK = 8740,
8765 PseudoVSEXT_VF4_M4 = 8741,
8766 PseudoVSEXT_VF4_M4_MASK = 8742,
8767 PseudoVSEXT_VF4_M8 = 8743,
8768 PseudoVSEXT_VF4_M8_MASK = 8744,
8769 PseudoVSEXT_VF4_MF2 = 8745,
8770 PseudoVSEXT_VF4_MF2_MASK = 8746,
8771 PseudoVSEXT_VF8_M1 = 8747,
8772 PseudoVSEXT_VF8_M1_MASK = 8748,
8773 PseudoVSEXT_VF8_M2 = 8749,
8774 PseudoVSEXT_VF8_M2_MASK = 8750,
8775 PseudoVSEXT_VF8_M4 = 8751,
8776 PseudoVSEXT_VF8_M4_MASK = 8752,
8777 PseudoVSEXT_VF8_M8 = 8753,
8778 PseudoVSEXT_VF8_M8_MASK = 8754,
8779 PseudoVSHA2CH_VV_M1 = 8755,
8780 PseudoVSHA2CH_VV_M2 = 8756,
8781 PseudoVSHA2CH_VV_M4 = 8757,
8782 PseudoVSHA2CH_VV_M8 = 8758,
8783 PseudoVSHA2CH_VV_MF2 = 8759,
8784 PseudoVSHA2CL_VV_M1 = 8760,
8785 PseudoVSHA2CL_VV_M2 = 8761,
8786 PseudoVSHA2CL_VV_M4 = 8762,
8787 PseudoVSHA2CL_VV_M8 = 8763,
8788 PseudoVSHA2CL_VV_MF2 = 8764,
8789 PseudoVSHA2MS_VV_M1 = 8765,
8790 PseudoVSHA2MS_VV_M2 = 8766,
8791 PseudoVSHA2MS_VV_M4 = 8767,
8792 PseudoVSHA2MS_VV_M8 = 8768,
8793 PseudoVSHA2MS_VV_MF2 = 8769,
8794 PseudoVSLIDE1DOWN_VX_M1 = 8770,
8795 PseudoVSLIDE1DOWN_VX_M1_MASK = 8771,
8796 PseudoVSLIDE1DOWN_VX_M2 = 8772,
8797 PseudoVSLIDE1DOWN_VX_M2_MASK = 8773,
8798 PseudoVSLIDE1DOWN_VX_M4 = 8774,
8799 PseudoVSLIDE1DOWN_VX_M4_MASK = 8775,
8800 PseudoVSLIDE1DOWN_VX_M8 = 8776,
8801 PseudoVSLIDE1DOWN_VX_M8_MASK = 8777,
8802 PseudoVSLIDE1DOWN_VX_MF2 = 8778,
8803 PseudoVSLIDE1DOWN_VX_MF2_MASK = 8779,
8804 PseudoVSLIDE1DOWN_VX_MF4 = 8780,
8805 PseudoVSLIDE1DOWN_VX_MF4_MASK = 8781,
8806 PseudoVSLIDE1DOWN_VX_MF8 = 8782,
8807 PseudoVSLIDE1DOWN_VX_MF8_MASK = 8783,
8808 PseudoVSLIDE1UP_VX_M1 = 8784,
8809 PseudoVSLIDE1UP_VX_M1_MASK = 8785,
8810 PseudoVSLIDE1UP_VX_M2 = 8786,
8811 PseudoVSLIDE1UP_VX_M2_MASK = 8787,
8812 PseudoVSLIDE1UP_VX_M4 = 8788,
8813 PseudoVSLIDE1UP_VX_M4_MASK = 8789,
8814 PseudoVSLIDE1UP_VX_M8 = 8790,
8815 PseudoVSLIDE1UP_VX_M8_MASK = 8791,
8816 PseudoVSLIDE1UP_VX_MF2 = 8792,
8817 PseudoVSLIDE1UP_VX_MF2_MASK = 8793,
8818 PseudoVSLIDE1UP_VX_MF4 = 8794,
8819 PseudoVSLIDE1UP_VX_MF4_MASK = 8795,
8820 PseudoVSLIDE1UP_VX_MF8 = 8796,
8821 PseudoVSLIDE1UP_VX_MF8_MASK = 8797,
8822 PseudoVSLIDEDOWN_VI_M1 = 8798,
8823 PseudoVSLIDEDOWN_VI_M1_MASK = 8799,
8824 PseudoVSLIDEDOWN_VI_M2 = 8800,
8825 PseudoVSLIDEDOWN_VI_M2_MASK = 8801,
8826 PseudoVSLIDEDOWN_VI_M4 = 8802,
8827 PseudoVSLIDEDOWN_VI_M4_MASK = 8803,
8828 PseudoVSLIDEDOWN_VI_M8 = 8804,
8829 PseudoVSLIDEDOWN_VI_M8_MASK = 8805,
8830 PseudoVSLIDEDOWN_VI_MF2 = 8806,
8831 PseudoVSLIDEDOWN_VI_MF2_MASK = 8807,
8832 PseudoVSLIDEDOWN_VI_MF4 = 8808,
8833 PseudoVSLIDEDOWN_VI_MF4_MASK = 8809,
8834 PseudoVSLIDEDOWN_VI_MF8 = 8810,
8835 PseudoVSLIDEDOWN_VI_MF8_MASK = 8811,
8836 PseudoVSLIDEDOWN_VX_M1 = 8812,
8837 PseudoVSLIDEDOWN_VX_M1_MASK = 8813,
8838 PseudoVSLIDEDOWN_VX_M2 = 8814,
8839 PseudoVSLIDEDOWN_VX_M2_MASK = 8815,
8840 PseudoVSLIDEDOWN_VX_M4 = 8816,
8841 PseudoVSLIDEDOWN_VX_M4_MASK = 8817,
8842 PseudoVSLIDEDOWN_VX_M8 = 8818,
8843 PseudoVSLIDEDOWN_VX_M8_MASK = 8819,
8844 PseudoVSLIDEDOWN_VX_MF2 = 8820,
8845 PseudoVSLIDEDOWN_VX_MF2_MASK = 8821,
8846 PseudoVSLIDEDOWN_VX_MF4 = 8822,
8847 PseudoVSLIDEDOWN_VX_MF4_MASK = 8823,
8848 PseudoVSLIDEDOWN_VX_MF8 = 8824,
8849 PseudoVSLIDEDOWN_VX_MF8_MASK = 8825,
8850 PseudoVSLIDEUP_VI_M1 = 8826,
8851 PseudoVSLIDEUP_VI_M1_MASK = 8827,
8852 PseudoVSLIDEUP_VI_M2 = 8828,
8853 PseudoVSLIDEUP_VI_M2_MASK = 8829,
8854 PseudoVSLIDEUP_VI_M4 = 8830,
8855 PseudoVSLIDEUP_VI_M4_MASK = 8831,
8856 PseudoVSLIDEUP_VI_M8 = 8832,
8857 PseudoVSLIDEUP_VI_M8_MASK = 8833,
8858 PseudoVSLIDEUP_VI_MF2 = 8834,
8859 PseudoVSLIDEUP_VI_MF2_MASK = 8835,
8860 PseudoVSLIDEUP_VI_MF4 = 8836,
8861 PseudoVSLIDEUP_VI_MF4_MASK = 8837,
8862 PseudoVSLIDEUP_VI_MF8 = 8838,
8863 PseudoVSLIDEUP_VI_MF8_MASK = 8839,
8864 PseudoVSLIDEUP_VX_M1 = 8840,
8865 PseudoVSLIDEUP_VX_M1_MASK = 8841,
8866 PseudoVSLIDEUP_VX_M2 = 8842,
8867 PseudoVSLIDEUP_VX_M2_MASK = 8843,
8868 PseudoVSLIDEUP_VX_M4 = 8844,
8869 PseudoVSLIDEUP_VX_M4_MASK = 8845,
8870 PseudoVSLIDEUP_VX_M8 = 8846,
8871 PseudoVSLIDEUP_VX_M8_MASK = 8847,
8872 PseudoVSLIDEUP_VX_MF2 = 8848,
8873 PseudoVSLIDEUP_VX_MF2_MASK = 8849,
8874 PseudoVSLIDEUP_VX_MF4 = 8850,
8875 PseudoVSLIDEUP_VX_MF4_MASK = 8851,
8876 PseudoVSLIDEUP_VX_MF8 = 8852,
8877 PseudoVSLIDEUP_VX_MF8_MASK = 8853,
8878 PseudoVSLL_VI_M1 = 8854,
8879 PseudoVSLL_VI_M1_MASK = 8855,
8880 PseudoVSLL_VI_M2 = 8856,
8881 PseudoVSLL_VI_M2_MASK = 8857,
8882 PseudoVSLL_VI_M4 = 8858,
8883 PseudoVSLL_VI_M4_MASK = 8859,
8884 PseudoVSLL_VI_M8 = 8860,
8885 PseudoVSLL_VI_M8_MASK = 8861,
8886 PseudoVSLL_VI_MF2 = 8862,
8887 PseudoVSLL_VI_MF2_MASK = 8863,
8888 PseudoVSLL_VI_MF4 = 8864,
8889 PseudoVSLL_VI_MF4_MASK = 8865,
8890 PseudoVSLL_VI_MF8 = 8866,
8891 PseudoVSLL_VI_MF8_MASK = 8867,
8892 PseudoVSLL_VV_M1 = 8868,
8893 PseudoVSLL_VV_M1_MASK = 8869,
8894 PseudoVSLL_VV_M2 = 8870,
8895 PseudoVSLL_VV_M2_MASK = 8871,
8896 PseudoVSLL_VV_M4 = 8872,
8897 PseudoVSLL_VV_M4_MASK = 8873,
8898 PseudoVSLL_VV_M8 = 8874,
8899 PseudoVSLL_VV_M8_MASK = 8875,
8900 PseudoVSLL_VV_MF2 = 8876,
8901 PseudoVSLL_VV_MF2_MASK = 8877,
8902 PseudoVSLL_VV_MF4 = 8878,
8903 PseudoVSLL_VV_MF4_MASK = 8879,
8904 PseudoVSLL_VV_MF8 = 8880,
8905 PseudoVSLL_VV_MF8_MASK = 8881,
8906 PseudoVSLL_VX_M1 = 8882,
8907 PseudoVSLL_VX_M1_MASK = 8883,
8908 PseudoVSLL_VX_M2 = 8884,
8909 PseudoVSLL_VX_M2_MASK = 8885,
8910 PseudoVSLL_VX_M4 = 8886,
8911 PseudoVSLL_VX_M4_MASK = 8887,
8912 PseudoVSLL_VX_M8 = 8888,
8913 PseudoVSLL_VX_M8_MASK = 8889,
8914 PseudoVSLL_VX_MF2 = 8890,
8915 PseudoVSLL_VX_MF2_MASK = 8891,
8916 PseudoVSLL_VX_MF4 = 8892,
8917 PseudoVSLL_VX_MF4_MASK = 8893,
8918 PseudoVSLL_VX_MF8 = 8894,
8919 PseudoVSLL_VX_MF8_MASK = 8895,
8920 PseudoVSM3C_VI_M1 = 8896,
8921 PseudoVSM3C_VI_M2 = 8897,
8922 PseudoVSM3C_VI_M4 = 8898,
8923 PseudoVSM3C_VI_M8 = 8899,
8924 PseudoVSM3C_VI_MF2 = 8900,
8925 PseudoVSM3ME_VV_M1 = 8901,
8926 PseudoVSM3ME_VV_M2 = 8902,
8927 PseudoVSM3ME_VV_M4 = 8903,
8928 PseudoVSM3ME_VV_M8 = 8904,
8929 PseudoVSM3ME_VV_MF2 = 8905,
8930 PseudoVSM4K_VI_M1 = 8906,
8931 PseudoVSM4K_VI_M2 = 8907,
8932 PseudoVSM4K_VI_M4 = 8908,
8933 PseudoVSM4K_VI_M8 = 8909,
8934 PseudoVSM4K_VI_MF2 = 8910,
8935 PseudoVSM4R_VS_M1_M1 = 8911,
8936 PseudoVSM4R_VS_M1_MF2 = 8912,
8937 PseudoVSM4R_VS_M1_MF4 = 8913,
8938 PseudoVSM4R_VS_M1_MF8 = 8914,
8939 PseudoVSM4R_VS_M2_M1 = 8915,
8940 PseudoVSM4R_VS_M2_M2 = 8916,
8941 PseudoVSM4R_VS_M2_MF2 = 8917,
8942 PseudoVSM4R_VS_M2_MF4 = 8918,
8943 PseudoVSM4R_VS_M2_MF8 = 8919,
8944 PseudoVSM4R_VS_M4_M1 = 8920,
8945 PseudoVSM4R_VS_M4_M2 = 8921,
8946 PseudoVSM4R_VS_M4_M4 = 8922,
8947 PseudoVSM4R_VS_M4_MF2 = 8923,
8948 PseudoVSM4R_VS_M4_MF4 = 8924,
8949 PseudoVSM4R_VS_M4_MF8 = 8925,
8950 PseudoVSM4R_VS_M8_M1 = 8926,
8951 PseudoVSM4R_VS_M8_M2 = 8927,
8952 PseudoVSM4R_VS_M8_M4 = 8928,
8953 PseudoVSM4R_VS_M8_MF2 = 8929,
8954 PseudoVSM4R_VS_M8_MF4 = 8930,
8955 PseudoVSM4R_VS_M8_MF8 = 8931,
8956 PseudoVSM4R_VS_MF2_MF2 = 8932,
8957 PseudoVSM4R_VS_MF2_MF4 = 8933,
8958 PseudoVSM4R_VS_MF2_MF8 = 8934,
8959 PseudoVSM4R_VV_M1 = 8935,
8960 PseudoVSM4R_VV_M2 = 8936,
8961 PseudoVSM4R_VV_M4 = 8937,
8962 PseudoVSM4R_VV_M8 = 8938,
8963 PseudoVSM4R_VV_MF2 = 8939,
8964 PseudoVSMUL_VV_M1 = 8940,
8965 PseudoVSMUL_VV_M1_MASK = 8941,
8966 PseudoVSMUL_VV_M2 = 8942,
8967 PseudoVSMUL_VV_M2_MASK = 8943,
8968 PseudoVSMUL_VV_M4 = 8944,
8969 PseudoVSMUL_VV_M4_MASK = 8945,
8970 PseudoVSMUL_VV_M8 = 8946,
8971 PseudoVSMUL_VV_M8_MASK = 8947,
8972 PseudoVSMUL_VV_MF2 = 8948,
8973 PseudoVSMUL_VV_MF2_MASK = 8949,
8974 PseudoVSMUL_VV_MF4 = 8950,
8975 PseudoVSMUL_VV_MF4_MASK = 8951,
8976 PseudoVSMUL_VV_MF8 = 8952,
8977 PseudoVSMUL_VV_MF8_MASK = 8953,
8978 PseudoVSMUL_VX_M1 = 8954,
8979 PseudoVSMUL_VX_M1_MASK = 8955,
8980 PseudoVSMUL_VX_M2 = 8956,
8981 PseudoVSMUL_VX_M2_MASK = 8957,
8982 PseudoVSMUL_VX_M4 = 8958,
8983 PseudoVSMUL_VX_M4_MASK = 8959,
8984 PseudoVSMUL_VX_M8 = 8960,
8985 PseudoVSMUL_VX_M8_MASK = 8961,
8986 PseudoVSMUL_VX_MF2 = 8962,
8987 PseudoVSMUL_VX_MF2_MASK = 8963,
8988 PseudoVSMUL_VX_MF4 = 8964,
8989 PseudoVSMUL_VX_MF4_MASK = 8965,
8990 PseudoVSMUL_VX_MF8 = 8966,
8991 PseudoVSMUL_VX_MF8_MASK = 8967,
8992 PseudoVSM_V_B1 = 8968,
8993 PseudoVSM_V_B16 = 8969,
8994 PseudoVSM_V_B2 = 8970,
8995 PseudoVSM_V_B32 = 8971,
8996 PseudoVSM_V_B4 = 8972,
8997 PseudoVSM_V_B64 = 8973,
8998 PseudoVSM_V_B8 = 8974,
8999 PseudoVSOXEI16_V_M1_M1 = 8975,
9000 PseudoVSOXEI16_V_M1_M1_MASK = 8976,
9001 PseudoVSOXEI16_V_M1_M2 = 8977,
9002 PseudoVSOXEI16_V_M1_M2_MASK = 8978,
9003 PseudoVSOXEI16_V_M1_M4 = 8979,
9004 PseudoVSOXEI16_V_M1_M4_MASK = 8980,
9005 PseudoVSOXEI16_V_M1_MF2 = 8981,
9006 PseudoVSOXEI16_V_M1_MF2_MASK = 8982,
9007 PseudoVSOXEI16_V_M2_M1 = 8983,
9008 PseudoVSOXEI16_V_M2_M1_MASK = 8984,
9009 PseudoVSOXEI16_V_M2_M2 = 8985,
9010 PseudoVSOXEI16_V_M2_M2_MASK = 8986,
9011 PseudoVSOXEI16_V_M2_M4 = 8987,
9012 PseudoVSOXEI16_V_M2_M4_MASK = 8988,
9013 PseudoVSOXEI16_V_M2_M8 = 8989,
9014 PseudoVSOXEI16_V_M2_M8_MASK = 8990,
9015 PseudoVSOXEI16_V_M4_M2 = 8991,
9016 PseudoVSOXEI16_V_M4_M2_MASK = 8992,
9017 PseudoVSOXEI16_V_M4_M4 = 8993,
9018 PseudoVSOXEI16_V_M4_M4_MASK = 8994,
9019 PseudoVSOXEI16_V_M4_M8 = 8995,
9020 PseudoVSOXEI16_V_M4_M8_MASK = 8996,
9021 PseudoVSOXEI16_V_M8_M4 = 8997,
9022 PseudoVSOXEI16_V_M8_M4_MASK = 8998,
9023 PseudoVSOXEI16_V_M8_M8 = 8999,
9024 PseudoVSOXEI16_V_M8_M8_MASK = 9000,
9025 PseudoVSOXEI16_V_MF2_M1 = 9001,
9026 PseudoVSOXEI16_V_MF2_M1_MASK = 9002,
9027 PseudoVSOXEI16_V_MF2_M2 = 9003,
9028 PseudoVSOXEI16_V_MF2_M2_MASK = 9004,
9029 PseudoVSOXEI16_V_MF2_MF2 = 9005,
9030 PseudoVSOXEI16_V_MF2_MF2_MASK = 9006,
9031 PseudoVSOXEI16_V_MF2_MF4 = 9007,
9032 PseudoVSOXEI16_V_MF2_MF4_MASK = 9008,
9033 PseudoVSOXEI16_V_MF4_M1 = 9009,
9034 PseudoVSOXEI16_V_MF4_M1_MASK = 9010,
9035 PseudoVSOXEI16_V_MF4_MF2 = 9011,
9036 PseudoVSOXEI16_V_MF4_MF2_MASK = 9012,
9037 PseudoVSOXEI16_V_MF4_MF4 = 9013,
9038 PseudoVSOXEI16_V_MF4_MF4_MASK = 9014,
9039 PseudoVSOXEI16_V_MF4_MF8 = 9015,
9040 PseudoVSOXEI16_V_MF4_MF8_MASK = 9016,
9041 PseudoVSOXEI32_V_M1_M1 = 9017,
9042 PseudoVSOXEI32_V_M1_M1_MASK = 9018,
9043 PseudoVSOXEI32_V_M1_M2 = 9019,
9044 PseudoVSOXEI32_V_M1_M2_MASK = 9020,
9045 PseudoVSOXEI32_V_M1_MF2 = 9021,
9046 PseudoVSOXEI32_V_M1_MF2_MASK = 9022,
9047 PseudoVSOXEI32_V_M1_MF4 = 9023,
9048 PseudoVSOXEI32_V_M1_MF4_MASK = 9024,
9049 PseudoVSOXEI32_V_M2_M1 = 9025,
9050 PseudoVSOXEI32_V_M2_M1_MASK = 9026,
9051 PseudoVSOXEI32_V_M2_M2 = 9027,
9052 PseudoVSOXEI32_V_M2_M2_MASK = 9028,
9053 PseudoVSOXEI32_V_M2_M4 = 9029,
9054 PseudoVSOXEI32_V_M2_M4_MASK = 9030,
9055 PseudoVSOXEI32_V_M2_MF2 = 9031,
9056 PseudoVSOXEI32_V_M2_MF2_MASK = 9032,
9057 PseudoVSOXEI32_V_M4_M1 = 9033,
9058 PseudoVSOXEI32_V_M4_M1_MASK = 9034,
9059 PseudoVSOXEI32_V_M4_M2 = 9035,
9060 PseudoVSOXEI32_V_M4_M2_MASK = 9036,
9061 PseudoVSOXEI32_V_M4_M4 = 9037,
9062 PseudoVSOXEI32_V_M4_M4_MASK = 9038,
9063 PseudoVSOXEI32_V_M4_M8 = 9039,
9064 PseudoVSOXEI32_V_M4_M8_MASK = 9040,
9065 PseudoVSOXEI32_V_M8_M2 = 9041,
9066 PseudoVSOXEI32_V_M8_M2_MASK = 9042,
9067 PseudoVSOXEI32_V_M8_M4 = 9043,
9068 PseudoVSOXEI32_V_M8_M4_MASK = 9044,
9069 PseudoVSOXEI32_V_M8_M8 = 9045,
9070 PseudoVSOXEI32_V_M8_M8_MASK = 9046,
9071 PseudoVSOXEI32_V_MF2_M1 = 9047,
9072 PseudoVSOXEI32_V_MF2_M1_MASK = 9048,
9073 PseudoVSOXEI32_V_MF2_MF2 = 9049,
9074 PseudoVSOXEI32_V_MF2_MF2_MASK = 9050,
9075 PseudoVSOXEI32_V_MF2_MF4 = 9051,
9076 PseudoVSOXEI32_V_MF2_MF4_MASK = 9052,
9077 PseudoVSOXEI32_V_MF2_MF8 = 9053,
9078 PseudoVSOXEI32_V_MF2_MF8_MASK = 9054,
9079 PseudoVSOXEI64_V_M1_M1 = 9055,
9080 PseudoVSOXEI64_V_M1_M1_MASK = 9056,
9081 PseudoVSOXEI64_V_M1_MF2 = 9057,
9082 PseudoVSOXEI64_V_M1_MF2_MASK = 9058,
9083 PseudoVSOXEI64_V_M1_MF4 = 9059,
9084 PseudoVSOXEI64_V_M1_MF4_MASK = 9060,
9085 PseudoVSOXEI64_V_M1_MF8 = 9061,
9086 PseudoVSOXEI64_V_M1_MF8_MASK = 9062,
9087 PseudoVSOXEI64_V_M2_M1 = 9063,
9088 PseudoVSOXEI64_V_M2_M1_MASK = 9064,
9089 PseudoVSOXEI64_V_M2_M2 = 9065,
9090 PseudoVSOXEI64_V_M2_M2_MASK = 9066,
9091 PseudoVSOXEI64_V_M2_MF2 = 9067,
9092 PseudoVSOXEI64_V_M2_MF2_MASK = 9068,
9093 PseudoVSOXEI64_V_M2_MF4 = 9069,
9094 PseudoVSOXEI64_V_M2_MF4_MASK = 9070,
9095 PseudoVSOXEI64_V_M4_M1 = 9071,
9096 PseudoVSOXEI64_V_M4_M1_MASK = 9072,
9097 PseudoVSOXEI64_V_M4_M2 = 9073,
9098 PseudoVSOXEI64_V_M4_M2_MASK = 9074,
9099 PseudoVSOXEI64_V_M4_M4 = 9075,
9100 PseudoVSOXEI64_V_M4_M4_MASK = 9076,
9101 PseudoVSOXEI64_V_M4_MF2 = 9077,
9102 PseudoVSOXEI64_V_M4_MF2_MASK = 9078,
9103 PseudoVSOXEI64_V_M8_M1 = 9079,
9104 PseudoVSOXEI64_V_M8_M1_MASK = 9080,
9105 PseudoVSOXEI64_V_M8_M2 = 9081,
9106 PseudoVSOXEI64_V_M8_M2_MASK = 9082,
9107 PseudoVSOXEI64_V_M8_M4 = 9083,
9108 PseudoVSOXEI64_V_M8_M4_MASK = 9084,
9109 PseudoVSOXEI64_V_M8_M8 = 9085,
9110 PseudoVSOXEI64_V_M8_M8_MASK = 9086,
9111 PseudoVSOXEI8_V_M1_M1 = 9087,
9112 PseudoVSOXEI8_V_M1_M1_MASK = 9088,
9113 PseudoVSOXEI8_V_M1_M2 = 9089,
9114 PseudoVSOXEI8_V_M1_M2_MASK = 9090,
9115 PseudoVSOXEI8_V_M1_M4 = 9091,
9116 PseudoVSOXEI8_V_M1_M4_MASK = 9092,
9117 PseudoVSOXEI8_V_M1_M8 = 9093,
9118 PseudoVSOXEI8_V_M1_M8_MASK = 9094,
9119 PseudoVSOXEI8_V_M2_M2 = 9095,
9120 PseudoVSOXEI8_V_M2_M2_MASK = 9096,
9121 PseudoVSOXEI8_V_M2_M4 = 9097,
9122 PseudoVSOXEI8_V_M2_M4_MASK = 9098,
9123 PseudoVSOXEI8_V_M2_M8 = 9099,
9124 PseudoVSOXEI8_V_M2_M8_MASK = 9100,
9125 PseudoVSOXEI8_V_M4_M4 = 9101,
9126 PseudoVSOXEI8_V_M4_M4_MASK = 9102,
9127 PseudoVSOXEI8_V_M4_M8 = 9103,
9128 PseudoVSOXEI8_V_M4_M8_MASK = 9104,
9129 PseudoVSOXEI8_V_M8_M8 = 9105,
9130 PseudoVSOXEI8_V_M8_M8_MASK = 9106,
9131 PseudoVSOXEI8_V_MF2_M1 = 9107,
9132 PseudoVSOXEI8_V_MF2_M1_MASK = 9108,
9133 PseudoVSOXEI8_V_MF2_M2 = 9109,
9134 PseudoVSOXEI8_V_MF2_M2_MASK = 9110,
9135 PseudoVSOXEI8_V_MF2_M4 = 9111,
9136 PseudoVSOXEI8_V_MF2_M4_MASK = 9112,
9137 PseudoVSOXEI8_V_MF2_MF2 = 9113,
9138 PseudoVSOXEI8_V_MF2_MF2_MASK = 9114,
9139 PseudoVSOXEI8_V_MF4_M1 = 9115,
9140 PseudoVSOXEI8_V_MF4_M1_MASK = 9116,
9141 PseudoVSOXEI8_V_MF4_M2 = 9117,
9142 PseudoVSOXEI8_V_MF4_M2_MASK = 9118,
9143 PseudoVSOXEI8_V_MF4_MF2 = 9119,
9144 PseudoVSOXEI8_V_MF4_MF2_MASK = 9120,
9145 PseudoVSOXEI8_V_MF4_MF4 = 9121,
9146 PseudoVSOXEI8_V_MF4_MF4_MASK = 9122,
9147 PseudoVSOXEI8_V_MF8_M1 = 9123,
9148 PseudoVSOXEI8_V_MF8_M1_MASK = 9124,
9149 PseudoVSOXEI8_V_MF8_MF2 = 9125,
9150 PseudoVSOXEI8_V_MF8_MF2_MASK = 9126,
9151 PseudoVSOXEI8_V_MF8_MF4 = 9127,
9152 PseudoVSOXEI8_V_MF8_MF4_MASK = 9128,
9153 PseudoVSOXEI8_V_MF8_MF8 = 9129,
9154 PseudoVSOXEI8_V_MF8_MF8_MASK = 9130,
9155 PseudoVSOXSEG2EI16_V_M1_M1 = 9131,
9156 PseudoVSOXSEG2EI16_V_M1_M1_MASK = 9132,
9157 PseudoVSOXSEG2EI16_V_M1_M2 = 9133,
9158 PseudoVSOXSEG2EI16_V_M1_M2_MASK = 9134,
9159 PseudoVSOXSEG2EI16_V_M1_M4 = 9135,
9160 PseudoVSOXSEG2EI16_V_M1_M4_MASK = 9136,
9161 PseudoVSOXSEG2EI16_V_M1_MF2 = 9137,
9162 PseudoVSOXSEG2EI16_V_M1_MF2_MASK = 9138,
9163 PseudoVSOXSEG2EI16_V_M2_M1 = 9139,
9164 PseudoVSOXSEG2EI16_V_M2_M1_MASK = 9140,
9165 PseudoVSOXSEG2EI16_V_M2_M2 = 9141,
9166 PseudoVSOXSEG2EI16_V_M2_M2_MASK = 9142,
9167 PseudoVSOXSEG2EI16_V_M2_M4 = 9143,
9168 PseudoVSOXSEG2EI16_V_M2_M4_MASK = 9144,
9169 PseudoVSOXSEG2EI16_V_M4_M2 = 9145,
9170 PseudoVSOXSEG2EI16_V_M4_M2_MASK = 9146,
9171 PseudoVSOXSEG2EI16_V_M4_M4 = 9147,
9172 PseudoVSOXSEG2EI16_V_M4_M4_MASK = 9148,
9173 PseudoVSOXSEG2EI16_V_M8_M4 = 9149,
9174 PseudoVSOXSEG2EI16_V_M8_M4_MASK = 9150,
9175 PseudoVSOXSEG2EI16_V_MF2_M1 = 9151,
9176 PseudoVSOXSEG2EI16_V_MF2_M1_MASK = 9152,
9177 PseudoVSOXSEG2EI16_V_MF2_M2 = 9153,
9178 PseudoVSOXSEG2EI16_V_MF2_M2_MASK = 9154,
9179 PseudoVSOXSEG2EI16_V_MF2_MF2 = 9155,
9180 PseudoVSOXSEG2EI16_V_MF2_MF2_MASK = 9156,
9181 PseudoVSOXSEG2EI16_V_MF2_MF4 = 9157,
9182 PseudoVSOXSEG2EI16_V_MF2_MF4_MASK = 9158,
9183 PseudoVSOXSEG2EI16_V_MF4_M1 = 9159,
9184 PseudoVSOXSEG2EI16_V_MF4_M1_MASK = 9160,
9185 PseudoVSOXSEG2EI16_V_MF4_MF2 = 9161,
9186 PseudoVSOXSEG2EI16_V_MF4_MF2_MASK = 9162,
9187 PseudoVSOXSEG2EI16_V_MF4_MF4 = 9163,
9188 PseudoVSOXSEG2EI16_V_MF4_MF4_MASK = 9164,
9189 PseudoVSOXSEG2EI16_V_MF4_MF8 = 9165,
9190 PseudoVSOXSEG2EI16_V_MF4_MF8_MASK = 9166,
9191 PseudoVSOXSEG2EI32_V_M1_M1 = 9167,
9192 PseudoVSOXSEG2EI32_V_M1_M1_MASK = 9168,
9193 PseudoVSOXSEG2EI32_V_M1_M2 = 9169,
9194 PseudoVSOXSEG2EI32_V_M1_M2_MASK = 9170,
9195 PseudoVSOXSEG2EI32_V_M1_MF2 = 9171,
9196 PseudoVSOXSEG2EI32_V_M1_MF2_MASK = 9172,
9197 PseudoVSOXSEG2EI32_V_M1_MF4 = 9173,
9198 PseudoVSOXSEG2EI32_V_M1_MF4_MASK = 9174,
9199 PseudoVSOXSEG2EI32_V_M2_M1 = 9175,
9200 PseudoVSOXSEG2EI32_V_M2_M1_MASK = 9176,
9201 PseudoVSOXSEG2EI32_V_M2_M2 = 9177,
9202 PseudoVSOXSEG2EI32_V_M2_M2_MASK = 9178,
9203 PseudoVSOXSEG2EI32_V_M2_M4 = 9179,
9204 PseudoVSOXSEG2EI32_V_M2_M4_MASK = 9180,
9205 PseudoVSOXSEG2EI32_V_M2_MF2 = 9181,
9206 PseudoVSOXSEG2EI32_V_M2_MF2_MASK = 9182,
9207 PseudoVSOXSEG2EI32_V_M4_M1 = 9183,
9208 PseudoVSOXSEG2EI32_V_M4_M1_MASK = 9184,
9209 PseudoVSOXSEG2EI32_V_M4_M2 = 9185,
9210 PseudoVSOXSEG2EI32_V_M4_M2_MASK = 9186,
9211 PseudoVSOXSEG2EI32_V_M4_M4 = 9187,
9212 PseudoVSOXSEG2EI32_V_M4_M4_MASK = 9188,
9213 PseudoVSOXSEG2EI32_V_M8_M2 = 9189,
9214 PseudoVSOXSEG2EI32_V_M8_M2_MASK = 9190,
9215 PseudoVSOXSEG2EI32_V_M8_M4 = 9191,
9216 PseudoVSOXSEG2EI32_V_M8_M4_MASK = 9192,
9217 PseudoVSOXSEG2EI32_V_MF2_M1 = 9193,
9218 PseudoVSOXSEG2EI32_V_MF2_M1_MASK = 9194,
9219 PseudoVSOXSEG2EI32_V_MF2_MF2 = 9195,
9220 PseudoVSOXSEG2EI32_V_MF2_MF2_MASK = 9196,
9221 PseudoVSOXSEG2EI32_V_MF2_MF4 = 9197,
9222 PseudoVSOXSEG2EI32_V_MF2_MF4_MASK = 9198,
9223 PseudoVSOXSEG2EI32_V_MF2_MF8 = 9199,
9224 PseudoVSOXSEG2EI32_V_MF2_MF8_MASK = 9200,
9225 PseudoVSOXSEG2EI64_V_M1_M1 = 9201,
9226 PseudoVSOXSEG2EI64_V_M1_M1_MASK = 9202,
9227 PseudoVSOXSEG2EI64_V_M1_MF2 = 9203,
9228 PseudoVSOXSEG2EI64_V_M1_MF2_MASK = 9204,
9229 PseudoVSOXSEG2EI64_V_M1_MF4 = 9205,
9230 PseudoVSOXSEG2EI64_V_M1_MF4_MASK = 9206,
9231 PseudoVSOXSEG2EI64_V_M1_MF8 = 9207,
9232 PseudoVSOXSEG2EI64_V_M1_MF8_MASK = 9208,
9233 PseudoVSOXSEG2EI64_V_M2_M1 = 9209,
9234 PseudoVSOXSEG2EI64_V_M2_M1_MASK = 9210,
9235 PseudoVSOXSEG2EI64_V_M2_M2 = 9211,
9236 PseudoVSOXSEG2EI64_V_M2_M2_MASK = 9212,
9237 PseudoVSOXSEG2EI64_V_M2_MF2 = 9213,
9238 PseudoVSOXSEG2EI64_V_M2_MF2_MASK = 9214,
9239 PseudoVSOXSEG2EI64_V_M2_MF4 = 9215,
9240 PseudoVSOXSEG2EI64_V_M2_MF4_MASK = 9216,
9241 PseudoVSOXSEG2EI64_V_M4_M1 = 9217,
9242 PseudoVSOXSEG2EI64_V_M4_M1_MASK = 9218,
9243 PseudoVSOXSEG2EI64_V_M4_M2 = 9219,
9244 PseudoVSOXSEG2EI64_V_M4_M2_MASK = 9220,
9245 PseudoVSOXSEG2EI64_V_M4_M4 = 9221,
9246 PseudoVSOXSEG2EI64_V_M4_M4_MASK = 9222,
9247 PseudoVSOXSEG2EI64_V_M4_MF2 = 9223,
9248 PseudoVSOXSEG2EI64_V_M4_MF2_MASK = 9224,
9249 PseudoVSOXSEG2EI64_V_M8_M1 = 9225,
9250 PseudoVSOXSEG2EI64_V_M8_M1_MASK = 9226,
9251 PseudoVSOXSEG2EI64_V_M8_M2 = 9227,
9252 PseudoVSOXSEG2EI64_V_M8_M2_MASK = 9228,
9253 PseudoVSOXSEG2EI64_V_M8_M4 = 9229,
9254 PseudoVSOXSEG2EI64_V_M8_M4_MASK = 9230,
9255 PseudoVSOXSEG2EI8_V_M1_M1 = 9231,
9256 PseudoVSOXSEG2EI8_V_M1_M1_MASK = 9232,
9257 PseudoVSOXSEG2EI8_V_M1_M2 = 9233,
9258 PseudoVSOXSEG2EI8_V_M1_M2_MASK = 9234,
9259 PseudoVSOXSEG2EI8_V_M1_M4 = 9235,
9260 PseudoVSOXSEG2EI8_V_M1_M4_MASK = 9236,
9261 PseudoVSOXSEG2EI8_V_M2_M2 = 9237,
9262 PseudoVSOXSEG2EI8_V_M2_M2_MASK = 9238,
9263 PseudoVSOXSEG2EI8_V_M2_M4 = 9239,
9264 PseudoVSOXSEG2EI8_V_M2_M4_MASK = 9240,
9265 PseudoVSOXSEG2EI8_V_M4_M4 = 9241,
9266 PseudoVSOXSEG2EI8_V_M4_M4_MASK = 9242,
9267 PseudoVSOXSEG2EI8_V_MF2_M1 = 9243,
9268 PseudoVSOXSEG2EI8_V_MF2_M1_MASK = 9244,
9269 PseudoVSOXSEG2EI8_V_MF2_M2 = 9245,
9270 PseudoVSOXSEG2EI8_V_MF2_M2_MASK = 9246,
9271 PseudoVSOXSEG2EI8_V_MF2_M4 = 9247,
9272 PseudoVSOXSEG2EI8_V_MF2_M4_MASK = 9248,
9273 PseudoVSOXSEG2EI8_V_MF2_MF2 = 9249,
9274 PseudoVSOXSEG2EI8_V_MF2_MF2_MASK = 9250,
9275 PseudoVSOXSEG2EI8_V_MF4_M1 = 9251,
9276 PseudoVSOXSEG2EI8_V_MF4_M1_MASK = 9252,
9277 PseudoVSOXSEG2EI8_V_MF4_M2 = 9253,
9278 PseudoVSOXSEG2EI8_V_MF4_M2_MASK = 9254,
9279 PseudoVSOXSEG2EI8_V_MF4_MF2 = 9255,
9280 PseudoVSOXSEG2EI8_V_MF4_MF2_MASK = 9256,
9281 PseudoVSOXSEG2EI8_V_MF4_MF4 = 9257,
9282 PseudoVSOXSEG2EI8_V_MF4_MF4_MASK = 9258,
9283 PseudoVSOXSEG2EI8_V_MF8_M1 = 9259,
9284 PseudoVSOXSEG2EI8_V_MF8_M1_MASK = 9260,
9285 PseudoVSOXSEG2EI8_V_MF8_MF2 = 9261,
9286 PseudoVSOXSEG2EI8_V_MF8_MF2_MASK = 9262,
9287 PseudoVSOXSEG2EI8_V_MF8_MF4 = 9263,
9288 PseudoVSOXSEG2EI8_V_MF8_MF4_MASK = 9264,
9289 PseudoVSOXSEG2EI8_V_MF8_MF8 = 9265,
9290 PseudoVSOXSEG2EI8_V_MF8_MF8_MASK = 9266,
9291 PseudoVSOXSEG3EI16_V_M1_M1 = 9267,
9292 PseudoVSOXSEG3EI16_V_M1_M1_MASK = 9268,
9293 PseudoVSOXSEG3EI16_V_M1_M2 = 9269,
9294 PseudoVSOXSEG3EI16_V_M1_M2_MASK = 9270,
9295 PseudoVSOXSEG3EI16_V_M1_MF2 = 9271,
9296 PseudoVSOXSEG3EI16_V_M1_MF2_MASK = 9272,
9297 PseudoVSOXSEG3EI16_V_M2_M1 = 9273,
9298 PseudoVSOXSEG3EI16_V_M2_M1_MASK = 9274,
9299 PseudoVSOXSEG3EI16_V_M2_M2 = 9275,
9300 PseudoVSOXSEG3EI16_V_M2_M2_MASK = 9276,
9301 PseudoVSOXSEG3EI16_V_M4_M2 = 9277,
9302 PseudoVSOXSEG3EI16_V_M4_M2_MASK = 9278,
9303 PseudoVSOXSEG3EI16_V_MF2_M1 = 9279,
9304 PseudoVSOXSEG3EI16_V_MF2_M1_MASK = 9280,
9305 PseudoVSOXSEG3EI16_V_MF2_M2 = 9281,
9306 PseudoVSOXSEG3EI16_V_MF2_M2_MASK = 9282,
9307 PseudoVSOXSEG3EI16_V_MF2_MF2 = 9283,
9308 PseudoVSOXSEG3EI16_V_MF2_MF2_MASK = 9284,
9309 PseudoVSOXSEG3EI16_V_MF2_MF4 = 9285,
9310 PseudoVSOXSEG3EI16_V_MF2_MF4_MASK = 9286,
9311 PseudoVSOXSEG3EI16_V_MF4_M1 = 9287,
9312 PseudoVSOXSEG3EI16_V_MF4_M1_MASK = 9288,
9313 PseudoVSOXSEG3EI16_V_MF4_MF2 = 9289,
9314 PseudoVSOXSEG3EI16_V_MF4_MF2_MASK = 9290,
9315 PseudoVSOXSEG3EI16_V_MF4_MF4 = 9291,
9316 PseudoVSOXSEG3EI16_V_MF4_MF4_MASK = 9292,
9317 PseudoVSOXSEG3EI16_V_MF4_MF8 = 9293,
9318 PseudoVSOXSEG3EI16_V_MF4_MF8_MASK = 9294,
9319 PseudoVSOXSEG3EI32_V_M1_M1 = 9295,
9320 PseudoVSOXSEG3EI32_V_M1_M1_MASK = 9296,
9321 PseudoVSOXSEG3EI32_V_M1_M2 = 9297,
9322 PseudoVSOXSEG3EI32_V_M1_M2_MASK = 9298,
9323 PseudoVSOXSEG3EI32_V_M1_MF2 = 9299,
9324 PseudoVSOXSEG3EI32_V_M1_MF2_MASK = 9300,
9325 PseudoVSOXSEG3EI32_V_M1_MF4 = 9301,
9326 PseudoVSOXSEG3EI32_V_M1_MF4_MASK = 9302,
9327 PseudoVSOXSEG3EI32_V_M2_M1 = 9303,
9328 PseudoVSOXSEG3EI32_V_M2_M1_MASK = 9304,
9329 PseudoVSOXSEG3EI32_V_M2_M2 = 9305,
9330 PseudoVSOXSEG3EI32_V_M2_M2_MASK = 9306,
9331 PseudoVSOXSEG3EI32_V_M2_MF2 = 9307,
9332 PseudoVSOXSEG3EI32_V_M2_MF2_MASK = 9308,
9333 PseudoVSOXSEG3EI32_V_M4_M1 = 9309,
9334 PseudoVSOXSEG3EI32_V_M4_M1_MASK = 9310,
9335 PseudoVSOXSEG3EI32_V_M4_M2 = 9311,
9336 PseudoVSOXSEG3EI32_V_M4_M2_MASK = 9312,
9337 PseudoVSOXSEG3EI32_V_M8_M2 = 9313,
9338 PseudoVSOXSEG3EI32_V_M8_M2_MASK = 9314,
9339 PseudoVSOXSEG3EI32_V_MF2_M1 = 9315,
9340 PseudoVSOXSEG3EI32_V_MF2_M1_MASK = 9316,
9341 PseudoVSOXSEG3EI32_V_MF2_MF2 = 9317,
9342 PseudoVSOXSEG3EI32_V_MF2_MF2_MASK = 9318,
9343 PseudoVSOXSEG3EI32_V_MF2_MF4 = 9319,
9344 PseudoVSOXSEG3EI32_V_MF2_MF4_MASK = 9320,
9345 PseudoVSOXSEG3EI32_V_MF2_MF8 = 9321,
9346 PseudoVSOXSEG3EI32_V_MF2_MF8_MASK = 9322,
9347 PseudoVSOXSEG3EI64_V_M1_M1 = 9323,
9348 PseudoVSOXSEG3EI64_V_M1_M1_MASK = 9324,
9349 PseudoVSOXSEG3EI64_V_M1_MF2 = 9325,
9350 PseudoVSOXSEG3EI64_V_M1_MF2_MASK = 9326,
9351 PseudoVSOXSEG3EI64_V_M1_MF4 = 9327,
9352 PseudoVSOXSEG3EI64_V_M1_MF4_MASK = 9328,
9353 PseudoVSOXSEG3EI64_V_M1_MF8 = 9329,
9354 PseudoVSOXSEG3EI64_V_M1_MF8_MASK = 9330,
9355 PseudoVSOXSEG3EI64_V_M2_M1 = 9331,
9356 PseudoVSOXSEG3EI64_V_M2_M1_MASK = 9332,
9357 PseudoVSOXSEG3EI64_V_M2_M2 = 9333,
9358 PseudoVSOXSEG3EI64_V_M2_M2_MASK = 9334,
9359 PseudoVSOXSEG3EI64_V_M2_MF2 = 9335,
9360 PseudoVSOXSEG3EI64_V_M2_MF2_MASK = 9336,
9361 PseudoVSOXSEG3EI64_V_M2_MF4 = 9337,
9362 PseudoVSOXSEG3EI64_V_M2_MF4_MASK = 9338,
9363 PseudoVSOXSEG3EI64_V_M4_M1 = 9339,
9364 PseudoVSOXSEG3EI64_V_M4_M1_MASK = 9340,
9365 PseudoVSOXSEG3EI64_V_M4_M2 = 9341,
9366 PseudoVSOXSEG3EI64_V_M4_M2_MASK = 9342,
9367 PseudoVSOXSEG3EI64_V_M4_MF2 = 9343,
9368 PseudoVSOXSEG3EI64_V_M4_MF2_MASK = 9344,
9369 PseudoVSOXSEG3EI64_V_M8_M1 = 9345,
9370 PseudoVSOXSEG3EI64_V_M8_M1_MASK = 9346,
9371 PseudoVSOXSEG3EI64_V_M8_M2 = 9347,
9372 PseudoVSOXSEG3EI64_V_M8_M2_MASK = 9348,
9373 PseudoVSOXSEG3EI8_V_M1_M1 = 9349,
9374 PseudoVSOXSEG3EI8_V_M1_M1_MASK = 9350,
9375 PseudoVSOXSEG3EI8_V_M1_M2 = 9351,
9376 PseudoVSOXSEG3EI8_V_M1_M2_MASK = 9352,
9377 PseudoVSOXSEG3EI8_V_M2_M2 = 9353,
9378 PseudoVSOXSEG3EI8_V_M2_M2_MASK = 9354,
9379 PseudoVSOXSEG3EI8_V_MF2_M1 = 9355,
9380 PseudoVSOXSEG3EI8_V_MF2_M1_MASK = 9356,
9381 PseudoVSOXSEG3EI8_V_MF2_M2 = 9357,
9382 PseudoVSOXSEG3EI8_V_MF2_M2_MASK = 9358,
9383 PseudoVSOXSEG3EI8_V_MF2_MF2 = 9359,
9384 PseudoVSOXSEG3EI8_V_MF2_MF2_MASK = 9360,
9385 PseudoVSOXSEG3EI8_V_MF4_M1 = 9361,
9386 PseudoVSOXSEG3EI8_V_MF4_M1_MASK = 9362,
9387 PseudoVSOXSEG3EI8_V_MF4_M2 = 9363,
9388 PseudoVSOXSEG3EI8_V_MF4_M2_MASK = 9364,
9389 PseudoVSOXSEG3EI8_V_MF4_MF2 = 9365,
9390 PseudoVSOXSEG3EI8_V_MF4_MF2_MASK = 9366,
9391 PseudoVSOXSEG3EI8_V_MF4_MF4 = 9367,
9392 PseudoVSOXSEG3EI8_V_MF4_MF4_MASK = 9368,
9393 PseudoVSOXSEG3EI8_V_MF8_M1 = 9369,
9394 PseudoVSOXSEG3EI8_V_MF8_M1_MASK = 9370,
9395 PseudoVSOXSEG3EI8_V_MF8_MF2 = 9371,
9396 PseudoVSOXSEG3EI8_V_MF8_MF2_MASK = 9372,
9397 PseudoVSOXSEG3EI8_V_MF8_MF4 = 9373,
9398 PseudoVSOXSEG3EI8_V_MF8_MF4_MASK = 9374,
9399 PseudoVSOXSEG3EI8_V_MF8_MF8 = 9375,
9400 PseudoVSOXSEG3EI8_V_MF8_MF8_MASK = 9376,
9401 PseudoVSOXSEG4EI16_V_M1_M1 = 9377,
9402 PseudoVSOXSEG4EI16_V_M1_M1_MASK = 9378,
9403 PseudoVSOXSEG4EI16_V_M1_M2 = 9379,
9404 PseudoVSOXSEG4EI16_V_M1_M2_MASK = 9380,
9405 PseudoVSOXSEG4EI16_V_M1_MF2 = 9381,
9406 PseudoVSOXSEG4EI16_V_M1_MF2_MASK = 9382,
9407 PseudoVSOXSEG4EI16_V_M2_M1 = 9383,
9408 PseudoVSOXSEG4EI16_V_M2_M1_MASK = 9384,
9409 PseudoVSOXSEG4EI16_V_M2_M2 = 9385,
9410 PseudoVSOXSEG4EI16_V_M2_M2_MASK = 9386,
9411 PseudoVSOXSEG4EI16_V_M4_M2 = 9387,
9412 PseudoVSOXSEG4EI16_V_M4_M2_MASK = 9388,
9413 PseudoVSOXSEG4EI16_V_MF2_M1 = 9389,
9414 PseudoVSOXSEG4EI16_V_MF2_M1_MASK = 9390,
9415 PseudoVSOXSEG4EI16_V_MF2_M2 = 9391,
9416 PseudoVSOXSEG4EI16_V_MF2_M2_MASK = 9392,
9417 PseudoVSOXSEG4EI16_V_MF2_MF2 = 9393,
9418 PseudoVSOXSEG4EI16_V_MF2_MF2_MASK = 9394,
9419 PseudoVSOXSEG4EI16_V_MF2_MF4 = 9395,
9420 PseudoVSOXSEG4EI16_V_MF2_MF4_MASK = 9396,
9421 PseudoVSOXSEG4EI16_V_MF4_M1 = 9397,
9422 PseudoVSOXSEG4EI16_V_MF4_M1_MASK = 9398,
9423 PseudoVSOXSEG4EI16_V_MF4_MF2 = 9399,
9424 PseudoVSOXSEG4EI16_V_MF4_MF2_MASK = 9400,
9425 PseudoVSOXSEG4EI16_V_MF4_MF4 = 9401,
9426 PseudoVSOXSEG4EI16_V_MF4_MF4_MASK = 9402,
9427 PseudoVSOXSEG4EI16_V_MF4_MF8 = 9403,
9428 PseudoVSOXSEG4EI16_V_MF4_MF8_MASK = 9404,
9429 PseudoVSOXSEG4EI32_V_M1_M1 = 9405,
9430 PseudoVSOXSEG4EI32_V_M1_M1_MASK = 9406,
9431 PseudoVSOXSEG4EI32_V_M1_M2 = 9407,
9432 PseudoVSOXSEG4EI32_V_M1_M2_MASK = 9408,
9433 PseudoVSOXSEG4EI32_V_M1_MF2 = 9409,
9434 PseudoVSOXSEG4EI32_V_M1_MF2_MASK = 9410,
9435 PseudoVSOXSEG4EI32_V_M1_MF4 = 9411,
9436 PseudoVSOXSEG4EI32_V_M1_MF4_MASK = 9412,
9437 PseudoVSOXSEG4EI32_V_M2_M1 = 9413,
9438 PseudoVSOXSEG4EI32_V_M2_M1_MASK = 9414,
9439 PseudoVSOXSEG4EI32_V_M2_M2 = 9415,
9440 PseudoVSOXSEG4EI32_V_M2_M2_MASK = 9416,
9441 PseudoVSOXSEG4EI32_V_M2_MF2 = 9417,
9442 PseudoVSOXSEG4EI32_V_M2_MF2_MASK = 9418,
9443 PseudoVSOXSEG4EI32_V_M4_M1 = 9419,
9444 PseudoVSOXSEG4EI32_V_M4_M1_MASK = 9420,
9445 PseudoVSOXSEG4EI32_V_M4_M2 = 9421,
9446 PseudoVSOXSEG4EI32_V_M4_M2_MASK = 9422,
9447 PseudoVSOXSEG4EI32_V_M8_M2 = 9423,
9448 PseudoVSOXSEG4EI32_V_M8_M2_MASK = 9424,
9449 PseudoVSOXSEG4EI32_V_MF2_M1 = 9425,
9450 PseudoVSOXSEG4EI32_V_MF2_M1_MASK = 9426,
9451 PseudoVSOXSEG4EI32_V_MF2_MF2 = 9427,
9452 PseudoVSOXSEG4EI32_V_MF2_MF2_MASK = 9428,
9453 PseudoVSOXSEG4EI32_V_MF2_MF4 = 9429,
9454 PseudoVSOXSEG4EI32_V_MF2_MF4_MASK = 9430,
9455 PseudoVSOXSEG4EI32_V_MF2_MF8 = 9431,
9456 PseudoVSOXSEG4EI32_V_MF2_MF8_MASK = 9432,
9457 PseudoVSOXSEG4EI64_V_M1_M1 = 9433,
9458 PseudoVSOXSEG4EI64_V_M1_M1_MASK = 9434,
9459 PseudoVSOXSEG4EI64_V_M1_MF2 = 9435,
9460 PseudoVSOXSEG4EI64_V_M1_MF2_MASK = 9436,
9461 PseudoVSOXSEG4EI64_V_M1_MF4 = 9437,
9462 PseudoVSOXSEG4EI64_V_M1_MF4_MASK = 9438,
9463 PseudoVSOXSEG4EI64_V_M1_MF8 = 9439,
9464 PseudoVSOXSEG4EI64_V_M1_MF8_MASK = 9440,
9465 PseudoVSOXSEG4EI64_V_M2_M1 = 9441,
9466 PseudoVSOXSEG4EI64_V_M2_M1_MASK = 9442,
9467 PseudoVSOXSEG4EI64_V_M2_M2 = 9443,
9468 PseudoVSOXSEG4EI64_V_M2_M2_MASK = 9444,
9469 PseudoVSOXSEG4EI64_V_M2_MF2 = 9445,
9470 PseudoVSOXSEG4EI64_V_M2_MF2_MASK = 9446,
9471 PseudoVSOXSEG4EI64_V_M2_MF4 = 9447,
9472 PseudoVSOXSEG4EI64_V_M2_MF4_MASK = 9448,
9473 PseudoVSOXSEG4EI64_V_M4_M1 = 9449,
9474 PseudoVSOXSEG4EI64_V_M4_M1_MASK = 9450,
9475 PseudoVSOXSEG4EI64_V_M4_M2 = 9451,
9476 PseudoVSOXSEG4EI64_V_M4_M2_MASK = 9452,
9477 PseudoVSOXSEG4EI64_V_M4_MF2 = 9453,
9478 PseudoVSOXSEG4EI64_V_M4_MF2_MASK = 9454,
9479 PseudoVSOXSEG4EI64_V_M8_M1 = 9455,
9480 PseudoVSOXSEG4EI64_V_M8_M1_MASK = 9456,
9481 PseudoVSOXSEG4EI64_V_M8_M2 = 9457,
9482 PseudoVSOXSEG4EI64_V_M8_M2_MASK = 9458,
9483 PseudoVSOXSEG4EI8_V_M1_M1 = 9459,
9484 PseudoVSOXSEG4EI8_V_M1_M1_MASK = 9460,
9485 PseudoVSOXSEG4EI8_V_M1_M2 = 9461,
9486 PseudoVSOXSEG4EI8_V_M1_M2_MASK = 9462,
9487 PseudoVSOXSEG4EI8_V_M2_M2 = 9463,
9488 PseudoVSOXSEG4EI8_V_M2_M2_MASK = 9464,
9489 PseudoVSOXSEG4EI8_V_MF2_M1 = 9465,
9490 PseudoVSOXSEG4EI8_V_MF2_M1_MASK = 9466,
9491 PseudoVSOXSEG4EI8_V_MF2_M2 = 9467,
9492 PseudoVSOXSEG4EI8_V_MF2_M2_MASK = 9468,
9493 PseudoVSOXSEG4EI8_V_MF2_MF2 = 9469,
9494 PseudoVSOXSEG4EI8_V_MF2_MF2_MASK = 9470,
9495 PseudoVSOXSEG4EI8_V_MF4_M1 = 9471,
9496 PseudoVSOXSEG4EI8_V_MF4_M1_MASK = 9472,
9497 PseudoVSOXSEG4EI8_V_MF4_M2 = 9473,
9498 PseudoVSOXSEG4EI8_V_MF4_M2_MASK = 9474,
9499 PseudoVSOXSEG4EI8_V_MF4_MF2 = 9475,
9500 PseudoVSOXSEG4EI8_V_MF4_MF2_MASK = 9476,
9501 PseudoVSOXSEG4EI8_V_MF4_MF4 = 9477,
9502 PseudoVSOXSEG4EI8_V_MF4_MF4_MASK = 9478,
9503 PseudoVSOXSEG4EI8_V_MF8_M1 = 9479,
9504 PseudoVSOXSEG4EI8_V_MF8_M1_MASK = 9480,
9505 PseudoVSOXSEG4EI8_V_MF8_MF2 = 9481,
9506 PseudoVSOXSEG4EI8_V_MF8_MF2_MASK = 9482,
9507 PseudoVSOXSEG4EI8_V_MF8_MF4 = 9483,
9508 PseudoVSOXSEG4EI8_V_MF8_MF4_MASK = 9484,
9509 PseudoVSOXSEG4EI8_V_MF8_MF8 = 9485,
9510 PseudoVSOXSEG4EI8_V_MF8_MF8_MASK = 9486,
9511 PseudoVSOXSEG5EI16_V_M1_M1 = 9487,
9512 PseudoVSOXSEG5EI16_V_M1_M1_MASK = 9488,
9513 PseudoVSOXSEG5EI16_V_M1_MF2 = 9489,
9514 PseudoVSOXSEG5EI16_V_M1_MF2_MASK = 9490,
9515 PseudoVSOXSEG5EI16_V_M2_M1 = 9491,
9516 PseudoVSOXSEG5EI16_V_M2_M1_MASK = 9492,
9517 PseudoVSOXSEG5EI16_V_MF2_M1 = 9493,
9518 PseudoVSOXSEG5EI16_V_MF2_M1_MASK = 9494,
9519 PseudoVSOXSEG5EI16_V_MF2_MF2 = 9495,
9520 PseudoVSOXSEG5EI16_V_MF2_MF2_MASK = 9496,
9521 PseudoVSOXSEG5EI16_V_MF2_MF4 = 9497,
9522 PseudoVSOXSEG5EI16_V_MF2_MF4_MASK = 9498,
9523 PseudoVSOXSEG5EI16_V_MF4_M1 = 9499,
9524 PseudoVSOXSEG5EI16_V_MF4_M1_MASK = 9500,
9525 PseudoVSOXSEG5EI16_V_MF4_MF2 = 9501,
9526 PseudoVSOXSEG5EI16_V_MF4_MF2_MASK = 9502,
9527 PseudoVSOXSEG5EI16_V_MF4_MF4 = 9503,
9528 PseudoVSOXSEG5EI16_V_MF4_MF4_MASK = 9504,
9529 PseudoVSOXSEG5EI16_V_MF4_MF8 = 9505,
9530 PseudoVSOXSEG5EI16_V_MF4_MF8_MASK = 9506,
9531 PseudoVSOXSEG5EI32_V_M1_M1 = 9507,
9532 PseudoVSOXSEG5EI32_V_M1_M1_MASK = 9508,
9533 PseudoVSOXSEG5EI32_V_M1_MF2 = 9509,
9534 PseudoVSOXSEG5EI32_V_M1_MF2_MASK = 9510,
9535 PseudoVSOXSEG5EI32_V_M1_MF4 = 9511,
9536 PseudoVSOXSEG5EI32_V_M1_MF4_MASK = 9512,
9537 PseudoVSOXSEG5EI32_V_M2_M1 = 9513,
9538 PseudoVSOXSEG5EI32_V_M2_M1_MASK = 9514,
9539 PseudoVSOXSEG5EI32_V_M2_MF2 = 9515,
9540 PseudoVSOXSEG5EI32_V_M2_MF2_MASK = 9516,
9541 PseudoVSOXSEG5EI32_V_M4_M1 = 9517,
9542 PseudoVSOXSEG5EI32_V_M4_M1_MASK = 9518,
9543 PseudoVSOXSEG5EI32_V_MF2_M1 = 9519,
9544 PseudoVSOXSEG5EI32_V_MF2_M1_MASK = 9520,
9545 PseudoVSOXSEG5EI32_V_MF2_MF2 = 9521,
9546 PseudoVSOXSEG5EI32_V_MF2_MF2_MASK = 9522,
9547 PseudoVSOXSEG5EI32_V_MF2_MF4 = 9523,
9548 PseudoVSOXSEG5EI32_V_MF2_MF4_MASK = 9524,
9549 PseudoVSOXSEG5EI32_V_MF2_MF8 = 9525,
9550 PseudoVSOXSEG5EI32_V_MF2_MF8_MASK = 9526,
9551 PseudoVSOXSEG5EI64_V_M1_M1 = 9527,
9552 PseudoVSOXSEG5EI64_V_M1_M1_MASK = 9528,
9553 PseudoVSOXSEG5EI64_V_M1_MF2 = 9529,
9554 PseudoVSOXSEG5EI64_V_M1_MF2_MASK = 9530,
9555 PseudoVSOXSEG5EI64_V_M1_MF4 = 9531,
9556 PseudoVSOXSEG5EI64_V_M1_MF4_MASK = 9532,
9557 PseudoVSOXSEG5EI64_V_M1_MF8 = 9533,
9558 PseudoVSOXSEG5EI64_V_M1_MF8_MASK = 9534,
9559 PseudoVSOXSEG5EI64_V_M2_M1 = 9535,
9560 PseudoVSOXSEG5EI64_V_M2_M1_MASK = 9536,
9561 PseudoVSOXSEG5EI64_V_M2_MF2 = 9537,
9562 PseudoVSOXSEG5EI64_V_M2_MF2_MASK = 9538,
9563 PseudoVSOXSEG5EI64_V_M2_MF4 = 9539,
9564 PseudoVSOXSEG5EI64_V_M2_MF4_MASK = 9540,
9565 PseudoVSOXSEG5EI64_V_M4_M1 = 9541,
9566 PseudoVSOXSEG5EI64_V_M4_M1_MASK = 9542,
9567 PseudoVSOXSEG5EI64_V_M4_MF2 = 9543,
9568 PseudoVSOXSEG5EI64_V_M4_MF2_MASK = 9544,
9569 PseudoVSOXSEG5EI64_V_M8_M1 = 9545,
9570 PseudoVSOXSEG5EI64_V_M8_M1_MASK = 9546,
9571 PseudoVSOXSEG5EI8_V_M1_M1 = 9547,
9572 PseudoVSOXSEG5EI8_V_M1_M1_MASK = 9548,
9573 PseudoVSOXSEG5EI8_V_MF2_M1 = 9549,
9574 PseudoVSOXSEG5EI8_V_MF2_M1_MASK = 9550,
9575 PseudoVSOXSEG5EI8_V_MF2_MF2 = 9551,
9576 PseudoVSOXSEG5EI8_V_MF2_MF2_MASK = 9552,
9577 PseudoVSOXSEG5EI8_V_MF4_M1 = 9553,
9578 PseudoVSOXSEG5EI8_V_MF4_M1_MASK = 9554,
9579 PseudoVSOXSEG5EI8_V_MF4_MF2 = 9555,
9580 PseudoVSOXSEG5EI8_V_MF4_MF2_MASK = 9556,
9581 PseudoVSOXSEG5EI8_V_MF4_MF4 = 9557,
9582 PseudoVSOXSEG5EI8_V_MF4_MF4_MASK = 9558,
9583 PseudoVSOXSEG5EI8_V_MF8_M1 = 9559,
9584 PseudoVSOXSEG5EI8_V_MF8_M1_MASK = 9560,
9585 PseudoVSOXSEG5EI8_V_MF8_MF2 = 9561,
9586 PseudoVSOXSEG5EI8_V_MF8_MF2_MASK = 9562,
9587 PseudoVSOXSEG5EI8_V_MF8_MF4 = 9563,
9588 PseudoVSOXSEG5EI8_V_MF8_MF4_MASK = 9564,
9589 PseudoVSOXSEG5EI8_V_MF8_MF8 = 9565,
9590 PseudoVSOXSEG5EI8_V_MF8_MF8_MASK = 9566,
9591 PseudoVSOXSEG6EI16_V_M1_M1 = 9567,
9592 PseudoVSOXSEG6EI16_V_M1_M1_MASK = 9568,
9593 PseudoVSOXSEG6EI16_V_M1_MF2 = 9569,
9594 PseudoVSOXSEG6EI16_V_M1_MF2_MASK = 9570,
9595 PseudoVSOXSEG6EI16_V_M2_M1 = 9571,
9596 PseudoVSOXSEG6EI16_V_M2_M1_MASK = 9572,
9597 PseudoVSOXSEG6EI16_V_MF2_M1 = 9573,
9598 PseudoVSOXSEG6EI16_V_MF2_M1_MASK = 9574,
9599 PseudoVSOXSEG6EI16_V_MF2_MF2 = 9575,
9600 PseudoVSOXSEG6EI16_V_MF2_MF2_MASK = 9576,
9601 PseudoVSOXSEG6EI16_V_MF2_MF4 = 9577,
9602 PseudoVSOXSEG6EI16_V_MF2_MF4_MASK = 9578,
9603 PseudoVSOXSEG6EI16_V_MF4_M1 = 9579,
9604 PseudoVSOXSEG6EI16_V_MF4_M1_MASK = 9580,
9605 PseudoVSOXSEG6EI16_V_MF4_MF2 = 9581,
9606 PseudoVSOXSEG6EI16_V_MF4_MF2_MASK = 9582,
9607 PseudoVSOXSEG6EI16_V_MF4_MF4 = 9583,
9608 PseudoVSOXSEG6EI16_V_MF4_MF4_MASK = 9584,
9609 PseudoVSOXSEG6EI16_V_MF4_MF8 = 9585,
9610 PseudoVSOXSEG6EI16_V_MF4_MF8_MASK = 9586,
9611 PseudoVSOXSEG6EI32_V_M1_M1 = 9587,
9612 PseudoVSOXSEG6EI32_V_M1_M1_MASK = 9588,
9613 PseudoVSOXSEG6EI32_V_M1_MF2 = 9589,
9614 PseudoVSOXSEG6EI32_V_M1_MF2_MASK = 9590,
9615 PseudoVSOXSEG6EI32_V_M1_MF4 = 9591,
9616 PseudoVSOXSEG6EI32_V_M1_MF4_MASK = 9592,
9617 PseudoVSOXSEG6EI32_V_M2_M1 = 9593,
9618 PseudoVSOXSEG6EI32_V_M2_M1_MASK = 9594,
9619 PseudoVSOXSEG6EI32_V_M2_MF2 = 9595,
9620 PseudoVSOXSEG6EI32_V_M2_MF2_MASK = 9596,
9621 PseudoVSOXSEG6EI32_V_M4_M1 = 9597,
9622 PseudoVSOXSEG6EI32_V_M4_M1_MASK = 9598,
9623 PseudoVSOXSEG6EI32_V_MF2_M1 = 9599,
9624 PseudoVSOXSEG6EI32_V_MF2_M1_MASK = 9600,
9625 PseudoVSOXSEG6EI32_V_MF2_MF2 = 9601,
9626 PseudoVSOXSEG6EI32_V_MF2_MF2_MASK = 9602,
9627 PseudoVSOXSEG6EI32_V_MF2_MF4 = 9603,
9628 PseudoVSOXSEG6EI32_V_MF2_MF4_MASK = 9604,
9629 PseudoVSOXSEG6EI32_V_MF2_MF8 = 9605,
9630 PseudoVSOXSEG6EI32_V_MF2_MF8_MASK = 9606,
9631 PseudoVSOXSEG6EI64_V_M1_M1 = 9607,
9632 PseudoVSOXSEG6EI64_V_M1_M1_MASK = 9608,
9633 PseudoVSOXSEG6EI64_V_M1_MF2 = 9609,
9634 PseudoVSOXSEG6EI64_V_M1_MF2_MASK = 9610,
9635 PseudoVSOXSEG6EI64_V_M1_MF4 = 9611,
9636 PseudoVSOXSEG6EI64_V_M1_MF4_MASK = 9612,
9637 PseudoVSOXSEG6EI64_V_M1_MF8 = 9613,
9638 PseudoVSOXSEG6EI64_V_M1_MF8_MASK = 9614,
9639 PseudoVSOXSEG6EI64_V_M2_M1 = 9615,
9640 PseudoVSOXSEG6EI64_V_M2_M1_MASK = 9616,
9641 PseudoVSOXSEG6EI64_V_M2_MF2 = 9617,
9642 PseudoVSOXSEG6EI64_V_M2_MF2_MASK = 9618,
9643 PseudoVSOXSEG6EI64_V_M2_MF4 = 9619,
9644 PseudoVSOXSEG6EI64_V_M2_MF4_MASK = 9620,
9645 PseudoVSOXSEG6EI64_V_M4_M1 = 9621,
9646 PseudoVSOXSEG6EI64_V_M4_M1_MASK = 9622,
9647 PseudoVSOXSEG6EI64_V_M4_MF2 = 9623,
9648 PseudoVSOXSEG6EI64_V_M4_MF2_MASK = 9624,
9649 PseudoVSOXSEG6EI64_V_M8_M1 = 9625,
9650 PseudoVSOXSEG6EI64_V_M8_M1_MASK = 9626,
9651 PseudoVSOXSEG6EI8_V_M1_M1 = 9627,
9652 PseudoVSOXSEG6EI8_V_M1_M1_MASK = 9628,
9653 PseudoVSOXSEG6EI8_V_MF2_M1 = 9629,
9654 PseudoVSOXSEG6EI8_V_MF2_M1_MASK = 9630,
9655 PseudoVSOXSEG6EI8_V_MF2_MF2 = 9631,
9656 PseudoVSOXSEG6EI8_V_MF2_MF2_MASK = 9632,
9657 PseudoVSOXSEG6EI8_V_MF4_M1 = 9633,
9658 PseudoVSOXSEG6EI8_V_MF4_M1_MASK = 9634,
9659 PseudoVSOXSEG6EI8_V_MF4_MF2 = 9635,
9660 PseudoVSOXSEG6EI8_V_MF4_MF2_MASK = 9636,
9661 PseudoVSOXSEG6EI8_V_MF4_MF4 = 9637,
9662 PseudoVSOXSEG6EI8_V_MF4_MF4_MASK = 9638,
9663 PseudoVSOXSEG6EI8_V_MF8_M1 = 9639,
9664 PseudoVSOXSEG6EI8_V_MF8_M1_MASK = 9640,
9665 PseudoVSOXSEG6EI8_V_MF8_MF2 = 9641,
9666 PseudoVSOXSEG6EI8_V_MF8_MF2_MASK = 9642,
9667 PseudoVSOXSEG6EI8_V_MF8_MF4 = 9643,
9668 PseudoVSOXSEG6EI8_V_MF8_MF4_MASK = 9644,
9669 PseudoVSOXSEG6EI8_V_MF8_MF8 = 9645,
9670 PseudoVSOXSEG6EI8_V_MF8_MF8_MASK = 9646,
9671 PseudoVSOXSEG7EI16_V_M1_M1 = 9647,
9672 PseudoVSOXSEG7EI16_V_M1_M1_MASK = 9648,
9673 PseudoVSOXSEG7EI16_V_M1_MF2 = 9649,
9674 PseudoVSOXSEG7EI16_V_M1_MF2_MASK = 9650,
9675 PseudoVSOXSEG7EI16_V_M2_M1 = 9651,
9676 PseudoVSOXSEG7EI16_V_M2_M1_MASK = 9652,
9677 PseudoVSOXSEG7EI16_V_MF2_M1 = 9653,
9678 PseudoVSOXSEG7EI16_V_MF2_M1_MASK = 9654,
9679 PseudoVSOXSEG7EI16_V_MF2_MF2 = 9655,
9680 PseudoVSOXSEG7EI16_V_MF2_MF2_MASK = 9656,
9681 PseudoVSOXSEG7EI16_V_MF2_MF4 = 9657,
9682 PseudoVSOXSEG7EI16_V_MF2_MF4_MASK = 9658,
9683 PseudoVSOXSEG7EI16_V_MF4_M1 = 9659,
9684 PseudoVSOXSEG7EI16_V_MF4_M1_MASK = 9660,
9685 PseudoVSOXSEG7EI16_V_MF4_MF2 = 9661,
9686 PseudoVSOXSEG7EI16_V_MF4_MF2_MASK = 9662,
9687 PseudoVSOXSEG7EI16_V_MF4_MF4 = 9663,
9688 PseudoVSOXSEG7EI16_V_MF4_MF4_MASK = 9664,
9689 PseudoVSOXSEG7EI16_V_MF4_MF8 = 9665,
9690 PseudoVSOXSEG7EI16_V_MF4_MF8_MASK = 9666,
9691 PseudoVSOXSEG7EI32_V_M1_M1 = 9667,
9692 PseudoVSOXSEG7EI32_V_M1_M1_MASK = 9668,
9693 PseudoVSOXSEG7EI32_V_M1_MF2 = 9669,
9694 PseudoVSOXSEG7EI32_V_M1_MF2_MASK = 9670,
9695 PseudoVSOXSEG7EI32_V_M1_MF4 = 9671,
9696 PseudoVSOXSEG7EI32_V_M1_MF4_MASK = 9672,
9697 PseudoVSOXSEG7EI32_V_M2_M1 = 9673,
9698 PseudoVSOXSEG7EI32_V_M2_M1_MASK = 9674,
9699 PseudoVSOXSEG7EI32_V_M2_MF2 = 9675,
9700 PseudoVSOXSEG7EI32_V_M2_MF2_MASK = 9676,
9701 PseudoVSOXSEG7EI32_V_M4_M1 = 9677,
9702 PseudoVSOXSEG7EI32_V_M4_M1_MASK = 9678,
9703 PseudoVSOXSEG7EI32_V_MF2_M1 = 9679,
9704 PseudoVSOXSEG7EI32_V_MF2_M1_MASK = 9680,
9705 PseudoVSOXSEG7EI32_V_MF2_MF2 = 9681,
9706 PseudoVSOXSEG7EI32_V_MF2_MF2_MASK = 9682,
9707 PseudoVSOXSEG7EI32_V_MF2_MF4 = 9683,
9708 PseudoVSOXSEG7EI32_V_MF2_MF4_MASK = 9684,
9709 PseudoVSOXSEG7EI32_V_MF2_MF8 = 9685,
9710 PseudoVSOXSEG7EI32_V_MF2_MF8_MASK = 9686,
9711 PseudoVSOXSEG7EI64_V_M1_M1 = 9687,
9712 PseudoVSOXSEG7EI64_V_M1_M1_MASK = 9688,
9713 PseudoVSOXSEG7EI64_V_M1_MF2 = 9689,
9714 PseudoVSOXSEG7EI64_V_M1_MF2_MASK = 9690,
9715 PseudoVSOXSEG7EI64_V_M1_MF4 = 9691,
9716 PseudoVSOXSEG7EI64_V_M1_MF4_MASK = 9692,
9717 PseudoVSOXSEG7EI64_V_M1_MF8 = 9693,
9718 PseudoVSOXSEG7EI64_V_M1_MF8_MASK = 9694,
9719 PseudoVSOXSEG7EI64_V_M2_M1 = 9695,
9720 PseudoVSOXSEG7EI64_V_M2_M1_MASK = 9696,
9721 PseudoVSOXSEG7EI64_V_M2_MF2 = 9697,
9722 PseudoVSOXSEG7EI64_V_M2_MF2_MASK = 9698,
9723 PseudoVSOXSEG7EI64_V_M2_MF4 = 9699,
9724 PseudoVSOXSEG7EI64_V_M2_MF4_MASK = 9700,
9725 PseudoVSOXSEG7EI64_V_M4_M1 = 9701,
9726 PseudoVSOXSEG7EI64_V_M4_M1_MASK = 9702,
9727 PseudoVSOXSEG7EI64_V_M4_MF2 = 9703,
9728 PseudoVSOXSEG7EI64_V_M4_MF2_MASK = 9704,
9729 PseudoVSOXSEG7EI64_V_M8_M1 = 9705,
9730 PseudoVSOXSEG7EI64_V_M8_M1_MASK = 9706,
9731 PseudoVSOXSEG7EI8_V_M1_M1 = 9707,
9732 PseudoVSOXSEG7EI8_V_M1_M1_MASK = 9708,
9733 PseudoVSOXSEG7EI8_V_MF2_M1 = 9709,
9734 PseudoVSOXSEG7EI8_V_MF2_M1_MASK = 9710,
9735 PseudoVSOXSEG7EI8_V_MF2_MF2 = 9711,
9736 PseudoVSOXSEG7EI8_V_MF2_MF2_MASK = 9712,
9737 PseudoVSOXSEG7EI8_V_MF4_M1 = 9713,
9738 PseudoVSOXSEG7EI8_V_MF4_M1_MASK = 9714,
9739 PseudoVSOXSEG7EI8_V_MF4_MF2 = 9715,
9740 PseudoVSOXSEG7EI8_V_MF4_MF2_MASK = 9716,
9741 PseudoVSOXSEG7EI8_V_MF4_MF4 = 9717,
9742 PseudoVSOXSEG7EI8_V_MF4_MF4_MASK = 9718,
9743 PseudoVSOXSEG7EI8_V_MF8_M1 = 9719,
9744 PseudoVSOXSEG7EI8_V_MF8_M1_MASK = 9720,
9745 PseudoVSOXSEG7EI8_V_MF8_MF2 = 9721,
9746 PseudoVSOXSEG7EI8_V_MF8_MF2_MASK = 9722,
9747 PseudoVSOXSEG7EI8_V_MF8_MF4 = 9723,
9748 PseudoVSOXSEG7EI8_V_MF8_MF4_MASK = 9724,
9749 PseudoVSOXSEG7EI8_V_MF8_MF8 = 9725,
9750 PseudoVSOXSEG7EI8_V_MF8_MF8_MASK = 9726,
9751 PseudoVSOXSEG8EI16_V_M1_M1 = 9727,
9752 PseudoVSOXSEG8EI16_V_M1_M1_MASK = 9728,
9753 PseudoVSOXSEG8EI16_V_M1_MF2 = 9729,
9754 PseudoVSOXSEG8EI16_V_M1_MF2_MASK = 9730,
9755 PseudoVSOXSEG8EI16_V_M2_M1 = 9731,
9756 PseudoVSOXSEG8EI16_V_M2_M1_MASK = 9732,
9757 PseudoVSOXSEG8EI16_V_MF2_M1 = 9733,
9758 PseudoVSOXSEG8EI16_V_MF2_M1_MASK = 9734,
9759 PseudoVSOXSEG8EI16_V_MF2_MF2 = 9735,
9760 PseudoVSOXSEG8EI16_V_MF2_MF2_MASK = 9736,
9761 PseudoVSOXSEG8EI16_V_MF2_MF4 = 9737,
9762 PseudoVSOXSEG8EI16_V_MF2_MF4_MASK = 9738,
9763 PseudoVSOXSEG8EI16_V_MF4_M1 = 9739,
9764 PseudoVSOXSEG8EI16_V_MF4_M1_MASK = 9740,
9765 PseudoVSOXSEG8EI16_V_MF4_MF2 = 9741,
9766 PseudoVSOXSEG8EI16_V_MF4_MF2_MASK = 9742,
9767 PseudoVSOXSEG8EI16_V_MF4_MF4 = 9743,
9768 PseudoVSOXSEG8EI16_V_MF4_MF4_MASK = 9744,
9769 PseudoVSOXSEG8EI16_V_MF4_MF8 = 9745,
9770 PseudoVSOXSEG8EI16_V_MF4_MF8_MASK = 9746,
9771 PseudoVSOXSEG8EI32_V_M1_M1 = 9747,
9772 PseudoVSOXSEG8EI32_V_M1_M1_MASK = 9748,
9773 PseudoVSOXSEG8EI32_V_M1_MF2 = 9749,
9774 PseudoVSOXSEG8EI32_V_M1_MF2_MASK = 9750,
9775 PseudoVSOXSEG8EI32_V_M1_MF4 = 9751,
9776 PseudoVSOXSEG8EI32_V_M1_MF4_MASK = 9752,
9777 PseudoVSOXSEG8EI32_V_M2_M1 = 9753,
9778 PseudoVSOXSEG8EI32_V_M2_M1_MASK = 9754,
9779 PseudoVSOXSEG8EI32_V_M2_MF2 = 9755,
9780 PseudoVSOXSEG8EI32_V_M2_MF2_MASK = 9756,
9781 PseudoVSOXSEG8EI32_V_M4_M1 = 9757,
9782 PseudoVSOXSEG8EI32_V_M4_M1_MASK = 9758,
9783 PseudoVSOXSEG8EI32_V_MF2_M1 = 9759,
9784 PseudoVSOXSEG8EI32_V_MF2_M1_MASK = 9760,
9785 PseudoVSOXSEG8EI32_V_MF2_MF2 = 9761,
9786 PseudoVSOXSEG8EI32_V_MF2_MF2_MASK = 9762,
9787 PseudoVSOXSEG8EI32_V_MF2_MF4 = 9763,
9788 PseudoVSOXSEG8EI32_V_MF2_MF4_MASK = 9764,
9789 PseudoVSOXSEG8EI32_V_MF2_MF8 = 9765,
9790 PseudoVSOXSEG8EI32_V_MF2_MF8_MASK = 9766,
9791 PseudoVSOXSEG8EI64_V_M1_M1 = 9767,
9792 PseudoVSOXSEG8EI64_V_M1_M1_MASK = 9768,
9793 PseudoVSOXSEG8EI64_V_M1_MF2 = 9769,
9794 PseudoVSOXSEG8EI64_V_M1_MF2_MASK = 9770,
9795 PseudoVSOXSEG8EI64_V_M1_MF4 = 9771,
9796 PseudoVSOXSEG8EI64_V_M1_MF4_MASK = 9772,
9797 PseudoVSOXSEG8EI64_V_M1_MF8 = 9773,
9798 PseudoVSOXSEG8EI64_V_M1_MF8_MASK = 9774,
9799 PseudoVSOXSEG8EI64_V_M2_M1 = 9775,
9800 PseudoVSOXSEG8EI64_V_M2_M1_MASK = 9776,
9801 PseudoVSOXSEG8EI64_V_M2_MF2 = 9777,
9802 PseudoVSOXSEG8EI64_V_M2_MF2_MASK = 9778,
9803 PseudoVSOXSEG8EI64_V_M2_MF4 = 9779,
9804 PseudoVSOXSEG8EI64_V_M2_MF4_MASK = 9780,
9805 PseudoVSOXSEG8EI64_V_M4_M1 = 9781,
9806 PseudoVSOXSEG8EI64_V_M4_M1_MASK = 9782,
9807 PseudoVSOXSEG8EI64_V_M4_MF2 = 9783,
9808 PseudoVSOXSEG8EI64_V_M4_MF2_MASK = 9784,
9809 PseudoVSOXSEG8EI64_V_M8_M1 = 9785,
9810 PseudoVSOXSEG8EI64_V_M8_M1_MASK = 9786,
9811 PseudoVSOXSEG8EI8_V_M1_M1 = 9787,
9812 PseudoVSOXSEG8EI8_V_M1_M1_MASK = 9788,
9813 PseudoVSOXSEG8EI8_V_MF2_M1 = 9789,
9814 PseudoVSOXSEG8EI8_V_MF2_M1_MASK = 9790,
9815 PseudoVSOXSEG8EI8_V_MF2_MF2 = 9791,
9816 PseudoVSOXSEG8EI8_V_MF2_MF2_MASK = 9792,
9817 PseudoVSOXSEG8EI8_V_MF4_M1 = 9793,
9818 PseudoVSOXSEG8EI8_V_MF4_M1_MASK = 9794,
9819 PseudoVSOXSEG8EI8_V_MF4_MF2 = 9795,
9820 PseudoVSOXSEG8EI8_V_MF4_MF2_MASK = 9796,
9821 PseudoVSOXSEG8EI8_V_MF4_MF4 = 9797,
9822 PseudoVSOXSEG8EI8_V_MF4_MF4_MASK = 9798,
9823 PseudoVSOXSEG8EI8_V_MF8_M1 = 9799,
9824 PseudoVSOXSEG8EI8_V_MF8_M1_MASK = 9800,
9825 PseudoVSOXSEG8EI8_V_MF8_MF2 = 9801,
9826 PseudoVSOXSEG8EI8_V_MF8_MF2_MASK = 9802,
9827 PseudoVSOXSEG8EI8_V_MF8_MF4 = 9803,
9828 PseudoVSOXSEG8EI8_V_MF8_MF4_MASK = 9804,
9829 PseudoVSOXSEG8EI8_V_MF8_MF8 = 9805,
9830 PseudoVSOXSEG8EI8_V_MF8_MF8_MASK = 9806,
9831 PseudoVSPILL2_M1 = 9807,
9832 PseudoVSPILL2_M2 = 9808,
9833 PseudoVSPILL2_M4 = 9809,
9834 PseudoVSPILL2_MF2 = 9810,
9835 PseudoVSPILL2_MF4 = 9811,
9836 PseudoVSPILL2_MF8 = 9812,
9837 PseudoVSPILL3_M1 = 9813,
9838 PseudoVSPILL3_M2 = 9814,
9839 PseudoVSPILL3_MF2 = 9815,
9840 PseudoVSPILL3_MF4 = 9816,
9841 PseudoVSPILL3_MF8 = 9817,
9842 PseudoVSPILL4_M1 = 9818,
9843 PseudoVSPILL4_M2 = 9819,
9844 PseudoVSPILL4_MF2 = 9820,
9845 PseudoVSPILL4_MF4 = 9821,
9846 PseudoVSPILL4_MF8 = 9822,
9847 PseudoVSPILL5_M1 = 9823,
9848 PseudoVSPILL5_MF2 = 9824,
9849 PseudoVSPILL5_MF4 = 9825,
9850 PseudoVSPILL5_MF8 = 9826,
9851 PseudoVSPILL6_M1 = 9827,
9852 PseudoVSPILL6_MF2 = 9828,
9853 PseudoVSPILL6_MF4 = 9829,
9854 PseudoVSPILL6_MF8 = 9830,
9855 PseudoVSPILL7_M1 = 9831,
9856 PseudoVSPILL7_MF2 = 9832,
9857 PseudoVSPILL7_MF4 = 9833,
9858 PseudoVSPILL7_MF8 = 9834,
9859 PseudoVSPILL8_M1 = 9835,
9860 PseudoVSPILL8_MF2 = 9836,
9861 PseudoVSPILL8_MF4 = 9837,
9862 PseudoVSPILL8_MF8 = 9838,
9863 PseudoVSRA_VI_M1 = 9839,
9864 PseudoVSRA_VI_M1_MASK = 9840,
9865 PseudoVSRA_VI_M2 = 9841,
9866 PseudoVSRA_VI_M2_MASK = 9842,
9867 PseudoVSRA_VI_M4 = 9843,
9868 PseudoVSRA_VI_M4_MASK = 9844,
9869 PseudoVSRA_VI_M8 = 9845,
9870 PseudoVSRA_VI_M8_MASK = 9846,
9871 PseudoVSRA_VI_MF2 = 9847,
9872 PseudoVSRA_VI_MF2_MASK = 9848,
9873 PseudoVSRA_VI_MF4 = 9849,
9874 PseudoVSRA_VI_MF4_MASK = 9850,
9875 PseudoVSRA_VI_MF8 = 9851,
9876 PseudoVSRA_VI_MF8_MASK = 9852,
9877 PseudoVSRA_VV_M1 = 9853,
9878 PseudoVSRA_VV_M1_MASK = 9854,
9879 PseudoVSRA_VV_M2 = 9855,
9880 PseudoVSRA_VV_M2_MASK = 9856,
9881 PseudoVSRA_VV_M4 = 9857,
9882 PseudoVSRA_VV_M4_MASK = 9858,
9883 PseudoVSRA_VV_M8 = 9859,
9884 PseudoVSRA_VV_M8_MASK = 9860,
9885 PseudoVSRA_VV_MF2 = 9861,
9886 PseudoVSRA_VV_MF2_MASK = 9862,
9887 PseudoVSRA_VV_MF4 = 9863,
9888 PseudoVSRA_VV_MF4_MASK = 9864,
9889 PseudoVSRA_VV_MF8 = 9865,
9890 PseudoVSRA_VV_MF8_MASK = 9866,
9891 PseudoVSRA_VX_M1 = 9867,
9892 PseudoVSRA_VX_M1_MASK = 9868,
9893 PseudoVSRA_VX_M2 = 9869,
9894 PseudoVSRA_VX_M2_MASK = 9870,
9895 PseudoVSRA_VX_M4 = 9871,
9896 PseudoVSRA_VX_M4_MASK = 9872,
9897 PseudoVSRA_VX_M8 = 9873,
9898 PseudoVSRA_VX_M8_MASK = 9874,
9899 PseudoVSRA_VX_MF2 = 9875,
9900 PseudoVSRA_VX_MF2_MASK = 9876,
9901 PseudoVSRA_VX_MF4 = 9877,
9902 PseudoVSRA_VX_MF4_MASK = 9878,
9903 PseudoVSRA_VX_MF8 = 9879,
9904 PseudoVSRA_VX_MF8_MASK = 9880,
9905 PseudoVSRL_VI_M1 = 9881,
9906 PseudoVSRL_VI_M1_MASK = 9882,
9907 PseudoVSRL_VI_M2 = 9883,
9908 PseudoVSRL_VI_M2_MASK = 9884,
9909 PseudoVSRL_VI_M4 = 9885,
9910 PseudoVSRL_VI_M4_MASK = 9886,
9911 PseudoVSRL_VI_M8 = 9887,
9912 PseudoVSRL_VI_M8_MASK = 9888,
9913 PseudoVSRL_VI_MF2 = 9889,
9914 PseudoVSRL_VI_MF2_MASK = 9890,
9915 PseudoVSRL_VI_MF4 = 9891,
9916 PseudoVSRL_VI_MF4_MASK = 9892,
9917 PseudoVSRL_VI_MF8 = 9893,
9918 PseudoVSRL_VI_MF8_MASK = 9894,
9919 PseudoVSRL_VV_M1 = 9895,
9920 PseudoVSRL_VV_M1_MASK = 9896,
9921 PseudoVSRL_VV_M2 = 9897,
9922 PseudoVSRL_VV_M2_MASK = 9898,
9923 PseudoVSRL_VV_M4 = 9899,
9924 PseudoVSRL_VV_M4_MASK = 9900,
9925 PseudoVSRL_VV_M8 = 9901,
9926 PseudoVSRL_VV_M8_MASK = 9902,
9927 PseudoVSRL_VV_MF2 = 9903,
9928 PseudoVSRL_VV_MF2_MASK = 9904,
9929 PseudoVSRL_VV_MF4 = 9905,
9930 PseudoVSRL_VV_MF4_MASK = 9906,
9931 PseudoVSRL_VV_MF8 = 9907,
9932 PseudoVSRL_VV_MF8_MASK = 9908,
9933 PseudoVSRL_VX_M1 = 9909,
9934 PseudoVSRL_VX_M1_MASK = 9910,
9935 PseudoVSRL_VX_M2 = 9911,
9936 PseudoVSRL_VX_M2_MASK = 9912,
9937 PseudoVSRL_VX_M4 = 9913,
9938 PseudoVSRL_VX_M4_MASK = 9914,
9939 PseudoVSRL_VX_M8 = 9915,
9940 PseudoVSRL_VX_M8_MASK = 9916,
9941 PseudoVSRL_VX_MF2 = 9917,
9942 PseudoVSRL_VX_MF2_MASK = 9918,
9943 PseudoVSRL_VX_MF4 = 9919,
9944 PseudoVSRL_VX_MF4_MASK = 9920,
9945 PseudoVSRL_VX_MF8 = 9921,
9946 PseudoVSRL_VX_MF8_MASK = 9922,
9947 PseudoVSSE16_V_M1 = 9923,
9948 PseudoVSSE16_V_M1_MASK = 9924,
9949 PseudoVSSE16_V_M2 = 9925,
9950 PseudoVSSE16_V_M2_MASK = 9926,
9951 PseudoVSSE16_V_M4 = 9927,
9952 PseudoVSSE16_V_M4_MASK = 9928,
9953 PseudoVSSE16_V_M8 = 9929,
9954 PseudoVSSE16_V_M8_MASK = 9930,
9955 PseudoVSSE16_V_MF2 = 9931,
9956 PseudoVSSE16_V_MF2_MASK = 9932,
9957 PseudoVSSE16_V_MF4 = 9933,
9958 PseudoVSSE16_V_MF4_MASK = 9934,
9959 PseudoVSSE32_V_M1 = 9935,
9960 PseudoVSSE32_V_M1_MASK = 9936,
9961 PseudoVSSE32_V_M2 = 9937,
9962 PseudoVSSE32_V_M2_MASK = 9938,
9963 PseudoVSSE32_V_M4 = 9939,
9964 PseudoVSSE32_V_M4_MASK = 9940,
9965 PseudoVSSE32_V_M8 = 9941,
9966 PseudoVSSE32_V_M8_MASK = 9942,
9967 PseudoVSSE32_V_MF2 = 9943,
9968 PseudoVSSE32_V_MF2_MASK = 9944,
9969 PseudoVSSE64_V_M1 = 9945,
9970 PseudoVSSE64_V_M1_MASK = 9946,
9971 PseudoVSSE64_V_M2 = 9947,
9972 PseudoVSSE64_V_M2_MASK = 9948,
9973 PseudoVSSE64_V_M4 = 9949,
9974 PseudoVSSE64_V_M4_MASK = 9950,
9975 PseudoVSSE64_V_M8 = 9951,
9976 PseudoVSSE64_V_M8_MASK = 9952,
9977 PseudoVSSE8_V_M1 = 9953,
9978 PseudoVSSE8_V_M1_MASK = 9954,
9979 PseudoVSSE8_V_M2 = 9955,
9980 PseudoVSSE8_V_M2_MASK = 9956,
9981 PseudoVSSE8_V_M4 = 9957,
9982 PseudoVSSE8_V_M4_MASK = 9958,
9983 PseudoVSSE8_V_M8 = 9959,
9984 PseudoVSSE8_V_M8_MASK = 9960,
9985 PseudoVSSE8_V_MF2 = 9961,
9986 PseudoVSSE8_V_MF2_MASK = 9962,
9987 PseudoVSSE8_V_MF4 = 9963,
9988 PseudoVSSE8_V_MF4_MASK = 9964,
9989 PseudoVSSE8_V_MF8 = 9965,
9990 PseudoVSSE8_V_MF8_MASK = 9966,
9991 PseudoVSSEG2E16_V_M1 = 9967,
9992 PseudoVSSEG2E16_V_M1_MASK = 9968,
9993 PseudoVSSEG2E16_V_M2 = 9969,
9994 PseudoVSSEG2E16_V_M2_MASK = 9970,
9995 PseudoVSSEG2E16_V_M4 = 9971,
9996 PseudoVSSEG2E16_V_M4_MASK = 9972,
9997 PseudoVSSEG2E16_V_MF2 = 9973,
9998 PseudoVSSEG2E16_V_MF2_MASK = 9974,
9999 PseudoVSSEG2E16_V_MF4 = 9975,
10000 PseudoVSSEG2E16_V_MF4_MASK = 9976,
10001 PseudoVSSEG2E32_V_M1 = 9977,
10002 PseudoVSSEG2E32_V_M1_MASK = 9978,
10003 PseudoVSSEG2E32_V_M2 = 9979,
10004 PseudoVSSEG2E32_V_M2_MASK = 9980,
10005 PseudoVSSEG2E32_V_M4 = 9981,
10006 PseudoVSSEG2E32_V_M4_MASK = 9982,
10007 PseudoVSSEG2E32_V_MF2 = 9983,
10008 PseudoVSSEG2E32_V_MF2_MASK = 9984,
10009 PseudoVSSEG2E64_V_M1 = 9985,
10010 PseudoVSSEG2E64_V_M1_MASK = 9986,
10011 PseudoVSSEG2E64_V_M2 = 9987,
10012 PseudoVSSEG2E64_V_M2_MASK = 9988,
10013 PseudoVSSEG2E64_V_M4 = 9989,
10014 PseudoVSSEG2E64_V_M4_MASK = 9990,
10015 PseudoVSSEG2E8_V_M1 = 9991,
10016 PseudoVSSEG2E8_V_M1_MASK = 9992,
10017 PseudoVSSEG2E8_V_M2 = 9993,
10018 PseudoVSSEG2E8_V_M2_MASK = 9994,
10019 PseudoVSSEG2E8_V_M4 = 9995,
10020 PseudoVSSEG2E8_V_M4_MASK = 9996,
10021 PseudoVSSEG2E8_V_MF2 = 9997,
10022 PseudoVSSEG2E8_V_MF2_MASK = 9998,
10023 PseudoVSSEG2E8_V_MF4 = 9999,
10024 PseudoVSSEG2E8_V_MF4_MASK = 10000,
10025 PseudoVSSEG2E8_V_MF8 = 10001,
10026 PseudoVSSEG2E8_V_MF8_MASK = 10002,
10027 PseudoVSSEG3E16_V_M1 = 10003,
10028 PseudoVSSEG3E16_V_M1_MASK = 10004,
10029 PseudoVSSEG3E16_V_M2 = 10005,
10030 PseudoVSSEG3E16_V_M2_MASK = 10006,
10031 PseudoVSSEG3E16_V_MF2 = 10007,
10032 PseudoVSSEG3E16_V_MF2_MASK = 10008,
10033 PseudoVSSEG3E16_V_MF4 = 10009,
10034 PseudoVSSEG3E16_V_MF4_MASK = 10010,
10035 PseudoVSSEG3E32_V_M1 = 10011,
10036 PseudoVSSEG3E32_V_M1_MASK = 10012,
10037 PseudoVSSEG3E32_V_M2 = 10013,
10038 PseudoVSSEG3E32_V_M2_MASK = 10014,
10039 PseudoVSSEG3E32_V_MF2 = 10015,
10040 PseudoVSSEG3E32_V_MF2_MASK = 10016,
10041 PseudoVSSEG3E64_V_M1 = 10017,
10042 PseudoVSSEG3E64_V_M1_MASK = 10018,
10043 PseudoVSSEG3E64_V_M2 = 10019,
10044 PseudoVSSEG3E64_V_M2_MASK = 10020,
10045 PseudoVSSEG3E8_V_M1 = 10021,
10046 PseudoVSSEG3E8_V_M1_MASK = 10022,
10047 PseudoVSSEG3E8_V_M2 = 10023,
10048 PseudoVSSEG3E8_V_M2_MASK = 10024,
10049 PseudoVSSEG3E8_V_MF2 = 10025,
10050 PseudoVSSEG3E8_V_MF2_MASK = 10026,
10051 PseudoVSSEG3E8_V_MF4 = 10027,
10052 PseudoVSSEG3E8_V_MF4_MASK = 10028,
10053 PseudoVSSEG3E8_V_MF8 = 10029,
10054 PseudoVSSEG3E8_V_MF8_MASK = 10030,
10055 PseudoVSSEG4E16_V_M1 = 10031,
10056 PseudoVSSEG4E16_V_M1_MASK = 10032,
10057 PseudoVSSEG4E16_V_M2 = 10033,
10058 PseudoVSSEG4E16_V_M2_MASK = 10034,
10059 PseudoVSSEG4E16_V_MF2 = 10035,
10060 PseudoVSSEG4E16_V_MF2_MASK = 10036,
10061 PseudoVSSEG4E16_V_MF4 = 10037,
10062 PseudoVSSEG4E16_V_MF4_MASK = 10038,
10063 PseudoVSSEG4E32_V_M1 = 10039,
10064 PseudoVSSEG4E32_V_M1_MASK = 10040,
10065 PseudoVSSEG4E32_V_M2 = 10041,
10066 PseudoVSSEG4E32_V_M2_MASK = 10042,
10067 PseudoVSSEG4E32_V_MF2 = 10043,
10068 PseudoVSSEG4E32_V_MF2_MASK = 10044,
10069 PseudoVSSEG4E64_V_M1 = 10045,
10070 PseudoVSSEG4E64_V_M1_MASK = 10046,
10071 PseudoVSSEG4E64_V_M2 = 10047,
10072 PseudoVSSEG4E64_V_M2_MASK = 10048,
10073 PseudoVSSEG4E8_V_M1 = 10049,
10074 PseudoVSSEG4E8_V_M1_MASK = 10050,
10075 PseudoVSSEG4E8_V_M2 = 10051,
10076 PseudoVSSEG4E8_V_M2_MASK = 10052,
10077 PseudoVSSEG4E8_V_MF2 = 10053,
10078 PseudoVSSEG4E8_V_MF2_MASK = 10054,
10079 PseudoVSSEG4E8_V_MF4 = 10055,
10080 PseudoVSSEG4E8_V_MF4_MASK = 10056,
10081 PseudoVSSEG4E8_V_MF8 = 10057,
10082 PseudoVSSEG4E8_V_MF8_MASK = 10058,
10083 PseudoVSSEG5E16_V_M1 = 10059,
10084 PseudoVSSEG5E16_V_M1_MASK = 10060,
10085 PseudoVSSEG5E16_V_MF2 = 10061,
10086 PseudoVSSEG5E16_V_MF2_MASK = 10062,
10087 PseudoVSSEG5E16_V_MF4 = 10063,
10088 PseudoVSSEG5E16_V_MF4_MASK = 10064,
10089 PseudoVSSEG5E32_V_M1 = 10065,
10090 PseudoVSSEG5E32_V_M1_MASK = 10066,
10091 PseudoVSSEG5E32_V_MF2 = 10067,
10092 PseudoVSSEG5E32_V_MF2_MASK = 10068,
10093 PseudoVSSEG5E64_V_M1 = 10069,
10094 PseudoVSSEG5E64_V_M1_MASK = 10070,
10095 PseudoVSSEG5E8_V_M1 = 10071,
10096 PseudoVSSEG5E8_V_M1_MASK = 10072,
10097 PseudoVSSEG5E8_V_MF2 = 10073,
10098 PseudoVSSEG5E8_V_MF2_MASK = 10074,
10099 PseudoVSSEG5E8_V_MF4 = 10075,
10100 PseudoVSSEG5E8_V_MF4_MASK = 10076,
10101 PseudoVSSEG5E8_V_MF8 = 10077,
10102 PseudoVSSEG5E8_V_MF8_MASK = 10078,
10103 PseudoVSSEG6E16_V_M1 = 10079,
10104 PseudoVSSEG6E16_V_M1_MASK = 10080,
10105 PseudoVSSEG6E16_V_MF2 = 10081,
10106 PseudoVSSEG6E16_V_MF2_MASK = 10082,
10107 PseudoVSSEG6E16_V_MF4 = 10083,
10108 PseudoVSSEG6E16_V_MF4_MASK = 10084,
10109 PseudoVSSEG6E32_V_M1 = 10085,
10110 PseudoVSSEG6E32_V_M1_MASK = 10086,
10111 PseudoVSSEG6E32_V_MF2 = 10087,
10112 PseudoVSSEG6E32_V_MF2_MASK = 10088,
10113 PseudoVSSEG6E64_V_M1 = 10089,
10114 PseudoVSSEG6E64_V_M1_MASK = 10090,
10115 PseudoVSSEG6E8_V_M1 = 10091,
10116 PseudoVSSEG6E8_V_M1_MASK = 10092,
10117 PseudoVSSEG6E8_V_MF2 = 10093,
10118 PseudoVSSEG6E8_V_MF2_MASK = 10094,
10119 PseudoVSSEG6E8_V_MF4 = 10095,
10120 PseudoVSSEG6E8_V_MF4_MASK = 10096,
10121 PseudoVSSEG6E8_V_MF8 = 10097,
10122 PseudoVSSEG6E8_V_MF8_MASK = 10098,
10123 PseudoVSSEG7E16_V_M1 = 10099,
10124 PseudoVSSEG7E16_V_M1_MASK = 10100,
10125 PseudoVSSEG7E16_V_MF2 = 10101,
10126 PseudoVSSEG7E16_V_MF2_MASK = 10102,
10127 PseudoVSSEG7E16_V_MF4 = 10103,
10128 PseudoVSSEG7E16_V_MF4_MASK = 10104,
10129 PseudoVSSEG7E32_V_M1 = 10105,
10130 PseudoVSSEG7E32_V_M1_MASK = 10106,
10131 PseudoVSSEG7E32_V_MF2 = 10107,
10132 PseudoVSSEG7E32_V_MF2_MASK = 10108,
10133 PseudoVSSEG7E64_V_M1 = 10109,
10134 PseudoVSSEG7E64_V_M1_MASK = 10110,
10135 PseudoVSSEG7E8_V_M1 = 10111,
10136 PseudoVSSEG7E8_V_M1_MASK = 10112,
10137 PseudoVSSEG7E8_V_MF2 = 10113,
10138 PseudoVSSEG7E8_V_MF2_MASK = 10114,
10139 PseudoVSSEG7E8_V_MF4 = 10115,
10140 PseudoVSSEG7E8_V_MF4_MASK = 10116,
10141 PseudoVSSEG7E8_V_MF8 = 10117,
10142 PseudoVSSEG7E8_V_MF8_MASK = 10118,
10143 PseudoVSSEG8E16_V_M1 = 10119,
10144 PseudoVSSEG8E16_V_M1_MASK = 10120,
10145 PseudoVSSEG8E16_V_MF2 = 10121,
10146 PseudoVSSEG8E16_V_MF2_MASK = 10122,
10147 PseudoVSSEG8E16_V_MF4 = 10123,
10148 PseudoVSSEG8E16_V_MF4_MASK = 10124,
10149 PseudoVSSEG8E32_V_M1 = 10125,
10150 PseudoVSSEG8E32_V_M1_MASK = 10126,
10151 PseudoVSSEG8E32_V_MF2 = 10127,
10152 PseudoVSSEG8E32_V_MF2_MASK = 10128,
10153 PseudoVSSEG8E64_V_M1 = 10129,
10154 PseudoVSSEG8E64_V_M1_MASK = 10130,
10155 PseudoVSSEG8E8_V_M1 = 10131,
10156 PseudoVSSEG8E8_V_M1_MASK = 10132,
10157 PseudoVSSEG8E8_V_MF2 = 10133,
10158 PseudoVSSEG8E8_V_MF2_MASK = 10134,
10159 PseudoVSSEG8E8_V_MF4 = 10135,
10160 PseudoVSSEG8E8_V_MF4_MASK = 10136,
10161 PseudoVSSEG8E8_V_MF8 = 10137,
10162 PseudoVSSEG8E8_V_MF8_MASK = 10138,
10163 PseudoVSSRA_VI_M1 = 10139,
10164 PseudoVSSRA_VI_M1_MASK = 10140,
10165 PseudoVSSRA_VI_M2 = 10141,
10166 PseudoVSSRA_VI_M2_MASK = 10142,
10167 PseudoVSSRA_VI_M4 = 10143,
10168 PseudoVSSRA_VI_M4_MASK = 10144,
10169 PseudoVSSRA_VI_M8 = 10145,
10170 PseudoVSSRA_VI_M8_MASK = 10146,
10171 PseudoVSSRA_VI_MF2 = 10147,
10172 PseudoVSSRA_VI_MF2_MASK = 10148,
10173 PseudoVSSRA_VI_MF4 = 10149,
10174 PseudoVSSRA_VI_MF4_MASK = 10150,
10175 PseudoVSSRA_VI_MF8 = 10151,
10176 PseudoVSSRA_VI_MF8_MASK = 10152,
10177 PseudoVSSRA_VV_M1 = 10153,
10178 PseudoVSSRA_VV_M1_MASK = 10154,
10179 PseudoVSSRA_VV_M2 = 10155,
10180 PseudoVSSRA_VV_M2_MASK = 10156,
10181 PseudoVSSRA_VV_M4 = 10157,
10182 PseudoVSSRA_VV_M4_MASK = 10158,
10183 PseudoVSSRA_VV_M8 = 10159,
10184 PseudoVSSRA_VV_M8_MASK = 10160,
10185 PseudoVSSRA_VV_MF2 = 10161,
10186 PseudoVSSRA_VV_MF2_MASK = 10162,
10187 PseudoVSSRA_VV_MF4 = 10163,
10188 PseudoVSSRA_VV_MF4_MASK = 10164,
10189 PseudoVSSRA_VV_MF8 = 10165,
10190 PseudoVSSRA_VV_MF8_MASK = 10166,
10191 PseudoVSSRA_VX_M1 = 10167,
10192 PseudoVSSRA_VX_M1_MASK = 10168,
10193 PseudoVSSRA_VX_M2 = 10169,
10194 PseudoVSSRA_VX_M2_MASK = 10170,
10195 PseudoVSSRA_VX_M4 = 10171,
10196 PseudoVSSRA_VX_M4_MASK = 10172,
10197 PseudoVSSRA_VX_M8 = 10173,
10198 PseudoVSSRA_VX_M8_MASK = 10174,
10199 PseudoVSSRA_VX_MF2 = 10175,
10200 PseudoVSSRA_VX_MF2_MASK = 10176,
10201 PseudoVSSRA_VX_MF4 = 10177,
10202 PseudoVSSRA_VX_MF4_MASK = 10178,
10203 PseudoVSSRA_VX_MF8 = 10179,
10204 PseudoVSSRA_VX_MF8_MASK = 10180,
10205 PseudoVSSRL_VI_M1 = 10181,
10206 PseudoVSSRL_VI_M1_MASK = 10182,
10207 PseudoVSSRL_VI_M2 = 10183,
10208 PseudoVSSRL_VI_M2_MASK = 10184,
10209 PseudoVSSRL_VI_M4 = 10185,
10210 PseudoVSSRL_VI_M4_MASK = 10186,
10211 PseudoVSSRL_VI_M8 = 10187,
10212 PseudoVSSRL_VI_M8_MASK = 10188,
10213 PseudoVSSRL_VI_MF2 = 10189,
10214 PseudoVSSRL_VI_MF2_MASK = 10190,
10215 PseudoVSSRL_VI_MF4 = 10191,
10216 PseudoVSSRL_VI_MF4_MASK = 10192,
10217 PseudoVSSRL_VI_MF8 = 10193,
10218 PseudoVSSRL_VI_MF8_MASK = 10194,
10219 PseudoVSSRL_VV_M1 = 10195,
10220 PseudoVSSRL_VV_M1_MASK = 10196,
10221 PseudoVSSRL_VV_M2 = 10197,
10222 PseudoVSSRL_VV_M2_MASK = 10198,
10223 PseudoVSSRL_VV_M4 = 10199,
10224 PseudoVSSRL_VV_M4_MASK = 10200,
10225 PseudoVSSRL_VV_M8 = 10201,
10226 PseudoVSSRL_VV_M8_MASK = 10202,
10227 PseudoVSSRL_VV_MF2 = 10203,
10228 PseudoVSSRL_VV_MF2_MASK = 10204,
10229 PseudoVSSRL_VV_MF4 = 10205,
10230 PseudoVSSRL_VV_MF4_MASK = 10206,
10231 PseudoVSSRL_VV_MF8 = 10207,
10232 PseudoVSSRL_VV_MF8_MASK = 10208,
10233 PseudoVSSRL_VX_M1 = 10209,
10234 PseudoVSSRL_VX_M1_MASK = 10210,
10235 PseudoVSSRL_VX_M2 = 10211,
10236 PseudoVSSRL_VX_M2_MASK = 10212,
10237 PseudoVSSRL_VX_M4 = 10213,
10238 PseudoVSSRL_VX_M4_MASK = 10214,
10239 PseudoVSSRL_VX_M8 = 10215,
10240 PseudoVSSRL_VX_M8_MASK = 10216,
10241 PseudoVSSRL_VX_MF2 = 10217,
10242 PseudoVSSRL_VX_MF2_MASK = 10218,
10243 PseudoVSSRL_VX_MF4 = 10219,
10244 PseudoVSSRL_VX_MF4_MASK = 10220,
10245 PseudoVSSRL_VX_MF8 = 10221,
10246 PseudoVSSRL_VX_MF8_MASK = 10222,
10247 PseudoVSSSEG2E16_V_M1 = 10223,
10248 PseudoVSSSEG2E16_V_M1_MASK = 10224,
10249 PseudoVSSSEG2E16_V_M2 = 10225,
10250 PseudoVSSSEG2E16_V_M2_MASK = 10226,
10251 PseudoVSSSEG2E16_V_M4 = 10227,
10252 PseudoVSSSEG2E16_V_M4_MASK = 10228,
10253 PseudoVSSSEG2E16_V_MF2 = 10229,
10254 PseudoVSSSEG2E16_V_MF2_MASK = 10230,
10255 PseudoVSSSEG2E16_V_MF4 = 10231,
10256 PseudoVSSSEG2E16_V_MF4_MASK = 10232,
10257 PseudoVSSSEG2E32_V_M1 = 10233,
10258 PseudoVSSSEG2E32_V_M1_MASK = 10234,
10259 PseudoVSSSEG2E32_V_M2 = 10235,
10260 PseudoVSSSEG2E32_V_M2_MASK = 10236,
10261 PseudoVSSSEG2E32_V_M4 = 10237,
10262 PseudoVSSSEG2E32_V_M4_MASK = 10238,
10263 PseudoVSSSEG2E32_V_MF2 = 10239,
10264 PseudoVSSSEG2E32_V_MF2_MASK = 10240,
10265 PseudoVSSSEG2E64_V_M1 = 10241,
10266 PseudoVSSSEG2E64_V_M1_MASK = 10242,
10267 PseudoVSSSEG2E64_V_M2 = 10243,
10268 PseudoVSSSEG2E64_V_M2_MASK = 10244,
10269 PseudoVSSSEG2E64_V_M4 = 10245,
10270 PseudoVSSSEG2E64_V_M4_MASK = 10246,
10271 PseudoVSSSEG2E8_V_M1 = 10247,
10272 PseudoVSSSEG2E8_V_M1_MASK = 10248,
10273 PseudoVSSSEG2E8_V_M2 = 10249,
10274 PseudoVSSSEG2E8_V_M2_MASK = 10250,
10275 PseudoVSSSEG2E8_V_M4 = 10251,
10276 PseudoVSSSEG2E8_V_M4_MASK = 10252,
10277 PseudoVSSSEG2E8_V_MF2 = 10253,
10278 PseudoVSSSEG2E8_V_MF2_MASK = 10254,
10279 PseudoVSSSEG2E8_V_MF4 = 10255,
10280 PseudoVSSSEG2E8_V_MF4_MASK = 10256,
10281 PseudoVSSSEG2E8_V_MF8 = 10257,
10282 PseudoVSSSEG2E8_V_MF8_MASK = 10258,
10283 PseudoVSSSEG3E16_V_M1 = 10259,
10284 PseudoVSSSEG3E16_V_M1_MASK = 10260,
10285 PseudoVSSSEG3E16_V_M2 = 10261,
10286 PseudoVSSSEG3E16_V_M2_MASK = 10262,
10287 PseudoVSSSEG3E16_V_MF2 = 10263,
10288 PseudoVSSSEG3E16_V_MF2_MASK = 10264,
10289 PseudoVSSSEG3E16_V_MF4 = 10265,
10290 PseudoVSSSEG3E16_V_MF4_MASK = 10266,
10291 PseudoVSSSEG3E32_V_M1 = 10267,
10292 PseudoVSSSEG3E32_V_M1_MASK = 10268,
10293 PseudoVSSSEG3E32_V_M2 = 10269,
10294 PseudoVSSSEG3E32_V_M2_MASK = 10270,
10295 PseudoVSSSEG3E32_V_MF2 = 10271,
10296 PseudoVSSSEG3E32_V_MF2_MASK = 10272,
10297 PseudoVSSSEG3E64_V_M1 = 10273,
10298 PseudoVSSSEG3E64_V_M1_MASK = 10274,
10299 PseudoVSSSEG3E64_V_M2 = 10275,
10300 PseudoVSSSEG3E64_V_M2_MASK = 10276,
10301 PseudoVSSSEG3E8_V_M1 = 10277,
10302 PseudoVSSSEG3E8_V_M1_MASK = 10278,
10303 PseudoVSSSEG3E8_V_M2 = 10279,
10304 PseudoVSSSEG3E8_V_M2_MASK = 10280,
10305 PseudoVSSSEG3E8_V_MF2 = 10281,
10306 PseudoVSSSEG3E8_V_MF2_MASK = 10282,
10307 PseudoVSSSEG3E8_V_MF4 = 10283,
10308 PseudoVSSSEG3E8_V_MF4_MASK = 10284,
10309 PseudoVSSSEG3E8_V_MF8 = 10285,
10310 PseudoVSSSEG3E8_V_MF8_MASK = 10286,
10311 PseudoVSSSEG4E16_V_M1 = 10287,
10312 PseudoVSSSEG4E16_V_M1_MASK = 10288,
10313 PseudoVSSSEG4E16_V_M2 = 10289,
10314 PseudoVSSSEG4E16_V_M2_MASK = 10290,
10315 PseudoVSSSEG4E16_V_MF2 = 10291,
10316 PseudoVSSSEG4E16_V_MF2_MASK = 10292,
10317 PseudoVSSSEG4E16_V_MF4 = 10293,
10318 PseudoVSSSEG4E16_V_MF4_MASK = 10294,
10319 PseudoVSSSEG4E32_V_M1 = 10295,
10320 PseudoVSSSEG4E32_V_M1_MASK = 10296,
10321 PseudoVSSSEG4E32_V_M2 = 10297,
10322 PseudoVSSSEG4E32_V_M2_MASK = 10298,
10323 PseudoVSSSEG4E32_V_MF2 = 10299,
10324 PseudoVSSSEG4E32_V_MF2_MASK = 10300,
10325 PseudoVSSSEG4E64_V_M1 = 10301,
10326 PseudoVSSSEG4E64_V_M1_MASK = 10302,
10327 PseudoVSSSEG4E64_V_M2 = 10303,
10328 PseudoVSSSEG4E64_V_M2_MASK = 10304,
10329 PseudoVSSSEG4E8_V_M1 = 10305,
10330 PseudoVSSSEG4E8_V_M1_MASK = 10306,
10331 PseudoVSSSEG4E8_V_M2 = 10307,
10332 PseudoVSSSEG4E8_V_M2_MASK = 10308,
10333 PseudoVSSSEG4E8_V_MF2 = 10309,
10334 PseudoVSSSEG4E8_V_MF2_MASK = 10310,
10335 PseudoVSSSEG4E8_V_MF4 = 10311,
10336 PseudoVSSSEG4E8_V_MF4_MASK = 10312,
10337 PseudoVSSSEG4E8_V_MF8 = 10313,
10338 PseudoVSSSEG4E8_V_MF8_MASK = 10314,
10339 PseudoVSSSEG5E16_V_M1 = 10315,
10340 PseudoVSSSEG5E16_V_M1_MASK = 10316,
10341 PseudoVSSSEG5E16_V_MF2 = 10317,
10342 PseudoVSSSEG5E16_V_MF2_MASK = 10318,
10343 PseudoVSSSEG5E16_V_MF4 = 10319,
10344 PseudoVSSSEG5E16_V_MF4_MASK = 10320,
10345 PseudoVSSSEG5E32_V_M1 = 10321,
10346 PseudoVSSSEG5E32_V_M1_MASK = 10322,
10347 PseudoVSSSEG5E32_V_MF2 = 10323,
10348 PseudoVSSSEG5E32_V_MF2_MASK = 10324,
10349 PseudoVSSSEG5E64_V_M1 = 10325,
10350 PseudoVSSSEG5E64_V_M1_MASK = 10326,
10351 PseudoVSSSEG5E8_V_M1 = 10327,
10352 PseudoVSSSEG5E8_V_M1_MASK = 10328,
10353 PseudoVSSSEG5E8_V_MF2 = 10329,
10354 PseudoVSSSEG5E8_V_MF2_MASK = 10330,
10355 PseudoVSSSEG5E8_V_MF4 = 10331,
10356 PseudoVSSSEG5E8_V_MF4_MASK = 10332,
10357 PseudoVSSSEG5E8_V_MF8 = 10333,
10358 PseudoVSSSEG5E8_V_MF8_MASK = 10334,
10359 PseudoVSSSEG6E16_V_M1 = 10335,
10360 PseudoVSSSEG6E16_V_M1_MASK = 10336,
10361 PseudoVSSSEG6E16_V_MF2 = 10337,
10362 PseudoVSSSEG6E16_V_MF2_MASK = 10338,
10363 PseudoVSSSEG6E16_V_MF4 = 10339,
10364 PseudoVSSSEG6E16_V_MF4_MASK = 10340,
10365 PseudoVSSSEG6E32_V_M1 = 10341,
10366 PseudoVSSSEG6E32_V_M1_MASK = 10342,
10367 PseudoVSSSEG6E32_V_MF2 = 10343,
10368 PseudoVSSSEG6E32_V_MF2_MASK = 10344,
10369 PseudoVSSSEG6E64_V_M1 = 10345,
10370 PseudoVSSSEG6E64_V_M1_MASK = 10346,
10371 PseudoVSSSEG6E8_V_M1 = 10347,
10372 PseudoVSSSEG6E8_V_M1_MASK = 10348,
10373 PseudoVSSSEG6E8_V_MF2 = 10349,
10374 PseudoVSSSEG6E8_V_MF2_MASK = 10350,
10375 PseudoVSSSEG6E8_V_MF4 = 10351,
10376 PseudoVSSSEG6E8_V_MF4_MASK = 10352,
10377 PseudoVSSSEG6E8_V_MF8 = 10353,
10378 PseudoVSSSEG6E8_V_MF8_MASK = 10354,
10379 PseudoVSSSEG7E16_V_M1 = 10355,
10380 PseudoVSSSEG7E16_V_M1_MASK = 10356,
10381 PseudoVSSSEG7E16_V_MF2 = 10357,
10382 PseudoVSSSEG7E16_V_MF2_MASK = 10358,
10383 PseudoVSSSEG7E16_V_MF4 = 10359,
10384 PseudoVSSSEG7E16_V_MF4_MASK = 10360,
10385 PseudoVSSSEG7E32_V_M1 = 10361,
10386 PseudoVSSSEG7E32_V_M1_MASK = 10362,
10387 PseudoVSSSEG7E32_V_MF2 = 10363,
10388 PseudoVSSSEG7E32_V_MF2_MASK = 10364,
10389 PseudoVSSSEG7E64_V_M1 = 10365,
10390 PseudoVSSSEG7E64_V_M1_MASK = 10366,
10391 PseudoVSSSEG7E8_V_M1 = 10367,
10392 PseudoVSSSEG7E8_V_M1_MASK = 10368,
10393 PseudoVSSSEG7E8_V_MF2 = 10369,
10394 PseudoVSSSEG7E8_V_MF2_MASK = 10370,
10395 PseudoVSSSEG7E8_V_MF4 = 10371,
10396 PseudoVSSSEG7E8_V_MF4_MASK = 10372,
10397 PseudoVSSSEG7E8_V_MF8 = 10373,
10398 PseudoVSSSEG7E8_V_MF8_MASK = 10374,
10399 PseudoVSSSEG8E16_V_M1 = 10375,
10400 PseudoVSSSEG8E16_V_M1_MASK = 10376,
10401 PseudoVSSSEG8E16_V_MF2 = 10377,
10402 PseudoVSSSEG8E16_V_MF2_MASK = 10378,
10403 PseudoVSSSEG8E16_V_MF4 = 10379,
10404 PseudoVSSSEG8E16_V_MF4_MASK = 10380,
10405 PseudoVSSSEG8E32_V_M1 = 10381,
10406 PseudoVSSSEG8E32_V_M1_MASK = 10382,
10407 PseudoVSSSEG8E32_V_MF2 = 10383,
10408 PseudoVSSSEG8E32_V_MF2_MASK = 10384,
10409 PseudoVSSSEG8E64_V_M1 = 10385,
10410 PseudoVSSSEG8E64_V_M1_MASK = 10386,
10411 PseudoVSSSEG8E8_V_M1 = 10387,
10412 PseudoVSSSEG8E8_V_M1_MASK = 10388,
10413 PseudoVSSSEG8E8_V_MF2 = 10389,
10414 PseudoVSSSEG8E8_V_MF2_MASK = 10390,
10415 PseudoVSSSEG8E8_V_MF4 = 10391,
10416 PseudoVSSSEG8E8_V_MF4_MASK = 10392,
10417 PseudoVSSSEG8E8_V_MF8 = 10393,
10418 PseudoVSSSEG8E8_V_MF8_MASK = 10394,
10419 PseudoVSSUBU_VV_M1 = 10395,
10420 PseudoVSSUBU_VV_M1_MASK = 10396,
10421 PseudoVSSUBU_VV_M2 = 10397,
10422 PseudoVSSUBU_VV_M2_MASK = 10398,
10423 PseudoVSSUBU_VV_M4 = 10399,
10424 PseudoVSSUBU_VV_M4_MASK = 10400,
10425 PseudoVSSUBU_VV_M8 = 10401,
10426 PseudoVSSUBU_VV_M8_MASK = 10402,
10427 PseudoVSSUBU_VV_MF2 = 10403,
10428 PseudoVSSUBU_VV_MF2_MASK = 10404,
10429 PseudoVSSUBU_VV_MF4 = 10405,
10430 PseudoVSSUBU_VV_MF4_MASK = 10406,
10431 PseudoVSSUBU_VV_MF8 = 10407,
10432 PseudoVSSUBU_VV_MF8_MASK = 10408,
10433 PseudoVSSUBU_VX_M1 = 10409,
10434 PseudoVSSUBU_VX_M1_MASK = 10410,
10435 PseudoVSSUBU_VX_M2 = 10411,
10436 PseudoVSSUBU_VX_M2_MASK = 10412,
10437 PseudoVSSUBU_VX_M4 = 10413,
10438 PseudoVSSUBU_VX_M4_MASK = 10414,
10439 PseudoVSSUBU_VX_M8 = 10415,
10440 PseudoVSSUBU_VX_M8_MASK = 10416,
10441 PseudoVSSUBU_VX_MF2 = 10417,
10442 PseudoVSSUBU_VX_MF2_MASK = 10418,
10443 PseudoVSSUBU_VX_MF4 = 10419,
10444 PseudoVSSUBU_VX_MF4_MASK = 10420,
10445 PseudoVSSUBU_VX_MF8 = 10421,
10446 PseudoVSSUBU_VX_MF8_MASK = 10422,
10447 PseudoVSSUB_VV_M1 = 10423,
10448 PseudoVSSUB_VV_M1_MASK = 10424,
10449 PseudoVSSUB_VV_M2 = 10425,
10450 PseudoVSSUB_VV_M2_MASK = 10426,
10451 PseudoVSSUB_VV_M4 = 10427,
10452 PseudoVSSUB_VV_M4_MASK = 10428,
10453 PseudoVSSUB_VV_M8 = 10429,
10454 PseudoVSSUB_VV_M8_MASK = 10430,
10455 PseudoVSSUB_VV_MF2 = 10431,
10456 PseudoVSSUB_VV_MF2_MASK = 10432,
10457 PseudoVSSUB_VV_MF4 = 10433,
10458 PseudoVSSUB_VV_MF4_MASK = 10434,
10459 PseudoVSSUB_VV_MF8 = 10435,
10460 PseudoVSSUB_VV_MF8_MASK = 10436,
10461 PseudoVSSUB_VX_M1 = 10437,
10462 PseudoVSSUB_VX_M1_MASK = 10438,
10463 PseudoVSSUB_VX_M2 = 10439,
10464 PseudoVSSUB_VX_M2_MASK = 10440,
10465 PseudoVSSUB_VX_M4 = 10441,
10466 PseudoVSSUB_VX_M4_MASK = 10442,
10467 PseudoVSSUB_VX_M8 = 10443,
10468 PseudoVSSUB_VX_M8_MASK = 10444,
10469 PseudoVSSUB_VX_MF2 = 10445,
10470 PseudoVSSUB_VX_MF2_MASK = 10446,
10471 PseudoVSSUB_VX_MF4 = 10447,
10472 PseudoVSSUB_VX_MF4_MASK = 10448,
10473 PseudoVSSUB_VX_MF8 = 10449,
10474 PseudoVSSUB_VX_MF8_MASK = 10450,
10475 PseudoVSUB_VV_M1 = 10451,
10476 PseudoVSUB_VV_M1_MASK = 10452,
10477 PseudoVSUB_VV_M2 = 10453,
10478 PseudoVSUB_VV_M2_MASK = 10454,
10479 PseudoVSUB_VV_M4 = 10455,
10480 PseudoVSUB_VV_M4_MASK = 10456,
10481 PseudoVSUB_VV_M8 = 10457,
10482 PseudoVSUB_VV_M8_MASK = 10458,
10483 PseudoVSUB_VV_MF2 = 10459,
10484 PseudoVSUB_VV_MF2_MASK = 10460,
10485 PseudoVSUB_VV_MF4 = 10461,
10486 PseudoVSUB_VV_MF4_MASK = 10462,
10487 PseudoVSUB_VV_MF8 = 10463,
10488 PseudoVSUB_VV_MF8_MASK = 10464,
10489 PseudoVSUB_VX_M1 = 10465,
10490 PseudoVSUB_VX_M1_MASK = 10466,
10491 PseudoVSUB_VX_M2 = 10467,
10492 PseudoVSUB_VX_M2_MASK = 10468,
10493 PseudoVSUB_VX_M4 = 10469,
10494 PseudoVSUB_VX_M4_MASK = 10470,
10495 PseudoVSUB_VX_M8 = 10471,
10496 PseudoVSUB_VX_M8_MASK = 10472,
10497 PseudoVSUB_VX_MF2 = 10473,
10498 PseudoVSUB_VX_MF2_MASK = 10474,
10499 PseudoVSUB_VX_MF4 = 10475,
10500 PseudoVSUB_VX_MF4_MASK = 10476,
10501 PseudoVSUB_VX_MF8 = 10477,
10502 PseudoVSUB_VX_MF8_MASK = 10478,
10503 PseudoVSUXEI16_V_M1_M1 = 10479,
10504 PseudoVSUXEI16_V_M1_M1_MASK = 10480,
10505 PseudoVSUXEI16_V_M1_M2 = 10481,
10506 PseudoVSUXEI16_V_M1_M2_MASK = 10482,
10507 PseudoVSUXEI16_V_M1_M4 = 10483,
10508 PseudoVSUXEI16_V_M1_M4_MASK = 10484,
10509 PseudoVSUXEI16_V_M1_MF2 = 10485,
10510 PseudoVSUXEI16_V_M1_MF2_MASK = 10486,
10511 PseudoVSUXEI16_V_M2_M1 = 10487,
10512 PseudoVSUXEI16_V_M2_M1_MASK = 10488,
10513 PseudoVSUXEI16_V_M2_M2 = 10489,
10514 PseudoVSUXEI16_V_M2_M2_MASK = 10490,
10515 PseudoVSUXEI16_V_M2_M4 = 10491,
10516 PseudoVSUXEI16_V_M2_M4_MASK = 10492,
10517 PseudoVSUXEI16_V_M2_M8 = 10493,
10518 PseudoVSUXEI16_V_M2_M8_MASK = 10494,
10519 PseudoVSUXEI16_V_M4_M2 = 10495,
10520 PseudoVSUXEI16_V_M4_M2_MASK = 10496,
10521 PseudoVSUXEI16_V_M4_M4 = 10497,
10522 PseudoVSUXEI16_V_M4_M4_MASK = 10498,
10523 PseudoVSUXEI16_V_M4_M8 = 10499,
10524 PseudoVSUXEI16_V_M4_M8_MASK = 10500,
10525 PseudoVSUXEI16_V_M8_M4 = 10501,
10526 PseudoVSUXEI16_V_M8_M4_MASK = 10502,
10527 PseudoVSUXEI16_V_M8_M8 = 10503,
10528 PseudoVSUXEI16_V_M8_M8_MASK = 10504,
10529 PseudoVSUXEI16_V_MF2_M1 = 10505,
10530 PseudoVSUXEI16_V_MF2_M1_MASK = 10506,
10531 PseudoVSUXEI16_V_MF2_M2 = 10507,
10532 PseudoVSUXEI16_V_MF2_M2_MASK = 10508,
10533 PseudoVSUXEI16_V_MF2_MF2 = 10509,
10534 PseudoVSUXEI16_V_MF2_MF2_MASK = 10510,
10535 PseudoVSUXEI16_V_MF2_MF4 = 10511,
10536 PseudoVSUXEI16_V_MF2_MF4_MASK = 10512,
10537 PseudoVSUXEI16_V_MF4_M1 = 10513,
10538 PseudoVSUXEI16_V_MF4_M1_MASK = 10514,
10539 PseudoVSUXEI16_V_MF4_MF2 = 10515,
10540 PseudoVSUXEI16_V_MF4_MF2_MASK = 10516,
10541 PseudoVSUXEI16_V_MF4_MF4 = 10517,
10542 PseudoVSUXEI16_V_MF4_MF4_MASK = 10518,
10543 PseudoVSUXEI16_V_MF4_MF8 = 10519,
10544 PseudoVSUXEI16_V_MF4_MF8_MASK = 10520,
10545 PseudoVSUXEI32_V_M1_M1 = 10521,
10546 PseudoVSUXEI32_V_M1_M1_MASK = 10522,
10547 PseudoVSUXEI32_V_M1_M2 = 10523,
10548 PseudoVSUXEI32_V_M1_M2_MASK = 10524,
10549 PseudoVSUXEI32_V_M1_MF2 = 10525,
10550 PseudoVSUXEI32_V_M1_MF2_MASK = 10526,
10551 PseudoVSUXEI32_V_M1_MF4 = 10527,
10552 PseudoVSUXEI32_V_M1_MF4_MASK = 10528,
10553 PseudoVSUXEI32_V_M2_M1 = 10529,
10554 PseudoVSUXEI32_V_M2_M1_MASK = 10530,
10555 PseudoVSUXEI32_V_M2_M2 = 10531,
10556 PseudoVSUXEI32_V_M2_M2_MASK = 10532,
10557 PseudoVSUXEI32_V_M2_M4 = 10533,
10558 PseudoVSUXEI32_V_M2_M4_MASK = 10534,
10559 PseudoVSUXEI32_V_M2_MF2 = 10535,
10560 PseudoVSUXEI32_V_M2_MF2_MASK = 10536,
10561 PseudoVSUXEI32_V_M4_M1 = 10537,
10562 PseudoVSUXEI32_V_M4_M1_MASK = 10538,
10563 PseudoVSUXEI32_V_M4_M2 = 10539,
10564 PseudoVSUXEI32_V_M4_M2_MASK = 10540,
10565 PseudoVSUXEI32_V_M4_M4 = 10541,
10566 PseudoVSUXEI32_V_M4_M4_MASK = 10542,
10567 PseudoVSUXEI32_V_M4_M8 = 10543,
10568 PseudoVSUXEI32_V_M4_M8_MASK = 10544,
10569 PseudoVSUXEI32_V_M8_M2 = 10545,
10570 PseudoVSUXEI32_V_M8_M2_MASK = 10546,
10571 PseudoVSUXEI32_V_M8_M4 = 10547,
10572 PseudoVSUXEI32_V_M8_M4_MASK = 10548,
10573 PseudoVSUXEI32_V_M8_M8 = 10549,
10574 PseudoVSUXEI32_V_M8_M8_MASK = 10550,
10575 PseudoVSUXEI32_V_MF2_M1 = 10551,
10576 PseudoVSUXEI32_V_MF2_M1_MASK = 10552,
10577 PseudoVSUXEI32_V_MF2_MF2 = 10553,
10578 PseudoVSUXEI32_V_MF2_MF2_MASK = 10554,
10579 PseudoVSUXEI32_V_MF2_MF4 = 10555,
10580 PseudoVSUXEI32_V_MF2_MF4_MASK = 10556,
10581 PseudoVSUXEI32_V_MF2_MF8 = 10557,
10582 PseudoVSUXEI32_V_MF2_MF8_MASK = 10558,
10583 PseudoVSUXEI64_V_M1_M1 = 10559,
10584 PseudoVSUXEI64_V_M1_M1_MASK = 10560,
10585 PseudoVSUXEI64_V_M1_MF2 = 10561,
10586 PseudoVSUXEI64_V_M1_MF2_MASK = 10562,
10587 PseudoVSUXEI64_V_M1_MF4 = 10563,
10588 PseudoVSUXEI64_V_M1_MF4_MASK = 10564,
10589 PseudoVSUXEI64_V_M1_MF8 = 10565,
10590 PseudoVSUXEI64_V_M1_MF8_MASK = 10566,
10591 PseudoVSUXEI64_V_M2_M1 = 10567,
10592 PseudoVSUXEI64_V_M2_M1_MASK = 10568,
10593 PseudoVSUXEI64_V_M2_M2 = 10569,
10594 PseudoVSUXEI64_V_M2_M2_MASK = 10570,
10595 PseudoVSUXEI64_V_M2_MF2 = 10571,
10596 PseudoVSUXEI64_V_M2_MF2_MASK = 10572,
10597 PseudoVSUXEI64_V_M2_MF4 = 10573,
10598 PseudoVSUXEI64_V_M2_MF4_MASK = 10574,
10599 PseudoVSUXEI64_V_M4_M1 = 10575,
10600 PseudoVSUXEI64_V_M4_M1_MASK = 10576,
10601 PseudoVSUXEI64_V_M4_M2 = 10577,
10602 PseudoVSUXEI64_V_M4_M2_MASK = 10578,
10603 PseudoVSUXEI64_V_M4_M4 = 10579,
10604 PseudoVSUXEI64_V_M4_M4_MASK = 10580,
10605 PseudoVSUXEI64_V_M4_MF2 = 10581,
10606 PseudoVSUXEI64_V_M4_MF2_MASK = 10582,
10607 PseudoVSUXEI64_V_M8_M1 = 10583,
10608 PseudoVSUXEI64_V_M8_M1_MASK = 10584,
10609 PseudoVSUXEI64_V_M8_M2 = 10585,
10610 PseudoVSUXEI64_V_M8_M2_MASK = 10586,
10611 PseudoVSUXEI64_V_M8_M4 = 10587,
10612 PseudoVSUXEI64_V_M8_M4_MASK = 10588,
10613 PseudoVSUXEI64_V_M8_M8 = 10589,
10614 PseudoVSUXEI64_V_M8_M8_MASK = 10590,
10615 PseudoVSUXEI8_V_M1_M1 = 10591,
10616 PseudoVSUXEI8_V_M1_M1_MASK = 10592,
10617 PseudoVSUXEI8_V_M1_M2 = 10593,
10618 PseudoVSUXEI8_V_M1_M2_MASK = 10594,
10619 PseudoVSUXEI8_V_M1_M4 = 10595,
10620 PseudoVSUXEI8_V_M1_M4_MASK = 10596,
10621 PseudoVSUXEI8_V_M1_M8 = 10597,
10622 PseudoVSUXEI8_V_M1_M8_MASK = 10598,
10623 PseudoVSUXEI8_V_M2_M2 = 10599,
10624 PseudoVSUXEI8_V_M2_M2_MASK = 10600,
10625 PseudoVSUXEI8_V_M2_M4 = 10601,
10626 PseudoVSUXEI8_V_M2_M4_MASK = 10602,
10627 PseudoVSUXEI8_V_M2_M8 = 10603,
10628 PseudoVSUXEI8_V_M2_M8_MASK = 10604,
10629 PseudoVSUXEI8_V_M4_M4 = 10605,
10630 PseudoVSUXEI8_V_M4_M4_MASK = 10606,
10631 PseudoVSUXEI8_V_M4_M8 = 10607,
10632 PseudoVSUXEI8_V_M4_M8_MASK = 10608,
10633 PseudoVSUXEI8_V_M8_M8 = 10609,
10634 PseudoVSUXEI8_V_M8_M8_MASK = 10610,
10635 PseudoVSUXEI8_V_MF2_M1 = 10611,
10636 PseudoVSUXEI8_V_MF2_M1_MASK = 10612,
10637 PseudoVSUXEI8_V_MF2_M2 = 10613,
10638 PseudoVSUXEI8_V_MF2_M2_MASK = 10614,
10639 PseudoVSUXEI8_V_MF2_M4 = 10615,
10640 PseudoVSUXEI8_V_MF2_M4_MASK = 10616,
10641 PseudoVSUXEI8_V_MF2_MF2 = 10617,
10642 PseudoVSUXEI8_V_MF2_MF2_MASK = 10618,
10643 PseudoVSUXEI8_V_MF4_M1 = 10619,
10644 PseudoVSUXEI8_V_MF4_M1_MASK = 10620,
10645 PseudoVSUXEI8_V_MF4_M2 = 10621,
10646 PseudoVSUXEI8_V_MF4_M2_MASK = 10622,
10647 PseudoVSUXEI8_V_MF4_MF2 = 10623,
10648 PseudoVSUXEI8_V_MF4_MF2_MASK = 10624,
10649 PseudoVSUXEI8_V_MF4_MF4 = 10625,
10650 PseudoVSUXEI8_V_MF4_MF4_MASK = 10626,
10651 PseudoVSUXEI8_V_MF8_M1 = 10627,
10652 PseudoVSUXEI8_V_MF8_M1_MASK = 10628,
10653 PseudoVSUXEI8_V_MF8_MF2 = 10629,
10654 PseudoVSUXEI8_V_MF8_MF2_MASK = 10630,
10655 PseudoVSUXEI8_V_MF8_MF4 = 10631,
10656 PseudoVSUXEI8_V_MF8_MF4_MASK = 10632,
10657 PseudoVSUXEI8_V_MF8_MF8 = 10633,
10658 PseudoVSUXEI8_V_MF8_MF8_MASK = 10634,
10659 PseudoVSUXSEG2EI16_V_M1_M1 = 10635,
10660 PseudoVSUXSEG2EI16_V_M1_M1_MASK = 10636,
10661 PseudoVSUXSEG2EI16_V_M1_M2 = 10637,
10662 PseudoVSUXSEG2EI16_V_M1_M2_MASK = 10638,
10663 PseudoVSUXSEG2EI16_V_M1_M4 = 10639,
10664 PseudoVSUXSEG2EI16_V_M1_M4_MASK = 10640,
10665 PseudoVSUXSEG2EI16_V_M1_MF2 = 10641,
10666 PseudoVSUXSEG2EI16_V_M1_MF2_MASK = 10642,
10667 PseudoVSUXSEG2EI16_V_M2_M1 = 10643,
10668 PseudoVSUXSEG2EI16_V_M2_M1_MASK = 10644,
10669 PseudoVSUXSEG2EI16_V_M2_M2 = 10645,
10670 PseudoVSUXSEG2EI16_V_M2_M2_MASK = 10646,
10671 PseudoVSUXSEG2EI16_V_M2_M4 = 10647,
10672 PseudoVSUXSEG2EI16_V_M2_M4_MASK = 10648,
10673 PseudoVSUXSEG2EI16_V_M4_M2 = 10649,
10674 PseudoVSUXSEG2EI16_V_M4_M2_MASK = 10650,
10675 PseudoVSUXSEG2EI16_V_M4_M4 = 10651,
10676 PseudoVSUXSEG2EI16_V_M4_M4_MASK = 10652,
10677 PseudoVSUXSEG2EI16_V_M8_M4 = 10653,
10678 PseudoVSUXSEG2EI16_V_M8_M4_MASK = 10654,
10679 PseudoVSUXSEG2EI16_V_MF2_M1 = 10655,
10680 PseudoVSUXSEG2EI16_V_MF2_M1_MASK = 10656,
10681 PseudoVSUXSEG2EI16_V_MF2_M2 = 10657,
10682 PseudoVSUXSEG2EI16_V_MF2_M2_MASK = 10658,
10683 PseudoVSUXSEG2EI16_V_MF2_MF2 = 10659,
10684 PseudoVSUXSEG2EI16_V_MF2_MF2_MASK = 10660,
10685 PseudoVSUXSEG2EI16_V_MF2_MF4 = 10661,
10686 PseudoVSUXSEG2EI16_V_MF2_MF4_MASK = 10662,
10687 PseudoVSUXSEG2EI16_V_MF4_M1 = 10663,
10688 PseudoVSUXSEG2EI16_V_MF4_M1_MASK = 10664,
10689 PseudoVSUXSEG2EI16_V_MF4_MF2 = 10665,
10690 PseudoVSUXSEG2EI16_V_MF4_MF2_MASK = 10666,
10691 PseudoVSUXSEG2EI16_V_MF4_MF4 = 10667,
10692 PseudoVSUXSEG2EI16_V_MF4_MF4_MASK = 10668,
10693 PseudoVSUXSEG2EI16_V_MF4_MF8 = 10669,
10694 PseudoVSUXSEG2EI16_V_MF4_MF8_MASK = 10670,
10695 PseudoVSUXSEG2EI32_V_M1_M1 = 10671,
10696 PseudoVSUXSEG2EI32_V_M1_M1_MASK = 10672,
10697 PseudoVSUXSEG2EI32_V_M1_M2 = 10673,
10698 PseudoVSUXSEG2EI32_V_M1_M2_MASK = 10674,
10699 PseudoVSUXSEG2EI32_V_M1_MF2 = 10675,
10700 PseudoVSUXSEG2EI32_V_M1_MF2_MASK = 10676,
10701 PseudoVSUXSEG2EI32_V_M1_MF4 = 10677,
10702 PseudoVSUXSEG2EI32_V_M1_MF4_MASK = 10678,
10703 PseudoVSUXSEG2EI32_V_M2_M1 = 10679,
10704 PseudoVSUXSEG2EI32_V_M2_M1_MASK = 10680,
10705 PseudoVSUXSEG2EI32_V_M2_M2 = 10681,
10706 PseudoVSUXSEG2EI32_V_M2_M2_MASK = 10682,
10707 PseudoVSUXSEG2EI32_V_M2_M4 = 10683,
10708 PseudoVSUXSEG2EI32_V_M2_M4_MASK = 10684,
10709 PseudoVSUXSEG2EI32_V_M2_MF2 = 10685,
10710 PseudoVSUXSEG2EI32_V_M2_MF2_MASK = 10686,
10711 PseudoVSUXSEG2EI32_V_M4_M1 = 10687,
10712 PseudoVSUXSEG2EI32_V_M4_M1_MASK = 10688,
10713 PseudoVSUXSEG2EI32_V_M4_M2 = 10689,
10714 PseudoVSUXSEG2EI32_V_M4_M2_MASK = 10690,
10715 PseudoVSUXSEG2EI32_V_M4_M4 = 10691,
10716 PseudoVSUXSEG2EI32_V_M4_M4_MASK = 10692,
10717 PseudoVSUXSEG2EI32_V_M8_M2 = 10693,
10718 PseudoVSUXSEG2EI32_V_M8_M2_MASK = 10694,
10719 PseudoVSUXSEG2EI32_V_M8_M4 = 10695,
10720 PseudoVSUXSEG2EI32_V_M8_M4_MASK = 10696,
10721 PseudoVSUXSEG2EI32_V_MF2_M1 = 10697,
10722 PseudoVSUXSEG2EI32_V_MF2_M1_MASK = 10698,
10723 PseudoVSUXSEG2EI32_V_MF2_MF2 = 10699,
10724 PseudoVSUXSEG2EI32_V_MF2_MF2_MASK = 10700,
10725 PseudoVSUXSEG2EI32_V_MF2_MF4 = 10701,
10726 PseudoVSUXSEG2EI32_V_MF2_MF4_MASK = 10702,
10727 PseudoVSUXSEG2EI32_V_MF2_MF8 = 10703,
10728 PseudoVSUXSEG2EI32_V_MF2_MF8_MASK = 10704,
10729 PseudoVSUXSEG2EI64_V_M1_M1 = 10705,
10730 PseudoVSUXSEG2EI64_V_M1_M1_MASK = 10706,
10731 PseudoVSUXSEG2EI64_V_M1_MF2 = 10707,
10732 PseudoVSUXSEG2EI64_V_M1_MF2_MASK = 10708,
10733 PseudoVSUXSEG2EI64_V_M1_MF4 = 10709,
10734 PseudoVSUXSEG2EI64_V_M1_MF4_MASK = 10710,
10735 PseudoVSUXSEG2EI64_V_M1_MF8 = 10711,
10736 PseudoVSUXSEG2EI64_V_M1_MF8_MASK = 10712,
10737 PseudoVSUXSEG2EI64_V_M2_M1 = 10713,
10738 PseudoVSUXSEG2EI64_V_M2_M1_MASK = 10714,
10739 PseudoVSUXSEG2EI64_V_M2_M2 = 10715,
10740 PseudoVSUXSEG2EI64_V_M2_M2_MASK = 10716,
10741 PseudoVSUXSEG2EI64_V_M2_MF2 = 10717,
10742 PseudoVSUXSEG2EI64_V_M2_MF2_MASK = 10718,
10743 PseudoVSUXSEG2EI64_V_M2_MF4 = 10719,
10744 PseudoVSUXSEG2EI64_V_M2_MF4_MASK = 10720,
10745 PseudoVSUXSEG2EI64_V_M4_M1 = 10721,
10746 PseudoVSUXSEG2EI64_V_M4_M1_MASK = 10722,
10747 PseudoVSUXSEG2EI64_V_M4_M2 = 10723,
10748 PseudoVSUXSEG2EI64_V_M4_M2_MASK = 10724,
10749 PseudoVSUXSEG2EI64_V_M4_M4 = 10725,
10750 PseudoVSUXSEG2EI64_V_M4_M4_MASK = 10726,
10751 PseudoVSUXSEG2EI64_V_M4_MF2 = 10727,
10752 PseudoVSUXSEG2EI64_V_M4_MF2_MASK = 10728,
10753 PseudoVSUXSEG2EI64_V_M8_M1 = 10729,
10754 PseudoVSUXSEG2EI64_V_M8_M1_MASK = 10730,
10755 PseudoVSUXSEG2EI64_V_M8_M2 = 10731,
10756 PseudoVSUXSEG2EI64_V_M8_M2_MASK = 10732,
10757 PseudoVSUXSEG2EI64_V_M8_M4 = 10733,
10758 PseudoVSUXSEG2EI64_V_M8_M4_MASK = 10734,
10759 PseudoVSUXSEG2EI8_V_M1_M1 = 10735,
10760 PseudoVSUXSEG2EI8_V_M1_M1_MASK = 10736,
10761 PseudoVSUXSEG2EI8_V_M1_M2 = 10737,
10762 PseudoVSUXSEG2EI8_V_M1_M2_MASK = 10738,
10763 PseudoVSUXSEG2EI8_V_M1_M4 = 10739,
10764 PseudoVSUXSEG2EI8_V_M1_M4_MASK = 10740,
10765 PseudoVSUXSEG2EI8_V_M2_M2 = 10741,
10766 PseudoVSUXSEG2EI8_V_M2_M2_MASK = 10742,
10767 PseudoVSUXSEG2EI8_V_M2_M4 = 10743,
10768 PseudoVSUXSEG2EI8_V_M2_M4_MASK = 10744,
10769 PseudoVSUXSEG2EI8_V_M4_M4 = 10745,
10770 PseudoVSUXSEG2EI8_V_M4_M4_MASK = 10746,
10771 PseudoVSUXSEG2EI8_V_MF2_M1 = 10747,
10772 PseudoVSUXSEG2EI8_V_MF2_M1_MASK = 10748,
10773 PseudoVSUXSEG2EI8_V_MF2_M2 = 10749,
10774 PseudoVSUXSEG2EI8_V_MF2_M2_MASK = 10750,
10775 PseudoVSUXSEG2EI8_V_MF2_M4 = 10751,
10776 PseudoVSUXSEG2EI8_V_MF2_M4_MASK = 10752,
10777 PseudoVSUXSEG2EI8_V_MF2_MF2 = 10753,
10778 PseudoVSUXSEG2EI8_V_MF2_MF2_MASK = 10754,
10779 PseudoVSUXSEG2EI8_V_MF4_M1 = 10755,
10780 PseudoVSUXSEG2EI8_V_MF4_M1_MASK = 10756,
10781 PseudoVSUXSEG2EI8_V_MF4_M2 = 10757,
10782 PseudoVSUXSEG2EI8_V_MF4_M2_MASK = 10758,
10783 PseudoVSUXSEG2EI8_V_MF4_MF2 = 10759,
10784 PseudoVSUXSEG2EI8_V_MF4_MF2_MASK = 10760,
10785 PseudoVSUXSEG2EI8_V_MF4_MF4 = 10761,
10786 PseudoVSUXSEG2EI8_V_MF4_MF4_MASK = 10762,
10787 PseudoVSUXSEG2EI8_V_MF8_M1 = 10763,
10788 PseudoVSUXSEG2EI8_V_MF8_M1_MASK = 10764,
10789 PseudoVSUXSEG2EI8_V_MF8_MF2 = 10765,
10790 PseudoVSUXSEG2EI8_V_MF8_MF2_MASK = 10766,
10791 PseudoVSUXSEG2EI8_V_MF8_MF4 = 10767,
10792 PseudoVSUXSEG2EI8_V_MF8_MF4_MASK = 10768,
10793 PseudoVSUXSEG2EI8_V_MF8_MF8 = 10769,
10794 PseudoVSUXSEG2EI8_V_MF8_MF8_MASK = 10770,
10795 PseudoVSUXSEG3EI16_V_M1_M1 = 10771,
10796 PseudoVSUXSEG3EI16_V_M1_M1_MASK = 10772,
10797 PseudoVSUXSEG3EI16_V_M1_M2 = 10773,
10798 PseudoVSUXSEG3EI16_V_M1_M2_MASK = 10774,
10799 PseudoVSUXSEG3EI16_V_M1_MF2 = 10775,
10800 PseudoVSUXSEG3EI16_V_M1_MF2_MASK = 10776,
10801 PseudoVSUXSEG3EI16_V_M2_M1 = 10777,
10802 PseudoVSUXSEG3EI16_V_M2_M1_MASK = 10778,
10803 PseudoVSUXSEG3EI16_V_M2_M2 = 10779,
10804 PseudoVSUXSEG3EI16_V_M2_M2_MASK = 10780,
10805 PseudoVSUXSEG3EI16_V_M4_M2 = 10781,
10806 PseudoVSUXSEG3EI16_V_M4_M2_MASK = 10782,
10807 PseudoVSUXSEG3EI16_V_MF2_M1 = 10783,
10808 PseudoVSUXSEG3EI16_V_MF2_M1_MASK = 10784,
10809 PseudoVSUXSEG3EI16_V_MF2_M2 = 10785,
10810 PseudoVSUXSEG3EI16_V_MF2_M2_MASK = 10786,
10811 PseudoVSUXSEG3EI16_V_MF2_MF2 = 10787,
10812 PseudoVSUXSEG3EI16_V_MF2_MF2_MASK = 10788,
10813 PseudoVSUXSEG3EI16_V_MF2_MF4 = 10789,
10814 PseudoVSUXSEG3EI16_V_MF2_MF4_MASK = 10790,
10815 PseudoVSUXSEG3EI16_V_MF4_M1 = 10791,
10816 PseudoVSUXSEG3EI16_V_MF4_M1_MASK = 10792,
10817 PseudoVSUXSEG3EI16_V_MF4_MF2 = 10793,
10818 PseudoVSUXSEG3EI16_V_MF4_MF2_MASK = 10794,
10819 PseudoVSUXSEG3EI16_V_MF4_MF4 = 10795,
10820 PseudoVSUXSEG3EI16_V_MF4_MF4_MASK = 10796,
10821 PseudoVSUXSEG3EI16_V_MF4_MF8 = 10797,
10822 PseudoVSUXSEG3EI16_V_MF4_MF8_MASK = 10798,
10823 PseudoVSUXSEG3EI32_V_M1_M1 = 10799,
10824 PseudoVSUXSEG3EI32_V_M1_M1_MASK = 10800,
10825 PseudoVSUXSEG3EI32_V_M1_M2 = 10801,
10826 PseudoVSUXSEG3EI32_V_M1_M2_MASK = 10802,
10827 PseudoVSUXSEG3EI32_V_M1_MF2 = 10803,
10828 PseudoVSUXSEG3EI32_V_M1_MF2_MASK = 10804,
10829 PseudoVSUXSEG3EI32_V_M1_MF4 = 10805,
10830 PseudoVSUXSEG3EI32_V_M1_MF4_MASK = 10806,
10831 PseudoVSUXSEG3EI32_V_M2_M1 = 10807,
10832 PseudoVSUXSEG3EI32_V_M2_M1_MASK = 10808,
10833 PseudoVSUXSEG3EI32_V_M2_M2 = 10809,
10834 PseudoVSUXSEG3EI32_V_M2_M2_MASK = 10810,
10835 PseudoVSUXSEG3EI32_V_M2_MF2 = 10811,
10836 PseudoVSUXSEG3EI32_V_M2_MF2_MASK = 10812,
10837 PseudoVSUXSEG3EI32_V_M4_M1 = 10813,
10838 PseudoVSUXSEG3EI32_V_M4_M1_MASK = 10814,
10839 PseudoVSUXSEG3EI32_V_M4_M2 = 10815,
10840 PseudoVSUXSEG3EI32_V_M4_M2_MASK = 10816,
10841 PseudoVSUXSEG3EI32_V_M8_M2 = 10817,
10842 PseudoVSUXSEG3EI32_V_M8_M2_MASK = 10818,
10843 PseudoVSUXSEG3EI32_V_MF2_M1 = 10819,
10844 PseudoVSUXSEG3EI32_V_MF2_M1_MASK = 10820,
10845 PseudoVSUXSEG3EI32_V_MF2_MF2 = 10821,
10846 PseudoVSUXSEG3EI32_V_MF2_MF2_MASK = 10822,
10847 PseudoVSUXSEG3EI32_V_MF2_MF4 = 10823,
10848 PseudoVSUXSEG3EI32_V_MF2_MF4_MASK = 10824,
10849 PseudoVSUXSEG3EI32_V_MF2_MF8 = 10825,
10850 PseudoVSUXSEG3EI32_V_MF2_MF8_MASK = 10826,
10851 PseudoVSUXSEG3EI64_V_M1_M1 = 10827,
10852 PseudoVSUXSEG3EI64_V_M1_M1_MASK = 10828,
10853 PseudoVSUXSEG3EI64_V_M1_MF2 = 10829,
10854 PseudoVSUXSEG3EI64_V_M1_MF2_MASK = 10830,
10855 PseudoVSUXSEG3EI64_V_M1_MF4 = 10831,
10856 PseudoVSUXSEG3EI64_V_M1_MF4_MASK = 10832,
10857 PseudoVSUXSEG3EI64_V_M1_MF8 = 10833,
10858 PseudoVSUXSEG3EI64_V_M1_MF8_MASK = 10834,
10859 PseudoVSUXSEG3EI64_V_M2_M1 = 10835,
10860 PseudoVSUXSEG3EI64_V_M2_M1_MASK = 10836,
10861 PseudoVSUXSEG3EI64_V_M2_M2 = 10837,
10862 PseudoVSUXSEG3EI64_V_M2_M2_MASK = 10838,
10863 PseudoVSUXSEG3EI64_V_M2_MF2 = 10839,
10864 PseudoVSUXSEG3EI64_V_M2_MF2_MASK = 10840,
10865 PseudoVSUXSEG3EI64_V_M2_MF4 = 10841,
10866 PseudoVSUXSEG3EI64_V_M2_MF4_MASK = 10842,
10867 PseudoVSUXSEG3EI64_V_M4_M1 = 10843,
10868 PseudoVSUXSEG3EI64_V_M4_M1_MASK = 10844,
10869 PseudoVSUXSEG3EI64_V_M4_M2 = 10845,
10870 PseudoVSUXSEG3EI64_V_M4_M2_MASK = 10846,
10871 PseudoVSUXSEG3EI64_V_M4_MF2 = 10847,
10872 PseudoVSUXSEG3EI64_V_M4_MF2_MASK = 10848,
10873 PseudoVSUXSEG3EI64_V_M8_M1 = 10849,
10874 PseudoVSUXSEG3EI64_V_M8_M1_MASK = 10850,
10875 PseudoVSUXSEG3EI64_V_M8_M2 = 10851,
10876 PseudoVSUXSEG3EI64_V_M8_M2_MASK = 10852,
10877 PseudoVSUXSEG3EI8_V_M1_M1 = 10853,
10878 PseudoVSUXSEG3EI8_V_M1_M1_MASK = 10854,
10879 PseudoVSUXSEG3EI8_V_M1_M2 = 10855,
10880 PseudoVSUXSEG3EI8_V_M1_M2_MASK = 10856,
10881 PseudoVSUXSEG3EI8_V_M2_M2 = 10857,
10882 PseudoVSUXSEG3EI8_V_M2_M2_MASK = 10858,
10883 PseudoVSUXSEG3EI8_V_MF2_M1 = 10859,
10884 PseudoVSUXSEG3EI8_V_MF2_M1_MASK = 10860,
10885 PseudoVSUXSEG3EI8_V_MF2_M2 = 10861,
10886 PseudoVSUXSEG3EI8_V_MF2_M2_MASK = 10862,
10887 PseudoVSUXSEG3EI8_V_MF2_MF2 = 10863,
10888 PseudoVSUXSEG3EI8_V_MF2_MF2_MASK = 10864,
10889 PseudoVSUXSEG3EI8_V_MF4_M1 = 10865,
10890 PseudoVSUXSEG3EI8_V_MF4_M1_MASK = 10866,
10891 PseudoVSUXSEG3EI8_V_MF4_M2 = 10867,
10892 PseudoVSUXSEG3EI8_V_MF4_M2_MASK = 10868,
10893 PseudoVSUXSEG3EI8_V_MF4_MF2 = 10869,
10894 PseudoVSUXSEG3EI8_V_MF4_MF2_MASK = 10870,
10895 PseudoVSUXSEG3EI8_V_MF4_MF4 = 10871,
10896 PseudoVSUXSEG3EI8_V_MF4_MF4_MASK = 10872,
10897 PseudoVSUXSEG3EI8_V_MF8_M1 = 10873,
10898 PseudoVSUXSEG3EI8_V_MF8_M1_MASK = 10874,
10899 PseudoVSUXSEG3EI8_V_MF8_MF2 = 10875,
10900 PseudoVSUXSEG3EI8_V_MF8_MF2_MASK = 10876,
10901 PseudoVSUXSEG3EI8_V_MF8_MF4 = 10877,
10902 PseudoVSUXSEG3EI8_V_MF8_MF4_MASK = 10878,
10903 PseudoVSUXSEG3EI8_V_MF8_MF8 = 10879,
10904 PseudoVSUXSEG3EI8_V_MF8_MF8_MASK = 10880,
10905 PseudoVSUXSEG4EI16_V_M1_M1 = 10881,
10906 PseudoVSUXSEG4EI16_V_M1_M1_MASK = 10882,
10907 PseudoVSUXSEG4EI16_V_M1_M2 = 10883,
10908 PseudoVSUXSEG4EI16_V_M1_M2_MASK = 10884,
10909 PseudoVSUXSEG4EI16_V_M1_MF2 = 10885,
10910 PseudoVSUXSEG4EI16_V_M1_MF2_MASK = 10886,
10911 PseudoVSUXSEG4EI16_V_M2_M1 = 10887,
10912 PseudoVSUXSEG4EI16_V_M2_M1_MASK = 10888,
10913 PseudoVSUXSEG4EI16_V_M2_M2 = 10889,
10914 PseudoVSUXSEG4EI16_V_M2_M2_MASK = 10890,
10915 PseudoVSUXSEG4EI16_V_M4_M2 = 10891,
10916 PseudoVSUXSEG4EI16_V_M4_M2_MASK = 10892,
10917 PseudoVSUXSEG4EI16_V_MF2_M1 = 10893,
10918 PseudoVSUXSEG4EI16_V_MF2_M1_MASK = 10894,
10919 PseudoVSUXSEG4EI16_V_MF2_M2 = 10895,
10920 PseudoVSUXSEG4EI16_V_MF2_M2_MASK = 10896,
10921 PseudoVSUXSEG4EI16_V_MF2_MF2 = 10897,
10922 PseudoVSUXSEG4EI16_V_MF2_MF2_MASK = 10898,
10923 PseudoVSUXSEG4EI16_V_MF2_MF4 = 10899,
10924 PseudoVSUXSEG4EI16_V_MF2_MF4_MASK = 10900,
10925 PseudoVSUXSEG4EI16_V_MF4_M1 = 10901,
10926 PseudoVSUXSEG4EI16_V_MF4_M1_MASK = 10902,
10927 PseudoVSUXSEG4EI16_V_MF4_MF2 = 10903,
10928 PseudoVSUXSEG4EI16_V_MF4_MF2_MASK = 10904,
10929 PseudoVSUXSEG4EI16_V_MF4_MF4 = 10905,
10930 PseudoVSUXSEG4EI16_V_MF4_MF4_MASK = 10906,
10931 PseudoVSUXSEG4EI16_V_MF4_MF8 = 10907,
10932 PseudoVSUXSEG4EI16_V_MF4_MF8_MASK = 10908,
10933 PseudoVSUXSEG4EI32_V_M1_M1 = 10909,
10934 PseudoVSUXSEG4EI32_V_M1_M1_MASK = 10910,
10935 PseudoVSUXSEG4EI32_V_M1_M2 = 10911,
10936 PseudoVSUXSEG4EI32_V_M1_M2_MASK = 10912,
10937 PseudoVSUXSEG4EI32_V_M1_MF2 = 10913,
10938 PseudoVSUXSEG4EI32_V_M1_MF2_MASK = 10914,
10939 PseudoVSUXSEG4EI32_V_M1_MF4 = 10915,
10940 PseudoVSUXSEG4EI32_V_M1_MF4_MASK = 10916,
10941 PseudoVSUXSEG4EI32_V_M2_M1 = 10917,
10942 PseudoVSUXSEG4EI32_V_M2_M1_MASK = 10918,
10943 PseudoVSUXSEG4EI32_V_M2_M2 = 10919,
10944 PseudoVSUXSEG4EI32_V_M2_M2_MASK = 10920,
10945 PseudoVSUXSEG4EI32_V_M2_MF2 = 10921,
10946 PseudoVSUXSEG4EI32_V_M2_MF2_MASK = 10922,
10947 PseudoVSUXSEG4EI32_V_M4_M1 = 10923,
10948 PseudoVSUXSEG4EI32_V_M4_M1_MASK = 10924,
10949 PseudoVSUXSEG4EI32_V_M4_M2 = 10925,
10950 PseudoVSUXSEG4EI32_V_M4_M2_MASK = 10926,
10951 PseudoVSUXSEG4EI32_V_M8_M2 = 10927,
10952 PseudoVSUXSEG4EI32_V_M8_M2_MASK = 10928,
10953 PseudoVSUXSEG4EI32_V_MF2_M1 = 10929,
10954 PseudoVSUXSEG4EI32_V_MF2_M1_MASK = 10930,
10955 PseudoVSUXSEG4EI32_V_MF2_MF2 = 10931,
10956 PseudoVSUXSEG4EI32_V_MF2_MF2_MASK = 10932,
10957 PseudoVSUXSEG4EI32_V_MF2_MF4 = 10933,
10958 PseudoVSUXSEG4EI32_V_MF2_MF4_MASK = 10934,
10959 PseudoVSUXSEG4EI32_V_MF2_MF8 = 10935,
10960 PseudoVSUXSEG4EI32_V_MF2_MF8_MASK = 10936,
10961 PseudoVSUXSEG4EI64_V_M1_M1 = 10937,
10962 PseudoVSUXSEG4EI64_V_M1_M1_MASK = 10938,
10963 PseudoVSUXSEG4EI64_V_M1_MF2 = 10939,
10964 PseudoVSUXSEG4EI64_V_M1_MF2_MASK = 10940,
10965 PseudoVSUXSEG4EI64_V_M1_MF4 = 10941,
10966 PseudoVSUXSEG4EI64_V_M1_MF4_MASK = 10942,
10967 PseudoVSUXSEG4EI64_V_M1_MF8 = 10943,
10968 PseudoVSUXSEG4EI64_V_M1_MF8_MASK = 10944,
10969 PseudoVSUXSEG4EI64_V_M2_M1 = 10945,
10970 PseudoVSUXSEG4EI64_V_M2_M1_MASK = 10946,
10971 PseudoVSUXSEG4EI64_V_M2_M2 = 10947,
10972 PseudoVSUXSEG4EI64_V_M2_M2_MASK = 10948,
10973 PseudoVSUXSEG4EI64_V_M2_MF2 = 10949,
10974 PseudoVSUXSEG4EI64_V_M2_MF2_MASK = 10950,
10975 PseudoVSUXSEG4EI64_V_M2_MF4 = 10951,
10976 PseudoVSUXSEG4EI64_V_M2_MF4_MASK = 10952,
10977 PseudoVSUXSEG4EI64_V_M4_M1 = 10953,
10978 PseudoVSUXSEG4EI64_V_M4_M1_MASK = 10954,
10979 PseudoVSUXSEG4EI64_V_M4_M2 = 10955,
10980 PseudoVSUXSEG4EI64_V_M4_M2_MASK = 10956,
10981 PseudoVSUXSEG4EI64_V_M4_MF2 = 10957,
10982 PseudoVSUXSEG4EI64_V_M4_MF2_MASK = 10958,
10983 PseudoVSUXSEG4EI64_V_M8_M1 = 10959,
10984 PseudoVSUXSEG4EI64_V_M8_M1_MASK = 10960,
10985 PseudoVSUXSEG4EI64_V_M8_M2 = 10961,
10986 PseudoVSUXSEG4EI64_V_M8_M2_MASK = 10962,
10987 PseudoVSUXSEG4EI8_V_M1_M1 = 10963,
10988 PseudoVSUXSEG4EI8_V_M1_M1_MASK = 10964,
10989 PseudoVSUXSEG4EI8_V_M1_M2 = 10965,
10990 PseudoVSUXSEG4EI8_V_M1_M2_MASK = 10966,
10991 PseudoVSUXSEG4EI8_V_M2_M2 = 10967,
10992 PseudoVSUXSEG4EI8_V_M2_M2_MASK = 10968,
10993 PseudoVSUXSEG4EI8_V_MF2_M1 = 10969,
10994 PseudoVSUXSEG4EI8_V_MF2_M1_MASK = 10970,
10995 PseudoVSUXSEG4EI8_V_MF2_M2 = 10971,
10996 PseudoVSUXSEG4EI8_V_MF2_M2_MASK = 10972,
10997 PseudoVSUXSEG4EI8_V_MF2_MF2 = 10973,
10998 PseudoVSUXSEG4EI8_V_MF2_MF2_MASK = 10974,
10999 PseudoVSUXSEG4EI8_V_MF4_M1 = 10975,
11000 PseudoVSUXSEG4EI8_V_MF4_M1_MASK = 10976,
11001 PseudoVSUXSEG4EI8_V_MF4_M2 = 10977,
11002 PseudoVSUXSEG4EI8_V_MF4_M2_MASK = 10978,
11003 PseudoVSUXSEG4EI8_V_MF4_MF2 = 10979,
11004 PseudoVSUXSEG4EI8_V_MF4_MF2_MASK = 10980,
11005 PseudoVSUXSEG4EI8_V_MF4_MF4 = 10981,
11006 PseudoVSUXSEG4EI8_V_MF4_MF4_MASK = 10982,
11007 PseudoVSUXSEG4EI8_V_MF8_M1 = 10983,
11008 PseudoVSUXSEG4EI8_V_MF8_M1_MASK = 10984,
11009 PseudoVSUXSEG4EI8_V_MF8_MF2 = 10985,
11010 PseudoVSUXSEG4EI8_V_MF8_MF2_MASK = 10986,
11011 PseudoVSUXSEG4EI8_V_MF8_MF4 = 10987,
11012 PseudoVSUXSEG4EI8_V_MF8_MF4_MASK = 10988,
11013 PseudoVSUXSEG4EI8_V_MF8_MF8 = 10989,
11014 PseudoVSUXSEG4EI8_V_MF8_MF8_MASK = 10990,
11015 PseudoVSUXSEG5EI16_V_M1_M1 = 10991,
11016 PseudoVSUXSEG5EI16_V_M1_M1_MASK = 10992,
11017 PseudoVSUXSEG5EI16_V_M1_MF2 = 10993,
11018 PseudoVSUXSEG5EI16_V_M1_MF2_MASK = 10994,
11019 PseudoVSUXSEG5EI16_V_M2_M1 = 10995,
11020 PseudoVSUXSEG5EI16_V_M2_M1_MASK = 10996,
11021 PseudoVSUXSEG5EI16_V_MF2_M1 = 10997,
11022 PseudoVSUXSEG5EI16_V_MF2_M1_MASK = 10998,
11023 PseudoVSUXSEG5EI16_V_MF2_MF2 = 10999,
11024 PseudoVSUXSEG5EI16_V_MF2_MF2_MASK = 11000,
11025 PseudoVSUXSEG5EI16_V_MF2_MF4 = 11001,
11026 PseudoVSUXSEG5EI16_V_MF2_MF4_MASK = 11002,
11027 PseudoVSUXSEG5EI16_V_MF4_M1 = 11003,
11028 PseudoVSUXSEG5EI16_V_MF4_M1_MASK = 11004,
11029 PseudoVSUXSEG5EI16_V_MF4_MF2 = 11005,
11030 PseudoVSUXSEG5EI16_V_MF4_MF2_MASK = 11006,
11031 PseudoVSUXSEG5EI16_V_MF4_MF4 = 11007,
11032 PseudoVSUXSEG5EI16_V_MF4_MF4_MASK = 11008,
11033 PseudoVSUXSEG5EI16_V_MF4_MF8 = 11009,
11034 PseudoVSUXSEG5EI16_V_MF4_MF8_MASK = 11010,
11035 PseudoVSUXSEG5EI32_V_M1_M1 = 11011,
11036 PseudoVSUXSEG5EI32_V_M1_M1_MASK = 11012,
11037 PseudoVSUXSEG5EI32_V_M1_MF2 = 11013,
11038 PseudoVSUXSEG5EI32_V_M1_MF2_MASK = 11014,
11039 PseudoVSUXSEG5EI32_V_M1_MF4 = 11015,
11040 PseudoVSUXSEG5EI32_V_M1_MF4_MASK = 11016,
11041 PseudoVSUXSEG5EI32_V_M2_M1 = 11017,
11042 PseudoVSUXSEG5EI32_V_M2_M1_MASK = 11018,
11043 PseudoVSUXSEG5EI32_V_M2_MF2 = 11019,
11044 PseudoVSUXSEG5EI32_V_M2_MF2_MASK = 11020,
11045 PseudoVSUXSEG5EI32_V_M4_M1 = 11021,
11046 PseudoVSUXSEG5EI32_V_M4_M1_MASK = 11022,
11047 PseudoVSUXSEG5EI32_V_MF2_M1 = 11023,
11048 PseudoVSUXSEG5EI32_V_MF2_M1_MASK = 11024,
11049 PseudoVSUXSEG5EI32_V_MF2_MF2 = 11025,
11050 PseudoVSUXSEG5EI32_V_MF2_MF2_MASK = 11026,
11051 PseudoVSUXSEG5EI32_V_MF2_MF4 = 11027,
11052 PseudoVSUXSEG5EI32_V_MF2_MF4_MASK = 11028,
11053 PseudoVSUXSEG5EI32_V_MF2_MF8 = 11029,
11054 PseudoVSUXSEG5EI32_V_MF2_MF8_MASK = 11030,
11055 PseudoVSUXSEG5EI64_V_M1_M1 = 11031,
11056 PseudoVSUXSEG5EI64_V_M1_M1_MASK = 11032,
11057 PseudoVSUXSEG5EI64_V_M1_MF2 = 11033,
11058 PseudoVSUXSEG5EI64_V_M1_MF2_MASK = 11034,
11059 PseudoVSUXSEG5EI64_V_M1_MF4 = 11035,
11060 PseudoVSUXSEG5EI64_V_M1_MF4_MASK = 11036,
11061 PseudoVSUXSEG5EI64_V_M1_MF8 = 11037,
11062 PseudoVSUXSEG5EI64_V_M1_MF8_MASK = 11038,
11063 PseudoVSUXSEG5EI64_V_M2_M1 = 11039,
11064 PseudoVSUXSEG5EI64_V_M2_M1_MASK = 11040,
11065 PseudoVSUXSEG5EI64_V_M2_MF2 = 11041,
11066 PseudoVSUXSEG5EI64_V_M2_MF2_MASK = 11042,
11067 PseudoVSUXSEG5EI64_V_M2_MF4 = 11043,
11068 PseudoVSUXSEG5EI64_V_M2_MF4_MASK = 11044,
11069 PseudoVSUXSEG5EI64_V_M4_M1 = 11045,
11070 PseudoVSUXSEG5EI64_V_M4_M1_MASK = 11046,
11071 PseudoVSUXSEG5EI64_V_M4_MF2 = 11047,
11072 PseudoVSUXSEG5EI64_V_M4_MF2_MASK = 11048,
11073 PseudoVSUXSEG5EI64_V_M8_M1 = 11049,
11074 PseudoVSUXSEG5EI64_V_M8_M1_MASK = 11050,
11075 PseudoVSUXSEG5EI8_V_M1_M1 = 11051,
11076 PseudoVSUXSEG5EI8_V_M1_M1_MASK = 11052,
11077 PseudoVSUXSEG5EI8_V_MF2_M1 = 11053,
11078 PseudoVSUXSEG5EI8_V_MF2_M1_MASK = 11054,
11079 PseudoVSUXSEG5EI8_V_MF2_MF2 = 11055,
11080 PseudoVSUXSEG5EI8_V_MF2_MF2_MASK = 11056,
11081 PseudoVSUXSEG5EI8_V_MF4_M1 = 11057,
11082 PseudoVSUXSEG5EI8_V_MF4_M1_MASK = 11058,
11083 PseudoVSUXSEG5EI8_V_MF4_MF2 = 11059,
11084 PseudoVSUXSEG5EI8_V_MF4_MF2_MASK = 11060,
11085 PseudoVSUXSEG5EI8_V_MF4_MF4 = 11061,
11086 PseudoVSUXSEG5EI8_V_MF4_MF4_MASK = 11062,
11087 PseudoVSUXSEG5EI8_V_MF8_M1 = 11063,
11088 PseudoVSUXSEG5EI8_V_MF8_M1_MASK = 11064,
11089 PseudoVSUXSEG5EI8_V_MF8_MF2 = 11065,
11090 PseudoVSUXSEG5EI8_V_MF8_MF2_MASK = 11066,
11091 PseudoVSUXSEG5EI8_V_MF8_MF4 = 11067,
11092 PseudoVSUXSEG5EI8_V_MF8_MF4_MASK = 11068,
11093 PseudoVSUXSEG5EI8_V_MF8_MF8 = 11069,
11094 PseudoVSUXSEG5EI8_V_MF8_MF8_MASK = 11070,
11095 PseudoVSUXSEG6EI16_V_M1_M1 = 11071,
11096 PseudoVSUXSEG6EI16_V_M1_M1_MASK = 11072,
11097 PseudoVSUXSEG6EI16_V_M1_MF2 = 11073,
11098 PseudoVSUXSEG6EI16_V_M1_MF2_MASK = 11074,
11099 PseudoVSUXSEG6EI16_V_M2_M1 = 11075,
11100 PseudoVSUXSEG6EI16_V_M2_M1_MASK = 11076,
11101 PseudoVSUXSEG6EI16_V_MF2_M1 = 11077,
11102 PseudoVSUXSEG6EI16_V_MF2_M1_MASK = 11078,
11103 PseudoVSUXSEG6EI16_V_MF2_MF2 = 11079,
11104 PseudoVSUXSEG6EI16_V_MF2_MF2_MASK = 11080,
11105 PseudoVSUXSEG6EI16_V_MF2_MF4 = 11081,
11106 PseudoVSUXSEG6EI16_V_MF2_MF4_MASK = 11082,
11107 PseudoVSUXSEG6EI16_V_MF4_M1 = 11083,
11108 PseudoVSUXSEG6EI16_V_MF4_M1_MASK = 11084,
11109 PseudoVSUXSEG6EI16_V_MF4_MF2 = 11085,
11110 PseudoVSUXSEG6EI16_V_MF4_MF2_MASK = 11086,
11111 PseudoVSUXSEG6EI16_V_MF4_MF4 = 11087,
11112 PseudoVSUXSEG6EI16_V_MF4_MF4_MASK = 11088,
11113 PseudoVSUXSEG6EI16_V_MF4_MF8 = 11089,
11114 PseudoVSUXSEG6EI16_V_MF4_MF8_MASK = 11090,
11115 PseudoVSUXSEG6EI32_V_M1_M1 = 11091,
11116 PseudoVSUXSEG6EI32_V_M1_M1_MASK = 11092,
11117 PseudoVSUXSEG6EI32_V_M1_MF2 = 11093,
11118 PseudoVSUXSEG6EI32_V_M1_MF2_MASK = 11094,
11119 PseudoVSUXSEG6EI32_V_M1_MF4 = 11095,
11120 PseudoVSUXSEG6EI32_V_M1_MF4_MASK = 11096,
11121 PseudoVSUXSEG6EI32_V_M2_M1 = 11097,
11122 PseudoVSUXSEG6EI32_V_M2_M1_MASK = 11098,
11123 PseudoVSUXSEG6EI32_V_M2_MF2 = 11099,
11124 PseudoVSUXSEG6EI32_V_M2_MF2_MASK = 11100,
11125 PseudoVSUXSEG6EI32_V_M4_M1 = 11101,
11126 PseudoVSUXSEG6EI32_V_M4_M1_MASK = 11102,
11127 PseudoVSUXSEG6EI32_V_MF2_M1 = 11103,
11128 PseudoVSUXSEG6EI32_V_MF2_M1_MASK = 11104,
11129 PseudoVSUXSEG6EI32_V_MF2_MF2 = 11105,
11130 PseudoVSUXSEG6EI32_V_MF2_MF2_MASK = 11106,
11131 PseudoVSUXSEG6EI32_V_MF2_MF4 = 11107,
11132 PseudoVSUXSEG6EI32_V_MF2_MF4_MASK = 11108,
11133 PseudoVSUXSEG6EI32_V_MF2_MF8 = 11109,
11134 PseudoVSUXSEG6EI32_V_MF2_MF8_MASK = 11110,
11135 PseudoVSUXSEG6EI64_V_M1_M1 = 11111,
11136 PseudoVSUXSEG6EI64_V_M1_M1_MASK = 11112,
11137 PseudoVSUXSEG6EI64_V_M1_MF2 = 11113,
11138 PseudoVSUXSEG6EI64_V_M1_MF2_MASK = 11114,
11139 PseudoVSUXSEG6EI64_V_M1_MF4 = 11115,
11140 PseudoVSUXSEG6EI64_V_M1_MF4_MASK = 11116,
11141 PseudoVSUXSEG6EI64_V_M1_MF8 = 11117,
11142 PseudoVSUXSEG6EI64_V_M1_MF8_MASK = 11118,
11143 PseudoVSUXSEG6EI64_V_M2_M1 = 11119,
11144 PseudoVSUXSEG6EI64_V_M2_M1_MASK = 11120,
11145 PseudoVSUXSEG6EI64_V_M2_MF2 = 11121,
11146 PseudoVSUXSEG6EI64_V_M2_MF2_MASK = 11122,
11147 PseudoVSUXSEG6EI64_V_M2_MF4 = 11123,
11148 PseudoVSUXSEG6EI64_V_M2_MF4_MASK = 11124,
11149 PseudoVSUXSEG6EI64_V_M4_M1 = 11125,
11150 PseudoVSUXSEG6EI64_V_M4_M1_MASK = 11126,
11151 PseudoVSUXSEG6EI64_V_M4_MF2 = 11127,
11152 PseudoVSUXSEG6EI64_V_M4_MF2_MASK = 11128,
11153 PseudoVSUXSEG6EI64_V_M8_M1 = 11129,
11154 PseudoVSUXSEG6EI64_V_M8_M1_MASK = 11130,
11155 PseudoVSUXSEG6EI8_V_M1_M1 = 11131,
11156 PseudoVSUXSEG6EI8_V_M1_M1_MASK = 11132,
11157 PseudoVSUXSEG6EI8_V_MF2_M1 = 11133,
11158 PseudoVSUXSEG6EI8_V_MF2_M1_MASK = 11134,
11159 PseudoVSUXSEG6EI8_V_MF2_MF2 = 11135,
11160 PseudoVSUXSEG6EI8_V_MF2_MF2_MASK = 11136,
11161 PseudoVSUXSEG6EI8_V_MF4_M1 = 11137,
11162 PseudoVSUXSEG6EI8_V_MF4_M1_MASK = 11138,
11163 PseudoVSUXSEG6EI8_V_MF4_MF2 = 11139,
11164 PseudoVSUXSEG6EI8_V_MF4_MF2_MASK = 11140,
11165 PseudoVSUXSEG6EI8_V_MF4_MF4 = 11141,
11166 PseudoVSUXSEG6EI8_V_MF4_MF4_MASK = 11142,
11167 PseudoVSUXSEG6EI8_V_MF8_M1 = 11143,
11168 PseudoVSUXSEG6EI8_V_MF8_M1_MASK = 11144,
11169 PseudoVSUXSEG6EI8_V_MF8_MF2 = 11145,
11170 PseudoVSUXSEG6EI8_V_MF8_MF2_MASK = 11146,
11171 PseudoVSUXSEG6EI8_V_MF8_MF4 = 11147,
11172 PseudoVSUXSEG6EI8_V_MF8_MF4_MASK = 11148,
11173 PseudoVSUXSEG6EI8_V_MF8_MF8 = 11149,
11174 PseudoVSUXSEG6EI8_V_MF8_MF8_MASK = 11150,
11175 PseudoVSUXSEG7EI16_V_M1_M1 = 11151,
11176 PseudoVSUXSEG7EI16_V_M1_M1_MASK = 11152,
11177 PseudoVSUXSEG7EI16_V_M1_MF2 = 11153,
11178 PseudoVSUXSEG7EI16_V_M1_MF2_MASK = 11154,
11179 PseudoVSUXSEG7EI16_V_M2_M1 = 11155,
11180 PseudoVSUXSEG7EI16_V_M2_M1_MASK = 11156,
11181 PseudoVSUXSEG7EI16_V_MF2_M1 = 11157,
11182 PseudoVSUXSEG7EI16_V_MF2_M1_MASK = 11158,
11183 PseudoVSUXSEG7EI16_V_MF2_MF2 = 11159,
11184 PseudoVSUXSEG7EI16_V_MF2_MF2_MASK = 11160,
11185 PseudoVSUXSEG7EI16_V_MF2_MF4 = 11161,
11186 PseudoVSUXSEG7EI16_V_MF2_MF4_MASK = 11162,
11187 PseudoVSUXSEG7EI16_V_MF4_M1 = 11163,
11188 PseudoVSUXSEG7EI16_V_MF4_M1_MASK = 11164,
11189 PseudoVSUXSEG7EI16_V_MF4_MF2 = 11165,
11190 PseudoVSUXSEG7EI16_V_MF4_MF2_MASK = 11166,
11191 PseudoVSUXSEG7EI16_V_MF4_MF4 = 11167,
11192 PseudoVSUXSEG7EI16_V_MF4_MF4_MASK = 11168,
11193 PseudoVSUXSEG7EI16_V_MF4_MF8 = 11169,
11194 PseudoVSUXSEG7EI16_V_MF4_MF8_MASK = 11170,
11195 PseudoVSUXSEG7EI32_V_M1_M1 = 11171,
11196 PseudoVSUXSEG7EI32_V_M1_M1_MASK = 11172,
11197 PseudoVSUXSEG7EI32_V_M1_MF2 = 11173,
11198 PseudoVSUXSEG7EI32_V_M1_MF2_MASK = 11174,
11199 PseudoVSUXSEG7EI32_V_M1_MF4 = 11175,
11200 PseudoVSUXSEG7EI32_V_M1_MF4_MASK = 11176,
11201 PseudoVSUXSEG7EI32_V_M2_M1 = 11177,
11202 PseudoVSUXSEG7EI32_V_M2_M1_MASK = 11178,
11203 PseudoVSUXSEG7EI32_V_M2_MF2 = 11179,
11204 PseudoVSUXSEG7EI32_V_M2_MF2_MASK = 11180,
11205 PseudoVSUXSEG7EI32_V_M4_M1 = 11181,
11206 PseudoVSUXSEG7EI32_V_M4_M1_MASK = 11182,
11207 PseudoVSUXSEG7EI32_V_MF2_M1 = 11183,
11208 PseudoVSUXSEG7EI32_V_MF2_M1_MASK = 11184,
11209 PseudoVSUXSEG7EI32_V_MF2_MF2 = 11185,
11210 PseudoVSUXSEG7EI32_V_MF2_MF2_MASK = 11186,
11211 PseudoVSUXSEG7EI32_V_MF2_MF4 = 11187,
11212 PseudoVSUXSEG7EI32_V_MF2_MF4_MASK = 11188,
11213 PseudoVSUXSEG7EI32_V_MF2_MF8 = 11189,
11214 PseudoVSUXSEG7EI32_V_MF2_MF8_MASK = 11190,
11215 PseudoVSUXSEG7EI64_V_M1_M1 = 11191,
11216 PseudoVSUXSEG7EI64_V_M1_M1_MASK = 11192,
11217 PseudoVSUXSEG7EI64_V_M1_MF2 = 11193,
11218 PseudoVSUXSEG7EI64_V_M1_MF2_MASK = 11194,
11219 PseudoVSUXSEG7EI64_V_M1_MF4 = 11195,
11220 PseudoVSUXSEG7EI64_V_M1_MF4_MASK = 11196,
11221 PseudoVSUXSEG7EI64_V_M1_MF8 = 11197,
11222 PseudoVSUXSEG7EI64_V_M1_MF8_MASK = 11198,
11223 PseudoVSUXSEG7EI64_V_M2_M1 = 11199,
11224 PseudoVSUXSEG7EI64_V_M2_M1_MASK = 11200,
11225 PseudoVSUXSEG7EI64_V_M2_MF2 = 11201,
11226 PseudoVSUXSEG7EI64_V_M2_MF2_MASK = 11202,
11227 PseudoVSUXSEG7EI64_V_M2_MF4 = 11203,
11228 PseudoVSUXSEG7EI64_V_M2_MF4_MASK = 11204,
11229 PseudoVSUXSEG7EI64_V_M4_M1 = 11205,
11230 PseudoVSUXSEG7EI64_V_M4_M1_MASK = 11206,
11231 PseudoVSUXSEG7EI64_V_M4_MF2 = 11207,
11232 PseudoVSUXSEG7EI64_V_M4_MF2_MASK = 11208,
11233 PseudoVSUXSEG7EI64_V_M8_M1 = 11209,
11234 PseudoVSUXSEG7EI64_V_M8_M1_MASK = 11210,
11235 PseudoVSUXSEG7EI8_V_M1_M1 = 11211,
11236 PseudoVSUXSEG7EI8_V_M1_M1_MASK = 11212,
11237 PseudoVSUXSEG7EI8_V_MF2_M1 = 11213,
11238 PseudoVSUXSEG7EI8_V_MF2_M1_MASK = 11214,
11239 PseudoVSUXSEG7EI8_V_MF2_MF2 = 11215,
11240 PseudoVSUXSEG7EI8_V_MF2_MF2_MASK = 11216,
11241 PseudoVSUXSEG7EI8_V_MF4_M1 = 11217,
11242 PseudoVSUXSEG7EI8_V_MF4_M1_MASK = 11218,
11243 PseudoVSUXSEG7EI8_V_MF4_MF2 = 11219,
11244 PseudoVSUXSEG7EI8_V_MF4_MF2_MASK = 11220,
11245 PseudoVSUXSEG7EI8_V_MF4_MF4 = 11221,
11246 PseudoVSUXSEG7EI8_V_MF4_MF4_MASK = 11222,
11247 PseudoVSUXSEG7EI8_V_MF8_M1 = 11223,
11248 PseudoVSUXSEG7EI8_V_MF8_M1_MASK = 11224,
11249 PseudoVSUXSEG7EI8_V_MF8_MF2 = 11225,
11250 PseudoVSUXSEG7EI8_V_MF8_MF2_MASK = 11226,
11251 PseudoVSUXSEG7EI8_V_MF8_MF4 = 11227,
11252 PseudoVSUXSEG7EI8_V_MF8_MF4_MASK = 11228,
11253 PseudoVSUXSEG7EI8_V_MF8_MF8 = 11229,
11254 PseudoVSUXSEG7EI8_V_MF8_MF8_MASK = 11230,
11255 PseudoVSUXSEG8EI16_V_M1_M1 = 11231,
11256 PseudoVSUXSEG8EI16_V_M1_M1_MASK = 11232,
11257 PseudoVSUXSEG8EI16_V_M1_MF2 = 11233,
11258 PseudoVSUXSEG8EI16_V_M1_MF2_MASK = 11234,
11259 PseudoVSUXSEG8EI16_V_M2_M1 = 11235,
11260 PseudoVSUXSEG8EI16_V_M2_M1_MASK = 11236,
11261 PseudoVSUXSEG8EI16_V_MF2_M1 = 11237,
11262 PseudoVSUXSEG8EI16_V_MF2_M1_MASK = 11238,
11263 PseudoVSUXSEG8EI16_V_MF2_MF2 = 11239,
11264 PseudoVSUXSEG8EI16_V_MF2_MF2_MASK = 11240,
11265 PseudoVSUXSEG8EI16_V_MF2_MF4 = 11241,
11266 PseudoVSUXSEG8EI16_V_MF2_MF4_MASK = 11242,
11267 PseudoVSUXSEG8EI16_V_MF4_M1 = 11243,
11268 PseudoVSUXSEG8EI16_V_MF4_M1_MASK = 11244,
11269 PseudoVSUXSEG8EI16_V_MF4_MF2 = 11245,
11270 PseudoVSUXSEG8EI16_V_MF4_MF2_MASK = 11246,
11271 PseudoVSUXSEG8EI16_V_MF4_MF4 = 11247,
11272 PseudoVSUXSEG8EI16_V_MF4_MF4_MASK = 11248,
11273 PseudoVSUXSEG8EI16_V_MF4_MF8 = 11249,
11274 PseudoVSUXSEG8EI16_V_MF4_MF8_MASK = 11250,
11275 PseudoVSUXSEG8EI32_V_M1_M1 = 11251,
11276 PseudoVSUXSEG8EI32_V_M1_M1_MASK = 11252,
11277 PseudoVSUXSEG8EI32_V_M1_MF2 = 11253,
11278 PseudoVSUXSEG8EI32_V_M1_MF2_MASK = 11254,
11279 PseudoVSUXSEG8EI32_V_M1_MF4 = 11255,
11280 PseudoVSUXSEG8EI32_V_M1_MF4_MASK = 11256,
11281 PseudoVSUXSEG8EI32_V_M2_M1 = 11257,
11282 PseudoVSUXSEG8EI32_V_M2_M1_MASK = 11258,
11283 PseudoVSUXSEG8EI32_V_M2_MF2 = 11259,
11284 PseudoVSUXSEG8EI32_V_M2_MF2_MASK = 11260,
11285 PseudoVSUXSEG8EI32_V_M4_M1 = 11261,
11286 PseudoVSUXSEG8EI32_V_M4_M1_MASK = 11262,
11287 PseudoVSUXSEG8EI32_V_MF2_M1 = 11263,
11288 PseudoVSUXSEG8EI32_V_MF2_M1_MASK = 11264,
11289 PseudoVSUXSEG8EI32_V_MF2_MF2 = 11265,
11290 PseudoVSUXSEG8EI32_V_MF2_MF2_MASK = 11266,
11291 PseudoVSUXSEG8EI32_V_MF2_MF4 = 11267,
11292 PseudoVSUXSEG8EI32_V_MF2_MF4_MASK = 11268,
11293 PseudoVSUXSEG8EI32_V_MF2_MF8 = 11269,
11294 PseudoVSUXSEG8EI32_V_MF2_MF8_MASK = 11270,
11295 PseudoVSUXSEG8EI64_V_M1_M1 = 11271,
11296 PseudoVSUXSEG8EI64_V_M1_M1_MASK = 11272,
11297 PseudoVSUXSEG8EI64_V_M1_MF2 = 11273,
11298 PseudoVSUXSEG8EI64_V_M1_MF2_MASK = 11274,
11299 PseudoVSUXSEG8EI64_V_M1_MF4 = 11275,
11300 PseudoVSUXSEG8EI64_V_M1_MF4_MASK = 11276,
11301 PseudoVSUXSEG8EI64_V_M1_MF8 = 11277,
11302 PseudoVSUXSEG8EI64_V_M1_MF8_MASK = 11278,
11303 PseudoVSUXSEG8EI64_V_M2_M1 = 11279,
11304 PseudoVSUXSEG8EI64_V_M2_M1_MASK = 11280,
11305 PseudoVSUXSEG8EI64_V_M2_MF2 = 11281,
11306 PseudoVSUXSEG8EI64_V_M2_MF2_MASK = 11282,
11307 PseudoVSUXSEG8EI64_V_M2_MF4 = 11283,
11308 PseudoVSUXSEG8EI64_V_M2_MF4_MASK = 11284,
11309 PseudoVSUXSEG8EI64_V_M4_M1 = 11285,
11310 PseudoVSUXSEG8EI64_V_M4_M1_MASK = 11286,
11311 PseudoVSUXSEG8EI64_V_M4_MF2 = 11287,
11312 PseudoVSUXSEG8EI64_V_M4_MF2_MASK = 11288,
11313 PseudoVSUXSEG8EI64_V_M8_M1 = 11289,
11314 PseudoVSUXSEG8EI64_V_M8_M1_MASK = 11290,
11315 PseudoVSUXSEG8EI8_V_M1_M1 = 11291,
11316 PseudoVSUXSEG8EI8_V_M1_M1_MASK = 11292,
11317 PseudoVSUXSEG8EI8_V_MF2_M1 = 11293,
11318 PseudoVSUXSEG8EI8_V_MF2_M1_MASK = 11294,
11319 PseudoVSUXSEG8EI8_V_MF2_MF2 = 11295,
11320 PseudoVSUXSEG8EI8_V_MF2_MF2_MASK = 11296,
11321 PseudoVSUXSEG8EI8_V_MF4_M1 = 11297,
11322 PseudoVSUXSEG8EI8_V_MF4_M1_MASK = 11298,
11323 PseudoVSUXSEG8EI8_V_MF4_MF2 = 11299,
11324 PseudoVSUXSEG8EI8_V_MF4_MF2_MASK = 11300,
11325 PseudoVSUXSEG8EI8_V_MF4_MF4 = 11301,
11326 PseudoVSUXSEG8EI8_V_MF4_MF4_MASK = 11302,
11327 PseudoVSUXSEG8EI8_V_MF8_M1 = 11303,
11328 PseudoVSUXSEG8EI8_V_MF8_M1_MASK = 11304,
11329 PseudoVSUXSEG8EI8_V_MF8_MF2 = 11305,
11330 PseudoVSUXSEG8EI8_V_MF8_MF2_MASK = 11306,
11331 PseudoVSUXSEG8EI8_V_MF8_MF4 = 11307,
11332 PseudoVSUXSEG8EI8_V_MF8_MF4_MASK = 11308,
11333 PseudoVSUXSEG8EI8_V_MF8_MF8 = 11309,
11334 PseudoVSUXSEG8EI8_V_MF8_MF8_MASK = 11310,
11335 PseudoVWADDU_VV_M1 = 11311,
11336 PseudoVWADDU_VV_M1_MASK = 11312,
11337 PseudoVWADDU_VV_M2 = 11313,
11338 PseudoVWADDU_VV_M2_MASK = 11314,
11339 PseudoVWADDU_VV_M4 = 11315,
11340 PseudoVWADDU_VV_M4_MASK = 11316,
11341 PseudoVWADDU_VV_MF2 = 11317,
11342 PseudoVWADDU_VV_MF2_MASK = 11318,
11343 PseudoVWADDU_VV_MF4 = 11319,
11344 PseudoVWADDU_VV_MF4_MASK = 11320,
11345 PseudoVWADDU_VV_MF8 = 11321,
11346 PseudoVWADDU_VV_MF8_MASK = 11322,
11347 PseudoVWADDU_VX_M1 = 11323,
11348 PseudoVWADDU_VX_M1_MASK = 11324,
11349 PseudoVWADDU_VX_M2 = 11325,
11350 PseudoVWADDU_VX_M2_MASK = 11326,
11351 PseudoVWADDU_VX_M4 = 11327,
11352 PseudoVWADDU_VX_M4_MASK = 11328,
11353 PseudoVWADDU_VX_MF2 = 11329,
11354 PseudoVWADDU_VX_MF2_MASK = 11330,
11355 PseudoVWADDU_VX_MF4 = 11331,
11356 PseudoVWADDU_VX_MF4_MASK = 11332,
11357 PseudoVWADDU_VX_MF8 = 11333,
11358 PseudoVWADDU_VX_MF8_MASK = 11334,
11359 PseudoVWADDU_WV_M1 = 11335,
11360 PseudoVWADDU_WV_M1_MASK = 11336,
11361 PseudoVWADDU_WV_M1_MASK_TIED = 11337,
11362 PseudoVWADDU_WV_M1_TIED = 11338,
11363 PseudoVWADDU_WV_M2 = 11339,
11364 PseudoVWADDU_WV_M2_MASK = 11340,
11365 PseudoVWADDU_WV_M2_MASK_TIED = 11341,
11366 PseudoVWADDU_WV_M2_TIED = 11342,
11367 PseudoVWADDU_WV_M4 = 11343,
11368 PseudoVWADDU_WV_M4_MASK = 11344,
11369 PseudoVWADDU_WV_M4_MASK_TIED = 11345,
11370 PseudoVWADDU_WV_M4_TIED = 11346,
11371 PseudoVWADDU_WV_MF2 = 11347,
11372 PseudoVWADDU_WV_MF2_MASK = 11348,
11373 PseudoVWADDU_WV_MF2_MASK_TIED = 11349,
11374 PseudoVWADDU_WV_MF2_TIED = 11350,
11375 PseudoVWADDU_WV_MF4 = 11351,
11376 PseudoVWADDU_WV_MF4_MASK = 11352,
11377 PseudoVWADDU_WV_MF4_MASK_TIED = 11353,
11378 PseudoVWADDU_WV_MF4_TIED = 11354,
11379 PseudoVWADDU_WV_MF8 = 11355,
11380 PseudoVWADDU_WV_MF8_MASK = 11356,
11381 PseudoVWADDU_WV_MF8_MASK_TIED = 11357,
11382 PseudoVWADDU_WV_MF8_TIED = 11358,
11383 PseudoVWADDU_WX_M1 = 11359,
11384 PseudoVWADDU_WX_M1_MASK = 11360,
11385 PseudoVWADDU_WX_M2 = 11361,
11386 PseudoVWADDU_WX_M2_MASK = 11362,
11387 PseudoVWADDU_WX_M4 = 11363,
11388 PseudoVWADDU_WX_M4_MASK = 11364,
11389 PseudoVWADDU_WX_MF2 = 11365,
11390 PseudoVWADDU_WX_MF2_MASK = 11366,
11391 PseudoVWADDU_WX_MF4 = 11367,
11392 PseudoVWADDU_WX_MF4_MASK = 11368,
11393 PseudoVWADDU_WX_MF8 = 11369,
11394 PseudoVWADDU_WX_MF8_MASK = 11370,
11395 PseudoVWADD_VV_M1 = 11371,
11396 PseudoVWADD_VV_M1_MASK = 11372,
11397 PseudoVWADD_VV_M2 = 11373,
11398 PseudoVWADD_VV_M2_MASK = 11374,
11399 PseudoVWADD_VV_M4 = 11375,
11400 PseudoVWADD_VV_M4_MASK = 11376,
11401 PseudoVWADD_VV_MF2 = 11377,
11402 PseudoVWADD_VV_MF2_MASK = 11378,
11403 PseudoVWADD_VV_MF4 = 11379,
11404 PseudoVWADD_VV_MF4_MASK = 11380,
11405 PseudoVWADD_VV_MF8 = 11381,
11406 PseudoVWADD_VV_MF8_MASK = 11382,
11407 PseudoVWADD_VX_M1 = 11383,
11408 PseudoVWADD_VX_M1_MASK = 11384,
11409 PseudoVWADD_VX_M2 = 11385,
11410 PseudoVWADD_VX_M2_MASK = 11386,
11411 PseudoVWADD_VX_M4 = 11387,
11412 PseudoVWADD_VX_M4_MASK = 11388,
11413 PseudoVWADD_VX_MF2 = 11389,
11414 PseudoVWADD_VX_MF2_MASK = 11390,
11415 PseudoVWADD_VX_MF4 = 11391,
11416 PseudoVWADD_VX_MF4_MASK = 11392,
11417 PseudoVWADD_VX_MF8 = 11393,
11418 PseudoVWADD_VX_MF8_MASK = 11394,
11419 PseudoVWADD_WV_M1 = 11395,
11420 PseudoVWADD_WV_M1_MASK = 11396,
11421 PseudoVWADD_WV_M1_MASK_TIED = 11397,
11422 PseudoVWADD_WV_M1_TIED = 11398,
11423 PseudoVWADD_WV_M2 = 11399,
11424 PseudoVWADD_WV_M2_MASK = 11400,
11425 PseudoVWADD_WV_M2_MASK_TIED = 11401,
11426 PseudoVWADD_WV_M2_TIED = 11402,
11427 PseudoVWADD_WV_M4 = 11403,
11428 PseudoVWADD_WV_M4_MASK = 11404,
11429 PseudoVWADD_WV_M4_MASK_TIED = 11405,
11430 PseudoVWADD_WV_M4_TIED = 11406,
11431 PseudoVWADD_WV_MF2 = 11407,
11432 PseudoVWADD_WV_MF2_MASK = 11408,
11433 PseudoVWADD_WV_MF2_MASK_TIED = 11409,
11434 PseudoVWADD_WV_MF2_TIED = 11410,
11435 PseudoVWADD_WV_MF4 = 11411,
11436 PseudoVWADD_WV_MF4_MASK = 11412,
11437 PseudoVWADD_WV_MF4_MASK_TIED = 11413,
11438 PseudoVWADD_WV_MF4_TIED = 11414,
11439 PseudoVWADD_WV_MF8 = 11415,
11440 PseudoVWADD_WV_MF8_MASK = 11416,
11441 PseudoVWADD_WV_MF8_MASK_TIED = 11417,
11442 PseudoVWADD_WV_MF8_TIED = 11418,
11443 PseudoVWADD_WX_M1 = 11419,
11444 PseudoVWADD_WX_M1_MASK = 11420,
11445 PseudoVWADD_WX_M2 = 11421,
11446 PseudoVWADD_WX_M2_MASK = 11422,
11447 PseudoVWADD_WX_M4 = 11423,
11448 PseudoVWADD_WX_M4_MASK = 11424,
11449 PseudoVWADD_WX_MF2 = 11425,
11450 PseudoVWADD_WX_MF2_MASK = 11426,
11451 PseudoVWADD_WX_MF4 = 11427,
11452 PseudoVWADD_WX_MF4_MASK = 11428,
11453 PseudoVWADD_WX_MF8 = 11429,
11454 PseudoVWADD_WX_MF8_MASK = 11430,
11455 PseudoVWMACCSU_VV_M1 = 11431,
11456 PseudoVWMACCSU_VV_M1_MASK = 11432,
11457 PseudoVWMACCSU_VV_M2 = 11433,
11458 PseudoVWMACCSU_VV_M2_MASK = 11434,
11459 PseudoVWMACCSU_VV_M4 = 11435,
11460 PseudoVWMACCSU_VV_M4_MASK = 11436,
11461 PseudoVWMACCSU_VV_MF2 = 11437,
11462 PseudoVWMACCSU_VV_MF2_MASK = 11438,
11463 PseudoVWMACCSU_VV_MF4 = 11439,
11464 PseudoVWMACCSU_VV_MF4_MASK = 11440,
11465 PseudoVWMACCSU_VV_MF8 = 11441,
11466 PseudoVWMACCSU_VV_MF8_MASK = 11442,
11467 PseudoVWMACCSU_VX_M1 = 11443,
11468 PseudoVWMACCSU_VX_M1_MASK = 11444,
11469 PseudoVWMACCSU_VX_M2 = 11445,
11470 PseudoVWMACCSU_VX_M2_MASK = 11446,
11471 PseudoVWMACCSU_VX_M4 = 11447,
11472 PseudoVWMACCSU_VX_M4_MASK = 11448,
11473 PseudoVWMACCSU_VX_MF2 = 11449,
11474 PseudoVWMACCSU_VX_MF2_MASK = 11450,
11475 PseudoVWMACCSU_VX_MF4 = 11451,
11476 PseudoVWMACCSU_VX_MF4_MASK = 11452,
11477 PseudoVWMACCSU_VX_MF8 = 11453,
11478 PseudoVWMACCSU_VX_MF8_MASK = 11454,
11479 PseudoVWMACCUS_VX_M1 = 11455,
11480 PseudoVWMACCUS_VX_M1_MASK = 11456,
11481 PseudoVWMACCUS_VX_M2 = 11457,
11482 PseudoVWMACCUS_VX_M2_MASK = 11458,
11483 PseudoVWMACCUS_VX_M4 = 11459,
11484 PseudoVWMACCUS_VX_M4_MASK = 11460,
11485 PseudoVWMACCUS_VX_MF2 = 11461,
11486 PseudoVWMACCUS_VX_MF2_MASK = 11462,
11487 PseudoVWMACCUS_VX_MF4 = 11463,
11488 PseudoVWMACCUS_VX_MF4_MASK = 11464,
11489 PseudoVWMACCUS_VX_MF8 = 11465,
11490 PseudoVWMACCUS_VX_MF8_MASK = 11466,
11491 PseudoVWMACCU_VV_M1 = 11467,
11492 PseudoVWMACCU_VV_M1_MASK = 11468,
11493 PseudoVWMACCU_VV_M2 = 11469,
11494 PseudoVWMACCU_VV_M2_MASK = 11470,
11495 PseudoVWMACCU_VV_M4 = 11471,
11496 PseudoVWMACCU_VV_M4_MASK = 11472,
11497 PseudoVWMACCU_VV_MF2 = 11473,
11498 PseudoVWMACCU_VV_MF2_MASK = 11474,
11499 PseudoVWMACCU_VV_MF4 = 11475,
11500 PseudoVWMACCU_VV_MF4_MASK = 11476,
11501 PseudoVWMACCU_VV_MF8 = 11477,
11502 PseudoVWMACCU_VV_MF8_MASK = 11478,
11503 PseudoVWMACCU_VX_M1 = 11479,
11504 PseudoVWMACCU_VX_M1_MASK = 11480,
11505 PseudoVWMACCU_VX_M2 = 11481,
11506 PseudoVWMACCU_VX_M2_MASK = 11482,
11507 PseudoVWMACCU_VX_M4 = 11483,
11508 PseudoVWMACCU_VX_M4_MASK = 11484,
11509 PseudoVWMACCU_VX_MF2 = 11485,
11510 PseudoVWMACCU_VX_MF2_MASK = 11486,
11511 PseudoVWMACCU_VX_MF4 = 11487,
11512 PseudoVWMACCU_VX_MF4_MASK = 11488,
11513 PseudoVWMACCU_VX_MF8 = 11489,
11514 PseudoVWMACCU_VX_MF8_MASK = 11490,
11515 PseudoVWMACC_VV_M1 = 11491,
11516 PseudoVWMACC_VV_M1_MASK = 11492,
11517 PseudoVWMACC_VV_M2 = 11493,
11518 PseudoVWMACC_VV_M2_MASK = 11494,
11519 PseudoVWMACC_VV_M4 = 11495,
11520 PseudoVWMACC_VV_M4_MASK = 11496,
11521 PseudoVWMACC_VV_MF2 = 11497,
11522 PseudoVWMACC_VV_MF2_MASK = 11498,
11523 PseudoVWMACC_VV_MF4 = 11499,
11524 PseudoVWMACC_VV_MF4_MASK = 11500,
11525 PseudoVWMACC_VV_MF8 = 11501,
11526 PseudoVWMACC_VV_MF8_MASK = 11502,
11527 PseudoVWMACC_VX_M1 = 11503,
11528 PseudoVWMACC_VX_M1_MASK = 11504,
11529 PseudoVWMACC_VX_M2 = 11505,
11530 PseudoVWMACC_VX_M2_MASK = 11506,
11531 PseudoVWMACC_VX_M4 = 11507,
11532 PseudoVWMACC_VX_M4_MASK = 11508,
11533 PseudoVWMACC_VX_MF2 = 11509,
11534 PseudoVWMACC_VX_MF2_MASK = 11510,
11535 PseudoVWMACC_VX_MF4 = 11511,
11536 PseudoVWMACC_VX_MF4_MASK = 11512,
11537 PseudoVWMACC_VX_MF8 = 11513,
11538 PseudoVWMACC_VX_MF8_MASK = 11514,
11539 PseudoVWMULSU_VV_M1 = 11515,
11540 PseudoVWMULSU_VV_M1_MASK = 11516,
11541 PseudoVWMULSU_VV_M2 = 11517,
11542 PseudoVWMULSU_VV_M2_MASK = 11518,
11543 PseudoVWMULSU_VV_M4 = 11519,
11544 PseudoVWMULSU_VV_M4_MASK = 11520,
11545 PseudoVWMULSU_VV_MF2 = 11521,
11546 PseudoVWMULSU_VV_MF2_MASK = 11522,
11547 PseudoVWMULSU_VV_MF4 = 11523,
11548 PseudoVWMULSU_VV_MF4_MASK = 11524,
11549 PseudoVWMULSU_VV_MF8 = 11525,
11550 PseudoVWMULSU_VV_MF8_MASK = 11526,
11551 PseudoVWMULSU_VX_M1 = 11527,
11552 PseudoVWMULSU_VX_M1_MASK = 11528,
11553 PseudoVWMULSU_VX_M2 = 11529,
11554 PseudoVWMULSU_VX_M2_MASK = 11530,
11555 PseudoVWMULSU_VX_M4 = 11531,
11556 PseudoVWMULSU_VX_M4_MASK = 11532,
11557 PseudoVWMULSU_VX_MF2 = 11533,
11558 PseudoVWMULSU_VX_MF2_MASK = 11534,
11559 PseudoVWMULSU_VX_MF4 = 11535,
11560 PseudoVWMULSU_VX_MF4_MASK = 11536,
11561 PseudoVWMULSU_VX_MF8 = 11537,
11562 PseudoVWMULSU_VX_MF8_MASK = 11538,
11563 PseudoVWMULU_VV_M1 = 11539,
11564 PseudoVWMULU_VV_M1_MASK = 11540,
11565 PseudoVWMULU_VV_M2 = 11541,
11566 PseudoVWMULU_VV_M2_MASK = 11542,
11567 PseudoVWMULU_VV_M4 = 11543,
11568 PseudoVWMULU_VV_M4_MASK = 11544,
11569 PseudoVWMULU_VV_MF2 = 11545,
11570 PseudoVWMULU_VV_MF2_MASK = 11546,
11571 PseudoVWMULU_VV_MF4 = 11547,
11572 PseudoVWMULU_VV_MF4_MASK = 11548,
11573 PseudoVWMULU_VV_MF8 = 11549,
11574 PseudoVWMULU_VV_MF8_MASK = 11550,
11575 PseudoVWMULU_VX_M1 = 11551,
11576 PseudoVWMULU_VX_M1_MASK = 11552,
11577 PseudoVWMULU_VX_M2 = 11553,
11578 PseudoVWMULU_VX_M2_MASK = 11554,
11579 PseudoVWMULU_VX_M4 = 11555,
11580 PseudoVWMULU_VX_M4_MASK = 11556,
11581 PseudoVWMULU_VX_MF2 = 11557,
11582 PseudoVWMULU_VX_MF2_MASK = 11558,
11583 PseudoVWMULU_VX_MF4 = 11559,
11584 PseudoVWMULU_VX_MF4_MASK = 11560,
11585 PseudoVWMULU_VX_MF8 = 11561,
11586 PseudoVWMULU_VX_MF8_MASK = 11562,
11587 PseudoVWMUL_VV_M1 = 11563,
11588 PseudoVWMUL_VV_M1_MASK = 11564,
11589 PseudoVWMUL_VV_M2 = 11565,
11590 PseudoVWMUL_VV_M2_MASK = 11566,
11591 PseudoVWMUL_VV_M4 = 11567,
11592 PseudoVWMUL_VV_M4_MASK = 11568,
11593 PseudoVWMUL_VV_MF2 = 11569,
11594 PseudoVWMUL_VV_MF2_MASK = 11570,
11595 PseudoVWMUL_VV_MF4 = 11571,
11596 PseudoVWMUL_VV_MF4_MASK = 11572,
11597 PseudoVWMUL_VV_MF8 = 11573,
11598 PseudoVWMUL_VV_MF8_MASK = 11574,
11599 PseudoVWMUL_VX_M1 = 11575,
11600 PseudoVWMUL_VX_M1_MASK = 11576,
11601 PseudoVWMUL_VX_M2 = 11577,
11602 PseudoVWMUL_VX_M2_MASK = 11578,
11603 PseudoVWMUL_VX_M4 = 11579,
11604 PseudoVWMUL_VX_M4_MASK = 11580,
11605 PseudoVWMUL_VX_MF2 = 11581,
11606 PseudoVWMUL_VX_MF2_MASK = 11582,
11607 PseudoVWMUL_VX_MF4 = 11583,
11608 PseudoVWMUL_VX_MF4_MASK = 11584,
11609 PseudoVWMUL_VX_MF8 = 11585,
11610 PseudoVWMUL_VX_MF8_MASK = 11586,
11611 PseudoVWREDSUMU_VS_M1_E16 = 11587,
11612 PseudoVWREDSUMU_VS_M1_E16_MASK = 11588,
11613 PseudoVWREDSUMU_VS_M1_E32 = 11589,
11614 PseudoVWREDSUMU_VS_M1_E32_MASK = 11590,
11615 PseudoVWREDSUMU_VS_M1_E8 = 11591,
11616 PseudoVWREDSUMU_VS_M1_E8_MASK = 11592,
11617 PseudoVWREDSUMU_VS_M2_E16 = 11593,
11618 PseudoVWREDSUMU_VS_M2_E16_MASK = 11594,
11619 PseudoVWREDSUMU_VS_M2_E32 = 11595,
11620 PseudoVWREDSUMU_VS_M2_E32_MASK = 11596,
11621 PseudoVWREDSUMU_VS_M2_E8 = 11597,
11622 PseudoVWREDSUMU_VS_M2_E8_MASK = 11598,
11623 PseudoVWREDSUMU_VS_M4_E16 = 11599,
11624 PseudoVWREDSUMU_VS_M4_E16_MASK = 11600,
11625 PseudoVWREDSUMU_VS_M4_E32 = 11601,
11626 PseudoVWREDSUMU_VS_M4_E32_MASK = 11602,
11627 PseudoVWREDSUMU_VS_M4_E8 = 11603,
11628 PseudoVWREDSUMU_VS_M4_E8_MASK = 11604,
11629 PseudoVWREDSUMU_VS_M8_E16 = 11605,
11630 PseudoVWREDSUMU_VS_M8_E16_MASK = 11606,
11631 PseudoVWREDSUMU_VS_M8_E32 = 11607,
11632 PseudoVWREDSUMU_VS_M8_E32_MASK = 11608,
11633 PseudoVWREDSUMU_VS_M8_E8 = 11609,
11634 PseudoVWREDSUMU_VS_M8_E8_MASK = 11610,
11635 PseudoVWREDSUMU_VS_MF2_E16 = 11611,
11636 PseudoVWREDSUMU_VS_MF2_E16_MASK = 11612,
11637 PseudoVWREDSUMU_VS_MF2_E32 = 11613,
11638 PseudoVWREDSUMU_VS_MF2_E32_MASK = 11614,
11639 PseudoVWREDSUMU_VS_MF2_E8 = 11615,
11640 PseudoVWREDSUMU_VS_MF2_E8_MASK = 11616,
11641 PseudoVWREDSUMU_VS_MF4_E16 = 11617,
11642 PseudoVWREDSUMU_VS_MF4_E16_MASK = 11618,
11643 PseudoVWREDSUMU_VS_MF4_E8 = 11619,
11644 PseudoVWREDSUMU_VS_MF4_E8_MASK = 11620,
11645 PseudoVWREDSUMU_VS_MF8_E8 = 11621,
11646 PseudoVWREDSUMU_VS_MF8_E8_MASK = 11622,
11647 PseudoVWREDSUM_VS_M1_E16 = 11623,
11648 PseudoVWREDSUM_VS_M1_E16_MASK = 11624,
11649 PseudoVWREDSUM_VS_M1_E32 = 11625,
11650 PseudoVWREDSUM_VS_M1_E32_MASK = 11626,
11651 PseudoVWREDSUM_VS_M1_E8 = 11627,
11652 PseudoVWREDSUM_VS_M1_E8_MASK = 11628,
11653 PseudoVWREDSUM_VS_M2_E16 = 11629,
11654 PseudoVWREDSUM_VS_M2_E16_MASK = 11630,
11655 PseudoVWREDSUM_VS_M2_E32 = 11631,
11656 PseudoVWREDSUM_VS_M2_E32_MASK = 11632,
11657 PseudoVWREDSUM_VS_M2_E8 = 11633,
11658 PseudoVWREDSUM_VS_M2_E8_MASK = 11634,
11659 PseudoVWREDSUM_VS_M4_E16 = 11635,
11660 PseudoVWREDSUM_VS_M4_E16_MASK = 11636,
11661 PseudoVWREDSUM_VS_M4_E32 = 11637,
11662 PseudoVWREDSUM_VS_M4_E32_MASK = 11638,
11663 PseudoVWREDSUM_VS_M4_E8 = 11639,
11664 PseudoVWREDSUM_VS_M4_E8_MASK = 11640,
11665 PseudoVWREDSUM_VS_M8_E16 = 11641,
11666 PseudoVWREDSUM_VS_M8_E16_MASK = 11642,
11667 PseudoVWREDSUM_VS_M8_E32 = 11643,
11668 PseudoVWREDSUM_VS_M8_E32_MASK = 11644,
11669 PseudoVWREDSUM_VS_M8_E8 = 11645,
11670 PseudoVWREDSUM_VS_M8_E8_MASK = 11646,
11671 PseudoVWREDSUM_VS_MF2_E16 = 11647,
11672 PseudoVWREDSUM_VS_MF2_E16_MASK = 11648,
11673 PseudoVWREDSUM_VS_MF2_E32 = 11649,
11674 PseudoVWREDSUM_VS_MF2_E32_MASK = 11650,
11675 PseudoVWREDSUM_VS_MF2_E8 = 11651,
11676 PseudoVWREDSUM_VS_MF2_E8_MASK = 11652,
11677 PseudoVWREDSUM_VS_MF4_E16 = 11653,
11678 PseudoVWREDSUM_VS_MF4_E16_MASK = 11654,
11679 PseudoVWREDSUM_VS_MF4_E8 = 11655,
11680 PseudoVWREDSUM_VS_MF4_E8_MASK = 11656,
11681 PseudoVWREDSUM_VS_MF8_E8 = 11657,
11682 PseudoVWREDSUM_VS_MF8_E8_MASK = 11658,
11683 PseudoVWSLL_VI_M1 = 11659,
11684 PseudoVWSLL_VI_M1_MASK = 11660,
11685 PseudoVWSLL_VI_M2 = 11661,
11686 PseudoVWSLL_VI_M2_MASK = 11662,
11687 PseudoVWSLL_VI_M4 = 11663,
11688 PseudoVWSLL_VI_M4_MASK = 11664,
11689 PseudoVWSLL_VI_MF2 = 11665,
11690 PseudoVWSLL_VI_MF2_MASK = 11666,
11691 PseudoVWSLL_VI_MF4 = 11667,
11692 PseudoVWSLL_VI_MF4_MASK = 11668,
11693 PseudoVWSLL_VI_MF8 = 11669,
11694 PseudoVWSLL_VI_MF8_MASK = 11670,
11695 PseudoVWSLL_VV_M1 = 11671,
11696 PseudoVWSLL_VV_M1_MASK = 11672,
11697 PseudoVWSLL_VV_M2 = 11673,
11698 PseudoVWSLL_VV_M2_MASK = 11674,
11699 PseudoVWSLL_VV_M4 = 11675,
11700 PseudoVWSLL_VV_M4_MASK = 11676,
11701 PseudoVWSLL_VV_MF2 = 11677,
11702 PseudoVWSLL_VV_MF2_MASK = 11678,
11703 PseudoVWSLL_VV_MF4 = 11679,
11704 PseudoVWSLL_VV_MF4_MASK = 11680,
11705 PseudoVWSLL_VV_MF8 = 11681,
11706 PseudoVWSLL_VV_MF8_MASK = 11682,
11707 PseudoVWSLL_VX_M1 = 11683,
11708 PseudoVWSLL_VX_M1_MASK = 11684,
11709 PseudoVWSLL_VX_M2 = 11685,
11710 PseudoVWSLL_VX_M2_MASK = 11686,
11711 PseudoVWSLL_VX_M4 = 11687,
11712 PseudoVWSLL_VX_M4_MASK = 11688,
11713 PseudoVWSLL_VX_MF2 = 11689,
11714 PseudoVWSLL_VX_MF2_MASK = 11690,
11715 PseudoVWSLL_VX_MF4 = 11691,
11716 PseudoVWSLL_VX_MF4_MASK = 11692,
11717 PseudoVWSLL_VX_MF8 = 11693,
11718 PseudoVWSLL_VX_MF8_MASK = 11694,
11719 PseudoVWSUBU_VV_M1 = 11695,
11720 PseudoVWSUBU_VV_M1_MASK = 11696,
11721 PseudoVWSUBU_VV_M2 = 11697,
11722 PseudoVWSUBU_VV_M2_MASK = 11698,
11723 PseudoVWSUBU_VV_M4 = 11699,
11724 PseudoVWSUBU_VV_M4_MASK = 11700,
11725 PseudoVWSUBU_VV_MF2 = 11701,
11726 PseudoVWSUBU_VV_MF2_MASK = 11702,
11727 PseudoVWSUBU_VV_MF4 = 11703,
11728 PseudoVWSUBU_VV_MF4_MASK = 11704,
11729 PseudoVWSUBU_VV_MF8 = 11705,
11730 PseudoVWSUBU_VV_MF8_MASK = 11706,
11731 PseudoVWSUBU_VX_M1 = 11707,
11732 PseudoVWSUBU_VX_M1_MASK = 11708,
11733 PseudoVWSUBU_VX_M2 = 11709,
11734 PseudoVWSUBU_VX_M2_MASK = 11710,
11735 PseudoVWSUBU_VX_M4 = 11711,
11736 PseudoVWSUBU_VX_M4_MASK = 11712,
11737 PseudoVWSUBU_VX_MF2 = 11713,
11738 PseudoVWSUBU_VX_MF2_MASK = 11714,
11739 PseudoVWSUBU_VX_MF4 = 11715,
11740 PseudoVWSUBU_VX_MF4_MASK = 11716,
11741 PseudoVWSUBU_VX_MF8 = 11717,
11742 PseudoVWSUBU_VX_MF8_MASK = 11718,
11743 PseudoVWSUBU_WV_M1 = 11719,
11744 PseudoVWSUBU_WV_M1_MASK = 11720,
11745 PseudoVWSUBU_WV_M1_MASK_TIED = 11721,
11746 PseudoVWSUBU_WV_M1_TIED = 11722,
11747 PseudoVWSUBU_WV_M2 = 11723,
11748 PseudoVWSUBU_WV_M2_MASK = 11724,
11749 PseudoVWSUBU_WV_M2_MASK_TIED = 11725,
11750 PseudoVWSUBU_WV_M2_TIED = 11726,
11751 PseudoVWSUBU_WV_M4 = 11727,
11752 PseudoVWSUBU_WV_M4_MASK = 11728,
11753 PseudoVWSUBU_WV_M4_MASK_TIED = 11729,
11754 PseudoVWSUBU_WV_M4_TIED = 11730,
11755 PseudoVWSUBU_WV_MF2 = 11731,
11756 PseudoVWSUBU_WV_MF2_MASK = 11732,
11757 PseudoVWSUBU_WV_MF2_MASK_TIED = 11733,
11758 PseudoVWSUBU_WV_MF2_TIED = 11734,
11759 PseudoVWSUBU_WV_MF4 = 11735,
11760 PseudoVWSUBU_WV_MF4_MASK = 11736,
11761 PseudoVWSUBU_WV_MF4_MASK_TIED = 11737,
11762 PseudoVWSUBU_WV_MF4_TIED = 11738,
11763 PseudoVWSUBU_WV_MF8 = 11739,
11764 PseudoVWSUBU_WV_MF8_MASK = 11740,
11765 PseudoVWSUBU_WV_MF8_MASK_TIED = 11741,
11766 PseudoVWSUBU_WV_MF8_TIED = 11742,
11767 PseudoVWSUBU_WX_M1 = 11743,
11768 PseudoVWSUBU_WX_M1_MASK = 11744,
11769 PseudoVWSUBU_WX_M2 = 11745,
11770 PseudoVWSUBU_WX_M2_MASK = 11746,
11771 PseudoVWSUBU_WX_M4 = 11747,
11772 PseudoVWSUBU_WX_M4_MASK = 11748,
11773 PseudoVWSUBU_WX_MF2 = 11749,
11774 PseudoVWSUBU_WX_MF2_MASK = 11750,
11775 PseudoVWSUBU_WX_MF4 = 11751,
11776 PseudoVWSUBU_WX_MF4_MASK = 11752,
11777 PseudoVWSUBU_WX_MF8 = 11753,
11778 PseudoVWSUBU_WX_MF8_MASK = 11754,
11779 PseudoVWSUB_VV_M1 = 11755,
11780 PseudoVWSUB_VV_M1_MASK = 11756,
11781 PseudoVWSUB_VV_M2 = 11757,
11782 PseudoVWSUB_VV_M2_MASK = 11758,
11783 PseudoVWSUB_VV_M4 = 11759,
11784 PseudoVWSUB_VV_M4_MASK = 11760,
11785 PseudoVWSUB_VV_MF2 = 11761,
11786 PseudoVWSUB_VV_MF2_MASK = 11762,
11787 PseudoVWSUB_VV_MF4 = 11763,
11788 PseudoVWSUB_VV_MF4_MASK = 11764,
11789 PseudoVWSUB_VV_MF8 = 11765,
11790 PseudoVWSUB_VV_MF8_MASK = 11766,
11791 PseudoVWSUB_VX_M1 = 11767,
11792 PseudoVWSUB_VX_M1_MASK = 11768,
11793 PseudoVWSUB_VX_M2 = 11769,
11794 PseudoVWSUB_VX_M2_MASK = 11770,
11795 PseudoVWSUB_VX_M4 = 11771,
11796 PseudoVWSUB_VX_M4_MASK = 11772,
11797 PseudoVWSUB_VX_MF2 = 11773,
11798 PseudoVWSUB_VX_MF2_MASK = 11774,
11799 PseudoVWSUB_VX_MF4 = 11775,
11800 PseudoVWSUB_VX_MF4_MASK = 11776,
11801 PseudoVWSUB_VX_MF8 = 11777,
11802 PseudoVWSUB_VX_MF8_MASK = 11778,
11803 PseudoVWSUB_WV_M1 = 11779,
11804 PseudoVWSUB_WV_M1_MASK = 11780,
11805 PseudoVWSUB_WV_M1_MASK_TIED = 11781,
11806 PseudoVWSUB_WV_M1_TIED = 11782,
11807 PseudoVWSUB_WV_M2 = 11783,
11808 PseudoVWSUB_WV_M2_MASK = 11784,
11809 PseudoVWSUB_WV_M2_MASK_TIED = 11785,
11810 PseudoVWSUB_WV_M2_TIED = 11786,
11811 PseudoVWSUB_WV_M4 = 11787,
11812 PseudoVWSUB_WV_M4_MASK = 11788,
11813 PseudoVWSUB_WV_M4_MASK_TIED = 11789,
11814 PseudoVWSUB_WV_M4_TIED = 11790,
11815 PseudoVWSUB_WV_MF2 = 11791,
11816 PseudoVWSUB_WV_MF2_MASK = 11792,
11817 PseudoVWSUB_WV_MF2_MASK_TIED = 11793,
11818 PseudoVWSUB_WV_MF2_TIED = 11794,
11819 PseudoVWSUB_WV_MF4 = 11795,
11820 PseudoVWSUB_WV_MF4_MASK = 11796,
11821 PseudoVWSUB_WV_MF4_MASK_TIED = 11797,
11822 PseudoVWSUB_WV_MF4_TIED = 11798,
11823 PseudoVWSUB_WV_MF8 = 11799,
11824 PseudoVWSUB_WV_MF8_MASK = 11800,
11825 PseudoVWSUB_WV_MF8_MASK_TIED = 11801,
11826 PseudoVWSUB_WV_MF8_TIED = 11802,
11827 PseudoVWSUB_WX_M1 = 11803,
11828 PseudoVWSUB_WX_M1_MASK = 11804,
11829 PseudoVWSUB_WX_M2 = 11805,
11830 PseudoVWSUB_WX_M2_MASK = 11806,
11831 PseudoVWSUB_WX_M4 = 11807,
11832 PseudoVWSUB_WX_M4_MASK = 11808,
11833 PseudoVWSUB_WX_MF2 = 11809,
11834 PseudoVWSUB_WX_MF2_MASK = 11810,
11835 PseudoVWSUB_WX_MF4 = 11811,
11836 PseudoVWSUB_WX_MF4_MASK = 11812,
11837 PseudoVWSUB_WX_MF8 = 11813,
11838 PseudoVWSUB_WX_MF8_MASK = 11814,
11839 PseudoVXOR_VI_M1 = 11815,
11840 PseudoVXOR_VI_M1_MASK = 11816,
11841 PseudoVXOR_VI_M2 = 11817,
11842 PseudoVXOR_VI_M2_MASK = 11818,
11843 PseudoVXOR_VI_M4 = 11819,
11844 PseudoVXOR_VI_M4_MASK = 11820,
11845 PseudoVXOR_VI_M8 = 11821,
11846 PseudoVXOR_VI_M8_MASK = 11822,
11847 PseudoVXOR_VI_MF2 = 11823,
11848 PseudoVXOR_VI_MF2_MASK = 11824,
11849 PseudoVXOR_VI_MF4 = 11825,
11850 PseudoVXOR_VI_MF4_MASK = 11826,
11851 PseudoVXOR_VI_MF8 = 11827,
11852 PseudoVXOR_VI_MF8_MASK = 11828,
11853 PseudoVXOR_VV_M1 = 11829,
11854 PseudoVXOR_VV_M1_MASK = 11830,
11855 PseudoVXOR_VV_M2 = 11831,
11856 PseudoVXOR_VV_M2_MASK = 11832,
11857 PseudoVXOR_VV_M4 = 11833,
11858 PseudoVXOR_VV_M4_MASK = 11834,
11859 PseudoVXOR_VV_M8 = 11835,
11860 PseudoVXOR_VV_M8_MASK = 11836,
11861 PseudoVXOR_VV_MF2 = 11837,
11862 PseudoVXOR_VV_MF2_MASK = 11838,
11863 PseudoVXOR_VV_MF4 = 11839,
11864 PseudoVXOR_VV_MF4_MASK = 11840,
11865 PseudoVXOR_VV_MF8 = 11841,
11866 PseudoVXOR_VV_MF8_MASK = 11842,
11867 PseudoVXOR_VX_M1 = 11843,
11868 PseudoVXOR_VX_M1_MASK = 11844,
11869 PseudoVXOR_VX_M2 = 11845,
11870 PseudoVXOR_VX_M2_MASK = 11846,
11871 PseudoVXOR_VX_M4 = 11847,
11872 PseudoVXOR_VX_M4_MASK = 11848,
11873 PseudoVXOR_VX_M8 = 11849,
11874 PseudoVXOR_VX_M8_MASK = 11850,
11875 PseudoVXOR_VX_MF2 = 11851,
11876 PseudoVXOR_VX_MF2_MASK = 11852,
11877 PseudoVXOR_VX_MF4 = 11853,
11878 PseudoVXOR_VX_MF4_MASK = 11854,
11879 PseudoVXOR_VX_MF8 = 11855,
11880 PseudoVXOR_VX_MF8_MASK = 11856,
11881 PseudoVZEXT_VF2_M1 = 11857,
11882 PseudoVZEXT_VF2_M1_MASK = 11858,
11883 PseudoVZEXT_VF2_M2 = 11859,
11884 PseudoVZEXT_VF2_M2_MASK = 11860,
11885 PseudoVZEXT_VF2_M4 = 11861,
11886 PseudoVZEXT_VF2_M4_MASK = 11862,
11887 PseudoVZEXT_VF2_M8 = 11863,
11888 PseudoVZEXT_VF2_M8_MASK = 11864,
11889 PseudoVZEXT_VF2_MF2 = 11865,
11890 PseudoVZEXT_VF2_MF2_MASK = 11866,
11891 PseudoVZEXT_VF2_MF4 = 11867,
11892 PseudoVZEXT_VF2_MF4_MASK = 11868,
11893 PseudoVZEXT_VF4_M1 = 11869,
11894 PseudoVZEXT_VF4_M1_MASK = 11870,
11895 PseudoVZEXT_VF4_M2 = 11871,
11896 PseudoVZEXT_VF4_M2_MASK = 11872,
11897 PseudoVZEXT_VF4_M4 = 11873,
11898 PseudoVZEXT_VF4_M4_MASK = 11874,
11899 PseudoVZEXT_VF4_M8 = 11875,
11900 PseudoVZEXT_VF4_M8_MASK = 11876,
11901 PseudoVZEXT_VF4_MF2 = 11877,
11902 PseudoVZEXT_VF4_MF2_MASK = 11878,
11903 PseudoVZEXT_VF8_M1 = 11879,
11904 PseudoVZEXT_VF8_M1_MASK = 11880,
11905 PseudoVZEXT_VF8_M2 = 11881,
11906 PseudoVZEXT_VF8_M2_MASK = 11882,
11907 PseudoVZEXT_VF8_M4 = 11883,
11908 PseudoVZEXT_VF8_M4_MASK = 11884,
11909 PseudoVZEXT_VF8_M8 = 11885,
11910 PseudoVZEXT_VF8_M8_MASK = 11886,
11911 PseudoZEXT_H = 11887,
11912 PseudoZEXT_W = 11888,
11913 ReadCounterWide = 11889,
11914 ReadFFLAGS = 11890,
11915 ReadFRM = 11891,
11916 Select_FPR16INX_Using_CC_GPR = 11892,
11917 Select_FPR16_Using_CC_GPR = 11893,
11918 Select_FPR32INX_Using_CC_GPR = 11894,
11919 Select_FPR32_Using_CC_GPR = 11895,
11920 Select_FPR64IN32X_Using_CC_GPR = 11896,
11921 Select_FPR64INX_Using_CC_GPR = 11897,
11922 Select_FPR64_Using_CC_GPR = 11898,
11923 Select_GPR_Using_CC_GPR = 11899,
11924 Select_GPR_Using_CC_Imm = 11900,
11925 SplitF64Pseudo = 11901,
11926 SwapFRMImm = 11902,
11927 WriteFFLAGS = 11903,
11928 WriteFRM = 11904,
11929 WriteFRMImm = 11905,
11930 WriteVXRMImm = 11906,
11931 ADD = 11907,
11932 ADDI = 11908,
11933 ADDIW = 11909,
11934 ADDW = 11910,
11935 ADD_UW = 11911,
11936 AES32DSI = 11912,
11937 AES32DSMI = 11913,
11938 AES32ESI = 11914,
11939 AES32ESMI = 11915,
11940 AES64DS = 11916,
11941 AES64DSM = 11917,
11942 AES64ES = 11918,
11943 AES64ESM = 11919,
11944 AES64IM = 11920,
11945 AES64KS1I = 11921,
11946 AES64KS2 = 11922,
11947 AMOADD_B = 11923,
11948 AMOADD_B_AQ = 11924,
11949 AMOADD_B_AQ_RL = 11925,
11950 AMOADD_B_RL = 11926,
11951 AMOADD_D = 11927,
11952 AMOADD_D_AQ = 11928,
11953 AMOADD_D_AQ_RL = 11929,
11954 AMOADD_D_RL = 11930,
11955 AMOADD_H = 11931,
11956 AMOADD_H_AQ = 11932,
11957 AMOADD_H_AQ_RL = 11933,
11958 AMOADD_H_RL = 11934,
11959 AMOADD_W = 11935,
11960 AMOADD_W_AQ = 11936,
11961 AMOADD_W_AQ_RL = 11937,
11962 AMOADD_W_RL = 11938,
11963 AMOAND_B = 11939,
11964 AMOAND_B_AQ = 11940,
11965 AMOAND_B_AQ_RL = 11941,
11966 AMOAND_B_RL = 11942,
11967 AMOAND_D = 11943,
11968 AMOAND_D_AQ = 11944,
11969 AMOAND_D_AQ_RL = 11945,
11970 AMOAND_D_RL = 11946,
11971 AMOAND_H = 11947,
11972 AMOAND_H_AQ = 11948,
11973 AMOAND_H_AQ_RL = 11949,
11974 AMOAND_H_RL = 11950,
11975 AMOAND_W = 11951,
11976 AMOAND_W_AQ = 11952,
11977 AMOAND_W_AQ_RL = 11953,
11978 AMOAND_W_RL = 11954,
11979 AMOCAS_B = 11955,
11980 AMOCAS_B_AQ = 11956,
11981 AMOCAS_B_AQ_RL = 11957,
11982 AMOCAS_B_RL = 11958,
11983 AMOCAS_D_RV32 = 11959,
11984 AMOCAS_D_RV32_AQ = 11960,
11985 AMOCAS_D_RV32_AQ_RL = 11961,
11986 AMOCAS_D_RV32_RL = 11962,
11987 AMOCAS_D_RV64 = 11963,
11988 AMOCAS_D_RV64_AQ = 11964,
11989 AMOCAS_D_RV64_AQ_RL = 11965,
11990 AMOCAS_D_RV64_RL = 11966,
11991 AMOCAS_H = 11967,
11992 AMOCAS_H_AQ = 11968,
11993 AMOCAS_H_AQ_RL = 11969,
11994 AMOCAS_H_RL = 11970,
11995 AMOCAS_Q = 11971,
11996 AMOCAS_Q_AQ = 11972,
11997 AMOCAS_Q_AQ_RL = 11973,
11998 AMOCAS_Q_RL = 11974,
11999 AMOCAS_W = 11975,
12000 AMOCAS_W_AQ = 11976,
12001 AMOCAS_W_AQ_RL = 11977,
12002 AMOCAS_W_RL = 11978,
12003 AMOMAXU_B = 11979,
12004 AMOMAXU_B_AQ = 11980,
12005 AMOMAXU_B_AQ_RL = 11981,
12006 AMOMAXU_B_RL = 11982,
12007 AMOMAXU_D = 11983,
12008 AMOMAXU_D_AQ = 11984,
12009 AMOMAXU_D_AQ_RL = 11985,
12010 AMOMAXU_D_RL = 11986,
12011 AMOMAXU_H = 11987,
12012 AMOMAXU_H_AQ = 11988,
12013 AMOMAXU_H_AQ_RL = 11989,
12014 AMOMAXU_H_RL = 11990,
12015 AMOMAXU_W = 11991,
12016 AMOMAXU_W_AQ = 11992,
12017 AMOMAXU_W_AQ_RL = 11993,
12018 AMOMAXU_W_RL = 11994,
12019 AMOMAX_B = 11995,
12020 AMOMAX_B_AQ = 11996,
12021 AMOMAX_B_AQ_RL = 11997,
12022 AMOMAX_B_RL = 11998,
12023 AMOMAX_D = 11999,
12024 AMOMAX_D_AQ = 12000,
12025 AMOMAX_D_AQ_RL = 12001,
12026 AMOMAX_D_RL = 12002,
12027 AMOMAX_H = 12003,
12028 AMOMAX_H_AQ = 12004,
12029 AMOMAX_H_AQ_RL = 12005,
12030 AMOMAX_H_RL = 12006,
12031 AMOMAX_W = 12007,
12032 AMOMAX_W_AQ = 12008,
12033 AMOMAX_W_AQ_RL = 12009,
12034 AMOMAX_W_RL = 12010,
12035 AMOMINU_B = 12011,
12036 AMOMINU_B_AQ = 12012,
12037 AMOMINU_B_AQ_RL = 12013,
12038 AMOMINU_B_RL = 12014,
12039 AMOMINU_D = 12015,
12040 AMOMINU_D_AQ = 12016,
12041 AMOMINU_D_AQ_RL = 12017,
12042 AMOMINU_D_RL = 12018,
12043 AMOMINU_H = 12019,
12044 AMOMINU_H_AQ = 12020,
12045 AMOMINU_H_AQ_RL = 12021,
12046 AMOMINU_H_RL = 12022,
12047 AMOMINU_W = 12023,
12048 AMOMINU_W_AQ = 12024,
12049 AMOMINU_W_AQ_RL = 12025,
12050 AMOMINU_W_RL = 12026,
12051 AMOMIN_B = 12027,
12052 AMOMIN_B_AQ = 12028,
12053 AMOMIN_B_AQ_RL = 12029,
12054 AMOMIN_B_RL = 12030,
12055 AMOMIN_D = 12031,
12056 AMOMIN_D_AQ = 12032,
12057 AMOMIN_D_AQ_RL = 12033,
12058 AMOMIN_D_RL = 12034,
12059 AMOMIN_H = 12035,
12060 AMOMIN_H_AQ = 12036,
12061 AMOMIN_H_AQ_RL = 12037,
12062 AMOMIN_H_RL = 12038,
12063 AMOMIN_W = 12039,
12064 AMOMIN_W_AQ = 12040,
12065 AMOMIN_W_AQ_RL = 12041,
12066 AMOMIN_W_RL = 12042,
12067 AMOOR_B = 12043,
12068 AMOOR_B_AQ = 12044,
12069 AMOOR_B_AQ_RL = 12045,
12070 AMOOR_B_RL = 12046,
12071 AMOOR_D = 12047,
12072 AMOOR_D_AQ = 12048,
12073 AMOOR_D_AQ_RL = 12049,
12074 AMOOR_D_RL = 12050,
12075 AMOOR_H = 12051,
12076 AMOOR_H_AQ = 12052,
12077 AMOOR_H_AQ_RL = 12053,
12078 AMOOR_H_RL = 12054,
12079 AMOOR_W = 12055,
12080 AMOOR_W_AQ = 12056,
12081 AMOOR_W_AQ_RL = 12057,
12082 AMOOR_W_RL = 12058,
12083 AMOSWAP_B = 12059,
12084 AMOSWAP_B_AQ = 12060,
12085 AMOSWAP_B_AQ_RL = 12061,
12086 AMOSWAP_B_RL = 12062,
12087 AMOSWAP_D = 12063,
12088 AMOSWAP_D_AQ = 12064,
12089 AMOSWAP_D_AQ_RL = 12065,
12090 AMOSWAP_D_RL = 12066,
12091 AMOSWAP_H = 12067,
12092 AMOSWAP_H_AQ = 12068,
12093 AMOSWAP_H_AQ_RL = 12069,
12094 AMOSWAP_H_RL = 12070,
12095 AMOSWAP_W = 12071,
12096 AMOSWAP_W_AQ = 12072,
12097 AMOSWAP_W_AQ_RL = 12073,
12098 AMOSWAP_W_RL = 12074,
12099 AMOXOR_B = 12075,
12100 AMOXOR_B_AQ = 12076,
12101 AMOXOR_B_AQ_RL = 12077,
12102 AMOXOR_B_RL = 12078,
12103 AMOXOR_D = 12079,
12104 AMOXOR_D_AQ = 12080,
12105 AMOXOR_D_AQ_RL = 12081,
12106 AMOXOR_D_RL = 12082,
12107 AMOXOR_H = 12083,
12108 AMOXOR_H_AQ = 12084,
12109 AMOXOR_H_AQ_RL = 12085,
12110 AMOXOR_H_RL = 12086,
12111 AMOXOR_W = 12087,
12112 AMOXOR_W_AQ = 12088,
12113 AMOXOR_W_AQ_RL = 12089,
12114 AMOXOR_W_RL = 12090,
12115 AND = 12091,
12116 ANDI = 12092,
12117 ANDN = 12093,
12118 AUIPC = 12094,
12119 BCLR = 12095,
12120 BCLRI = 12096,
12121 BEQ = 12097,
12122 BEXT = 12098,
12123 BEXTI = 12099,
12124 BGE = 12100,
12125 BGEU = 12101,
12126 BINV = 12102,
12127 BINVI = 12103,
12128 BLT = 12104,
12129 BLTU = 12105,
12130 BNE = 12106,
12131 BREV8 = 12107,
12132 BSET = 12108,
12133 BSETI = 12109,
12134 CBO_CLEAN = 12110,
12135 CBO_FLUSH = 12111,
12136 CBO_INVAL = 12112,
12137 CBO_ZERO = 12113,
12138 CLMUL = 12114,
12139 CLMULH = 12115,
12140 CLMULR = 12116,
12141 CLZ = 12117,
12142 CLZW = 12118,
12143 CM_JALT = 12119,
12144 CM_JT = 12120,
12145 CM_MVA01S = 12121,
12146 CM_MVSA01 = 12122,
12147 CM_POP = 12123,
12148 CM_POPRET = 12124,
12149 CM_POPRETZ = 12125,
12150 CM_PUSH = 12126,
12151 CPOP = 12127,
12152 CPOPW = 12128,
12153 CSRRC = 12129,
12154 CSRRCI = 12130,
12155 CSRRS = 12131,
12156 CSRRSI = 12132,
12157 CSRRW = 12133,
12158 CSRRWI = 12134,
12159 CTZ = 12135,
12160 CTZW = 12136,
12161 CV_ABS = 12137,
12162 CV_ABS_B = 12138,
12163 CV_ABS_H = 12139,
12164 CV_ADDN = 12140,
12165 CV_ADDNR = 12141,
12166 CV_ADDRN = 12142,
12167 CV_ADDRNR = 12143,
12168 CV_ADDUN = 12144,
12169 CV_ADDUNR = 12145,
12170 CV_ADDURN = 12146,
12171 CV_ADDURNR = 12147,
12172 CV_ADD_B = 12148,
12173 CV_ADD_DIV2 = 12149,
12174 CV_ADD_DIV4 = 12150,
12175 CV_ADD_DIV8 = 12151,
12176 CV_ADD_H = 12152,
12177 CV_ADD_SCI_B = 12153,
12178 CV_ADD_SCI_H = 12154,
12179 CV_ADD_SC_B = 12155,
12180 CV_ADD_SC_H = 12156,
12181 CV_AND_B = 12157,
12182 CV_AND_H = 12158,
12183 CV_AND_SCI_B = 12159,
12184 CV_AND_SCI_H = 12160,
12185 CV_AND_SC_B = 12161,
12186 CV_AND_SC_H = 12162,
12187 CV_AVGU_B = 12163,
12188 CV_AVGU_H = 12164,
12189 CV_AVGU_SCI_B = 12165,
12190 CV_AVGU_SCI_H = 12166,
12191 CV_AVGU_SC_B = 12167,
12192 CV_AVGU_SC_H = 12168,
12193 CV_AVG_B = 12169,
12194 CV_AVG_H = 12170,
12195 CV_AVG_SCI_B = 12171,
12196 CV_AVG_SCI_H = 12172,
12197 CV_AVG_SC_B = 12173,
12198 CV_AVG_SC_H = 12174,
12199 CV_BCLR = 12175,
12200 CV_BCLRR = 12176,
12201 CV_BEQIMM = 12177,
12202 CV_BITREV = 12178,
12203 CV_BNEIMM = 12179,
12204 CV_BSET = 12180,
12205 CV_BSETR = 12181,
12206 CV_CLB = 12182,
12207 CV_CLIP = 12183,
12208 CV_CLIPR = 12184,
12209 CV_CLIPU = 12185,
12210 CV_CLIPUR = 12186,
12211 CV_CMPEQ_B = 12187,
12212 CV_CMPEQ_H = 12188,
12213 CV_CMPEQ_SCI_B = 12189,
12214 CV_CMPEQ_SCI_H = 12190,
12215 CV_CMPEQ_SC_B = 12191,
12216 CV_CMPEQ_SC_H = 12192,
12217 CV_CMPGEU_B = 12193,
12218 CV_CMPGEU_H = 12194,
12219 CV_CMPGEU_SCI_B = 12195,
12220 CV_CMPGEU_SCI_H = 12196,
12221 CV_CMPGEU_SC_B = 12197,
12222 CV_CMPGEU_SC_H = 12198,
12223 CV_CMPGE_B = 12199,
12224 CV_CMPGE_H = 12200,
12225 CV_CMPGE_SCI_B = 12201,
12226 CV_CMPGE_SCI_H = 12202,
12227 CV_CMPGE_SC_B = 12203,
12228 CV_CMPGE_SC_H = 12204,
12229 CV_CMPGTU_B = 12205,
12230 CV_CMPGTU_H = 12206,
12231 CV_CMPGTU_SCI_B = 12207,
12232 CV_CMPGTU_SCI_H = 12208,
12233 CV_CMPGTU_SC_B = 12209,
12234 CV_CMPGTU_SC_H = 12210,
12235 CV_CMPGT_B = 12211,
12236 CV_CMPGT_H = 12212,
12237 CV_CMPGT_SCI_B = 12213,
12238 CV_CMPGT_SCI_H = 12214,
12239 CV_CMPGT_SC_B = 12215,
12240 CV_CMPGT_SC_H = 12216,
12241 CV_CMPLEU_B = 12217,
12242 CV_CMPLEU_H = 12218,
12243 CV_CMPLEU_SCI_B = 12219,
12244 CV_CMPLEU_SCI_H = 12220,
12245 CV_CMPLEU_SC_B = 12221,
12246 CV_CMPLEU_SC_H = 12222,
12247 CV_CMPLE_B = 12223,
12248 CV_CMPLE_H = 12224,
12249 CV_CMPLE_SCI_B = 12225,
12250 CV_CMPLE_SCI_H = 12226,
12251 CV_CMPLE_SC_B = 12227,
12252 CV_CMPLE_SC_H = 12228,
12253 CV_CMPLTU_B = 12229,
12254 CV_CMPLTU_H = 12230,
12255 CV_CMPLTU_SCI_B = 12231,
12256 CV_CMPLTU_SCI_H = 12232,
12257 CV_CMPLTU_SC_B = 12233,
12258 CV_CMPLTU_SC_H = 12234,
12259 CV_CMPLT_B = 12235,
12260 CV_CMPLT_H = 12236,
12261 CV_CMPLT_SCI_B = 12237,
12262 CV_CMPLT_SCI_H = 12238,
12263 CV_CMPLT_SC_B = 12239,
12264 CV_CMPLT_SC_H = 12240,
12265 CV_CMPNE_B = 12241,
12266 CV_CMPNE_H = 12242,
12267 CV_CMPNE_SCI_B = 12243,
12268 CV_CMPNE_SCI_H = 12244,
12269 CV_CMPNE_SC_B = 12245,
12270 CV_CMPNE_SC_H = 12246,
12271 CV_CNT = 12247,
12272 CV_CPLXCONJ = 12248,
12273 CV_CPLXMUL_I = 12249,
12274 CV_CPLXMUL_I_DIV2 = 12250,
12275 CV_CPLXMUL_I_DIV4 = 12251,
12276 CV_CPLXMUL_I_DIV8 = 12252,
12277 CV_CPLXMUL_R = 12253,
12278 CV_CPLXMUL_R_DIV2 = 12254,
12279 CV_CPLXMUL_R_DIV4 = 12255,
12280 CV_CPLXMUL_R_DIV8 = 12256,
12281 CV_DOTSP_B = 12257,
12282 CV_DOTSP_H = 12258,
12283 CV_DOTSP_SCI_B = 12259,
12284 CV_DOTSP_SCI_H = 12260,
12285 CV_DOTSP_SC_B = 12261,
12286 CV_DOTSP_SC_H = 12262,
12287 CV_DOTUP_B = 12263,
12288 CV_DOTUP_H = 12264,
12289 CV_DOTUP_SCI_B = 12265,
12290 CV_DOTUP_SCI_H = 12266,
12291 CV_DOTUP_SC_B = 12267,
12292 CV_DOTUP_SC_H = 12268,
12293 CV_DOTUSP_B = 12269,
12294 CV_DOTUSP_H = 12270,
12295 CV_DOTUSP_SCI_B = 12271,
12296 CV_DOTUSP_SCI_H = 12272,
12297 CV_DOTUSP_SC_B = 12273,
12298 CV_DOTUSP_SC_H = 12274,
12299 CV_ELW = 12275,
12300 CV_EXTBS = 12276,
12301 CV_EXTBZ = 12277,
12302 CV_EXTHS = 12278,
12303 CV_EXTHZ = 12279,
12304 CV_EXTRACT = 12280,
12305 CV_EXTRACTR = 12281,
12306 CV_EXTRACTU = 12282,
12307 CV_EXTRACTUR = 12283,
12308 CV_EXTRACTU_B = 12284,
12309 CV_EXTRACTU_H = 12285,
12310 CV_EXTRACT_B = 12286,
12311 CV_EXTRACT_H = 12287,
12312 CV_FF1 = 12288,
12313 CV_FL1 = 12289,
12314 CV_INSERT = 12290,
12315 CV_INSERTR = 12291,
12316 CV_INSERT_B = 12292,
12317 CV_INSERT_H = 12293,
12318 CV_LBU_ri_inc = 12294,
12319 CV_LBU_rr = 12295,
12320 CV_LBU_rr_inc = 12296,
12321 CV_LB_ri_inc = 12297,
12322 CV_LB_rr = 12298,
12323 CV_LB_rr_inc = 12299,
12324 CV_LHU_ri_inc = 12300,
12325 CV_LHU_rr = 12301,
12326 CV_LHU_rr_inc = 12302,
12327 CV_LH_ri_inc = 12303,
12328 CV_LH_rr = 12304,
12329 CV_LH_rr_inc = 12305,
12330 CV_LW_ri_inc = 12306,
12331 CV_LW_rr = 12307,
12332 CV_LW_rr_inc = 12308,
12333 CV_MAC = 12309,
12334 CV_MACHHSN = 12310,
12335 CV_MACHHSRN = 12311,
12336 CV_MACHHUN = 12312,
12337 CV_MACHHURN = 12313,
12338 CV_MACSN = 12314,
12339 CV_MACSRN = 12315,
12340 CV_MACUN = 12316,
12341 CV_MACURN = 12317,
12342 CV_MAX = 12318,
12343 CV_MAXU = 12319,
12344 CV_MAXU_B = 12320,
12345 CV_MAXU_H = 12321,
12346 CV_MAXU_SCI_B = 12322,
12347 CV_MAXU_SCI_H = 12323,
12348 CV_MAXU_SC_B = 12324,
12349 CV_MAXU_SC_H = 12325,
12350 CV_MAX_B = 12326,
12351 CV_MAX_H = 12327,
12352 CV_MAX_SCI_B = 12328,
12353 CV_MAX_SCI_H = 12329,
12354 CV_MAX_SC_B = 12330,
12355 CV_MAX_SC_H = 12331,
12356 CV_MIN = 12332,
12357 CV_MINU = 12333,
12358 CV_MINU_B = 12334,
12359 CV_MINU_H = 12335,
12360 CV_MINU_SCI_B = 12336,
12361 CV_MINU_SCI_H = 12337,
12362 CV_MINU_SC_B = 12338,
12363 CV_MINU_SC_H = 12339,
12364 CV_MIN_B = 12340,
12365 CV_MIN_H = 12341,
12366 CV_MIN_SCI_B = 12342,
12367 CV_MIN_SCI_H = 12343,
12368 CV_MIN_SC_B = 12344,
12369 CV_MIN_SC_H = 12345,
12370 CV_MSU = 12346,
12371 CV_MULHHSN = 12347,
12372 CV_MULHHSRN = 12348,
12373 CV_MULHHUN = 12349,
12374 CV_MULHHURN = 12350,
12375 CV_MULSN = 12351,
12376 CV_MULSRN = 12352,
12377 CV_MULUN = 12353,
12378 CV_MULURN = 12354,
12379 CV_OR_B = 12355,
12380 CV_OR_H = 12356,
12381 CV_OR_SCI_B = 12357,
12382 CV_OR_SCI_H = 12358,
12383 CV_OR_SC_B = 12359,
12384 CV_OR_SC_H = 12360,
12385 CV_PACK = 12361,
12386 CV_PACKHI_B = 12362,
12387 CV_PACKLO_B = 12363,
12388 CV_PACK_H = 12364,
12389 CV_ROR = 12365,
12390 CV_SB_ri_inc = 12366,
12391 CV_SB_rr = 12367,
12392 CV_SB_rr_inc = 12368,
12393 CV_SDOTSP_B = 12369,
12394 CV_SDOTSP_H = 12370,
12395 CV_SDOTSP_SCI_B = 12371,
12396 CV_SDOTSP_SCI_H = 12372,
12397 CV_SDOTSP_SC_B = 12373,
12398 CV_SDOTSP_SC_H = 12374,
12399 CV_SDOTUP_B = 12375,
12400 CV_SDOTUP_H = 12376,
12401 CV_SDOTUP_SCI_B = 12377,
12402 CV_SDOTUP_SCI_H = 12378,
12403 CV_SDOTUP_SC_B = 12379,
12404 CV_SDOTUP_SC_H = 12380,
12405 CV_SDOTUSP_B = 12381,
12406 CV_SDOTUSP_H = 12382,
12407 CV_SDOTUSP_SCI_B = 12383,
12408 CV_SDOTUSP_SCI_H = 12384,
12409 CV_SDOTUSP_SC_B = 12385,
12410 CV_SDOTUSP_SC_H = 12386,
12411 CV_SHUFFLE2_B = 12387,
12412 CV_SHUFFLE2_H = 12388,
12413 CV_SHUFFLEI0_SCI_B = 12389,
12414 CV_SHUFFLEI1_SCI_B = 12390,
12415 CV_SHUFFLEI2_SCI_B = 12391,
12416 CV_SHUFFLEI3_SCI_B = 12392,
12417 CV_SHUFFLE_B = 12393,
12418 CV_SHUFFLE_H = 12394,
12419 CV_SHUFFLE_SCI_H = 12395,
12420 CV_SH_ri_inc = 12396,
12421 CV_SH_rr = 12397,
12422 CV_SH_rr_inc = 12398,
12423 CV_SLET = 12399,
12424 CV_SLETU = 12400,
12425 CV_SLL_B = 12401,
12426 CV_SLL_H = 12402,
12427 CV_SLL_SCI_B = 12403,
12428 CV_SLL_SCI_H = 12404,
12429 CV_SLL_SC_B = 12405,
12430 CV_SLL_SC_H = 12406,
12431 CV_SRA_B = 12407,
12432 CV_SRA_H = 12408,
12433 CV_SRA_SCI_B = 12409,
12434 CV_SRA_SCI_H = 12410,
12435 CV_SRA_SC_B = 12411,
12436 CV_SRA_SC_H = 12412,
12437 CV_SRL_B = 12413,
12438 CV_SRL_H = 12414,
12439 CV_SRL_SCI_B = 12415,
12440 CV_SRL_SCI_H = 12416,
12441 CV_SRL_SC_B = 12417,
12442 CV_SRL_SC_H = 12418,
12443 CV_SUBN = 12419,
12444 CV_SUBNR = 12420,
12445 CV_SUBRN = 12421,
12446 CV_SUBRNR = 12422,
12447 CV_SUBROTMJ = 12423,
12448 CV_SUBROTMJ_DIV2 = 12424,
12449 CV_SUBROTMJ_DIV4 = 12425,
12450 CV_SUBROTMJ_DIV8 = 12426,
12451 CV_SUBUN = 12427,
12452 CV_SUBUNR = 12428,
12453 CV_SUBURN = 12429,
12454 CV_SUBURNR = 12430,
12455 CV_SUB_B = 12431,
12456 CV_SUB_DIV2 = 12432,
12457 CV_SUB_DIV4 = 12433,
12458 CV_SUB_DIV8 = 12434,
12459 CV_SUB_H = 12435,
12460 CV_SUB_SCI_B = 12436,
12461 CV_SUB_SCI_H = 12437,
12462 CV_SUB_SC_B = 12438,
12463 CV_SUB_SC_H = 12439,
12464 CV_SW_ri_inc = 12440,
12465 CV_SW_rr = 12441,
12466 CV_SW_rr_inc = 12442,
12467 CV_XOR_B = 12443,
12468 CV_XOR_H = 12444,
12469 CV_XOR_SCI_B = 12445,
12470 CV_XOR_SCI_H = 12446,
12471 CV_XOR_SC_B = 12447,
12472 CV_XOR_SC_H = 12448,
12473 CZERO_EQZ = 12449,
12474 CZERO_NEZ = 12450,
12475 C_ADD = 12451,
12476 C_ADDI = 12452,
12477 C_ADDI16SP = 12453,
12478 C_ADDI4SPN = 12454,
12479 C_ADDIW = 12455,
12480 C_ADDI_HINT_IMM_ZERO = 12456,
12481 C_ADDI_NOP = 12457,
12482 C_ADDW = 12458,
12483 C_ADD_HINT = 12459,
12484 C_AND = 12460,
12485 C_ANDI = 12461,
12486 C_BEQZ = 12462,
12487 C_BNEZ = 12463,
12488 C_EBREAK = 12464,
12489 C_FLD = 12465,
12490 C_FLDSP = 12466,
12491 C_FLW = 12467,
12492 C_FLWSP = 12468,
12493 C_FSD = 12469,
12494 C_FSDSP = 12470,
12495 C_FSW = 12471,
12496 C_FSWSP = 12472,
12497 C_J = 12473,
12498 C_JAL = 12474,
12499 C_JALR = 12475,
12500 C_JR = 12476,
12501 C_LBU = 12477,
12502 C_LD = 12478,
12503 C_LDSP = 12479,
12504 C_LH = 12480,
12505 C_LHU = 12481,
12506 C_LI = 12482,
12507 C_LI_HINT = 12483,
12508 C_LUI = 12484,
12509 C_LUI_HINT = 12485,
12510 C_LW = 12486,
12511 C_LWSP = 12487,
12512 C_MOP1 = 12488,
12513 C_MOP11 = 12489,
12514 C_MOP13 = 12490,
12515 C_MOP15 = 12491,
12516 C_MOP3 = 12492,
12517 C_MOP5 = 12493,
12518 C_MOP7 = 12494,
12519 C_MOP9 = 12495,
12520 C_MUL = 12496,
12521 C_MV = 12497,
12522 C_MV_HINT = 12498,
12523 C_NOP = 12499,
12524 C_NOP_HINT = 12500,
12525 C_NOT = 12501,
12526 C_OR = 12502,
12527 C_SB = 12503,
12528 C_SD = 12504,
12529 C_SDSP = 12505,
12530 C_SEXT_B = 12506,
12531 C_SEXT_H = 12507,
12532 C_SH = 12508,
12533 C_SLLI = 12509,
12534 C_SLLI64_HINT = 12510,
12535 C_SLLI_HINT = 12511,
12536 C_SRAI = 12512,
12537 C_SRAI64_HINT = 12513,
12538 C_SRLI = 12514,
12539 C_SRLI64_HINT = 12515,
12540 C_SSPOPCHK = 12516,
12541 C_SSPUSH = 12517,
12542 C_SUB = 12518,
12543 C_SUBW = 12519,
12544 C_SW = 12520,
12545 C_SWSP = 12521,
12546 C_UNIMP = 12522,
12547 C_XOR = 12523,
12548 C_ZEXT_B = 12524,
12549 C_ZEXT_H = 12525,
12550 C_ZEXT_W = 12526,
12551 DIV = 12527,
12552 DIVU = 12528,
12553 DIVUW = 12529,
12554 DIVW = 12530,
12555 DRET = 12531,
12556 EBREAK = 12532,
12557 ECALL = 12533,
12558 FADD_D = 12534,
12559 FADD_D_IN32X = 12535,
12560 FADD_D_INX = 12536,
12561 FADD_H = 12537,
12562 FADD_H_INX = 12538,
12563 FADD_S = 12539,
12564 FADD_S_INX = 12540,
12565 FCLASS_D = 12541,
12566 FCLASS_D_IN32X = 12542,
12567 FCLASS_D_INX = 12543,
12568 FCLASS_H = 12544,
12569 FCLASS_H_INX = 12545,
12570 FCLASS_S = 12546,
12571 FCLASS_S_INX = 12547,
12572 FCVTMOD_W_D = 12548,
12573 FCVT_BF16_S = 12549,
12574 FCVT_D_H = 12550,
12575 FCVT_D_H_IN32X = 12551,
12576 FCVT_D_H_INX = 12552,
12577 FCVT_D_L = 12553,
12578 FCVT_D_LU = 12554,
12579 FCVT_D_LU_INX = 12555,
12580 FCVT_D_L_INX = 12556,
12581 FCVT_D_S = 12557,
12582 FCVT_D_S_IN32X = 12558,
12583 FCVT_D_S_INX = 12559,
12584 FCVT_D_W = 12560,
12585 FCVT_D_WU = 12561,
12586 FCVT_D_WU_IN32X = 12562,
12587 FCVT_D_WU_INX = 12563,
12588 FCVT_D_W_IN32X = 12564,
12589 FCVT_D_W_INX = 12565,
12590 FCVT_H_D = 12566,
12591 FCVT_H_D_IN32X = 12567,
12592 FCVT_H_D_INX = 12568,
12593 FCVT_H_L = 12569,
12594 FCVT_H_LU = 12570,
12595 FCVT_H_LU_INX = 12571,
12596 FCVT_H_L_INX = 12572,
12597 FCVT_H_S = 12573,
12598 FCVT_H_S_INX = 12574,
12599 FCVT_H_W = 12575,
12600 FCVT_H_WU = 12576,
12601 FCVT_H_WU_INX = 12577,
12602 FCVT_H_W_INX = 12578,
12603 FCVT_LU_D = 12579,
12604 FCVT_LU_D_INX = 12580,
12605 FCVT_LU_H = 12581,
12606 FCVT_LU_H_INX = 12582,
12607 FCVT_LU_S = 12583,
12608 FCVT_LU_S_INX = 12584,
12609 FCVT_L_D = 12585,
12610 FCVT_L_D_INX = 12586,
12611 FCVT_L_H = 12587,
12612 FCVT_L_H_INX = 12588,
12613 FCVT_L_S = 12589,
12614 FCVT_L_S_INX = 12590,
12615 FCVT_S_BF16 = 12591,
12616 FCVT_S_D = 12592,
12617 FCVT_S_D_IN32X = 12593,
12618 FCVT_S_D_INX = 12594,
12619 FCVT_S_H = 12595,
12620 FCVT_S_H_INX = 12596,
12621 FCVT_S_L = 12597,
12622 FCVT_S_LU = 12598,
12623 FCVT_S_LU_INX = 12599,
12624 FCVT_S_L_INX = 12600,
12625 FCVT_S_W = 12601,
12626 FCVT_S_WU = 12602,
12627 FCVT_S_WU_INX = 12603,
12628 FCVT_S_W_INX = 12604,
12629 FCVT_WU_D = 12605,
12630 FCVT_WU_D_IN32X = 12606,
12631 FCVT_WU_D_INX = 12607,
12632 FCVT_WU_H = 12608,
12633 FCVT_WU_H_INX = 12609,
12634 FCVT_WU_S = 12610,
12635 FCVT_WU_S_INX = 12611,
12636 FCVT_W_D = 12612,
12637 FCVT_W_D_IN32X = 12613,
12638 FCVT_W_D_INX = 12614,
12639 FCVT_W_H = 12615,
12640 FCVT_W_H_INX = 12616,
12641 FCVT_W_S = 12617,
12642 FCVT_W_S_INX = 12618,
12643 FDIV_D = 12619,
12644 FDIV_D_IN32X = 12620,
12645 FDIV_D_INX = 12621,
12646 FDIV_H = 12622,
12647 FDIV_H_INX = 12623,
12648 FDIV_S = 12624,
12649 FDIV_S_INX = 12625,
12650 FENCE = 12626,
12651 FENCE_I = 12627,
12652 FENCE_TSO = 12628,
12653 FEQ_D = 12629,
12654 FEQ_D_IN32X = 12630,
12655 FEQ_D_INX = 12631,
12656 FEQ_H = 12632,
12657 FEQ_H_INX = 12633,
12658 FEQ_S = 12634,
12659 FEQ_S_INX = 12635,
12660 FLD = 12636,
12661 FLEQ_D = 12637,
12662 FLEQ_H = 12638,
12663 FLEQ_S = 12639,
12664 FLE_D = 12640,
12665 FLE_D_IN32X = 12641,
12666 FLE_D_INX = 12642,
12667 FLE_H = 12643,
12668 FLE_H_INX = 12644,
12669 FLE_S = 12645,
12670 FLE_S_INX = 12646,
12671 FLH = 12647,
12672 FLI_D = 12648,
12673 FLI_H = 12649,
12674 FLI_S = 12650,
12675 FLTQ_D = 12651,
12676 FLTQ_H = 12652,
12677 FLTQ_S = 12653,
12678 FLT_D = 12654,
12679 FLT_D_IN32X = 12655,
12680 FLT_D_INX = 12656,
12681 FLT_H = 12657,
12682 FLT_H_INX = 12658,
12683 FLT_S = 12659,
12684 FLT_S_INX = 12660,
12685 FLW = 12661,
12686 FMADD_D = 12662,
12687 FMADD_D_IN32X = 12663,
12688 FMADD_D_INX = 12664,
12689 FMADD_H = 12665,
12690 FMADD_H_INX = 12666,
12691 FMADD_S = 12667,
12692 FMADD_S_INX = 12668,
12693 FMAXM_D = 12669,
12694 FMAXM_H = 12670,
12695 FMAXM_S = 12671,
12696 FMAX_D = 12672,
12697 FMAX_D_IN32X = 12673,
12698 FMAX_D_INX = 12674,
12699 FMAX_H = 12675,
12700 FMAX_H_INX = 12676,
12701 FMAX_S = 12677,
12702 FMAX_S_INX = 12678,
12703 FMINM_D = 12679,
12704 FMINM_H = 12680,
12705 FMINM_S = 12681,
12706 FMIN_D = 12682,
12707 FMIN_D_IN32X = 12683,
12708 FMIN_D_INX = 12684,
12709 FMIN_H = 12685,
12710 FMIN_H_INX = 12686,
12711 FMIN_S = 12687,
12712 FMIN_S_INX = 12688,
12713 FMSUB_D = 12689,
12714 FMSUB_D_IN32X = 12690,
12715 FMSUB_D_INX = 12691,
12716 FMSUB_H = 12692,
12717 FMSUB_H_INX = 12693,
12718 FMSUB_S = 12694,
12719 FMSUB_S_INX = 12695,
12720 FMUL_D = 12696,
12721 FMUL_D_IN32X = 12697,
12722 FMUL_D_INX = 12698,
12723 FMUL_H = 12699,
12724 FMUL_H_INX = 12700,
12725 FMUL_S = 12701,
12726 FMUL_S_INX = 12702,
12727 FMVH_X_D = 12703,
12728 FMVP_D_X = 12704,
12729 FMV_D_X = 12705,
12730 FMV_H_X = 12706,
12731 FMV_W_X = 12707,
12732 FMV_X_D = 12708,
12733 FMV_X_H = 12709,
12734 FMV_X_W = 12710,
12735 FMV_X_W_FPR64 = 12711,
12736 FNMADD_D = 12712,
12737 FNMADD_D_IN32X = 12713,
12738 FNMADD_D_INX = 12714,
12739 FNMADD_H = 12715,
12740 FNMADD_H_INX = 12716,
12741 FNMADD_S = 12717,
12742 FNMADD_S_INX = 12718,
12743 FNMSUB_D = 12719,
12744 FNMSUB_D_IN32X = 12720,
12745 FNMSUB_D_INX = 12721,
12746 FNMSUB_H = 12722,
12747 FNMSUB_H_INX = 12723,
12748 FNMSUB_S = 12724,
12749 FNMSUB_S_INX = 12725,
12750 FROUNDNX_D = 12726,
12751 FROUNDNX_H = 12727,
12752 FROUNDNX_S = 12728,
12753 FROUND_D = 12729,
12754 FROUND_H = 12730,
12755 FROUND_S = 12731,
12756 FSD = 12732,
12757 FSGNJN_D = 12733,
12758 FSGNJN_D_IN32X = 12734,
12759 FSGNJN_D_INX = 12735,
12760 FSGNJN_H = 12736,
12761 FSGNJN_H_INX = 12737,
12762 FSGNJN_S = 12738,
12763 FSGNJN_S_INX = 12739,
12764 FSGNJX_D = 12740,
12765 FSGNJX_D_IN32X = 12741,
12766 FSGNJX_D_INX = 12742,
12767 FSGNJX_H = 12743,
12768 FSGNJX_H_INX = 12744,
12769 FSGNJX_S = 12745,
12770 FSGNJX_S_INX = 12746,
12771 FSGNJ_D = 12747,
12772 FSGNJ_D_IN32X = 12748,
12773 FSGNJ_D_INX = 12749,
12774 FSGNJ_H = 12750,
12775 FSGNJ_H_INX = 12751,
12776 FSGNJ_S = 12752,
12777 FSGNJ_S_INX = 12753,
12778 FSH = 12754,
12779 FSQRT_D = 12755,
12780 FSQRT_D_IN32X = 12756,
12781 FSQRT_D_INX = 12757,
12782 FSQRT_H = 12758,
12783 FSQRT_H_INX = 12759,
12784 FSQRT_S = 12760,
12785 FSQRT_S_INX = 12761,
12786 FSUB_D = 12762,
12787 FSUB_D_IN32X = 12763,
12788 FSUB_D_INX = 12764,
12789 FSUB_H = 12765,
12790 FSUB_H_INX = 12766,
12791 FSUB_S = 12767,
12792 FSUB_S_INX = 12768,
12793 FSW = 12769,
12794 HFENCE_GVMA = 12770,
12795 HFENCE_VVMA = 12771,
12796 HINVAL_GVMA = 12772,
12797 HINVAL_VVMA = 12773,
12798 HLVX_HU = 12774,
12799 HLVX_WU = 12775,
12800 HLV_B = 12776,
12801 HLV_BU = 12777,
12802 HLV_D = 12778,
12803 HLV_H = 12779,
12804 HLV_HU = 12780,
12805 HLV_W = 12781,
12806 HLV_WU = 12782,
12807 HSV_B = 12783,
12808 HSV_D = 12784,
12809 HSV_H = 12785,
12810 HSV_W = 12786,
12811 Insn16 = 12787,
12812 Insn32 = 12788,
12813 InsnB = 12789,
12814 InsnCA = 12790,
12815 InsnCB = 12791,
12816 InsnCI = 12792,
12817 InsnCIW = 12793,
12818 InsnCJ = 12794,
12819 InsnCL = 12795,
12820 InsnCR = 12796,
12821 InsnCS = 12797,
12822 InsnCSS = 12798,
12823 InsnI = 12799,
12824 InsnI_Mem = 12800,
12825 InsnJ = 12801,
12826 InsnR = 12802,
12827 InsnR4 = 12803,
12828 InsnS = 12804,
12829 InsnU = 12805,
12830 JAL = 12806,
12831 JALR = 12807,
12832 LB = 12808,
12833 LBU = 12809,
12834 LB_AQ = 12810,
12835 LB_AQ_RL = 12811,
12836 LD = 12812,
12837 LD_AQ = 12813,
12838 LD_AQ_RL = 12814,
12839 LH = 12815,
12840 LHU = 12816,
12841 LH_AQ = 12817,
12842 LH_AQ_RL = 12818,
12843 LR_D = 12819,
12844 LR_D_AQ = 12820,
12845 LR_D_AQ_RL = 12821,
12846 LR_D_RL = 12822,
12847 LR_W = 12823,
12848 LR_W_AQ = 12824,
12849 LR_W_AQ_RL = 12825,
12850 LR_W_RL = 12826,
12851 LUI = 12827,
12852 LW = 12828,
12853 LWU = 12829,
12854 LW_AQ = 12830,
12855 LW_AQ_RL = 12831,
12856 MAX = 12832,
12857 MAXU = 12833,
12858 MIN = 12834,
12859 MINU = 12835,
12860 MOPR0 = 12836,
12861 MOPR1 = 12837,
12862 MOPR10 = 12838,
12863 MOPR11 = 12839,
12864 MOPR12 = 12840,
12865 MOPR13 = 12841,
12866 MOPR14 = 12842,
12867 MOPR15 = 12843,
12868 MOPR16 = 12844,
12869 MOPR17 = 12845,
12870 MOPR18 = 12846,
12871 MOPR19 = 12847,
12872 MOPR2 = 12848,
12873 MOPR20 = 12849,
12874 MOPR21 = 12850,
12875 MOPR22 = 12851,
12876 MOPR23 = 12852,
12877 MOPR24 = 12853,
12878 MOPR25 = 12854,
12879 MOPR26 = 12855,
12880 MOPR27 = 12856,
12881 MOPR28 = 12857,
12882 MOPR29 = 12858,
12883 MOPR3 = 12859,
12884 MOPR30 = 12860,
12885 MOPR31 = 12861,
12886 MOPR4 = 12862,
12887 MOPR5 = 12863,
12888 MOPR6 = 12864,
12889 MOPR7 = 12865,
12890 MOPR8 = 12866,
12891 MOPR9 = 12867,
12892 MOPRR0 = 12868,
12893 MOPRR1 = 12869,
12894 MOPRR2 = 12870,
12895 MOPRR3 = 12871,
12896 MOPRR4 = 12872,
12897 MOPRR5 = 12873,
12898 MOPRR6 = 12874,
12899 MOPRR7 = 12875,
12900 MRET = 12876,
12901 MUL = 12877,
12902 MULH = 12878,
12903 MULHSU = 12879,
12904 MULHU = 12880,
12905 MULW = 12881,
12906 OR = 12882,
12907 ORC_B = 12883,
12908 ORI = 12884,
12909 ORN = 12885,
12910 PACK = 12886,
12911 PACKH = 12887,
12912 PACKW = 12888,
12913 PREFETCH_I = 12889,
12914 PREFETCH_R = 12890,
12915 PREFETCH_W = 12891,
12916 QK_C_LBU = 12892,
12917 QK_C_LBUSP = 12893,
12918 QK_C_LHU = 12894,
12919 QK_C_LHUSP = 12895,
12920 QK_C_SB = 12896,
12921 QK_C_SBSP = 12897,
12922 QK_C_SH = 12898,
12923 QK_C_SHSP = 12899,
12924 REM = 12900,
12925 REMU = 12901,
12926 REMUW = 12902,
12927 REMW = 12903,
12928 REV8_RV32 = 12904,
12929 REV8_RV64 = 12905,
12930 ROL = 12906,
12931 ROLW = 12907,
12932 ROR = 12908,
12933 RORI = 12909,
12934 RORIW = 12910,
12935 RORW = 12911,
12936 SB = 12912,
12937 SB_AQ_RL = 12913,
12938 SB_RL = 12914,
12939 SC_D = 12915,
12940 SC_D_AQ = 12916,
12941 SC_D_AQ_RL = 12917,
12942 SC_D_RL = 12918,
12943 SC_W = 12919,
12944 SC_W_AQ = 12920,
12945 SC_W_AQ_RL = 12921,
12946 SC_W_RL = 12922,
12947 SD = 12923,
12948 SD_AQ_RL = 12924,
12949 SD_RL = 12925,
12950 SEXT_B = 12926,
12951 SEXT_H = 12927,
12952 SFENCE_INVAL_IR = 12928,
12953 SFENCE_VMA = 12929,
12954 SFENCE_W_INVAL = 12930,
12955 SF_CDISCARD_D_L1 = 12931,
12956 SF_CEASE = 12932,
12957 SF_CFLUSH_D_L1 = 12933,
12958 SH = 12934,
12959 SH1ADD = 12935,
12960 SH1ADD_UW = 12936,
12961 SH2ADD = 12937,
12962 SH2ADD_UW = 12938,
12963 SH3ADD = 12939,
12964 SH3ADD_UW = 12940,
12965 SHA256SIG0 = 12941,
12966 SHA256SIG1 = 12942,
12967 SHA256SUM0 = 12943,
12968 SHA256SUM1 = 12944,
12969 SHA512SIG0 = 12945,
12970 SHA512SIG0H = 12946,
12971 SHA512SIG0L = 12947,
12972 SHA512SIG1 = 12948,
12973 SHA512SIG1H = 12949,
12974 SHA512SIG1L = 12950,
12975 SHA512SUM0 = 12951,
12976 SHA512SUM0R = 12952,
12977 SHA512SUM1 = 12953,
12978 SHA512SUM1R = 12954,
12979 SH_AQ_RL = 12955,
12980 SH_RL = 12956,
12981 SINVAL_VMA = 12957,
12982 SLL = 12958,
12983 SLLI = 12959,
12984 SLLIW = 12960,
12985 SLLI_UW = 12961,
12986 SLLW = 12962,
12987 SLT = 12963,
12988 SLTI = 12964,
12989 SLTIU = 12965,
12990 SLTU = 12966,
12991 SM3P0 = 12967,
12992 SM3P1 = 12968,
12993 SM4ED = 12969,
12994 SM4KS = 12970,
12995 SRA = 12971,
12996 SRAI = 12972,
12997 SRAIW = 12973,
12998 SRAW = 12974,
12999 SRET = 12975,
13000 SRL = 12976,
13001 SRLI = 12977,
13002 SRLIW = 12978,
13003 SRLW = 12979,
13004 SSAMOSWAP_D = 12980,
13005 SSAMOSWAP_D_AQ = 12981,
13006 SSAMOSWAP_D_AQ_RL = 12982,
13007 SSAMOSWAP_D_RL = 12983,
13008 SSAMOSWAP_W = 12984,
13009 SSAMOSWAP_W_AQ = 12985,
13010 SSAMOSWAP_W_AQ_RL = 12986,
13011 SSAMOSWAP_W_RL = 12987,
13012 SSPOPCHK = 12988,
13013 SSPUSH = 12989,
13014 SSRDP = 12990,
13015 SUB = 12991,
13016 SUBW = 12992,
13017 SW = 12993,
13018 SW_AQ_RL = 12994,
13019 SW_RL = 12995,
13020 THVdotVMAQASU_VV = 12996,
13021 THVdotVMAQASU_VX = 12997,
13022 THVdotVMAQAUS_VX = 12998,
13023 THVdotVMAQAU_VV = 12999,
13024 THVdotVMAQAU_VX = 13000,
13025 THVdotVMAQA_VV = 13001,
13026 THVdotVMAQA_VX = 13002,
13027 TH_ADDSL = 13003,
13028 TH_DCACHE_CALL = 13004,
13029 TH_DCACHE_CIALL = 13005,
13030 TH_DCACHE_CIPA = 13006,
13031 TH_DCACHE_CISW = 13007,
13032 TH_DCACHE_CIVA = 13008,
13033 TH_DCACHE_CPA = 13009,
13034 TH_DCACHE_CPAL1 = 13010,
13035 TH_DCACHE_CSW = 13011,
13036 TH_DCACHE_CVA = 13012,
13037 TH_DCACHE_CVAL1 = 13013,
13038 TH_DCACHE_IALL = 13014,
13039 TH_DCACHE_IPA = 13015,
13040 TH_DCACHE_ISW = 13016,
13041 TH_DCACHE_IVA = 13017,
13042 TH_EXT = 13018,
13043 TH_EXTU = 13019,
13044 TH_FF0 = 13020,
13045 TH_FF1 = 13021,
13046 TH_FLRD = 13022,
13047 TH_FLRW = 13023,
13048 TH_FLURD = 13024,
13049 TH_FLURW = 13025,
13050 TH_FSRD = 13026,
13051 TH_FSRW = 13027,
13052 TH_FSURD = 13028,
13053 TH_FSURW = 13029,
13054 TH_ICACHE_IALL = 13030,
13055 TH_ICACHE_IALLS = 13031,
13056 TH_ICACHE_IPA = 13032,
13057 TH_ICACHE_IVA = 13033,
13058 TH_L2CACHE_CALL = 13034,
13059 TH_L2CACHE_CIALL = 13035,
13060 TH_L2CACHE_IALL = 13036,
13061 TH_LBIA = 13037,
13062 TH_LBIB = 13038,
13063 TH_LBUIA = 13039,
13064 TH_LBUIB = 13040,
13065 TH_LDD = 13041,
13066 TH_LDIA = 13042,
13067 TH_LDIB = 13043,
13068 TH_LHIA = 13044,
13069 TH_LHIB = 13045,
13070 TH_LHUIA = 13046,
13071 TH_LHUIB = 13047,
13072 TH_LRB = 13048,
13073 TH_LRBU = 13049,
13074 TH_LRD = 13050,
13075 TH_LRH = 13051,
13076 TH_LRHU = 13052,
13077 TH_LRW = 13053,
13078 TH_LRWU = 13054,
13079 TH_LURB = 13055,
13080 TH_LURBU = 13056,
13081 TH_LURD = 13057,
13082 TH_LURH = 13058,
13083 TH_LURHU = 13059,
13084 TH_LURW = 13060,
13085 TH_LURWU = 13061,
13086 TH_LWD = 13062,
13087 TH_LWIA = 13063,
13088 TH_LWIB = 13064,
13089 TH_LWUD = 13065,
13090 TH_LWUIA = 13066,
13091 TH_LWUIB = 13067,
13092 TH_MULA = 13068,
13093 TH_MULAH = 13069,
13094 TH_MULAW = 13070,
13095 TH_MULS = 13071,
13096 TH_MULSH = 13072,
13097 TH_MULSW = 13073,
13098 TH_MVEQZ = 13074,
13099 TH_MVNEZ = 13075,
13100 TH_REV = 13076,
13101 TH_REVW = 13077,
13102 TH_SBIA = 13078,
13103 TH_SBIB = 13079,
13104 TH_SDD = 13080,
13105 TH_SDIA = 13081,
13106 TH_SDIB = 13082,
13107 TH_SFENCE_VMAS = 13083,
13108 TH_SHIA = 13084,
13109 TH_SHIB = 13085,
13110 TH_SRB = 13086,
13111 TH_SRD = 13087,
13112 TH_SRH = 13088,
13113 TH_SRRI = 13089,
13114 TH_SRRIW = 13090,
13115 TH_SRW = 13091,
13116 TH_SURB = 13092,
13117 TH_SURD = 13093,
13118 TH_SURH = 13094,
13119 TH_SURW = 13095,
13120 TH_SWD = 13096,
13121 TH_SWIA = 13097,
13122 TH_SWIB = 13098,
13123 TH_SYNC = 13099,
13124 TH_SYNC_I = 13100,
13125 TH_SYNC_IS = 13101,
13126 TH_SYNC_S = 13102,
13127 TH_TST = 13103,
13128 TH_TSTNBZ = 13104,
13129 UNIMP = 13105,
13130 UNZIP_RV32 = 13106,
13131 VAADDU_VV = 13107,
13132 VAADDU_VX = 13108,
13133 VAADD_VV = 13109,
13134 VAADD_VX = 13110,
13135 VADC_VIM = 13111,
13136 VADC_VVM = 13112,
13137 VADC_VXM = 13113,
13138 VADD_VI = 13114,
13139 VADD_VV = 13115,
13140 VADD_VX = 13116,
13141 VAESDF_VS = 13117,
13142 VAESDF_VV = 13118,
13143 VAESDM_VS = 13119,
13144 VAESDM_VV = 13120,
13145 VAESEF_VS = 13121,
13146 VAESEF_VV = 13122,
13147 VAESEM_VS = 13123,
13148 VAESEM_VV = 13124,
13149 VAESKF1_VI = 13125,
13150 VAESKF2_VI = 13126,
13151 VAESZ_VS = 13127,
13152 VANDN_VV = 13128,
13153 VANDN_VX = 13129,
13154 VAND_VI = 13130,
13155 VAND_VV = 13131,
13156 VAND_VX = 13132,
13157 VASUBU_VV = 13133,
13158 VASUBU_VX = 13134,
13159 VASUB_VV = 13135,
13160 VASUB_VX = 13136,
13161 VBREV8_V = 13137,
13162 VBREV_V = 13138,
13163 VCLMULH_VV = 13139,
13164 VCLMULH_VX = 13140,
13165 VCLMUL_VV = 13141,
13166 VCLMUL_VX = 13142,
13167 VCLZ_V = 13143,
13168 VCOMPRESS_VM = 13144,
13169 VCPOP_M = 13145,
13170 VCPOP_V = 13146,
13171 VCTZ_V = 13147,
13172 VC_FV = 13148,
13173 VC_FVV = 13149,
13174 VC_FVW = 13150,
13175 VC_I = 13151,
13176 VC_IV = 13152,
13177 VC_IVV = 13153,
13178 VC_IVW = 13154,
13179 VC_VV = 13155,
13180 VC_VVV = 13156,
13181 VC_VVW = 13157,
13182 VC_V_FV = 13158,
13183 VC_V_FVV = 13159,
13184 VC_V_FVW = 13160,
13185 VC_V_I = 13161,
13186 VC_V_IV = 13162,
13187 VC_V_IVV = 13163,
13188 VC_V_IVW = 13164,
13189 VC_V_VV = 13165,
13190 VC_V_VVV = 13166,
13191 VC_V_VVW = 13167,
13192 VC_V_X = 13168,
13193 VC_V_XV = 13169,
13194 VC_V_XVV = 13170,
13195 VC_V_XVW = 13171,
13196 VC_X = 13172,
13197 VC_XV = 13173,
13198 VC_XVV = 13174,
13199 VC_XVW = 13175,
13200 VDIVU_VV = 13176,
13201 VDIVU_VX = 13177,
13202 VDIV_VV = 13178,
13203 VDIV_VX = 13179,
13204 VFADD_VF = 13180,
13205 VFADD_VV = 13181,
13206 VFCLASS_V = 13182,
13207 VFCVT_F_XU_V = 13183,
13208 VFCVT_F_X_V = 13184,
13209 VFCVT_RTZ_XU_F_V = 13185,
13210 VFCVT_RTZ_X_F_V = 13186,
13211 VFCVT_XU_F_V = 13187,
13212 VFCVT_X_F_V = 13188,
13213 VFDIV_VF = 13189,
13214 VFDIV_VV = 13190,
13215 VFIRST_M = 13191,
13216 VFMACC_VF = 13192,
13217 VFMACC_VV = 13193,
13218 VFMADD_VF = 13194,
13219 VFMADD_VV = 13195,
13220 VFMAX_VF = 13196,
13221 VFMAX_VV = 13197,
13222 VFMERGE_VFM = 13198,
13223 VFMIN_VF = 13199,
13224 VFMIN_VV = 13200,
13225 VFMSAC_VF = 13201,
13226 VFMSAC_VV = 13202,
13227 VFMSUB_VF = 13203,
13228 VFMSUB_VV = 13204,
13229 VFMUL_VF = 13205,
13230 VFMUL_VV = 13206,
13231 VFMV_F_S = 13207,
13232 VFMV_S_F = 13208,
13233 VFMV_V_F = 13209,
13234 VFNCVTBF16_F_F_W = 13210,
13235 VFNCVT_F_F_W = 13211,
13236 VFNCVT_F_XU_W = 13212,
13237 VFNCVT_F_X_W = 13213,
13238 VFNCVT_ROD_F_F_W = 13214,
13239 VFNCVT_RTZ_XU_F_W = 13215,
13240 VFNCVT_RTZ_X_F_W = 13216,
13241 VFNCVT_XU_F_W = 13217,
13242 VFNCVT_X_F_W = 13218,
13243 VFNMACC_VF = 13219,
13244 VFNMACC_VV = 13220,
13245 VFNMADD_VF = 13221,
13246 VFNMADD_VV = 13222,
13247 VFNMSAC_VF = 13223,
13248 VFNMSAC_VV = 13224,
13249 VFNMSUB_VF = 13225,
13250 VFNMSUB_VV = 13226,
13251 VFNRCLIP_XU_F_QF = 13227,
13252 VFNRCLIP_X_F_QF = 13228,
13253 VFRDIV_VF = 13229,
13254 VFREC7_V = 13230,
13255 VFREDMAX_VS = 13231,
13256 VFREDMIN_VS = 13232,
13257 VFREDOSUM_VS = 13233,
13258 VFREDUSUM_VS = 13234,
13259 VFRSQRT7_V = 13235,
13260 VFRSUB_VF = 13236,
13261 VFSGNJN_VF = 13237,
13262 VFSGNJN_VV = 13238,
13263 VFSGNJX_VF = 13239,
13264 VFSGNJX_VV = 13240,
13265 VFSGNJ_VF = 13241,
13266 VFSGNJ_VV = 13242,
13267 VFSLIDE1DOWN_VF = 13243,
13268 VFSLIDE1UP_VF = 13244,
13269 VFSQRT_V = 13245,
13270 VFSUB_VF = 13246,
13271 VFSUB_VV = 13247,
13272 VFWADD_VF = 13248,
13273 VFWADD_VV = 13249,
13274 VFWADD_WF = 13250,
13275 VFWADD_WV = 13251,
13276 VFWCVTBF16_F_F_V = 13252,
13277 VFWCVT_F_F_V = 13253,
13278 VFWCVT_F_XU_V = 13254,
13279 VFWCVT_F_X_V = 13255,
13280 VFWCVT_RTZ_XU_F_V = 13256,
13281 VFWCVT_RTZ_X_F_V = 13257,
13282 VFWCVT_XU_F_V = 13258,
13283 VFWCVT_X_F_V = 13259,
13284 VFWMACCBF16_VF = 13260,
13285 VFWMACCBF16_VV = 13261,
13286 VFWMACC_4x4x4 = 13262,
13287 VFWMACC_VF = 13263,
13288 VFWMACC_VV = 13264,
13289 VFWMSAC_VF = 13265,
13290 VFWMSAC_VV = 13266,
13291 VFWMUL_VF = 13267,
13292 VFWMUL_VV = 13268,
13293 VFWNMACC_VF = 13269,
13294 VFWNMACC_VV = 13270,
13295 VFWNMSAC_VF = 13271,
13296 VFWNMSAC_VV = 13272,
13297 VFWREDOSUM_VS = 13273,
13298 VFWREDUSUM_VS = 13274,
13299 VFWSUB_VF = 13275,
13300 VFWSUB_VV = 13276,
13301 VFWSUB_WF = 13277,
13302 VFWSUB_WV = 13278,
13303 VGHSH_VV = 13279,
13304 VGMUL_VV = 13280,
13305 VID_V = 13281,
13306 VIOTA_M = 13282,
13307 VL1RE16_V = 13283,
13308 VL1RE32_V = 13284,
13309 VL1RE64_V = 13285,
13310 VL1RE8_V = 13286,
13311 VL2RE16_V = 13287,
13312 VL2RE32_V = 13288,
13313 VL2RE64_V = 13289,
13314 VL2RE8_V = 13290,
13315 VL4RE16_V = 13291,
13316 VL4RE32_V = 13292,
13317 VL4RE64_V = 13293,
13318 VL4RE8_V = 13294,
13319 VL8RE16_V = 13295,
13320 VL8RE32_V = 13296,
13321 VL8RE64_V = 13297,
13322 VL8RE8_V = 13298,
13323 VLE16FF_V = 13299,
13324 VLE16_V = 13300,
13325 VLE32FF_V = 13301,
13326 VLE32_V = 13302,
13327 VLE64FF_V = 13303,
13328 VLE64_V = 13304,
13329 VLE8FF_V = 13305,
13330 VLE8_V = 13306,
13331 VLM_V = 13307,
13332 VLOXEI16_V = 13308,
13333 VLOXEI32_V = 13309,
13334 VLOXEI64_V = 13310,
13335 VLOXEI8_V = 13311,
13336 VLOXSEG2EI16_V = 13312,
13337 VLOXSEG2EI32_V = 13313,
13338 VLOXSEG2EI64_V = 13314,
13339 VLOXSEG2EI8_V = 13315,
13340 VLOXSEG3EI16_V = 13316,
13341 VLOXSEG3EI32_V = 13317,
13342 VLOXSEG3EI64_V = 13318,
13343 VLOXSEG3EI8_V = 13319,
13344 VLOXSEG4EI16_V = 13320,
13345 VLOXSEG4EI32_V = 13321,
13346 VLOXSEG4EI64_V = 13322,
13347 VLOXSEG4EI8_V = 13323,
13348 VLOXSEG5EI16_V = 13324,
13349 VLOXSEG5EI32_V = 13325,
13350 VLOXSEG5EI64_V = 13326,
13351 VLOXSEG5EI8_V = 13327,
13352 VLOXSEG6EI16_V = 13328,
13353 VLOXSEG6EI32_V = 13329,
13354 VLOXSEG6EI64_V = 13330,
13355 VLOXSEG6EI8_V = 13331,
13356 VLOXSEG7EI16_V = 13332,
13357 VLOXSEG7EI32_V = 13333,
13358 VLOXSEG7EI64_V = 13334,
13359 VLOXSEG7EI8_V = 13335,
13360 VLOXSEG8EI16_V = 13336,
13361 VLOXSEG8EI32_V = 13337,
13362 VLOXSEG8EI64_V = 13338,
13363 VLOXSEG8EI8_V = 13339,
13364 VLSE16_V = 13340,
13365 VLSE32_V = 13341,
13366 VLSE64_V = 13342,
13367 VLSE8_V = 13343,
13368 VLSEG2E16FF_V = 13344,
13369 VLSEG2E16_V = 13345,
13370 VLSEG2E32FF_V = 13346,
13371 VLSEG2E32_V = 13347,
13372 VLSEG2E64FF_V = 13348,
13373 VLSEG2E64_V = 13349,
13374 VLSEG2E8FF_V = 13350,
13375 VLSEG2E8_V = 13351,
13376 VLSEG3E16FF_V = 13352,
13377 VLSEG3E16_V = 13353,
13378 VLSEG3E32FF_V = 13354,
13379 VLSEG3E32_V = 13355,
13380 VLSEG3E64FF_V = 13356,
13381 VLSEG3E64_V = 13357,
13382 VLSEG3E8FF_V = 13358,
13383 VLSEG3E8_V = 13359,
13384 VLSEG4E16FF_V = 13360,
13385 VLSEG4E16_V = 13361,
13386 VLSEG4E32FF_V = 13362,
13387 VLSEG4E32_V = 13363,
13388 VLSEG4E64FF_V = 13364,
13389 VLSEG4E64_V = 13365,
13390 VLSEG4E8FF_V = 13366,
13391 VLSEG4E8_V = 13367,
13392 VLSEG5E16FF_V = 13368,
13393 VLSEG5E16_V = 13369,
13394 VLSEG5E32FF_V = 13370,
13395 VLSEG5E32_V = 13371,
13396 VLSEG5E64FF_V = 13372,
13397 VLSEG5E64_V = 13373,
13398 VLSEG5E8FF_V = 13374,
13399 VLSEG5E8_V = 13375,
13400 VLSEG6E16FF_V = 13376,
13401 VLSEG6E16_V = 13377,
13402 VLSEG6E32FF_V = 13378,
13403 VLSEG6E32_V = 13379,
13404 VLSEG6E64FF_V = 13380,
13405 VLSEG6E64_V = 13381,
13406 VLSEG6E8FF_V = 13382,
13407 VLSEG6E8_V = 13383,
13408 VLSEG7E16FF_V = 13384,
13409 VLSEG7E16_V = 13385,
13410 VLSEG7E32FF_V = 13386,
13411 VLSEG7E32_V = 13387,
13412 VLSEG7E64FF_V = 13388,
13413 VLSEG7E64_V = 13389,
13414 VLSEG7E8FF_V = 13390,
13415 VLSEG7E8_V = 13391,
13416 VLSEG8E16FF_V = 13392,
13417 VLSEG8E16_V = 13393,
13418 VLSEG8E32FF_V = 13394,
13419 VLSEG8E32_V = 13395,
13420 VLSEG8E64FF_V = 13396,
13421 VLSEG8E64_V = 13397,
13422 VLSEG8E8FF_V = 13398,
13423 VLSEG8E8_V = 13399,
13424 VLSSEG2E16_V = 13400,
13425 VLSSEG2E32_V = 13401,
13426 VLSSEG2E64_V = 13402,
13427 VLSSEG2E8_V = 13403,
13428 VLSSEG3E16_V = 13404,
13429 VLSSEG3E32_V = 13405,
13430 VLSSEG3E64_V = 13406,
13431 VLSSEG3E8_V = 13407,
13432 VLSSEG4E16_V = 13408,
13433 VLSSEG4E32_V = 13409,
13434 VLSSEG4E64_V = 13410,
13435 VLSSEG4E8_V = 13411,
13436 VLSSEG5E16_V = 13412,
13437 VLSSEG5E32_V = 13413,
13438 VLSSEG5E64_V = 13414,
13439 VLSSEG5E8_V = 13415,
13440 VLSSEG6E16_V = 13416,
13441 VLSSEG6E32_V = 13417,
13442 VLSSEG6E64_V = 13418,
13443 VLSSEG6E8_V = 13419,
13444 VLSSEG7E16_V = 13420,
13445 VLSSEG7E32_V = 13421,
13446 VLSSEG7E64_V = 13422,
13447 VLSSEG7E8_V = 13423,
13448 VLSSEG8E16_V = 13424,
13449 VLSSEG8E32_V = 13425,
13450 VLSSEG8E64_V = 13426,
13451 VLSSEG8E8_V = 13427,
13452 VLUXEI16_V = 13428,
13453 VLUXEI32_V = 13429,
13454 VLUXEI64_V = 13430,
13455 VLUXEI8_V = 13431,
13456 VLUXSEG2EI16_V = 13432,
13457 VLUXSEG2EI32_V = 13433,
13458 VLUXSEG2EI64_V = 13434,
13459 VLUXSEG2EI8_V = 13435,
13460 VLUXSEG3EI16_V = 13436,
13461 VLUXSEG3EI32_V = 13437,
13462 VLUXSEG3EI64_V = 13438,
13463 VLUXSEG3EI8_V = 13439,
13464 VLUXSEG4EI16_V = 13440,
13465 VLUXSEG4EI32_V = 13441,
13466 VLUXSEG4EI64_V = 13442,
13467 VLUXSEG4EI8_V = 13443,
13468 VLUXSEG5EI16_V = 13444,
13469 VLUXSEG5EI32_V = 13445,
13470 VLUXSEG5EI64_V = 13446,
13471 VLUXSEG5EI8_V = 13447,
13472 VLUXSEG6EI16_V = 13448,
13473 VLUXSEG6EI32_V = 13449,
13474 VLUXSEG6EI64_V = 13450,
13475 VLUXSEG6EI8_V = 13451,
13476 VLUXSEG7EI16_V = 13452,
13477 VLUXSEG7EI32_V = 13453,
13478 VLUXSEG7EI64_V = 13454,
13479 VLUXSEG7EI8_V = 13455,
13480 VLUXSEG8EI16_V = 13456,
13481 VLUXSEG8EI32_V = 13457,
13482 VLUXSEG8EI64_V = 13458,
13483 VLUXSEG8EI8_V = 13459,
13484 VMACC_VV = 13460,
13485 VMACC_VX = 13461,
13486 VMADC_VI = 13462,
13487 VMADC_VIM = 13463,
13488 VMADC_VV = 13464,
13489 VMADC_VVM = 13465,
13490 VMADC_VX = 13466,
13491 VMADC_VXM = 13467,
13492 VMADD_VV = 13468,
13493 VMADD_VX = 13469,
13494 VMANDN_MM = 13470,
13495 VMAND_MM = 13471,
13496 VMAXU_VV = 13472,
13497 VMAXU_VX = 13473,
13498 VMAX_VV = 13474,
13499 VMAX_VX = 13475,
13500 VMERGE_VIM = 13476,
13501 VMERGE_VVM = 13477,
13502 VMERGE_VXM = 13478,
13503 VMFEQ_VF = 13479,
13504 VMFEQ_VV = 13480,
13505 VMFGE_VF = 13481,
13506 VMFGT_VF = 13482,
13507 VMFLE_VF = 13483,
13508 VMFLE_VV = 13484,
13509 VMFLT_VF = 13485,
13510 VMFLT_VV = 13486,
13511 VMFNE_VF = 13487,
13512 VMFNE_VV = 13488,
13513 VMINU_VV = 13489,
13514 VMINU_VX = 13490,
13515 VMIN_VV = 13491,
13516 VMIN_VX = 13492,
13517 VMNAND_MM = 13493,
13518 VMNOR_MM = 13494,
13519 VMORN_MM = 13495,
13520 VMOR_MM = 13496,
13521 VMSBC_VV = 13497,
13522 VMSBC_VVM = 13498,
13523 VMSBC_VX = 13499,
13524 VMSBC_VXM = 13500,
13525 VMSBF_M = 13501,
13526 VMSEQ_VI = 13502,
13527 VMSEQ_VV = 13503,
13528 VMSEQ_VX = 13504,
13529 VMSGTU_VI = 13505,
13530 VMSGTU_VX = 13506,
13531 VMSGT_VI = 13507,
13532 VMSGT_VX = 13508,
13533 VMSIF_M = 13509,
13534 VMSLEU_VI = 13510,
13535 VMSLEU_VV = 13511,
13536 VMSLEU_VX = 13512,
13537 VMSLE_VI = 13513,
13538 VMSLE_VV = 13514,
13539 VMSLE_VX = 13515,
13540 VMSLTU_VV = 13516,
13541 VMSLTU_VX = 13517,
13542 VMSLT_VV = 13518,
13543 VMSLT_VX = 13519,
13544 VMSNE_VI = 13520,
13545 VMSNE_VV = 13521,
13546 VMSNE_VX = 13522,
13547 VMSOF_M = 13523,
13548 VMULHSU_VV = 13524,
13549 VMULHSU_VX = 13525,
13550 VMULHU_VV = 13526,
13551 VMULHU_VX = 13527,
13552 VMULH_VV = 13528,
13553 VMULH_VX = 13529,
13554 VMUL_VV = 13530,
13555 VMUL_VX = 13531,
13556 VMV1R_V = 13532,
13557 VMV2R_V = 13533,
13558 VMV4R_V = 13534,
13559 VMV8R_V = 13535,
13560 VMV_S_X = 13536,
13561 VMV_V_I = 13537,
13562 VMV_V_V = 13538,
13563 VMV_V_X = 13539,
13564 VMV_X_S = 13540,
13565 VMXNOR_MM = 13541,
13566 VMXOR_MM = 13542,
13567 VNCLIPU_WI = 13543,
13568 VNCLIPU_WV = 13544,
13569 VNCLIPU_WX = 13545,
13570 VNCLIP_WI = 13546,
13571 VNCLIP_WV = 13547,
13572 VNCLIP_WX = 13548,
13573 VNMSAC_VV = 13549,
13574 VNMSAC_VX = 13550,
13575 VNMSUB_VV = 13551,
13576 VNMSUB_VX = 13552,
13577 VNSRA_WI = 13553,
13578 VNSRA_WV = 13554,
13579 VNSRA_WX = 13555,
13580 VNSRL_WI = 13556,
13581 VNSRL_WV = 13557,
13582 VNSRL_WX = 13558,
13583 VOR_VI = 13559,
13584 VOR_VV = 13560,
13585 VOR_VX = 13561,
13586 VQMACCSU_2x8x2 = 13562,
13587 VQMACCSU_4x8x4 = 13563,
13588 VQMACCUS_2x8x2 = 13564,
13589 VQMACCUS_4x8x4 = 13565,
13590 VQMACCU_2x8x2 = 13566,
13591 VQMACCU_4x8x4 = 13567,
13592 VQMACC_2x8x2 = 13568,
13593 VQMACC_4x8x4 = 13569,
13594 VREDAND_VS = 13570,
13595 VREDMAXU_VS = 13571,
13596 VREDMAX_VS = 13572,
13597 VREDMINU_VS = 13573,
13598 VREDMIN_VS = 13574,
13599 VREDOR_VS = 13575,
13600 VREDSUM_VS = 13576,
13601 VREDXOR_VS = 13577,
13602 VREMU_VV = 13578,
13603 VREMU_VX = 13579,
13604 VREM_VV = 13580,
13605 VREM_VX = 13581,
13606 VREV8_V = 13582,
13607 VRGATHEREI16_VV = 13583,
13608 VRGATHER_VI = 13584,
13609 VRGATHER_VV = 13585,
13610 VRGATHER_VX = 13586,
13611 VROL_VV = 13587,
13612 VROL_VX = 13588,
13613 VROR_VI = 13589,
13614 VROR_VV = 13590,
13615 VROR_VX = 13591,
13616 VRSUB_VI = 13592,
13617 VRSUB_VX = 13593,
13618 VS1R_V = 13594,
13619 VS2R_V = 13595,
13620 VS4R_V = 13596,
13621 VS8R_V = 13597,
13622 VSADDU_VI = 13598,
13623 VSADDU_VV = 13599,
13624 VSADDU_VX = 13600,
13625 VSADD_VI = 13601,
13626 VSADD_VV = 13602,
13627 VSADD_VX = 13603,
13628 VSBC_VVM = 13604,
13629 VSBC_VXM = 13605,
13630 VSE16_V = 13606,
13631 VSE32_V = 13607,
13632 VSE64_V = 13608,
13633 VSE8_V = 13609,
13634 VSETIVLI = 13610,
13635 VSETVL = 13611,
13636 VSETVLI = 13612,
13637 VSEXT_VF2 = 13613,
13638 VSEXT_VF4 = 13614,
13639 VSEXT_VF8 = 13615,
13640 VSHA2CH_VV = 13616,
13641 VSHA2CL_VV = 13617,
13642 VSHA2MS_VV = 13618,
13643 VSLIDE1DOWN_VX = 13619,
13644 VSLIDE1UP_VX = 13620,
13645 VSLIDEDOWN_VI = 13621,
13646 VSLIDEDOWN_VX = 13622,
13647 VSLIDEUP_VI = 13623,
13648 VSLIDEUP_VX = 13624,
13649 VSLL_VI = 13625,
13650 VSLL_VV = 13626,
13651 VSLL_VX = 13627,
13652 VSM3C_VI = 13628,
13653 VSM3ME_VV = 13629,
13654 VSM4K_VI = 13630,
13655 VSM4R_VS = 13631,
13656 VSM4R_VV = 13632,
13657 VSMUL_VV = 13633,
13658 VSMUL_VX = 13634,
13659 VSM_V = 13635,
13660 VSOXEI16_V = 13636,
13661 VSOXEI32_V = 13637,
13662 VSOXEI64_V = 13638,
13663 VSOXEI8_V = 13639,
13664 VSOXSEG2EI16_V = 13640,
13665 VSOXSEG2EI32_V = 13641,
13666 VSOXSEG2EI64_V = 13642,
13667 VSOXSEG2EI8_V = 13643,
13668 VSOXSEG3EI16_V = 13644,
13669 VSOXSEG3EI32_V = 13645,
13670 VSOXSEG3EI64_V = 13646,
13671 VSOXSEG3EI8_V = 13647,
13672 VSOXSEG4EI16_V = 13648,
13673 VSOXSEG4EI32_V = 13649,
13674 VSOXSEG4EI64_V = 13650,
13675 VSOXSEG4EI8_V = 13651,
13676 VSOXSEG5EI16_V = 13652,
13677 VSOXSEG5EI32_V = 13653,
13678 VSOXSEG5EI64_V = 13654,
13679 VSOXSEG5EI8_V = 13655,
13680 VSOXSEG6EI16_V = 13656,
13681 VSOXSEG6EI32_V = 13657,
13682 VSOXSEG6EI64_V = 13658,
13683 VSOXSEG6EI8_V = 13659,
13684 VSOXSEG7EI16_V = 13660,
13685 VSOXSEG7EI32_V = 13661,
13686 VSOXSEG7EI64_V = 13662,
13687 VSOXSEG7EI8_V = 13663,
13688 VSOXSEG8EI16_V = 13664,
13689 VSOXSEG8EI32_V = 13665,
13690 VSOXSEG8EI64_V = 13666,
13691 VSOXSEG8EI8_V = 13667,
13692 VSRA_VI = 13668,
13693 VSRA_VV = 13669,
13694 VSRA_VX = 13670,
13695 VSRL_VI = 13671,
13696 VSRL_VV = 13672,
13697 VSRL_VX = 13673,
13698 VSSE16_V = 13674,
13699 VSSE32_V = 13675,
13700 VSSE64_V = 13676,
13701 VSSE8_V = 13677,
13702 VSSEG2E16_V = 13678,
13703 VSSEG2E32_V = 13679,
13704 VSSEG2E64_V = 13680,
13705 VSSEG2E8_V = 13681,
13706 VSSEG3E16_V = 13682,
13707 VSSEG3E32_V = 13683,
13708 VSSEG3E64_V = 13684,
13709 VSSEG3E8_V = 13685,
13710 VSSEG4E16_V = 13686,
13711 VSSEG4E32_V = 13687,
13712 VSSEG4E64_V = 13688,
13713 VSSEG4E8_V = 13689,
13714 VSSEG5E16_V = 13690,
13715 VSSEG5E32_V = 13691,
13716 VSSEG5E64_V = 13692,
13717 VSSEG5E8_V = 13693,
13718 VSSEG6E16_V = 13694,
13719 VSSEG6E32_V = 13695,
13720 VSSEG6E64_V = 13696,
13721 VSSEG6E8_V = 13697,
13722 VSSEG7E16_V = 13698,
13723 VSSEG7E32_V = 13699,
13724 VSSEG7E64_V = 13700,
13725 VSSEG7E8_V = 13701,
13726 VSSEG8E16_V = 13702,
13727 VSSEG8E32_V = 13703,
13728 VSSEG8E64_V = 13704,
13729 VSSEG8E8_V = 13705,
13730 VSSRA_VI = 13706,
13731 VSSRA_VV = 13707,
13732 VSSRA_VX = 13708,
13733 VSSRL_VI = 13709,
13734 VSSRL_VV = 13710,
13735 VSSRL_VX = 13711,
13736 VSSSEG2E16_V = 13712,
13737 VSSSEG2E32_V = 13713,
13738 VSSSEG2E64_V = 13714,
13739 VSSSEG2E8_V = 13715,
13740 VSSSEG3E16_V = 13716,
13741 VSSSEG3E32_V = 13717,
13742 VSSSEG3E64_V = 13718,
13743 VSSSEG3E8_V = 13719,
13744 VSSSEG4E16_V = 13720,
13745 VSSSEG4E32_V = 13721,
13746 VSSSEG4E64_V = 13722,
13747 VSSSEG4E8_V = 13723,
13748 VSSSEG5E16_V = 13724,
13749 VSSSEG5E32_V = 13725,
13750 VSSSEG5E64_V = 13726,
13751 VSSSEG5E8_V = 13727,
13752 VSSSEG6E16_V = 13728,
13753 VSSSEG6E32_V = 13729,
13754 VSSSEG6E64_V = 13730,
13755 VSSSEG6E8_V = 13731,
13756 VSSSEG7E16_V = 13732,
13757 VSSSEG7E32_V = 13733,
13758 VSSSEG7E64_V = 13734,
13759 VSSSEG7E8_V = 13735,
13760 VSSSEG8E16_V = 13736,
13761 VSSSEG8E32_V = 13737,
13762 VSSSEG8E64_V = 13738,
13763 VSSSEG8E8_V = 13739,
13764 VSSUBU_VV = 13740,
13765 VSSUBU_VX = 13741,
13766 VSSUB_VV = 13742,
13767 VSSUB_VX = 13743,
13768 VSUB_VV = 13744,
13769 VSUB_VX = 13745,
13770 VSUXEI16_V = 13746,
13771 VSUXEI32_V = 13747,
13772 VSUXEI64_V = 13748,
13773 VSUXEI8_V = 13749,
13774 VSUXSEG2EI16_V = 13750,
13775 VSUXSEG2EI32_V = 13751,
13776 VSUXSEG2EI64_V = 13752,
13777 VSUXSEG2EI8_V = 13753,
13778 VSUXSEG3EI16_V = 13754,
13779 VSUXSEG3EI32_V = 13755,
13780 VSUXSEG3EI64_V = 13756,
13781 VSUXSEG3EI8_V = 13757,
13782 VSUXSEG4EI16_V = 13758,
13783 VSUXSEG4EI32_V = 13759,
13784 VSUXSEG4EI64_V = 13760,
13785 VSUXSEG4EI8_V = 13761,
13786 VSUXSEG5EI16_V = 13762,
13787 VSUXSEG5EI32_V = 13763,
13788 VSUXSEG5EI64_V = 13764,
13789 VSUXSEG5EI8_V = 13765,
13790 VSUXSEG6EI16_V = 13766,
13791 VSUXSEG6EI32_V = 13767,
13792 VSUXSEG6EI64_V = 13768,
13793 VSUXSEG6EI8_V = 13769,
13794 VSUXSEG7EI16_V = 13770,
13795 VSUXSEG7EI32_V = 13771,
13796 VSUXSEG7EI64_V = 13772,
13797 VSUXSEG7EI8_V = 13773,
13798 VSUXSEG8EI16_V = 13774,
13799 VSUXSEG8EI32_V = 13775,
13800 VSUXSEG8EI64_V = 13776,
13801 VSUXSEG8EI8_V = 13777,
13802 VT_MASKC = 13778,
13803 VT_MASKCN = 13779,
13804 VWADDU_VV = 13780,
13805 VWADDU_VX = 13781,
13806 VWADDU_WV = 13782,
13807 VWADDU_WX = 13783,
13808 VWADD_VV = 13784,
13809 VWADD_VX = 13785,
13810 VWADD_WV = 13786,
13811 VWADD_WX = 13787,
13812 VWMACCSU_VV = 13788,
13813 VWMACCSU_VX = 13789,
13814 VWMACCUS_VX = 13790,
13815 VWMACCU_VV = 13791,
13816 VWMACCU_VX = 13792,
13817 VWMACC_VV = 13793,
13818 VWMACC_VX = 13794,
13819 VWMULSU_VV = 13795,
13820 VWMULSU_VX = 13796,
13821 VWMULU_VV = 13797,
13822 VWMULU_VX = 13798,
13823 VWMUL_VV = 13799,
13824 VWMUL_VX = 13800,
13825 VWREDSUMU_VS = 13801,
13826 VWREDSUM_VS = 13802,
13827 VWSLL_VI = 13803,
13828 VWSLL_VV = 13804,
13829 VWSLL_VX = 13805,
13830 VWSUBU_VV = 13806,
13831 VWSUBU_VX = 13807,
13832 VWSUBU_WV = 13808,
13833 VWSUBU_WX = 13809,
13834 VWSUB_VV = 13810,
13835 VWSUB_VX = 13811,
13836 VWSUB_WV = 13812,
13837 VWSUB_WX = 13813,
13838 VXOR_VI = 13814,
13839 VXOR_VV = 13815,
13840 VXOR_VX = 13816,
13841 VZEXT_VF2 = 13817,
13842 VZEXT_VF4 = 13818,
13843 VZEXT_VF8 = 13819,
13844 WFI = 13820,
13845 WRS_NTO = 13821,
13846 WRS_STO = 13822,
13847 XNOR = 13823,
13848 XOR = 13824,
13849 XORI = 13825,
13850 XPERM4 = 13826,
13851 XPERM8 = 13827,
13852 ZEXT_H_RV32 = 13828,
13853 ZEXT_H_RV64 = 13829,
13854 ZIP_RV32 = 13830,
13855 INSTRUCTION_LIST_END = 13831,
13856};
13857}
13858}
13859}
13860#endif
LIEF::assembly::riscv
RISC-V architecture-related namespace.
Definition riscv/Instruction.hpp:26
LIEF::assembly::riscv::OPCODE
OPCODE
Definition riscv/opcodes.hpp:23
LIEF::assembly::riscv::OPCODE::SC_W_AQ
@ SC_W_AQ
Definition riscv/opcodes.hpp:12944
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF4
@ PseudoVFCVT_RTZ_XU_F_V_MF4
Definition riscv/opcodes.hpp:1825
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E16
@ PseudoVFCVT_RM_F_XU_V_M8_E16
Definition riscv/opcodes.hpp:1749
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2
@ PseudoVWADDU_WV_M2
Definition riscv/opcodes.hpp:11363
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF4_MASK
@ PseudoVFCVT_RTZ_X_F_V_MF4_MASK
Definition riscv/opcodes.hpp:1838
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF2
@ PseudoVMSLT_VV_MF2
Definition riscv/opcodes.hpp:7201
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32V_SE_MF2
@ PseudoVC_FPR32V_SE_MF2
Definition riscv/opcodes.hpp:1110
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E16
@ PseudoVFNCVT_F_F_W_M4_E16
Definition riscv/opcodes.hpp:2443
LIEF::assembly::riscv::OPCODE::CBO_CLEAN
@ CBO_CLEAN
Definition riscv/opcodes.hpp:12134
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF2
@ PseudoVMSEQ_VX_MF2
Definition riscv/opcodes.hpp:6988
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF8
@ PseudoVWSUB_WX_MF8
Definition riscv/opcodes.hpp:11837
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF4
@ PseudoVFSLIDE1UP_VFPR16_MF4
Definition riscv/opcodes.hpp:3341
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E32
@ PseudoVDIVU_VX_M4_E32
Definition riscv/opcodes.hpp:1485
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E64
@ PseudoVFSGNJ_VV_M1_E64
Definition riscv/opcodes.hpp:3275
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF4
@ PseudoVLOXSEG4EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:4604
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E32_MASK
@ PseudoVREDXOR_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:8019
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF4_MASK
@ PseudoVMSLTU_VV_MF4_MASK
Definition riscv/opcodes.hpp:7175
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16_MASK_TIED
@ PseudoVFWADD_WV_MF2_E16_MASK_TIED
Definition riscv/opcodes.hpp:3531
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF8_MASK
@ PseudoVFNRCLIP_X_F_QF_MF8_MASK
Definition riscv/opcodes.hpp:2874
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF2
@ PseudoVWMACCU_VV_MF2
Definition riscv/opcodes.hpp:11497
LIEF::assembly::riscv::OPCODE::G_EXTRACT_SUBVECTOR
@ G_EXTRACT_SUBVECTOR
Definition riscv/opcodes.hpp:249
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M4
@ PseudoVSEXT_VF4_M4
Definition riscv/opcodes.hpp:8765
LIEF::assembly::riscv::OPCODE::TH_LRD
@ TH_LRD
Definition riscv/opcodes.hpp:13074
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF4_MASK
@ PseudoVSOXSEG4EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:9508
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_MF2_E32
@ PseudoVFWMUL_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3819
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF2_MASK
@ PseudoVSOXSEG6EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9626
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF4
@ PseudoVLOXSEG4EI64_V_M1_MF4
Definition riscv/opcodes.hpp:4640
LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M8_MASK
@ PseudoVLE64_V_M8_MASK
Definition riscv/opcodes.hpp:4142
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M4_E32_MASK
@ PseudoVFMSUB_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2269
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M2
@ PseudoVREV8_V_M2
Definition riscv/opcodes.hpp:8262
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E8_MASK
@ PseudoVDIVU_VX_MF2_E8_MASK
Definition riscv/opcodes.hpp:1504
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E32_MASK
@ PseudoVFWMSAC_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3788
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF8_MASK
@ PseudoVMUL_VV_MF8_MASK
Definition riscv/opcodes.hpp:7374
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M4
@ PseudoVFNCVT_RM_X_F_W_M4
Definition riscv/opcodes.hpp:2541
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M8_MASK
@ PseudoVRGATHEREI16_VV_M8_E16_M8_MASK
Definition riscv/opcodes.hpp:8375
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF2_MASK
@ PseudoVSOXSEG8EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:9826
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF8
@ PseudoVLUXSEG7EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:6320
LIEF::assembly::riscv::OPCODE::VSADDU_VI
@ VSADDU_VI
Definition riscv/opcodes.hpp:13622
LIEF::assembly::riscv::OPCODE::CV_SLL_SC_H
@ CV_SLL_SC_H
Definition riscv/opcodes.hpp:12430
LIEF::assembly::riscv::OPCODE::VOR_VV
@ VOR_VV
Definition riscv/opcodes.hpp:13584
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_MF2_MASK
@ PseudoVMFNE_VFPR32_MF2_MASK
Definition riscv/opcodes.hpp:6805
LIEF::assembly::riscv::OPCODE::SSPOPCHK
@ SSPOPCHK
Definition riscv/opcodes.hpp:13012
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64_V_M1_MASK
@ PseudoVLSEG5E64_V_M1_MASK
Definition riscv/opcodes.hpp:5261
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF2
@ PseudoVSOXSEG4EI64_V_M2_MF2
Definition riscv/opcodes.hpp:9469
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M1
@ PseudoVSOXSEG2EI16_V_M2_M1
Definition riscv/opcodes.hpp:9163
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E16
@ PseudoVFWREDUSUM_VS_M8_E16
Definition riscv/opcodes.hpp:3945
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E64_MASK
@ PseudoVFNMADD_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:2710
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E16
@ PseudoVFREDMAX_VS_M2_E16
Definition riscv/opcodes.hpp:2941
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E16_MASK
@ PseudoVFWCVT_F_F_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:3572
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E32
@ PseudoVFSGNJ_VV_M1_E32
Definition riscv/opcodes.hpp:3273
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M2
@ PseudoVNMSAC_VV_M2
Definition riscv/opcodes.hpp:7500
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E32_MASK
@ PseudoVFMACC_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:1976
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M1
@ PseudoVSUXSEG3EI8_V_MF4_M1
Definition riscv/opcodes.hpp:10889
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M8
@ PseudoVMAX_VX_M8
Definition riscv/opcodes.hpp:6562
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF8
@ PseudoVLOXEI64_V_M1_MF8
Definition riscv/opcodes.hpp:4264
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF4_MASK
@ PseudoVLSEG4E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5235
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_M1_MASK
@ PseudoVSSSEG6E8_V_M1_MASK
Definition riscv/opcodes.hpp:10372
LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_M1
@ PseudoVSPILL8_M1
Definition riscv/opcodes.hpp:9859
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M4
@ PseudoVCLZ_V_M4
Definition riscv/opcodes.hpp:1004
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E32_MASK
@ PseudoVFNMSUB_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:2846
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M8
@ PseudoVFMERGE_VFPR32M_M8
Definition riscv/opcodes.hpp:2126
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_MF2_MASK
@ PseudoVLUXSEG7EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6307
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M4
@ PseudoVSSE16_V_M4
Definition riscv/opcodes.hpp:9951
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_M1_MASK
@ PseudoVSOXSEG4EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9450
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF8_MASK
@ PseudoVWMULSU_VV_MF8_MASK
Definition riscv/opcodes.hpp:11550
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF4
@ PseudoVSLL_VX_MF4
Definition riscv/opcodes.hpp:8916
LIEF::assembly::riscv::OPCODE::VL4RE64_V
@ VL4RE64_V
Definition riscv/opcodes.hpp:13317
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M1
@ PseudoVSLL_VX_M1
Definition riscv/opcodes.hpp:8906
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M1
@ PseudoVLUXSEG4EI16_V_M2_M1
Definition riscv/opcodes.hpp:5978
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M2
@ PseudoVLUXSEG3EI8_V_M1_M2
Definition riscv/opcodes.hpp:5946
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E32
@ PseudoVREM_VV_M2_E32
Definition riscv/opcodes.hpp:8182
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32_MASK
@ PseudoVFWADD_WV_M2_E32_MASK
Definition riscv/opcodes.hpp:3518
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF4
@ PseudoVLSE8_V_MF4
Definition riscv/opcodes.hpp:5050
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK
@ PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK
Definition riscv/opcodes.hpp:8297
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_OR
@ G_VECREDUCE_OR
Definition riscv/opcodes.hpp:311
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M4
@ PseudoVSLL_VX_M4
Definition riscv/opcodes.hpp:8910
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF8
@ PseudoVNSRL_WV_MF8
Definition riscv/opcodes.hpp:7612
LIEF::assembly::riscv::OPCODE::VNCLIP_WV
@ VNCLIP_WV
Definition riscv/opcodes.hpp:13571
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF4_MASK
@ PseudoVWMACCUS_VX_MF4_MASK
Definition riscv/opcodes.hpp:11488
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M8_M1
@ PseudoVSOXSEG7EI64_V_M8_M1
Definition riscv/opcodes.hpp:9729
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M2_MASK
@ PseudoVLSEG2E32_V_M2_MASK
Definition riscv/opcodes.hpp:5085
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M4_E64_MASK
@ PseudoVFMACC_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:1964
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF2
@ PseudoVWMULSU_VV_MF2
Definition riscv/opcodes.hpp:11545
LIEF::assembly::riscv::OPCODE::CTZ
@ CTZ
Definition riscv/opcodes.hpp:12159
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E16
@ PseudoVREDXOR_VS_M8_E16
Definition riscv/opcodes.hpp:8032
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_M1
@ PseudoVLUXSEG7EI32_V_M1_M1
Definition riscv/opcodes.hpp:6262
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E32
@ PseudoVFNCVTBF16_F_F_W_M2_E32
Definition riscv/opcodes.hpp:2423
LIEF::assembly::riscv::OPCODE::TH_LWIA
@ TH_LWIA
Definition riscv/opcodes.hpp:13087
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_M1
@ PseudoVLUXSEG8EI16_V_MF2_M1
Definition riscv/opcodes.hpp:6328
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF4_MASK
@ PseudoVLOXSEG6EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4795
LIEF::assembly::riscv::OPCODE::VFREDMAX_VS
@ VFREDMAX_VS
Definition riscv/opcodes.hpp:13255
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF4_MASK
@ PseudoVWMACCSU_VX_MF4_MASK
Definition riscv/opcodes.hpp:11476
LIEF::assembly::riscv::OPCODE::TH_LDIB
@ TH_LDIB
Definition riscv/opcodes.hpp:13067
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M4
@ PseudoVSSSEG2E32_V_M4
Definition riscv/opcodes.hpp:10261
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF4
@ PseudoVLSEG8E16FF_V_MF4
Definition riscv/opcodes.hpp:5362
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF2
@ PseudoVNMSUB_VV_MF2
Definition riscv/opcodes.hpp:7534
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF4_MASK
@ PseudoVSSEG4E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10062
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF2
@ PseudoVLSEG7E16_V_MF2
Definition riscv/opcodes.hpp:5326
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M2_MASK
@ PseudoVLOXSEG2EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:4357
LIEF::assembly::riscv::OPCODE::DRET
@ DRET
Definition riscv/opcodes.hpp:12555
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M1_MASK
@ PseudoVSOXEI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9026
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E16
@ PseudoVWREDSUM_VS_M8_E16
Definition riscv/opcodes.hpp:11665
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_M1_MASK
@ PseudoVSSSEG6E16_V_M1_MASK
Definition riscv/opcodes.hpp:10360
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E64_MASK
@ PseudoVFMSAC_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:2245
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF2_MASK
@ PseudoVWADD_VX_MF2_MASK
Definition riscv/opcodes.hpp:11414
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M2
@ PseudoTHVdotVMAQAU_VX_M2
Definition riscv/opcodes.hpp:492
LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_M8
@ PseudoVMXNOR_MM_M8
Definition riscv/opcodes.hpp:7415
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M1
@ PseudoVLSEG4E64_V_M1
Definition riscv/opcodes.hpp:5214
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M2_E32_MASK
@ PseudoVFMSUB_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2267
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF2
@ PseudoVSOXSEG5EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:9519
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E32_MASK
@ PseudoVFCVT_F_XU_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:1698
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M1
@ PseudoVSEXT_VF4_M1
Definition riscv/opcodes.hpp:8761
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF2
@ PseudoVSUXSEG6EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:11163
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E32_MASK
@ PseudoVFNMADD_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:2708
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF4_MASK
@ PseudoVSUXSEG5EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:11060
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M4_E64_MASK
@ PseudoVFNMSAC_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2762
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SEQ_FMUL
@ G_VECREDUCE_SEQ_FMUL
Definition riscv/opcodes.hpp:301
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M2
@ PseudoVSADD_VV_M2
Definition riscv/opcodes.hpp:8662
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF2
@ PseudoVFSLIDE1UP_VFPR16_MF2
Definition riscv/opcodes.hpp:3339
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E32_MASK
@ PseudoVFNMACC_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:2660
LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_4x8x4_MF2
@ PseudoVQMACCSU_4x8x4_MF2
Definition riscv/opcodes.hpp:7675
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M4_MASK
@ PseudoVWMACCUS_VX_M4_MASK
Definition riscv/opcodes.hpp:11484
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_M1_MASK
@ PseudoVSOXSEG8EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9814
LIEF::assembly::riscv::OPCODE::G_FMINNUM_IEEE
@ G_FMINNUM_IEEE
Definition riscv/opcodes.hpp:226
LIEF::assembly::riscv::OPCODE::C_SWSP
@ C_SWSP
Definition riscv/opcodes.hpp:12545
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_M2
@ PseudoVC_V_VVV_M2
Definition riscv/opcodes.hpp:1303
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF8
@ PseudoVSOXSEG6EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:9669
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF2
@ PseudoVSSSEG4E16_V_MF2
Definition riscv/opcodes.hpp:10315
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E32_MASK
@ PseudoVFWREDUSUM_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:3940
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_M1
@ PseudoVAESEM_VS_M1_M1
Definition riscv/opcodes.hpp:727
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF2
@ PseudoVSUXEI8_V_MF8_MF2
Definition riscv/opcodes.hpp:10653
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M4
@ PseudoVMFLE_VV_M4
Definition riscv/opcodes.hpp:6734
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_M1
@ PseudoVSUXSEG7EI64_V_M4_M1
Definition riscv/opcodes.hpp:11229
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M2
@ PseudoVFMERGE_VFPR16M_M2
Definition riscv/opcodes.hpp:2118
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF2_MASK
@ PseudoVAADD_VX_MF2_MASK
Definition riscv/opcodes.hpp:572
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M1_E16
@ PseudoVFNMADD_VFPR16_M1_E16
Definition riscv/opcodes.hpp:2675
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M2_MASK
@ PseudoVLOXSEG2EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4345
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF2_MASK
@ PseudoVFCVT_RTZ_XU_F_V_MF2_MASK
Definition riscv/opcodes.hpp:1824
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M2_MASK
@ PseudoVLOXSEG2EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:4449
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2
@ PseudoVWSUBU_WV_MF2
Definition riscv/opcodes.hpp:11755
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_MF4
@ PseudoVAESDF_VS_M1_MF4
Definition riscv/opcodes.hpp:642
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E32_MASK
@ PseudoVFMAX_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:2102
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M1_MASK
@ PseudoVSSUB_VV_M1_MASK
Definition riscv/opcodes.hpp:10448
LIEF::assembly::riscv::OPCODE::VSRL_VI
@ VSRL_VI
Definition riscv/opcodes.hpp:13695
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E16_MASK
@ PseudoVFWNMACC_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3870
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF4
@ PseudoVLOXSEG8EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:5006
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M4_MASK
@ PseudoVMUL_VV_M4_MASK
Definition riscv/opcodes.hpp:7366
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M8_E16_MASK
@ PseudoVFNMACC_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2622
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M1
@ PseudoVAESEM_VV_M1
Definition riscv/opcodes.hpp:751
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M8_MASK
@ PseudoVSSUB_VX_M8_MASK
Definition riscv/opcodes.hpp:10468
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF2
@ PseudoVSUXSEG5EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:11089
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M8_MASK
@ PseudoVZEXT_VF2_M8_MASK
Definition riscv/opcodes.hpp:11888
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M2_MASK
@ PseudoVLUXSEG3EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:5865
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF8_MASK
@ PseudoVWADDU_VX_MF8_MASK
Definition riscv/opcodes.hpp:11358
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E16
@ PseudoVREMU_VV_M1_E16
Definition riscv/opcodes.hpp:8084
LIEF::assembly::riscv::OPCODE::VCLZ_V
@ VCLZ_V
Definition riscv/opcodes.hpp:13167
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_M1_MASK
@ PseudoVSUXSEG4EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10962
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF8
@ PseudoVMSLEU_VX_MF8
Definition riscv/opcodes.hpp:7119
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF4_MASK
@ PseudoVLSEG3E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5179
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_M1
@ PseudoVLSEG7E16_V_M1
Definition riscv/opcodes.hpp:5324
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M8
@ PseudoVMSLE_VX_M8
Definition riscv/opcodes.hpp:7155
LIEF::assembly::riscv::OPCODE::VC_I
@ VC_I
Definition riscv/opcodes.hpp:13175
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF2_MASK
@ PseudoVSSSEG4E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10316
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_M1
@ PseudoVSOXSEG7EI32_V_M1_M1
Definition riscv/opcodes.hpp:9691
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF4_MASK
@ PseudoVNMSUB_VV_MF4_MASK
Definition riscv/opcodes.hpp:7537
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M2_M2_MASK
@ PseudoVLUXSEG3EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5949
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF4_E16_MASK
@ PseudoVFWADD_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3486
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M4
@ PseudoVSUXEI16_V_M2_M4
Definition riscv/opcodes.hpp:10515
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M2_MASK
@ PseudoVLSEG3E8_V_M2_MASK
Definition riscv/opcodes.hpp:5175
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M8_MASK
@ PseudoVRGATHEREI16_VV_M4_E64_M8_MASK
Definition riscv/opcodes.hpp:8361
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M4_MASK
@ PseudoVMFLT_VFPR16_M4_MASK
Definition riscv/opcodes.hpp:6747
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF2_MASK
@ PseudoVMULH_VX_MF2_MASK
Definition riscv/opcodes.hpp:7356
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M2_MASK
@ PseudoVSUXEI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:10570
LIEF::assembly::riscv::OPCODE::VSSRA_VV
@ VSSRA_VV
Definition riscv/opcodes.hpp:13731
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF8_MASK
@ PseudoVSUXSEG4EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:11014
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E16
@ PseudoVFMUL_VV_M4_E16
Definition riscv/opcodes.hpp:2354
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M8_E32
@ PseudoVFMUL_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2330
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M2
@ PseudoVRGATHEREI16_VV_M2_E8_M2
Definition riscv/opcodes.hpp:8332
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M2
@ PseudoVSUXSEG3EI8_V_M1_M2
Definition riscv/opcodes.hpp:10879
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_MF2
@ PseudoVFMV_V_FPR32_MF2
Definition riscv/opcodes.hpp:2412
LIEF::assembly::riscv::OPCODE::FSQRT_H_INX
@ FSQRT_H_INX
Definition riscv/opcodes.hpp:12783
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF4_MASK
@ PseudoVSUXSEG3EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:10856
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF2
@ PseudoVLOXSEG7EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:4858
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E16
@ PseudoVREM_VV_M1_E16
Definition riscv/opcodes.hpp:8172
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E16
@ PseudoVREMU_VX_M1_E16
Definition riscv/opcodes.hpp:8128
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF4_MASK
@ PseudoVAND_VV_MF4_MASK
Definition riscv/opcodes.hpp:843
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF2
@ PseudoVSOXSEG2EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:9219
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M2_MASK
@ PseudoVMULHU_VV_M2_MASK
Definition riscv/opcodes.hpp:7308
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF4
@ PseudoVSUXSEG8EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:11325
LIEF::assembly::riscv::OPCODE::CV_CLIPU
@ CV_CLIPU
Definition riscv/opcodes.hpp:12209
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M8_MASK
@ PseudoVMFGT_VFPR16_M8_MASK
Definition riscv/opcodes.hpp:6677
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E32_MASK
@ PseudoVFWNMSAC_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3904
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M1_E16
@ PseudoVFSGNJN_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3121
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E16
@ PseudoVFSQRT_V_MF2_E16
Definition riscv/opcodes.hpp:3385
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S_M1
@ PseudoVFMV_FPR32_S_M1
Definition riscv/opcodes.hpp:2378
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF4
@ PseudoVSSRL_VX_MF4
Definition riscv/opcodes.hpp:10243
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_MF2
@ PseudoVSSSEG7E32_V_MF2
Definition riscv/opcodes.hpp:10387
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M2
@ PseudoVSSEG3E64_V_M2
Definition riscv/opcodes.hpp:10043
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4_MASK_TIED
@ PseudoVWADD_WV_MF4_MASK_TIED
Definition riscv/opcodes.hpp:11437
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M2_MASK
@ PseudoVFWCVT_RM_XU_F_V_M2_MASK
Definition riscv/opcodes.hpp:3640
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M4_MASK
@ PseudoVFCVT_X_F_V_M4_MASK
Definition riscv/opcodes.hpp:1856
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E8
@ PseudoVREMU_VX_MF2_E8
Definition riscv/opcodes.hpp:8164
LIEF::assembly::riscv::OPCODE::AMOMAXU_H
@ AMOMAXU_H
Definition riscv/opcodes.hpp:12011
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF2
@ PseudoVLSEG3E16_V_MF2
Definition riscv/opcodes.hpp:5138
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E64_MASK
@ PseudoVDIVU_VX_M1_E64_MASK
Definition riscv/opcodes.hpp:1472
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_MF2
@ PseudoVLOXSEG8EI64_V_M4_MF2
Definition riscv/opcodes.hpp:4986
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E32
@ PseudoVFMSAC_VV_M2_E32
Definition riscv/opcodes.hpp:2230
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E64
@ PseudoVREDMIN_VS_M4_E64
Definition riscv/opcodes.hpp:7896
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M1_MASK
@ PseudoVLSSEG2E32_V_M1_MASK
Definition riscv/opcodes.hpp:5409
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M1
@ PseudoVLUXSEG3EI16_V_MF2_M1
Definition riscv/opcodes.hpp:5874
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_MF2_E32_MASK
@ PseudoVFMADD_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2018
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK
@ PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK
Definition riscv/opcodes.hpp:8411
LIEF::assembly::riscv::OPCODE::CV_CMPLEU_B
@ CV_CMPLEU_B
Definition riscv/opcodes.hpp:12241
LIEF::assembly::riscv::OPCODE::PseudoCmpXchg32
@ PseudoCmpXchg32
Definition riscv/opcodes.hpp:369
LIEF::assembly::riscv::OPCODE::G_SSUBSAT
@ G_SSUBSAT
Definition riscv/opcodes.hpp:185
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_MF4
@ PseudoVAESEM_VS_M2_MF4
Definition riscv/opcodes.hpp:734
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_M1_MASK
@ PseudoVLOXSEG8EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4943
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF4_MASK
@ PseudoVLUXSEG3EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:5923
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M2_MASK
@ PseudoVNSRA_WI_M2_MASK
Definition riscv/opcodes.hpp:7557
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF2
@ PseudoVMADD_VV_MF2
Definition riscv/opcodes.hpp:6480
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E32_MASK
@ PseudoVFNMACC_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:2666
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF8
@ PseudoVMSNE_VI_MF8
Definition riscv/opcodes.hpp:7233
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_SE_M4
@ PseudoVC_V_FPR64V_SE_M4
Definition riscv/opcodes.hpp:1246
LIEF::assembly::riscv::OPCODE::PseudoTAILIndirect
@ PseudoTAILIndirect
Definition riscv/opcodes.hpp:448
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M1_E16_MASK
@ PseudoVFADD_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:1600
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M8
@ PseudoVMSBC_VX_M8
Definition riscv/opcodes.hpp:6934
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_M1_MASK
@ PseudoVLUXSEG5EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:6095
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M8_MASK
@ PseudoVRGATHEREI16_VV_M4_E32_M8_MASK
Definition riscv/opcodes.hpp:8353
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF4_E16_MASK
@ PseudoVFNMADD_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:2734
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E8_MASK
@ PseudoVDIV_VV_M8_E8_MASK
Definition riscv/opcodes.hpp:1542
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_MF4
@ PseudoVMADC_VVM_MF4
Definition riscv/opcodes.hpp:6449
LIEF::assembly::riscv::OPCODE::G_USUBSAT
@ G_USUBSAT
Definition riscv/opcodes.hpp:184
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E64
@ PseudoVFDIV_VV_M1_E64
Definition riscv/opcodes.hpp:1897
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E64_MASK
@ PseudoVFNMACC_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:2650
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M8
@ PseudoVSLIDEDOWN_VI_M8
Definition riscv/opcodes.hpp:8828
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M1_MASK
@ PseudoVLUXSEG4EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:6051
LIEF::assembly::riscv::OPCODE::MOPR10
@ MOPR10
Definition riscv/opcodes.hpp:12862
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF4
@ PseudoVWADDU_WX_MF4
Definition riscv/opcodes.hpp:11391
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_M1_MASK
@ PseudoVLUXSEG6EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6189
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M1_E32
@ PseudoVFMACC_VFPR32_M1_E32
Definition riscv/opcodes.hpp:1949
LIEF::assembly::riscv::OPCODE::PseudoVQMACC_2x8x2_M8
@ PseudoVQMACC_2x8x2_M8
Definition riscv/opcodes.hpp:7695
LIEF::assembly::riscv::OPCODE::PseudoSB
@ PseudoSB
Definition riscv/opcodes.hpp:441
LIEF::assembly::riscv::OPCODE::FADD_D_IN32X
@ FADD_D_IN32X
Definition riscv/opcodes.hpp:12559
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF4_E16
@ PseudoVFMAX_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2067
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M4_MASK
@ PseudoVSUXSEG2EI64_V_M4_M4_MASK
Definition riscv/opcodes.hpp:10750
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E8_MASK
@ PseudoVREDXOR_VS_M2_E8_MASK
Definition riscv/opcodes.hpp:8023
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M2
@ PseudoVNSRL_WV_M2
Definition riscv/opcodes.hpp:7604
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E32
@ PseudoVREDSUM_VS_M4_E32
Definition riscv/opcodes.hpp:7982
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_MF2_MASK
@ PseudoVFWCVT_RM_XU_F_V_MF2_MASK
Definition riscv/opcodes.hpp:3644
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M8_M1
@ PseudoVSUXSEG6EI64_V_M8_M1
Definition riscv/opcodes.hpp:11153
LIEF::assembly::riscv::OPCODE::HLV_HU
@ HLV_HU
Definition riscv/opcodes.hpp:12804
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF8_MASK
@ PseudoVADD_VV_MF8_MASK
Definition riscv/opcodes.hpp:625
LIEF::assembly::riscv::OPCODE::VL2RE64_V
@ VL2RE64_V
Definition riscv/opcodes.hpp:13313
LIEF::assembly::riscv::OPCODE::C_SSPOPCHK
@ C_SSPOPCHK
Definition riscv/opcodes.hpp:12540
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M2
@ PseudoVFCVT_RTZ_X_F_V_M2
Definition riscv/opcodes.hpp:1829
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E16
@ PseudoVFNCVT_F_F_W_MF2_E16
Definition riscv/opcodes.hpp:2447
LIEF::assembly::riscv::OPCODE::C_NOT
@ C_NOT
Definition riscv/opcodes.hpp:12525
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF4
@ PseudoVSUXSEG6EI64_V_M2_MF4
Definition riscv/opcodes.hpp:11147
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_MF2
@ PseudoVAESDF_VS_M1_MF2
Definition riscv/opcodes.hpp:641
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M1_MASK
@ PseudoVLOXSEG3EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4513
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M4_E16_MASK
@ PseudoVFMACC_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:1942
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_MF4
@ PseudoVFMERGE_VFPR16M_MF4
Definition riscv/opcodes.hpp:2122
LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_M1
@ PseudoVMXNOR_MM_M1
Definition riscv/opcodes.hpp:7412
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E32_MASK
@ PseudoVFWCVT_F_XU_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:3598
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M8_E32_MASK
@ PseudoVFSUB_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:3410
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M8_MASK
@ PseudoVSRL_VI_M8_MASK
Definition riscv/opcodes.hpp:9912
LIEF::assembly::riscv::OPCODE::TH_TST
@ TH_TST
Definition riscv/opcodes.hpp:13127
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2
@ PseudoVWADD_WV_MF2
Definition riscv/opcodes.hpp:11431
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M2
@ PseudoVCLZ_V_M2
Definition riscv/opcodes.hpp:1002
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M1
@ PseudoVLSSEG4E8_V_M1
Definition riscv/opcodes.hpp:5480
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M2
@ PseudoVLSE8_V_M2
Definition riscv/opcodes.hpp:5042
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M1
@ PseudoVMFGT_VFPR16_M1
Definition riscv/opcodes.hpp:6670
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E32_MASK
@ PseudoVFREDMAX_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:2950
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E8_MASK
@ PseudoVREDOR_VS_MF4_E8_MASK
Definition riscv/opcodes.hpp:7961
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M1
@ PseudoVSUXSEG4EI16_V_M1_M1
Definition riscv/opcodes.hpp:10905
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF2
@ PseudoVLOXSEG7EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:4924
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M2_MASK
@ PseudoVLUXSEG2EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:5829
LIEF::assembly::riscv::OPCODE::VMNAND_MM
@ VMNAND_MM
Definition riscv/opcodes.hpp:13517
LIEF::assembly::riscv::OPCODE::VFSGNJN_VV
@ VFSGNJN_VV
Definition riscv/opcodes.hpp:13262
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M1_MASK
@ PseudoVANDN_VX_M1_MASK
Definition riscv/opcodes.hpp:805
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M1
@ PseudoVNCLIPU_WI_M1
Definition riscv/opcodes.hpp:7426
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E32
@ PseudoVFMIN_VV_M8_E32
Definition riscv/opcodes.hpp:2182
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E32
@ PseudoVFSGNJ_VV_M8_E32
Definition riscv/opcodes.hpp:3291
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_MF2_MASK
@ PseudoVSUXSEG4EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10910
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E8_MASK
@ PseudoVFWCVT_F_X_V_M2_E8_MASK
Definition riscv/opcodes.hpp:3618
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_M1_MASK
@ PseudoVSUXSEG8EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11296
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M4_MASK
@ PseudoVXOR_VX_M4_MASK
Definition riscv/opcodes.hpp:11872
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_SE_MF2
@ PseudoVC_V_FPR32V_SE_MF2
Definition riscv/opcodes.hpp:1231
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E16_MASK
@ PseudoVFNCVT_F_F_W_M1_E16_MASK
Definition riscv/opcodes.hpp:2436
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF4_MASK
@ PseudoVWSLL_VI_MF4_MASK
Definition riscv/opcodes.hpp:11692
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M1_E16_MASK
@ PseudoVFRDIV_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:2876
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E16
@ PseudoVFCVT_RM_F_XU_V_M1_E16
Definition riscv/opcodes.hpp:1731
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M8_MASK
@ PseudoVCLMUL_VV_M8_MASK
Definition riscv/opcodes.hpp:979
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF4
@ PseudoVFCVT_XU_F_V_MF4
Definition riscv/opcodes.hpp:1849
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF8_MASK
@ PseudoVSSRA_VI_MF8_MASK
Definition riscv/opcodes.hpp:10176
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M1_MASK
@ PseudoVLSEG2E64FF_V_M1_MASK
Definition riscv/opcodes.hpp:5091
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF4_MASK
@ PseudoVSUXSEG3EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:10902
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E32_MASK
@ PseudoVFMACC_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:1988
LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B1
@ PseudoVLM_V_B1
Definition riscv/opcodes.hpp:4171
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M2
@ PseudoVCPOP_V_M2
Definition riscv/opcodes.hpp:1052
LIEF::assembly::riscv::OPCODE::PseudoVID_V_M2_MASK
@ PseudoVID_V_M2_MASK
Definition riscv/opcodes.hpp:4058
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E16_MASK
@ PseudoVFMUL_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:2343
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF2_MASK
@ PseudoVLOXSEG6EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4805
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E16
@ PseudoVFRSQRT7_V_MF2_E16
Definition riscv/opcodes.hpp:3085
LIEF::assembly::riscv::OPCODE::HINVAL_GVMA
@ HINVAL_GVMA
Definition riscv/opcodes.hpp:12796
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M8
@ PseudoVLUXEI8_V_M2_M8
Definition riscv/opcodes.hpp:5694
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E16_MASK
@ PseudoVFMAX_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:2106
LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_MF8
@ PseudoVMNOR_MM_MF8
Definition riscv/opcodes.hpp:6895
LIEF::assembly::riscv::OPCODE::G_FCEIL
@ G_FCEIL
Definition riscv/opcodes.hpp:262
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M8_M2_MASK
@ PseudoVSOXSEG4EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:9448
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E32
@ PseudoVREDSUM_VS_M1_E32
Definition riscv/opcodes.hpp:7966
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M1_MASK
@ PseudoVLSSEG3E16_V_M1_MASK
Definition riscv/opcodes.hpp:5435
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64V_SE_M2
@ PseudoVC_FPR64V_SE_M2
Definition riscv/opcodes.hpp:1116
LIEF::assembly::riscv::OPCODE::FMVP_D_X
@ FMVP_D_X
Definition riscv/opcodes.hpp:12728
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF2
@ PseudoVSRA_VI_MF2
Definition riscv/opcodes.hpp:9871
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M4
@ PseudoVMSLEU_VI_M4
Definition riscv/opcodes.hpp:7083
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF2_E16
@ PseudoVFMADD_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2005
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M4_MASK
@ PseudoVNMSAC_VX_M4_MASK
Definition riscv/opcodes.hpp:7517
LIEF::assembly::riscv::OPCODE::AMOMINU_B
@ AMOMINU_B
Definition riscv/opcodes.hpp:12035
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E16
@ PseudoVREMU_VX_MF2_E16
Definition riscv/opcodes.hpp:8160
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M1_MASK
@ PseudoVLOXEI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:4283
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M8_MASK
@ PseudoVSLIDEDOWN_VX_M8_MASK
Definition riscv/opcodes.hpp:8843
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF2_MASK
@ PseudoVLOXSEG8EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:5005
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF2_MASK
@ PseudoVNCLIPU_WX_MF2_MASK
Definition riscv/opcodes.hpp:7457
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M1
@ PseudoVLSSEG4E16_V_M1
Definition riscv/opcodes.hpp:5462
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M1
@ PseudoVCLMULH_VV_M1
Definition riscv/opcodes.hpp:944
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF2_MASK
@ PseudoVSOXSEG7EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9694
LIEF::assembly::riscv::OPCODE::FADD_S_INX
@ FADD_S_INX
Definition riscv/opcodes.hpp:12564
LIEF::assembly::riscv::OPCODE::VC_V_XV
@ VC_V_XV
Definition riscv/opcodes.hpp:13193
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M1_MASK
@ PseudoVSOXEI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9112
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M8
@ PseudoVSOXEI16_V_M4_M8
Definition riscv/opcodes.hpp:9019
LIEF::assembly::riscv::OPCODE::TH_SRD
@ TH_SRD
Definition riscv/opcodes.hpp:13111
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M8
@ PseudoTHVdotVMAQAU_VV_M8
Definition riscv/opcodes.hpp:486
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E32
@ PseudoVFNMADD_VV_M4_E32
Definition riscv/opcodes.hpp:2719
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M2
@ PseudoVMADC_VX_M2
Definition riscv/opcodes.hpp:6466
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF8_MASK
@ PseudoVNCLIPU_WI_MF8_MASK
Definition riscv/opcodes.hpp:7437
LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF8
@ PseudoVID_V_MF8
Definition riscv/opcodes.hpp:4067
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M8_M1_MASK
@ PseudoVLUXSEG7EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:6301
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M2_E64_MASK
@ PseudoVFMSAC_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2217
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E32_MASK
@ PseudoVFWCVTBF16_F_F_V_M1_E32_MASK
Definition riscv/opcodes.hpp:3544
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF4_E16_MASK
@ PseudoVFDIV_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:1874
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF4_MASK
@ PseudoVLOXSEG3EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4489
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M2_MASK
@ PseudoVLOXSEG4EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4647
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E8_MASK
@ PseudoVREMU_VV_M8_E8_MASK
Definition riscv/opcodes.hpp:8115
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF2_MASK
@ PseudoVSOXSEG5EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9534
LIEF::assembly::riscv::OPCODE::VSOXSEG4EI16_V
@ VSOXSEG4EI16_V
Definition riscv/opcodes.hpp:13672
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M2_M2_MASK
@ PseudoVSOXSEG4EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9488
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M1_MASK
@ PseudoVWMUL_VV_M1_MASK
Definition riscv/opcodes.hpp:11588
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF4
@ PseudoVSUXSEG4EI64_V_M1_MF4
Definition riscv/opcodes.hpp:10965
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_M2
@ PseudoVAESDF_VS_M2_M2
Definition riscv/opcodes.hpp:645
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M2_MASK
@ PseudoVLOXEI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4277
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E16_MASK
@ PseudoVFRSQRT7_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:3086
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M2
@ PseudoVWSUB_VX_M2
Definition riscv/opcodes.hpp:11793
LIEF::assembly::riscv::OPCODE::ADD_UW
@ ADD_UW
Definition riscv/opcodes.hpp:11935
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_MF2_MASK
@ PseudoVSUXSEG5EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11080
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M2
@ PseudoVSUXSEG3EI16_V_M1_M2
Definition riscv/opcodes.hpp:10797
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_M1
@ PseudoVC_V_X_SE_M1
Definition riscv/opcodes.hpp:1389
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M2
@ PseudoVSUXSEG4EI32_V_M1_M2
Definition riscv/opcodes.hpp:10935
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF8
@ PseudoVSUXSEG7EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:11213
LIEF::assembly::riscv::OPCODE::CV_MINU_SC_B
@ CV_MINU_SC_B
Definition riscv/opcodes.hpp:12362
LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_MF4
@ PseudoVMNOR_MM_MF4
Definition riscv/opcodes.hpp:6894
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E64
@ PseudoVFCVT_RM_F_X_V_M2_E64
Definition riscv/opcodes.hpp:1771
LIEF::assembly::riscv::OPCODE::VCPOP_V
@ VCPOP_V
Definition riscv/opcodes.hpp:13170
LIEF::assembly::riscv::OPCODE::VSLIDEUP_VX
@ VSLIDEUP_VX
Definition riscv/opcodes.hpp:13648
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M1
@ PseudoVSOXEI16_V_M1_M1
Definition riscv/opcodes.hpp:8999
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M2_MASK
@ PseudoVWSUB_VV_M2_MASK
Definition riscv/opcodes.hpp:11782
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_M1
@ PseudoVLOXSEG7EI64_V_M1_M1
Definition riscv/opcodes.hpp:4890
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF4
@ PseudoVLUXSEG2EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:5852
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF8
@ PseudoVROR_VI_MF8
Definition riscv/opcodes.hpp:8546
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF2_MASK
@ PseudoVIOTA_M_MF2_MASK
Definition riscv/opcodes.hpp:4078
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M2
@ PseudoVAND_VV_M2
Definition riscv/opcodes.hpp:834
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF8
@ PseudoVOR_VX_MF8
Definition riscv/opcodes.hpp:7666
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M2
@ PseudoVSADDU_VV_M2
Definition riscv/opcodes.hpp:8620
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF2
@ PseudoVSOXSEG6EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:9625
LIEF::assembly::riscv::OPCODE::VSSRL_VX
@ VSSRL_VX
Definition riscv/opcodes.hpp:13735
LIEF::assembly::riscv::OPCODE::HLV_WU
@ HLV_WU
Definition riscv/opcodes.hpp:12806
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_M1_MASK
@ PseudoVSUXSEG5EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11042
LIEF::assembly::riscv::OPCODE::VDIV_VV
@ VDIV_VV
Definition riscv/opcodes.hpp:13202
LIEF::assembly::riscv::OPCODE::InsnS
@ InsnS
Definition riscv/opcodes.hpp:12828
LIEF::assembly::riscv::OPCODE::G_FLOG10
@ G_FLOG10
Definition riscv/opcodes.hpp:210
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2_TIED
@ PseudoVWADDU_WV_M2_TIED
Definition riscv/opcodes.hpp:11366
LIEF::assembly::riscv::OPCODE::C_BEQZ
@ C_BEQZ
Definition riscv/opcodes.hpp:12486
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M4_MASK
@ PseudoVSSEG2E16_V_M4_MASK
Definition riscv/opcodes.hpp:9996
LIEF::assembly::riscv::OPCODE::AMOMAX_D_AQ
@ AMOMAX_D_AQ
Definition riscv/opcodes.hpp:12024
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_MF2
@ PseudoVC_V_VV_SE_MF2
Definition riscv/opcodes.hpp:1339
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF8
@ PseudoVSLIDE1UP_VX_MF8
Definition riscv/opcodes.hpp:8820
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E64
@ PseudoVDIVU_VV_M1_E64
Definition riscv/opcodes.hpp:1427
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M2_MASK
@ PseudoVRGATHEREI16_VV_M4_E8_M2_MASK
Definition riscv/opcodes.hpp:8365
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M1_MASK
@ PseudoVLOXSEG3EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4507
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_M2
@ PseudoVC_V_IVW_M2
Definition riscv/opcodes.hpp:1263
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_M1
@ PseudoVLUXSEG6EI16_V_MF2_M1
Definition riscv/opcodes.hpp:6168
LIEF::assembly::riscv::OPCODE::AMOADD_H_AQ
@ AMOADD_H_AQ
Definition riscv/opcodes.hpp:11956
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF4
@ PseudoVWMUL_VV_MF4
Definition riscv/opcodes.hpp:11595
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF4_MASK
@ PseudoVSADDU_VI_MF4_MASK
Definition riscv/opcodes.hpp:8615
LIEF::assembly::riscv::OPCODE::G_FCOPYSIGN
@ G_FCOPYSIGN
Definition riscv/opcodes.hpp:221
LIEF::assembly::riscv::OPCODE::VSOXSEG8EI32_V
@ VSOXSEG8EI32_V
Definition riscv/opcodes.hpp:13689
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M8
@ PseudoTHVdotVMAQASU_VX_M8
Definition riscv/opcodes.hpp:466
LIEF::assembly::riscv::OPCODE::AMOXOR_D_AQ
@ AMOXOR_D_AQ
Definition riscv/opcodes.hpp:12104
LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_M1
@ PseudoVC_IV_SE_M1
Definition riscv/opcodes.hpp:1132
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M2
@ PseudoVSOXSEG2EI32_V_M8_M2
Definition riscv/opcodes.hpp:9213
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M1
@ PseudoVSSSEG2E64_V_M1
Definition riscv/opcodes.hpp:10265
LIEF::assembly::riscv::OPCODE::VSM_V
@ VSM_V
Definition riscv/opcodes.hpp:13659
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK
@ PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK
Definition riscv/opcodes.hpp:8425
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_M1_MASK
@ PseudoVSUXEI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10576
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF4
@ PseudoVLSEG2E16FF_V_MF4
Definition riscv/opcodes.hpp:5062
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF4
@ PseudoVLUXSEG2EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:5858
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF8_MASK
@ PseudoVSUXSEG4EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:10968
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_MF8
@ PseudoVAESZ_VS_M8_MF8
Definition riscv/opcodes.hpp:786
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M1_E32_MASK
@ PseudoVFWMSAC_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3778
LIEF::assembly::riscv::OPCODE::C_EBREAK
@ C_EBREAK
Definition riscv/opcodes.hpp:12488
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF4
@ PseudoVMSLTU_VV_MF4
Definition riscv/opcodes.hpp:7174
LIEF::assembly::riscv::OPCODE::G_FASIN
@ G_FASIN
Definition riscv/opcodes.hpp:267
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF8
@ PseudoVMSLEU_VV_MF8
Definition riscv/opcodes.hpp:7105
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64VV_SE_M2
@ PseudoVC_FPR64VV_SE_M2
Definition riscv/opcodes.hpp:1112
LIEF::assembly::riscv::OPCODE::SW_AQ_RL
@ SW_AQ_RL
Definition riscv/opcodes.hpp:13018
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M1_MASK
@ PseudoVMSEQ_VI_M1_MASK
Definition riscv/opcodes.hpp:6953
LIEF::assembly::riscv::OPCODE::AMOOR_H_RL
@ AMOOR_H_RL
Definition riscv/opcodes.hpp:12078
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF2_E16_MASK
@ PseudoVFNMACC_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2624
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M2_E16
@ PseudoVFADD_VFPR16_M2_E16
Definition riscv/opcodes.hpp:1601
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M1_E32_MASK
@ PseudoVFMSAC_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2205
LIEF::assembly::riscv::OPCODE::VMSLTU_VV
@ VMSLTU_VV
Definition riscv/opcodes.hpp:13540
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF2
@ PseudoVRGATHEREI16_VV_MF2_E8_MF2
Definition riscv/opcodes.hpp:8412
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_MF2
@ PseudoVSSSEG5E32_V_MF2
Definition riscv/opcodes.hpp:10347
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M1
@ PseudoVLUXSEG4EI64_V_M2_M1
Definition riscv/opcodes.hpp:6036
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_MF8
@ PseudoVRELOAD7_MF8
Definition riscv/opcodes.hpp:8079
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF2_MASK
@ PseudoVSSE16_V_MF2_MASK
Definition riscv/opcodes.hpp:9956
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_M1
@ PseudoVSOXSEG7EI64_V_M4_M1
Definition riscv/opcodes.hpp:9725
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF4
@ PseudoVSUXSEG2EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:10785
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E8_MASK
@ PseudoVDIV_VX_M2_E8_MASK
Definition riscv/opcodes.hpp:1570
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M1_E32
@ PseudoVFSGNJN_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3133
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_M1_MASK
@ PseudoVSUXSEG5EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:11082
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF2
@ PseudoVFNCVT_RM_XU_F_W_MF2
Definition riscv/opcodes.hpp:2531
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E32
@ PseudoVREMU_VX_M4_E32
Definition riscv/opcodes.hpp:8146
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M2_MASK
@ PseudoVSOXEI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:9106
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF4
@ PseudoVLUXSEG4EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:6024
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M2_E64_MASK
@ PseudoVFMACC_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:1962
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E8
@ PseudoVREDMINU_VS_M2_E8
Definition riscv/opcodes.hpp:7846
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_MF2
@ PseudoVMSBC_VXM_MF2
Definition riscv/opcodes.hpp:6928
LIEF::assembly::riscv::OPCODE::VSOXSEG6EI32_V
@ VSOXSEG6EI32_V
Definition riscv/opcodes.hpp:13681
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E16_MASK
@ PseudoVDIVU_VX_M8_E16_MASK
Definition riscv/opcodes.hpp:1492
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E16
@ PseudoVFREDMIN_VS_M8_E16
Definition riscv/opcodes.hpp:2983
LIEF::assembly::riscv::OPCODE::ROLW
@ ROLW
Definition riscv/opcodes.hpp:12931
LIEF::assembly::riscv::OPCODE::VWREDSUM_VS
@ VWREDSUM_VS
Definition riscv/opcodes.hpp:13826
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M1_MASK
@ PseudoVMFLT_VV_M1_MASK
Definition riscv/opcodes.hpp:6773
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF4
@ PseudoVNSRA_WX_MF4
Definition riscv/opcodes.hpp:7586
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_M1
@ PseudoVLUXSEG4EI64_V_M1_M1
Definition riscv/opcodes.hpp:6028
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF4_MASK
@ PseudoVSOXSEG4EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9420
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M4_MASK
@ PseudoVMFLE_VFPR32_M4_MASK
Definition riscv/opcodes.hpp:6717
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M2
@ PseudoVSOXEI16_V_M1_M2
Definition riscv/opcodes.hpp:9001
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_MF2_MASK
@ PseudoVLUXSEG6EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6227
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M2_MASK
@ PseudoVFNCVT_RTZ_X_F_W_M2_MASK
Definition riscv/opcodes.hpp:2582
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E32_MASK
@ PseudoVFSGNJN_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3160
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M4
@ PseudoVMUL_VX_M4
Definition riscv/opcodes.hpp:7379
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF4_MASK
@ PseudoVSSSEG8E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10404
LIEF::assembly::riscv::OPCODE::G_PHI
@ G_PHI
Definition riscv/opcodes.hpp:88
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M4
@ PseudoVLOXSEG2EI64_V_M4_M4
Definition riscv/opcodes.hpp:4424
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_M1
@ PseudoVAESDF_VS_M2_M1
Definition riscv/opcodes.hpp:644
LIEF::assembly::riscv::OPCODE::FMVH_X_D
@ FMVH_X_D
Definition riscv/opcodes.hpp:12727
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_M2_MASK
@ PseudoVFNRCLIP_XU_F_QF_M2_MASK
Definition riscv/opcodes.hpp:2858
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M4
@ PseudoVFCVT_XU_F_V_M4
Definition riscv/opcodes.hpp:1843
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF2_MASK
@ PseudoVMIN_VX_MF2_MASK
Definition riscv/opcodes.hpp:6877
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M4
@ PseudoVLUXEI8_V_M4_M4
Definition riscv/opcodes.hpp:5696
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_M1_MASK
@ PseudoVLOXSEG5EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4731
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E64
@ PseudoVFREDOSUM_VS_M4_E64
Definition riscv/opcodes.hpp:3011
LIEF::assembly::riscv::OPCODE::TH_LWUIA
@ TH_LWUIA
Definition riscv/opcodes.hpp:13090
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M1
@ PseudoVSUXSEG3EI16_V_MF2_M1
Definition riscv/opcodes.hpp:10807
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF2_MASK
@ PseudoVSUXSEG7EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11184
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M2
@ PseudoVSUXSEG2EI32_V_M8_M2
Definition riscv/opcodes.hpp:10717
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF2
@ PseudoVNCLIPU_WI_MF2
Definition riscv/opcodes.hpp:7432
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E32_MASK
@ PseudoVFNCVT_F_X_W_M1_E32_MASK
Definition riscv/opcodes.hpp:2474
LIEF::assembly::riscv::OPCODE::VLSEG6E64FF_V
@ VLSEG6E64FF_V
Definition riscv/opcodes.hpp:13404
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E32_MASK
@ PseudoVREDXOR_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:8011
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF2_E16
@ PseudoVFNMSUB_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2803
LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_M2
@ PseudoVMORN_MM_M2
Definition riscv/opcodes.hpp:6897
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E32
@ PseudoVFSGNJN_VV_M1_E32
Definition riscv/opcodes.hpp:3153
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M2_MASK
@ PseudoVRGATHEREI16_VV_M4_E64_M2_MASK
Definition riscv/opcodes.hpp:8357
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF8_MASK
@ PseudoVAND_VX_MF8_MASK
Definition riscv/opcodes.hpp:859
LIEF::assembly::riscv::OPCODE::FCVT_D_W_IN32X
@ FCVT_D_W_IN32X
Definition riscv/opcodes.hpp:12588
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_MF2
@ PseudoVSSSEG4E32_V_MF2
Definition riscv/opcodes.hpp:10323
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M1_E32
@ PseudoVFWADD_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3461
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E32_MASK
@ PseudoVFWREDUSUM_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:3944
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E16_MASK
@ PseudoVDIVU_VX_M4_E16_MASK
Definition riscv/opcodes.hpp:1484
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32_TIED
@ PseudoVFWADD_WV_M1_E32_TIED
Definition riscv/opcodes.hpp:3512
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_M1_MASK
@ PseudoVLOXSEG2EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4397
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M4_E64
@ PseudoVFNMACC_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2641
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M1
@ PseudoVSOXSEG3EI16_V_M2_M1
Definition riscv/opcodes.hpp:9297
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E32_MASK
@ PseudoVFADD_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:1650
LIEF::assembly::riscv::OPCODE::QK_C_LBU
@ QK_C_LBU
Definition riscv/opcodes.hpp:12916
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M2
@ PseudoVLSEG4E8FF_V_M2
Definition riscv/opcodes.hpp:5220
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M2_MASK
@ PseudoVSUXSEG2EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:10718
LIEF::assembly::riscv::OPCODE::PseudoLA_TLS_IE
@ PseudoLA_TLS_IE
Definition riscv/opcodes.hpp:389
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M1_E16
@ PseudoVFSUB_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3391
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF8
@ PseudoVLOXSEG4EI64_V_M1_MF8
Definition riscv/opcodes.hpp:4642
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M2
@ PseudoVSOXSEG3EI8_V_M1_M2
Definition riscv/opcodes.hpp:9375
LIEF::assembly::riscv::OPCODE::CV_ADDUN
@ CV_ADDUN
Definition riscv/opcodes.hpp:12168
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_M1
@ PseudoVLOXSEG6EI8_V_MF8_M1
Definition riscv/opcodes.hpp:4842
LIEF::assembly::riscv::OPCODE::AMOMAXU_B_AQ_RL
@ AMOMAXU_B_AQ_RL
Definition riscv/opcodes.hpp:12005
LIEF::assembly::riscv::OPCODE::VSE16_V
@ VSE16_V
Definition riscv/opcodes.hpp:13630
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF4
@ PseudoVSSSEG7E16_V_MF4
Definition riscv/opcodes.hpp:10383
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E64
@ PseudoVFDIV_VV_M8_E64
Definition riscv/opcodes.hpp:1915
LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_M4
@ PseudoVMXOR_MM_M4
Definition riscv/opcodes.hpp:7421
LIEF::assembly::riscv::OPCODE::TH_DCACHE_CPA
@ TH_DCACHE_CPA
Definition riscv/opcodes.hpp:13033
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF8_MASK
@ PseudoVWSLL_VV_MF8_MASK
Definition riscv/opcodes.hpp:11706
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M2_MASK
@ PseudoTHVdotVMAQAU_VX_M2_MASK
Definition riscv/opcodes.hpp:493
LIEF::assembly::riscv::OPCODE::G_GET_FPENV
@ G_GET_FPENV
Definition riscv/opcodes.hpp:230
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF2_MASK
@ PseudoVSOXSEG3EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9314
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E32
@ PseudoVDIVU_VV_M1_E32
Definition riscv/opcodes.hpp:1425
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E64_MASK
@ PseudoVFREDMAX_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:2952
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_M1
@ PseudoVLUXSEG7EI16_V_MF2_M1
Definition riscv/opcodes.hpp:6248
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E64_V_M1_MASK
@ PseudoVSSEG7E64_V_M1_MASK
Definition riscv/opcodes.hpp:10134
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF8
@ PseudoVWSLL_VV_MF8
Definition riscv/opcodes.hpp:11705
LIEF::assembly::riscv::OPCODE::VREDMAX_VS
@ VREDMAX_VS
Definition riscv/opcodes.hpp:13596
LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M1_MASK
@ PseudoVSSE64_V_M1_MASK
Definition riscv/opcodes.hpp:9970
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF2
@ PseudoVMACC_VV_MF2
Definition riscv/opcodes.hpp:6410
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E64
@ PseudoVREDOR_VS_M4_E64
Definition riscv/opcodes.hpp:7940
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF2_MASK
@ PseudoVSUXSEG7EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:11226
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK
@ PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK
Definition riscv/opcodes.hpp:2524
LIEF::assembly::riscv::OPCODE::VMSLTU_VX
@ VMSLTU_VX
Definition riscv/opcodes.hpp:13541
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF4_E16_MASK
@ PseudoVFWNMSAC_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3884
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M4_M1_MASK
@ PseudoVSUXSEG7EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:11206
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E16_MASK
@ PseudoVREM_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:8211
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M8_MASK
@ PseudoVSADDU_VV_M8_MASK
Definition riscv/opcodes.hpp:8625
LIEF::assembly::riscv::OPCODE::AMOOR_H_AQ_RL
@ AMOOR_H_AQ_RL
Definition riscv/opcodes.hpp:12077
LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M2
@ PseudoVADC_VXM_M2
Definition riscv/opcodes.hpp:592
LIEF::assembly::riscv::OPCODE::VLUXSEG3EI16_V
@ VLUXSEG3EI16_V
Definition riscv/opcodes.hpp:13460
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M8_E16_MASK
@ PseudoVFADD_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:1606
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M8
@ PseudoVMACC_VV_M8
Definition riscv/opcodes.hpp:6408
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_MF4
@ PseudoVSBC_VVM_MF4
Definition riscv/opcodes.hpp:8693
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_M1_MASK
@ PseudoVSOXSEG8EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9752
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF2
@ PseudoVSUXEI8_V_MF4_MF2
Definition riscv/opcodes.hpp:10647
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_MF2
@ PseudoVSBC_VXM_MF2
Definition riscv/opcodes.hpp:8699
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M1_MASK
@ PseudoVRGATHEREI16_VV_M1_E8_M1_MASK
Definition riscv/opcodes.hpp:8299
LIEF::assembly::riscv::OPCODE::G_FNEARBYINT
@ G_FNEARBYINT
Definition riscv/opcodes.hpp:275
LIEF::assembly::riscv::OPCODE::G_UITOFP
@ G_UITOFP
Definition riscv/opcodes.hpp:219
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF8_MASK
@ PseudoVSUXSEG5EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:11054
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF4_MASK
@ PseudoVCPOP_V_MF4_MASK
Definition riscv/opcodes.hpp:1061
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E16_MASK
@ PseudoVREMU_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:8101
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E8_MASK
@ PseudoVWREDSUM_VS_MF2_E8_MASK
Definition riscv/opcodes.hpp:11676
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M8_MASK
@ PseudoTHVdotVMAQAUS_VX_M8_MASK
Definition riscv/opcodes.hpp:477
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M4_MASK
@ PseudoVSADD_VV_M4_MASK
Definition riscv/opcodes.hpp:8665
LIEF::assembly::riscv::OPCODE::FCVT_S_LU
@ FCVT_S_LU
Definition riscv/opcodes.hpp:12622
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M2
@ PseudoVSSEG4E32_V_M2
Definition riscv/opcodes.hpp:10065
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M1_E64_MASK
@ PseudoVFMADD_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2020
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF2_MASK
@ PseudoVLSEG2E16FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5061
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M2_MASK
@ PseudoVSSEG4E64_V_M2_MASK
Definition riscv/opcodes.hpp:10072
LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M1
@ PseudoVADC_VVM_M1
Definition riscv/opcodes.hpp:584
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF2
@ PseudoVMSLEU_VV_MF2
Definition riscv/opcodes.hpp:7101
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF2
@ PseudoVSOXSEG3EI32_V_M1_MF2
Definition riscv/opcodes.hpp:9323
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M4
@ PseudoVMULHU_VV_M4
Definition riscv/opcodes.hpp:7309
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF2
@ PseudoVSOXEI32_V_MF2_MF2
Definition riscv/opcodes.hpp:9073
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF4_MASK
@ PseudoVMUL_VV_MF4_MASK
Definition riscv/opcodes.hpp:7372
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B64_MASK
@ PseudoVMSIF_M_B64_MASK
Definition riscv/opcodes.hpp:7076
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF2
@ PseudoVSUXSEG2EI64_V_M2_MF2
Definition riscv/opcodes.hpp:10741
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF2
@ PseudoVFCVT_XU_F_V_MF2
Definition riscv/opcodes.hpp:1847
LIEF::assembly::riscv::OPCODE::VDIVU_VX
@ VDIVU_VX
Definition riscv/opcodes.hpp:13201
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF2
@ PseudoVSOXSEG2EI64_V_M2_MF2
Definition riscv/opcodes.hpp:9237
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF2
@ PseudoVMINU_VV_MF2
Definition riscv/opcodes.hpp:6834
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E32
@ PseudoVFRSQRT7_V_M2_E32
Definition riscv/opcodes.hpp:3069
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF8_MASK
@ PseudoVASUB_VX_MF8_MASK
Definition riscv/opcodes.hpp:915
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF2_MASK
@ PseudoVLSEG2E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5071
LIEF::assembly::riscv::OPCODE::VNMSUB_VX
@ VNMSUB_VX
Definition riscv/opcodes.hpp:13576
LIEF::assembly::riscv::OPCODE::FMAX_S
@ FMAX_S
Definition riscv/opcodes.hpp:12701
LIEF::assembly::riscv::OPCODE::DBG_VALUE_LIST
@ DBG_VALUE_LIST
Definition riscv/opcodes.hpp:38
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF4_E16
@ PseudoVFWMSAC_VV_MF4_E16
Definition riscv/opcodes.hpp:3801
LIEF::assembly::riscv::OPCODE::G_UNMERGE_VALUES
@ G_UNMERGE_VALUES
Definition riscv/opcodes.hpp:94
LIEF::assembly::riscv::OPCODE::PseudoCALL
@ PseudoCALL
Definition riscv/opcodes.hpp:336
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_M1
@ PseudoVLUXSEG6EI64_V_M2_M1
Definition riscv/opcodes.hpp:6210
LIEF::assembly::riscv::OPCODE::VLSEG8E8FF_V
@ VLSEG8E8FF_V
Definition riscv/opcodes.hpp:13422
LIEF::assembly::riscv::OPCODE::G_INDEXED_ZEXTLOAD
@ G_INDEXED_ZEXTLOAD
Definition riscv/opcodes.hpp:118
LIEF::assembly::riscv::OPCODE::VLUXSEG2EI64_V
@ VLUXSEG2EI64_V
Definition riscv/opcodes.hpp:13458
LIEF::assembly::riscv::OPCODE::G_SSHLSAT
@ G_SSHLSAT
Definition riscv/opcodes.hpp:187
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M2
@ PseudoVSRA_VX_M2
Definition riscv/opcodes.hpp:9893
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF2
@ PseudoVLOXSEG5EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:4758
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M1
@ PseudoVSLIDE1UP_VX_M1
Definition riscv/opcodes.hpp:8808
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF2_MASK
@ PseudoVSOXSEG5EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9526
LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D
@ SSAMOSWAP_D
Definition riscv/opcodes.hpp:13004
LIEF::assembly::riscv::OPCODE::MOPR14
@ MOPR14
Definition riscv/opcodes.hpp:12866
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M2_MASK
@ PseudoVMFGE_VFPR32_M2_MASK
Definition riscv/opcodes.hpp:6655
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M4
@ PseudoVLUXSEG2EI64_V_M4_M4
Definition riscv/opcodes.hpp:5816
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_MF2_MASK
@ PseudoVMFLT_VFPR32_MF2_MASK
Definition riscv/opcodes.hpp:6763
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_M1
@ PseudoVC_V_XVV_SE_M1
Definition riscv/opcodes.hpp:1349
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF2
@ PseudoVLSE16_V_MF2
Definition riscv/opcodes.hpp:5018
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF4
@ PseudoVSUXSEG3EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:10819
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF2_MASK
@ PseudoVLSEG5E8FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5265
LIEF::assembly::riscv::OPCODE::VSADDU_VV
@ VSADDU_VV
Definition riscv/opcodes.hpp:13623
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M1_E32_MASK
@ PseudoVFMADD_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2010
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_MF2
@ PseudoVC_V_FPR32VW_MF2
Definition riscv/opcodes.hpp:1216
LIEF::assembly::riscv::OPCODE::CV_MULHHSN
@ CV_MULHHSN
Definition riscv/opcodes.hpp:12371
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF8_MASK
@ PseudoVWMACCU_VV_MF8_MASK
Definition riscv/opcodes.hpp:11502
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M4
@ PseudoVAND_VV_M4
Definition riscv/opcodes.hpp:836
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E16_MASK
@ PseudoVREMU_VX_M4_E16_MASK
Definition riscv/opcodes.hpp:8145
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E32_MASK
@ PseudoVFWMSAC_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3796
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E32_MASK
@ PseudoVFREDUSUM_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:3028
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF2_MASK
@ PseudoVSOXSEG8EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9766
LIEF::assembly::riscv::OPCODE::PREFETCH_R
@ PREFETCH_R
Definition riscv/opcodes.hpp:12914
LIEF::assembly::riscv::OPCODE::InsnJ
@ InsnJ
Definition riscv/opcodes.hpp:12825
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF2
@ PseudoVSOXSEG4EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:9505
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF8_MASK
@ PseudoVMSGTU_VI_MF8_MASK
Definition riscv/opcodes.hpp:7022
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M4_MASK
@ PseudoVFNCVT_RTZ_XU_F_W_M4_MASK
Definition riscv/opcodes.hpp:2572
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M2_MASK
@ PseudoVMSLT_VX_M2_MASK
Definition riscv/opcodes.hpp:7210
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E16
@ PseudoVFWCVT_F_XU_V_MF4_E16
Definition riscv/opcodes.hpp:3601
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF8
@ PseudoVFNCVT_RTZ_X_F_W_MF8
Definition riscv/opcodes.hpp:2589
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M1
@ PseudoVMFGE_VFPR64_M1
Definition riscv/opcodes.hpp:6662
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_MF2_MASK
@ PseudoVSOXSEG8EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9780
LIEF::assembly::riscv::OPCODE::FCVT_WU_D_IN32X
@ FCVT_WU_D_IN32X
Definition riscv/opcodes.hpp:12630
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF4_E16_MASK
@ PseudoVFSGNJ_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3300
LIEF::assembly::riscv::OPCODE::CV_ADD_B
@ CV_ADD_B
Definition riscv/opcodes.hpp:12172
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_M1
@ PseudoVLOXSEG2EI8_V_MF8_M1
Definition riscv/opcodes.hpp:4462
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK
@ PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK
Definition riscv/opcodes.hpp:2562
LIEF::assembly::riscv::OPCODE::TH_FLURW
@ TH_FLURW
Definition riscv/opcodes.hpp:13049
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_M1
@ PseudoVSUXSEG6EI8_V_MF4_M1
Definition riscv/opcodes.hpp:11161
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M1
@ PseudoVSOXSEG3EI64_V_M4_M1
Definition riscv/opcodes.hpp:9363
LIEF::assembly::riscv::OPCODE::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
@ G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
Definition riscv/opcodes.hpp:148
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK
@ PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK
Definition riscv/opcodes.hpp:3310
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF4_MASK
@ PseudoVLE16_V_MF4_MASK
Definition riscv/opcodes.hpp:4106
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M4_M1_MASK
@ PseudoVSUXSEG5EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:11046
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_M1_MASK
@ PseudoVSOXSEG5EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9566
LIEF::assembly::riscv::OPCODE::HLVX_HU
@ HLVX_HU
Definition riscv/opcodes.hpp:12798
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M1
@ PseudoVBREV_V_M1
Definition riscv/opcodes.hpp:930
LIEF::assembly::riscv::OPCODE::TH_DCACHE_CVAL1
@ TH_DCACHE_CVAL1
Definition riscv/opcodes.hpp:13037
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_MF8
@ PseudoVMSBC_VVM_MF8
Definition riscv/opcodes.hpp:6916
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M2_MASK
@ PseudoVLUXSEG3EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:5877
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF8_MASK
@ PseudoVBREV_V_MF8_MASK
Definition riscv/opcodes.hpp:943
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_M1_MASK
@ PseudoVSOXSEG7EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9692
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_M1
@ PseudoVLUXEI64_V_M1_M1
Definition riscv/opcodes.hpp:5650
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF4_MASK
@ PseudoVLUXSEG8EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:6339
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M1
@ PseudoVLUXSEG2EI8_V_M1_M1
Definition riscv/opcodes.hpp:5826
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF8
@ PseudoVLOXSEG4EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:4688
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E32_MASK
@ PseudoVREM_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:8199
LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_MF8
@ PseudoVC_X_SE_MF8
Definition riscv/opcodes.hpp:1422
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M4_MASK
@ PseudoVNMSUB_VX_M4_MASK
Definition riscv/opcodes.hpp:7545
LIEF::assembly::riscv::OPCODE::PseudoCCSUBW
@ PseudoCCSUBW
Definition riscv/opcodes.hpp:365
LIEF::assembly::riscv::OPCODE::VSE64_V
@ VSE64_V
Definition riscv/opcodes.hpp:13632
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF2
@ PseudoVLUXSEG6EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:6230
LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ_DIV2
@ CV_SUBROTMJ_DIV2
Definition riscv/opcodes.hpp:12448
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF2_MASK
@ PseudoVLOXEI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4253
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E64
@ PseudoVFNMADD_VV_M1_E64
Definition riscv/opcodes.hpp:2709
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF4
@ PseudoVLUXSEG2EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:5752
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M4
@ PseudoVSEXT_VF2_M4
Definition riscv/opcodes.hpp:8753
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M4
@ PseudoVSLIDE1DOWN_VX_M4
Definition riscv/opcodes.hpp:8798
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF2_MASK
@ PseudoVWMACCSU_VV_MF2_MASK
Definition riscv/opcodes.hpp:11462
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF4_MASK
@ PseudoVLE16FF_V_MF4_MASK
Definition riscv/opcodes.hpp:4094
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M1_MASK
@ PseudoVMFNE_VFPR64_M1_MASK
Definition riscv/opcodes.hpp:6807
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_M1
@ PseudoVSUXSEG5EI32_V_M2_M1
Definition riscv/opcodes.hpp:11041
LIEF::assembly::riscv::OPCODE::G_ASHR
@ G_ASHR
Definition riscv/opcodes.hpp:160
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M8_MASK
@ PseudoVIOTA_M_M8_MASK
Definition riscv/opcodes.hpp:4076
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E32
@ PseudoVFREDMAX_VS_M8_E32
Definition riscv/opcodes.hpp:2955
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF8
@ PseudoVMSLTU_VV_MF8
Definition riscv/opcodes.hpp:7176
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M8
@ PseudoVSSRL_VX_M8
Definition riscv/opcodes.hpp:10239
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B4_MASK
@ PseudoVMSOF_M_B4_MASK
Definition riscv/opcodes.hpp:7272
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M1
@ PseudoVNSRL_WI_M1
Definition riscv/opcodes.hpp:7590
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF4_E16_MASK
@ PseudoVFWMUL_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3838
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E16
@ PseudoVFWMUL_VV_M4_E16
Definition riscv/opcodes.hpp:3829
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF2_MASK
@ PseudoVSSEG3E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10032
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M2
@ PseudoVSSEG2E32_V_M2
Definition riscv/opcodes.hpp:10003
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M1_E16
@ PseudoVFMIN_VFPR16_M1_E16
Definition riscv/opcodes.hpp:2132
LIEF::assembly::riscv::OPCODE::VWMULU_VX
@ VWMULU_VX
Definition riscv/opcodes.hpp:13822
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_M1
@ PseudoVSOXSEG2EI16_V_MF4_M1
Definition riscv/opcodes.hpp:9183
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M1
@ PseudoVSADDU_VV_M1
Definition riscv/opcodes.hpp:8618
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF4
@ PseudoVWMULSU_VV_MF4
Definition riscv/opcodes.hpp:11547
LIEF::assembly::riscv::OPCODE::VMADC_VV
@ VMADC_VV
Definition riscv/opcodes.hpp:13488
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M1
@ PseudoVLUXEI16_V_M1_M1
Definition riscv/opcodes.hpp:5570
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M4_E32
@ PseudoVFWNMSAC_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3889
LIEF::assembly::riscv::OPCODE::PseudoSW
@ PseudoSW
Definition riscv/opcodes.hpp:446
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_MF4
@ PseudoVC_V_IVV_MF4
Definition riscv/opcodes.hpp:1253
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF8_E8_MASK
@ PseudoVDIV_VX_MF8_E8_MASK
Definition riscv/opcodes.hpp:1598
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B2_MASK
@ PseudoVCPOP_M_B2_MASK
Definition riscv/opcodes.hpp:1041
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_M4
@ PseudoVC_V_XV_M4
Definition riscv/opcodes.hpp:1370
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF4
@ PseudoVWSLL_VV_MF4
Definition riscv/opcodes.hpp:11703
LIEF::assembly::riscv::OPCODE::CV_SRA_SCI_H
@ CV_SRA_SCI_H
Definition riscv/opcodes.hpp:12434
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E32
@ PseudoVFSGNJX_VV_M1_E32
Definition riscv/opcodes.hpp:3213
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M2
@ PseudoVMSLE_VI_M2
Definition riscv/opcodes.hpp:7123
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M8_MASK
@ PseudoVFSLIDE1UP_VFPR64_M8_MASK
Definition riscv/opcodes.hpp:3360
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E16
@ PseudoVFWSUB_VV_MF2_E16
Definition riscv/opcodes.hpp:3985
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M4
@ PseudoVMSGT_VI_M4
Definition riscv/opcodes.hpp:7041
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_M1
@ PseudoVLSSEG5E16_V_M1
Definition riscv/opcodes.hpp:5490
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_M1_M1_MASK
@ PseudoVLOXSEG6EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4831
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF4
@ PseudoVMSLEU_VV_MF4
Definition riscv/opcodes.hpp:7103
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M4
@ PseudoVSSUB_VX_M4
Definition riscv/opcodes.hpp:10465
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M1_MASK
@ PseudoVSUXEI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:10644
LIEF::assembly::riscv::OPCODE::G_INSERT_VECTOR_ELT
@ G_INSERT_VECTOR_ELT
Definition riscv/opcodes.hpp:250
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M8
@ PseudoVRSUB_VX_M8
Definition riscv/opcodes.hpp:8596
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_M1
@ PseudoVSSEG7E8_V_M1
Definition riscv/opcodes.hpp:10135
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M4_MASK
@ PseudoVLOXEI16_V_M2_M4_MASK
Definition riscv/opcodes.hpp:4191
LIEF::assembly::riscv::OPCODE::TH_SHIB
@ TH_SHIB
Definition riscv/opcodes.hpp:13109
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_M1_MASK
@ PseudoVLOXSEG5EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4717
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF8_MASK
@ PseudoVCLMUL_VV_MF8_MASK
Definition riscv/opcodes.hpp:985
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M4_MASK
@ PseudoVADD_VI_M4_MASK
Definition riscv/opcodes.hpp:603
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_MF2
@ PseudoVAESEM_VS_M4_MF2
Definition riscv/opcodes.hpp:739
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF2
@ PseudoVSUXSEG6EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:11103
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF8_E8
@ PseudoVREDXOR_VS_MF8_E8
Definition riscv/opcodes.hpp:8050
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF4_MASK
@ PseudoVWADD_WX_MF4_MASK
Definition riscv/opcodes.hpp:11452
LIEF::assembly::riscv::OPCODE::G_FMAXIMUM
@ G_FMAXIMUM
Definition riscv/opcodes.hpp:229
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E64_V_M1_MASK
@ PseudoVSSEG6E64_V_M1_MASK
Definition riscv/opcodes.hpp:10114
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E16_MASK
@ PseudoVFSGNJ_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:3290
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E16_MASK
@ PseudoVREDMAXU_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:7769
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF2_MASK
@ PseudoVSUXSEG3EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10846
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF2
@ PseudoVCTZ_V_MF2
Definition riscv/opcodes.hpp:1072
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF4_MASK
@ PseudoVLUXSEG4EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:5997
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF2_MASK
@ PseudoVLSEG5E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5273
LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_M1
@ PseudoVC_IVV_SE_M1
Definition riscv/opcodes.hpp:1119
LIEF::assembly::riscv::OPCODE::CV_PACK
@ CV_PACK
Definition riscv/opcodes.hpp:12385
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF4_MASK
@ PseudoVSRA_VV_MF4_MASK
Definition riscv/opcodes.hpp:9888
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M4
@ PseudoVCLMULH_VX_M4
Definition riscv/opcodes.hpp:962
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M2_MASK
@ PseudoVSADDU_VX_M2_MASK
Definition riscv/opcodes.hpp:8635
LIEF::assembly::riscv::OPCODE::VMSBC_VX
@ VMSBC_VX
Definition riscv/opcodes.hpp:13523
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF4_E16_MASK
@ PseudoVFWNMACC_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3848
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E16
@ PseudoVFWCVT_F_XU_V_M4_E16
Definition riscv/opcodes.hpp:3589
LIEF::assembly::riscv::OPCODE::G_FPOW
@ G_FPOW
Definition riscv/opcodes.hpp:203
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M8_M4
@ PseudoVSOXSEG2EI16_V_M8_M4
Definition riscv/opcodes.hpp:9173
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF2
@ PseudoVSUXEI32_V_M1_MF2
Definition riscv/opcodes.hpp:10549
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M8
@ PseudoVMSLE_VV_M8
Definition riscv/opcodes.hpp:7141
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M1_MASK
@ PseudoVSRL_VI_M1_MASK
Definition riscv/opcodes.hpp:9906
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M8
@ PseudoVMFLT_VFPR32_M8
Definition riscv/opcodes.hpp:6760
LIEF::assembly::riscv::OPCODE::THVdotVMAQASU_VV
@ THVdotVMAQASU_VV
Definition riscv/opcodes.hpp:13020
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E32
@ PseudoVFWREDUSUM_VS_M4_E32
Definition riscv/opcodes.hpp:3943
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_MF2
@ PseudoVLUXEI64_V_M4_MF2
Definition riscv/opcodes.hpp:5672
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF8
@ PseudoVLUXSEG7EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:6280
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF4
@ PseudoVSSSEG3E16_V_MF4
Definition riscv/opcodes.hpp:10289
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF2_MASK
@ PseudoVWMACC_VV_MF2_MASK
Definition riscv/opcodes.hpp:11522
LIEF::assembly::riscv::OPCODE::VAESDF_VS
@ VAESDF_VS
Definition riscv/opcodes.hpp:13141
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M8_MASK
@ PseudoVFCVT_X_F_V_M8_MASK
Definition riscv/opcodes.hpp:1858
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M2
@ PseudoVSUXSEG4EI16_V_M1_M2
Definition riscv/opcodes.hpp:10907
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E32_MASK
@ PseudoVFREDMAX_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:2956
LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M1
@ PseudoVSSE32_V_M1
Definition riscv/opcodes.hpp:9959
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M2
@ PseudoVFCVT_RM_X_F_V_M2
Definition riscv/opcodes.hpp:1805
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E16
@ PseudoVFWCVTBF16_F_F_V_MF2_E16
Definition riscv/opcodes.hpp:3553
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E64_MASK
@ PseudoVREM_VX_M2_E64_MASK
Definition riscv/opcodes.hpp:8229
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M4_E16_MASK
@ PseudoVFWMUL_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3808
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M1_MASK
@ PseudoVXOR_VX_M1_MASK
Definition riscv/opcodes.hpp:11868
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF4_MASK
@ PseudoVSSRL_VV_MF4_MASK
Definition riscv/opcodes.hpp:10230
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E64
@ PseudoVFREC7_V_M4_E64
Definition riscv/opcodes.hpp:2921
LIEF::assembly::riscv::OPCODE::PseudoFSH
@ PseudoFSH
Definition riscv/opcodes.hpp:382
LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_M2
@ PseudoVC_X_SE_M2
Definition riscv/opcodes.hpp:1417
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_M1
@ PseudoVSUXSEG5EI16_V_MF2_M1
Definition riscv/opcodes.hpp:11021
LIEF::assembly::riscv::OPCODE::FMUL_D_INX
@ FMUL_D_INX
Definition riscv/opcodes.hpp:12722
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_M1_MASK
@ PseudoVLOXSEG8EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4979
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M8
@ PseudoVSUXEI64_V_M8_M8
Definition riscv/opcodes.hpp:10613
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF8_MASK
@ PseudoVMSEQ_VX_MF8_MASK
Definition riscv/opcodes.hpp:6993
LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_M8
@ PseudoVMORN_MM_M8
Definition riscv/opcodes.hpp:6899
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF2_MASK
@ PseudoVLOXSEG3EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4539
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2_MASK
@ PseudoVWSUB_WV_M2_MASK
Definition riscv/opcodes.hpp:11808
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M2_E32_MASK
@ PseudoVFWMUL_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3816
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF2_MASK
@ PseudoVFNRCLIP_X_F_QF_MF2_MASK
Definition riscv/opcodes.hpp:2870
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF8_E8_MASK
@ PseudoVREDMAX_VS_MF8_E8_MASK
Definition riscv/opcodes.hpp:7831
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M2
@ PseudoVSUXEI16_V_M4_M2
Definition riscv/opcodes.hpp:10519
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M4_MASK
@ PseudoVSE16_V_M4_MASK
Definition riscv/opcodes.hpp:8707
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF4
@ PseudoVLOXSEG3EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:4494
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF4
@ PseudoVMFLT_VFPR16_MF4
Definition riscv/opcodes.hpp:6752
LIEF::assembly::riscv::OPCODE::LH_AQ
@ LH_AQ
Definition riscv/opcodes.hpp:12841
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_MF2_E32
@ PseudoVFWSUB_WFPR32_MF2_E32
Definition riscv/opcodes.hpp:4007
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M2_MASK
@ PseudoVMFLE_VFPR32_M2_MASK
Definition riscv/opcodes.hpp:6715
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_MF4
@ PseudoVC_V_I_MF4
Definition riscv/opcodes.hpp:1293
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E8_MASK
@ PseudoVREM_VX_M2_E8_MASK
Definition riscv/opcodes.hpp:8231
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B16
@ PseudoVMSOF_M_B16
Definition riscv/opcodes.hpp:7264
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF4
@ PseudoVSOXSEG8EI64_V_M1_MF4
Definition riscv/opcodes.hpp:9795
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M1_MASK
@ PseudoVLOXSEG3EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4499
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M2
@ PseudoVSLIDEUP_VI_M2
Definition riscv/opcodes.hpp:8852
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M8_MASK
@ PseudoVCLMUL_VX_M8_MASK
Definition riscv/opcodes.hpp:993
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M4
@ PseudoVAESDF_VV_M4
Definition riscv/opcodes.hpp:666
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M2
@ PseudoVLOXSEG3EI8_V_MF4_M2
Definition riscv/opcodes.hpp:4566
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M2
@ PseudoVSOXSEG2EI32_V_M4_M2
Definition riscv/opcodes.hpp:9209
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E32
@ PseudoVFMADD_VV_M4_E32
Definition riscv/opcodes.hpp:2041
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF8_MASK
@ PseudoVLUXSEG6EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:6181
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M4
@ PseudoVMADC_VI_M4
Definition riscv/opcodes.hpp:6439
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF8
@ PseudoVNCLIPU_WX_MF8
Definition riscv/opcodes.hpp:7460
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF8_MASK
@ PseudoVROR_VI_MF8_MASK
Definition riscv/opcodes.hpp:8547
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M8_E16_MASK
@ PseudoVFMUL_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2319
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E64_MASK
@ PseudoVREDSUM_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:7985
LIEF::assembly::riscv::OPCODE::TH_LURD
@ TH_LURD
Definition riscv/opcodes.hpp:13081
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF8_MASK
@ PseudoVMADD_VX_MF8_MASK
Definition riscv/opcodes.hpp:6499
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E32_MASK
@ PseudoVFREC7_V_M2_E32_MASK
Definition riscv/opcodes.hpp:2914
LIEF::assembly::riscv::OPCODE::CV_LB_ri_inc
@ CV_LB_ri_inc
Definition riscv/opcodes.hpp:12321
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E64
@ PseudoVDIVU_VV_M2_E64
Definition riscv/opcodes.hpp:1435
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E32_MASK
@ PseudoVFNCVT_F_X_W_MF2_E32_MASK
Definition riscv/opcodes.hpp:2486
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_M1
@ PseudoVLOXSEG6EI32_V_M1_M1
Definition riscv/opcodes.hpp:4790
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_SE_M4
@ PseudoVC_V_FPR32V_SE_M4
Definition riscv/opcodes.hpp:1229
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF4_MASK
@ PseudoVSOXSEG4EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9502
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M1
@ PseudoVSEXT_VF2_M1
Definition riscv/opcodes.hpp:8749
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_MF2_MASK
@ PseudoTHVdotVMAQA_VX_MF2_MASK
Definition riscv/opcodes.hpp:519
LIEF::assembly::riscv::OPCODE::VXOR_VI
@ VXOR_VI
Definition riscv/opcodes.hpp:13838
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E64
@ PseudoVREDMAX_VS_M4_E64
Definition riscv/opcodes.hpp:7808
LIEF::assembly::riscv::OPCODE::FROUNDNX_H
@ FROUNDNX_H
Definition riscv/opcodes.hpp:12751
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M4_MASK
@ PseudoVSSRA_VX_M4_MASK
Definition riscv/opcodes.hpp:10196
LIEF::assembly::riscv::OPCODE::VLSEG2E8FF_V
@ VLSEG2E8FF_V
Definition riscv/opcodes.hpp:13374
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M2
@ PseudoVASUBU_VV_M2
Definition riscv/opcodes.hpp:862
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_MF2
@ PseudoVLUXSEG3EI64_V_M4_MF2
Definition riscv/opcodes.hpp:5938
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF2
@ PseudoVLSEG6E8FF_V_MF2
Definition riscv/opcodes.hpp:5304
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M4_E32_MASK
@ PseudoVFDIV_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:1880
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E32
@ PseudoVREDXOR_VS_M8_E32
Definition riscv/opcodes.hpp:8034
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M1
@ PseudoVFWCVT_RTZ_X_F_V_M1
Definition riscv/opcodes.hpp:3667
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M1_E32
@ PseudoVFSGNJ_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3253
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF2
@ PseudoVSUXSEG3EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:10893
LIEF::assembly::riscv::OPCODE::C_JAL
@ C_JAL
Definition riscv/opcodes.hpp:12498
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M8_M4_MASK
@ PseudoVSOXSEG2EI16_V_M8_M4_MASK
Definition riscv/opcodes.hpp:9174
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M2
@ PseudoVLOXEI8_V_MF2_M2
Definition riscv/opcodes.hpp:4312
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF2_MASK
@ PseudoVFSLIDE1UP_VFPR16_MF2_MASK
Definition riscv/opcodes.hpp:3340
LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_M2
@ PseudoVC_XV_SE_M2
Definition riscv/opcodes.hpp:1410
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF2
@ PseudoVMSLEU_VX_MF2
Definition riscv/opcodes.hpp:7115
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M1_MASK
@ PseudoVFNCVT_X_F_W_M1_MASK
Definition riscv/opcodes.hpp:2604
LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B8
@ PseudoVMCLR_M_B8
Definition riscv/opcodes.hpp:6576
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E64
@ PseudoVFREDOSUM_VS_M1_E64
Definition riscv/opcodes.hpp:2999
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M1_MASK
@ PseudoVWMACCSU_VV_M1_MASK
Definition riscv/opcodes.hpp:11456
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF4
@ PseudoVSUXSEG6EI64_V_M1_MF4
Definition riscv/opcodes.hpp:11139
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M4
@ PseudoVLUXSEG2EI16_V_M1_M4
Definition riscv/opcodes.hpp:5730
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M1_E64_MASK
@ PseudoVFMIN_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2155
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_MF2
@ PseudoVC_V_FPR32V_MF2
Definition riscv/opcodes.hpp:1226
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E16
@ PseudoVFNCVT_ROD_F_F_W_M4_E16
Definition riscv/opcodes.hpp:2557
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF2_MASK
@ PseudoVASUB_VX_MF2_MASK
Definition riscv/opcodes.hpp:911
LIEF::assembly::riscv::OPCODE::G_ATOMIC_CMPXCHG_WITH_SUCCESS
@ G_ATOMIC_CMPXCHG_WITH_SUCCESS
Definition riscv/opcodes.hpp:121
LIEF::assembly::riscv::OPCODE::VMFGT_VF
@ VMFGT_VF
Definition riscv/opcodes.hpp:13506
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E16_MASK
@ PseudoVFNMSAC_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:2778
LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M8
@ PseudoVGMUL_VV_M8
Definition riscv/opcodes.hpp:4053
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_M1
@ PseudoVLSEG6E8_V_M1
Definition riscv/opcodes.hpp:5310
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M2_MASK
@ PseudoVSSSEG4E8_V_M2_MASK
Definition riscv/opcodes.hpp:10332
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M8_MASK
@ PseudoVSMUL_VX_M8_MASK
Definition riscv/opcodes.hpp:8985
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M2_MASK
@ PseudoVANDN_VX_M2_MASK
Definition riscv/opcodes.hpp:807
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M1
@ PseudoVLOXSEG2EI64_V_M2_M1
Definition riscv/opcodes.hpp:4412
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_M8
@ PseudoVC_V_FPR32V_M8
Definition riscv/opcodes.hpp:1225
LIEF::assembly::riscv::OPCODE::G_CTPOP
@ G_CTPOP
Definition riscv/opcodes.hpp:259
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_M4
@ PseudoVAESDF_VS_M8_M4
Definition riscv/opcodes.hpp:657
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M8
@ PseudoVLOXEI16_V_M4_M8
Definition riscv/opcodes.hpp:4198
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_MF2_MASK
@ PseudoVLOXSEG4EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4673
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_M1
@ PseudoVSOXSEG4EI32_V_MF2_M1
Definition riscv/opcodes.hpp:9449
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_MF4
@ PseudoVC_V_XVW_SE_MF4
Definition riscv/opcodes.hpp:1366
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M4_E16
@ PseudoVFNMSUB_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2799
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M8_M2_MASK
@ PseudoVLOXSEG3EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:4517
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M8_M1_MASK
@ PseudoVSUXSEG6EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:11154
LIEF::assembly::riscv::OPCODE::VFSGNJX_VV
@ VFSGNJX_VV
Definition riscv/opcodes.hpp:13264
LIEF::assembly::riscv::OPCODE::G_LSHR
@ G_LSHR
Definition riscv/opcodes.hpp:159
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_M1_MASK
@ PseudoVSOXSEG8EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9806
LIEF::assembly::riscv::OPCODE::SC_D_RL
@ SC_D_RL
Definition riscv/opcodes.hpp:12942
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M2_MASK
@ PseudoVLSSEG2E8_V_M2_MASK
Definition riscv/opcodes.hpp:5425
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M1
@ PseudoVLSEG4E16_V_M1
Definition riscv/opcodes.hpp:5190
LIEF::assembly::riscv::OPCODE::PseudoCCADD
@ PseudoCCADD
Definition riscv/opcodes.hpp:340
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E32
@ PseudoVFREDMIN_VS_M2_E32
Definition riscv/opcodes.hpp:2973
LIEF::assembly::riscv::OPCODE::VLSEG6E16FF_V
@ VLSEG6E16FF_V
Definition riscv/opcodes.hpp:13400
LIEF::assembly::riscv::OPCODE::VSUXSEG3EI8_V
@ VSUXSEG3EI8_V
Definition riscv/opcodes.hpp:13781
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E16
@ PseudoVFSQRT_V_M1_E16
Definition riscv/opcodes.hpp:3361
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF4_MASK
@ PseudoVMSLT_VV_MF4_MASK
Definition riscv/opcodes.hpp:7204
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E64_MASK
@ PseudoVFNMSAC_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:2788
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_M1
@ PseudoVSSSEG7E32_V_M1
Definition riscv/opcodes.hpp:10385
LIEF::assembly::riscv::OPCODE::TH_SDIB
@ TH_SDIB
Definition riscv/opcodes.hpp:13106
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M8_MASK
@ PseudoVLOXEI32_V_M4_M8_MASK
Definition riscv/opcodes.hpp:4243
LIEF::assembly::riscv::OPCODE::VLSSEG3E16_V
@ VLSSEG3E16_V
Definition riscv/opcodes.hpp:13428
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M2_MASK
@ PseudoVROR_VI_M2_MASK
Definition riscv/opcodes.hpp:8537
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E16_MASK
@ PseudoVFSGNJ_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3278
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_MF4
@ PseudoVC_V_XV_SE_MF4
Definition riscv/opcodes.hpp:1380
LIEF::assembly::riscv::OPCODE::TH_ICACHE_IVA
@ TH_ICACHE_IVA
Definition riscv/opcodes.hpp:13057
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF4_MASK
@ PseudoVLUXSEG8EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:6375
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M1_E16
@ PseudoVFRSUB_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3091
LIEF::assembly::riscv::OPCODE::VLSSEG5E8_V
@ VLSSEG5E8_V
Definition riscv/opcodes.hpp:13439
LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_M2
@ PseudoVMANDN_MM_M2
Definition riscv/opcodes.hpp:6501
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF8_MASK
@ PseudoVSOXSEG6EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:9670
LIEF::assembly::riscv::OPCODE::BGE
@ BGE
Definition riscv/opcodes.hpp:12124
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF2
@ PseudoVFNRCLIP_X_F_QF_MF2
Definition riscv/opcodes.hpp:2869
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF2
@ PseudoVMSNE_VX_MF2
Definition riscv/opcodes.hpp:7257
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M2_E64
@ PseudoVFMSAC_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2216
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF4_MASK
@ PseudoVLUXSEG4EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:6025
LIEF::assembly::riscv::OPCODE::SHA512SIG1
@ SHA512SIG1
Definition riscv/opcodes.hpp:12972
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M4
@ PseudoVNSRL_WX_M4
Definition riscv/opcodes.hpp:7618
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M2_E16
@ PseudoVFSGNJN_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3123
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF2
@ PseudoVSSE8_V_MF2
Definition riscv/opcodes.hpp:9985
LIEF::assembly::riscv::OPCODE::VLSEG4E8_V
@ VLSEG4E8_V
Definition riscv/opcodes.hpp:13391
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_M1_MASK
@ PseudoVSOXEI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9080
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_M1_MASK
@ PseudoVLSEG6E8_V_M1_MASK
Definition riscv/opcodes.hpp:5311
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M8_MASK
@ PseudoVROL_VV_M8_MASK
Definition riscv/opcodes.hpp:8513
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK
@ PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK
Definition riscv/opcodes.hpp:8417
LIEF::assembly::riscv::OPCODE::CV_MINU
@ CV_MINU
Definition riscv/opcodes.hpp:12357
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M8_MASK
@ PseudoVMACC_VV_M8_MASK
Definition riscv/opcodes.hpp:6409
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_M1
@ PseudoVLUXSEG6EI64_V_M1_M1
Definition riscv/opcodes.hpp:6202
LIEF::assembly::riscv::OPCODE::VSSSEG8E16_V
@ VSSSEG8E16_V
Definition riscv/opcodes.hpp:13760
LIEF::assembly::riscv::OPCODE::G_SEXT_INREG
@ G_SEXT_INREG
Definition riscv/opcodes.hpp:156
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF8_MASK
@ PseudoVLOXSEG3EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:4533
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M1_MASK
@ PseudoVADD_VV_M1_MASK
Definition riscv/opcodes.hpp:613
LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SCI_H
@ CV_SDOTSP_SCI_H
Definition riscv/opcodes.hpp:12396
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E64
@ PseudoVDIVU_VX_M8_E64
Definition riscv/opcodes.hpp:1495
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M4_MASK
@ PseudoVSLIDEUP_VI_M4_MASK
Definition riscv/opcodes.hpp:8855
LIEF::assembly::riscv::OPCODE::VFDIV_VV
@ VFDIV_VV
Definition riscv/opcodes.hpp:13214
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E64
@ PseudoVFMSUB_VV_M1_E64
Definition riscv/opcodes.hpp:2286
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E64
@ PseudoVFREC7_V_M8_E64
Definition riscv/opcodes.hpp:2927
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_M1
@ PseudoVSSSEG8E16_V_M1
Definition riscv/opcodes.hpp:10399
LIEF::assembly::riscv::OPCODE::SHA512SUM1R
@ SHA512SUM1R
Definition riscv/opcodes.hpp:12978
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M2_E32_MASK
@ PseudoVFMSAC_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2207
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF4
@ PseudoVLSEG3E16_V_MF4
Definition riscv/opcodes.hpp:5140
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E32
@ PseudoVDIV_VV_M8_E32
Definition riscv/opcodes.hpp:1537
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M1
@ PseudoVMFLT_VFPR64_M1
Definition riscv/opcodes.hpp:6764
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF2_MASK
@ PseudoVSSRL_VI_MF2_MASK
Definition riscv/opcodes.hpp:10214
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_MF4
@ PseudoVFMV_S_FPR16_MF4
Definition riscv/opcodes.hpp:2392
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF8
@ PseudoVSOXSEG7EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:9709
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF4_MASK
@ PseudoVSOXSEG8EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9788
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF8
@ PseudoVLUXSEG4EI64_V_M1_MF8
Definition riscv/opcodes.hpp:6034
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M1
@ PseudoVRGATHEREI16_VV_M4_E32_M1
Definition riscv/opcodes.hpp:8346
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF2_MASK
@ PseudoVSSSEG8E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10402
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF8
@ PseudoVAADD_VV_MF8
Definition riscv/opcodes.hpp:561
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF2
@ PseudoVSUXSEG3EI64_V_M2_MF2
Definition riscv/opcodes.hpp:10863
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_M1
@ PseudoVSOXSEG8EI32_V_MF2_M1
Definition riscv/opcodes.hpp:9783
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E32_MASK
@ PseudoVFSQRT_V_M1_E32_MASK
Definition riscv/opcodes.hpp:3364
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M2
@ PseudoVNSRL_WX_M2
Definition riscv/opcodes.hpp:7616
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_MF2
@ PseudoVAESEF_VS_M4_MF2
Definition riscv/opcodes.hpp:710
LIEF::assembly::riscv::OPCODE::FLI_D
@ FLI_D
Definition riscv/opcodes.hpp:12672
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M8_E64_MASK
@ PseudoVFRSUB_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:3120
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M2_MASK
@ PseudoVSOXSEG2EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9262
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E32
@ PseudoVFMSUB_VV_M1_E32
Definition riscv/opcodes.hpp:2284
LIEF::assembly::riscv::OPCODE::AMOADD_B
@ AMOADD_B
Definition riscv/opcodes.hpp:11947
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF4_MASK
@ PseudoVLOXSEG5EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4735
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M1
@ PseudoVFMERGE_VFPR16M_M1
Definition riscv/opcodes.hpp:2117
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E32
@ PseudoVFREDMAX_VS_M2_E32
Definition riscv/opcodes.hpp:2943
LIEF::assembly::riscv::OPCODE::VFNMACC_VV
@ VFNMACC_VV
Definition riscv/opcodes.hpp:13244
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M2_MASK
@ PseudoVSSUB_VV_M2_MASK
Definition riscv/opcodes.hpp:10450
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF8_E8
@ PseudoVREMU_VV_MF8_E8
Definition riscv/opcodes.hpp:8126
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M2
@ PseudoVMFNE_VFPR16_M2
Definition riscv/opcodes.hpp:6786
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M4_MASK
@ PseudoVWADDU_VV_M4_MASK
Definition riscv/opcodes.hpp:11340
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E16_MASK
@ PseudoVDIV_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:1550
LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_MF2
@ PseudoVADC_VXM_MF2
Definition riscv/opcodes.hpp:595
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16_MASK
@ PseudoVFWADD_WV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3538
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M2
@ PseudoVSSEG3E32_V_M2
Definition riscv/opcodes.hpp:10037
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E16
@ PseudoVFWNMACC_VV_M4_E16
Definition riscv/opcodes.hpp:3865
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M4
@ PseudoVMADD_VX_M4
Definition riscv/opcodes.hpp:6490
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M2_MASK
@ PseudoVWMULU_VV_M2_MASK
Definition riscv/opcodes.hpp:11566
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF4
@ PseudoVLUXSEG8EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:6398
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M4
@ PseudoVRGATHEREI16_VV_M2_E32_M4
Definition riscv/opcodes.hpp:8318
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF2
@ PseudoVWMULU_VX_MF2
Definition riscv/opcodes.hpp:11581
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M2
@ PseudoVSEXT_VF4_M2
Definition riscv/opcodes.hpp:8763
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_MF2
@ PseudoVAESDF_VV_MF2
Definition riscv/opcodes.hpp:668
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M2_E64
@ PseudoVFSGNJ_VFPR64_M2_E64
Definition riscv/opcodes.hpp:3265
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_MF2
@ PseudoVLOXSEG4EI64_V_M4_MF2
Definition riscv/opcodes.hpp:4656
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M1_E16
@ PseudoVFSGNJX_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3181
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M8_MASK
@ PseudoVOR_VX_M8_MASK
Definition riscv/opcodes.hpp:7661
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M1
@ PseudoVROR_VI_M1
Definition riscv/opcodes.hpp:8534
LIEF::assembly::riscv::OPCODE::CV_SUBRN
@ CV_SUBRN
Definition riscv/opcodes.hpp:12445
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M2
@ PseudoVFWCVT_X_F_V_M2
Definition riscv/opcodes.hpp:3689
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M4_E16
@ PseudoVFSUB_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3395
LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_MF2
@ PseudoVMORN_MM_MF2
Definition riscv/opcodes.hpp:6900
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M8_MASK
@ PseudoVSOXEI32_V_M8_M8_MASK
Definition riscv/opcodes.hpp:9070
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M2
@ PseudoVLOXSEG2EI32_V_M1_M2
Definition riscv/opcodes.hpp:4372
LIEF::assembly::riscv::OPCODE::FSUB_D
@ FSUB_D
Definition riscv/opcodes.hpp:12786
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M8
@ PseudoVOR_VX_M8
Definition riscv/opcodes.hpp:7660
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF8_MASK
@ PseudoVREV8_V_MF8_MASK
Definition riscv/opcodes.hpp:8273
LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_2x8x2_M8
@ PseudoVQMACCUS_2x8x2_M8
Definition riscv/opcodes.hpp:7679
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M1_MASK
@ PseudoVSUXSEG2EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:10754
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E32_MASK
@ PseudoVFMSUB_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:2291
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_M1
@ PseudoVLOXSEG8EI8_V_MF2_M1
Definition riscv/opcodes.hpp:4992
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M2_MASK
@ PseudoVMSLE_VX_M2_MASK
Definition riscv/opcodes.hpp:7152
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M8_E16
@ PseudoVFNMSUB_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2801
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M4
@ PseudoVMAXU_VV_M4
Definition riscv/opcodes.hpp:6518
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4_TIED
@ PseudoVWSUB_WV_M4_TIED
Definition riscv/opcodes.hpp:11814
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF2_MASK
@ PseudoVMSEQ_VV_MF2_MASK
Definition riscv/opcodes.hpp:6975
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF8
@ PseudoVLSEG6E8FF_V_MF8
Definition riscv/opcodes.hpp:5308
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_M1_MASK
@ PseudoVLUXSEG3EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5919
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M2_MASK
@ PseudoVSOXEI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9090
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF4_E16
@ PseudoVFNMACC_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2625
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M4_E32
@ PseudoVFWSUB_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3969
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M4_MASK
@ PseudoVFSLIDE1DOWN_VFPR64_M4_MASK
Definition riscv/opcodes.hpp:3328
LIEF::assembly::riscv::OPCODE::CV_BCLRR
@ CV_BCLRR
Definition riscv/opcodes.hpp:12200
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M4
@ PseudoVMV_V_V_M4
Definition riscv/opcodes.hpp:7399
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E8
@ PseudoVDIV_VV_MF2_E8
Definition riscv/opcodes.hpp:1547
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M1
@ PseudoVSUXSEG2EI16_V_MF2_M1
Definition riscv/opcodes.hpp:10679
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E32_MASK
@ PseudoVFNCVT_F_F_W_M2_E32_MASK
Definition riscv/opcodes.hpp:2442
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M4_MASK
@ PseudoVLE16_V_M4_MASK
Definition riscv/opcodes.hpp:4100
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M1
@ PseudoVMADC_VIM_M1
Definition riscv/opcodes.hpp:6430
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF4
@ PseudoVLUXSEG5EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:6152
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E16
@ PseudoVFCVT_F_XU_V_M2_E16
Definition riscv/opcodes.hpp:1677
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M1
@ PseudoVLOXSEG4EI64_V_M2_M1
Definition riscv/opcodes.hpp:4644
LIEF::assembly::riscv::OPCODE::VLUXSEG4EI64_V
@ VLUXSEG4EI64_V
Definition riscv/opcodes.hpp:13466
LIEF::assembly::riscv::OPCODE::AMOOR_D_RL
@ AMOOR_D_RL
Definition riscv/opcodes.hpp:12074
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF2
@ PseudoVFWCVT_RTZ_XU_F_V_MF2
Definition riscv/opcodes.hpp:3663
LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_2x8x2_M4
@ PseudoVQMACCSU_2x8x2_M4
Definition riscv/opcodes.hpp:7670
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_M1
@ PseudoVC_V_FPR16VW_M1
Definition riscv/opcodes.hpp:1178
LIEF::assembly::riscv::OPCODE::VLUXSEG3EI8_V
@ VLUXSEG3EI8_V
Definition riscv/opcodes.hpp:13463
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF4_MASK
@ PseudoVSOXSEG6EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9636
LIEF::assembly::riscv::OPCODE::AES64ESM
@ AES64ESM
Definition riscv/opcodes.hpp:11943
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M4_MASK
@ PseudoVLOXEI8_V_M4_M4_MASK
Definition riscv/opcodes.hpp:4305
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_M4
@ PseudoVFMV_FPR16_S_M4
Definition riscv/opcodes.hpp:2374
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E32_MASK
@ PseudoVFREDMIN_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:2980
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M2
@ PseudoVWSUB_VV_M2
Definition riscv/opcodes.hpp:11781
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M2_M2
@ PseudoVSUXSEG4EI8_V_M2_M2
Definition riscv/opcodes.hpp:10991
LIEF::assembly::riscv::OPCODE::C_J
@ C_J
Definition riscv/opcodes.hpp:12497
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2_TIED
@ PseudoVWADD_WV_M2_TIED
Definition riscv/opcodes.hpp:11426
LIEF::assembly::riscv::OPCODE::CV_EXTRACTU_H
@ CV_EXTRACTU_H
Definition riscv/opcodes.hpp:12309
LIEF::assembly::riscv::OPCODE::C_LDSP
@ C_LDSP
Definition riscv/opcodes.hpp:12503
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF8
@ PseudoVAADDU_VX_MF8
Definition riscv/opcodes.hpp:547
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E8
@ PseudoVREDSUM_VS_M4_E8
Definition riscv/opcodes.hpp:7986
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M2_MASK
@ PseudoVSOXSEG4EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9468
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M1
@ PseudoVSOXEI64_V_M8_M1
Definition riscv/opcodes.hpp:9103
LIEF::assembly::riscv::OPCODE::AMOOR_B_AQ
@ AMOOR_B_AQ
Definition riscv/opcodes.hpp:12068
LIEF::assembly::riscv::OPCODE::VMSLE_VX
@ VMSLE_VX
Definition riscv/opcodes.hpp:13539
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M2_MASK
@ PseudoVLUXSEG3EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5929
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M4_MASK
@ PseudoVSUXSEG2EI16_V_M1_M4_MASK
Definition riscv/opcodes.hpp:10664
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E16
@ PseudoVFWMSAC_VV_MF2_E16
Definition riscv/opcodes.hpp:3797
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF2_MASK
@ PseudoVNSRA_WI_MF2_MASK
Definition riscv/opcodes.hpp:7561
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M2
@ PseudoVMADC_VV_M2
Definition riscv/opcodes.hpp:6452
LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI1_SCI_B
@ CV_SHUFFLEI1_SCI_B
Definition riscv/opcodes.hpp:12414
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M1_E16
@ PseudoVFNMSUB_VFPR16_M1_E16
Definition riscv/opcodes.hpp:2795
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M4_MASK
@ PseudoVROR_VI_M4_MASK
Definition riscv/opcodes.hpp:8539
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M4_MASK
@ PseudoVSSEG2E32_V_M4_MASK
Definition riscv/opcodes.hpp:10006
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M1_MASK
@ PseudoVSLIDEDOWN_VX_M1_MASK
Definition riscv/opcodes.hpp:8837
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M4
@ PseudoVMSBC_VXM_M4
Definition riscv/opcodes.hpp:6926
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M8_E16
@ PseudoVFADD_VFPR16_M8_E16
Definition riscv/opcodes.hpp:1605
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M4
@ PseudoVLOXEI8_V_M4_M4
Definition riscv/opcodes.hpp:4304
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_SE_M1
@ PseudoVC_V_FPR64V_SE_M1
Definition riscv/opcodes.hpp:1244
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF4_MASK
@ PseudoVSOXSEG2EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9222
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E8_MASK
@ PseudoVREM_VV_MF4_E8_MASK
Definition riscv/opcodes.hpp:8213
LIEF::assembly::riscv::OPCODE::FMV_X_H
@ FMV_X_H
Definition riscv/opcodes.hpp:12733
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M1
@ PseudoVLOXSEG2EI16_V_MF2_M1
Definition riscv/opcodes.hpp:4354
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF4_E16_MASK
@ PseudoVFWMSAC_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3776
LIEF::assembly::riscv::OPCODE::FDIV_H
@ FDIV_H
Definition riscv/opcodes.hpp:12646
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF4_MASK
@ PseudoVLSEG5E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5275
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B32_MASK
@ PseudoVFIRST_M_B32_MASK
Definition riscv/opcodes.hpp:1930
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M4_E64
@ PseudoVFDIV_VFPR64_M4_E64
Definition riscv/opcodes.hpp:1889
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF4
@ PseudoVSOXSEG4EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:9425
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_M1_MASK
@ PseudoVSSSEG6E32_V_M1_MASK
Definition riscv/opcodes.hpp:10366
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M1_MASK
@ PseudoVLOXSEG4EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4675
LIEF::assembly::riscv::OPCODE::LW_AQ
@ LW_AQ
Definition riscv/opcodes.hpp:12854
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M2
@ PseudoVWMACC_VX_M2
Definition riscv/opcodes.hpp:11529
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_M1
@ PseudoVSOXSEG7EI16_V_MF2_M1
Definition riscv/opcodes.hpp:9677
LIEF::assembly::riscv::OPCODE::G_FATAN
@ G_FATAN
Definition riscv/opcodes.hpp:268
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF2_MASK
@ PseudoVSSUBU_VX_MF2_MASK
Definition riscv/opcodes.hpp:10442
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E16_MASK
@ PseudoVFWCVTBF16_F_F_V_M2_E16_MASK
Definition riscv/opcodes.hpp:3546
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_M1_MASK
@ PseudoVSUXSEG6EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11144
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF4_MASK
@ PseudoVNSRL_WV_MF4_MASK
Definition riscv/opcodes.hpp:7611
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF2_MASK
@ PseudoVWMULU_VX_MF2_MASK
Definition riscv/opcodes.hpp:11582
LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_MF2
@ PseudoVSM4K_VI_MF2
Definition riscv/opcodes.hpp:8934
LIEF::assembly::riscv::OPCODE::FADD_D_INX
@ FADD_D_INX
Definition riscv/opcodes.hpp:12560
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF2
@ PseudoVSUXSEG4EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:10921
LIEF::assembly::riscv::OPCODE::CV_AVG_H
@ CV_AVG_H
Definition riscv/opcodes.hpp:12194
LIEF::assembly::riscv::OPCODE::FSGNJ_S_INX
@ FSGNJ_S_INX
Definition riscv/opcodes.hpp:12777
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF8_MASK
@ PseudoVROL_VX_MF8_MASK
Definition riscv/opcodes.hpp:8533
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF2
@ PseudoVADD_VX_MF2
Definition riscv/opcodes.hpp:634
LIEF::assembly::riscv::OPCODE::BLTU
@ BLTU
Definition riscv/opcodes.hpp:12129
LIEF::assembly::riscv::OPCODE::CV_DOTUP_SCI_B
@ CV_DOTUP_SCI_B
Definition riscv/opcodes.hpp:12289
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M4
@ PseudoTHVdotVMAQASU_VX_M4
Definition riscv/opcodes.hpp:464
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF4
@ PseudoVSOXSEG8EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:9821
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E16
@ PseudoVFSGNJ_VV_M1_E16
Definition riscv/opcodes.hpp:3271
LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_M8
@ PseudoVC_XVV_SE_M8
Definition riscv/opcodes.hpp:1399
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M2_MASK
@ PseudoVLOXSEG3EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4515
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M4_MASK
@ PseudoVSUXSEG2EI64_V_M8_M4_MASK
Definition riscv/opcodes.hpp:10758
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M8_M1
@ PseudoVLUXSEG8EI64_V_M8_M1
Definition riscv/opcodes.hpp:6380
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M1
@ PseudoVFCVT_RM_X_F_V_M1
Definition riscv/opcodes.hpp:1803
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_MF2_MASK
@ PseudoVLSEG5E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5257
LIEF::assembly::riscv::OPCODE::BGEU
@ BGEU
Definition riscv/opcodes.hpp:12125
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M1_E16
@ PseudoVFWADD_WFPR16_M1_E16
Definition riscv/opcodes.hpp:3487
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16
@ PseudoVFWADD_WV_M4_E16
Definition riscv/opcodes.hpp:3521
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B16_MASK
@ PseudoVMSBF_M_B16_MASK
Definition riscv/opcodes.hpp:6940
LIEF::assembly::riscv::OPCODE::CV_INSERT_H
@ CV_INSERT_H
Definition riscv/opcodes.hpp:12317
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M4_MASK
@ PseudoVFWCVT_RTZ_XU_F_V_M4_MASK
Definition riscv/opcodes.hpp:3662
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_M2
@ PseudoVC_FPR16V_SE_M2
Definition riscv/opcodes.hpp:1091
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2_MASK_TIED
@ PseudoVWADD_WV_MF2_MASK_TIED
Definition riscv/opcodes.hpp:11433
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF2
@ PseudoVLUXSEG7EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:6256
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M8_MASK
@ PseudoVCPOP_V_M8_MASK
Definition riscv/opcodes.hpp:1057
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_M1_MASK
@ PseudoVLUXSEG7EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:6309
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF4
@ PseudoVSUXSEG5EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:11031
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M4_MASK
@ PseudoVMFEQ_VV_M4_MASK
Definition riscv/opcodes.hpp:6633
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF4
@ PseudoVLOXSEG3EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:4570
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8_MASK_TIED
@ PseudoVWSUB_WV_MF8_MASK_TIED
Definition riscv/opcodes.hpp:11825
LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B1
@ PseudoVMSET_M_B1
Definition riscv/opcodes.hpp:6994
LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M2_MASK
@ PseudoVLE64FF_V_M2_MASK
Definition riscv/opcodes.hpp:4130
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M4
@ PseudoVRGATHEREI16_VV_M4_E32_M4
Definition riscv/opcodes.hpp:8350
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_MF8
@ PseudoVMSBC_VX_MF8
Definition riscv/opcodes.hpp:6937
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF2
@ PseudoVNMSUB_VX_MF2
Definition riscv/opcodes.hpp:7548
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF2_MASK
@ PseudoVLSEG8E8FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5385
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_MF2_MASK
@ PseudoTHVdotVMAQAUS_VX_MF2_MASK
Definition riscv/opcodes.hpp:479
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF2_MASK
@ PseudoVSLL_VV_MF2_MASK
Definition riscv/opcodes.hpp:8901
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2_MASK
@ PseudoVWADDU_WV_M2_MASK
Definition riscv/opcodes.hpp:11364
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_M2_MASK
@ PseudoVFNRCLIP_X_F_QF_M2_MASK
Definition riscv/opcodes.hpp:2868
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M8_M2_MASK
@ PseudoVLUXSEG4EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:6019
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_MF4
@ PseudoVC_V_FPR16V_SE_MF4
Definition riscv/opcodes.hpp:1201
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF2
@ PseudoVNCLIP_WV_MF2
Definition riscv/opcodes.hpp:7480
LIEF::assembly::riscv::OPCODE::VLOXSEG3EI8_V
@ VLOXSEG3EI8_V
Definition riscv/opcodes.hpp:13343
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF8
@ PseudoVWMULU_VX_MF8
Definition riscv/opcodes.hpp:11585
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M4_MASK
@ PseudoVMAXU_VV_M4_MASK
Definition riscv/opcodes.hpp:6519
LIEF::assembly::riscv::OPCODE::G_FENCE
@ G_FENCE
Definition riscv/opcodes.hpp:140
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M2_E64_MASK
@ PseudoVFMIN_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2157
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E64
@ PseudoVFRSQRT7_V_M8_E64
Definition riscv/opcodes.hpp:3083
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E32_MASK
@ PseudoVFWMSAC_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3792
LIEF::assembly::riscv::OPCODE::TH_ICACHE_IPA
@ TH_ICACHE_IPA
Definition riscv/opcodes.hpp:13056
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_MF2
@ PseudoVC_V_I_SE_MF2
Definition riscv/opcodes.hpp:1299
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E64
@ PseudoVDIV_VX_M4_E64
Definition riscv/opcodes.hpp:1575
LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M1_MASK
@ PseudoVLSE64_V_M1_MASK
Definition riscv/opcodes.hpp:5033
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_MF2_MASK
@ PseudoVLOXSEG7EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4915
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M1_MASK
@ PseudoVLSEG2E8FF_V_M1_MASK
Definition riscv/opcodes.hpp:5103
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M2_E64
@ PseudoVFMACC_VFPR64_M2_E64
Definition riscv/opcodes.hpp:1961
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E16_MASK
@ PseudoVREDAND_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:7739
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M1
@ PseudoVFMERGE_VFPR64M_M1
Definition riscv/opcodes.hpp:2128
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF2
@ PseudoVLE16_V_MF2
Definition riscv/opcodes.hpp:4103
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M4_M1
@ PseudoVLUXSEG7EI32_V_M4_M1
Definition riscv/opcodes.hpp:6272
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M1_MASK
@ PseudoVLOXSEG2EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4413
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF4
@ PseudoVFNCVT_RTZ_X_F_W_MF4
Definition riscv/opcodes.hpp:2587
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M4_E16_MASK
@ PseudoVFSUB_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3396
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M2
@ PseudoVSBC_VVM_M2
Definition riscv/opcodes.hpp:8689
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_MF2_MASK
@ PseudoVLSEG4E32FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5203
LIEF::assembly::riscv::OPCODE::CV_SDOTSP_H
@ CV_SDOTSP_H
Definition riscv/opcodes.hpp:12394
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M2_MASK
@ PseudoVWSLL_VV_M2_MASK
Definition riscv/opcodes.hpp:11698
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M4_M1_MASK
@ PseudoVLOXSEG7EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4881
LIEF::assembly::riscv::OPCODE::VLOXSEG2EI8_V
@ VLOXSEG2EI8_V
Definition riscv/opcodes.hpp:13339
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF8
@ PseudoVSOXSEG5EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:9549
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF4_MASK
@ PseudoVAADDU_VV_MF4_MASK
Definition riscv/opcodes.hpp:532
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF8
@ PseudoVSSEG7E8_V_MF8
Definition riscv/opcodes.hpp:10141
LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D_RL
@ SSAMOSWAP_D_RL
Definition riscv/opcodes.hpp:13007
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M4_MASK
@ PseudoVRGATHEREI16_VV_M2_E32_M4_MASK
Definition riscv/opcodes.hpp:8319
LIEF::assembly::riscv::OPCODE::PseudoBRINDNonX7
@ PseudoBRINDNonX7
Definition riscv/opcodes.hpp:334
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B4_MASK
@ PseudoVFIRST_M_B4_MASK
Definition riscv/opcodes.hpp:1932
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF2
@ PseudoVLUXSEG7EI64_V_M1_MF2
Definition riscv/opcodes.hpp:6284
LIEF::assembly::riscv::OPCODE::G_STACKRESTORE
@ G_STACKRESTORE
Definition riscv/opcodes.hpp:281
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M4
@ PseudoVFWCVT_RTZ_XU_F_V_M4
Definition riscv/opcodes.hpp:3661
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E32_MASK
@ PseudoVFREDMAX_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:2962
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF8
@ PseudoVSUXSEG2EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:10693
LIEF::assembly::riscv::OPCODE::VLSEG2E64FF_V
@ VLSEG2E64FF_V
Definition riscv/opcodes.hpp:13372
LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B2
@ PseudoVMSET_M_B2
Definition riscv/opcodes.hpp:6996
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_MF4
@ PseudoVFWCVT_RM_X_F_V_MF4
Definition riscv/opcodes.hpp:3655
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M2_MASK
@ PseudoVNMSAC_VX_M2_MASK
Definition riscv/opcodes.hpp:7515
LIEF::assembly::riscv::OPCODE::FMV_W_X
@ FMV_W_X
Definition riscv/opcodes.hpp:12731
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16_TIED
@ PseudoVFWSUB_WV_M4_E16_TIED
Definition riscv/opcodes.hpp:4028
LIEF::assembly::riscv::OPCODE::VFWCVTBF16_F_F_V
@ VFWCVTBF16_F_F_V
Definition riscv/opcodes.hpp:13276
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M8_E32
@ PseudoVFSGNJX_VFPR32_M8_E32
Definition riscv/opcodes.hpp:3199
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M8_E16
@ PseudoVFMACC_VFPR16_M8_E16
Definition riscv/opcodes.hpp:1943
LIEF::assembly::riscv::OPCODE::VNCLIP_WX
@ VNCLIP_WX
Definition riscv/opcodes.hpp:13572
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M2
@ PseudoVSLL_VV_M2
Definition riscv/opcodes.hpp:8894
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M4
@ PseudoVSSRA_VX_M4
Definition riscv/opcodes.hpp:10195
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M4_MASK
@ PseudoVWADDU_VX_M4_MASK
Definition riscv/opcodes.hpp:11352
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E16_MASK
@ PseudoVFSUB_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:3440
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_M1
@ PseudoVC_V_XV_M1
Definition riscv/opcodes.hpp:1368
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF8_MASK
@ PseudoVLOXSEG3EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:4525
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M8
@ PseudoVNMSUB_VV_M8
Definition riscv/opcodes.hpp:7532
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M2_E32_MASK
@ PseudoVFWNMSAC_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3888
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M2_MASK
@ PseudoVSUXSEG2EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10698
LIEF::assembly::riscv::OPCODE::G_READSTEADYCOUNTER
@ G_READSTEADYCOUNTER
Definition riscv/opcodes.hpp:112
LIEF::assembly::riscv::OPCODE::G_FFLOOR
@ G_FFLOOR
Definition riscv/opcodes.hpp:273
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M2_MASK
@ PseudoTHVdotVMAQAUS_VX_M2_MASK
Definition riscv/opcodes.hpp:473
LIEF::assembly::riscv::OPCODE::VMAX_VV
@ VMAX_VV
Definition riscv/opcodes.hpp:13498
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M4
@ PseudoVLUXEI16_V_M4_M4
Definition riscv/opcodes.hpp:5588
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E16_MASK
@ PseudoVFWREDOSUM_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:3916
LIEF::assembly::riscv::OPCODE::MULH
@ MULH
Definition riscv/opcodes.hpp:12902
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_M1_MASK
@ PseudoVSOXSEG5EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9524
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M1
@ PseudoVSUXSEG4EI32_V_M1_M1
Definition riscv/opcodes.hpp:10933
LIEF::assembly::riscv::OPCODE::PseudoFLD
@ PseudoFLD
Definition riscv/opcodes.hpp:371
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_M1_MASK
@ PseudoVLSEG5E16_V_M1_MASK
Definition riscv/opcodes.hpp:5245
LIEF::assembly::riscv::OPCODE::FSH
@ FSH
Definition riscv/opcodes.hpp:12778
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E32
@ PseudoVFNMACC_VV_M2_E32
Definition riscv/opcodes.hpp:2653
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF4_MASK
@ PseudoVLOXSEG5EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4701
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_M1_MASK
@ PseudoVSSSEG8E32_V_M1_MASK
Definition riscv/opcodes.hpp:10406
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF4_MASK
@ PseudoVSADD_VI_MF4_MASK
Definition riscv/opcodes.hpp:8657
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_M1_MASK
@ PseudoVLUXSEG8EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:6389
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_M1
@ PseudoVLOXSEG5EI16_V_MF2_M1
Definition riscv/opcodes.hpp:4696
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E64
@ PseudoVCOMPRESS_VM_M1_E64
Definition riscv/opcodes.hpp:1016
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E64
@ PseudoVREM_VV_M2_E64
Definition riscv/opcodes.hpp:8184
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M1_E64
@ PseudoVFNMADD_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2697
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF4
@ PseudoVWMULU_VX_MF4
Definition riscv/opcodes.hpp:11583
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M1_E16
@ PseudoVFWNMSAC_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3875
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF8_MASK
@ PseudoVWSUB_WX_MF8_MASK
Definition riscv/opcodes.hpp:11838
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF8_MASK
@ PseudoVSUXSEG7EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:11254
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M1
@ PseudoVADD_VV_M1
Definition riscv/opcodes.hpp:612
LIEF::assembly::riscv::OPCODE::FSQRT_D
@ FSQRT_D
Definition riscv/opcodes.hpp:12779
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF8
@ PseudoVSOXEI64_V_M1_MF8
Definition riscv/opcodes.hpp:9085
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M2_M1_MASK
@ PseudoVLOXSEG6EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4775
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_M1
@ PseudoVRELOAD6_M1
Definition riscv/opcodes.hpp:8072
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF4_MASK
@ PseudoVRGATHER_VI_MF4_MASK
Definition riscv/opcodes.hpp:8445
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E32
@ PseudoVFSQRT_V_MF2_E32
Definition riscv/opcodes.hpp:3387
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E32_MASK
@ PseudoVFMIN_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:2165
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF4_MASK
@ PseudoVLOXSEG5EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4715
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_M1
@ PseudoVLOXEI16_V_MF4_M1
Definition riscv/opcodes.hpp:4212
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E64
@ PseudoVFSGNJ_VV_M4_E64
Definition riscv/opcodes.hpp:3287
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF2
@ PseudoVLUXSEG4EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:6022
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M2_MASK
@ PseudoVCLMUL_VV_M2_MASK
Definition riscv/opcodes.hpp:975
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E8_MASK
@ PseudoVREDAND_VS_M8_E8_MASK
Definition riscv/opcodes.hpp:7731
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_MF2
@ PseudoVSOXSEG6EI32_V_M2_MF2
Definition riscv/opcodes.hpp:9619
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M2_MASK
@ PseudoVSUXEI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10564
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M4_E16_MASK
@ PseudoVFRDIV_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2880
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_ADD
@ G_ATOMICRMW_ADD
Definition riscv/opcodes.hpp:124
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF2_MASK
@ PseudoVLSEG4E8FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5223
LIEF::assembly::riscv::OPCODE::AMOXOR_D_AQ_RL
@ AMOXOR_D_AQ_RL
Definition riscv/opcodes.hpp:12105
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M2_MASK
@ PseudoVFSLIDE1UP_VFPR16_M2_MASK
Definition riscv/opcodes.hpp:3334
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M1_MASK
@ PseudoVRGATHER_VI_M1_MASK
Definition riscv/opcodes.hpp:8435
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M4_MASK
@ PseudoVSOXSEG2EI8_V_M2_M4_MASK
Definition riscv/opcodes.hpp:9264
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M8
@ PseudoVMAXU_VX_M8
Definition riscv/opcodes.hpp:6534
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_MF2_MASK
@ PseudoVLUXSEG6EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6165
LIEF::assembly::riscv::OPCODE::PseudoCALLIndirect
@ PseudoCALLIndirect
Definition riscv/opcodes.hpp:337
LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadNand32
@ PseudoMaskedAtomicLoadNand32
Definition riscv/opcodes.hpp:410
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_MF2_MASK
@ PseudoVLUXSEG7EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:6299
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_M1
@ PseudoVC_V_VV_M1
Definition riscv/opcodes.hpp:1328
LIEF::assembly::riscv::OPCODE::SHA256SUM1
@ SHA256SUM1
Definition riscv/opcodes.hpp:12968
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF4_MASK
@ PseudoVLUXSEG4EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:6033
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M1_MASK
@ PseudoVBREV8_V_M1_MASK
Definition riscv/opcodes.hpp:917
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF2_MASK
@ PseudoVREV8_V_MF2_MASK
Definition riscv/opcodes.hpp:8269
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF4_MASK
@ PseudoVMSLT_VX_MF4_MASK
Definition riscv/opcodes.hpp:7218
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_MF2
@ PseudoVSEXT_VF4_MF2
Definition riscv/opcodes.hpp:8769
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF4_MASK
@ PseudoVLOXSEG7EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:4927
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B64
@ PseudoVCPOP_M_B64
Definition riscv/opcodes.hpp:1046
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M1_E16
@ PseudoVFDIV_VFPR16_M1_E16
Definition riscv/opcodes.hpp:1863
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF8
@ PseudoVLOXSEG3EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:4496
LIEF::assembly::riscv::OPCODE::VSUXSEG8EI32_V
@ VSUXSEG8EI32_V
Definition riscv/opcodes.hpp:13799
LIEF::assembly::riscv::OPCODE::G_CONSTANT_POOL
@ G_CONSTANT_POOL
Definition riscv/opcodes.hpp:92
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M2_MASK
@ PseudoVSSSEG3E16_V_M2_MASK
Definition riscv/opcodes.hpp:10286
LIEF::assembly::riscv::OPCODE::G_STRICT_FMUL
@ G_STRICT_FMUL
Definition riscv/opcodes.hpp:284
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E8
@ PseudoVFWCVT_F_XU_V_M4_E8
Definition riscv/opcodes.hpp:3593
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_M1
@ PseudoVLUXSEG8EI16_V_M1_M1
Definition riscv/opcodes.hpp:6322
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M8_M8
@ PseudoVLOXEI8_V_M8_M8
Definition riscv/opcodes.hpp:4308
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M2
@ PseudoVWMULU_VV_M2
Definition riscv/opcodes.hpp:11565
LIEF::assembly::riscv::OPCODE::VWADD_WV
@ VWADD_WV
Definition riscv/opcodes.hpp:13810
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M2_MASK
@ PseudoVNCLIP_WV_M2_MASK
Definition riscv/opcodes.hpp:7477
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF4_MASK
@ PseudoVSOXSEG7EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:9748
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M1
@ PseudoVLUXEI32_V_M4_M1
Definition riscv/opcodes.hpp:5628
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M2
@ PseudoVSRL_VI_M2
Definition riscv/opcodes.hpp:9907
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M1_MASK
@ PseudoVSUXSEG2EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10696
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M8
@ PseudoVRGATHEREI16_VV_M8_E16_M8
Definition riscv/opcodes.hpp:8374
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M8
@ PseudoVCLMUL_VV_M8
Definition riscv/opcodes.hpp:978
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UMAX
@ G_ATOMICRMW_UMAX
Definition riscv/opcodes.hpp:132
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_M1
@ PseudoVSSSEG6E32_V_M1
Definition riscv/opcodes.hpp:10365
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M8_MASK
@ PseudoVFCVT_XU_F_V_M8_MASK
Definition riscv/opcodes.hpp:1846
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF8
@ PseudoVSUXSEG2EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:10793
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M1
@ PseudoVLE8FF_V_M1
Definition riscv/opcodes.hpp:4143
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF8
@ PseudoVLOXEI32_V_MF2_MF8
Definition riscv/opcodes.hpp:4256
LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M2_MASK
@ PseudoVLSE64_V_M2_MASK
Definition riscv/opcodes.hpp:5035
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M2_MASK
@ PseudoVNMSUB_VX_M2_MASK
Definition riscv/opcodes.hpp:7543
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF2_MASK
@ PseudoVSMUL_VV_MF2_MASK
Definition riscv/opcodes.hpp:8973
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M8_M4_MASK
@ PseudoVLUXSEG2EI16_V_M8_M4_MASK
Definition riscv/opcodes.hpp:5745
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF2
@ PseudoVLOXEI16_V_MF2_MF2
Definition riscv/opcodes.hpp:4208
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M1_MASK
@ PseudoVWMULU_VX_M1_MASK
Definition riscv/opcodes.hpp:11576
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF2
@ PseudoVMSLE_VV_MF2
Definition riscv/opcodes.hpp:7143
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_M1
@ PseudoVLOXSEG5EI8_V_MF8_M1
Definition riscv/opcodes.hpp:4762
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4
@ PseudoVWSUBU_WV_MF4
Definition riscv/opcodes.hpp:11759
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M8
@ PseudoVMSLT_VV_M8
Definition riscv/opcodes.hpp:7199
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF4
@ PseudoVMSEQ_VI_MF4
Definition riscv/opcodes.hpp:6962
LIEF::assembly::riscv::OPCODE::TH_FSRW
@ TH_FSRW
Definition riscv/opcodes.hpp:13051
LIEF::assembly::riscv::OPCODE::G_FEXP2
@ G_FEXP2
Definition riscv/opcodes.hpp:206
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_M1
@ PseudoVSOXSEG8EI8_V_MF4_M1
Definition riscv/opcodes.hpp:9817
LIEF::assembly::riscv::OPCODE::BINV
@ BINV
Definition riscv/opcodes.hpp:12126
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF4_MASK
@ PseudoVCLMUL_VX_MF4_MASK
Definition riscv/opcodes.hpp:997
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E16
@ PseudoVDIV_VX_M8_E16
Definition riscv/opcodes.hpp:1579
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_MF4
@ PseudoVFCVT_RM_XU_F_V_MF4
Definition riscv/opcodes.hpp:1801
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E8_MASK
@ PseudoVREDMAX_VS_MF4_E8_MASK
Definition riscv/opcodes.hpp:7829
LIEF::assembly::riscv::OPCODE::AMOMAX_D_RL
@ AMOMAX_D_RL
Definition riscv/opcodes.hpp:12026
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M2
@ PseudoVSOXSEG2EI16_V_M4_M2
Definition riscv/opcodes.hpp:9169
LIEF::assembly::riscv::OPCODE::G_SMULO
@ G_SMULO
Definition riscv/opcodes.hpp:179
LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_MF2
@ PseudoVSPILL7_MF2
Definition riscv/opcodes.hpp:9856
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E16_MASK
@ PseudoVREDMIN_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:7915
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF4_MASK
@ PseudoVFWCVT_RTZ_X_F_V_MF4_MASK
Definition riscv/opcodes.hpp:3676
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M1
@ PseudoVLOXEI8_V_M1_M1
Definition riscv/opcodes.hpp:4290
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M4
@ PseudoVMULHSU_VX_M4
Definition riscv/opcodes.hpp:7295
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E32
@ PseudoVREMU_VV_M8_E32
Definition riscv/opcodes.hpp:8110
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M4_MASK
@ PseudoVCTZ_V_M4_MASK
Definition riscv/opcodes.hpp:1069
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M2
@ PseudoVSSSEG4E8_V_M2
Definition riscv/opcodes.hpp:10331
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E8_MASK
@ PseudoVREMU_VV_MF4_E8_MASK
Definition riscv/opcodes.hpp:8125
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M8
@ PseudoVMFNE_VFPR64_M8
Definition riscv/opcodes.hpp:6812
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M1_MASK
@ PseudoVSSEG4E64_V_M1_MASK
Definition riscv/opcodes.hpp:10070
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF8
@ PseudoVLOXSEG8EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:5008
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF4
@ PseudoVSUXSEG8EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:11265
LIEF::assembly::riscv::OPCODE::G_CTTZ
@ G_CTTZ
Definition riscv/opcodes.hpp:255
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF2_MASK
@ PseudoVSRL_VI_MF2_MASK
Definition riscv/opcodes.hpp:9914
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M8_E64_MASK
@ PseudoVFMADD_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2026
LIEF::assembly::riscv::OPCODE::VWSUBU_WX
@ VWSUBU_WX
Definition riscv/opcodes.hpp:13833
LIEF::assembly::riscv::OPCODE::G_FCOSH
@ G_FCOSH
Definition riscv/opcodes.hpp:269
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M2_MASK
@ PseudoVSOXSEG4EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:9482
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E32_MASK
@ PseudoVFNMSUB_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:2834
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF4_MASK
@ PseudoVWADDU_VV_MF4_MASK
Definition riscv/opcodes.hpp:11344
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_MF2_MASK
@ PseudoVSSEG5E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10092
LIEF::assembly::riscv::OPCODE::CSRRW
@ CSRRW
Definition riscv/opcodes.hpp:12157
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF2_MASK
@ PseudoVLSSEG5E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5505
LIEF::assembly::riscv::OPCODE::AMOAND_W
@ AMOAND_W
Definition riscv/opcodes.hpp:11975
LIEF::assembly::riscv::OPCODE::FMV_D_X
@ FMV_D_X
Definition riscv/opcodes.hpp:12729
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF4_MASK
@ PseudoVLUXSEG5EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:6135
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M4_MASK
@ PseudoVLUXEI64_V_M8_M4_MASK
Definition riscv/opcodes.hpp:5679
LIEF::assembly::riscv::OPCODE::CV_SHUFFLE_B
@ CV_SHUFFLE_B
Definition riscv/opcodes.hpp:12417
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF4
@ PseudoVLSSEG3E8_V_MF4
Definition riscv/opcodes.hpp:5458
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M4
@ PseudoVFCVT_RM_X_F_V_M4
Definition riscv/opcodes.hpp:1807
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF8_MASK
@ PseudoVSUXSEG7EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:11222
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF8_MASK
@ PseudoVLSEG4E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5237
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF4
@ PseudoVSSEG7E16_V_MF4
Definition riscv/opcodes.hpp:10127
LIEF::assembly::riscv::OPCODE::JALR
@ JALR
Definition riscv/opcodes.hpp:12831
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF4_MASK
@ PseudoVSOXSEG8EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9776
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_MF2_MASK
@ PseudoVSSEG3E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10040
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M2
@ PseudoVMFGE_VFPR64_M2
Definition riscv/opcodes.hpp:6664
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M1
@ PseudoVLSEG4E32FF_V_M1
Definition riscv/opcodes.hpp:5198
LIEF::assembly::riscv::OPCODE::CV_INSERTR
@ CV_INSERTR
Definition riscv/opcodes.hpp:12315
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_M1_MASK
@ PseudoVLSSEG6E8_V_M1_MASK
Definition riscv/opcodes.hpp:5523
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M4_E16_MASK
@ PseudoVFNMACC_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2620
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M2
@ PseudoVSOXEI64_V_M8_M2
Definition riscv/opcodes.hpp:9105
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF4
@ PseudoVNCLIPU_WV_MF4
Definition riscv/opcodes.hpp:7446
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF4
@ PseudoVSUXEI8_V_MF4_MF4
Definition riscv/opcodes.hpp:10649
LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SCI_H
@ CV_CMPEQ_SCI_H
Definition riscv/opcodes.hpp:12214
LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VI
@ PseudoVMSGE_VI
Definition riscv/opcodes.hpp:7005
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M1
@ PseudoVLOXSEG2EI8_V_MF2_M1
Definition riscv/opcodes.hpp:4446
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M8_E32_MASK
@ PseudoVFMADD_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2016
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF8_MASK
@ PseudoVSLL_VX_MF8_MASK
Definition riscv/opcodes.hpp:8919
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M1_E32_MASK
@ PseudoVFSGNJX_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3194
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E64_MASK
@ PseudoVFRSQRT7_V_M4_E64_MASK
Definition riscv/opcodes.hpp:3078
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E8
@ PseudoVREM_VX_M1_E8
Definition riscv/opcodes.hpp:8222
LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_MF8
@ PseudoVSPILL8_MF8
Definition riscv/opcodes.hpp:9862
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF2
@ PseudoVLOXSEG2EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:4464
LIEF::assembly::riscv::OPCODE::VSADD_VV
@ VSADD_VV
Definition riscv/opcodes.hpp:13626
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E16_MASK
@ PseudoVREDXOR_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:8047
LIEF::assembly::riscv::OPCODE::CV_MAX_H
@ CV_MAX_H
Definition riscv/opcodes.hpp:12351
LIEF::assembly::riscv::OPCODE::CV_CMPGT_SCI_H
@ CV_CMPGT_SCI_H
Definition riscv/opcodes.hpp:12238
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF2
@ PseudoVMAXU_VV_MF2
Definition riscv/opcodes.hpp:6522
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF2_MASK
@ PseudoVLSSEG3E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5457
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E16_MASK
@ PseudoVFNMACC_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:2658
LIEF::assembly::riscv::OPCODE::G_ASSERT_ALIGN
@ G_ASSERT_ALIGN
Definition riscv/opcodes.hpp:74
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M2
@ PseudoVSUXSEG2EI16_V_M1_M2
Definition riscv/opcodes.hpp:10661
LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_M1
@ PseudoVC_XVV_SE_M1
Definition riscv/opcodes.hpp:1396
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF2_MASK
@ PseudoVLUXSEG3EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:5895
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF8_MASK
@ PseudoVWMULU_VX_MF8_MASK
Definition riscv/opcodes.hpp:11586
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M4
@ PseudoVLSEG2E16FF_V_M4
Definition riscv/opcodes.hpp:5058
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M2_MASK
@ PseudoVLOXSEG4EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4625
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_MF2_MASK
@ PseudoVLUXSEG6EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:6191
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_M1_MASK
@ PseudoVLUXSEG8EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6329
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF4_MASK
@ PseudoVLUXSEG7EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:6295
LIEF::assembly::riscv::OPCODE::C_MOP9
@ C_MOP9
Definition riscv/opcodes.hpp:12519
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M2_MASK
@ PseudoVSOXEI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:9028
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF2
@ PseudoVREV8_V_MF2
Definition riscv/opcodes.hpp:8268
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E32
@ PseudoVREDMIN_VS_MF2_E32
Definition riscv/opcodes.hpp:7910
LIEF::assembly::riscv::OPCODE::InsnCJ
@ InsnCJ
Definition riscv/opcodes.hpp:12818
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF8_MASK
@ PseudoVSOXSEG3EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:9318
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M1_E16
@ PseudoVFMADD_VFPR16_M1_E16
Definition riscv/opcodes.hpp:1997
LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_MF4
@ PseudoVC_XV_SE_MF4
Definition riscv/opcodes.hpp:1414
LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M1
@ PseudoVSSE64_V_M1
Definition riscv/opcodes.hpp:9969
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_M1
@ PseudoVSOXSEG7EI8_V_MF2_M1
Definition riscv/opcodes.hpp:9733
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E64_MASK
@ PseudoVFMSAC_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:2233
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF4_MASK
@ PseudoVLUXSEG8EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:6393
LIEF::assembly::riscv::OPCODE::CV_MAX_SC_B
@ CV_MAX_SC_B
Definition riscv/opcodes.hpp:12354
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E8_MASK
@ PseudoVREDMINU_VS_MF4_E8_MASK
Definition riscv/opcodes.hpp:7873
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64_V_M1
@ PseudoVLSEG5E64_V_M1
Definition riscv/opcodes.hpp:5260
LIEF::assembly::riscv::OPCODE::TH_LWUIB
@ TH_LWUIB
Definition riscv/opcodes.hpp:13091
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF4
@ PseudoVLUXSEG8EI64_V_M2_MF4
Definition riscv/opcodes.hpp:6374
LIEF::assembly::riscv::OPCODE::C_SH
@ C_SH
Definition riscv/opcodes.hpp:12532
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M2_M2
@ PseudoVLUXSEG3EI8_V_M2_M2
Definition riscv/opcodes.hpp:5948
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF2_MASK
@ PseudoVMSLTU_VX_MF2_MASK
Definition riscv/opcodes.hpp:7187
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E16
@ PseudoVFNCVT_ROD_F_F_W_MF2_E16
Definition riscv/opcodes.hpp:2561
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF8_E8_MASK
@ PseudoVDIVU_VV_MF8_E8_MASK
Definition riscv/opcodes.hpp:1466
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M4
@ PseudoVMSLEU_VV_M4
Definition riscv/opcodes.hpp:7097
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_M1_MASK
@ PseudoVLOXSEG8EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:5003
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_MF2_MASK
@ PseudoVMFLE_VFPR32_MF2_MASK
Definition riscv/opcodes.hpp:6721
LIEF::assembly::riscv::OPCODE::G_ABS
@ G_ABS
Definition riscv/opcodes.hpp:242
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M1_MASK
@ PseudoVWSLL_VX_M1_MASK
Definition riscv/opcodes.hpp:11708
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF8
@ PseudoVLSSEG7E8_V_MF8
Definition riscv/opcodes.hpp:5548
LIEF::assembly::riscv::OPCODE::VSSSEG8E64_V
@ VSSSEG8E64_V
Definition riscv/opcodes.hpp:13762
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M4_E32
@ PseudoVFWADD_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3465
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M2
@ PseudoVSUXSEG2EI32_V_M2_M2
Definition riscv/opcodes.hpp:10705
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_M1
@ PseudoVSOXSEG3EI16_V_MF4_M1
Definition riscv/opcodes.hpp:9311
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M1
@ PseudoVSRL_VV_M1
Definition riscv/opcodes.hpp:9919
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF2_MASK
@ PseudoVLUXEI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:5617
LIEF::assembly::riscv::OPCODE::FSGNJ_D
@ FSGNJ_D
Definition riscv/opcodes.hpp:12771
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M2_MASK
@ PseudoVLUXEI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5661
LIEF::assembly::riscv::OPCODE::VLSSEG4E64_V
@ VLSSEG4E64_V
Definition riscv/opcodes.hpp:13434
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M2
@ PseudoVLOXSEG2EI16_V_M1_M2
Definition riscv/opcodes.hpp:4336
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M2_MASK
@ PseudoVWMACCSU_VX_M2_MASK
Definition riscv/opcodes.hpp:11470
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M2_MASK
@ PseudoVXOR_VX_M2_MASK
Definition riscv/opcodes.hpp:11870
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_M1_MASK
@ PseudoVLSEG6E32_V_M1_MASK
Definition riscv/opcodes.hpp:5295
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF4
@ PseudoVSOXSEG2EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:9287
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_MF2_MASK
@ PseudoVSUXSEG6EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11098
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_MF4
@ PseudoVAESDM_VS_M4_MF4
Definition riscv/opcodes.hpp:682
LIEF::assembly::riscv::OPCODE::AMOMINU_B_AQ_RL
@ AMOMINU_B_AQ_RL
Definition riscv/opcodes.hpp:12037
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF2
@ PseudoVLOXSEG5EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:4704
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF8
@ PseudoVLSSEG8E8_V_MF8
Definition riscv/opcodes.hpp:5568
LIEF::assembly::riscv::OPCODE::FMADD_H
@ FMADD_H
Definition riscv/opcodes.hpp:12689
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M4_MASK
@ PseudoVASUBU_VX_M4_MASK
Definition riscv/opcodes.hpp:879
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E64_MASK
@ PseudoVFMACC_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:1972
LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M1
@ PseudoVSE32_V_M1
Definition riscv/opcodes.hpp:8714
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF4_MASK
@ PseudoVCLMULH_VV_MF4_MASK
Definition riscv/opcodes.hpp:955
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E16_MASK
@ PseudoVFNMSUB_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:2844
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_MF2_MASK
@ PseudoVSUXSEG7EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:11204
LIEF::assembly::riscv::OPCODE::CV_MAX_B
@ CV_MAX_B
Definition riscv/opcodes.hpp:12350
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF2_E16
@ PseudoVFDIV_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:1871
LIEF::assembly::riscv::OPCODE::CV_ADDRNR
@ CV_ADDRNR
Definition riscv/opcodes.hpp:12167
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M2
@ PseudoVNSRA_WX_M2
Definition riscv/opcodes.hpp:7580
LIEF::assembly::riscv::OPCODE::CV_CMPGTU_B
@ CV_CMPGTU_B
Definition riscv/opcodes.hpp:12229
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_MF2
@ PseudoVC_V_FPR16VW_MF2
Definition riscv/opcodes.hpp:1182
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_M1
@ PseudoVSUXSEG4EI64_V_M1_M1
Definition riscv/opcodes.hpp:10961
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF2_MASK
@ PseudoVLUXSEG8EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6365
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M2
@ PseudoVLUXEI8_V_M2_M2
Definition riscv/opcodes.hpp:5690
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF8
@ PseudoVSOXSEG4EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:9427
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M2
@ PseudoVRGATHEREI16_VV_M8_E8_M2
Definition riscv/opcodes.hpp:8388
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF8
@ PseudoVLSEG7E8_V_MF8
Definition riscv/opcodes.hpp:5356
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK
@ PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK
Definition riscv/opcodes.hpp:3666
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF4_MASK
@ PseudoVSADDU_VV_MF4_MASK
Definition riscv/opcodes.hpp:8629
LIEF::assembly::riscv::OPCODE::VMERGE_VVM
@ VMERGE_VVM
Definition riscv/opcodes.hpp:13501
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF8_MASK
@ PseudoVAADDU_VV_MF8_MASK
Definition riscv/opcodes.hpp:534
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_M1_MASK
@ PseudoVLOXSEG6EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4783
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M1
@ PseudoVLE8_V_M1
Definition riscv/opcodes.hpp:4157
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M1
@ PseudoVFWCVT_XU_F_V_M1
Definition riscv/opcodes.hpp:3677
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M1_E32
@ PseudoVFADD_VFPR32_M1_E32
Definition riscv/opcodes.hpp:1611
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR64_S_M4
@ PseudoVFMV_FPR64_S_M4
Definition riscv/opcodes.hpp:2385
LIEF::assembly::riscv::OPCODE::G_EXTRACT_VECTOR_ELT
@ G_EXTRACT_VECTOR_ELT
Definition riscv/opcodes.hpp:251
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF4
@ PseudoVLOXSEG5EI64_V_M2_MF4
Definition riscv/opcodes.hpp:4742
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E64_V_M1
@ PseudoVSSSEG7E64_V_M1
Definition riscv/opcodes.hpp:10389
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF8_E8
@ PseudoVREDOR_VS_MF8_E8
Definition riscv/opcodes.hpp:7962
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M8_E32
@ PseudoVFNMSUB_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2813
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M4_MASK
@ PseudoVNCLIP_WI_M4_MASK
Definition riscv/opcodes.hpp:7467
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF2_MASK
@ PseudoVFNCVT_XU_F_W_MF2_MASK
Definition riscv/opcodes.hpp:2598
LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_MF2
@ PseudoVAESKF2_VI_MF2
Definition riscv/opcodes.hpp:765
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M4
@ PseudoVSUXEI32_V_M4_M4
Definition riscv/opcodes.hpp:10565
LIEF::assembly::riscv::OPCODE::VFCVT_RTZ_X_F_V
@ VFCVT_RTZ_X_F_V
Definition riscv/opcodes.hpp:13210
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF4_MASK
@ PseudoVWSUB_WX_MF4_MASK
Definition riscv/opcodes.hpp:11836
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M4
@ PseudoVLUXEI8_V_MF2_M4
Definition riscv/opcodes.hpp:5706
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF2_E16
@ PseudoVFMUL_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2320
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M8
@ PseudoVFSLIDE1UP_VFPR32_M8
Definition riscv/opcodes.hpp:3349
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_M1
@ PseudoVLOXSEG3EI16_V_MF4_M1
Definition riscv/opcodes.hpp:4490
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E32
@ PseudoVFCVT_F_X_V_M4_E32
Definition riscv/opcodes.hpp:1715
LIEF::assembly::riscv::OPCODE::VAESEF_VS
@ VAESEF_VS
Definition riscv/opcodes.hpp:13145
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M4
@ PseudoVFCVT_X_F_V_M4
Definition riscv/opcodes.hpp:1855
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF4_MASK
@ PseudoVSLIDEDOWN_VX_MF4_MASK
Definition riscv/opcodes.hpp:8847
LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_S_INX
@ PseudoQuietFLT_S_INX
Definition riscv/opcodes.hpp:431
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF2_MASK
@ PseudoVLOXSEG6EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4821
LIEF::assembly::riscv::OPCODE::VSSEG4E64_V
@ VSSEG4E64_V
Definition riscv/opcodes.hpp:13712
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF8
@ PseudoVADD_VX_MF8
Definition riscv/opcodes.hpp:638
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_M1_MASK
@ PseudoVLOXEI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4213
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E32
@ PseudoVFWADD_VV_M2_E32
Definition riscv/opcodes.hpp:3475
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMINIMUM
@ G_VECREDUCE_FMINIMUM
Definition riscv/opcodes.hpp:307
LIEF::assembly::riscv::OPCODE::CV_MACSN
@ CV_MACSN
Definition riscv/opcodes.hpp:12338
LIEF::assembly::riscv::OPCODE::VFRSUB_VF
@ VFRSUB_VF
Definition riscv/opcodes.hpp:13260
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M2
@ PseudoVSSEG3E16_V_M2
Definition riscv/opcodes.hpp:10029
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E16
@ PseudoVFNCVT_F_XU_W_M2_E16
Definition riscv/opcodes.hpp:2457
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_MF2
@ PseudoVSSEG5E32_V_MF2
Definition riscv/opcodes.hpp:10091
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF8_MASK
@ PseudoVAADDU_VX_MF8_MASK
Definition riscv/opcodes.hpp:548
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_MF2
@ PseudoVSOXSEG4EI64_V_M4_MF2
Definition riscv/opcodes.hpp:9477
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E16_MASK
@ PseudoVFWADD_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3474
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF4_MASK
@ PseudoVMADD_VX_MF4_MASK
Definition riscv/opcodes.hpp:6497
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1
@ PseudoVWSUB_WV_M1
Definition riscv/opcodes.hpp:11803
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M2
@ PseudoVSE16_V_M2
Definition riscv/opcodes.hpp:8704
LIEF::assembly::riscv::OPCODE::G_UBSANTRAP
@ G_UBSANTRAP
Definition riscv/opcodes.hpp:299
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M4_E64_MASK
@ PseudoVFMSAC_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2219
LIEF::assembly::riscv::OPCODE::VFNCVT_X_F_W
@ VFNCVT_X_F_W
Definition riscv/opcodes.hpp:13242
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M2_E32_MASK
@ PseudoVFMACC_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:1952
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_M2
@ PseudoVC_V_IVW_SE_M2
Definition riscv/opcodes.hpp:1269
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF8
@ PseudoVSSRA_VX_MF8
Definition riscv/opcodes.hpp:10203
LIEF::assembly::riscv::OPCODE::VSOXSEG7EI8_V
@ VSOXSEG7EI8_V
Definition riscv/opcodes.hpp:13687
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M4
@ PseudoVWMUL_VV_M4
Definition riscv/opcodes.hpp:11591
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK
@ PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:1758
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E8
@ PseudoVREDOR_VS_MF4_E8
Definition riscv/opcodes.hpp:7960
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M2_MASK
@ PseudoVSSEG3E64_V_M2_MASK
Definition riscv/opcodes.hpp:10044
LIEF::assembly::riscv::OPCODE::VSOXSEG3EI32_V
@ VSOXSEG3EI32_V
Definition riscv/opcodes.hpp:13669
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF4_MASK
@ PseudoVWMULSU_VX_MF4_MASK
Definition riscv/opcodes.hpp:11560
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M4_E32_MASK
@ PseudoVFRDIV_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2892
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E32
@ PseudoVRGATHER_VV_M8_E32
Definition riscv/opcodes.hpp:8474
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E64
@ PseudoVFCVT_RM_F_XU_V_M2_E64
Definition riscv/opcodes.hpp:1741
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E8_MASK
@ PseudoVDIV_VX_M1_E8_MASK
Definition riscv/opcodes.hpp:1562
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF4_E16_MASK
@ PseudoVFWADD_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3460
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M2_E16
@ PseudoVFMAX_VFPR16_M2_E16
Definition riscv/opcodes.hpp:2059
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M1
@ PseudoVSSRL_VI_M1
Definition riscv/opcodes.hpp:10205
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M2
@ PseudoVRGATHEREI16_VV_M2_E32_M2
Definition riscv/opcodes.hpp:8316
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E8
@ PseudoVREDSUM_VS_M1_E8
Definition riscv/opcodes.hpp:7970
LIEF::assembly::riscv::OPCODE::CV_LW_rr
@ CV_LW_rr
Definition riscv/opcodes.hpp:12331
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M1
@ PseudoVBREV8_V_M1
Definition riscv/opcodes.hpp:916
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M8
@ PseudoVMSLEU_VV_M8
Definition riscv/opcodes.hpp:7099
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_MF4
@ PseudoVMADC_VX_MF4
Definition riscv/opcodes.hpp:6470
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E32_MASK
@ PseudoVFSGNJ_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3286
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M1
@ PseudoVNCLIPU_WX_M1
Definition riscv/opcodes.hpp:7450
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E16_MASK
@ PseudoVREDXOR_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:8009
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M4
@ PseudoVSUXSEG2EI32_V_M8_M4
Definition riscv/opcodes.hpp:10719
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M1_MASK
@ PseudoVRSUB_VX_M1_MASK
Definition riscv/opcodes.hpp:8591
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M8_M1_MASK
@ PseudoVLUXSEG8EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:6381
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M1_E64
@ PseudoVFSGNJ_VFPR64_M1_E64
Definition riscv/opcodes.hpp:3263
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_M1_MASK
@ PseudoVSOXSEG7EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9734
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_MF2_MASK
@ PseudoVSOXSEG5EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:9568
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E16_MASK
@ PseudoVREM_VX_M1_E16_MASK
Definition riscv/opcodes.hpp:8217
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF4_MASK
@ PseudoVSUXSEG5EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:11026
LIEF::assembly::riscv::OPCODE::CV_CLIPR
@ CV_CLIPR
Definition riscv/opcodes.hpp:12208
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M8_MASK
@ PseudoVSSRA_VV_M8_MASK
Definition riscv/opcodes.hpp:10184
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF8_E8
@ PseudoVREDAND_VS_MF8_E8
Definition riscv/opcodes.hpp:7742
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M1_MASK
@ PseudoVSUXSEG2EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10772
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E32_MASK
@ PseudoVFMAX_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:2114
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_MF2
@ PseudoVLOXSEG3EI64_V_M4_MF2
Definition riscv/opcodes.hpp:4546
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2
@ PseudoVWSUB_WV_MF2
Definition riscv/opcodes.hpp:11815
LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M8
@ PseudoVLSE64_V_M8
Definition riscv/opcodes.hpp:5038
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF8_MASK
@ PseudoVLSEG2E8FF_V_MF8_MASK
Definition riscv/opcodes.hpp:5113
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF4_MASK
@ PseudoVLOXSEG7EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:4903
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B16
@ PseudoVCPOP_M_B16
Definition riscv/opcodes.hpp:1037
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF4_MASK
@ PseudoVSSSEG2E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10280
LIEF::assembly::riscv::OPCODE::ZIP_RV32
@ ZIP_RV32
Definition riscv/opcodes.hpp:13854
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF2_MASK
@ PseudoVLUXSEG2EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:5751
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF8
@ PseudoVCTZ_V_MF8
Definition riscv/opcodes.hpp:1076
LIEF::assembly::riscv::OPCODE::CBO_FLUSH
@ CBO_FLUSH
Definition riscv/opcodes.hpp:12135
LIEF::assembly::riscv::OPCODE::VWADDU_VX
@ VWADDU_VX
Definition riscv/opcodes.hpp:13805
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M1_MASK
@ PseudoVLOXSEG4EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4653
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M4
@ PseudoVMADC_VVM_M4
Definition riscv/opcodes.hpp:6446
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF2_MASK
@ PseudoVAND_VI_MF2_MASK
Definition riscv/opcodes.hpp:827
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E16_MASK
@ PseudoVFWCVT_F_F_V_M4_E16_MASK
Definition riscv/opcodes.hpp:3568
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E32
@ PseudoVFNMSUB_VV_MF2_E32
Definition riscv/opcodes.hpp:2851
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E32_MASK
@ PseudoVFWADD_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3476
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M4
@ PseudoVMV_V_I_M4
Definition riscv/opcodes.hpp:7392
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M2
@ PseudoVASUB_VV_M2
Definition riscv/opcodes.hpp:890
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_MF2
@ PseudoVLUXEI32_V_M2_MF2
Definition riscv/opcodes.hpp:5626
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M4_M1_MASK
@ PseudoVLUXSEG7EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:6273
LIEF::assembly::riscv::OPCODE::AMOAND_D_RL
@ AMOAND_D_RL
Definition riscv/opcodes.hpp:11970
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M8
@ PseudoVFMV_V_FPR16_M8
Definition riscv/opcodes.hpp:2405
LIEF::assembly::riscv::OPCODE::TH_DCACHE_CIPA
@ TH_DCACHE_CIPA
Definition riscv/opcodes.hpp:13030
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M2
@ PseudoVSUXEI64_V_M8_M2
Definition riscv/opcodes.hpp:10609
LIEF::assembly::riscv::OPCODE::VLSEG3E8FF_V
@ VLSEG3E8FF_V
Definition riscv/opcodes.hpp:13382
LIEF::assembly::riscv::OPCODE::PseudoLH
@ PseudoLH
Definition riscv/opcodes.hpp:394
LIEF::assembly::riscv::OPCODE::VC_IV
@ VC_IV
Definition riscv/opcodes.hpp:13176
LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D_AQ
@ SSAMOSWAP_D_AQ
Definition riscv/opcodes.hpp:13005
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_MF2_MASK
@ PseudoVLOXSEG4EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4585
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF8_MASK
@ PseudoVLOXSEG3EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:4579
LIEF::assembly::riscv::OPCODE::OR
@ OR
Definition riscv/opcodes.hpp:12906
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF4
@ PseudoVASUBU_VX_MF4
Definition riscv/opcodes.hpp:884
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M8_E16
@ PseudoVFMAX_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2063
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M4
@ PseudoVWSUB_WX_M4
Definition riscv/opcodes.hpp:11831
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF4_E16_MASK
@ PseudoVFWNMSAC_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3910
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_MF2
@ PseudoVC_V_XVV_MF2
Definition riscv/opcodes.hpp:1346
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E64_MASK
@ PseudoVFNMSUB_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:2848
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E8_MASK
@ PseudoVRGATHER_VV_M4_E8_MASK
Definition riscv/opcodes.hpp:8471
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF4_MASK
@ PseudoVSUXSEG4EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:11012
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF4_E16
@ PseudoVFNCVT_ROD_F_F_W_MF4_E16
Definition riscv/opcodes.hpp:2565
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E64_MASK
@ PseudoVFSGNJX_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:3228
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M1_E32_MASK
@ PseudoVFRDIV_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2888
LIEF::assembly::riscv::OPCODE::CV_DOTSP_B
@ CV_DOTSP_B
Definition riscv/opcodes.hpp:12281
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF8_MASK
@ PseudoVLOXSEG6EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:4809
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_M1_MASK
@ PseudoVSUXSEG7EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11182
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF8_MASK
@ PseudoVMACC_VV_MF8_MASK
Definition riscv/opcodes.hpp:6415
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF8_MASK
@ PseudoVAND_VI_MF8_MASK
Definition riscv/opcodes.hpp:831
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M4_E16_MASK
@ PseudoVFMSAC_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2197
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_MF2_MASK
@ PseudoVLSEG7E32FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5333
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E8_MASK
@ PseudoVREM_VV_MF2_E8_MASK
Definition riscv/opcodes.hpp:8209
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_M1_MASK
@ PseudoVSOXSEG7EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:9744
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M1
@ PseudoVFSLIDE1DOWN_VFPR16_M1
Definition riscv/opcodes.hpp:3301
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF8_MASK
@ PseudoVSOXSEG8EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:9770
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M1_MASK
@ PseudoVLSEG3E64_V_M1_MASK
Definition riscv/opcodes.hpp:5159
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_M1
@ PseudoVAESEM_VS_M2_M1
Definition riscv/opcodes.hpp:731
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M8
@ PseudoVSADDU_VV_M8
Definition riscv/opcodes.hpp:8624
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E32_MASK
@ PseudoVDIVU_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:1434
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF8_E8_MASK
@ PseudoVREM_VV_MF8_E8_MASK
Definition riscv/opcodes.hpp:8215
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF2_MASK
@ PseudoVLUXSEG5EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:6157
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M2_MASK
@ PseudoVSUXSEG4EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10950
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF2_MASK
@ PseudoVLUXSEG7EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6251
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_MF4_MASK
@ PseudoVFCVT_RM_XU_F_V_MF4_MASK
Definition riscv/opcodes.hpp:1802
LIEF::assembly::riscv::OPCODE::VLE8FF_V
@ VLE8FF_V
Definition riscv/opcodes.hpp:13329
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E16_MASK
@ PseudoVFREDMAX_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:2942
LIEF::assembly::riscv::OPCODE::VS4R_V
@ VS4R_V
Definition riscv/opcodes.hpp:13620
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF8_MASK
@ PseudoVSADDU_VI_MF8_MASK
Definition riscv/opcodes.hpp:8617
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M2
@ PseudoVRGATHEREI16_VV_M1_E16_M2
Definition riscv/opcodes.hpp:8276
LIEF::assembly::riscv::OPCODE::AMOADD_B_AQ_RL
@ AMOADD_B_AQ_RL
Definition riscv/opcodes.hpp:11949
LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_M4
@ PseudoVC_X_SE_M4
Definition riscv/opcodes.hpp:1418
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF4
@ PseudoVSUXSEG2EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:10725
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E32_MASK
@ PseudoVREDMINU_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:7835
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF2_MASK
@ PseudoVLSSEG2E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5429
LIEF::assembly::riscv::OPCODE::SRAIW
@ SRAIW
Definition riscv/opcodes.hpp:12997
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF8_MASK
@ PseudoVLUXSEG5EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:6101
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_MF2
@ PseudoVSUXSEG3EI16_V_M1_MF2
Definition riscv/opcodes.hpp:10799
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF4
@ PseudoVNSRL_WV_MF4
Definition riscv/opcodes.hpp:7610
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E8
@ PseudoVREDXOR_VS_M4_E8
Definition riscv/opcodes.hpp:8030
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_M1
@ PseudoVSOXSEG4EI16_V_MF4_M1
Definition riscv/opcodes.hpp:9421
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_MF2
@ PseudoVSOXSEG6EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:9655
LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64_AQ
@ AMOCAS_D_RV64_AQ
Definition riscv/opcodes.hpp:11988
LIEF::assembly::riscv::OPCODE::G_STRICT_FDIV
@ G_STRICT_FDIV
Definition riscv/opcodes.hpp:285
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M4_E32
@ PseudoVFWMUL_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3817
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M2_MASK
@ PseudoVIOTA_M_M2_MASK
Definition riscv/opcodes.hpp:4072
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF2
@ PseudoVLSEG4E8FF_V_MF2
Definition riscv/opcodes.hpp:5222
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M4
@ PseudoVSOXSEG2EI8_V_M1_M4
Definition riscv/opcodes.hpp:9259
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF8
@ PseudoVROL_VX_MF8
Definition riscv/opcodes.hpp:8532
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_M1
@ PseudoVLOXSEG5EI32_V_MF2_M1
Definition riscv/opcodes.hpp:4722
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M4_MASK
@ PseudoVSUXSEG2EI8_V_M2_M4_MASK
Definition riscv/opcodes.hpp:10768
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_MF8
@ PseudoVAESEF_VS_M1_MF8
Definition riscv/opcodes.hpp:701
LIEF::assembly::riscv::OPCODE::ReadFFLAGS
@ ReadFFLAGS
Definition riscv/opcodes.hpp:11914
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M1_MASK
@ PseudoVLUXSEG2EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:5747
LIEF::assembly::riscv::OPCODE::AMOMINU_D_AQ_RL
@ AMOMINU_D_AQ_RL
Definition riscv/opcodes.hpp:12041
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_M1
@ PseudoVLUXSEG4EI16_V_MF4_M1
Definition riscv/opcodes.hpp:5992
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M1_MASK
@ PseudoVMFGE_VFPR64_M1_MASK
Definition riscv/opcodes.hpp:6663
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M8_E16
@ PseudoVFMSUB_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2258
LIEF::assembly::riscv::OPCODE::PseudoReadVLENB
@ PseudoReadVLENB
Definition riscv/opcodes.hpp:440
LIEF::assembly::riscv::OPCODE::G_SDIV
@ G_SDIV
Definition riscv/opcodes.hpp:78
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_MF2
@ PseudoVAESZ_VS_M4_MF2
Definition riscv/opcodes.hpp:778
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E16_MASK
@ PseudoVFWNMACC_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3866
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E64
@ PseudoVREM_VX_M1_E64
Definition riscv/opcodes.hpp:8220
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF4
@ PseudoVSUXSEG2EI32_V_M1_MF4
Definition riscv/opcodes.hpp:10701
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF2
@ PseudoVFNCVT_RTZ_X_F_W_MF2
Definition riscv/opcodes.hpp:2585
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF4_MASK
@ PseudoVSUXSEG4EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:10930
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E64_MASK
@ PseudoVFCVT_F_X_V_M1_E64_MASK
Definition riscv/opcodes.hpp:1706
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M1_E64_MASK
@ PseudoVFRSUB_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:3114
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF8
@ PseudoVSOXSEG2EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:9289
LIEF::assembly::riscv::OPCODE::FCVT_LU_S
@ FCVT_LU_S
Definition riscv/opcodes.hpp:12607
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK
@ PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK
Definition riscv/opcodes.hpp:8429
LIEF::assembly::riscv::OPCODE::VLE64FF_V
@ VLE64FF_V
Definition riscv/opcodes.hpp:13327
LIEF::assembly::riscv::OPCODE::VMFNE_VF
@ VMFNE_VF
Definition riscv/opcodes.hpp:13511
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF2_E16
@ PseudoVFWADD_WFPR16_MF2_E16
Definition riscv/opcodes.hpp:3493
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_M1
@ PseudoVFMV_S_FPR16_M1
Definition riscv/opcodes.hpp:2387
LIEF::assembly::riscv::OPCODE::AMOMAXU_H_AQ_RL
@ AMOMAXU_H_AQ_RL
Definition riscv/opcodes.hpp:12013
LIEF::assembly::riscv::OPCODE::G_READ_REGISTER
@ G_READ_REGISTER
Definition riscv/opcodes.hpp:290
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_MF8
@ PseudoVMERGE_VIM_MF8
Definition riscv/opcodes.hpp:6583
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M1_MASK
@ PseudoVLOXSEG3EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4565
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M1
@ PseudoVSOXSEG4EI32_V_M2_M1
Definition riscv/opcodes.hpp:9437
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M1
@ PseudoVLSEG2E16_V_M1
Definition riscv/opcodes.hpp:5064
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_M1_MASK
@ PseudoVSUXSEG5EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11016
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF2_MASK
@ PseudoVSSEG2E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10022
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E8
@ PseudoVFWCVT_F_XU_V_MF2_E8
Definition riscv/opcodes.hpp:3599
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E64_V_M1
@ PseudoVLSSEG8E64_V_M1
Definition riscv/opcodes.hpp:5560
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M1_MASK
@ PseudoVLSEG2E8_V_M1_MASK
Definition riscv/opcodes.hpp:5115
LIEF::assembly::riscv::OPCODE::AMOMAXU_H_RL
@ AMOMAXU_H_RL
Definition riscv/opcodes.hpp:12014
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_MF2_MASK
@ PseudoVSSSEG6E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10368
LIEF::assembly::riscv::OPCODE::VLOXSEG4EI16_V
@ VLOXSEG4EI16_V
Definition riscv/opcodes.hpp:13344
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M1
@ PseudoVSSSEG2E32_V_M1
Definition riscv/opcodes.hpp:10257
LIEF::assembly::riscv::OPCODE::CV_CMPNE_H
@ CV_CMPNE_H
Definition riscv/opcodes.hpp:12266
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E64
@ PseudoVDIV_VV_M1_E64
Definition riscv/opcodes.hpp:1515
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M2
@ PseudoVLSSEG2E32_V_M2
Definition riscv/opcodes.hpp:5410
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M1_MASK
@ PseudoVLSEG3E8FF_V_M1_MASK
Definition riscv/opcodes.hpp:5163
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E32
@ PseudoVFWREDUSUM_VS_MF2_E32
Definition riscv/opcodes.hpp:3951
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E64_MASK
@ PseudoVFCVT_F_XU_V_M1_E64_MASK
Definition riscv/opcodes.hpp:1676
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF2_E16
@ PseudoVFSGNJ_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3249
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M4_E32
@ PseudoVFMAX_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2073
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M1_MASK
@ PseudoVOR_VI_M1_MASK
Definition riscv/opcodes.hpp:7627
LIEF::assembly::riscv::OPCODE::VSSSEG6E16_V
@ VSSSEG6E16_V
Definition riscv/opcodes.hpp:13752
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M1_MASK
@ PseudoVSOXEI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9042
LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_MF2
@ PseudoVSE32_V_MF2
Definition riscv/opcodes.hpp:8722
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M4
@ PseudoVFSLIDE1UP_VFPR64_M4
Definition riscv/opcodes.hpp:3357
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E64
@ PseudoVREDSUM_VS_M8_E64
Definition riscv/opcodes.hpp:7992
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E64
@ PseudoVFADD_VV_M1_E64
Definition riscv/opcodes.hpp:1633
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_MF2
@ PseudoVAESZ_VS_M8_MF2
Definition riscv/opcodes.hpp:784
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M2
@ PseudoVLOXSEG2EI8_V_M2_M2
Definition riscv/opcodes.hpp:4440
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF4
@ PseudoVLSSEG2E16_V_MF4
Definition riscv/opcodes.hpp:5406
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M2_MASK
@ PseudoVLUXSEG4EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:6011
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_M1_MASK
@ PseudoVSOXSEG6EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9604
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M2_M2
@ PseudoVSOXSEG4EI8_V_M2_M2
Definition riscv/opcodes.hpp:9487
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF4
@ PseudoVLUXSEG2EI64_V_M1_MF4
Definition riscv/opcodes.hpp:5800
LIEF::assembly::riscv::OPCODE::FCVT_L_D
@ FCVT_L_D
Definition riscv/opcodes.hpp:12609
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M4
@ PseudoVMAX_VV_M4
Definition riscv/opcodes.hpp:6546
LIEF::assembly::riscv::OPCODE::CV_MAX_SC_H
@ CV_MAX_SC_H
Definition riscv/opcodes.hpp:12355
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_MF2
@ PseudoVC_V_IVV_MF2
Definition riscv/opcodes.hpp:1252
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M2
@ PseudoVLE16FF_V_M2
Definition riscv/opcodes.hpp:4085
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_M1_MASK
@ PseudoVSOXEI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:9148
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E16_MASK
@ PseudoVFCVT_RM_F_X_V_M2_E16_MASK
Definition riscv/opcodes.hpp:1768
LIEF::assembly::riscv::OPCODE::VLSEG4E16FF_V
@ VLSEG4E16FF_V
Definition riscv/opcodes.hpp:13384
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_M1_MASK
@ PseudoVLOXSEG5EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:4763
LIEF::assembly::riscv::OPCODE::CV_CMPNE_SC_H
@ CV_CMPNE_SC_H
Definition riscv/opcodes.hpp:12270
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E64_MASK
@ PseudoVDIVU_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:1436
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E16_MASK
@ PseudoVFNCVT_F_XU_W_M1_E16_MASK
Definition riscv/opcodes.hpp:2454
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32_TIED
@ PseudoVFWSUB_WV_M1_E32_TIED
Definition riscv/opcodes.hpp:4016
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E16
@ PseudoVWREDSUMU_VS_M1_E16
Definition riscv/opcodes.hpp:11611
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E32_MASK
@ PseudoVREM_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:8175
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M8_MASK
@ PseudoVSUXEI16_V_M2_M8_MASK
Definition riscv/opcodes.hpp:10518
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF2_MASK
@ PseudoVLUXSEG3EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:5931
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF4_MASK
@ PseudoVWADD_VV_MF4_MASK
Definition riscv/opcodes.hpp:11404
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M4_MASK
@ PseudoVFNCVT_X_F_W_M4_MASK
Definition riscv/opcodes.hpp:2608
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M8
@ PseudoVSSRL_VV_M8
Definition riscv/opcodes.hpp:10225
LIEF::assembly::riscv::OPCODE::G_VMCLR_VL
@ G_VMCLR_VL
Definition riscv/opcodes.hpp:325
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF2
@ PseudoVSRL_VI_MF2
Definition riscv/opcodes.hpp:9913
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_M1
@ PseudoVSOXSEG6EI64_V_M1_M1
Definition riscv/opcodes.hpp:9631
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4_TIED
@ PseudoVWSUBU_WV_MF4_TIED
Definition riscv/opcodes.hpp:11762
LIEF::assembly::riscv::OPCODE::VSSEG6E32_V
@ VSSEG6E32_V
Definition riscv/opcodes.hpp:13719
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M4
@ PseudoVMFGE_VFPR16_M4
Definition riscv/opcodes.hpp:6644
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_MF2_MASK
@ PseudoVSUXSEG8EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11320
LIEF::assembly::riscv::OPCODE::VSRL_VV
@ VSRL_VV
Definition riscv/opcodes.hpp:13696
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF2
@ PseudoVLUXEI32_V_M1_MF2
Definition riscv/opcodes.hpp:5616
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E8
@ PseudoVREDOR_VS_M8_E8
Definition riscv/opcodes.hpp:7950
LIEF::assembly::riscv::OPCODE::FCVT_D_S_IN32X
@ FCVT_D_S_IN32X
Definition riscv/opcodes.hpp:12582
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF2
@ PseudoVSADDU_VI_MF2
Definition riscv/opcodes.hpp:8612
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M1_MASK
@ PseudoVAND_VI_M1_MASK
Definition riscv/opcodes.hpp:819
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E8
@ PseudoVREM_VV_M2_E8
Definition riscv/opcodes.hpp:8186
LIEF::assembly::riscv::OPCODE::AMOMAX_B_RL
@ AMOMAX_B_RL
Definition riscv/opcodes.hpp:12022
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M2_E16
@ PseudoVFNMSUB_VFPR16_M2_E16
Definition riscv/opcodes.hpp:2797
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E8_MASK
@ PseudoVREDSUM_VS_M8_E8_MASK
Definition riscv/opcodes.hpp:7995
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_M1
@ PseudoVLSEG5E32FF_V_M1
Definition riscv/opcodes.hpp:5250
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M2
@ PseudoVLUXSEG2EI8_V_M2_M2
Definition riscv/opcodes.hpp:5832
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E32
@ PseudoVFMSUB_VV_M2_E32
Definition riscv/opcodes.hpp:2290
LIEF::assembly::riscv::OPCODE::PseudoCmpXchg64
@ PseudoCmpXchg64
Definition riscv/opcodes.hpp:370
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_M1
@ PseudoVSOXSEG7EI64_V_M1_M1
Definition riscv/opcodes.hpp:9711
LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M1_MASK
@ PseudoVFROUND_NOEXCEPT_V_M1_MASK
Definition riscv/opcodes.hpp:3055
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M2_MASK
@ PseudoVLSSEG4E16_V_M2_MASK
Definition riscv/opcodes.hpp:5465
LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M1
@ PseudoVAESKF1_VI_M1
Definition riscv/opcodes.hpp:756
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M1
@ PseudoVZEXT_VF2_M1
Definition riscv/opcodes.hpp:11881
LIEF::assembly::riscv::OPCODE::TH_SYNC_S
@ TH_SYNC_S
Definition riscv/opcodes.hpp:13126
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF2_MASK
@ PseudoVMIN_VV_MF2_MASK
Definition riscv/opcodes.hpp:6863
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M4_MASK
@ PseudoVSUXEI32_V_M4_M4_MASK
Definition riscv/opcodes.hpp:10566
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF4
@ PseudoVLOXSEG3EI64_V_M2_MF4
Definition riscv/opcodes.hpp:4540
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M1
@ PseudoVRSUB_VI_M1
Definition riscv/opcodes.hpp:8576
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF8
@ PseudoVSUXEI16_V_MF4_MF8
Definition riscv/opcodes.hpp:10543
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M2_MASK
@ PseudoVLSEG3E8FF_V_M2_MASK
Definition riscv/opcodes.hpp:5165
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF4_MASK
@ PseudoVLOXSEG8EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:5001
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF2_E16
@ PseudoVFRSUB_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3099
LIEF::assembly::riscv::OPCODE::CV_XOR_B
@ CV_XOR_B
Definition riscv/opcodes.hpp:12467
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E64_MASK
@ PseudoVREMU_VX_M8_E64_MASK
Definition riscv/opcodes.hpp:8157
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF8
@ PseudoVMULH_VX_MF8
Definition riscv/opcodes.hpp:7359
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M2_MASK
@ PseudoVBREV_V_M2_MASK
Definition riscv/opcodes.hpp:933
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M2_MASK
@ PseudoVRGATHEREI16_VV_M1_E64_M2_MASK
Definition riscv/opcodes.hpp:8293
LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M4
@ PseudoVLSE32_V_M4
Definition riscv/opcodes.hpp:5026
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M4_E16
@ PseudoVFRDIV_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2879
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M4_MASK
@ PseudoVLOXEI32_V_M4_M4_MASK
Definition riscv/opcodes.hpp:4241
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8_TIED
@ PseudoVWADD_WV_MF8_TIED
Definition riscv/opcodes.hpp:11442
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M4_MASK
@ PseudoVRGATHEREI16_VV_M2_E64_M4_MASK
Definition riscv/opcodes.hpp:8327
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M4_MASK
@ PseudoVSRL_VV_M4_MASK
Definition riscv/opcodes.hpp:9924
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF8
@ PseudoVRGATHEREI16_VV_MF2_E8_MF8
Definition riscv/opcodes.hpp:8416
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M8_MASK
@ PseudoVZEXT_VF4_M8_MASK
Definition riscv/opcodes.hpp:11900
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF8
@ PseudoVSSEG2E8_V_MF8
Definition riscv/opcodes.hpp:10025
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF8
@ PseudoVFNRCLIP_XU_F_QF_MF8
Definition riscv/opcodes.hpp:2863
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M4_MASK
@ PseudoVLUXSEG2EI64_V_M8_M4_MASK
Definition riscv/opcodes.hpp:5825
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_MF2
@ PseudoVMV_V_I_MF2
Definition riscv/opcodes.hpp:7394
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF8_MASK
@ PseudoVLOXSEG5EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:4769
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1_MASK
@ PseudoVWSUBU_WV_M1_MASK
Definition riscv/opcodes.hpp:11744
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF2_MASK
@ PseudoVLOXSEG7EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4859
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF4
@ PseudoVLSEG6E16_V_MF4
Definition riscv/opcodes.hpp:5288
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_M2
@ PseudoVC_V_IVV_M2
Definition riscv/opcodes.hpp:1249
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M2
@ PseudoVMFLT_VV_M2
Definition riscv/opcodes.hpp:6774
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M2
@ PseudoVMSLT_VX_M2
Definition riscv/opcodes.hpp:7209
LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M8_MASK
@ PseudoVLE32FF_V_M8_MASK
Definition riscv/opcodes.hpp:4114
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M4_MASK
@ PseudoVSLL_VX_M4_MASK
Definition riscv/opcodes.hpp:8911
LIEF::assembly::riscv::OPCODE::CSRRWI
@ CSRRWI
Definition riscv/opcodes.hpp:12158
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF2
@ PseudoVLOXSEG5EI64_V_M1_MF2
Definition riscv/opcodes.hpp:4732
LIEF::assembly::riscv::OPCODE::VMSEQ_VX
@ VMSEQ_VX
Definition riscv/opcodes.hpp:13528
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF4
@ PseudoVSOXSEG2EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:9281
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M4
@ PseudoVSRA_VX_M4
Definition riscv/opcodes.hpp:9895
LIEF::assembly::riscv::OPCODE::CV_ADDN
@ CV_ADDN
Definition riscv/opcodes.hpp:12164
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M2
@ PseudoVMV_V_I_M2
Definition riscv/opcodes.hpp:7391
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF2_MASK
@ PseudoVSOXSEG4EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9470
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF2
@ PseudoVSLIDEDOWN_VX_MF2
Definition riscv/opcodes.hpp:8844
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF2
@ PseudoVASUB_VV_MF2
Definition riscv/opcodes.hpp:896
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M1_MASK
@ PseudoVSUXSEG4EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:11000
LIEF::assembly::riscv::OPCODE::CV_MINU_SCI_B
@ CV_MINU_SCI_B
Definition riscv/opcodes.hpp:12360
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E16_MASK
@ PseudoVFREDMIN_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:2966
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E32_MASK
@ PseudoVFCVT_F_X_V_M4_E32_MASK
Definition riscv/opcodes.hpp:1716
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E16_MASK
@ PseudoVFSQRT_V_M2_E16_MASK
Definition riscv/opcodes.hpp:3368
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M1
@ PseudoVWADD_WX_M1
Definition riscv/opcodes.hpp:11443
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M1
@ PseudoVMSLE_VI_M1
Definition riscv/opcodes.hpp:7121
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M8
@ PseudoVRSUB_VI_M8
Definition riscv/opcodes.hpp:8582
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32_MASK_TIED
@ PseudoVFWSUB_WV_MF2_E32_MASK_TIED
Definition riscv/opcodes.hpp:4039
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M1
@ PseudoVMACC_VX_M1
Definition riscv/opcodes.hpp:6416
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_M1
@ PseudoVLUXSEG5EI64_V_M1_M1
Definition riscv/opcodes.hpp:6122
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF2_MASK
@ PseudoVSSUBU_VV_MF2_MASK
Definition riscv/opcodes.hpp:10428
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E8
@ PseudoVCOMPRESS_VM_M1_E8
Definition riscv/opcodes.hpp:1017
LIEF::assembly::riscv::OPCODE::G_FCMP
@ G_FCMP
Definition riscv/opcodes.hpp:166
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF4
@ PseudoVLOXSEG7EI64_V_M2_MF4
Definition riscv/opcodes.hpp:4902
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_M4
@ PseudoVC_V_IV_M4
Definition riscv/opcodes.hpp:1276
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M2
@ PseudoVRGATHEREI16_VV_M4_E32_M2
Definition riscv/opcodes.hpp:8348
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M4_MASK
@ PseudoVSUXEI64_V_M4_M4_MASK
Definition riscv/opcodes.hpp:10604
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF8
@ PseudoVSUXSEG4EI64_V_M1_MF8
Definition riscv/opcodes.hpp:10967
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M2_MASK
@ PseudoVLUXSEG3EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:5937
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M2
@ PseudoVSOXSEG3EI64_V_M2_M2
Definition riscv/opcodes.hpp:9357
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M1
@ PseudoVOR_VV_M1
Definition riscv/opcodes.hpp:7640
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E32_MASK
@ PseudoVREDOR_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:7947
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_M1
@ PseudoVAESZ_VS_M1_M1
Definition riscv/opcodes.hpp:766
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF4_E16_MASK
@ PseudoVFADD_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:1658
LIEF::assembly::riscv::OPCODE::FMIN_D
@ FMIN_D
Definition riscv/opcodes.hpp:12706
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M2_E16
@ PseudoVFNMSAC_VFPR16_M2_E16
Definition riscv/opcodes.hpp:2737
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M4
@ PseudoVNSRA_WV_M4
Definition riscv/opcodes.hpp:7570
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF2
@ PseudoVSUXSEG8EI32_V_M1_MF2
Definition riscv/opcodes.hpp:11277
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF4_E16
@ PseudoVFWADD_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3459
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_M1_MASK
@ PseudoVLUXSEG2EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:5855
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E16_MASK
@ PseudoVFWREDUSUM_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:3942
LIEF::assembly::riscv::OPCODE::VSOXSEG7EI64_V
@ VSOXSEG7EI64_V
Definition riscv/opcodes.hpp:13686
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M2_MASK
@ PseudoVSUXSEG4EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10914
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_M1
@ PseudoVLOXSEG5EI32_V_M1_M1
Definition riscv/opcodes.hpp:4710
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF4
@ PseudoVLOXSEG4EI32_V_M1_MF4
Definition riscv/opcodes.hpp:4614
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M8
@ PseudoVCLMULH_VX_M8
Definition riscv/opcodes.hpp:964
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64_V_M1
@ PseudoVLSEG8E64_V_M1
Definition riscv/opcodes.hpp:5380
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E16_MASK
@ PseudoVFSUB_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3446
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M8_MASK
@ PseudoVADD_VI_M8_MASK
Definition riscv/opcodes.hpp:605
LIEF::assembly::riscv::OPCODE::FMUL_H_INX
@ FMUL_H_INX
Definition riscv/opcodes.hpp:12724
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M4_M4_MASK
@ PseudoVLOXSEG2EI8_V_M4_M4_MASK
Definition riscv/opcodes.hpp:4445
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF2
@ PseudoVMSLTU_VV_MF2
Definition riscv/opcodes.hpp:7172
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_M1_MASK
@ PseudoVSUXSEG7EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:11248
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_MF2_MASK
@ PseudoVSOXSEG5EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9514
LIEF::assembly::riscv::OPCODE::KCFI_CHECK
@ KCFI_CHECK
Definition riscv/opcodes.hpp:328
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B1_MASK
@ PseudoVCPOP_M_B1_MASK
Definition riscv/opcodes.hpp:1039
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M8_MASK
@ PseudoVLOXEI8_V_M1_M8_MASK
Definition riscv/opcodes.hpp:4297
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E32_MASK
@ PseudoVRGATHER_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:8451
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_M8
@ PseudoVC_V_FPR16VW_SE_M8
Definition riscv/opcodes.hpp:1187
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M1_E64
@ PseudoVFMSAC_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2214
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M2_E32_MASK
@ PseudoVFWNMACC_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3852
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M4_E16
@ PseudoVFNCVT_RM_F_X_W_M4_E16
Definition riscv/opcodes.hpp:2515
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF4
@ PseudoVLSEG7E8_V_MF4
Definition riscv/opcodes.hpp:5354
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M4
@ PseudoVLUXEI32_V_M2_M4
Definition riscv/opcodes.hpp:5624
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF4_MASK
@ PseudoVSOXSEG6EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9628
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M8
@ PseudoVAND_VI_M8
Definition riscv/opcodes.hpp:824
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M4
@ PseudoVRGATHEREI16_VV_M8_E16_M4
Definition riscv/opcodes.hpp:8372
LIEF::assembly::riscv::OPCODE::CV_SUBRNR
@ CV_SUBRNR
Definition riscv/opcodes.hpp:12446
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E64
@ PseudoVFREDMIN_VS_M1_E64
Definition riscv/opcodes.hpp:2969
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M4_MASK
@ PseudoVSSSEG2E64_V_M4_MASK
Definition riscv/opcodes.hpp:10270
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF2_MASK
@ PseudoVROR_VI_MF2_MASK
Definition riscv/opcodes.hpp:8543
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B2
@ PseudoVFIRST_M_B2
Definition riscv/opcodes.hpp:1927
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M1
@ PseudoVSOXSEG4EI32_V_M4_M1
Definition riscv/opcodes.hpp:9443
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M8
@ PseudoVFCVT_RM_XU_F_V_M8
Definition riscv/opcodes.hpp:1797
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M2
@ PseudoVWMACCU_VV_M2
Definition riscv/opcodes.hpp:11493
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M1_MASK
@ PseudoVLUXEI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:5629
LIEF::assembly::riscv::OPCODE::FDIV_H_INX
@ FDIV_H_INX
Definition riscv/opcodes.hpp:12647
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_M1
@ PseudoVLSEG6E16_V_M1
Definition riscv/opcodes.hpp:5284
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M4
@ PseudoVLOXSEG2EI32_V_M2_M4
Definition riscv/opcodes.hpp:4382
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M1_MASK
@ PseudoVWSUBU_VX_M1_MASK
Definition riscv/opcodes.hpp:11732
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M4_MASK
@ PseudoVLUXEI8_V_M1_M4_MASK
Definition riscv/opcodes.hpp:5687
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M2
@ PseudoVWMACCUS_VX_M2
Definition riscv/opcodes.hpp:11481
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_M1_MASK
@ PseudoVSOXSEG8EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9758
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M8
@ PseudoVFCVT_XU_F_V_M8
Definition riscv/opcodes.hpp:1845
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF2
@ PseudoVLUXSEG8EI64_V_M1_MF2
Definition riscv/opcodes.hpp:6364
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF8_MASK
@ PseudoVLUXSEG8EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:6401
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E16
@ PseudoVFNMACC_VV_MF2_E16
Definition riscv/opcodes.hpp:2669
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M2_MASK
@ PseudoVLUXSEG4EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5981
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF2_MASK
@ PseudoVSSEG5E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10086
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_M1
@ PseudoVLUXSEG2EI64_V_M1_M1
Definition riscv/opcodes.hpp:5796
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_MF2_MASK
@ PseudoVLUXEI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:5673
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M2_MASK
@ PseudoVSOXSEG2EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9202
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M4
@ PseudoVWMULU_VX_M4
Definition riscv/opcodes.hpp:11579
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_MF2_MASK
@ PseudoVLUXSEG3EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:5903
LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_MF4
@ PseudoVSPILL5_MF4
Definition riscv/opcodes.hpp:9849
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_MF4
@ PseudoVC_V_XV_MF4
Definition riscv/opcodes.hpp:1373
LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_MF8
@ PseudoVC_IVW_SE_MF8
Definition riscv/opcodes.hpp:1131
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF2_MASK
@ PseudoVWADDU_WX_MF2_MASK
Definition riscv/opcodes.hpp:11390
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M1_MASK
@ PseudoVLOXEI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4229
LIEF::assembly::riscv::OPCODE::AMOADD_H_AQ_RL
@ AMOADD_H_AQ_RL
Definition riscv/opcodes.hpp:11957
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF4_MASK
@ PseudoVMIN_VX_MF4_MASK
Definition riscv/opcodes.hpp:6879
LIEF::assembly::riscv::OPCODE::AMOMIN_W_AQ_RL
@ AMOMIN_W_AQ_RL
Definition riscv/opcodes.hpp:12065
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_MF2
@ PseudoVSOXSEG5EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:9575
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M1_MASK
@ PseudoVMFGT_VFPR64_M1_MASK
Definition riscv/opcodes.hpp:6693
LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M8
@ PseudoVADC_VXM_M8
Definition riscv/opcodes.hpp:594
LIEF::assembly::riscv::OPCODE::VFCVT_XU_F_V
@ VFCVT_XU_F_V
Definition riscv/opcodes.hpp:13211
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_MF8
@ PseudoVAESDF_VS_M4_MF8
Definition riscv/opcodes.hpp:654
LIEF::assembly::riscv::OPCODE::VAESKF1_VI
@ VAESKF1_VI
Definition riscv/opcodes.hpp:13149
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF2
@ PseudoVSADD_VV_MF2
Definition riscv/opcodes.hpp:8668
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M4
@ PseudoVSUXEI16_V_M4_M4
Definition riscv/opcodes.hpp:10521
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M4_E32
@ PseudoVFRSUB_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3107
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF4_MASK
@ PseudoVSUXSEG2EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:10686
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2_MASK
@ PseudoVWADD_WV_MF2_MASK
Definition riscv/opcodes.hpp:11432
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF4
@ PseudoVSUXSEG2EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:10791
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E8_MASK
@ PseudoVREDAND_VS_M2_E8_MASK
Definition riscv/opcodes.hpp:7715
LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M8_MASK
@ PseudoVLSE64_V_M8_MASK
Definition riscv/opcodes.hpp:5039
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF4
@ PseudoVSUXSEG7EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:11191
LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B2
@ PseudoVLM_V_B2
Definition riscv/opcodes.hpp:4173
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E8_MASK
@ PseudoVREMU_VX_M1_E8_MASK
Definition riscv/opcodes.hpp:8135
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32_TIED
@ PseudoVFWADD_WV_M2_E32_TIED
Definition riscv/opcodes.hpp:3520
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M8_E16_MASK
@ PseudoVFMADD_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2004
LIEF::assembly::riscv::OPCODE::PREALLOCATED_SETUP
@ PREALLOCATED_SETUP
Definition riscv/opcodes.hpp:53
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M4
@ PseudoVADD_VX_M4
Definition riscv/opcodes.hpp:630
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M2
@ PseudoVASUBU_VX_M2
Definition riscv/opcodes.hpp:876
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_M1_MASK
@ PseudoVSOXSEG7EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9738
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M2
@ PseudoVMAXU_VX_M2
Definition riscv/opcodes.hpp:6530
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M2_MASK
@ PseudoVLOXSEG4EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4611
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF2_MASK
@ PseudoVADD_VX_MF2_MASK
Definition riscv/opcodes.hpp:635
LIEF::assembly::riscv::OPCODE::VLUXEI32_V
@ VLUXEI32_V
Definition riscv/opcodes.hpp:13453
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E16
@ PseudoVFWSUB_VV_M1_E16
Definition riscv/opcodes.hpp:3973
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_M8
@ PseudoVC_V_IVV_SE_M8
Definition riscv/opcodes.hpp:1258
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E32
@ PseudoVFWCVT_F_XU_V_M2_E32
Definition riscv/opcodes.hpp:3585
LIEF::assembly::riscv::OPCODE::CV_CMPEQ_H
@ CV_CMPEQ_H
Definition riscv/opcodes.hpp:12212
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E32_MASK
@ PseudoVFWADD_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3480
LIEF::assembly::riscv::OPCODE::CV_CMPGE_H
@ CV_CMPGE_H
Definition riscv/opcodes.hpp:12224
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M1
@ PseudoVLOXSEG3EI16_V_MF2_M1
Definition riscv/opcodes.hpp:4482
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M1_MASK
@ PseudoTHVdotVMAQAU_VX_M1_MASK
Definition riscv/opcodes.hpp:491
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M4
@ PseudoVMSEQ_VV_M4
Definition riscv/opcodes.hpp:6970
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF8
@ PseudoVMUL_VV_MF8
Definition riscv/opcodes.hpp:7373
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M2
@ PseudoVLOXEI32_V_M8_M2
Definition riscv/opcodes.hpp:4244
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF4
@ PseudoVLOXSEG6EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:4806
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M1_E16
@ PseudoVFWMACC_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3731
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M4
@ PseudoVFMV_V_FPR16_M4
Definition riscv/opcodes.hpp:2404
LIEF::assembly::riscv::OPCODE::CV_MINU_SC_H
@ CV_MINU_SC_H
Definition riscv/opcodes.hpp:12363
LIEF::assembly::riscv::OPCODE::VLUXSEG8EI16_V
@ VLUXSEG8EI16_V
Definition riscv/opcodes.hpp:13480
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E16_MASK
@ PseudoVDIV_VX_M1_E16_MASK
Definition riscv/opcodes.hpp:1556
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M4
@ PseudoVMSLE_VX_M4
Definition riscv/opcodes.hpp:7153
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M1
@ PseudoVSOXEI32_V_M4_M1
Definition riscv/opcodes.hpp:9057
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF4
@ PseudoVLSEG4E16FF_V_MF4
Definition riscv/opcodes.hpp:5188
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_MF2
@ PseudoVRELOAD3_MF2
Definition riscv/opcodes.hpp:8060
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF4
@ PseudoVSSEG7E8_V_MF4
Definition riscv/opcodes.hpp:10139
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF2
@ PseudoVLUXSEG5EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:6150
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF8_MASK
@ PseudoVRSUB_VI_MF8_MASK
Definition riscv/opcodes.hpp:8589
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF8
@ PseudoVSOXSEG5EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:9589
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M2_E32_MASK
@ PseudoVFRSUB_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3106
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M1
@ PseudoVSUXSEG3EI16_V_M1_M1
Definition riscv/opcodes.hpp:10795
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_SE_M8
@ PseudoVC_V_FPR32VV_SE_M8
Definition riscv/opcodes.hpp:1210
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M1
@ PseudoVSSSEG3E16_V_M1
Definition riscv/opcodes.hpp:10283
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF4
@ PseudoVCLMULH_VV_MF4
Definition riscv/opcodes.hpp:954
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF4_MASK
@ PseudoVLOXSEG3EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4523
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M2_E64_MASK
@ PseudoVFDIV_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:1888
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M2_MASK
@ PseudoVLOXEI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4195
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M4
@ PseudoVMFGT_VFPR64_M4
Definition riscv/opcodes.hpp:6696
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M1
@ PseudoVRSUB_VX_M1
Definition riscv/opcodes.hpp:8590
LIEF::assembly::riscv::OPCODE::CV_OR_B
@ CV_OR_B
Definition riscv/opcodes.hpp:12379
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_M1_MASK
@ PseudoVLOXSEG7EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4851
LIEF::assembly::riscv::OPCODE::VLSEG8E64FF_V
@ VLSEG8E64FF_V
Definition riscv/opcodes.hpp:13420
LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_M2
@ PseudoVC_IV_SE_M2
Definition riscv/opcodes.hpp:1133
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M4
@ PseudoVMSBC_VVM_M4
Definition riscv/opcodes.hpp:6912
LIEF::assembly::riscv::OPCODE::VSMUL_VV
@ VSMUL_VV
Definition riscv/opcodes.hpp:13657
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_MF2_MASK
@ PseudoVLOXSEG5EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4693
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M8_E64_MASK
@ PseudoVFMACC_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:1966
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M1_MASK
@ PseudoVLUXSEG3EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:5927
LIEF::assembly::riscv::OPCODE::SUB
@ SUB
Definition riscv/opcodes.hpp:13015
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M2
@ PseudoVLUXSEG2EI8_V_MF2_M2
Definition riscv/opcodes.hpp:5840
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M2_MASK
@ PseudoVMFEQ_VFPR32_M2_MASK
Definition riscv/opcodes.hpp:6613
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M2_MASK
@ PseudoVLSEG3E64FF_V_M2_MASK
Definition riscv/opcodes.hpp:5157
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M2_MASK
@ PseudoVLOXEI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4293
LIEF::assembly::riscv::OPCODE::G_SPLAT_VECTOR
@ G_SPLAT_VECTOR
Definition riscv/opcodes.hpp:253
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E16
@ PseudoVFSGNJN_VV_MF2_E16
Definition riscv/opcodes.hpp:3175
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF4_MASK
@ PseudoVMFLT_VFPR16_MF4_MASK
Definition riscv/opcodes.hpp:6753
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF4
@ PseudoVSOXSEG8EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:9761
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF2_MASK
@ PseudoVLOXSEG3EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4521
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF4
@ PseudoVSOXSEG4EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:9453
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M1_MASK
@ PseudoVLUXSEG2EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:5813
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF4
@ PseudoVSOXSEG2EI32_V_M1_MF4
Definition riscv/opcodes.hpp:9197
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M8
@ PseudoVAND_VV_M8
Definition riscv/opcodes.hpp:838
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_M1
@ PseudoVLSSEG8E32_V_M1
Definition riscv/opcodes.hpp:5556
LIEF::assembly::riscv::OPCODE::QK_C_LHU
@ QK_C_LHU
Definition riscv/opcodes.hpp:12918
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF2
@ PseudoVLUXSEG2EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:5750
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M4_MASK
@ PseudoTHVdotVMAQASU_VX_M4_MASK
Definition riscv/opcodes.hpp:465
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M4_E64
@ PseudoVFMAX_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2083
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M4_MASK
@ PseudoVLOXSEG2EI32_V_M4_M4_MASK
Definition riscv/opcodes.hpp:4391
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF4_MASK
@ PseudoVLUXEI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:5723
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M4_MASK
@ PseudoVLUXSEG2EI32_V_M8_M4_MASK
Definition riscv/opcodes.hpp:5787
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32_MASK
@ PseudoVFWSUB_WV_MF2_E32_MASK
Definition riscv/opcodes.hpp:4038
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF8
@ PseudoVSLIDEDOWN_VI_MF8
Definition riscv/opcodes.hpp:8834
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M1
@ PseudoVSSE16_V_M1
Definition riscv/opcodes.hpp:9947
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M8_MASK
@ PseudoVMFLT_VFPR32_M8_MASK
Definition riscv/opcodes.hpp:6761
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E64
@ PseudoVFMSAC_VV_M1_E64
Definition riscv/opcodes.hpp:2226
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E64_MASK
@ PseudoVREM_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:8177
LIEF::assembly::riscv::OPCODE::TH_SDD
@ TH_SDD
Definition riscv/opcodes.hpp:13104
LIEF::assembly::riscv::OPCODE::VFSUB_VV
@ VFSUB_VV
Definition riscv/opcodes.hpp:13271
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E64
@ PseudoVFREDMAX_VS_M4_E64
Definition riscv/opcodes.hpp:2951
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M1
@ PseudoVWMULSU_VX_M1
Definition riscv/opcodes.hpp:11551
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M1_MASK
@ PseudoVMULHSU_VX_M1_MASK
Definition riscv/opcodes.hpp:7292
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M4_E16_MASK
@ PseudoVFSGNJN_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3126
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M2_MASK
@ PseudoVMSNE_VX_M2_MASK
Definition riscv/opcodes.hpp:7252
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M4_E16
@ PseudoVFMUL_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2316
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M1_MASK
@ PseudoVMSNE_VV_M1_MASK
Definition riscv/opcodes.hpp:7236
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF4_MASK
@ PseudoVLSEG7E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5329
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF4_MASK
@ PseudoVSSEG8E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10160
LIEF::assembly::riscv::OPCODE::FNMSUB_H_INX
@ FNMSUB_H_INX
Definition riscv/opcodes.hpp:12747
LIEF::assembly::riscv::OPCODE::VFMV_S_F
@ VFMV_S_F
Definition riscv/opcodes.hpp:13232
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M2
@ PseudoVSSSEG2E64_V_M2
Definition riscv/opcodes.hpp:10267
LIEF::assembly::riscv::OPCODE::PseudoVID_V_M8_MASK
@ PseudoVID_V_M8_MASK
Definition riscv/opcodes.hpp:4062
LIEF::assembly::riscv::OPCODE::INLINEASM_BR
@ INLINEASM_BR
Definition riscv/opcodes.hpp:26
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF4_MASK
@ PseudoVMADD_VV_MF4_MASK
Definition riscv/opcodes.hpp:6483
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_MF8
@ PseudoVAESDM_VS_M8_MF8
Definition riscv/opcodes.hpp:689
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M8
@ PseudoVSSUBU_VV_M8
Definition riscv/opcodes.hpp:10425
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF8
@ PseudoVRGATHEREI16_VV_MF4_E16_MF8
Definition riscv/opcodes.hpp:8422
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF4
@ PseudoVLUXSEG4EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:5996
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF2
@ PseudoVOR_VI_MF2
Definition riscv/opcodes.hpp:7634
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E16
@ PseudoVFWREDUSUM_VS_MF2_E16
Definition riscv/opcodes.hpp:3949
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_M1
@ PseudoVSSSEG5E32_V_M1
Definition riscv/opcodes.hpp:10345
LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M2
@ PseudoVLE64FF_V_M2
Definition riscv/opcodes.hpp:4129
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF2_MASK
@ PseudoVRGATHER_VI_MF2_MASK
Definition riscv/opcodes.hpp:8443
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_MF2_E32_MASK
@ PseudoVFADD_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:1620
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF8_MASK
@ PseudoVLOXSEG5EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:4737
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_MF2_MF4
@ PseudoVAESZ_VS_MF2_MF4
Definition riscv/opcodes.hpp:788
LIEF::assembly::riscv::OPCODE::SD_AQ_RL
@ SD_AQ_RL
Definition riscv/opcodes.hpp:12948
LIEF::assembly::riscv::OPCODE::VWSUBU_VX
@ VWSUBU_VX
Definition riscv/opcodes.hpp:13831
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF4
@ PseudoVMSLT_VV_MF4
Definition riscv/opcodes.hpp:7203
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF2_MASK
@ PseudoVLUXSEG3EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:5913
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M1_MASK
@ PseudoVMFLT_VFPR32_M1_MASK
Definition riscv/opcodes.hpp:6755
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M2
@ PseudoVLSSEG3E64_V_M2
Definition riscv/opcodes.hpp:5450
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF2_MASK
@ PseudoVLOXSEG6EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4785
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_MF2_MASK
@ PseudoVSUXEI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10642
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UMIN
@ G_ATOMICRMW_UMIN
Definition riscv/opcodes.hpp:133
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_M1_MASK
@ PseudoVSOXSEG4EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9422
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M2_E16_MASK
@ PseudoVFMSAC_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2195
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF4
@ PseudoVSUXSEG5EI32_V_M1_MF4
Definition riscv/opcodes.hpp:11039
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF8_MASK
@ PseudoVROL_VV_MF8_MASK
Definition riscv/opcodes.hpp:8519
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF2_MASK
@ PseudoVAADDU_VV_MF2_MASK
Definition riscv/opcodes.hpp:530
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_M1
@ PseudoVLSEG5E8FF_V_M1
Definition riscv/opcodes.hpp:5262
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M1
@ PseudoVMSEQ_VI_M1
Definition riscv/opcodes.hpp:6952
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF4
@ PseudoVSOXSEG7EI64_V_M2_MF4
Definition riscv/opcodes.hpp:9723
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF2_MASK
@ PseudoVSSSEG2E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10254
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF4_MASK
@ PseudoVLOXSEG2EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4401
LIEF::assembly::riscv::OPCODE::INSERT_SUBREG
@ INSERT_SUBREG
Definition riscv/opcodes.hpp:33
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M2
@ PseudoVAADDU_VX_M2
Definition riscv/opcodes.hpp:537
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF2_MASK
@ PseudoVSOXSEG2EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9180
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF2_E16
@ PseudoVFNMADD_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2683
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M1
@ PseudoVSE16_V_M1
Definition riscv/opcodes.hpp:8702
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF8_MASK
@ PseudoVWADDU_WX_MF8_MASK
Definition riscv/opcodes.hpp:11394
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M1_MASK
@ PseudoVLOXSEG4EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4587
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M4
@ PseudoVSOXEI8_V_MF2_M4
Definition riscv/opcodes.hpp:9135
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF4_E16
@ PseudoVFNMSAC_VV_MF4_E16
Definition riscv/opcodes.hpp:2793
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M1
@ PseudoVLOXSEG2EI16_V_M2_M1
Definition riscv/opcodes.hpp:4342
LIEF::assembly::riscv::OPCODE::VWADD_VV
@ VWADD_VV
Definition riscv/opcodes.hpp:13808
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E32_MASK
@ PseudoVFADD_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:1638
LIEF::assembly::riscv::OPCODE::AMOOR_W
@ AMOOR_W
Definition riscv/opcodes.hpp:12079
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF2_MASK
@ PseudoVSSSEG2E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10278
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF4
@ PseudoVXOR_VX_MF4
Definition riscv/opcodes.hpp:11877
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M2_MASK
@ PseudoVSSSEG2E64_V_M2_MASK
Definition riscv/opcodes.hpp:10268
LIEF::assembly::riscv::OPCODE::TH_MVEQZ
@ TH_MVEQZ
Definition riscv/opcodes.hpp:13098
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_MF2
@ PseudoVSOXSEG6EI64_V_M4_MF2
Definition riscv/opcodes.hpp:9647
LIEF::assembly::riscv::OPCODE::FCVT_WU_D
@ FCVT_WU_D
Definition riscv/opcodes.hpp:12629
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E64
@ PseudoVFREDUSUM_VS_M8_E64
Definition riscv/opcodes.hpp:3047
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32_TIED
@ PseudoVFWSUB_WV_M2_E32_TIED
Definition riscv/opcodes.hpp:4024
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M2
@ PseudoVMFLE_VFPR64_M2
Definition riscv/opcodes.hpp:6724
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M2_MASK
@ PseudoVSUXSEG4EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10908
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF8_MASK
@ PseudoVSOXSEG8EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:9798
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_MF4
@ PseudoVC_V_FPR16V_MF4
Definition riscv/opcodes.hpp:1195
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M1_E16_MASK
@ PseudoVFSGNJX_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3182
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E16
@ PseudoVFCVT_RM_F_X_V_M4_E16
Definition riscv/opcodes.hpp:1773
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M2_E16_MASK
@ PseudoVFNMACC_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2618
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_MF2_MASK
@ PseudoVLUXSEG8EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:6379
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF2
@ PseudoVFNCVT_RTZ_XU_F_W_MF2
Definition riscv/opcodes.hpp:2573
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF4_MASK
@ PseudoVSLIDE1UP_VX_MF4_MASK
Definition riscv/opcodes.hpp:8819
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M2_M1_MASK
@ PseudoVSOXSEG7EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9676
LIEF::assembly::riscv::OPCODE::VFADD_VV
@ VFADD_VV
Definition riscv/opcodes.hpp:13205
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF2_MASK
@ PseudoVROR_VX_MF2_MASK
Definition riscv/opcodes.hpp:8571
LIEF::assembly::riscv::OPCODE::VZEXT_VF2
@ VZEXT_VF2
Definition riscv/opcodes.hpp:13841
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E16
@ PseudoVREDMINU_VS_MF2_E16
Definition riscv/opcodes.hpp:7864
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M8
@ PseudoVXOR_VX_M8
Definition riscv/opcodes.hpp:11873
LIEF::assembly::riscv::OPCODE::G_FCLASS
@ G_FCLASS
Definition riscv/opcodes.hpp:322
LIEF::assembly::riscv::OPCODE::SF_CFLUSH_D_L1
@ SF_CFLUSH_D_L1
Definition riscv/opcodes.hpp:12957
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF4_MASK
@ PseudoVLOXSEG8EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4947
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M1_MASK
@ PseudoVLSSEG2E16_V_M1_MASK
Definition riscv/opcodes.hpp:5399
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M2
@ PseudoVSOXEI8_V_M1_M2
Definition riscv/opcodes.hpp:9113
LIEF::assembly::riscv::OPCODE::CV_SDOTSP_B
@ CV_SDOTSP_B
Definition riscv/opcodes.hpp:12393
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E16_MASK
@ PseudoVREDMAX_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:7805
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M2
@ PseudoVADD_VV_M2
Definition riscv/opcodes.hpp:614
LIEF::assembly::riscv::OPCODE::CM_POP
@ CM_POP
Definition riscv/opcodes.hpp:12147
LIEF::assembly::riscv::OPCODE::MOPR4
@ MOPR4
Definition riscv/opcodes.hpp:12886
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E16
@ PseudoVFDIV_VV_M2_E16
Definition riscv/opcodes.hpp:1899
LIEF::assembly::riscv::OPCODE::VSSEG7E8_V
@ VSSEG7E8_V
Definition riscv/opcodes.hpp:13725
LIEF::assembly::riscv::OPCODE::VSUXEI16_V
@ VSUXEI16_V
Definition riscv/opcodes.hpp:13770
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M1
@ PseudoVLUXEI32_V_M1_M1
Definition riscv/opcodes.hpp:5612
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF8_E8_MASK
@ PseudoVREDMIN_VS_MF8_E8_MASK
Definition riscv/opcodes.hpp:7919
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M2
@ PseudoVMSLT_VV_M2
Definition riscv/opcodes.hpp:7195
LIEF::assembly::riscv::OPCODE::CV_MAX
@ CV_MAX
Definition riscv/opcodes.hpp:12342
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_MF2_MASK
@ PseudoVSUXSEG8EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11258
LIEF::assembly::riscv::OPCODE::AMOMIN_W
@ AMOMIN_W
Definition riscv/opcodes.hpp:12063
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF4
@ PseudoVSOXSEG6EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:9667
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF2
@ PseudoVSLL_VV_MF2
Definition riscv/opcodes.hpp:8900
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF2_MASK
@ PseudoVMFEQ_VV_MF2_MASK
Definition riscv/opcodes.hpp:6637
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF4_MASK
@ PseudoVFNCVT_RTZ_X_F_W_MF4_MASK
Definition riscv/opcodes.hpp:2588
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF2_MASK
@ PseudoVLUXEI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:5663
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_MF2
@ PseudoVSM4R_VS_M1_MF2
Definition riscv/opcodes.hpp:8936
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32
@ PseudoVFWSUB_WV_M4_E32
Definition riscv/opcodes.hpp:4029
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF4_E16
@ PseudoVFADD_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:1609
LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M1_MASK
@ PseudoVSSE32_V_M1_MASK
Definition riscv/opcodes.hpp:9960
LIEF::assembly::riscv::OPCODE::MAX
@ MAX
Definition riscv/opcodes.hpp:12856
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M8_E16
@ PseudoVFMIN_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2138
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M4_M2_MASK
@ PseudoVLUXSEG4EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:5983
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_M8
@ PseudoVC_V_FPR32VV_M8
Definition riscv/opcodes.hpp:1205
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E64
@ PseudoVFNMSAC_VV_M1_E64
Definition riscv/opcodes.hpp:2769
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF2
@ PseudoVLOXSEG8EI32_V_M1_MF2
Definition riscv/opcodes.hpp:4952
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF2
@ PseudoVSSSEG6E16_V_MF2
Definition riscv/opcodes.hpp:10361
LIEF::assembly::riscv::OPCODE::G_LROUND
@ G_LROUND
Definition riscv/opcodes.hpp:243
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF2
@ PseudoVRGATHEREI16_VV_M1_E8_MF2
Definition riscv/opcodes.hpp:8302
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_MF4
@ PseudoVMERGE_VVM_MF4
Definition riscv/opcodes.hpp:6589
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2_MASK_TIED
@ PseudoVWADD_WV_M2_MASK_TIED
Definition riscv/opcodes.hpp:11425
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M1
@ PseudoVSOXSEG2EI64_V_M4_M1
Definition riscv/opcodes.hpp:9241
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M1_MASK
@ PseudoVWMUL_VX_M1_MASK
Definition riscv/opcodes.hpp:11600
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M2
@ PseudoVSRA_VV_M2
Definition riscv/opcodes.hpp:9879
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF2
@ PseudoVSUXSEG3EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:10817
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E32_MASK
@ PseudoVFREDUSUM_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:3052
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M4
@ PseudoVWADDU_VV_M4
Definition riscv/opcodes.hpp:11339
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF2_E16_MASK
@ PseudoVFMACC_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:1946
LIEF::assembly::riscv::OPCODE::VNMSAC_VV
@ VNMSAC_VV
Definition riscv/opcodes.hpp:13573
LIEF::assembly::riscv::OPCODE::PseudoVQMACC_2x8x2_M1
@ PseudoVQMACC_2x8x2_M1
Definition riscv/opcodes.hpp:7692
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_M4
@ PseudoVAESDM_VS_M4_M4
Definition riscv/opcodes.hpp:680
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_MF2_MASK
@ PseudoVSOXSEG3EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9332
LIEF::assembly::riscv::OPCODE::AMOMIN_B_RL
@ AMOMIN_B_RL
Definition riscv/opcodes.hpp:12054
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M1
@ PseudoVSUXSEG2EI16_V_M2_M1
Definition riscv/opcodes.hpp:10667
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E32_MASK
@ PseudoVFMAX_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:2108
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E64_MASK
@ PseudoVFCVT_F_XU_V_M4_E64_MASK
Definition riscv/opcodes.hpp:1688
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M4_E16
@ PseudoVFWNMSAC_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3879
LIEF::assembly::riscv::OPCODE::VC_V_X
@ VC_V_X
Definition riscv/opcodes.hpp:13192
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF2_MASK
@ PseudoVXOR_VX_MF2_MASK
Definition riscv/opcodes.hpp:11876
LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_M8
@ PseudoVC_XV_SE_M8
Definition riscv/opcodes.hpp:1412
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK
@ PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK
Definition riscv/opcodes.hpp:2566
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF4_MASK
@ PseudoVSUXSEG7EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:11212
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF4_MASK
@ PseudoVSOXSEG5EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9582
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF4_MASK
@ PseudoVSUXSEG2EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:10786
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E16
@ PseudoVFNCVT_ROD_F_F_W_M2_E16
Definition riscv/opcodes.hpp:2553
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M2_MASK
@ PseudoVLOXSEG2EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4337
LIEF::assembly::riscv::OPCODE::VQMACC_2x8x2
@ VQMACC_2x8x2
Definition riscv/opcodes.hpp:13592
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_M1
@ PseudoVLUXSEG2EI8_V_MF8_M1
Definition riscv/opcodes.hpp:5854
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E16_MASK
@ PseudoVREMU_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:8093
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M2
@ PseudoVMFLE_VV_M2
Definition riscv/opcodes.hpp:6732
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E64_MASK
@ PseudoVREDOR_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:7933
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_MF2_MASK
@ PseudoVSUXEI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10510
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2
@ PseudoVWADDU_WV_MF2
Definition riscv/opcodes.hpp:11371
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2_MASK_TIED
@ PseudoVWSUBU_WV_MF2_MASK_TIED
Definition riscv/opcodes.hpp:11757
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF2_E16_MASK
@ PseudoVFWADD_WFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3494
LIEF::assembly::riscv::OPCODE::VLSSEG8E64_V
@ VLSSEG8E64_V
Definition riscv/opcodes.hpp:13450
LIEF::assembly::riscv::OPCODE::PseudoCCSLLW
@ PseudoCCSLLW
Definition riscv/opcodes.hpp:355
LIEF::assembly::riscv::OPCODE::DBG_VALUE
@ DBG_VALUE
Definition riscv/opcodes.hpp:37
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M4
@ PseudoVRSUB_VX_M4
Definition riscv/opcodes.hpp:8594
LIEF::assembly::riscv::OPCODE::PseudoBRIND
@ PseudoBRIND
Definition riscv/opcodes.hpp:333
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF8
@ PseudoVRGATHEREI16_VV_MF2_E32_MF8
Definition riscv/opcodes.hpp:8408
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M1
@ PseudoVLOXSEG2EI64_V_M4_M1
Definition riscv/opcodes.hpp:4420
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E64_MASK
@ PseudoVFDIV_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:1904
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_M1
@ PseudoVLSEG6E32FF_V_M1
Definition riscv/opcodes.hpp:5290
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E64_MASK
@ PseudoVREDXOR_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:8021
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF8_MASK
@ PseudoVLOXSEG2EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:4469
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M4_M1
@ PseudoVLOXSEG6EI32_V_M4_M1
Definition riscv/opcodes.hpp:4800
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E16
@ PseudoVFSGNJX_VV_M1_E16
Definition riscv/opcodes.hpp:3211
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M2_MASK
@ PseudoVMSLE_VV_M2_MASK
Definition riscv/opcodes.hpp:7138
LIEF::assembly::riscv::OPCODE::PseudoLI
@ PseudoLI
Definition riscv/opcodes.hpp:396
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M1
@ PseudoVSSEG4E16_V_M1
Definition riscv/opcodes.hpp:10055
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M1
@ PseudoVFNCVT_RM_X_F_W_M1
Definition riscv/opcodes.hpp:2537
LIEF::assembly::riscv::OPCODE::SplitF64Pseudo
@ SplitF64Pseudo
Definition riscv/opcodes.hpp:11925
LIEF::assembly::riscv::OPCODE::PseudoFSD
@ PseudoFSD
Definition riscv/opcodes.hpp:381
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_MF2
@ PseudoVRGATHEREI16_VV_M2_E8_MF2
Definition riscv/opcodes.hpp:8336
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF4
@ PseudoVLOXSEG5EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:4766
LIEF::assembly::riscv::OPCODE::G_FMAD
@ G_FMAD
Definition riscv/opcodes.hpp:200
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_M1
@ PseudoVSOXEI8_V_MF8_M1
Definition riscv/opcodes.hpp:9147
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M4_M1_MASK
@ PseudoVLOXSEG8EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4961
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF2_E16_MASK
@ PseudoVFWADD_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3458
LIEF::assembly::riscv::OPCODE::AMOMAXU_W_AQ_RL
@ AMOMAXU_W_AQ_RL
Definition riscv/opcodes.hpp:12017
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF4_MASK
@ PseudoVNSRA_WX_MF4_MASK
Definition riscv/opcodes.hpp:7587
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M8_E16_MASK
@ PseudoVFSGNJX_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:3188
LIEF::assembly::riscv::OPCODE::VSSEG7E64_V
@ VSSEG7E64_V
Definition riscv/opcodes.hpp:13724
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M4
@ PseudoVAESEM_VV_M4
Definition riscv/opcodes.hpp:753
LIEF::assembly::riscv::OPCODE::C_SUBW
@ C_SUBW
Definition riscv/opcodes.hpp:12543
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_MF2_MF2
@ PseudoVAESZ_VS_MF2_MF2
Definition riscv/opcodes.hpp:787
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E16_MASK
@ PseudoVDIVU_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:1440
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF8_MASK
@ PseudoVSSSEG7E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10398
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF2_MASK
@ PseudoVLOXEI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4209
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M2_E32_MASK
@ PseudoVFNMADD_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2690
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M1
@ PseudoVSOXSEG2EI16_V_MF2_M1
Definition riscv/opcodes.hpp:9175
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M4
@ PseudoVMSLE_VV_M4
Definition riscv/opcodes.hpp:7139
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF2_MASK
@ PseudoVSUXSEG7EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:11190
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF4
@ PseudoVSOXSEG3EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:9391
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M2
@ PseudoVSSSEG3E32_V_M2
Definition riscv/opcodes.hpp:10293
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M2
@ PseudoTHVdotVMAQAUS_VX_M2
Definition riscv/opcodes.hpp:472
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E32
@ PseudoVFDIV_VV_M1_E32
Definition riscv/opcodes.hpp:1895
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E32
@ PseudoVFWADD_VV_M4_E32
Definition riscv/opcodes.hpp:3479
LIEF::assembly::riscv::OPCODE::PseudoVID_V_M4_MASK
@ PseudoVID_V_M4_MASK
Definition riscv/opcodes.hpp:4060
LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_M2
@ PseudoVC_VVV_SE_M2
Definition riscv/opcodes.hpp:1147
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M2_E16_MASK
@ PseudoVFNCVT_RM_F_X_W_M2_E16_MASK
Definition riscv/opcodes.hpp:2512
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M4_MASK
@ PseudoVAADD_VV_M4_MASK
Definition riscv/opcodes.hpp:554
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF2_MASK
@ PseudoVSLIDE1UP_VX_MF2_MASK
Definition riscv/opcodes.hpp:8817
LIEF::assembly::riscv::OPCODE::VQMACCSU_4x8x4
@ VQMACCSU_4x8x4
Definition riscv/opcodes.hpp:13587
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF4
@ PseudoVRGATHER_VX_MF4
Definition riscv/opcodes.hpp:8502
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M1
@ PseudoVMFNE_VFPR16_M1
Definition riscv/opcodes.hpp:6784
LIEF::assembly::riscv::OPCODE::G_UDIVFIX
@ G_UDIVFIX
Definition riscv/opcodes.hpp:193
LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_MF8
@ PseudoVADC_VVM_MF8
Definition riscv/opcodes.hpp:590
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF2
@ PseudoVSOXSEG2EI32_V_M1_MF2
Definition riscv/opcodes.hpp:9195
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF8
@ PseudoVLUXSEG7EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:6260
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B4_MASK
@ PseudoVCPOP_M_B4_MASK
Definition riscv/opcodes.hpp:1045
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M8
@ PseudoVMFLE_VFPR16_M8
Definition riscv/opcodes.hpp:6706
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF2
@ PseudoVMFLE_VFPR16_MF2
Definition riscv/opcodes.hpp:6708
LIEF::assembly::riscv::OPCODE::VMSLT_VV
@ VMSLT_VV
Definition riscv/opcodes.hpp:13542
LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M4_MASK
@ PseudoVLE32_V_M4_MASK
Definition riscv/opcodes.hpp:4122
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M8_MASK
@ PseudoVLE16FF_V_M8_MASK
Definition riscv/opcodes.hpp:4090
LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SC_B
@ CV_CMPLEU_SC_B
Definition riscv/opcodes.hpp:12245
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E32_MASK
@ PseudoVFWMUL_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3832
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_M4
@ PseudoVC_V_VVW_SE_M4
Definition riscv/opcodes.hpp:1324
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M4
@ PseudoVIOTA_M_M4
Definition riscv/opcodes.hpp:4073
LIEF::assembly::riscv::OPCODE::TH_DCACHE_CSW
@ TH_DCACHE_CSW
Definition riscv/opcodes.hpp:13035
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M1_E32
@ PseudoVFNCVT_RM_F_X_W_M1_E32
Definition riscv/opcodes.hpp:2509
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M8
@ PseudoVLOXEI8_V_M2_M8
Definition riscv/opcodes.hpp:4302
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF4
@ PseudoVSSSEG4E8_V_MF4
Definition riscv/opcodes.hpp:10335
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M2
@ PseudoVMAX_VX_M2
Definition riscv/opcodes.hpp:6558
LIEF::assembly::riscv::OPCODE::SC_W_RL
@ SC_W_RL
Definition riscv/opcodes.hpp:12946
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M4_E32_MASK
@ PseudoVFWNMACC_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3854
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M8_MASK
@ PseudoVSADDU_VI_M8_MASK
Definition riscv/opcodes.hpp:8611
LIEF::assembly::riscv::OPCODE::VLOXSEG5EI64_V
@ VLOXSEG5EI64_V
Definition riscv/opcodes.hpp:13350
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF2
@ PseudoVSSEG4E16_V_MF2
Definition riscv/opcodes.hpp:10059
LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_MF2
@ PseudoVLE32_V_MF2
Definition riscv/opcodes.hpp:4125
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M8_M8
@ PseudoVSOXEI8_V_M8_M8
Definition riscv/opcodes.hpp:9129
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E32_MASK
@ PseudoVFCVT_F_X_V_M8_E32_MASK
Definition riscv/opcodes.hpp:1722
LIEF::assembly::riscv::OPCODE::CV_CNT
@ CV_CNT
Definition riscv/opcodes.hpp:12271
LIEF::assembly::riscv::OPCODE::G_OR
@ G_OR
Definition riscv/opcodes.hpp:85
LIEF::assembly::riscv::OPCODE::VLM_V
@ VLM_V
Definition riscv/opcodes.hpp:13331
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF4
@ PseudoVMAX_VV_MF4
Definition riscv/opcodes.hpp:6552
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M1_MASK
@ PseudoVSSSEG4E32_V_M1_MASK
Definition riscv/opcodes.hpp:10320
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E32_MASK
@ PseudoVFSUB_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:3442
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M1
@ PseudoVSOXSEG3EI8_V_M1_M1
Definition riscv/opcodes.hpp:9373
LIEF::assembly::riscv::OPCODE::CV_DOTUP_H
@ CV_DOTUP_H
Definition riscv/opcodes.hpp:12288
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E64_V_M1_MASK
@ PseudoVLSSEG6E64_V_M1_MASK
Definition riscv/opcodes.hpp:5521
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M2_MASK
@ PseudoVLUXSEG4EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:6047
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M1
@ PseudoVLOXEI16_V_M1_M1
Definition riscv/opcodes.hpp:4178
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M1
@ PseudoVMSEQ_VX_M1
Definition riscv/opcodes.hpp:6980
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M1
@ PseudoVFMERGE_VFPR32M_M1
Definition riscv/opcodes.hpp:2123
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_MF2
@ PseudoVLUXSEG7EI16_V_M1_MF2
Definition riscv/opcodes.hpp:6244
LIEF::assembly::riscv::OPCODE::VFWADD_VF
@ VFWADD_VF
Definition riscv/opcodes.hpp:13272
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E64
@ PseudoVFCVT_F_XU_V_M8_E64
Definition riscv/opcodes.hpp:1693
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E16
@ PseudoVFREDMIN_VS_M4_E16
Definition riscv/opcodes.hpp:2977
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M8
@ PseudoVLSE8_V_M8
Definition riscv/opcodes.hpp:5046
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF4
@ PseudoVWMACCU_VX_MF4
Definition riscv/opcodes.hpp:11511
LIEF::assembly::riscv::OPCODE::DIV
@ DIV
Definition riscv/opcodes.hpp:12551
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF4_MASK
@ PseudoVLUXSEG5EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:6093
LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_M4
@ PseudoVC_XVV_SE_M4
Definition riscv/opcodes.hpp:1398
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E8
@ PseudoVDIV_VX_M1_E8
Definition riscv/opcodes.hpp:1561
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF2
@ PseudoVRSUB_VX_MF2
Definition riscv/opcodes.hpp:8598
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M8_E32
@ PseudoVFMACC_VFPR32_M8_E32
Definition riscv/opcodes.hpp:1955
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M2
@ PseudoVSOXSEG2EI8_V_M2_M2
Definition riscv/opcodes.hpp:9261
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M4
@ PseudoVMERGE_VVM_M4
Definition riscv/opcodes.hpp:6586
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M1_MASK
@ PseudoVSADDU_VI_M1_MASK
Definition riscv/opcodes.hpp:8605
LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VX_M
@ PseudoVMSGEU_VX_M
Definition riscv/opcodes.hpp:7003
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_M1
@ PseudoVSOXSEG5EI64_V_M2_M1
Definition riscv/opcodes.hpp:9559
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M1
@ PseudoVAND_VV_M1
Definition riscv/opcodes.hpp:832
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF4_MASK
@ PseudoVSUXSEG2EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:10734
LIEF::assembly::riscv::OPCODE::VSOXSEG8EI64_V
@ VSOXSEG8EI64_V
Definition riscv/opcodes.hpp:13690
LIEF::assembly::riscv::OPCODE::PseudoLAImm
@ PseudoLAImm
Definition riscv/opcodes.hpp:386
LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M8_MASK
@ PseudoVSSE64_V_M8_MASK
Definition riscv/opcodes.hpp:9976
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF4
@ PseudoVWSUBU_VV_MF4
Definition riscv/opcodes.hpp:11727
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_M1
@ PseudoVLUXSEG5EI64_V_M2_M1
Definition riscv/opcodes.hpp:6130
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF2
@ PseudoVMACC_VX_MF2
Definition riscv/opcodes.hpp:6424
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF8_MASK
@ PseudoVNMSAC_VX_MF8_MASK
Definition riscv/opcodes.hpp:7525
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M4_MASK
@ PseudoVSUXEI8_V_MF2_M4_MASK
Definition riscv/opcodes.hpp:10640
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_M1_MASK
@ PseudoVSOXSEG7EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9698
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E16
@ PseudoVFNMSAC_VV_M1_E16
Definition riscv/opcodes.hpp:2765
LIEF::assembly::riscv::OPCODE::CV_EXTRACT_H
@ CV_EXTRACT_H
Definition riscv/opcodes.hpp:12311
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF8
@ PseudoVLOXSEG4EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:4634
LIEF::assembly::riscv::OPCODE::G_SBFX
@ G_SBFX
Definition riscv/opcodes.hpp:317
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M2
@ PseudoVSSRA_VI_M2
Definition riscv/opcodes.hpp:10165
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E64_MASK
@ PseudoVFSQRT_V_M4_E64_MASK
Definition riscv/opcodes.hpp:3378
LIEF::assembly::riscv::OPCODE::CV_BNEIMM
@ CV_BNEIMM
Definition riscv/opcodes.hpp:12203
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF4
@ PseudoVLUXSEG2EI64_V_M2_MF4
Definition riscv/opcodes.hpp:5810
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E16_MASK
@ PseudoVREDMIN_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:7901
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E32_MASK
@ PseudoVFREDOSUM_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:3022
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64FF_V_M1
@ PseudoVLSEG7E64FF_V_M1
Definition riscv/opcodes.hpp:5338
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M2
@ PseudoVSUXSEG2EI32_V_M4_M2
Definition riscv/opcodes.hpp:10713
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF2_MASK
@ PseudoVNSRL_WV_MF2_MASK
Definition riscv/opcodes.hpp:7609
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M4_MASK
@ PseudoVSOXSEG2EI32_V_M8_M4_MASK
Definition riscv/opcodes.hpp:9216
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4
@ PseudoVWADDU_WV_MF4
Definition riscv/opcodes.hpp:11375
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M2_MASK
@ PseudoVSOXEI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9060
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4
@ PseudoVWADD_WV_M4
Definition riscv/opcodes.hpp:11427
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E64_MASK
@ PseudoVFNMSAC_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:2770
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E16
@ PseudoVFREDOSUM_VS_M4_E16
Definition riscv/opcodes.hpp:3007
LIEF::assembly::riscv::OPCODE::FMIN_S_INX
@ FMIN_S_INX
Definition riscv/opcodes.hpp:12712
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M2_MASK
@ PseudoVSADDU_VV_M2_MASK
Definition riscv/opcodes.hpp:8621
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E64
@ PseudoVFSGNJX_VV_M8_E64
Definition riscv/opcodes.hpp:3233
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M1_E32_MASK
@ PseudoVFMIN_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2145
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF2
@ PseudoVLOXSEG4EI64_V_M1_MF2
Definition riscv/opcodes.hpp:4638
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_MF2
@ PseudoVSOXSEG5EI32_V_M2_MF2
Definition riscv/opcodes.hpp:9539
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF4
@ PseudoVRGATHEREI16_VV_MF8_E8_MF4
Definition riscv/opcodes.hpp:8430
LIEF::assembly::riscv::OPCODE::CV_LB_rr_inc
@ CV_LB_rr_inc
Definition riscv/opcodes.hpp:12323
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M4
@ PseudoVLOXEI8_V_MF2_M4
Definition riscv/opcodes.hpp:4314
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M4_MASK
@ PseudoVFCVT_RM_X_F_V_M4_MASK
Definition riscv/opcodes.hpp:1808
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M8_MASK
@ PseudoVMFLE_VFPR16_M8_MASK
Definition riscv/opcodes.hpp:6707
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF2
@ PseudoVSOXSEG7EI64_V_M1_MF2
Definition riscv/opcodes.hpp:9713
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E64_MASK
@ PseudoVFMUL_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:2353
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M2
@ PseudoVMERGE_VXM_M2
Definition riscv/opcodes.hpp:6592
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF4_MASK
@ PseudoVMAXU_VV_MF4_MASK
Definition riscv/opcodes.hpp:6525
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E32_MASK
@ PseudoVREDMIN_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:7911
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M2
@ PseudoVWMULSU_VV_M2
Definition riscv/opcodes.hpp:11541
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF2
@ PseudoVLUXSEG4EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:5988
LIEF::assembly::riscv::OPCODE::THVdotVMAQAUS_VX
@ THVdotVMAQAUS_VX
Definition riscv/opcodes.hpp:13022
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E64
@ PseudoVFMADD_VV_M4_E64
Definition riscv/opcodes.hpp:2043
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF2
@ PseudoVMIN_VV_MF2
Definition riscv/opcodes.hpp:6862
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF4_MASK
@ PseudoVLUXSEG5EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:6099
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF2
@ PseudoVWMULU_VV_MF2
Definition riscv/opcodes.hpp:11569
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF2
@ PseudoVSUXSEG6EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:11129
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M4
@ PseudoVNCLIPU_WI_M4
Definition riscv/opcodes.hpp:7430
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M1
@ PseudoVSUB_VV_M1
Definition riscv/opcodes.hpp:10475
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF4
@ PseudoVLUXSEG7EI32_V_M1_MF4
Definition riscv/opcodes.hpp:6266
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_MF2_E32
@ PseudoVFMADD_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2017
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_MF8
@ PseudoVC_V_IVW_MF8
Definition riscv/opcodes.hpp:1267
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF4_MASK
@ PseudoVFNCVT_X_F_W_MF4_MASK
Definition riscv/opcodes.hpp:2612
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_MF8
@ PseudoVAESDF_VS_M2_MF8
Definition riscv/opcodes.hpp:648
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF4_MASK
@ PseudoVSOXSEG4EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9462
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E32_MASK
@ PseudoVFREDMAX_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:2938
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_MF2_MF8
@ PseudoVAESDM_VS_MF2_MF8
Definition riscv/opcodes.hpp:692
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_M1
@ PseudoVSUXSEG7EI32_V_M2_M1
Definition riscv/opcodes.hpp:11201
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF4
@ PseudoVMFGT_VFPR16_MF4
Definition riscv/opcodes.hpp:6680
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M4_MASK
@ PseudoVMSLT_VV_M4_MASK
Definition riscv/opcodes.hpp:7198
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E32_MASK
@ PseudoVDIV_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:1538
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_M1
@ PseudoVSM4R_VS_M2_M1
Definition riscv/opcodes.hpp:8939
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_M1_MASK
@ PseudoVLSSEG5E8_V_M1_MASK
Definition riscv/opcodes.hpp:5503
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M4_E16
@ PseudoVFMAX_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2061
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M8
@ PseudoVMADC_VXM_M8
Definition riscv/opcodes.hpp:6461
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF8
@ PseudoVLOXSEG2EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:4402
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF4
@ PseudoVLOXSEG5EI64_V_M1_MF4
Definition riscv/opcodes.hpp:4734
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E32
@ PseudoVFNCVT_F_X_W_M4_E32
Definition riscv/opcodes.hpp:2481
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF4
@ PseudoVNSRA_WV_MF4
Definition riscv/opcodes.hpp:7574
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF4_E16
@ PseudoVFNMSAC_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2745
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E32
@ PseudoVFADD_VV_MF2_E32
Definition riscv/opcodes.hpp:1655
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M2_MASK
@ PseudoVLSSEG3E64_V_M2_MASK
Definition riscv/opcodes.hpp:5451
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E16
@ PseudoVREDAND_VS_M8_E16
Definition riscv/opcodes.hpp:7724
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF2_MASK
@ PseudoVSOXSEG7EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9740
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M4
@ PseudoVSLIDEDOWN_VX_M4
Definition riscv/opcodes.hpp:8840
LIEF::assembly::riscv::OPCODE::C_FSWSP
@ C_FSWSP
Definition riscv/opcodes.hpp:12496
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M8_M1
@ PseudoVSOXSEG8EI64_V_M8_M1
Definition riscv/opcodes.hpp:9809
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M4_E32_MASK
@ PseudoVFMACC_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:1954
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M1
@ PseudoVFNCVT_X_F_W_M1
Definition riscv/opcodes.hpp:2603
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M2_MASK
@ PseudoVREV8_V_M2_MASK
Definition riscv/opcodes.hpp:8263
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E16
@ PseudoVREDMAXU_VS_M4_E16
Definition riscv/opcodes.hpp:7760
LIEF::assembly::riscv::OPCODE::LH
@ LH
Definition riscv/opcodes.hpp:12839
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E32_MASK
@ PseudoVFDIV_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:1902
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M2_E32_MASK
@ PseudoVFRDIV_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2890
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M1
@ PseudoVRGATHEREI16_VV_M1_E32_M1
Definition riscv/opcodes.hpp:8282
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B1
@ PseudoVFIRST_M_B1
Definition riscv/opcodes.hpp:1923
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M1
@ PseudoVLSEG4E32_V_M1
Definition riscv/opcodes.hpp:5204
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF2_MASK
@ PseudoVLSSEG8E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5565
LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_M8
@ PseudoVMNOR_MM_M8
Definition riscv/opcodes.hpp:6892
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M1_MASK
@ PseudoVFNCVT_RTZ_XU_F_W_M1_MASK
Definition riscv/opcodes.hpp:2568
LIEF::assembly::riscv::OPCODE::VMV_X_S
@ VMV_X_S
Definition riscv/opcodes.hpp:13564
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M8_MASK
@ PseudoVSUXEI32_V_M4_M8_MASK
Definition riscv/opcodes.hpp:10568
LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M8
@ PseudoVSM3ME_VV_M8
Definition riscv/opcodes.hpp:8928
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_M1_MASK
@ PseudoVLOXSEG5EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4739
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF2
@ PseudoVFWCVT_X_F_V_MF2
Definition riscv/opcodes.hpp:3693
LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_MF2_MASK
@ PseudoVLE32FF_V_MF2_MASK
Definition riscv/opcodes.hpp:4116
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M2_M1_MASK
@ PseudoVSUXSEG6EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11100
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M8_MASK
@ PseudoVMFGE_VFPR16_M8_MASK
Definition riscv/opcodes.hpp:6647
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M4_MASK
@ PseudoVLE8_V_M4_MASK
Definition riscv/opcodes.hpp:4162
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M1_E32_MASK
@ PseudoVFWMACC_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3742
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E16
@ PseudoVWREDSUMU_VS_M4_E16
Definition riscv/opcodes.hpp:11623
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF2_MASK
@ PseudoVBREV8_V_MF2_MASK
Definition riscv/opcodes.hpp:925
LIEF::assembly::riscv::OPCODE::FCVT_H_WU_INX
@ FCVT_H_WU_INX
Definition riscv/opcodes.hpp:12601
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M1
@ PseudoVLOXSEG2EI32_V_M4_M1
Definition riscv/opcodes.hpp:4386
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M4_E64
@ PseudoVFMIN_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2158
LIEF::assembly::riscv::OPCODE::FMIN_S
@ FMIN_S
Definition riscv/opcodes.hpp:12711
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M8_M8
@ PseudoVLUXEI8_V_M8_M8
Definition riscv/opcodes.hpp:5700
LIEF::assembly::riscv::OPCODE::VLSEG7E64_V
@ VLSEG7E64_V
Definition riscv/opcodes.hpp:13413
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E16_MASK
@ PseudoVDIV_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:1536
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E8_MASK
@ PseudoVREDXOR_VS_MF2_E8_MASK
Definition riscv/opcodes.hpp:8045
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF4
@ PseudoVSRA_VX_MF4
Definition riscv/opcodes.hpp:9901
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF2
@ PseudoVLUXSEG2EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:5856
LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M4_MASK
@ PseudoVFROUND_NOEXCEPT_V_M4_MASK
Definition riscv/opcodes.hpp:3057
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E16_MASK
@ PseudoVFCVT_F_XU_V_M8_E16_MASK
Definition riscv/opcodes.hpp:1690
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF8
@ PseudoVNMSUB_VV_MF8
Definition riscv/opcodes.hpp:7538
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_M1_MASK
@ PseudoVSSEG5E16_V_M1_MASK
Definition riscv/opcodes.hpp:10084
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF2
@ PseudoVNSRL_WI_MF2
Definition riscv/opcodes.hpp:7596
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M4_E16
@ PseudoVFSGNJX_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3185
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF4
@ PseudoVLOXEI8_V_MF4_MF4
Definition riscv/opcodes.hpp:4324
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_M1
@ PseudoVSUXSEG8EI16_V_M1_M1
Definition riscv/opcodes.hpp:11255
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E8
@ PseudoVREDAND_VS_M2_E8
Definition riscv/opcodes.hpp:7714
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF8
@ PseudoVLUXSEG4EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:6026
LIEF::assembly::riscv::OPCODE::C_SB
@ C_SB
Definition riscv/opcodes.hpp:12527
LIEF::assembly::riscv::OPCODE::VSUXSEG4EI64_V
@ VSUXSEG4EI64_V
Definition riscv/opcodes.hpp:13784
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF4
@ PseudoVWMACCSU_VV_MF4
Definition riscv/opcodes.hpp:11463
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_MF2_E32_MASK
@ PseudoVFWNMACC_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3856
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M1_MASK
@ PseudoVZEXT_VF4_M1_MASK
Definition riscv/opcodes.hpp:11894
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M2
@ PseudoVSUXSEG4EI8_V_MF4_M2
Definition riscv/opcodes.hpp:11001
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_M4
@ PseudoVC_FPR16V_SE_M4
Definition riscv/opcodes.hpp:1092
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E16_MASK
@ PseudoVFNMADD_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:2724
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF2
@ PseudoVLOXSEG6EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:4804
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF8
@ PseudoVSOXSEG3EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:9399
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M8
@ PseudoVFMERGE_VFPR64M_M8
Definition riscv/opcodes.hpp:2131
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M2
@ PseudoVLUXEI64_V_M2_M2
Definition riscv/opcodes.hpp:5660
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_MF4
@ PseudoVC_V_VVW_MF4
Definition riscv/opcodes.hpp:1320
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M2_MASK
@ PseudoVLE16_V_M2_MASK
Definition riscv/opcodes.hpp:4098
LIEF::assembly::riscv::OPCODE::VSRA_VX
@ VSRA_VX
Definition riscv/opcodes.hpp:13694
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_MF4
@ PseudoVC_V_IV_MF4
Definition riscv/opcodes.hpp:1279
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_MF2
@ PseudoVLUXSEG7EI64_V_M4_MF2
Definition riscv/opcodes.hpp:6298
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF8
@ PseudoVFNCVT_RM_XU_F_W_MF8
Definition riscv/opcodes.hpp:2535
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK
@ PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK
Definition riscv/opcodes.hpp:2554
LIEF::assembly::riscv::OPCODE::MUL
@ MUL
Definition riscv/opcodes.hpp:12901
LIEF::assembly::riscv::OPCODE::AMOMIN_D_AQ_RL
@ AMOMIN_D_AQ_RL
Definition riscv/opcodes.hpp:12057
LIEF::assembly::riscv::OPCODE::FSUB_H_INX
@ FSUB_H_INX
Definition riscv/opcodes.hpp:12790
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M4
@ PseudoVFCLASS_V_M4
Definition riscv/opcodes.hpp:1663
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF2_MASK
@ PseudoVLSSEG2E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5405
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF4_MASK
@ PseudoVSUXEI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:10588
LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_4x8x4_M1
@ PseudoVQMACCSU_4x8x4_M1
Definition riscv/opcodes.hpp:7672
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M4
@ PseudoVOR_VV_M4
Definition riscv/opcodes.hpp:7644
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF8_MASK
@ PseudoVWSLL_VX_MF8_MASK
Definition riscv/opcodes.hpp:11718
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E16
@ PseudoVFREC7_V_M4_E16
Definition riscv/opcodes.hpp:2917
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M8_E64
@ PseudoVFMSAC_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2220
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E16
@ PseudoVREM_VV_MF2_E16
Definition riscv/opcodes.hpp:8204
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M1_MASK
@ PseudoVSOXSEG3EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:9370
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M2
@ PseudoVSUXSEG3EI64_V_M4_M2
Definition riscv/opcodes.hpp:10869
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M4
@ PseudoVSMUL_VX_M4
Definition riscv/opcodes.hpp:8982
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M8_MASK
@ PseudoVSUXEI8_V_M4_M8_MASK
Definition riscv/opcodes.hpp:10632
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E64
@ PseudoVFMIN_VV_M2_E64
Definition riscv/opcodes.hpp:2172
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M1
@ PseudoVMSNE_VI_M1
Definition riscv/opcodes.hpp:7221
LIEF::assembly::riscv::OPCODE::FCVT_D_H_IN32X
@ FCVT_D_H_IN32X
Definition riscv/opcodes.hpp:12575
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF4
@ PseudoVRSUB_VI_MF4
Definition riscv/opcodes.hpp:8586
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M1_MASK
@ PseudoVLOXEI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4221
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E8
@ PseudoVWREDSUMU_VS_M8_E8
Definition riscv/opcodes.hpp:11633
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF2_MASK
@ PseudoVLUXSEG7EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6285
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF2_MASK
@ PseudoVSSEG8E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10158
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M1
@ PseudoVFSLIDE1UP_VFPR16_M1
Definition riscv/opcodes.hpp:3331
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_MF2
@ PseudoVLUXSEG8EI64_V_M4_MF2
Definition riscv/opcodes.hpp:6378
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF4_MASK
@ PseudoVMFGE_VFPR16_MF4_MASK
Definition riscv/opcodes.hpp:6651
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E32
@ PseudoVFSGNJN_VV_M8_E32
Definition riscv/opcodes.hpp:3171
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF4
@ PseudoVSSSEG8E8_V_MF4
Definition riscv/opcodes.hpp:10415
LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M8
@ PseudoVSM4K_VI_M8
Definition riscv/opcodes.hpp:8933
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M4_MASK
@ PseudoVMSGTU_VI_M4_MASK
Definition riscv/opcodes.hpp:7014
LIEF::assembly::riscv::OPCODE::FSGNJX_H
@ FSGNJX_H
Definition riscv/opcodes.hpp:12767
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF4_E16
@ PseudoVFRDIV_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2885
LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B32
@ PseudoVMCLR_M_B32
Definition riscv/opcodes.hpp:6573
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF4_MASK
@ PseudoVFWCVT_XU_F_V_MF4_MASK
Definition riscv/opcodes.hpp:3686
LIEF::assembly::riscv::OPCODE::AMOMAXU_D
@ AMOMAXU_D
Definition riscv/opcodes.hpp:12007
LIEF::assembly::riscv::OPCODE::VFRSQRT7_V
@ VFRSQRT7_V
Definition riscv/opcodes.hpp:13259
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M8
@ PseudoVFSLIDE1DOWN_VFPR32_M8
Definition riscv/opcodes.hpp:3319
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M1_MASK
@ PseudoVLUXSEG4EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6037
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B2_MASK
@ PseudoVFIRST_M_B2_MASK
Definition riscv/opcodes.hpp:1928
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M8_MASK
@ PseudoVFSLIDE1DOWN_VFPR16_M8_MASK
Definition riscv/opcodes.hpp:3308
LIEF::assembly::riscv::OPCODE::VMFLE_VV
@ VMFLE_VV
Definition riscv/opcodes.hpp:13508
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF4_MASK
@ PseudoVMFLT_VV_MF4_MASK
Definition riscv/opcodes.hpp:6783
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF8
@ PseudoVSUXSEG4EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:10931
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF2
@ PseudoVLSSEG7E16_V_MF2
Definition riscv/opcodes.hpp:5532
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M1_MASK
@ PseudoVFWCVT_RM_XU_F_V_M1_MASK
Definition riscv/opcodes.hpp:3638
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S_M8
@ PseudoVFMV_FPR32_S_M8
Definition riscv/opcodes.hpp:2381
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF8_MASK
@ PseudoVLOXSEG7EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:4889
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B32
@ PseudoVMSBF_M_B32
Definition riscv/opcodes.hpp:6944
LIEF::assembly::riscv::OPCODE::AMOCAS_B_RL
@ AMOCAS_B_RL
Definition riscv/opcodes.hpp:11982
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF4_MASK
@ PseudoVLE8FF_V_MF4_MASK
Definition riscv/opcodes.hpp:4154
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M8
@ PseudoVLUXEI32_V_M8_M8
Definition riscv/opcodes.hpp:5640
LIEF::assembly::riscv::OPCODE::AMOMIN_H_AQ
@ AMOMIN_H_AQ
Definition riscv/opcodes.hpp:12060
LIEF::assembly::riscv::OPCODE::PseudoLBU
@ PseudoLBU
Definition riscv/opcodes.hpp:391
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E8_MASK
@ PseudoVDIVU_VV_M4_E8_MASK
Definition riscv/opcodes.hpp:1446
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M2_MASK
@ PseudoVSOXSEG3EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:9388
LIEF::assembly::riscv::OPCODE::VSHA2CH_VV
@ VSHA2CH_VV
Definition riscv/opcodes.hpp:13640
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF4_MASK
@ PseudoVSADD_VV_MF4_MASK
Definition riscv/opcodes.hpp:8671
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF4
@ PseudoVWMULSU_VX_MF4
Definition riscv/opcodes.hpp:11559
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M1
@ PseudoVLOXSEG3EI8_V_MF2_M1
Definition riscv/opcodes.hpp:4558
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF8_MASK
@ PseudoVLOXSEG4EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:4607
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M8_MASK
@ PseudoVFCVT_RM_XU_F_V_M8_MASK
Definition riscv/opcodes.hpp:1798
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E16_MASK
@ PseudoVFCVT_F_XU_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:1696
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M1_E64
@ PseudoVFADD_VFPR64_M1_E64
Definition riscv/opcodes.hpp:1621
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32
@ PseudoVFWSUB_WV_MF2_E32
Definition riscv/opcodes.hpp:4037
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_M8
@ PseudoVC_V_FPR64V_M8
Definition riscv/opcodes.hpp:1243
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M2
@ PseudoVSOXEI16_V_M2_M2
Definition riscv/opcodes.hpp:9009
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M1
@ PseudoVLOXSEG4EI8_V_MF2_M1
Definition riscv/opcodes.hpp:4668
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF2_MASK
@ PseudoVLOXSEG7EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4919
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M4
@ PseudoVCPOP_V_M4
Definition riscv/opcodes.hpp:1054
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF8_E8_MASK
@ PseudoVREDSUM_VS_MF8_E8_MASK
Definition riscv/opcodes.hpp:8007
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M1
@ PseudoVSUXSEG4EI8_V_M1_M1
Definition riscv/opcodes.hpp:10987
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF4
@ PseudoVSADDU_VV_MF4
Definition riscv/opcodes.hpp:8628
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF2_MASK
@ PseudoVLOXSEG8EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4973
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF4_MASK
@ PseudoVLUXSEG3EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:5897
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF4
@ PseudoVLUXSEG8EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:6332
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF4
@ PseudoVCLMULH_VX_MF4
Definition riscv/opcodes.hpp:968
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32_MASK_TIED
@ PseudoVFWADD_WV_M4_E32_MASK_TIED
Definition riscv/opcodes.hpp:3527
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M2
@ PseudoVLOXSEG4EI8_V_MF2_M2
Definition riscv/opcodes.hpp:4670
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M2
@ PseudoVSOXSEG4EI64_V_M8_M2
Definition riscv/opcodes.hpp:9481
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF8
@ PseudoVRGATHER_VI_MF8
Definition riscv/opcodes.hpp:8446
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF8
@ PseudoVSUXSEG8EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:11293
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF2_MASK
@ PseudoVLSSEG4E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5485
LIEF::assembly::riscv::OPCODE::VLSSEG7E32_V
@ VLSSEG7E32_V
Definition riscv/opcodes.hpp:13445
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF8
@ PseudoVMSGT_VI_MF8
Definition riscv/opcodes.hpp:7049
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF4
@ PseudoVSOXSEG6EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:9661
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E32
@ PseudoVFREDOSUM_VS_M1_E32
Definition riscv/opcodes.hpp:2997
LIEF::assembly::riscv::OPCODE::VLOXSEG3EI64_V
@ VLOXSEG3EI64_V
Definition riscv/opcodes.hpp:13342
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M8_MASK
@ PseudoVROR_VI_M8_MASK
Definition riscv/opcodes.hpp:8541
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M4
@ PseudoVMSGT_VX_M4
Definition riscv/opcodes.hpp:7055
LIEF::assembly::riscv::OPCODE::FLT_D_INX
@ FLT_D_INX
Definition riscv/opcodes.hpp:12680
LIEF::assembly::riscv::OPCODE::C_MV
@ C_MV
Definition riscv/opcodes.hpp:12521
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_MF2
@ PseudoVSUXSEG7EI64_V_M4_MF2
Definition riscv/opcodes.hpp:11231
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF2
@ PseudoVLUXSEG8EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:6390
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M1_MASK
@ PseudoVRSUB_VI_M1_MASK
Definition riscv/opcodes.hpp:8577
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_M1
@ PseudoVC_V_FPR32VW_M1
Definition riscv/opcodes.hpp:1212
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1
@ PseudoVWADDU_WV_M1
Definition riscv/opcodes.hpp:11359
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M2
@ PseudoVFNCVT_RTZ_X_F_W_M2
Definition riscv/opcodes.hpp:2581
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF4_MASK
@ PseudoVSOXSEG3EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9392
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E8_MASK
@ PseudoVREMU_VX_M2_E8_MASK
Definition riscv/opcodes.hpp:8143
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E64_MASK
@ PseudoVFREDMIN_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:2970
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF4_MASK
@ PseudoVLOXSEG8EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:4983
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E16
@ PseudoVREDMIN_VS_M8_E16
Definition riscv/opcodes.hpp:7900
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_M1_MASK
@ PseudoVLUXSEG8EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6371
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF2
@ PseudoVLOXSEG6EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:4778
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF4_MASK
@ PseudoVSUXEI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:10598
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M2_MASK
@ PseudoVFWCVT_XU_F_V_M2_MASK
Definition riscv/opcodes.hpp:3680
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M1_MASK
@ PseudoVFWCVT_RM_X_F_V_M1_MASK
Definition riscv/opcodes.hpp:3648
LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_M2
@ PseudoVC_IVV_SE_M2
Definition riscv/opcodes.hpp:1120
LIEF::assembly::riscv::OPCODE::PseudoCCSRLW
@ PseudoCCSRLW
Definition riscv/opcodes.hpp:363
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M2_MASK
@ PseudoVLOXSEG2EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4381
LIEF::assembly::riscv::OPCODE::LR_D_RL
@ LR_D_RL
Definition riscv/opcodes.hpp:12846
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M2
@ PseudoVMULHSU_VV_M2
Definition riscv/opcodes.hpp:7279
LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadUMax32
@ PseudoMaskedAtomicLoadUMax32
Definition riscv/opcodes.hpp:412
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M1_MASK
@ PseudoVSOXEI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9058
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E64_MASK
@ PseudoVFREC7_V_M8_E64_MASK
Definition riscv/opcodes.hpp:2928
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF2
@ PseudoVRGATHER_VX_MF2
Definition riscv/opcodes.hpp:8500
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E16
@ PseudoVREDOR_VS_M1_E16
Definition riscv/opcodes.hpp:7920
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E32
@ PseudoVFREDOSUM_VS_MF2_E32
Definition riscv/opcodes.hpp:3021
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M4_MASK
@ PseudoVLUXEI16_V_M2_M4_MASK
Definition riscv/opcodes.hpp:5583
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF2
@ PseudoVFNCVT_XU_F_W_MF2
Definition riscv/opcodes.hpp:2597
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF2_MASK
@ PseudoVLOXSEG5EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4759
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF4
@ PseudoVLOXSEG3EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:4576
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E16
@ PseudoVREDMAXU_VS_MF4_E16
Definition riscv/opcodes.hpp:7782
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E64_MASK
@ PseudoVFSGNJ_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:3294
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M2_MASK
@ PseudoVLUXSEG2EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:5841
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M4_MASK
@ PseudoVMFGT_VFPR16_M4_MASK
Definition riscv/opcodes.hpp:6675
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M4
@ PseudoVLSEG2E32_V_M4
Definition riscv/opcodes.hpp:5086
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M2_MASK
@ PseudoVSOXSEG3EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:9382
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M4
@ PseudoVMADD_VV_M4
Definition riscv/opcodes.hpp:6476
LIEF::assembly::riscv::OPCODE::VLSEG4E64_V
@ VLSEG4E64_V
Definition riscv/opcodes.hpp:13389
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M2_MASK
@ PseudoVMAX_VX_M2_MASK
Definition riscv/opcodes.hpp:6559
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF2_MASK
@ PseudoVSUXSEG3EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:10894
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M2_M1
@ PseudoVLOXSEG8EI16_V_M2_M1
Definition riscv/opcodes.hpp:4934
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF8_MASK
@ PseudoVMSLEU_VX_MF8_MASK
Definition riscv/opcodes.hpp:7120
LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_2x8x2_M4
@ PseudoVQMACCU_2x8x2_M4
Definition riscv/opcodes.hpp:7686
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_MF8
@ PseudoVMADC_VXM_MF8
Definition riscv/opcodes.hpp:6464
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF2
@ PseudoVWADD_WX_MF2
Definition riscv/opcodes.hpp:11449
LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_D_INX
@ PseudoQuietFLE_D_INX
Definition riscv/opcodes.hpp:420
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E32_MASK
@ PseudoVFWMSAC_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3800
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF8
@ PseudoVLOXSEG6EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:4808
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_M4
@ PseudoVSM4R_VS_M8_M4
Definition riscv/opcodes.hpp:8952
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF4_MASK
@ PseudoVWADDU_WX_MF4_MASK
Definition riscv/opcodes.hpp:11392
LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M2
@ PseudoVGMUL_VV_M2
Definition riscv/opcodes.hpp:4051
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E32
@ PseudoVFSGNJX_VV_MF2_E32
Definition riscv/opcodes.hpp:3237
LIEF::assembly::riscv::OPCODE::SHA512SIG0L
@ SHA512SIG0L
Definition riscv/opcodes.hpp:12971
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF4
@ PseudoVSUXSEG8EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:11291
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E16_MASK
@ PseudoVFCVT_RM_F_XU_V_M1_E16_MASK
Definition riscv/opcodes.hpp:1732
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF8_MASK
@ PseudoVSUXSEG6EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:11114
LIEF::assembly::riscv::OPCODE::InsnCB
@ InsnCB
Definition riscv/opcodes.hpp:12815
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF2_E16_MASK
@ PseudoVFMSUB_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2261
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64VV_SE_M4
@ PseudoVC_FPR64VV_SE_M4
Definition riscv/opcodes.hpp:1113
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF8
@ PseudoVSRA_VI_MF8
Definition riscv/opcodes.hpp:9875
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M4
@ PseudoVMFNE_VFPR32_M4
Definition riscv/opcodes.hpp:6800
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M2_E16_MASK
@ PseudoVFADD_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:1602
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M4
@ PseudoVRGATHEREI16_VV_M8_E32_M4
Definition riscv/opcodes.hpp:8378
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF8
@ PseudoVLUXSEG8EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:6400
LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_MF4
@ PseudoVADC_VVM_MF4
Definition riscv/opcodes.hpp:589
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E32_MASK
@ PseudoVFWCVTBF16_F_F_V_M2_E32_MASK
Definition riscv/opcodes.hpp:3548
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M4
@ PseudoVFNCVT_XU_F_W_M4
Definition riscv/opcodes.hpp:2595
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VI
@ PseudoVMSLTU_VI
Definition riscv/opcodes.hpp:7163
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_M4
@ PseudoVAESEM_VS_M8_M4
Definition riscv/opcodes.hpp:744
LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_M2
@ PseudoVC_XVW_SE_M2
Definition riscv/opcodes.hpp:1404
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E16_MASK
@ PseudoVREDSUM_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:7997
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF2_MASK
@ PseudoVFWCVT_RTZ_X_F_V_MF2_MASK
Definition riscv/opcodes.hpp:3674
LIEF::assembly::riscv::OPCODE::VSBC_VXM
@ VSBC_VXM
Definition riscv/opcodes.hpp:13629
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M2
@ PseudoVSOXSEG2EI64_V_M2_M2
Definition riscv/opcodes.hpp:9235
LIEF::assembly::riscv::OPCODE::DBG_LABEL
@ DBG_LABEL
Definition riscv/opcodes.hpp:41
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF2
@ PseudoVMULHU_VV_MF2
Definition riscv/opcodes.hpp:7313
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E8
@ PseudoVREDSUM_VS_M2_E8
Definition riscv/opcodes.hpp:7978
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF2
@ PseudoVLSEG5E16FF_V_MF2
Definition riscv/opcodes.hpp:5240
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF2
@ PseudoVLUXSEG2EI32_V_M1_MF2
Definition riscv/opcodes.hpp:5766
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF4_MASK
@ PseudoVLOXSEG7EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4887
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M2_MASK
@ PseudoVFNCVT_RM_XU_F_W_M2_MASK
Definition riscv/opcodes.hpp:2528
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M4_MASK
@ PseudoVMULH_VV_M4_MASK
Definition riscv/opcodes.hpp:7338
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_M1_MASK
@ PseudoVSOXSEG6EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9654
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M4_M2
@ PseudoVLOXSEG4EI16_V_M4_M2
Definition riscv/opcodes.hpp:4590
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF2
@ PseudoVLOXSEG5EI64_V_M2_MF2
Definition riscv/opcodes.hpp:4740
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF4_MASK
@ PseudoVROL_VX_MF4_MASK
Definition riscv/opcodes.hpp:8531
LIEF::assembly::riscv::OPCODE::CV_MAXU_SCI_H
@ CV_MAXU_SCI_H
Definition riscv/opcodes.hpp:12347
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK
@ PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK
Definition riscv/opcodes.hpp:8419
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E64_MASK
@ PseudoVREDOR_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:7941
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_M1
@ PseudoVLOXSEG6EI8_V_MF4_M1
Definition riscv/opcodes.hpp:4836
LIEF::assembly::riscv::OPCODE::C_FLW
@ C_FLW
Definition riscv/opcodes.hpp:12491
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF2
@ PseudoVSOXSEG5EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:9525
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF2
@ PseudoVLOXSEG5EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:4764
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_M1_MASK
@ PseudoVSOXSEG6EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9632
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M4
@ PseudoVSRL_VX_M4
Definition riscv/opcodes.hpp:9937
LIEF::assembly::riscv::OPCODE::VFNCVTBF16_F_F_W
@ VFNCVTBF16_F_F_W
Definition riscv/opcodes.hpp:13234
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF4
@ PseudoVSUXSEG8EI32_V_M1_MF4
Definition riscv/opcodes.hpp:11279
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M1_MASK
@ PseudoVWSUBU_WX_M1_MASK
Definition riscv/opcodes.hpp:11768
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M2
@ PseudoVLSEG4E64FF_V_M2
Definition riscv/opcodes.hpp:5212
LIEF::assembly::riscv::OPCODE::CV_LH_rr_inc
@ CV_LH_rr_inc
Definition riscv/opcodes.hpp:12329
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_M8
@ PseudoVC_V_VV_SE_M8
Definition riscv/opcodes.hpp:1338
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E32_MASK
@ PseudoVREDXOR_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:8043
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E32
@ PseudoVFREDUSUM_VS_M8_E32
Definition riscv/opcodes.hpp:3045
LIEF::assembly::riscv::OPCODE::VLSSEG2E16_V
@ VLSSEG2E16_V
Definition riscv/opcodes.hpp:13424
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF2_MASK
@ PseudoVWSUB_VX_MF2_MASK
Definition riscv/opcodes.hpp:11798
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF2_MASK
@ PseudoVLUXSEG6EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:6231
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_M8
@ PseudoVC_V_I_SE_M8
Definition riscv/opcodes.hpp:1298
LIEF::assembly::riscv::OPCODE::VFMUL_VF
@ VFMUL_VF
Definition riscv/opcodes.hpp:13229
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_MF2_MASK
@ PseudoVLSSEG7E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5539
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M1_MASK
@ PseudoVFCVT_RM_XU_F_V_M1_MASK
Definition riscv/opcodes.hpp:1792
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M4_MASK
@ PseudoVZEXT_VF2_M4_MASK
Definition riscv/opcodes.hpp:11886
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E16_MASK
@ PseudoVFMUL_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:2361
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_MF4
@ PseudoVC_V_X_MF4
Definition riscv/opcodes.hpp:1387
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E32_MASK
@ PseudoVFMSUB_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:2303
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF4_MASK
@ PseudoVMSLE_VI_MF4_MASK
Definition riscv/opcodes.hpp:7132
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M4_E16_MASK
@ PseudoVFMAX_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2062
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E64
@ PseudoVFSGNJX_VV_M2_E64
Definition riscv/opcodes.hpp:3221
LIEF::assembly::riscv::OPCODE::SW_RL
@ SW_RL
Definition riscv/opcodes.hpp:13019
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M1
@ PseudoVRGATHEREI16_VV_M2_E8_M1
Definition riscv/opcodes.hpp:8330
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF4_E16
@ PseudoVFREC7_V_MF4_E16
Definition riscv/opcodes.hpp:2933
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF2
@ PseudoVMUL_VX_MF2
Definition riscv/opcodes.hpp:7383
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E32_MASK
@ PseudoVFNMADD_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:2726
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M1_MASK
@ PseudoVSUXSEG2EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10668
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_MF4_MASK
@ PseudoVFWCVT_RM_X_F_V_MF4_MASK
Definition riscv/opcodes.hpp:3656
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_M1
@ PseudoVLUXSEG5EI8_V_MF8_M1
Definition riscv/opcodes.hpp:6154
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_MF2
@ PseudoVSOXEI16_V_M1_MF2
Definition riscv/opcodes.hpp:9005
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M4_E32
@ PseudoVFRDIV_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2891
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M8_MASK
@ PseudoTHVdotVMAQAU_VV_M8_MASK
Definition riscv/opcodes.hpp:487
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_M1_MASK
@ PseudoVLOXSEG6EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4771
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M1
@ PseudoVMFLE_VFPR16_M1
Definition riscv/opcodes.hpp:6700
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M2
@ PseudoVSUXSEG4EI32_V_M2_M2
Definition riscv/opcodes.hpp:10943
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M8_E16_MASK
@ PseudoVFRSUB_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:3098
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M8_E32
@ PseudoVFSGNJ_VFPR32_M8_E32
Definition riscv/opcodes.hpp:3259
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E32
@ PseudoVFCVT_RM_F_XU_V_M2_E32
Definition riscv/opcodes.hpp:1739
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF4_MASK
@ PseudoVSUXSEG3EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:10814
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M4_E32
@ PseudoVFMUL_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2328
LIEF::assembly::riscv::OPCODE::CV_AND_B
@ CV_AND_B
Definition riscv/opcodes.hpp:12181
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF4
@ PseudoVAADDU_VX_MF4
Definition riscv/opcodes.hpp:545
LIEF::assembly::riscv::OPCODE::VMAND_MM
@ VMAND_MM
Definition riscv/opcodes.hpp:13495
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E32_MASK
@ PseudoVFCVT_F_X_V_M2_E32_MASK
Definition riscv/opcodes.hpp:1710
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M2_E16
@ PseudoVFWMUL_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3805
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M1
@ PseudoVNMSAC_VX_M1
Definition riscv/opcodes.hpp:7512
LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_M1
@ PseudoVSPILL5_M1
Definition riscv/opcodes.hpp:9847
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M2_MASK
@ PseudoVRGATHEREI16_VV_M2_E8_M2_MASK
Definition riscv/opcodes.hpp:8333
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M8_E64_MASK
@ PseudoVFADD_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:1628
LIEF::assembly::riscv::OPCODE::FROUNDNX_D
@ FROUNDNX_D
Definition riscv/opcodes.hpp:12750
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M2_MASK
@ PseudoVSUXSEG3EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:10876
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M4_MASK
@ PseudoVSOXSEG2EI64_V_M4_M4_MASK
Definition riscv/opcodes.hpp:9246
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_MF2
@ PseudoVSOXSEG7EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:9735
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M1
@ PseudoVSLIDEDOWN_VX_M1
Definition riscv/opcodes.hpp:8836
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M2_MASK
@ PseudoVMSLEU_VV_M2_MASK
Definition riscv/opcodes.hpp:7096
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF2_MASK
@ PseudoVLOXSEG2EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4375
LIEF::assembly::riscv::OPCODE::LR_W_AQ_RL
@ LR_W_AQ_RL
Definition riscv/opcodes.hpp:12849
LIEF::assembly::riscv::OPCODE::G_PREFETCH
@ G_PREFETCH
Definition riscv/opcodes.hpp:141
LIEF::assembly::riscv::OPCODE::AMOADD_H_RL
@ AMOADD_H_RL
Definition riscv/opcodes.hpp:11958
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M4_MASK
@ PseudoVLSSEG2E32_V_M4_MASK
Definition riscv/opcodes.hpp:5413
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4_MASK
@ PseudoVWSUB_WV_MF4_MASK
Definition riscv/opcodes.hpp:11820
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF2_MASK
@ PseudoVSADD_VX_MF2_MASK
Definition riscv/opcodes.hpp:8683
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16
@ PseudoVFWADD_WV_M1_E16
Definition riscv/opcodes.hpp:3505
LIEF::assembly::riscv::OPCODE::G_FEXP10
@ G_FEXP10
Definition riscv/opcodes.hpp:207
LIEF::assembly::riscv::OPCODE::FLE_D_INX
@ FLE_D_INX
Definition riscv/opcodes.hpp:12666
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M8_MASK
@ PseudoTHVdotVMAQASU_VV_M8_MASK
Definition riscv/opcodes.hpp:457
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_MF2_MASK
@ PseudoVSUXSEG5EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:11044
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_M1
@ PseudoVLUXSEG5EI16_V_MF2_M1
Definition riscv/opcodes.hpp:6088
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E8
@ PseudoVREMU_VV_MF4_E8
Definition riscv/opcodes.hpp:8124
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF8
@ PseudoVOR_VI_MF8
Definition riscv/opcodes.hpp:7638
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF4_E16
@ PseudoVFNCVT_RM_F_XU_W_MF4_E16
Definition riscv/opcodes.hpp:2505
LIEF::assembly::riscv::OPCODE::AES64KS1I
@ AES64KS1I
Definition riscv/opcodes.hpp:11945
LIEF::assembly::riscv::OPCODE::FCVT_S_W_INX
@ FCVT_S_W_INX
Definition riscv/opcodes.hpp:12628
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M2_MASK
@ PseudoVLOXSEG3EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4545
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E32_MASK
@ PseudoVFCVT_RM_F_XU_V_M1_E32_MASK
Definition riscv/opcodes.hpp:1734
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF4_E16_MASK
@ PseudoVFREDOSUM_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:3024
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M4_E32
@ PseudoVFSGNJN_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3137
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF4_E16
@ PseudoVFCVT_RM_F_X_V_MF4_E16
Definition riscv/opcodes.hpp:1789
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M2_MASK
@ PseudoVLSEG2E16FF_V_M2_MASK
Definition riscv/opcodes.hpp:5057
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M1_MASK
@ PseudoVLOXEI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4291
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF4
@ PseudoVADD_VI_MF4
Definition riscv/opcodes.hpp:608
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E32_MASK
@ PseudoVFMADD_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:2054
LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M4
@ PseudoVADC_VXM_M4
Definition riscv/opcodes.hpp:593
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M4
@ PseudoVNMSUB_VV_M4
Definition riscv/opcodes.hpp:7530
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_MF2
@ PseudoVC_V_X_MF2
Definition riscv/opcodes.hpp:1386
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M8_E64
@ PseudoVFNMSUB_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2823
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_SE_M2
@ PseudoVC_V_FPR64V_SE_M2
Definition riscv/opcodes.hpp:1245
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF8
@ PseudoVLOXSEG8EI64_V_M1_MF8
Definition riscv/opcodes.hpp:4976
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_MF2
@ PseudoVSOXSEG8EI32_V_M2_MF2
Definition riscv/opcodes.hpp:9779
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF2_MASK
@ PseudoVMULH_VV_MF2_MASK
Definition riscv/opcodes.hpp:7342
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF2
@ PseudoVMSNE_VV_MF2
Definition riscv/opcodes.hpp:7243
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF2_MASK
@ PseudoVLUXSEG2EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:5809
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M4
@ PseudoVSUXSEG2EI32_V_M2_M4
Definition riscv/opcodes.hpp:10707
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_M1_MASK
@ PseudoVSUXSEG7EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11238
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M2
@ PseudoVSSEG4E16_V_M2
Definition riscv/opcodes.hpp:10057
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_MF8
@ PseudoVAESDF_VS_M8_MF8
Definition riscv/opcodes.hpp:660
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M1_MASK
@ PseudoVSSRA_VX_M1_MASK
Definition riscv/opcodes.hpp:10192
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF8_MASK
@ PseudoVLUXSEG6EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:6241
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E16_MASK
@ PseudoVFNCVTBF16_F_F_W_M2_E16_MASK
Definition riscv/opcodes.hpp:2422
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF4_MASK
@ PseudoVLSEG6E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5315
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF4_E16
@ PseudoVFSUB_VV_MF4_E16
Definition riscv/opcodes.hpp:3449
LIEF::assembly::riscv::OPCODE::SC_W
@ SC_W
Definition riscv/opcodes.hpp:12943
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M1_E32
@ PseudoVFSGNJX_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3193
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF2_MASK
@ PseudoVLE16_V_MF2_MASK
Definition riscv/opcodes.hpp:4104
LIEF::assembly::riscv::OPCODE::ICALL_BRANCH_FUNNEL
@ ICALL_BRANCH_FUNNEL
Definition riscv/opcodes.hpp:65
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E32_MASK
@ PseudoVFMSAC_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:2243
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF2
@ PseudoVSSSEG8E16_V_MF2
Definition riscv/opcodes.hpp:10401
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF4
@ PseudoVWADDU_VV_MF4
Definition riscv/opcodes.hpp:11343
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M2
@ PseudoTHVdotVMAQAU_VV_M2
Definition riscv/opcodes.hpp:482
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_M1_MASK
@ PseudoVSSEG8E32_V_M1_MASK
Definition riscv/opcodes.hpp:10150
LIEF::assembly::riscv::OPCODE::CV_CMPGEU_H
@ CV_CMPGEU_H
Definition riscv/opcodes.hpp:12218
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF8
@ PseudoVLSEG6E8_V_MF8
Definition riscv/opcodes.hpp:5316
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M1
@ PseudoVLOXSEG4EI16_V_M2_M1
Definition riscv/opcodes.hpp:4586
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E16_MASK
@ PseudoVFWMUL_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3822
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF8
@ PseudoVSOXSEG8EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:9829
LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M4
@ PseudoVADC_VVM_M4
Definition riscv/opcodes.hpp:586
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M2_E16_MASK
@ PseudoVFNMSUB_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2798
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF4_MASK
@ PseudoVSOXSEG8EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9822
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E16_MASK
@ PseudoVRGATHER_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:8487
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF2
@ PseudoVLUXSEG2EI64_V_M1_MF2
Definition riscv/opcodes.hpp:5798
LIEF::assembly::riscv::OPCODE::FCVT_WU_H
@ FCVT_WU_H
Definition riscv/opcodes.hpp:12632
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M4_MASK
@ PseudoVRGATHEREI16_VV_M8_E16_M4_MASK
Definition riscv/opcodes.hpp:8373
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF4_MASK
@ PseudoVLOXSEG6EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4841
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_M1
@ PseudoVSOXSEG6EI16_V_MF2_M1
Definition riscv/opcodes.hpp:9597
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF4
@ PseudoVROR_VX_MF4
Definition riscv/opcodes.hpp:8572
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF4_MASK
@ PseudoVSUXSEG5EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:11068
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M2
@ PseudoVSBC_VXM_M2
Definition riscv/opcodes.hpp:8696
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M4
@ PseudoVSUXEI16_V_M8_M4
Definition riscv/opcodes.hpp:10525
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF4
@ PseudoVSLIDEUP_VX_MF4
Definition riscv/opcodes.hpp:8874
LIEF::assembly::riscv::OPCODE::G_VSCALE
@ G_VSCALE
Definition riscv/opcodes.hpp:247
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M2_MASK
@ PseudoVSUXEI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10618
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E32
@ PseudoVDIV_VV_M4_E32
Definition riscv/opcodes.hpp:1529
LIEF::assembly::riscv::OPCODE::VSUXSEG3EI32_V
@ VSUXSEG3EI32_V
Definition riscv/opcodes.hpp:13779
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E8_MASK
@ PseudoVREDSUM_VS_MF2_E8_MASK
Definition riscv/opcodes.hpp:8001
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF8
@ PseudoVSOXSEG5EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:9529
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF2_MASK
@ PseudoVMFLE_VFPR16_MF2_MASK
Definition riscv/opcodes.hpp:6709
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E8_MASK
@ PseudoVREMU_VX_M8_E8_MASK
Definition riscv/opcodes.hpp:8159
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M1_MASK
@ PseudoVSOXSEG4EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9408
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M8
@ PseudoVSUXEI8_V_M2_M8
Definition riscv/opcodes.hpp:10627
LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_MF4
@ PseudoVC_X_SE_MF4
Definition riscv/opcodes.hpp:1421
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M1_MASK
@ PseudoVSUXSEG4EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10918
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M1_MASK
@ PseudoVLSEG4E8FF_V_M1_MASK
Definition riscv/opcodes.hpp:5219
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_MF2_E32_MASK
@ PseudoVFSGNJX_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3202
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E32_MASK
@ PseudoVREDMAXU_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:7771
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF4
@ PseudoVLOXSEG4EI64_V_M2_MF4
Definition riscv/opcodes.hpp:4650
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M2
@ PseudoVLOXSEG3EI64_V_M8_M2
Definition riscv/opcodes.hpp:4550
LIEF::assembly::riscv::OPCODE::AMOOR_B_RL
@ AMOOR_B_RL
Definition riscv/opcodes.hpp:12070
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_M4
@ PseudoVC_V_FPR16VW_M4
Definition riscv/opcodes.hpp:1180
LIEF::assembly::riscv::OPCODE::CV_AVGU_SC_H
@ CV_AVGU_SC_H
Definition riscv/opcodes.hpp:12192
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF4_E16_MASK
@ PseudoVFWSUB_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3990
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF4_MASK
@ PseudoVNSRL_WX_MF4_MASK
Definition riscv/opcodes.hpp:7623
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF4_MASK
@ PseudoVSUXSEG6EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:11106
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_MF2_MASK
@ PseudoVLOXEI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4235
LIEF::assembly::riscv::OPCODE::AMOCAS_B_AQ_RL
@ AMOCAS_B_AQ_RL
Definition riscv/opcodes.hpp:11981
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E16
@ PseudoVFWCVTBF16_F_F_V_M4_E16
Definition riscv/opcodes.hpp:3549
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M1_E16_MASK
@ PseudoVFNMSAC_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:2736
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_MF2
@ PseudoVMADC_VI_MF2
Definition riscv/opcodes.hpp:6441
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_MF2
@ PseudoVSUXSEG8EI32_V_M2_MF2
Definition riscv/opcodes.hpp:11283
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M2_MASK
@ PseudoVRGATHEREI16_VV_M8_E8_M2_MASK
Definition riscv/opcodes.hpp:8389
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M1
@ PseudoVSUXSEG2EI8_V_MF2_M1
Definition riscv/opcodes.hpp:10771
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_MF2
@ PseudoVSOXEI64_V_M4_MF2
Definition riscv/opcodes.hpp:9101
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_M2
@ PseudoVSM4R_VS_M4_M2
Definition riscv/opcodes.hpp:8945
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M8
@ PseudoVMACC_VX_M8
Definition riscv/opcodes.hpp:6422
LIEF::assembly::riscv::OPCODE::FMADD_D_IN32X
@ FMADD_D_IN32X
Definition riscv/opcodes.hpp:12687
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M4_MASK
@ PseudoVFSLIDE1DOWN_VFPR16_M4_MASK
Definition riscv/opcodes.hpp:3306
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF4
@ PseudoVNCLIP_WI_MF4
Definition riscv/opcodes.hpp:7470
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E16
@ PseudoVWREDSUMU_VS_MF4_E16
Definition riscv/opcodes.hpp:11641
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E16_MASK
@ PseudoVFCVT_RM_F_XU_V_M2_E16_MASK
Definition riscv/opcodes.hpp:1738
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E32
@ PseudoVFWCVTBF16_F_F_V_M1_E32
Definition riscv/opcodes.hpp:3543
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF2
@ PseudoVLOXSEG2EI32_V_M1_MF2
Definition riscv/opcodes.hpp:4374
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF2_MASK
@ PseudoVSOXSEG6EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9634
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF8_MASK
@ PseudoVSSSEG6E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10378
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E16_MASK
@ PseudoVFCVT_RM_F_X_V_M8_E16_MASK
Definition riscv/opcodes.hpp:1780
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF2
@ PseudoVAADDU_VX_MF2
Definition riscv/opcodes.hpp:543
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF4
@ PseudoVLUXSEG5EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:6092
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M1
@ PseudoVSOXEI64_V_M4_M1
Definition riscv/opcodes.hpp:9095
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E64_MASK
@ PseudoVFREDMIN_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:2988
LIEF::assembly::riscv::OPCODE::VLUXSEG5EI16_V
@ VLUXSEG5EI16_V
Definition riscv/opcodes.hpp:13468
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M4
@ PseudoVSMUL_VV_M4
Definition riscv/opcodes.hpp:8968
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E16
@ PseudoVFMIN_VV_MF2_E16
Definition riscv/opcodes.hpp:2186
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF2_MASK
@ PseudoVMAXU_VV_MF2_MASK
Definition riscv/opcodes.hpp:6523
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF8_MASK
@ PseudoVLUXSEG3EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:5971
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF8_MASK
@ PseudoVMUL_VX_MF8_MASK
Definition riscv/opcodes.hpp:7388
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_MF2
@ PseudoVMFEQ_VFPR32_MF2
Definition riscv/opcodes.hpp:6618
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M1_MASK
@ PseudoVRGATHEREI16_VV_M2_E32_M1_MASK
Definition riscv/opcodes.hpp:8315
LIEF::assembly::riscv::OPCODE::VC_XV
@ VC_XV
Definition riscv/opcodes.hpp:13197
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M8
@ PseudoVXOR_VV_M8
Definition riscv/opcodes.hpp:11859
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF2_MASK
@ PseudoVNSRL_WX_MF2_MASK
Definition riscv/opcodes.hpp:7621
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF2_MASK
@ PseudoVSLIDEDOWN_VI_MF2_MASK
Definition riscv/opcodes.hpp:8831
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M1
@ PseudoVLUXSEG4EI32_V_M2_M1
Definition riscv/opcodes.hpp:6008
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E64_MASK
@ PseudoVDIV_VX_M4_E64_MASK
Definition riscv/opcodes.hpp:1576
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF8_MASK
@ PseudoVSE8_V_MF8_MASK
Definition riscv/opcodes.hpp:8745
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF4_MASK
@ PseudoVLSSEG5E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5507
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_MF4
@ PseudoVRELOAD8_MF4
Definition riscv/opcodes.hpp:8082
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64_V_M1_MASK
@ PseudoVLSEG8E64_V_M1_MASK
Definition riscv/opcodes.hpp:5381
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF4
@ PseudoVLSEG5E8FF_V_MF4
Definition riscv/opcodes.hpp:5266
LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_M8
@ PseudoVC_VV_SE_M8
Definition riscv/opcodes.hpp:1162
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF2
@ PseudoVSOXSEG8EI64_V_M1_MF2
Definition riscv/opcodes.hpp:9793
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M1_MASK
@ PseudoVSRL_VX_M1_MASK
Definition riscv/opcodes.hpp:9934
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF2
@ PseudoVLSEG2E8_V_MF2
Definition riscv/opcodes.hpp:5120
LIEF::assembly::riscv::OPCODE::AMOMIN_H_RL
@ AMOMIN_H_RL
Definition riscv/opcodes.hpp:12062
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF2_MASK
@ PseudoVLOXSEG2EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4365
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M8_M1
@ PseudoVSOXSEG5EI64_V_M8_M1
Definition riscv/opcodes.hpp:9569
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M1
@ PseudoVZEXT_VF8_M1
Definition riscv/opcodes.hpp:11903
LIEF::assembly::riscv::OPCODE::FMADD_H_INX
@ FMADD_H_INX
Definition riscv/opcodes.hpp:12690
LIEF::assembly::riscv::OPCODE::VLSEG7E32FF_V
@ VLSEG7E32FF_V
Definition riscv/opcodes.hpp:13410
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_MF2
@ PseudoVSUXSEG2EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:10777
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E16
@ PseudoVFMSUB_VV_M8_E16
Definition riscv/opcodes.hpp:2300
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E32
@ PseudoVWREDSUMU_VS_MF2_E32
Definition riscv/opcodes.hpp:11637
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M2_MASK
@ PseudoVSUXEI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10594
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E8
@ PseudoVREDSUM_VS_M8_E8
Definition riscv/opcodes.hpp:7994
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF2_E32
@ PseudoVCOMPRESS_VM_MF2_E32
Definition riscv/opcodes.hpp:1031
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E32
@ PseudoVFREDOSUM_VS_M2_E32
Definition riscv/opcodes.hpp:3003
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M1_MASK
@ PseudoVNSRL_WX_M1_MASK
Definition riscv/opcodes.hpp:7615
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_MF2
@ PseudoVLOXSEG4EI16_V_M1_MF2
Definition riscv/opcodes.hpp:4584
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M2_MASK
@ PseudoVSUXEI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:10646
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF4_MASK
@ PseudoVLUXSEG5EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:6159
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M2
@ PseudoVLSSEG2E64_V_M2
Definition riscv/opcodes.hpp:5418
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_M1
@ PseudoVC_V_VVV_M1
Definition riscv/opcodes.hpp:1302
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FADD
@ G_VECREDUCE_FADD
Definition riscv/opcodes.hpp:302
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M1_MASK
@ PseudoVMSGT_VX_M1_MASK
Definition riscv/opcodes.hpp:7052
LIEF::assembly::riscv::OPCODE::VSSEG3E8_V
@ VSSEG3E8_V
Definition riscv/opcodes.hpp:13709
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M8_MASK
@ PseudoVBREV_V_M8_MASK
Definition riscv/opcodes.hpp:937
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M2_MASK
@ PseudoVSUXEI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10514
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_MF8
@ PseudoVAESEF_VS_M2_MF8
Definition riscv/opcodes.hpp:706
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E32
@ PseudoVFWREDUSUM_VS_M2_E32
Definition riscv/opcodes.hpp:3939
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M8_E32
@ PseudoVFMADD_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2015
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M4_MASK
@ PseudoVSOXEI16_V_M4_M4_MASK
Definition riscv/opcodes.hpp:9018
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E16
@ PseudoVFNCVTBF16_F_F_W_M4_E16
Definition riscv/opcodes.hpp:2425
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E64_MASK
@ PseudoVFREDMAX_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:2946
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E32
@ PseudoVFCVT_RM_F_X_V_M1_E32
Definition riscv/opcodes.hpp:1763
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M2
@ PseudoVFWCVT_RTZ_X_F_V_M2
Definition riscv/opcodes.hpp:3669
LIEF::assembly::riscv::OPCODE::VLSSEG6E16_V
@ VLSSEG6E16_V
Definition riscv/opcodes.hpp:13440
LIEF::assembly::riscv::OPCODE::CV_DOTSP_SCI_H
@ CV_DOTSP_SCI_H
Definition riscv/opcodes.hpp:12284
LIEF::assembly::riscv::OPCODE::CV_MULHHUN
@ CV_MULHHUN
Definition riscv/opcodes.hpp:12373
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF2_MASK
@ PseudoVSSRL_VV_MF2_MASK
Definition riscv/opcodes.hpp:10228
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_MF2
@ PseudoVSUXEI8_V_MF2_MF2
Definition riscv/opcodes.hpp:10641
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF8_MASK
@ PseudoVWADDU_VV_MF8_MASK
Definition riscv/opcodes.hpp:11346
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M8
@ PseudoVMERGE_VVM_M8
Definition riscv/opcodes.hpp:6587
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF4_MASK
@ PseudoVNMSAC_VV_MF4_MASK
Definition riscv/opcodes.hpp:7509
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_MF2
@ PseudoVC_FPR16VV_SE_MF2
Definition riscv/opcodes.hpp:1082
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E8
@ PseudoVREM_VV_M1_E8
Definition riscv/opcodes.hpp:8178
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M2
@ PseudoVSUXSEG2EI16_V_M2_M2
Definition riscv/opcodes.hpp:10669
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E64_MASK
@ PseudoVREDSUM_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:7977
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M8
@ PseudoVFMV_V_FPR64_M8
Definition riscv/opcodes.hpp:2416
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M4_MASK
@ PseudoVSMUL_VX_M4_MASK
Definition riscv/opcodes.hpp:8983
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E16
@ PseudoVFWMSAC_VV_M1_E16
Definition riscv/opcodes.hpp:3785
LIEF::assembly::riscv::OPCODE::VSM4K_VI
@ VSM4K_VI
Definition riscv/opcodes.hpp:13654
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M2_MASK
@ PseudoVLOXSEG3EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4479
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M4
@ PseudoVLOXSEG2EI16_V_M1_M4
Definition riscv/opcodes.hpp:4338
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M2
@ PseudoVMFLE_VFPR32_M2
Definition riscv/opcodes.hpp:6714
LIEF::assembly::riscv::OPCODE::VFWMSAC_VV
@ VFWMSAC_VV
Definition riscv/opcodes.hpp:13290
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK
@ PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK
Definition riscv/opcodes.hpp:2500
LIEF::assembly::riscv::OPCODE::G_VMSET_VL
@ G_VMSET_VL
Definition riscv/opcodes.hpp:326
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E32_MASK
@ PseudoVFSGNJN_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3166
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E8
@ PseudoVREMU_VV_MF2_E8
Definition riscv/opcodes.hpp:8120
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M2_MASK
@ PseudoVFCVT_RTZ_XU_F_V_M2_MASK
Definition riscv/opcodes.hpp:1818
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF4_E16
@ PseudoVFMSAC_VV_MF4_E16
Definition riscv/opcodes.hpp:2250
LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_2x8x2_M1
@ PseudoVQMACCSU_2x8x2_M1
Definition riscv/opcodes.hpp:7668
LIEF::assembly::riscv::OPCODE::PseudoCCXOR
@ PseudoCCXOR
Definition riscv/opcodes.hpp:367
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M2_MASK
@ PseudoVLOXSEG4EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4619
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M2_E32
@ PseudoVFWADD_WFPR32_M2_E32
Definition riscv/opcodes.hpp:3499
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M8_MASK
@ PseudoVMFGE_VFPR32_M8_MASK
Definition riscv/opcodes.hpp:6659
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VW_SE_M1
@ PseudoVC_FPR32VW_SE_M1
Definition riscv/opcodes.hpp:1101
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF2_MASK
@ PseudoVCLMULH_VX_MF2_MASK
Definition riscv/opcodes.hpp:967
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E16_MASK
@ PseudoVFWREDUSUM_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:3950
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M1_MASK
@ PseudoVNCLIPU_WI_M1_MASK
Definition riscv/opcodes.hpp:7427
LIEF::assembly::riscv::OPCODE::VFNCVT_F_XU_W
@ VFNCVT_F_XU_W
Definition riscv/opcodes.hpp:13236
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M1
@ PseudoVSUXSEG4EI32_V_M2_M1
Definition riscv/opcodes.hpp:10941
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M4_E16_MASK
@ PseudoVFNMSUB_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2800
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M8_MASK
@ PseudoVANDN_VV_M8_MASK
Definition riscv/opcodes.hpp:797
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF4_E16
@ PseudoVFRSQRT7_V_MF4_E16
Definition riscv/opcodes.hpp:3089
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_MF2
@ PseudoVFSLIDE1DOWN_VFPR32_MF2
Definition riscv/opcodes.hpp:3321
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_M1_MASK
@ PseudoVSUXSEG4EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10954
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF4_MASK
@ PseudoVLUXSEG8EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:6367
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF2
@ PseudoVBREV_V_MF2
Definition riscv/opcodes.hpp:938
LIEF::assembly::riscv::OPCODE::TH_SRW
@ TH_SRW
Definition riscv/opcodes.hpp:13115
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E32_MASK
@ PseudoVFADD_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:1632
LIEF::assembly::riscv::OPCODE::AMOMAX_B_AQ
@ AMOMAX_B_AQ
Definition riscv/opcodes.hpp:12020
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_M1
@ PseudoVSUXSEG5EI8_V_MF8_M1
Definition riscv/opcodes.hpp:11087
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M1_E64
@ PseudoVFRDIV_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2897
LIEF::assembly::riscv::OPCODE::PseudoCCSRAW
@ PseudoCCSRAW
Definition riscv/opcodes.hpp:359
LIEF::assembly::riscv::OPCODE::VMADC_VI
@ VMADC_VI
Definition riscv/opcodes.hpp:13486
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E32
@ PseudoVFREDUSUM_VS_M4_E32
Definition riscv/opcodes.hpp:3039
LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_D
@ PseudoQuietFLT_D
Definition riscv/opcodes.hpp:425
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M8
@ PseudoVMFGT_VFPR16_M8
Definition riscv/opcodes.hpp:6676
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF2
@ PseudoVWSUBU_WX_MF2
Definition riscv/opcodes.hpp:11773
LIEF::assembly::riscv::OPCODE::PseudoCCSLLI
@ PseudoCCSLLI
Definition riscv/opcodes.hpp:353
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E16_MASK
@ PseudoVFMSAC_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:2229
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M4
@ PseudoVSBC_VVM_M4
Definition riscv/opcodes.hpp:8690
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E16
@ PseudoVDIVU_VV_M4_E16
Definition riscv/opcodes.hpp:1439
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M2
@ PseudoVMADC_VIM_M2
Definition riscv/opcodes.hpp:6431
LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_4x8x4_M4
@ PseudoVQMACCU_4x8x4_M4
Definition riscv/opcodes.hpp:7690
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E32
@ PseudoVFNMSUB_VV_M1_E32
Definition riscv/opcodes.hpp:2827
LIEF::assembly::riscv::OPCODE::TH_LHIA
@ TH_LHIA
Definition riscv/opcodes.hpp:13068
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF8
@ PseudoVSLIDE1DOWN_VX_MF8
Definition riscv/opcodes.hpp:8806
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M1
@ PseudoVLUXSEG4EI8_V_MF2_M1
Definition riscv/opcodes.hpp:6060
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_M1_MASK
@ PseudoVLSSEG7E8_V_M1_MASK
Definition riscv/opcodes.hpp:5543
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF2
@ PseudoVASUBU_VV_MF2
Definition riscv/opcodes.hpp:868
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF2
@ PseudoVLOXSEG3EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:4486
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF2
@ PseudoVLUXSEG3EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:5960
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF2_MASK
@ PseudoVSUXSEG2EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10732
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF8_MASK
@ PseudoVSSSEG2E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10282
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF8
@ PseudoVMULHU_VX_MF8
Definition riscv/opcodes.hpp:7331
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M2
@ PseudoVSUXSEG2EI16_V_MF2_M2
Definition riscv/opcodes.hpp:10681
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M4_MASK
@ PseudoVWSUB_VV_M4_MASK
Definition riscv/opcodes.hpp:11784
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E64_MASK
@ PseudoVFNMSUB_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:2842
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_M1_MASK
@ PseudoVLOXSEG8EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4963
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M1
@ PseudoVAADD_VX_M1
Definition riscv/opcodes.hpp:563
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E16
@ PseudoVFNMSAC_VV_M4_E16
Definition riscv/opcodes.hpp:2777
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M2
@ PseudoVSUXSEG3EI8_V_MF2_M2
Definition riscv/opcodes.hpp:10885
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF2_E16_MASK
@ PseudoVFSUB_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3400
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF2_MASK
@ PseudoVROL_VX_MF2_MASK
Definition riscv/opcodes.hpp:8529
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E8
@ PseudoVREDOR_VS_M1_E8
Definition riscv/opcodes.hpp:7926
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M1_E64_MASK
@ PseudoVFRDIV_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2898
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF2_MASK
@ PseudoVASUBU_VX_MF2_MASK
Definition riscv/opcodes.hpp:883
LIEF::assembly::riscv::OPCODE::CV_CMPLE_SCI_B
@ CV_CMPLE_SCI_B
Definition riscv/opcodes.hpp:12249
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF2_MASK
@ PseudoVLOXSEG3EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:4575
LIEF::assembly::riscv::OPCODE::AMOMAXU_W
@ AMOMAXU_W
Definition riscv/opcodes.hpp:12015
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M1_MASK
@ PseudoVSUXSEG2EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10660
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF2_MASK
@ PseudoVMULHSU_VV_MF2_MASK
Definition riscv/opcodes.hpp:7286
LIEF::assembly::riscv::OPCODE::AMOADD_H
@ AMOADD_H
Definition riscv/opcodes.hpp:11955
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E8
@ PseudoVREDOR_VS_M4_E8
Definition riscv/opcodes.hpp:7942
LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_S
@ PseudoQuietFLE_S
Definition riscv/opcodes.hpp:423
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF8
@ PseudoVSUXSEG5EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:11093
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF4_MASK
@ PseudoVLUXSEG5EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:6107
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M2
@ PseudoVMFLT_VFPR64_M2
Definition riscv/opcodes.hpp:6766
LIEF::assembly::riscv::OPCODE::VSOXSEG5EI16_V
@ VSOXSEG5EI16_V
Definition riscv/opcodes.hpp:13676
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M4_M1_MASK
@ PseudoVSOXSEG6EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9622
LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SCI_B
@ CV_CMPLTU_SCI_B
Definition riscv/opcodes.hpp:12255
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M2
@ PseudoVRGATHEREI16_VV_M1_E8_M2
Definition riscv/opcodes.hpp:8300
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M2_MASK
@ PseudoVRGATHER_VX_M2_MASK
Definition riscv/opcodes.hpp:8495
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E16
@ PseudoVFSGNJX_VV_M2_E16
Definition riscv/opcodes.hpp:3217
LIEF::assembly::riscv::OPCODE::C_ZEXT_B
@ C_ZEXT_B
Definition riscv/opcodes.hpp:12548
LIEF::assembly::riscv::OPCODE::G_INSERT_SUBVECTOR
@ G_INSERT_SUBVECTOR
Definition riscv/opcodes.hpp:248
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF4_E16
@ PseudoVFCVT_F_XU_V_MF4_E16
Definition riscv/opcodes.hpp:1699
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M2_MASK
@ PseudoVSUXSEG2EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10762
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M8
@ PseudoVSOXEI8_V_M2_M8
Definition riscv/opcodes.hpp:9123
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_MF4
@ PseudoVAESEF_VS_M1_MF4
Definition riscv/opcodes.hpp:700
LIEF::assembly::riscv::OPCODE::PseudoCCSLLIW
@ PseudoCCSLLIW
Definition riscv/opcodes.hpp:354
LIEF::assembly::riscv::OPCODE::SHA512SIG0
@ SHA512SIG0
Definition riscv/opcodes.hpp:12969
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_M1
@ PseudoVAESEF_VS_M8_M1
Definition riscv/opcodes.hpp:713
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E16
@ PseudoVREDMINU_VS_MF4_E16
Definition riscv/opcodes.hpp:7870
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M2_MASK
@ PseudoVLOXEI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4269
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E64
@ PseudoVFREDMAX_VS_M1_E64
Definition riscv/opcodes.hpp:2939
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M1
@ PseudoTHVdotVMAQASU_VV_M1
Definition riscv/opcodes.hpp:450
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF8_MASK
@ PseudoVSOXSEG5EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:9550
LIEF::assembly::riscv::OPCODE::VL4RE32_V
@ VL4RE32_V
Definition riscv/opcodes.hpp:13316
LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_MF4
@ PseudoVMXOR_MM_MF4
Definition riscv/opcodes.hpp:7424
LIEF::assembly::riscv::OPCODE::PREALLOCATED_ARG
@ PREALLOCATED_ARG
Definition riscv/opcodes.hpp:54
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M1
@ PseudoVWMUL_VV_M1
Definition riscv/opcodes.hpp:11587
LIEF::assembly::riscv::OPCODE::FMSUB_H_INX
@ FMSUB_H_INX
Definition riscv/opcodes.hpp:12717
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_M1_MASK
@ PseudoVLOXSEG8EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4931
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_M1
@ PseudoVSUXSEG8EI64_V_M4_M1
Definition riscv/opcodes.hpp:11309
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M2
@ PseudoVLSE16_V_M2
Definition riscv/opcodes.hpp:5012
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M8_MASK
@ PseudoVSUXEI8_V_M1_M8_MASK
Definition riscv/opcodes.hpp:10622
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E16
@ PseudoVFMSUB_VV_M1_E16
Definition riscv/opcodes.hpp:2282
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M2_MASK
@ PseudoVSUXSEG2EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10766
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF8
@ PseudoVWMUL_VX_MF8
Definition riscv/opcodes.hpp:11609
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M8
@ PseudoVNMSAC_VX_M8
Definition riscv/opcodes.hpp:7518
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF4
@ PseudoVFWCVT_X_F_V_MF4
Definition riscv/opcodes.hpp:3695
LIEF::assembly::riscv::OPCODE::VC_X
@ VC_X
Definition riscv/opcodes.hpp:13196
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF4_E16_MASK
@ PseudoVFSGNJN_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3180
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF8
@ PseudoVLUXEI64_V_M1_MF8
Definition riscv/opcodes.hpp:5656
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF4_MASK
@ PseudoVCLMUL_VV_MF4_MASK
Definition riscv/opcodes.hpp:983
LIEF::assembly::riscv::OPCODE::SHA512SIG0H
@ SHA512SIG0H
Definition riscv/opcodes.hpp:12970
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF4_E16_MASK
@ PseudoVFNMSAC_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:2794
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E16_MASK
@ PseudoVFREC7_V_M1_E16_MASK
Definition riscv/opcodes.hpp:2906
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E32_MASK
@ PseudoVWREDSUM_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:11656
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF2
@ PseudoVLOXEI32_V_MF2_MF2
Definition riscv/opcodes.hpp:4252
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M4
@ PseudoVLOXEI16_V_M2_M4
Definition riscv/opcodes.hpp:4190
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF4
@ PseudoVLSEG7E16_V_MF4
Definition riscv/opcodes.hpp:5328
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR64_S_M1
@ PseudoVFMV_FPR64_S_M1
Definition riscv/opcodes.hpp:2383
LIEF::assembly::riscv::OPCODE::G_SET_FPENV
@ G_SET_FPENV
Definition riscv/opcodes.hpp:231
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M8
@ PseudoVMSLEU_VX_M8
Definition riscv/opcodes.hpp:7113
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M8_MASK
@ PseudoVLUXEI32_V_M8_M8_MASK
Definition riscv/opcodes.hpp:5641
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M4_E32_MASK
@ PseudoVFWMUL_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3818
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF8_MASK
@ PseudoVSSUBU_VV_MF8_MASK
Definition riscv/opcodes.hpp:10432
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M1
@ PseudoVMFEQ_VFPR32_M1
Definition riscv/opcodes.hpp:6610
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF2_MASK
@ PseudoVLSE8_V_MF2_MASK
Definition riscv/opcodes.hpp:5049
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M4_E32
@ PseudoVFMSUB_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2268
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M2
@ PseudoVMSGTU_VX_M2
Definition riscv/opcodes.hpp:7025
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF2_MASK
@ PseudoVSOXSEG6EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9606
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32_MASK_TIED
@ PseudoVFWSUB_WV_M1_E32_MASK_TIED
Definition riscv/opcodes.hpp:4015
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M1_E16
@ PseudoVFMUL_VFPR16_M1_E16
Definition riscv/opcodes.hpp:2312
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF8
@ PseudoVANDN_VX_MF8
Definition riscv/opcodes.hpp:816
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E8
@ PseudoVREMU_VV_M1_E8
Definition riscv/opcodes.hpp:8090
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF2_MASK
@ PseudoVLUXSEG4EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:6041
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M1_MASK
@ PseudoVWADDU_VV_M1_MASK
Definition riscv/opcodes.hpp:11336
LIEF::assembly::riscv::OPCODE::VLSEG5E64FF_V
@ VLSEG5E64FF_V
Definition riscv/opcodes.hpp:13396
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M1
@ PseudoVLOXSEG4EI32_V_M2_M1
Definition riscv/opcodes.hpp:4616
LIEF::assembly::riscv::OPCODE::VMSLT_VX
@ VMSLT_VX
Definition riscv/opcodes.hpp:13543
LIEF::assembly::riscv::OPCODE::PseudoMaskedCmpXchg32
@ PseudoMaskedCmpXchg32
Definition riscv/opcodes.hpp:415
LIEF::assembly::riscv::OPCODE::VMFLT_VV
@ VMFLT_VV
Definition riscv/opcodes.hpp:13510
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E16_MASK
@ PseudoVREMU_VX_M2_E16_MASK
Definition riscv/opcodes.hpp:8137
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_MF2
@ PseudoVLSEG2E32FF_V_MF2
Definition riscv/opcodes.hpp:5080
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E32
@ PseudoVRGATHER_VV_M2_E32
Definition riscv/opcodes.hpp:8458
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF8_E8_MASK
@ PseudoVREDOR_VS_MF8_E8_MASK
Definition riscv/opcodes.hpp:7963
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E32_MASK
@ PseudoVREMU_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:8111
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M1_MASK
@ PseudoVLUXSEG4EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6061
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E32
@ PseudoVREDMINU_VS_MF2_E32
Definition riscv/opcodes.hpp:7866
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M2
@ PseudoVSOXEI8_V_M2_M2
Definition riscv/opcodes.hpp:9119
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M1_MASK
@ PseudoVROR_VX_M1_MASK
Definition riscv/opcodes.hpp:8563
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF8
@ PseudoVSSRL_VX_MF8
Definition riscv/opcodes.hpp:10245
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M4
@ PseudoVSOXEI8_V_M4_M4
Definition riscv/opcodes.hpp:9125
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E32_MASK
@ PseudoVWREDSUMU_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:11626
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E16_MASK
@ PseudoVWREDSUMU_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:11636
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M2_E32
@ PseudoVFNMADD_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2689
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF2_MASK
@ PseudoVLOXSEG6EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4779
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF2_MASK
@ PseudoVLUXSEG8EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:6391
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E32_MASK
@ PseudoVFWNMSAC_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3908
LIEF::assembly::riscv::OPCODE::SLLI_UW
@ SLLI_UW
Definition riscv/opcodes.hpp:12985
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M1_MASK
@ PseudoVLUXSEG4EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6009
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M1_E32_MASK
@ PseudoVFMSUB_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2265
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E64
@ PseudoVREDSUM_VS_M2_E64
Definition riscv/opcodes.hpp:7976
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF4
@ PseudoVAND_VI_MF4
Definition riscv/opcodes.hpp:828
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M1_MASK
@ PseudoTHVdotVMAQASU_VX_M1_MASK
Definition riscv/opcodes.hpp:461
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M2_M1
@ PseudoVSOXSEG5EI16_V_M2_M1
Definition riscv/opcodes.hpp:9515
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M2
@ PseudoVSSEG4E8_V_M2
Definition riscv/opcodes.hpp:10075
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF4
@ PseudoVNMSAC_VV_MF4
Definition riscv/opcodes.hpp:7508
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF8
@ PseudoVMIN_VV_MF8
Definition riscv/opcodes.hpp:6866
LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B4
@ PseudoVMCLR_M_B4
Definition riscv/opcodes.hpp:6574
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF8
@ PseudoVLOXSEG8EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:4968
LIEF::assembly::riscv::OPCODE::VLOXSEG2EI64_V
@ VLOXSEG2EI64_V
Definition riscv/opcodes.hpp:13338
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M1
@ PseudoVMSBC_VX_M1
Definition riscv/opcodes.hpp:6931
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF2_MASK
@ PseudoVLUXSEG6EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6205
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF2_MASK
@ PseudoVLSEG4E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5233
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M8_E64
@ PseudoVFNMACC_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2643
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M2_MASK
@ PseudoVMAXU_VV_M2_MASK
Definition riscv/opcodes.hpp:6517
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E64_MASK
@ PseudoVFCVT_F_X_V_M8_E64_MASK
Definition riscv/opcodes.hpp:1724
LIEF::assembly::riscv::OPCODE::TH_ADDSL
@ TH_ADDSL
Definition riscv/opcodes.hpp:13027
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M1_MASK
@ PseudoVMFLE_VFPR32_M1_MASK
Definition riscv/opcodes.hpp:6713
LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_MF2
@ PseudoVMXOR_MM_MF2
Definition riscv/opcodes.hpp:7423
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_M1_MASK
@ PseudoVLOXSEG6EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4825
LIEF::assembly::riscv::OPCODE::CV_ADDRN
@ CV_ADDRN
Definition riscv/opcodes.hpp:12166
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E16
@ PseudoVFWREDOSUM_VS_M8_E16
Definition riscv/opcodes.hpp:3923
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF4
@ PseudoVMSEQ_VV_MF4
Definition riscv/opcodes.hpp:6976
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_MF2_MASK
@ PseudoVLUXSEG4EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:5977
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E64
@ PseudoVREDMAXU_VS_M8_E64
Definition riscv/opcodes.hpp:7772
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK
@ PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK
Definition riscv/opcodes.hpp:8287
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF8_E8_MASK
@ PseudoVREMU_VX_MF8_E8_MASK
Definition riscv/opcodes.hpp:8171
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E32_MASK
@ PseudoVFWREDOSUM_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:3926
LIEF::assembly::riscv::OPCODE::MULW
@ MULW
Definition riscv/opcodes.hpp:12905
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_M1
@ PseudoVSUXSEG7EI16_V_MF4_M1
Definition riscv/opcodes.hpp:11187
LIEF::assembly::riscv::OPCODE::VADC_VXM
@ VADC_VXM
Definition riscv/opcodes.hpp:13137
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF8
@ PseudoVLSEG8E8FF_V_MF8
Definition riscv/opcodes.hpp:5388
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E16
@ PseudoVFCVT_F_X_V_MF2_E16
Definition riscv/opcodes.hpp:1725
LIEF::assembly::riscv::OPCODE::FMIN_D_INX
@ FMIN_D_INX
Definition riscv/opcodes.hpp:12708
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_MF2
@ PseudoVLUXSEG6EI32_V_M2_MF2
Definition riscv/opcodes.hpp:6190
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E16
@ PseudoVFWCVT_F_X_V_M4_E16
Definition riscv/opcodes.hpp:3619
LIEF::assembly::riscv::OPCODE::FCVT_H_W
@ FCVT_H_W
Definition riscv/opcodes.hpp:12599
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E16
@ PseudoVFREC7_V_M2_E16
Definition riscv/opcodes.hpp:2911
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF2_MASK
@ PseudoVSOXEI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9030
LIEF::assembly::riscv::OPCODE::AMOMINU_D_RL
@ AMOMINU_D_RL
Definition riscv/opcodes.hpp:12042
LIEF::assembly::riscv::OPCODE::VFNRCLIP_X_F_QF
@ VFNRCLIP_X_F_QF
Definition riscv/opcodes.hpp:13252
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_M1
@ PseudoVLOXEI32_V_MF2_M1
Definition riscv/opcodes.hpp:4250
LIEF::assembly::riscv::OPCODE::PATCHABLE_OP
@ PATCHABLE_OP
Definition riscv/opcodes.hpp:58
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF2_MASK
@ PseudoVWADDU_VV_MF2_MASK
Definition riscv/opcodes.hpp:11342
LIEF::assembly::riscv::OPCODE::AMOADD_D_AQ
@ AMOADD_D_AQ
Definition riscv/opcodes.hpp:11952
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M1_E64_MASK
@ PseudoVFSUB_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:3414
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF2
@ PseudoVSUXSEG3EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:10845
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_M1
@ PseudoVLOXSEG4EI16_V_MF4_M1
Definition riscv/opcodes.hpp:4600
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E64_V_M1
@ PseudoVSSEG6E64_V_M1
Definition riscv/opcodes.hpp:10113
LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SCI_H
@ CV_CMPLTU_SCI_H
Definition riscv/opcodes.hpp:12256
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M2_MASK
@ PseudoVMFNE_VFPR64_M2_MASK
Definition riscv/opcodes.hpp:6809
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF4_E16
@ PseudoVFSGNJ_VV_MF4_E16
Definition riscv/opcodes.hpp:3299
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M2_E16
@ PseudoVFWADD_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3453
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF2
@ PseudoVLUXSEG5EI32_V_M1_MF2
Definition riscv/opcodes.hpp:6104
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M2_MASK
@ PseudoVWMACC_VV_M2_MASK
Definition riscv/opcodes.hpp:11518
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF8_MASK
@ PseudoVMSNE_VI_MF8_MASK
Definition riscv/opcodes.hpp:7234
LIEF::assembly::riscv::OPCODE::MOPRR1
@ MOPRR1
Definition riscv/opcodes.hpp:12893
LIEF::assembly::riscv::OPCODE::FSUB_H
@ FSUB_H
Definition riscv/opcodes.hpp:12789
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M8_MASK
@ PseudoVMSNE_VV_M8_MASK
Definition riscv/opcodes.hpp:7242
LIEF::assembly::riscv::OPCODE::PseudoVQMACC_2x8x2_M4
@ PseudoVQMACC_2x8x2_M4
Definition riscv/opcodes.hpp:7694
LIEF::assembly::riscv::OPCODE::SD
@ SD
Definition riscv/opcodes.hpp:12947
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_MF8
@ PseudoVC_V_XV_MF8
Definition riscv/opcodes.hpp:1374
LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_4x8x4_M1
@ PseudoVQMACCUS_4x8x4_M1
Definition riscv/opcodes.hpp:7680
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF2
@ PseudoVSOXSEG3EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:9341
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E16
@ PseudoVREDOR_VS_M4_E16
Definition riscv/opcodes.hpp:7936
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M2_MASK
@ PseudoVSUXSEG3EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:10886
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF4
@ PseudoVSSEG6E16_V_MF4
Definition riscv/opcodes.hpp:10107
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8_TIED
@ PseudoVWSUBU_WV_MF8_TIED
Definition riscv/opcodes.hpp:11766
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_MF2
@ PseudoVSOXSEG7EI64_V_M4_MF2
Definition riscv/opcodes.hpp:9727
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF4
@ PseudoVWSUB_VV_MF4
Definition riscv/opcodes.hpp:11787
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M1_MASK
@ PseudoVFCVT_X_F_V_M1_MASK
Definition riscv/opcodes.hpp:1852
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF4
@ PseudoVSOXSEG2EI64_V_M1_MF4
Definition riscv/opcodes.hpp:9229
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M8
@ PseudoVSUXEI16_V_M8_M8
Definition riscv/opcodes.hpp:10527
LIEF::assembly::riscv::OPCODE::ANDI
@ ANDI
Definition riscv/opcodes.hpp:12116
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF2
@ PseudoVSOXSEG6EI64_V_M2_MF2
Definition riscv/opcodes.hpp:9641
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M2_MASK
@ PseudoVADD_VV_M2_MASK
Definition riscv/opcodes.hpp:615
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_M4
@ PseudoVC_V_VVW_M4
Definition riscv/opcodes.hpp:1318
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M1
@ PseudoVSUXSEG2EI16_V_M1_M1
Definition riscv/opcodes.hpp:10659
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF2_MASK
@ PseudoVFCVT_X_F_V_MF2_MASK
Definition riscv/opcodes.hpp:1860
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF2
@ PseudoVLUXSEG8EI64_V_M2_MF2
Definition riscv/opcodes.hpp:6372
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M2_MASK
@ PseudoVLOXSEG2EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:4393
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M2
@ PseudoVSOXSEG3EI8_V_MF2_M2
Definition riscv/opcodes.hpp:9381
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E32
@ PseudoVREM_VX_M4_E32
Definition riscv/opcodes.hpp:8234
LIEF::assembly::riscv::OPCODE::PseudoTAILIndirectNonX7
@ PseudoTAILIndirectNonX7
Definition riscv/opcodes.hpp:449
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E64_MASK
@ PseudoVFMACC_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:1978
LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_4x8x4_M2
@ PseudoVQMACCSU_4x8x4_M2
Definition riscv/opcodes.hpp:7673
LIEF::assembly::riscv::OPCODE::PseudoVQMACC_4x8x4_M1
@ PseudoVQMACC_4x8x4_M1
Definition riscv/opcodes.hpp:7696
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF2_E16
@ PseudoVFMIN_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2140
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E16
@ PseudoVFMSAC_VV_M4_E16
Definition riscv/opcodes.hpp:2234
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF4_MASK
@ PseudoVSSEG2E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10024
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M1
@ PseudoVIOTA_M_M1
Definition riscv/opcodes.hpp:4069
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M1_MASK
@ PseudoVSOXSEG4EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9438
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF4_MASK
@ PseudoVNCLIP_WV_MF4_MASK
Definition riscv/opcodes.hpp:7483
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF2
@ PseudoVLUXEI16_V_MF4_MF2
Definition riscv/opcodes.hpp:5606
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M8
@ PseudoVSADD_VX_M8
Definition riscv/opcodes.hpp:8680
LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_MF2
@ PseudoVC_I_SE_MF2
Definition riscv/opcodes.hpp:1143
LIEF::assembly::riscv::OPCODE::KILL
@ KILL
Definition riscv/opcodes.hpp:31
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF2
@ PseudoVLOXSEG7EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:4918
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF4
@ PseudoVFNCVT_RM_X_F_W_MF4
Definition riscv/opcodes.hpp:2545
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E16
@ PseudoVFSGNJ_VV_M8_E16
Definition riscv/opcodes.hpp:3289
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M8_M4_MASK
@ PseudoVLOXSEG2EI16_V_M8_M4_MASK
Definition riscv/opcodes.hpp:4353
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E32_MASK
@ PseudoVREM_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:8183
LIEF::assembly::riscv::OPCODE::TH_LBIB
@ TH_LBIB
Definition riscv/opcodes.hpp:13062
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E16_MASK
@ PseudoVFSGNJN_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3176
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF4
@ PseudoVLSEG4E16_V_MF4
Definition riscv/opcodes.hpp:5196
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF2
@ PseudoVFCLASS_V_MF2
Definition riscv/opcodes.hpp:1667
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF4_MASK
@ PseudoVLOXSEG8EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4975
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_MF2
@ PseudoVAESZ_VS_M2_MF2
Definition riscv/opcodes.hpp:772
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M8_MASK
@ PseudoVRGATHER_VI_M8_MASK
Definition riscv/opcodes.hpp:8441
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M2_MASK
@ PseudoVSSSEG3E8_V_M2_MASK
Definition riscv/opcodes.hpp:10304
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF4
@ PseudoVLUXSEG4EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:6078
LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_MF8
@ PseudoVSPILL4_MF8
Definition riscv/opcodes.hpp:9846
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF4_E16_MASK
@ PseudoVFWSUB_WFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:4000
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4_MASK
@ PseudoVWADD_WV_MF4_MASK
Definition riscv/opcodes.hpp:11436
LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M1
@ PseudoVLE32FF_V_M1
Definition riscv/opcodes.hpp:4107
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M1
@ PseudoVLSEG3E8FF_V_M1
Definition riscv/opcodes.hpp:5162
LIEF::assembly::riscv::OPCODE::VLSEG7E8_V
@ VLSEG7E8_V
Definition riscv/opcodes.hpp:13415
LIEF::assembly::riscv::OPCODE::C_NOP_HINT
@ C_NOP_HINT
Definition riscv/opcodes.hpp:12524
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF2
@ PseudoVSRA_VX_MF2
Definition riscv/opcodes.hpp:9899
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF4
@ PseudoVSEXT_VF2_MF4
Definition riscv/opcodes.hpp:8759
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M4_MASK
@ PseudoVRGATHEREI16_VV_M2_E16_M4_MASK
Definition riscv/opcodes.hpp:8311
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E32_MASK
@ PseudoVFCVT_RM_F_X_V_M4_E32_MASK
Definition riscv/opcodes.hpp:1776
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF4
@ PseudoVLUXEI16_V_MF2_MF4
Definition riscv/opcodes.hpp:5602
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M4_MASK
@ PseudoVWMUL_VV_M4_MASK
Definition riscv/opcodes.hpp:11592
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_MF2_MF8
@ PseudoVAESDF_VS_MF2_MF8
Definition riscv/opcodes.hpp:663
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF4_MASK
@ PseudoVSSSEG5E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10356
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF4_E16_MASK
@ PseudoVFSGNJ_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3252
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M8_MASK
@ PseudoVAADDU_VV_M8_MASK
Definition riscv/opcodes.hpp:528
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E16_MASK
@ PseudoVFMSUB_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:2301
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF8_MASK
@ PseudoVSUXSEG8EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:11294
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M2
@ PseudoVRGATHEREI16_VV_M1_E64_M2
Definition riscv/opcodes.hpp:8292
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M2
@ PseudoVSSSEG4E16_V_M2
Definition riscv/opcodes.hpp:10313
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M2_MASK
@ PseudoVRGATHEREI16_VV_M2_E32_M2_MASK
Definition riscv/opcodes.hpp:8317
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E16_MASK
@ PseudoVFWADD_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3470
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M4
@ PseudoVSOXEI32_V_M2_M4
Definition riscv/opcodes.hpp:9053
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E8
@ PseudoVCOMPRESS_VM_M2_E8
Definition riscv/opcodes.hpp:1021
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M1
@ PseudoVLSEG2E32_V_M1
Definition riscv/opcodes.hpp:5082
LIEF::assembly::riscv::OPCODE::WriteVXRMImm
@ WriteVXRMImm
Definition riscv/opcodes.hpp:11930
LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_MF8
@ PseudoVSPILL2_MF8
Definition riscv/opcodes.hpp:9836
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M1_MASK
@ PseudoVMSGTU_VX_M1_MASK
Definition riscv/opcodes.hpp:7024
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF2
@ PseudoVLOXSEG5EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:4698
LIEF::assembly::riscv::OPCODE::CZERO_NEZ
@ CZERO_NEZ
Definition riscv/opcodes.hpp:12474
LIEF::assembly::riscv::OPCODE::TH_TSTNBZ
@ TH_TSTNBZ
Definition riscv/opcodes.hpp:13128
LIEF::assembly::riscv::OPCODE::AMOSWAP_D_AQ
@ AMOSWAP_D_AQ
Definition riscv/opcodes.hpp:12088
LIEF::assembly::riscv::OPCODE::VSSUBU_VX
@ VSSUBU_VX
Definition riscv/opcodes.hpp:13765
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M2
@ PseudoVSUXSEG3EI32_V_M1_M2
Definition riscv/opcodes.hpp:10825
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_M1_MASK
@ PseudoVLSSEG5E32_V_M1_MASK
Definition riscv/opcodes.hpp:5497
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF8_MASK
@ PseudoVNSRL_WV_MF8_MASK
Definition riscv/opcodes.hpp:7613
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E64
@ PseudoVFMUL_VV_M4_E64
Definition riscv/opcodes.hpp:2358
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_M1_MASK
@ PseudoVLSEG6E32FF_V_M1_MASK
Definition riscv/opcodes.hpp:5291
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32_MASK_TIED
@ PseudoVFWADD_WV_M1_E32_MASK_TIED
Definition riscv/opcodes.hpp:3511
LIEF::assembly::riscv::OPCODE::C_SLLI
@ C_SLLI
Definition riscv/opcodes.hpp:12533
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M8
@ PseudoVMFGE_VFPR16_M8
Definition riscv/opcodes.hpp:6646
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E32_MASK
@ PseudoVREDSUM_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:7975
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M2
@ PseudoVSOXSEG2EI16_V_MF2_M2
Definition riscv/opcodes.hpp:9177
LIEF::assembly::riscv::OPCODE::TH_EXTU
@ TH_EXTU
Definition riscv/opcodes.hpp:13043
LIEF::assembly::riscv::OPCODE::VMSEQ_VI
@ VMSEQ_VI
Definition riscv/opcodes.hpp:13526
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M4_MASK
@ PseudoVSOXSEG2EI16_V_M4_M4_MASK
Definition riscv/opcodes.hpp:9172
LIEF::assembly::riscv::OPCODE::G_INTRINSIC_W_SIDE_EFFECTS
@ G_INTRINSIC_W_SIDE_EFFECTS
Definition riscv/opcodes.hpp:146
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E32_MASK
@ PseudoVREMU_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:8087
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF2
@ PseudoVLSSEG7E8_V_MF2
Definition riscv/opcodes.hpp:5544
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_M4
@ PseudoVC_V_FPR32VV_M4
Definition riscv/opcodes.hpp:1204
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E8
@ PseudoVREDSUM_VS_MF4_E8
Definition riscv/opcodes.hpp:8004
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E32
@ PseudoVFWSUB_VV_M4_E32
Definition riscv/opcodes.hpp:3983
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF8_MASK
@ PseudoVLOXSEG8EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:4977
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E8_MASK
@ PseudoVREDMAX_VS_MF2_E8_MASK
Definition riscv/opcodes.hpp:7825
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF2
@ PseudoVSUXSEG3EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:10899
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF2_MASK
@ PseudoVROL_VV_MF2_MASK
Definition riscv/opcodes.hpp:8515
LIEF::assembly::riscv::OPCODE::CV_LBU_ri_inc
@ CV_LBU_ri_inc
Definition riscv/opcodes.hpp:12318
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF2_MASK
@ PseudoVLUXSEG3EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:5967
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M4_MASK
@ PseudoVZEXT_VF8_M4_MASK
Definition riscv/opcodes.hpp:11908
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M2
@ PseudoVLOXSEG3EI32_V_M2_M2
Definition riscv/opcodes.hpp:4508
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E8
@ PseudoVREDMINU_VS_MF4_E8
Definition riscv/opcodes.hpp:7872
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF8
@ PseudoVIOTA_M_MF8
Definition riscv/opcodes.hpp:4081
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E16
@ PseudoVFNCVT_F_XU_W_MF2_E16
Definition riscv/opcodes.hpp:2465
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF8_MASK
@ PseudoVLUXEI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:5657
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B8
@ PseudoVMSBF_M_B8
Definition riscv/opcodes.hpp:6950
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_MF2_MASK
@ PseudoVSOXSEG5EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9576
LIEF::assembly::riscv::OPCODE::CV_XOR_SCI_B
@ CV_XOR_SCI_B
Definition riscv/opcodes.hpp:12469
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_M1_MASK
@ PseudoVLUXSEG5EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6131
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF2_MASK
@ PseudoVSOXSEG5EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9554
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF2
@ PseudoVMAX_VV_MF2
Definition riscv/opcodes.hpp:6550
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF4
@ PseudoVSUXSEG4EI64_V_M2_MF4
Definition riscv/opcodes.hpp:10975
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M1
@ PseudoVRGATHER_VI_M1
Definition riscv/opcodes.hpp:8434
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M2_MASK
@ PseudoVLOXSEG4EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4583
LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M4
@ PseudoVSSE64_V_M4
Definition riscv/opcodes.hpp:9973
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M1
@ PseudoVLOXSEG4EI64_V_M4_M1
Definition riscv/opcodes.hpp:4652
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E8
@ PseudoVREDXOR_VS_MF4_E8
Definition riscv/opcodes.hpp:8048
LIEF::assembly::riscv::OPCODE::MOPR11
@ MOPR11
Definition riscv/opcodes.hpp:12863
LIEF::assembly::riscv::OPCODE::VLSEG4E32FF_V
@ VLSEG4E32FF_V
Definition riscv/opcodes.hpp:13386
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M2
@ PseudoVNCLIP_WX_M2
Definition riscv/opcodes.hpp:7488
LIEF::assembly::riscv::OPCODE::PseudoCCSUB
@ PseudoCCSUB
Definition riscv/opcodes.hpp:364
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M1
@ PseudoVSOXSEG3EI64_V_M2_M1
Definition riscv/opcodes.hpp:9355
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_MF2
@ PseudoVLSSEG3E32_V_MF2
Definition riscv/opcodes.hpp:5446
LIEF::assembly::riscv::OPCODE::G_STRICT_FLDEXP
@ G_STRICT_FLDEXP
Definition riscv/opcodes.hpp:289
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E32_MASK
@ PseudoVFRSQRT7_V_M8_E32_MASK
Definition riscv/opcodes.hpp:3082
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M2
@ PseudoVSUXSEG2EI8_V_MF4_M2
Definition riscv/opcodes.hpp:10781
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF2
@ PseudoVSUXSEG2EI32_V_M1_MF2
Definition riscv/opcodes.hpp:10699
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF2
@ PseudoVSSSEG3E8_V_MF2
Definition riscv/opcodes.hpp:10305
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M2
@ PseudoVMSEQ_VI_M2
Definition riscv/opcodes.hpp:6954
LIEF::assembly::riscv::OPCODE::MOPR9
@ MOPR9
Definition riscv/opcodes.hpp:12891
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M1_E16_MASK
@ PseudoVFNCVT_RM_F_X_W_M1_E16_MASK
Definition riscv/opcodes.hpp:2508
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E16_MASK
@ PseudoVFWMACC_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3762
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B2_MASK
@ PseudoVMSBF_M_B2_MASK
Definition riscv/opcodes.hpp:6943
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M1_MASK
@ PseudoVSOXSEG3EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9364
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF2_MASK
@ PseudoVSUXSEG2EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:10790
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_MF2
@ PseudoVLSEG3E32_V_MF2
Definition riscv/opcodes.hpp:5152
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF2
@ PseudoVLUXSEG6EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:6196
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M1
@ PseudoVMULHSU_VX_M1
Definition riscv/opcodes.hpp:7291
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_MF2_MF8
@ PseudoVAESEF_VS_MF2_MF8
Definition riscv/opcodes.hpp:721
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M2_E32
@ PseudoVFNMSUB_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2809
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B16_MASK
@ PseudoVMSIF_M_B16_MASK
Definition riscv/opcodes.hpp:7067
LIEF::assembly::riscv::OPCODE::CV_SUB_SCI_B
@ CV_SUB_SCI_B
Definition riscv/opcodes.hpp:12460
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF2
@ PseudoVWADDU_VX_MF2
Definition riscv/opcodes.hpp:11353
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E16_MASK
@ PseudoVREMU_VX_M8_E16_MASK
Definition riscv/opcodes.hpp:8153
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E8_MASK
@ PseudoVDIVU_VV_M1_E8_MASK
Definition riscv/opcodes.hpp:1430
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E64
@ PseudoVFMAX_VV_M1_E64
Definition riscv/opcodes.hpp:2091
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E16_MASK
@ PseudoVWREDSUMU_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:11618
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E64
@ PseudoVFMADD_VV_M1_E64
Definition riscv/opcodes.hpp:2031
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_MF2
@ PseudoVLSEG5E32FF_V_MF2
Definition riscv/opcodes.hpp:5252
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF2_MASK
@ PseudoVSOXSEG2EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:9286
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E32_MASK
@ PseudoVFCVT_F_XU_V_M4_E32_MASK
Definition riscv/opcodes.hpp:1686
LIEF::assembly::riscv::OPCODE::CV_XOR_H
@ CV_XOR_H
Definition riscv/opcodes.hpp:12468
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M2
@ PseudoVLOXEI8_V_MF4_M2
Definition riscv/opcodes.hpp:4320
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M2
@ PseudoVLUXSEG4EI8_V_MF4_M2
Definition riscv/opcodes.hpp:6068
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF8_E8_MASK
@ PseudoVREDAND_VS_MF8_E8_MASK
Definition riscv/opcodes.hpp:7743
LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_M4
@ PseudoVC_XVW_SE_M4
Definition riscv/opcodes.hpp:1405
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M1_E16_MASK
@ PseudoVFMIN_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:2133
LIEF::assembly::riscv::OPCODE::VWSUB_VX
@ VWSUB_VX
Definition riscv/opcodes.hpp:13835
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M2
@ PseudoVSUXEI8_V_M2_M2
Definition riscv/opcodes.hpp:10623
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E8
@ PseudoVDIV_VV_M1_E8
Definition riscv/opcodes.hpp:1517
LIEF::assembly::riscv::OPCODE::C_OR
@ C_OR
Definition riscv/opcodes.hpp:12526
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF2_MASK
@ PseudoVSUXSEG8EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11298
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E8
@ PseudoVRGATHER_VV_M2_E8
Definition riscv/opcodes.hpp:8462
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M2_E16_MASK
@ PseudoVFWNMSAC_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3878
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E64_MASK
@ PseudoVFREDMIN_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:2976
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M2_MASK
@ PseudoVMAXU_VX_M2_MASK
Definition riscv/opcodes.hpp:6531
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E64_MASK
@ PseudoVFMACC_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:1984
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF2
@ PseudoVLOXSEG4EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:4678
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E32
@ PseudoVFMAX_VV_M1_E32
Definition riscv/opcodes.hpp:2089
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M2_E32
@ PseudoVFNCVT_RM_F_XU_W_M2_E32
Definition riscv/opcodes.hpp:2495
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF8_MASK
@ PseudoVLUXSEG7EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:6281
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF4
@ PseudoVSOXSEG4EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:9501
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E8
@ PseudoVREMU_VV_M4_E8
Definition riscv/opcodes.hpp:8106
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_M1_MASK
@ PseudoVSOXSEG6EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:9664
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E64_MASK
@ PseudoVFREDUSUM_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:3030
LIEF::assembly::riscv::OPCODE::VLSSEG7E8_V
@ VLSSEG7E8_V
Definition riscv/opcodes.hpp:13447
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_M2
@ PseudoVFMV_S_FPR16_M2
Definition riscv/opcodes.hpp:2388
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E8
@ PseudoVREMU_VX_M8_E8
Definition riscv/opcodes.hpp:8158
LIEF::assembly::riscv::OPCODE::G_ZEXTLOAD
@ G_ZEXTLOAD
Definition riscv/opcodes.hpp:115
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M1_E32_MASK
@ PseudoVFDIV_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:1876
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M8_MASK
@ PseudoVMSLT_VX_M8_MASK
Definition riscv/opcodes.hpp:7214
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M1
@ PseudoVMV_V_I_M1
Definition riscv/opcodes.hpp:7390
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF2
@ PseudoVWSUB_VV_MF2
Definition riscv/opcodes.hpp:11785
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M8_MASK
@ PseudoVASUBU_VV_M8_MASK
Definition riscv/opcodes.hpp:867
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E16_MASK
@ PseudoVWREDSUMU_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:11612
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E64_MASK
@ PseudoVFMIN_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:2185
LIEF::assembly::riscv::OPCODE::HFENCE_GVMA
@ HFENCE_GVMA
Definition riscv/opcodes.hpp:12794
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M8_E64
@ PseudoVFMAX_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2085
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M2_MASK
@ PseudoVSOXEI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9016
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M4
@ PseudoVWMACC_VX_M4
Definition riscv/opcodes.hpp:11531
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M2
@ PseudoVSUXSEG4EI64_V_M2_M2
Definition riscv/opcodes.hpp:10971
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF8_MASK
@ PseudoVSUXSEG2EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:10736
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF4_MASK
@ PseudoVSSSEG3E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10290
LIEF::assembly::riscv::OPCODE::VLOXSEG3EI16_V
@ VLOXSEG3EI16_V
Definition riscv/opcodes.hpp:13340
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M2_MASK
@ PseudoVSUXSEG4EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10980
LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_MF4
@ PseudoVC_VVV_SE_MF4
Definition riscv/opcodes.hpp:1151
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M2_MASK
@ PseudoVSSUBU_VX_M2_MASK
Definition riscv/opcodes.hpp:10436
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF4_MASK
@ PseudoVLUXSEG4EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:6079
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_M1
@ PseudoVC_V_IV_SE_M1
Definition riscv/opcodes.hpp:1281
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF2_MASK
@ PseudoVNCLIP_WI_MF2_MASK
Definition riscv/opcodes.hpp:7469
LIEF::assembly::riscv::OPCODE::Select_FPR64INX_Using_CC_GPR
@ Select_FPR64INX_Using_CC_GPR
Definition riscv/opcodes.hpp:11921
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF8_MASK
@ PseudoVSMUL_VV_MF8_MASK
Definition riscv/opcodes.hpp:8977
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M4_E32_MASK
@ PseudoVFSGNJ_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3258
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF8
@ PseudoVLUXSEG7EI64_V_M1_MF8
Definition riscv/opcodes.hpp:6288
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF8
@ PseudoVNCLIPU_WI_MF8
Definition riscv/opcodes.hpp:7436
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E16_MASK
@ PseudoVREDXOR_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:8033
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF2_MASK
@ PseudoVLSSEG6E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5513
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF2
@ PseudoVLUXSEG7EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:6310
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M8
@ PseudoVROL_VV_M8
Definition riscv/opcodes.hpp:8512
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M2_MASK
@ PseudoVLSSEG3E8_V_M2_MASK
Definition riscv/opcodes.hpp:5455
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF4
@ PseudoVSOXSEG7EI64_V_M1_MF4
Definition riscv/opcodes.hpp:9715
LIEF::assembly::riscv::OPCODE::MOPR26
@ MOPR26
Definition riscv/opcodes.hpp:12879
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF4_MASK
@ PseudoVSOXEI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9048
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M4_M2_MASK
@ PseudoVLUXSEG3EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:5873
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF8_MASK
@ PseudoVMAX_VX_MF8_MASK
Definition riscv/opcodes.hpp:6569
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E16
@ PseudoVFMSUB_VV_M2_E16
Definition riscv/opcodes.hpp:2288
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M1_MASK
@ PseudoVWMACC_VV_M1_MASK
Definition riscv/opcodes.hpp:11516
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M4
@ PseudoVSOXEI8_V_M2_M4
Definition riscv/opcodes.hpp:9121
LIEF::assembly::riscv::OPCODE::THVdotVMAQA_VX
@ THVdotVMAQA_VX
Definition riscv/opcodes.hpp:13026
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M8
@ PseudoVAESEM_VV_M8
Definition riscv/opcodes.hpp:754
LIEF::assembly::riscv::OPCODE::ANNOTATION_LABEL
@ ANNOTATION_LABEL
Definition riscv/opcodes.hpp:30
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M4_E16
@ PseudoVFWNMACC_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3843
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M4_M1_MASK
@ PseudoVLUXSEG5EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:6113
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M1_MASK
@ PseudoVSOXSEG2EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9256
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF8
@ PseudoVMULHSU_VX_MF8
Definition riscv/opcodes.hpp:7303
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF2
@ PseudoVWSLL_VV_MF2
Definition riscv/opcodes.hpp:11701
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_M1_MASK
@ PseudoVLOXSEG5EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4703
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF8
@ PseudoVNCLIP_WX_MF8
Definition riscv/opcodes.hpp:7496
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF2
@ PseudoVLOXSEG3EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:4568
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M2
@ PseudoVWMULSU_VX_M2
Definition riscv/opcodes.hpp:11553
LIEF::assembly::riscv::OPCODE::VFWMSAC_VF
@ VFWMSAC_VF
Definition riscv/opcodes.hpp:13289
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF2
@ PseudoVSUXSEG7EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:11243
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M1
@ PseudoVMERGE_VXM_M1
Definition riscv/opcodes.hpp:6591
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_MF2_MASK
@ PseudoVLOXEI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4185
LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SCI_H
@ CV_CMPGTU_SCI_H
Definition riscv/opcodes.hpp:12232
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M2_MASK
@ PseudoVAND_VX_M2_MASK
Definition riscv/opcodes.hpp:849
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF2_E16
@ PseudoVFMSAC_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2200
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M4_MASK
@ PseudoVAND_VV_M4_MASK
Definition riscv/opcodes.hpp:837
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF2
@ PseudoVNSRA_WX_MF2
Definition riscv/opcodes.hpp:7584
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M1_MASK
@ PseudoVLUXSEG3EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:5869
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF8_MASK
@ PseudoVLSSEG8E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5569
LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R_DIV4
@ CV_CPLXMUL_R_DIV4
Definition riscv/opcodes.hpp:12279
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF2
@ PseudoVLOXSEG7EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:4884
LIEF::assembly::riscv::OPCODE::PATCHABLE_RET
@ PATCHABLE_RET
Definition riscv/opcodes.hpp:60
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF4
@ PseudoVLUXEI8_V_MF8_MF4
Definition riscv/opcodes.hpp:5722
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF4
@ PseudoVLUXSEG3EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:5962
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M2_M2_MASK
@ PseudoVSOXSEG3EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9378
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF4_E16
@ PseudoVFSGNJ_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3251
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E32
@ PseudoVREDMINU_VS_M2_E32
Definition riscv/opcodes.hpp:7842
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M8_MASK
@ PseudoVSOXEI16_V_M2_M8_MASK
Definition riscv/opcodes.hpp:9014
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_M4
@ PseudoVC_V_XVV_SE_M4
Definition riscv/opcodes.hpp:1351
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_M1
@ PseudoVC_V_I_M1
Definition riscv/opcodes.hpp:1288
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E16_MASK
@ PseudoVFNMSUB_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:2850
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M2_MASK
@ PseudoVSOXSEG2EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:9278
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_M1
@ PseudoVLUXSEG5EI32_V_M1_M1
Definition riscv/opcodes.hpp:6102
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E64_MASK
@ PseudoVREMU_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:8113
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M1_E16_MASK
@ PseudoVFWMACCBF16_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3698
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M4_MASK
@ PseudoVWADD_WX_M4_MASK
Definition riscv/opcodes.hpp:11448
LIEF::assembly::riscv::OPCODE::VMIN_VV
@ VMIN_VV
Definition riscv/opcodes.hpp:13515
LIEF::assembly::riscv::OPCODE::VFMUL_VV
@ VFMUL_VV
Definition riscv/opcodes.hpp:13230
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M2
@ PseudoVSUXSEG4EI8_V_M1_M2
Definition riscv/opcodes.hpp:10989
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M2
@ PseudoVRGATHEREI16_VV_M8_E32_M2
Definition riscv/opcodes.hpp:8376
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E16_MASK
@ PseudoVFWADD_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3478
LIEF::assembly::riscv::OPCODE::CV_DOTSP_SCI_B
@ CV_DOTSP_SCI_B
Definition riscv/opcodes.hpp:12283
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF4
@ PseudoVMINU_VX_MF4
Definition riscv/opcodes.hpp:6850
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF2
@ PseudoVMFGE_VFPR16_MF2
Definition riscv/opcodes.hpp:6648
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E32_MASK
@ PseudoVFNMSUB_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:2852
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M2
@ PseudoVSOXEI16_V_M4_M2
Definition riscv/opcodes.hpp:9015
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M8
@ PseudoVMSGTU_VX_M8
Definition riscv/opcodes.hpp:7029
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E32_MASK
@ PseudoVRGATHER_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:8483
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF4
@ PseudoVLOXSEG6EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:4786
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF4
@ PseudoVLOXSEG5EI32_V_M1_MF4
Definition riscv/opcodes.hpp:4714
LIEF::assembly::riscv::OPCODE::VLSEG2E16FF_V
@ VLSEG2E16FF_V
Definition riscv/opcodes.hpp:13368
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF2
@ PseudoVCLZ_V_MF2
Definition riscv/opcodes.hpp:1008
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M2
@ PseudoVMADC_VXM_M2
Definition riscv/opcodes.hpp:6459
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF2
@ PseudoVLUXSEG7EI64_V_M2_MF2
Definition riscv/opcodes.hpp:6292
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M1
@ PseudoVLUXSEG2EI64_V_M4_M1
Definition riscv/opcodes.hpp:5812
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M1_MASK
@ PseudoVMSLEU_VV_M1_MASK
Definition riscv/opcodes.hpp:7094
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M4
@ PseudoVMFGT_VFPR32_M4
Definition riscv/opcodes.hpp:6686
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E64
@ PseudoVREDMAXU_VS_M1_E64
Definition riscv/opcodes.hpp:7748
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF4
@ PseudoVSOXSEG2EI64_V_M2_MF4
Definition riscv/opcodes.hpp:9239
LIEF::assembly::riscv::OPCODE::VMSLEU_VV
@ VMSLEU_VV
Definition riscv/opcodes.hpp:13535
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E64
@ PseudoVFSGNJ_VV_M2_E64
Definition riscv/opcodes.hpp:3281
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E32_MASK
@ PseudoVFMIN_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:2189
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF2_MASK
@ PseudoVSUXEI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10578
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M2
@ PseudoVFCVT_XU_F_V_M2
Definition riscv/opcodes.hpp:1841
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M4_E32
@ PseudoVFWADD_WFPR32_M4_E32
Definition riscv/opcodes.hpp:3501
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M4_MASK
@ PseudoVSSUBU_VX_M4_MASK
Definition riscv/opcodes.hpp:10438
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF2
@ PseudoVSUXSEG8EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:11263
LIEF::assembly::riscv::OPCODE::VNMSAC_VX
@ VNMSAC_VX
Definition riscv/opcodes.hpp:13574
LIEF::assembly::riscv::OPCODE::CV_AVG_B
@ CV_AVG_B
Definition riscv/opcodes.hpp:12193
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF4_MASK
@ PseudoVLOXSEG2EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4377
LIEF::assembly::riscv::OPCODE::SH3ADD
@ SH3ADD
Definition riscv/opcodes.hpp:12963
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M1_MASK
@ PseudoVSOXSEG2EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9176
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_MF2_MASK
@ PseudoVMFGT_VFPR32_MF2_MASK
Definition riscv/opcodes.hpp:6691
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF2_MASK
@ PseudoVLOXSEG8EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4965
LIEF::assembly::riscv::OPCODE::VFRDIV_VF
@ VFRDIV_VF
Definition riscv/opcodes.hpp:13253
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M2_MASK
@ PseudoVLUXSEG3EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:5893
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF8_MASK
@ PseudoVSOXSEG6EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:9610
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_M1_MASK
@ PseudoVSUXSEG7EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11176
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF8_MASK
@ PseudoVLOXSEG3EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:4497
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E64_MASK
@ PseudoVFCVT_RM_F_X_V_M1_E64_MASK
Definition riscv/opcodes.hpp:1766
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M4
@ PseudoVMAX_VX_M4
Definition riscv/opcodes.hpp:6560
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M2
@ PseudoVNCLIP_WV_M2
Definition riscv/opcodes.hpp:7476
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M8_E64
@ PseudoVFMSUB_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2280
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF4
@ PseudoVSSSEG4E16_V_MF4
Definition riscv/opcodes.hpp:10317
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF4_MASK
@ PseudoVSOXSEG6EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:9668
LIEF::assembly::riscv::OPCODE::SHA512SIG1L
@ SHA512SIG1L
Definition riscv/opcodes.hpp:12974
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4_MASK
@ PseudoVWSUBU_WV_M4_MASK
Definition riscv/opcodes.hpp:11752
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E32
@ PseudoVFNMSAC_VV_M2_E32
Definition riscv/opcodes.hpp:2773
LIEF::assembly::riscv::OPCODE::G_STORE
@ G_STORE
Definition riscv/opcodes.hpp:119
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M4
@ PseudoVSOXSEG2EI64_V_M4_M4
Definition riscv/opcodes.hpp:9245
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E8_MASK
@ PseudoVDIV_VV_M1_E8_MASK
Definition riscv/opcodes.hpp:1518
LIEF::assembly::riscv::OPCODE::CV_INSERT
@ CV_INSERT
Definition riscv/opcodes.hpp:12314
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF4_MASK
@ PseudoVLOXSEG5EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4761
LIEF::assembly::riscv::OPCODE::CV_MINU_SCI_H
@ CV_MINU_SCI_H
Definition riscv/opcodes.hpp:12361
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M8_MASK
@ PseudoVLOXEI64_V_M8_M8_MASK
Definition riscv/opcodes.hpp:4289
LIEF::assembly::riscv::OPCODE::MOPR16
@ MOPR16
Definition riscv/opcodes.hpp:12868
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_M1
@ PseudoVSOXSEG8EI64_V_M2_M1
Definition riscv/opcodes.hpp:9799
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF8
@ PseudoVWADDU_VX_MF8
Definition riscv/opcodes.hpp:11357
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M4_M1
@ PseudoVLOXSEG5EI32_V_M4_M1
Definition riscv/opcodes.hpp:4720
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M1
@ PseudoVSUXSEG2EI8_V_M1_M1
Definition riscv/opcodes.hpp:10759
LIEF::assembly::riscv::OPCODE::VSSSEG4E64_V
@ VSSSEG4E64_V
Definition riscv/opcodes.hpp:13746
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E64_MASK
@ PseudoVFNMSUB_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:2836
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_M1_M1
@ PseudoVLUXSEG6EI8_V_M1_M1
Definition riscv/opcodes.hpp:6222
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E32_MASK
@ PseudoVFDIV_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:1908
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E64_MASK
@ PseudoVREM_VX_M1_E64_MASK
Definition riscv/opcodes.hpp:8221
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M2_M1
@ PseudoVLUXSEG5EI16_V_M2_M1
Definition riscv/opcodes.hpp:6086
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF2_E16
@ PseudoVFWMACCBF16_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3703
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_M1_MASK
@ PseudoVSOXSEG8EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9772
LIEF::assembly::riscv::OPCODE::VFMSAC_VF
@ VFMSAC_VF
Definition riscv/opcodes.hpp:13225
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_M1
@ PseudoVSSEG5E8_V_M1
Definition riscv/opcodes.hpp:10095
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF4_MASK
@ PseudoVLUXSEG4EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:6073
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF2
@ PseudoVLOXSEG6EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:4838
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M4
@ PseudoVSE16_V_M4
Definition riscv/opcodes.hpp:8706
LIEF::assembly::riscv::OPCODE::VFWSUB_WF
@ VFWSUB_WF
Definition riscv/opcodes.hpp:13301
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_M1_MASK
@ PseudoVLOXSEG4EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:4683
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF4_MASK
@ PseudoVMSNE_VI_MF4_MASK
Definition riscv/opcodes.hpp:7232
LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M1
@ PseudoVLE64FF_V_M1
Definition riscv/opcodes.hpp:4127
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF2
@ PseudoVLOXSEG6EI64_V_M1_MF2
Definition riscv/opcodes.hpp:4812
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_M2
@ PseudoVC_V_FPR32V_M2
Definition riscv/opcodes.hpp:1223
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M4_MASK
@ PseudoVAADDU_VX_M4_MASK
Definition riscv/opcodes.hpp:540
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M2_MASK
@ PseudoTHVdotVMAQA_VX_M2_MASK
Definition riscv/opcodes.hpp:513
LIEF::assembly::riscv::OPCODE::CV_LHU_rr
@ CV_LHU_rr
Definition riscv/opcodes.hpp:12325
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M2
@ PseudoVNMSUB_VV_M2
Definition riscv/opcodes.hpp:7528
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_MF8
@ PseudoVRELOAD3_MF8
Definition riscv/opcodes.hpp:8062
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF4_E16
@ PseudoVFMUL_VV_MF4_E16
Definition riscv/opcodes.hpp:2370
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E64_MASK
@ PseudoVFSGNJ_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:3282
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF4_MASK
@ PseudoVLUXSEG2EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:5759
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF4_MASK
@ PseudoVSOXSEG3EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9326
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF4
@ PseudoVSUXSEG2EI64_V_M1_MF4
Definition riscv/opcodes.hpp:10733
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_SE_M2
@ PseudoVC_V_FPR32V_SE_M2
Definition riscv/opcodes.hpp:1228
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M4_MASK
@ PseudoVLOXSEG2EI32_V_M8_M4_MASK
Definition riscv/opcodes.hpp:4395
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M1_MASK
@ PseudoVSSSEG4E8_V_M1_MASK
Definition riscv/opcodes.hpp:10330
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E64_MASK
@ PseudoVREM_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:8193
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M4_MASK
@ PseudoVANDN_VV_M4_MASK
Definition riscv/opcodes.hpp:795
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M8
@ PseudoVMERGE_VIM_M8
Definition riscv/opcodes.hpp:6580
LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_M1
@ PseudoVMORN_MM_M1
Definition riscv/opcodes.hpp:6896
LIEF::assembly::riscv::OPCODE::VMSGTU_VI
@ VMSGTU_VI
Definition riscv/opcodes.hpp:13529
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M4_MASK
@ PseudoVMSGT_VI_M4_MASK
Definition riscv/opcodes.hpp:7042
LIEF::assembly::riscv::OPCODE::CV_BITREV
@ CV_BITREV
Definition riscv/opcodes.hpp:12202
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M1_MASK
@ PseudoVMSLEU_VX_M1_MASK
Definition riscv/opcodes.hpp:7108
LIEF::assembly::riscv::OPCODE::TH_FF0
@ TH_FF0
Definition riscv/opcodes.hpp:13044
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF2_MASK
@ PseudoVLUXSEG2EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:5857
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK
@ PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK
Definition riscv/opcodes.hpp:2496
LIEF::assembly::riscv::OPCODE::G_UBFX
@ G_UBFX
Definition riscv/opcodes.hpp:318
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M1_E64
@ PseudoVFSGNJX_VFPR64_M1_E64
Definition riscv/opcodes.hpp:3203
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF2_MASK
@ PseudoVLSSEG7E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5533
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF2
@ PseudoVSSEG4E8_V_MF2
Definition riscv/opcodes.hpp:10077
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_M1
@ PseudoVLUXSEG5EI8_V_MF2_M1
Definition riscv/opcodes.hpp:6144
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M2
@ PseudoVMSBC_VX_M2
Definition riscv/opcodes.hpp:6932
LIEF::assembly::riscv::OPCODE::SRA
@ SRA
Definition riscv/opcodes.hpp:12995
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF2_MASK
@ PseudoVMULHU_VX_MF2_MASK
Definition riscv/opcodes.hpp:7328
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M2
@ PseudoVCLMULH_VV_M2
Definition riscv/opcodes.hpp:946
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_MF4
@ PseudoVAESEM_VS_M4_MF4
Definition riscv/opcodes.hpp:740
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF8
@ PseudoVSOXSEG3EI64_V_M1_MF8
Definition riscv/opcodes.hpp:9353
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M1_MASK
@ PseudoVMFGT_VFPR16_M1_MASK
Definition riscv/opcodes.hpp:6671
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_MF2_E32_MASK
@ PseudoVFRDIV_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2896
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M8_E32_MASK
@ PseudoVFRSUB_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:3110
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M2_MASK
@ PseudoVMULH_VX_M2_MASK
Definition riscv/opcodes.hpp:7350
LIEF::assembly::riscv::OPCODE::FLTQ_D
@ FLTQ_D
Definition riscv/opcodes.hpp:12675
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M8_MASK
@ PseudoVRSUB_VX_M8_MASK
Definition riscv/opcodes.hpp:8597
LIEF::assembly::riscv::OPCODE::VLSEG5E32_V
@ VLSEG5E32_V
Definition riscv/opcodes.hpp:13395
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E16_MASK
@ PseudoVDIVU_VX_MF2_E16_MASK
Definition riscv/opcodes.hpp:1500
LIEF::assembly::riscv::OPCODE::VLSE8_V
@ VLSE8_V
Definition riscv/opcodes.hpp:13367
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M4
@ PseudoVAND_VI_M4
Definition riscv/opcodes.hpp:822
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_M1_MASK
@ PseudoVLSEG7E32FF_V_M1_MASK
Definition riscv/opcodes.hpp:5331
LIEF::assembly::riscv::OPCODE::FCVT_H_WU
@ FCVT_H_WU
Definition riscv/opcodes.hpp:12600
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M4_E16
@ PseudoVFNCVT_RM_F_XU_W_M4_E16
Definition riscv/opcodes.hpp:2497
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E32_MASK
@ PseudoVREMU_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:8095
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M1
@ PseudoVFSLIDE1DOWN_VFPR32_M1
Definition riscv/opcodes.hpp:3313
LIEF::assembly::riscv::OPCODE::VSM4R_VV
@ VSM4R_VV
Definition riscv/opcodes.hpp:13656
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_M1
@ PseudoVAESEM_VS_M4_M1
Definition riscv/opcodes.hpp:736
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M4_E32
@ PseudoVFMACC_VFPR32_M4_E32
Definition riscv/opcodes.hpp:1953
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF2
@ PseudoVSSSEG2E8_V_MF2
Definition riscv/opcodes.hpp:10277
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_MF2_MASK
@ PseudoVLOXSEG6EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4835
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M8_MASK
@ PseudoVSADDU_VX_M8_MASK
Definition riscv/opcodes.hpp:8639
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF4_MASK
@ PseudoVWSUBU_VV_MF4_MASK
Definition riscv/opcodes.hpp:11728
LIEF::assembly::riscv::OPCODE::G_RESET_FPMODE
@ G_RESET_FPMODE
Definition riscv/opcodes.hpp:235
LIEF::assembly::riscv::OPCODE::VSUXSEG5EI8_V
@ VSUXSEG5EI8_V
Definition riscv/opcodes.hpp:13789
LIEF::assembly::riscv::OPCODE::AMOXOR_B_RL
@ AMOXOR_B_RL
Definition riscv/opcodes.hpp:12102
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M1_MASK
@ PseudoVSOXSEG3EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9356
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M2_MASK
@ PseudoVMACC_VX_M2_MASK
Definition riscv/opcodes.hpp:6419
LIEF::assembly::riscv::OPCODE::G_MEMCPY_INLINE
@ G_MEMCPY_INLINE
Definition riscv/opcodes.hpp:293
LIEF::assembly::riscv::OPCODE::VZEXT_VF8
@ VZEXT_VF8
Definition riscv/opcodes.hpp:13843
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF8_MASK
@ PseudoVSADDU_VV_MF8_MASK
Definition riscv/opcodes.hpp:8631
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E64_MASK
@ PseudoVREDMAX_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:7801
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E32_MASK
@ PseudoVREMU_VX_M2_E32_MASK
Definition riscv/opcodes.hpp:8139
LIEF::assembly::riscv::OPCODE::MOPR31
@ MOPR31
Definition riscv/opcodes.hpp:12885
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF4_MASK
@ PseudoVLUXSEG7EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:6259
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M8
@ PseudoVLOXEI16_V_M8_M8
Definition riscv/opcodes.hpp:4202
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_SE_MF2
@ PseudoVC_V_FPR32VV_SE_MF2
Definition riscv/opcodes.hpp:1211
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF4
@ PseudoVLUXSEG3EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:5968
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF2_MASK
@ PseudoVWMACCU_VV_MF2_MASK
Definition riscv/opcodes.hpp:11498
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M2
@ PseudoVROL_VV_M2
Definition riscv/opcodes.hpp:8508
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M2_MASK
@ PseudoVSUXSEG4EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10990
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M1_E32
@ PseudoVFDIV_VFPR32_M1_E32
Definition riscv/opcodes.hpp:1875
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF2
@ PseudoVSUXSEG3EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:10811
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M1_MASK
@ PseudoVLUXEI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:5711
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M4_MASK
@ PseudoVSUB_VV_M4_MASK
Definition riscv/opcodes.hpp:10480
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF2
@ PseudoVNMSAC_VV_MF2
Definition riscv/opcodes.hpp:7506
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E16_MASK
@ PseudoVFWCVT_F_XU_V_M4_E16_MASK
Definition riscv/opcodes.hpp:3590
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF2_MASK
@ PseudoVLOXEI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4225
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_M1_MASK
@ PseudoVSUXSEG4EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:11008
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_M1
@ PseudoVLOXEI64_V_M1_M1
Definition riscv/opcodes.hpp:4258
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E64
@ PseudoVFDIV_VV_M2_E64
Definition riscv/opcodes.hpp:1903
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M4
@ PseudoTHVdotVMAQASU_VV_M4
Definition riscv/opcodes.hpp:454
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF2
@ PseudoVLSSEG2E16_V_MF2
Definition riscv/opcodes.hpp:5404
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M1
@ PseudoVSOXSEG3EI32_V_M1_M1
Definition riscv/opcodes.hpp:9319
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_M2
@ PseudoVC_V_I_M2
Definition riscv/opcodes.hpp:1289
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2_MASK_TIED
@ PseudoVWADDU_WV_MF2_MASK_TIED
Definition riscv/opcodes.hpp:11373
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_SE_M1
@ PseudoVC_V_FPR32V_SE_M1
Definition riscv/opcodes.hpp:1227
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF4_E16
@ PseudoVFSUB_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3401
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E64_MASK
@ PseudoVFNMADD_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:2722
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF8
@ PseudoVBREV_V_MF8
Definition riscv/opcodes.hpp:942
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E16
@ PseudoVFRSQRT7_V_M8_E16
Definition riscv/opcodes.hpp:3079
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M4
@ PseudoVSSSEG2E8_V_M4
Definition riscv/opcodes.hpp:10275
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M1
@ PseudoVMSLTU_VX_M1
Definition riscv/opcodes.hpp:7178
LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_M4
@ PseudoVMNAND_MM_M4
Definition riscv/opcodes.hpp:6884
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M2_MASK
@ PseudoVXOR_VI_M2_MASK
Definition riscv/opcodes.hpp:11842
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E32_MASK
@ PseudoVFWNMACC_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3860
LIEF::assembly::riscv::OPCODE::LR_W
@ LR_W
Definition riscv/opcodes.hpp:12847
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E16_MASK
@ PseudoVFSQRT_V_M1_E16_MASK
Definition riscv/opcodes.hpp:3362
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF2_MASK
@ PseudoVSSRA_VI_MF2_MASK
Definition riscv/opcodes.hpp:10172
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_M1
@ PseudoVSUXSEG4EI16_V_MF4_M1
Definition riscv/opcodes.hpp:10925
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF8
@ PseudoVSSRA_VI_MF8
Definition riscv/opcodes.hpp:10175
LIEF::assembly::riscv::OPCODE::PseudoTLSDESCCall
@ PseudoTLSDESCCall
Definition riscv/opcodes.hpp:520
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M1_MASK
@ PseudoVSUXSEG4EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10994
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M1
@ PseudoVLSEG2E64_V_M1
Definition riscv/opcodes.hpp:5096
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF2_MASK
@ PseudoVNMSUB_VV_MF2_MASK
Definition riscv/opcodes.hpp:7535
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF2
@ PseudoVSOXSEG2EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:9179
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E8
@ PseudoVWREDSUM_VS_M2_E8
Definition riscv/opcodes.hpp:11657
LIEF::assembly::riscv::OPCODE::C_MOP5
@ C_MOP5
Definition riscv/opcodes.hpp:12517
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M2
@ PseudoVADD_VX_M2
Definition riscv/opcodes.hpp:628
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M2_MASK
@ PseudoVLSEG4E16_V_M2_MASK
Definition riscv/opcodes.hpp:5193
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF4_MASK
@ PseudoVROL_VV_MF4_MASK
Definition riscv/opcodes.hpp:8517
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M2_E16
@ PseudoVFNCVT_RM_F_XU_W_M2_E16
Definition riscv/opcodes.hpp:2493
LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF4_MASK
@ PseudoVID_V_MF4_MASK
Definition riscv/opcodes.hpp:4066
LIEF::assembly::riscv::OPCODE::CV_CMPGT_SC_H
@ CV_CMPGT_SC_H
Definition riscv/opcodes.hpp:12240
LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_M8
@ PseudoVMOR_MM_M8
Definition riscv/opcodes.hpp:6906
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_M1
@ PseudoVSOXSEG8EI32_V_M1_M1
Definition riscv/opcodes.hpp:9771
LIEF::assembly::riscv::OPCODE::PseudoSEXT_H
@ PseudoSEXT_H
Definition riscv/opcodes.hpp:444
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_M1
@ PseudoVLUXSEG7EI32_V_M2_M1
Definition riscv/opcodes.hpp:6268
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M1
@ PseudoVSOXSEG3EI8_V_MF2_M1
Definition riscv/opcodes.hpp:9379
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF4_MASK
@ PseudoVSOXSEG4EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9426
LIEF::assembly::riscv::OPCODE::VSOXSEG2EI16_V
@ VSOXSEG2EI16_V
Definition riscv/opcodes.hpp:13664
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M8_MASK
@ PseudoVSRA_VX_M8_MASK
Definition riscv/opcodes.hpp:9898
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF2
@ PseudoVLUXSEG4EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:6070
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M2
@ PseudoVNCLIPU_WX_M2
Definition riscv/opcodes.hpp:7452
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SEQ_FADD
@ G_VECREDUCE_SEQ_FADD
Definition riscv/opcodes.hpp:300
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E32
@ PseudoVFNCVT_F_X_W_M1_E32
Definition riscv/opcodes.hpp:2473
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M8_M2
@ PseudoVLOXSEG3EI32_V_M8_M2
Definition riscv/opcodes.hpp:4516
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E16
@ PseudoVFNMACC_VV_M2_E16
Definition riscv/opcodes.hpp:2651
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF4_E16
@ PseudoVFMIN_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2142
LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SCI_H
@ CV_SDOTUP_SCI_H
Definition riscv/opcodes.hpp:12402
LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_MF2_MASK
@ PseudoVFROUND_NOEXCEPT_V_MF2_MASK
Definition riscv/opcodes.hpp:3059
LIEF::assembly::riscv::OPCODE::VFNMSUB_VV
@ VFNMSUB_VV
Definition riscv/opcodes.hpp:13250
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E64_MASK
@ PseudoVREMU_VX_M2_E64_MASK
Definition riscv/opcodes.hpp:8141
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF4_MASK
@ PseudoVSUXSEG7EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:11200
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E8_MASK
@ PseudoVFWCVT_F_X_V_M1_E8_MASK
Definition riscv/opcodes.hpp:3612
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF8
@ PseudoVSOXSEG8EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:9769
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF8
@ PseudoVMAXU_VX_MF8
Definition riscv/opcodes.hpp:6540
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_MF2_MASK
@ PseudoTHVdotVMAQA_VV_MF2_MASK
Definition riscv/opcodes.hpp:509
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF4_E16_MASK
@ PseudoVFMUL_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:2371
LIEF::assembly::riscv::OPCODE::VMV4R_V
@ VMV4R_V
Definition riscv/opcodes.hpp:13558
LIEF::assembly::riscv::OPCODE::PseudoRVVInitUndefM1
@ PseudoRVVInitUndefM1
Definition riscv/opcodes.hpp:435
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_M2
@ PseudoVAESEM_VS_M2_M2
Definition riscv/opcodes.hpp:732
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E64_MASK
@ PseudoVFMADD_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:2044
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF4
@ PseudoVMFNE_VFPR16_MF4
Definition riscv/opcodes.hpp:6794
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E16
@ PseudoVFNMACC_VV_M1_E16
Definition riscv/opcodes.hpp:2645
LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_MF4
@ PseudoVSPILL7_MF4
Definition riscv/opcodes.hpp:9857
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M8_M1_MASK
@ PseudoVLUXSEG6EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:6221
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M8_MASK
@ PseudoVMFNE_VFPR64_M8_MASK
Definition riscv/opcodes.hpp:6813
LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B8
@ PseudoVLM_V_B8
Definition riscv/opcodes.hpp:4177
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1_TIED
@ PseudoVWSUB_WV_M1_TIED
Definition riscv/opcodes.hpp:11806
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF2
@ PseudoVLSEG7E16FF_V_MF2
Definition riscv/opcodes.hpp:5320
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF4
@ PseudoVMSLE_VX_MF4
Definition riscv/opcodes.hpp:7159
LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M2
@ PseudoVLSE32_V_M2
Definition riscv/opcodes.hpp:5024
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMIN
@ G_VECREDUCE_FMIN
Definition riscv/opcodes.hpp:305
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_MF8
@ PseudoVAESEF_VS_M8_MF8
Definition riscv/opcodes.hpp:718
LIEF::assembly::riscv::OPCODE::AMOCAS_B_AQ
@ AMOCAS_B_AQ
Definition riscv/opcodes.hpp:11980
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M4_MASK
@ PseudoVMSNE_VV_M4_MASK
Definition riscv/opcodes.hpp:7240
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E16_MASK
@ PseudoVFMSAC_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:2223
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_M4
@ PseudoVAESDF_VS_M4_M4
Definition riscv/opcodes.hpp:651
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M2_MASK
@ PseudoVLOXSEG4EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:4661
LIEF::assembly::riscv::OPCODE::STACKMAP
@ STACKMAP
Definition riscv/opcodes.hpp:49
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E32_MASK
@ PseudoVFWCVT_F_F_V_M4_E32_MASK
Definition riscv/opcodes.hpp:3570
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF4
@ PseudoVLOXSEG8EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:5000
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M2_MASK
@ PseudoVMSGT_VI_M2_MASK
Definition riscv/opcodes.hpp:7040
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_M1
@ PseudoVLUXEI8_V_MF8_M1
Definition riscv/opcodes.hpp:5718
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF8_MASK
@ PseudoVSUXSEG8EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:11274
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF2_MASK
@ PseudoVLE8_V_MF2_MASK
Definition riscv/opcodes.hpp:4166
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M8
@ PseudoVLUXEI16_V_M4_M8
Definition riscv/opcodes.hpp:5590
LIEF::assembly::riscv::OPCODE::FMAX_D_IN32X
@ FMAX_D_IN32X
Definition riscv/opcodes.hpp:12697
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_M1
@ PseudoVSUXSEG5EI64_V_M2_M1
Definition riscv/opcodes.hpp:11063
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E16
@ PseudoVFSGNJN_VV_M8_E16
Definition riscv/opcodes.hpp:3169
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_M1
@ PseudoVLSEG5E8_V_M1
Definition riscv/opcodes.hpp:5270
LIEF::assembly::riscv::OPCODE::AMOXOR_W
@ AMOXOR_W
Definition riscv/opcodes.hpp:12111
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M2_E16_MASK
@ PseudoVFRSUB_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3094
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M8_M2
@ PseudoVLUXSEG3EI32_V_M8_M2
Definition riscv/opcodes.hpp:5908
LIEF::assembly::riscv::OPCODE::VMSBC_VVM
@ VMSBC_VVM
Definition riscv/opcodes.hpp:13522
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF4_MASK
@ PseudoVLUXSEG3EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:5933
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF4_E16_MASK
@ PseudoVFSGNJN_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3132
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E8_MASK
@ PseudoVFWCVT_F_XU_V_M1_E8_MASK
Definition riscv/opcodes.hpp:3582
LIEF::assembly::riscv::OPCODE::G_FDIV
@ G_FDIV
Definition riscv/opcodes.hpp:201
LIEF::assembly::riscv::OPCODE::VAESDM_VS
@ VAESDM_VS
Definition riscv/opcodes.hpp:13143
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF4
@ PseudoVLOXSEG2EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:4466
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E16
@ PseudoVFMSAC_VV_M8_E16
Definition riscv/opcodes.hpp:2240
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF8_MASK
@ PseudoVSRA_VI_MF8_MASK
Definition riscv/opcodes.hpp:9876
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E32_MASK
@ PseudoVREDMINU_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:7851
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_M2_MASK
@ PseudoVSOXSEG3EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9358
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M2_MASK
@ PseudoVMADD_VV_M2_MASK
Definition riscv/opcodes.hpp:6475
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF8
@ PseudoVMSLT_VV_MF8
Definition riscv/opcodes.hpp:7205
LIEF::assembly::riscv::OPCODE::VC_VVW
@ VC_VVW
Definition riscv/opcodes.hpp:13181
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E8
@ PseudoVDIV_VX_M8_E8
Definition riscv/opcodes.hpp:1585
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF2_MASK
@ PseudoVLOXSEG2EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4407
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF4
@ PseudoVSE16_V_MF4
Definition riscv/opcodes.hpp:8712
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_M1_MASK
@ PseudoVSUXSEG6EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:11168
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M1_MASK
@ PseudoVSOXEI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9132
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_M1
@ PseudoVSSSEG7E8_V_M1
Definition riscv/opcodes.hpp:10391
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M4_MASK
@ PseudoVMADD_VX_M4_MASK
Definition riscv/opcodes.hpp:6491
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF4_MASK
@ PseudoVSSEG7E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10128
LIEF::assembly::riscv::OPCODE::VL2RE32_V
@ VL2RE32_V
Definition riscv/opcodes.hpp:13312
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF4_MASK
@ PseudoVLOXSEG2EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:4419
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E32_MASK
@ PseudoVFNCVTBF16_F_F_W_M1_E32_MASK
Definition riscv/opcodes.hpp:2420
LIEF::assembly::riscv::OPCODE::PREFETCH_W
@ PREFETCH_W
Definition riscv/opcodes.hpp:12915
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M4
@ PseudoVXOR_VI_M4
Definition riscv/opcodes.hpp:11843
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M2_MASK
@ PseudoVNSRL_WX_M2_MASK
Definition riscv/opcodes.hpp:7617
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF8_MASK
@ PseudoVLUXSEG6EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:6209
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E64_MASK
@ PseudoVRGATHER_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:8469
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M2_E16
@ PseudoVFNMACC_VFPR16_M2_E16
Definition riscv/opcodes.hpp:2617
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SMIN
@ G_VECREDUCE_SMIN
Definition riscv/opcodes.hpp:314
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E8
@ PseudoVDIV_VV_M4_E8
Definition riscv/opcodes.hpp:1533
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M2
@ PseudoVSUXEI8_V_M1_M2
Definition riscv/opcodes.hpp:10617
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M4_MASK
@ PseudoVCLMUL_VV_M4_MASK
Definition riscv/opcodes.hpp:977
LIEF::assembly::riscv::OPCODE::VSBC_VVM
@ VSBC_VVM
Definition riscv/opcodes.hpp:13628
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF4_MASK
@ PseudoVWMACCU_VX_MF4_MASK
Definition riscv/opcodes.hpp:11512
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E8
@ PseudoVREDMAX_VS_M2_E8
Definition riscv/opcodes.hpp:7802
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E32
@ PseudoVDIVU_VX_MF2_E32
Definition riscv/opcodes.hpp:1501
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_MF8
@ PseudoVC_V_VVV_SE_MF8
Definition riscv/opcodes.hpp:1315
LIEF::assembly::riscv::OPCODE::G_MEMMOVE
@ G_MEMMOVE
Definition riscv/opcodes.hpp:294
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_MF8
@ PseudoVMSBC_VXM_MF8
Definition riscv/opcodes.hpp:6930
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M8
@ PseudoVSLL_VI_M8
Definition riscv/opcodes.hpp:8884
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF4_MASK
@ PseudoVMSLEU_VV_MF4_MASK
Definition riscv/opcodes.hpp:7104
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E8
@ PseudoVREDMINU_VS_MF2_E8
Definition riscv/opcodes.hpp:7868
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF4
@ PseudoVLSSEG6E16_V_MF4
Definition riscv/opcodes.hpp:5514
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E32_MASK
@ PseudoVFMAX_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:2090
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M1
@ PseudoVWMACCSU_VV_M1
Definition riscv/opcodes.hpp:11455
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M4
@ PseudoVWSLL_VX_M4
Definition riscv/opcodes.hpp:11711
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_M2
@ PseudoVC_V_X_SE_M2
Definition riscv/opcodes.hpp:1390
LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_MF2
@ PseudoVADC_VIM_MF2
Definition riscv/opcodes.hpp:581
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M1_MASK
@ PseudoVMSLT_VX_M1_MASK
Definition riscv/opcodes.hpp:7208
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF2_MASK
@ PseudoVWSUBU_WX_MF2_MASK
Definition riscv/opcodes.hpp:11774
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_M1_MASK
@ PseudoVLUXSEG7EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:6255
LIEF::assembly::riscv::OPCODE::VLSEG6E32_V
@ VLSEG6E32_V
Definition riscv/opcodes.hpp:13403
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M8_MASK
@ PseudoVMSLEU_VI_M8_MASK
Definition riscv/opcodes.hpp:7086
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E32
@ PseudoVFNCVT_F_X_W_MF2_E32
Definition riscv/opcodes.hpp:2485
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF4
@ PseudoVLSEG3E8FF_V_MF4
Definition riscv/opcodes.hpp:5168
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF2
@ PseudoVLUXSEG3EI32_V_M1_MF2
Definition riscv/opcodes.hpp:5894
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E16
@ PseudoVFNCVTBF16_F_F_W_M1_E16
Definition riscv/opcodes.hpp:2417
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E32
@ PseudoVFREDMIN_VS_M4_E32
Definition riscv/opcodes.hpp:2979
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E16
@ PseudoVFWMACCBF16_VV_M4_E16
Definition riscv/opcodes.hpp:3715
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M8_MASK
@ PseudoVSSUBU_VV_M8_MASK
Definition riscv/opcodes.hpp:10426
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF8_MASK
@ PseudoVADD_VI_MF8_MASK
Definition riscv/opcodes.hpp:611
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M2_M1
@ PseudoVSOXSEG8EI16_V_M2_M1
Definition riscv/opcodes.hpp:9755
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M1_MASK
@ PseudoVASUBU_VV_M1_MASK
Definition riscv/opcodes.hpp:861
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_M1
@ PseudoVSOXSEG7EI32_V_MF2_M1
Definition riscv/opcodes.hpp:9703
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF4_MASK
@ PseudoVMSEQ_VI_MF4_MASK
Definition riscv/opcodes.hpp:6963
LIEF::assembly::riscv::OPCODE::VFSGNJN_VF
@ VFSGNJN_VF
Definition riscv/opcodes.hpp:13261
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M8_E16
@ PseudoVFMADD_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2003
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E16
@ PseudoVFMSUB_VV_M4_E16
Definition riscv/opcodes.hpp:2294
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF8
@ PseudoVSOXEI32_V_MF2_MF8
Definition riscv/opcodes.hpp:9077
LIEF::assembly::riscv::OPCODE::VQMACC_4x8x4
@ VQMACC_4x8x4
Definition riscv/opcodes.hpp:13593
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF4_MASK
@ PseudoVLSEG8E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5395
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_MF2
@ PseudoVMSBC_VVM_MF2
Definition riscv/opcodes.hpp:6914
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M4
@ PseudoVMACC_VX_M4
Definition riscv/opcodes.hpp:6420
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E32_MASK
@ PseudoVFREDMIN_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:2992
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M8
@ PseudoVSE16_V_M8
Definition riscv/opcodes.hpp:8708
LIEF::assembly::riscv::OPCODE::FCVT_S_D_INX
@ FCVT_S_D_INX
Definition riscv/opcodes.hpp:12618
LIEF::assembly::riscv::OPCODE::PseudoVID_V_M2
@ PseudoVID_V_M2
Definition riscv/opcodes.hpp:4057
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF2_MASK
@ PseudoVLOXSEG6EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:4845
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E16
@ PseudoVFWNMACC_VV_MF2_E16
Definition riscv/opcodes.hpp:3869
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF8_MASK
@ PseudoVROR_VV_MF8_MASK
Definition riscv/opcodes.hpp:8561
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF4
@ PseudoVSOXEI64_V_M1_MF4
Definition riscv/opcodes.hpp:9083
LIEF::assembly::riscv::OPCODE::FNMADD_D_IN32X
@ FNMADD_D_IN32X
Definition riscv/opcodes.hpp:12737
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E16_MASK
@ PseudoVFWMSAC_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3786
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E16_MASK
@ PseudoVFNCVT_F_X_W_M2_E16_MASK
Definition riscv/opcodes.hpp:2476
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_M1
@ PseudoVSOXSEG6EI32_V_M2_M1
Definition riscv/opcodes.hpp:9617
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M1_MASK
@ PseudoVNSRL_WI_M1_MASK
Definition riscv/opcodes.hpp:7591
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E32_MASK
@ PseudoVFWREDOSUM_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:3918
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_MF2
@ PseudoTHVdotVMAQAUS_VX_MF2
Definition riscv/opcodes.hpp:478
LIEF::assembly::riscv::OPCODE::VQMACCUS_4x8x4
@ VQMACCUS_4x8x4
Definition riscv/opcodes.hpp:13589
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M4
@ PseudoVLSEG2E16_V_M4
Definition riscv/opcodes.hpp:5068
LIEF::assembly::riscv::OPCODE::C_SW
@ C_SW
Definition riscv/opcodes.hpp:12544
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK
@ PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK
Definition riscv/opcodes.hpp:2556
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M1_MASK
@ PseudoVSUXSEG3EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10832
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M1_MASK
@ PseudoVSLL_VI_M1_MASK
Definition riscv/opcodes.hpp:8879
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M2
@ PseudoVSMUL_VX_M2
Definition riscv/opcodes.hpp:8980
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_M1_MASK
@ PseudoVLUXSEG3EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:5911
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E32
@ PseudoVDIVU_VV_M2_E32
Definition riscv/opcodes.hpp:1433
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16_MASK_TIED
@ PseudoVFWSUB_WV_MF4_E16_MASK_TIED
Definition riscv/opcodes.hpp:4043
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF4_MASK
@ PseudoVCLZ_V_MF4_MASK
Definition riscv/opcodes.hpp:1011
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M2_MASK
@ PseudoVMSLTU_VX_M2_MASK
Definition riscv/opcodes.hpp:7181
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E32
@ PseudoVFWCVT_F_X_V_MF2_E32
Definition riscv/opcodes.hpp:3627
LIEF::assembly::riscv::OPCODE::FADD_H
@ FADD_H
Definition riscv/opcodes.hpp:12561
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_M2
@ PseudoVFMV_FPR16_S_M2
Definition riscv/opcodes.hpp:2373
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF8_MASK
@ PseudoVSUXSEG5EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:11034
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_MF2_MASK
@ PseudoVLOXSEG5EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:4747
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M2_MASK
@ PseudoVSMUL_VV_M2_MASK
Definition riscv/opcodes.hpp:8967
LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_MF4
@ PseudoVMANDN_MM_MF4
Definition riscv/opcodes.hpp:6505
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E32
@ PseudoVFWSUB_VV_M1_E32
Definition riscv/opcodes.hpp:3975
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E16
@ PseudoVDIV_VX_M1_E16
Definition riscv/opcodes.hpp:1555
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E32
@ PseudoVFMSAC_VV_M4_E32
Definition riscv/opcodes.hpp:2236
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M2
@ PseudoVLUXEI32_V_M4_M2
Definition riscv/opcodes.hpp:5630
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M4_MASK
@ PseudoVLOXEI8_V_M1_M4_MASK
Definition riscv/opcodes.hpp:4295
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E64_MASK
@ PseudoVREDSUM_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:7969
LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI0_SCI_B
@ CV_SHUFFLEI0_SCI_B
Definition riscv/opcodes.hpp:12413
LIEF::assembly::riscv::OPCODE::G_BR
@ G_BR
Definition riscv/opcodes.hpp:245
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_M1_MASK
@ PseudoVSUXSEG6EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11122
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M1
@ PseudoVSUB_VX_M1
Definition riscv/opcodes.hpp:10489
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M1
@ PseudoVMSEQ_VV_M1
Definition riscv/opcodes.hpp:6966
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M2
@ PseudoVMAX_VV_M2
Definition riscv/opcodes.hpp:6544
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M2_MASK
@ PseudoVMSEQ_VX_M2_MASK
Definition riscv/opcodes.hpp:6983
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_M1_MASK
@ PseudoVLSEG5E32FF_V_M1_MASK
Definition riscv/opcodes.hpp:5251
LIEF::assembly::riscv::OPCODE::VAESEM_VV
@ VAESEM_VV
Definition riscv/opcodes.hpp:13148
LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32_AQ
@ AMOCAS_D_RV32_AQ
Definition riscv/opcodes.hpp:11984
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M2
@ PseudoVANDN_VV_M2
Definition riscv/opcodes.hpp:792
LIEF::assembly::riscv::OPCODE::VMSBC_VV
@ VMSBC_VV
Definition riscv/opcodes.hpp:13521
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF4
@ PseudoVLOXSEG6EI64_V_M2_MF4
Definition riscv/opcodes.hpp:4822
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M1
@ PseudoTHVdotVMAQA_VX_M1
Definition riscv/opcodes.hpp:510
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF8_E8_MASK
@ PseudoVREDMINU_VS_MF8_E8_MASK
Definition riscv/opcodes.hpp:7875
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_M1
@ PseudoVSSEG7E32_V_M1
Definition riscv/opcodes.hpp:10129
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF2
@ PseudoVLOXSEG2EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:4398
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M8_MASK
@ PseudoVADD_VV_M8_MASK
Definition riscv/opcodes.hpp:619
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M8
@ PseudoVSRA_VV_M8
Definition riscv/opcodes.hpp:9883
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M8
@ PseudoVMIN_VX_M8
Definition riscv/opcodes.hpp:6874
LIEF::assembly::riscv::OPCODE::CV_SLL_SCI_B
@ CV_SLL_SCI_B
Definition riscv/opcodes.hpp:12427
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M2
@ PseudoVWMACC_VV_M2
Definition riscv/opcodes.hpp:11517
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E64
@ PseudoVREDMINU_VS_M1_E64
Definition riscv/opcodes.hpp:7836
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF8_MASK
@ PseudoVNSRA_WI_MF8_MASK
Definition riscv/opcodes.hpp:7565
LIEF::assembly::riscv::OPCODE::VSSEG6E16_V
@ VSSEG6E16_V
Definition riscv/opcodes.hpp:13718
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF2_E32
@ PseudoVFCVT_RM_F_XU_V_MF2_E32
Definition riscv/opcodes.hpp:1757
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M2
@ PseudoTHVdotVMAQASU_VX_M2
Definition riscv/opcodes.hpp:462
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF4_MASK
@ PseudoVSUB_VX_MF4_MASK
Definition riscv/opcodes.hpp:10500
LIEF::assembly::riscv::OPCODE::PseudoCCADDIW
@ PseudoCCADDIW
Definition riscv/opcodes.hpp:342
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF2_MASK
@ PseudoVLOXSEG2EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4417
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M4_MASK
@ PseudoVSUXEI16_V_M2_M4_MASK
Definition riscv/opcodes.hpp:10516
LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M4
@ PseudoVSE64_V_M4
Definition riscv/opcodes.hpp:8728
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M2
@ PseudoVSOXEI32_V_M1_M2
Definition riscv/opcodes.hpp:9043
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M2_MASK
@ PseudoVLUXSEG2EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:5741
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF2_MASK
@ PseudoVSUXSEG8EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:11270
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_M1
@ PseudoVSUXSEG5EI32_V_M1_M1
Definition riscv/opcodes.hpp:11035
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M4
@ PseudoVRGATHER_VI_M4
Definition riscv/opcodes.hpp:8438
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M8
@ PseudoVMSGT_VX_M8
Definition riscv/opcodes.hpp:7057
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF4_MASK
@ PseudoVSLIDEUP_VX_MF4_MASK
Definition riscv/opcodes.hpp:8875
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M4
@ PseudoVLOXSEG2EI8_V_M1_M4
Definition riscv/opcodes.hpp:4438
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF2
@ PseudoVLSSEG5E16_V_MF2
Definition riscv/opcodes.hpp:5492
LIEF::assembly::riscv::OPCODE::VOR_VI
@ VOR_VI
Definition riscv/opcodes.hpp:13583
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M2
@ PseudoVFNCVT_RTZ_XU_F_W_M2
Definition riscv/opcodes.hpp:2569
LIEF::assembly::riscv::OPCODE::VLUXSEG7EI8_V
@ VLUXSEG7EI8_V
Definition riscv/opcodes.hpp:13479
LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_MF8
@ PseudoVADC_VXM_MF8
Definition riscv/opcodes.hpp:597
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8
@ PseudoVWADDU_WV_MF8
Definition riscv/opcodes.hpp:11379
LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_MF4
@ PseudoVMORN_MM_MF4
Definition riscv/opcodes.hpp:6901
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M1
@ PseudoVFWCVT_RM_XU_F_V_M1
Definition riscv/opcodes.hpp:3637
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M2_MASK
@ PseudoVSOXEI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9002
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M2_E32
@ PseudoVFWMSAC_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3779
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF8
@ PseudoVLOXSEG2EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:4468
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M4
@ PseudoTHVdotVMAQAUS_VX_M4
Definition riscv/opcodes.hpp:474
LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SCI_H
@ CV_SDOTUSP_SCI_H
Definition riscv/opcodes.hpp:12408
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M8_E16_MASK
@ PseudoVFSUB_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:3398
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M1
@ PseudoVFSLIDE1UP_VFPR32_M1
Definition riscv/opcodes.hpp:3343
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF4
@ PseudoVLSSEG6E8_V_MF4
Definition riscv/opcodes.hpp:5526
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E16
@ PseudoVFREDOSUM_VS_M1_E16
Definition riscv/opcodes.hpp:2995
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E32
@ PseudoVFWCVTBF16_F_F_V_M2_E32
Definition riscv/opcodes.hpp:3547
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF2_MASK
@ PseudoVSOXSEG5EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9520
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_M1
@ PseudoVSUXSEG5EI8_V_MF2_M1
Definition riscv/opcodes.hpp:11077
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF4
@ PseudoVMUL_VX_MF4
Definition riscv/opcodes.hpp:7385
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M4
@ PseudoVSUXSEG2EI8_V_MF2_M4
Definition riscv/opcodes.hpp:10775
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M1_MASK
@ PseudoVLSEG4E16FF_V_M1_MASK
Definition riscv/opcodes.hpp:5183
LIEF::assembly::riscv::OPCODE::FSGNJ_S
@ FSGNJ_S
Definition riscv/opcodes.hpp:12776
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16_TIED
@ PseudoVFWADD_WV_M4_E16_TIED
Definition riscv/opcodes.hpp:3524
LIEF::assembly::riscv::OPCODE::G_STRICT_FREM
@ G_STRICT_FREM
Definition riscv/opcodes.hpp:286
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF8
@ PseudoVWMULU_VV_MF8
Definition riscv/opcodes.hpp:11573
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF4_MASK
@ PseudoVWADDU_VX_MF4_MASK
Definition riscv/opcodes.hpp:11356
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF2_MASK
@ PseudoVSSSEG3E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10288
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M1
@ PseudoVRGATHEREI16_VV_M4_E8_M1
Definition riscv/opcodes.hpp:8362
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M1_MASK
@ PseudoVRGATHEREI16_VV_M2_E64_M1_MASK
Definition riscv/opcodes.hpp:8323
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E16_MASK
@ PseudoVREM_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:8197
LIEF::assembly::riscv::OPCODE::VSSSEG6E64_V
@ VSSSEG6E64_V
Definition riscv/opcodes.hpp:13754
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M8_MASK
@ PseudoVLOXEI16_V_M4_M8_MASK
Definition riscv/opcodes.hpp:4199
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M1_MASK
@ PseudoVSLL_VV_M1_MASK
Definition riscv/opcodes.hpp:8893
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF2_MASK
@ PseudoVLOXSEG2EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4359
LIEF::assembly::riscv::OPCODE::VLOXSEG5EI16_V
@ VLOXSEG5EI16_V
Definition riscv/opcodes.hpp:13348
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E32_MASK
@ PseudoVDIV_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:1514
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M2_MASK
@ PseudoVLUXSEG2EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5773
LIEF::assembly::riscv::OPCODE::SEXT_B
@ SEXT_B
Definition riscv/opcodes.hpp:12950
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M1_MASK
@ PseudoVFSLIDE1DOWN_VFPR16_M1_MASK
Definition riscv/opcodes.hpp:3302
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_M1_MASK
@ PseudoVLUXSEG7EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6243
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M2_MASK
@ PseudoVAADD_VV_M2_MASK
Definition riscv/opcodes.hpp:552
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF4_E16
@ PseudoVFWSUB_VV_MF4_E16
Definition riscv/opcodes.hpp:3989
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF4
@ PseudoVSOXSEG7EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:9741
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_MF2
@ PseudoVLOXSEG3EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:4562
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_M1
@ PseudoVC_V_XV_SE_M1
Definition riscv/opcodes.hpp:1375
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M4
@ PseudoVMERGE_VXM_M4
Definition riscv/opcodes.hpp:6593
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M2
@ PseudoVNSRA_WV_M2
Definition riscv/opcodes.hpp:7568
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF4_E16_MASK
@ PseudoVFMSAC_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2203
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_M1_MASK
@ PseudoVLUXSEG8EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:6377
LIEF::assembly::riscv::OPCODE::TH_SBIA
@ TH_SBIA
Definition riscv/opcodes.hpp:13102
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF2_MASK
@ PseudoVLSE16_V_MF2_MASK
Definition riscv/opcodes.hpp:5019
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M2
@ PseudoVMULHU_VX_M2
Definition riscv/opcodes.hpp:7321
LIEF::assembly::riscv::OPCODE::VSSSEG2E64_V
@ VSSSEG2E64_V
Definition riscv/opcodes.hpp:13738
LIEF::assembly::riscv::OPCODE::AMOSWAP_W_AQ_RL
@ AMOSWAP_W_AQ_RL
Definition riscv/opcodes.hpp:12097
LIEF::assembly::riscv::OPCODE::BLT
@ BLT
Definition riscv/opcodes.hpp:12128
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E32
@ PseudoVFSGNJX_VV_M4_E32
Definition riscv/opcodes.hpp:3225
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_M1_MASK
@ PseudoVSUXSEG8EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11256
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M1
@ PseudoVROR_VX_M1
Definition riscv/opcodes.hpp:8562
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M2
@ PseudoVMFGE_VFPR32_M2
Definition riscv/opcodes.hpp:6654
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF2
@ PseudoVSUXEI64_V_M1_MF2
Definition riscv/opcodes.hpp:10585
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M4_E16
@ PseudoVFRSUB_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3095
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF4_MASK
@ PseudoVASUBU_VV_MF4_MASK
Definition riscv/opcodes.hpp:871
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_MF2_MASK
@ PseudoVSOXSEG3EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:9368
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK
@ PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK
Definition riscv/opcodes.hpp:2502
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF4_MASK
@ PseudoVWSUB_VX_MF4_MASK
Definition riscv/opcodes.hpp:11800
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_M8
@ PseudoVC_FPR16V_SE_M8
Definition riscv/opcodes.hpp:1093
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E16
@ PseudoVREMU_VV_MF2_E16
Definition riscv/opcodes.hpp:8116
LIEF::assembly::riscv::OPCODE::G_ADDRSPACE_CAST
@ G_ADDRSPACE_CAST
Definition riscv/opcodes.hpp:276
LIEF::assembly::riscv::OPCODE::FCVT_D_S
@ FCVT_D_S
Definition riscv/opcodes.hpp:12581
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M1_MASK
@ PseudoVLUXSEG3EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:5875
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M2
@ PseudoVWSLL_VV_M2
Definition riscv/opcodes.hpp:11697
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E32_MASK
@ PseudoVFCVT_F_XU_V_M2_E32_MASK
Definition riscv/opcodes.hpp:1680
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M4
@ PseudoVNCLIPU_WV_M4
Definition riscv/opcodes.hpp:7442
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF2
@ PseudoVANDN_VX_MF2
Definition riscv/opcodes.hpp:812
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_MF2
@ PseudoVLOXSEG7EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:4914
LIEF::assembly::riscv::OPCODE::CV_SUBNR
@ CV_SUBNR
Definition riscv/opcodes.hpp:12444
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E64
@ PseudoVRGATHER_VV_M2_E64
Definition riscv/opcodes.hpp:8460
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M1_MASK
@ PseudoVSOXEI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9050
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M2
@ PseudoVLUXEI32_V_M8_M2
Definition riscv/opcodes.hpp:5636
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF2_MASK
@ PseudoVSOXSEG7EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9706
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M8_E64_MASK
@ PseudoVFMSAC_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2221
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E64
@ PseudoVDIVU_VX_M4_E64
Definition riscv/opcodes.hpp:1487
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M4_E32
@ PseudoVFNMACC_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2631
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_M1_MASK
@ PseudoVLUXSEG4EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:5993
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M2
@ PseudoVLSEG3E16FF_V_M2
Definition riscv/opcodes.hpp:5128
LIEF::assembly::riscv::OPCODE::C_SSPUSH
@ C_SSPUSH
Definition riscv/opcodes.hpp:12541
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_M1_MASK
@ PseudoVSUXSEG8EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11262
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF2
@ PseudoVLSEG8E8FF_V_MF2
Definition riscv/opcodes.hpp:5384
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M4_E64_MASK
@ PseudoVFMSUB_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2279
LIEF::assembly::riscv::OPCODE::CV_SH_rr
@ CV_SH_rr
Definition riscv/opcodes.hpp:12421
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF2
@ PseudoVLSEG5E8FF_V_MF2
Definition riscv/opcodes.hpp:5264
LIEF::assembly::riscv::OPCODE::VMSGT_VX
@ VMSGT_VX
Definition riscv/opcodes.hpp:13532
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32_MASK
@ PseudoVFWADD_WV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3534
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M8
@ PseudoVLOXEI32_V_M8_M8
Definition riscv/opcodes.hpp:4248
LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M1
@ PseudoVSHA2CH_VV_M1
Definition riscv/opcodes.hpp:8779
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E8
@ PseudoVDIVU_VV_M8_E8
Definition riscv/opcodes.hpp:1453
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M4
@ PseudoVFSLIDE1UP_VFPR32_M4
Definition riscv/opcodes.hpp:3347
LIEF::assembly::riscv::OPCODE::SF_CEASE
@ SF_CEASE
Definition riscv/opcodes.hpp:12956
LIEF::assembly::riscv::OPCODE::CLMULR
@ CLMULR
Definition riscv/opcodes.hpp:12140
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF8_MASK
@ PseudoVLUXSEG4EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:6035
LIEF::assembly::riscv::OPCODE::VC_V_FVW
@ VC_V_FVW
Definition riscv/opcodes.hpp:13184
LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M2_MASK
@ PseudoVSSE32_V_M2_MASK
Definition riscv/opcodes.hpp:9962
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF4
@ PseudoVSUXSEG7EI64_V_M1_MF4
Definition riscv/opcodes.hpp:11219
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M2_M1_MASK
@ PseudoVLOXSEG7EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4855
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E64
@ PseudoVREDMINU_VS_M8_E64
Definition riscv/opcodes.hpp:7860
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_M1_MASK
@ PseudoVSUXSEG5EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11048
LIEF::assembly::riscv::OPCODE::AMOMIN_H
@ AMOMIN_H
Definition riscv/opcodes.hpp:12059
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M1_MASK
@ PseudoVWMULU_VV_M1_MASK
Definition riscv/opcodes.hpp:11564
LIEF::assembly::riscv::OPCODE::VMAX_VX
@ VMAX_VX
Definition riscv/opcodes.hpp:13499
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E16
@ PseudoVREDXOR_VS_M4_E16
Definition riscv/opcodes.hpp:8024
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_MF2
@ PseudoVZEXT_VF4_MF2
Definition riscv/opcodes.hpp:11901
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M1_E16
@ PseudoVFADD_VFPR16_M1_E16
Definition riscv/opcodes.hpp:1599
LIEF::assembly::riscv::OPCODE::VFWMACCBF16_VV
@ VFWMACCBF16_VV
Definition riscv/opcodes.hpp:13285
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M4_E16_MASK
@ PseudoVFWMACCBF16_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3702
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF2
@ PseudoVLUXSEG6EI32_V_M1_MF2
Definition riscv/opcodes.hpp:6184
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF2_MASK
@ PseudoVLOXSEG4EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4613
LIEF::assembly::riscv::OPCODE::VMFLT_VF
@ VMFLT_VF
Definition riscv/opcodes.hpp:13509
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M1
@ PseudoVLSSEG3E32_V_M1
Definition riscv/opcodes.hpp:5442
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF4
@ PseudoVLOXSEG2EI64_V_M1_MF4
Definition riscv/opcodes.hpp:4408
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M4_MASK
@ PseudoVNCLIPU_WV_M4_MASK
Definition riscv/opcodes.hpp:7443
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF8
@ PseudoVWMACCU_VX_MF8
Definition riscv/opcodes.hpp:11513
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF8
@ PseudoVLOXSEG7EI64_V_M1_MF8
Definition riscv/opcodes.hpp:4896
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF2_MASK
@ PseudoVSE16_V_MF2_MASK
Definition riscv/opcodes.hpp:8711
LIEF::assembly::riscv::OPCODE::CV_DOTUP_SC_H
@ CV_DOTUP_SC_H
Definition riscv/opcodes.hpp:12292
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M2
@ PseudoVSUB_VV_M2
Definition riscv/opcodes.hpp:10477
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF2_E16_MASK
@ PseudoVFWSUB_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3962
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF4_MASK
@ PseudoVSSEG5E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10100
LIEF::assembly::riscv::OPCODE::G_GET_FPMODE
@ G_GET_FPMODE
Definition riscv/opcodes.hpp:233
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF4_MASK
@ PseudoVSSRL_VI_MF4_MASK
Definition riscv/opcodes.hpp:10216
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M1_MASK
@ PseudoVMSGTU_VI_M1_MASK
Definition riscv/opcodes.hpp:7010
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8_MASK
@ PseudoVWADD_WV_MF8_MASK
Definition riscv/opcodes.hpp:11440
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF2_MASK
@ PseudoVLSSEG6E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5525
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M1
@ PseudoVMADD_VX_M1
Definition riscv/opcodes.hpp:6486
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E16_MASK
@ PseudoVREMU_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:8117
LIEF::assembly::riscv::OPCODE::VMSLEU_VX
@ VMSLEU_VX
Definition riscv/opcodes.hpp:13536
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF8
@ PseudoVSUXSEG5EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:11033
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF2
@ PseudoVLUXSEG4EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:6076
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M2
@ PseudoVLUXEI8_V_MF2_M2
Definition riscv/opcodes.hpp:5704
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_M1_MASK
@ PseudoVSUXSEG8EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11276
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M1_MASK
@ PseudoVMULH_VV_M1_MASK
Definition riscv/opcodes.hpp:7334
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF2_MASK
@ PseudoVSUXSEG4EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:10928
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M1_E16
@ PseudoVFNCVT_RM_F_XU_W_M1_E16
Definition riscv/opcodes.hpp:2489
LIEF::assembly::riscv::OPCODE::VMINU_VV
@ VMINU_VV
Definition riscv/opcodes.hpp:13513
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_M2
@ PseudoVFNRCLIP_XU_F_QF_M2
Definition riscv/opcodes.hpp:2857
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E32_MASK
@ PseudoVFWCVT_F_X_V_M4_E32_MASK
Definition riscv/opcodes.hpp:3622
LIEF::assembly::riscv::OPCODE::VWMACCSU_VV
@ VWMACCSU_VV
Definition riscv/opcodes.hpp:13812
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M4_E16
@ PseudoVFMSAC_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2196
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF4
@ PseudoVROR_VV_MF4
Definition riscv/opcodes.hpp:8558
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M2_MASK
@ PseudoVSOXSEG2EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:9214
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF2_MASK
@ PseudoVAADDU_VX_MF2_MASK
Definition riscv/opcodes.hpp:544
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_MF2_E32
@ PseudoVFRSUB_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3111
LIEF::assembly::riscv::OPCODE::G_INDEXED_LOAD
@ G_INDEXED_LOAD
Definition riscv/opcodes.hpp:116
LIEF::assembly::riscv::OPCODE::SC_W_AQ_RL
@ SC_W_AQ_RL
Definition riscv/opcodes.hpp:12945
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M2_MASK
@ PseudoVSSRL_VI_M2_MASK
Definition riscv/opcodes.hpp:10208
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M2
@ PseudoVLUXEI64_V_M4_M2
Definition riscv/opcodes.hpp:5668
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M4_E32_MASK
@ PseudoVFNMADD_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2692
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M1_MASK
@ PseudoVMAXU_VX_M1_MASK
Definition riscv/opcodes.hpp:6529
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M4
@ PseudoVRGATHEREI16_VV_M4_E16_M4
Definition riscv/opcodes.hpp:8342
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M2
@ PseudoVSUXSEG2EI64_V_M8_M2
Definition riscv/opcodes.hpp:10755
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E8
@ PseudoVDIV_VV_M8_E8
Definition riscv/opcodes.hpp:1541
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF2
@ PseudoVLOXEI64_V_M1_MF2
Definition riscv/opcodes.hpp:4260
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M8
@ PseudoVMSLTU_VV_M8
Definition riscv/opcodes.hpp:7170
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF4
@ PseudoVOR_VX_MF4
Definition riscv/opcodes.hpp:7664
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF4
@ PseudoVMAXU_VV_MF4
Definition riscv/opcodes.hpp:6524
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF4
@ PseudoVMULHSU_VV_MF4
Definition riscv/opcodes.hpp:7287
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M1
@ PseudoVWADDU_VX_M1
Definition riscv/opcodes.hpp:11347
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M8_MASK
@ PseudoVSSRL_VV_M8_MASK
Definition riscv/opcodes.hpp:10226
LIEF::assembly::riscv::OPCODE::PseudoSH
@ PseudoSH
Definition riscv/opcodes.hpp:445
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_M1
@ PseudoVLUXSEG6EI32_V_M1_M1
Definition riscv/opcodes.hpp:6182
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M8_MASK
@ PseudoVSSUB_VV_M8_MASK
Definition riscv/opcodes.hpp:10454
LIEF::assembly::riscv::OPCODE::CV_ABS_H
@ CV_ABS_H
Definition riscv/opcodes.hpp:12163
LIEF::assembly::riscv::OPCODE::VLUXSEG8EI32_V
@ VLUXSEG8EI32_V
Definition riscv/opcodes.hpp:13481
LIEF::assembly::riscv::OPCODE::CFI_INSTRUCTION
@ CFI_INSTRUCTION
Definition riscv/opcodes.hpp:27
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_MF2_MASK
@ PseudoVLOXSEG7EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:4907
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M1
@ PseudoVLSSEG2E8_V_M1
Definition riscv/opcodes.hpp:5422
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF8
@ PseudoVLUXEI8_V_MF8_MF8
Definition riscv/opcodes.hpp:5724
LIEF::assembly::riscv::OPCODE::C_ADD
@ C_ADD
Definition riscv/opcodes.hpp:12475
LIEF::assembly::riscv::OPCODE::VMUL_VX
@ VMUL_VX
Definition riscv/opcodes.hpp:13555
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF4_MASK
@ PseudoVLUXSEG6EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:6239
LIEF::assembly::riscv::OPCODE::BEQ
@ BEQ
Definition riscv/opcodes.hpp:12121
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M4_MASK
@ PseudoVWMULSU_VV_M4_MASK
Definition riscv/opcodes.hpp:11544
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M1
@ PseudoVZEXT_VF4_M1
Definition riscv/opcodes.hpp:11893
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M2
@ PseudoVSUXSEG2EI32_V_M1_M2
Definition riscv/opcodes.hpp:10697
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M1_MASK
@ PseudoVSSEG2E8_V_M1_MASK
Definition riscv/opcodes.hpp:10016
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_M1_MASK
@ PseudoVSSEG6E16_V_M1_MASK
Definition riscv/opcodes.hpp:10104
LIEF::assembly::riscv::OPCODE::AMOADD_D_RL
@ AMOADD_D_RL
Definition riscv/opcodes.hpp:11954
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF4
@ PseudoVCTZ_V_MF4
Definition riscv/opcodes.hpp:1074
LIEF::assembly::riscv::OPCODE::CV_CMPLE_B
@ CV_CMPLE_B
Definition riscv/opcodes.hpp:12247
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M2_E64_MASK
@ PseudoVFSGNJN_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:3146
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M4_E32_MASK
@ PseudoVFADD_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:1616
LIEF::assembly::riscv::OPCODE::VFWNMSAC_VV
@ VFWNMSAC_VV
Definition riscv/opcodes.hpp:13296
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M4_MASK
@ PseudoVFNCVT_XU_F_W_M4_MASK
Definition riscv/opcodes.hpp:2596
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF4
@ PseudoVSOXSEG5EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:9587
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF4_MASK
@ PseudoVSOXSEG5EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9548
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M8_M2_MASK
@ PseudoVSUXSEG4EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:10952
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E32
@ PseudoVFWMUL_VV_M2_E32
Definition riscv/opcodes.hpp:3827
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M4
@ PseudoVLOXSEG2EI32_V_M8_M4
Definition riscv/opcodes.hpp:4394
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M1_MASK
@ PseudoVLOXEI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4319
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF4_E16_MASK
@ PseudoVFMSUB_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2263
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M1_MASK
@ PseudoVFNCVT_XU_F_W_M1_MASK
Definition riscv/opcodes.hpp:2592
LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_M4
@ PseudoVC_VV_SE_M4
Definition riscv/opcodes.hpp:1161
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M4_MASK
@ PseudoVSLIDE1UP_VX_M4_MASK
Definition riscv/opcodes.hpp:8813
LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_4x8x4_M1
@ PseudoVQMACCU_4x8x4_M1
Definition riscv/opcodes.hpp:7688
LIEF::assembly::riscv::OPCODE::VLUXSEG4EI16_V
@ VLUXSEG4EI16_V
Definition riscv/opcodes.hpp:13464
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF4
@ PseudoVLOXSEG4EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:4686
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M4_MASK
@ PseudoVSUXEI16_V_M8_M4_MASK
Definition riscv/opcodes.hpp:10526
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF2
@ PseudoVSLIDE1UP_VX_MF2
Definition riscv/opcodes.hpp:8816
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E64_MASK
@ PseudoVFADD_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:1646
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF4
@ PseudoVSOXSEG5EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:9521
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M8_MASK
@ PseudoVRSUB_VI_M8_MASK
Definition riscv/opcodes.hpp:8583
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M1_MASK
@ PseudoVASUB_VV_M1_MASK
Definition riscv/opcodes.hpp:889
LIEF::assembly::riscv::OPCODE::PseudoCCAND
@ PseudoCCAND
Definition riscv/opcodes.hpp:344
LIEF::assembly::riscv::OPCODE::CV_SUB_SC_B
@ CV_SUB_SC_B
Definition riscv/opcodes.hpp:12462
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M8
@ PseudoVLUXEI64_V_M8_M8
Definition riscv/opcodes.hpp:5680
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_M2
@ PseudoVC_V_VVW_SE_M2
Definition riscv/opcodes.hpp:1323
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E32_MASK
@ PseudoVFMSAC_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:2231
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF8_MASK
@ PseudoVLUXSEG4EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:6081
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M8_E32
@ PseudoVFNMADD_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2693
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E64
@ PseudoVFMSAC_VV_M8_E64
Definition riscv/opcodes.hpp:2244
LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M8_MASK
@ PseudoVSE32_V_M8_MASK
Definition riscv/opcodes.hpp:8721
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF8_MASK
@ PseudoVNSRA_WX_MF8_MASK
Definition riscv/opcodes.hpp:7589
LIEF::assembly::riscv::OPCODE::VSLIDEDOWN_VI
@ VSLIDEDOWN_VI
Definition riscv/opcodes.hpp:13645
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E16
@ PseudoVDIVU_VX_M2_E16
Definition riscv/opcodes.hpp:1475
LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VX
@ PseudoVMSGEU_VX
Definition riscv/opcodes.hpp:7002
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF2_MASK
@ PseudoVSSEG4E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10060
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M4
@ PseudoVSRA_VI_M4
Definition riscv/opcodes.hpp:9867
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF2_MASK
@ PseudoVMINU_VV_MF2_MASK
Definition riscv/opcodes.hpp:6835
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_MF8
@ PseudoVC_V_IVV_SE_MF8
Definition riscv/opcodes.hpp:1261
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF4
@ PseudoVSUXSEG7EI32_V_M1_MF4
Definition riscv/opcodes.hpp:11199
LIEF::assembly::riscv::OPCODE::VSOXSEG3EI16_V
@ VSOXSEG3EI16_V
Definition riscv/opcodes.hpp:13668
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M2_E16
@ PseudoVFWNMSAC_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3877
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E64
@ PseudoVFMSUB_VV_M8_E64
Definition riscv/opcodes.hpp:2304
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF2_E16_MASK
@ PseudoVFNMSAC_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2744
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF2
@ PseudoVSUXSEG6EI64_V_M1_MF2
Definition riscv/opcodes.hpp:11137
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M8
@ PseudoTHVdotVMAQA_VV_M8
Definition riscv/opcodes.hpp:506
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_MF2
@ PseudoVLSEG7E32_V_MF2
Definition riscv/opcodes.hpp:5336
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E64_MASK
@ PseudoVFMSAC_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:2239
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E64_MASK
@ PseudoVFRSQRT7_V_M1_E64_MASK
Definition riscv/opcodes.hpp:3066
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E16
@ PseudoVREDAND_VS_MF4_E16
Definition riscv/opcodes.hpp:7738
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M2_MASK
@ PseudoVSUXSEG2EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:10782
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M2_E64_MASK
@ PseudoVFNMADD_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2700
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E16_MASK
@ PseudoVFREC7_V_M2_E16_MASK
Definition riscv/opcodes.hpp:2912
LIEF::assembly::riscv::OPCODE::ADDW
@ ADDW
Definition riscv/opcodes.hpp:11934
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E16
@ PseudoVFREDUSUM_VS_M4_E16
Definition riscv/opcodes.hpp:3037
LIEF::assembly::riscv::OPCODE::VC_VV
@ VC_VV
Definition riscv/opcodes.hpp:13179
LIEF::assembly::riscv::OPCODE::VSSSEG2E16_V
@ VSSSEG2E16_V
Definition riscv/opcodes.hpp:13736
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M4
@ PseudoVWMULSU_VX_M4
Definition riscv/opcodes.hpp:11555
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E16_MASK
@ PseudoVREMU_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:8109
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF2_MASK
@ PseudoVLSEG3E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5139
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M1
@ PseudoVRGATHEREI16_VV_M4_E64_M1
Definition riscv/opcodes.hpp:8354
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E32_MASK
@ PseudoVWREDSUM_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:11668
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E8
@ PseudoVREMU_VV_M2_E8
Definition riscv/opcodes.hpp:8098
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF2_MASK
@ PseudoVSSEG7E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10138
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF2
@ PseudoVSOXSEG3EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:9395
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M4
@ PseudoVMAXU_VX_M4
Definition riscv/opcodes.hpp:6532
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M1
@ PseudoVAND_VI_M1
Definition riscv/opcodes.hpp:818
LIEF::assembly::riscv::OPCODE::VSSSEG5E64_V
@ VSSSEG5E64_V
Definition riscv/opcodes.hpp:13750
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF2_MASK
@ PseudoVSUXSEG2EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10684
LIEF::assembly::riscv::OPCODE::VFCLASS_V
@ VFCLASS_V
Definition riscv/opcodes.hpp:13206
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M2_MASK
@ PseudoVSSEG2E64_V_M2_MASK
Definition riscv/opcodes.hpp:10012
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M1_MASK
@ PseudoVLOXSEG4EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4669
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E16_MASK
@ PseudoVREDMINU_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:7833
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M2_MASK
@ PseudoVLOXSEG3EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:4561
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M1
@ PseudoVSUXEI8_V_M1_M1
Definition riscv/opcodes.hpp:10615
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E8_MASK
@ PseudoVDIV_VX_M4_E8_MASK
Definition riscv/opcodes.hpp:1578
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M8
@ PseudoVRGATHEREI16_VV_M8_E32_M8
Definition riscv/opcodes.hpp:8380
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M1_M1_MASK
@ PseudoVSUXSEG4EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10988
LIEF::assembly::riscv::OPCODE::VSOXSEG5EI32_V
@ VSOXSEG5EI32_V
Definition riscv/opcodes.hpp:13677
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_M1_MASK
@ PseudoVLOXSEG8EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4985
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E16
@ PseudoVDIVU_VV_M1_E16
Definition riscv/opcodes.hpp:1423
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M8_M1
@ PseudoVLOXSEG5EI64_V_M8_M1
Definition riscv/opcodes.hpp:4748
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M1_MASK
@ PseudoVSUXSEG3EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:10890
LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_MF2
@ PseudoVSPILL2_MF2
Definition riscv/opcodes.hpp:9834
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E8
@ PseudoVREDMIN_VS_M4_E8
Definition riscv/opcodes.hpp:7898
LIEF::assembly::riscv::OPCODE::FMAX_H_INX
@ FMAX_H_INX
Definition riscv/opcodes.hpp:12700
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M1_MASK
@ PseudoVRGATHEREI16_VV_M4_E16_M1_MASK
Definition riscv/opcodes.hpp:8339
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF4_E16
@ PseudoVFWMACCBF16_VV_MF4_E16
Definition riscv/opcodes.hpp:3723
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E64_MASK
@ PseudoVREM_VX_M8_E64_MASK
Definition riscv/opcodes.hpp:8245
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E16_MASK
@ PseudoVFMIN_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:2163
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF2
@ PseudoVSUXSEG4EI64_V_M2_MF2
Definition riscv/opcodes.hpp:10973
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M2
@ PseudoVSSSEG4E32_V_M2
Definition riscv/opcodes.hpp:10321
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M2_MASK
@ PseudoVMSNE_VV_M2_MASK
Definition riscv/opcodes.hpp:7238
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M2_M2
@ PseudoVLOXSEG3EI8_V_M2_M2
Definition riscv/opcodes.hpp:4556
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E32_MASK
@ PseudoVRGATHER_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:8467
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E16
@ PseudoVWREDSUM_VS_M4_E16
Definition riscv/opcodes.hpp:11659
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF2
@ PseudoVSUXSEG5EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:11023
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E32_MASK
@ PseudoVDIVU_VX_M4_E32_MASK
Definition riscv/opcodes.hpp:1486
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_MF2
@ PseudoVLUXSEG3EI32_V_M2_MF2
Definition riscv/opcodes.hpp:5902
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF2
@ PseudoVSSRL_VX_MF2
Definition riscv/opcodes.hpp:10241
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M2
@ PseudoVMSLTU_VV_M2
Definition riscv/opcodes.hpp:7166
LIEF::assembly::riscv::OPCODE::AMOXOR_H_RL
@ AMOXOR_H_RL
Definition riscv/opcodes.hpp:12110
LIEF::assembly::riscv::OPCODE::FNMSUB_H
@ FNMSUB_H
Definition riscv/opcodes.hpp:12746
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M1_MASK
@ PseudoVFCVT_RTZ_XU_F_V_M1_MASK
Definition riscv/opcodes.hpp:1816
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF4_E16_MASK
@ PseudoVFNMSAC_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2746
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_M1_MASK
@ PseudoVSOXSEG6EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9646
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF8
@ PseudoVSUXSEG4EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:11013
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF4
@ PseudoVLE8_V_MF4
Definition riscv/opcodes.hpp:4167
LIEF::assembly::riscv::OPCODE::TH_LRW
@ TH_LRW
Definition riscv/opcodes.hpp:13077
LIEF::assembly::riscv::OPCODE::FCVTMOD_W_D
@ FCVTMOD_W_D
Definition riscv/opcodes.hpp:12572
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF4
@ PseudoVAADDU_VV_MF4
Definition riscv/opcodes.hpp:531
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_MF2_MASK
@ PseudoVLSEG2E32FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5081
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF2_E16
@ PseudoVFNCVT_RM_F_X_W_MF2_E16
Definition riscv/opcodes.hpp:2519
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E32
@ PseudoVREDOR_VS_M2_E32
Definition riscv/opcodes.hpp:7930
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M2
@ PseudoVASUB_VX_M2
Definition riscv/opcodes.hpp:904
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E16_MASK
@ PseudoVREM_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:8205
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M1_MASK
@ PseudoVCLMULH_VV_M1_MASK
Definition riscv/opcodes.hpp:945
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M4
@ PseudoVSLL_VI_M4
Definition riscv/opcodes.hpp:8882
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_MF2
@ PseudoVLOXSEG5EI64_V_M4_MF2
Definition riscv/opcodes.hpp:4746
LIEF::assembly::riscv::OPCODE::CV_DOTSP_SC_B
@ CV_DOTSP_SC_B
Definition riscv/opcodes.hpp:12285
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF2_MASK
@ PseudoVLUXSEG2EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:5767
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E32_MASK
@ PseudoVFWMACC_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3752
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M2
@ PseudoVLOXSEG3EI16_V_MF2_M2
Definition riscv/opcodes.hpp:4484
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E32
@ PseudoVFNMADD_VV_MF2_E32
Definition riscv/opcodes.hpp:2731
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M2_MASK
@ PseudoVLUXSEG4EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:6039
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF4
@ PseudoVLUXSEG5EI32_V_M1_MF4
Definition riscv/opcodes.hpp:6106
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF2_MASK
@ PseudoVSUXEI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:10654
LIEF::assembly::riscv::OPCODE::VL2RE8_V
@ VL2RE8_V
Definition riscv/opcodes.hpp:13314
LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M1_MASK
@ PseudoVLE64FF_V_M1_MASK
Definition riscv/opcodes.hpp:4128
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_MF2
@ PseudoVRELOAD5_MF2
Definition riscv/opcodes.hpp:8069
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF8_MASK
@ PseudoVSSUB_VX_MF8_MASK
Definition riscv/opcodes.hpp:10474
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF2
@ PseudoVSE16_V_MF2
Definition riscv/opcodes.hpp:8710
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF8
@ PseudoVNSRA_WX_MF8
Definition riscv/opcodes.hpp:7588
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M1
@ PseudoVSADDU_VI_M1
Definition riscv/opcodes.hpp:8604
LIEF::assembly::riscv::OPCODE::C_LUI
@ C_LUI
Definition riscv/opcodes.hpp:12508
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_M1
@ PseudoVSOXSEG5EI16_V_M1_M1
Definition riscv/opcodes.hpp:9511
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF8
@ PseudoVLOXSEG6EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:4848
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E64
@ PseudoVFNMSUB_VV_M1_E64
Definition riscv/opcodes.hpp:2829
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M4
@ PseudoVMSLTU_VX_M4
Definition riscv/opcodes.hpp:7182
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_MF2_MASK
@ PseudoVLOXSEG7EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4879
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M2
@ PseudoVLOXSEG3EI32_V_M1_M2
Definition riscv/opcodes.hpp:4500
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E16_MASK
@ PseudoVDIVU_VX_M1_E16_MASK
Definition riscv/opcodes.hpp:1468
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M4_E32_MASK
@ PseudoVFNMSAC_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2752
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M4
@ PseudoVBREV_V_M4
Definition riscv/opcodes.hpp:934
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF8_MASK
@ PseudoVSSRL_VI_MF8_MASK
Definition riscv/opcodes.hpp:10218
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF8_MASK
@ PseudoVSOXSEG8EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:9830
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_MF2
@ PseudoVAESEM_VS_M2_MF2
Definition riscv/opcodes.hpp:733
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_MF2_MASK
@ PseudoVSOXSEG4EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9406
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M1
@ PseudoVFCVT_RTZ_XU_F_V_M1
Definition riscv/opcodes.hpp:1815
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF8_MASK
@ PseudoVLSEG5E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5277
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF4_MASK
@ PseudoVMFGT_VFPR16_MF4_MASK
Definition riscv/opcodes.hpp:6681
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_MF2
@ PseudoVLUXSEG2EI32_V_M2_MF2
Definition riscv/opcodes.hpp:5776
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M8_E64
@ PseudoVFMIN_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2160
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF2_MASK
@ PseudoVLOXSEG5EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4705
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B2_MASK
@ PseudoVMSIF_M_B2_MASK
Definition riscv/opcodes.hpp:7070
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M1_MASK
@ PseudoVASUB_VX_M1_MASK
Definition riscv/opcodes.hpp:903
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF8
@ PseudoVLSEG8E8_V_MF8
Definition riscv/opcodes.hpp:5396
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_M2
@ PseudoVAESDM_VS_M2_M2
Definition riscv/opcodes.hpp:674
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M4
@ PseudoVSOXEI16_V_M4_M4
Definition riscv/opcodes.hpp:9017
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M8_MASK
@ PseudoVSOXEI16_V_M8_M8_MASK
Definition riscv/opcodes.hpp:9024
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M8_MASK
@ PseudoVLE16_V_M8_MASK
Definition riscv/opcodes.hpp:4102
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M1_MASK
@ PseudoVCTZ_V_M1_MASK
Definition riscv/opcodes.hpp:1065
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M2
@ PseudoVNCLIPU_WV_M2
Definition riscv/opcodes.hpp:7440
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M8_MASK
@ PseudoVSUB_VV_M8_MASK
Definition riscv/opcodes.hpp:10482
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M2_MASK
@ PseudoVSSUB_VX_M2_MASK
Definition riscv/opcodes.hpp:10464
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF4_E16
@ PseudoVFWNMACC_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3847
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_M1
@ PseudoVLUXSEG3EI8_V_MF8_M1
Definition riscv/opcodes.hpp:5964
LIEF::assembly::riscv::OPCODE::ReadFRM
@ ReadFRM
Definition riscv/opcodes.hpp:11915
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF2_E16_MASK
@ PseudoVFMAX_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2066
LIEF::assembly::riscv::OPCODE::G_MUL
@ G_MUL
Definition riscv/opcodes.hpp:77
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M1
@ PseudoVLE16_V_M1
Definition riscv/opcodes.hpp:4095
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M1_MASK
@ PseudoVSOXEI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9000
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_MF4
@ PseudoVMV_V_X_MF4
Definition riscv/opcodes.hpp:7409
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF4_MASK
@ PseudoVSOXSEG6EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9616
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M8_E16_MASK
@ PseudoVFMIN_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2139
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF8_E8
@ PseudoVREDSUM_VS_MF8_E8
Definition riscv/opcodes.hpp:8006
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E8_MASK
@ PseudoVREMU_VV_M4_E8_MASK
Definition riscv/opcodes.hpp:8107
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4_MASK_TIED
@ PseudoVWSUB_WV_M4_MASK_TIED
Definition riscv/opcodes.hpp:11813
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF2_MASK
@ PseudoVLUXSEG7EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:6293
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_MF4
@ PseudoVMADC_VXM_MF4
Definition riscv/opcodes.hpp:6463
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M8
@ PseudoVMSBC_VXM_M8
Definition riscv/opcodes.hpp:6927
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E32_MASK
@ PseudoVDIV_VX_MF2_E32_MASK
Definition riscv/opcodes.hpp:1590
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M8_E32_MASK
@ PseudoVFMSUB_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2271
LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_M1
@ PseudoVMANDN_MM_M1
Definition riscv/opcodes.hpp:6500
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF4
@ PseudoVLUXSEG3EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:5880
LIEF::assembly::riscv::OPCODE::VFWSUB_VF
@ VFWSUB_VF
Definition riscv/opcodes.hpp:13299
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF4_MASK
@ PseudoVANDN_VV_MF4_MASK
Definition riscv/opcodes.hpp:801
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E32_MASK
@ PseudoVREDOR_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:7931
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M1
@ PseudoVSOXEI16_V_MF2_M1
Definition riscv/opcodes.hpp:9025
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF4_MASK
@ PseudoVSUXSEG4EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:11006
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF2
@ PseudoVSOXSEG3EI64_V_M2_MF2
Definition riscv/opcodes.hpp:9359
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E64
@ PseudoVREDXOR_VS_M2_E64
Definition riscv/opcodes.hpp:8020
LIEF::assembly::riscv::OPCODE::CV_ROR
@ CV_ROR
Definition riscv/opcodes.hpp:12389
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M2_MASK
@ PseudoVLSEG3E64_V_M2_MASK
Definition riscv/opcodes.hpp:5161
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF2
@ PseudoVMSGTU_VX_MF2
Definition riscv/opcodes.hpp:7031
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_MF2_MASK
@ PseudoVSOXSEG2EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:9248
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M1_MASK
@ PseudoVLUXSEG4EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:5979
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_MF4_MASK
@ PseudoVSSSEG4E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10318
LIEF::assembly::riscv::OPCODE::PATCHABLE_TYPED_EVENT_CALL
@ PATCHABLE_TYPED_EVENT_CALL
Definition riscv/opcodes.hpp:64
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64FF_V_M1
@ PseudoVLSEG6E64FF_V_M1
Definition riscv/opcodes.hpp:5298
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E16
@ PseudoVFMUL_VV_M1_E16
Definition riscv/opcodes.hpp:2342
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_M1_MASK
@ PseudoVLSSEG8E16_V_M1_MASK
Definition riscv/opcodes.hpp:5551
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E16_MASK
@ PseudoVFNCVT_F_X_W_MF2_E16_MASK
Definition riscv/opcodes.hpp:2484
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_M2
@ PseudoVC_V_FPR32VV_M2
Definition riscv/opcodes.hpp:1203
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF2
@ PseudoVSUXSEG4EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:11009
LIEF::assembly::riscv::OPCODE::AMOMAX_W_RL
@ AMOMAX_W_RL
Definition riscv/opcodes.hpp:12034
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M4
@ PseudoVLOXEI16_V_M4_M4
Definition riscv/opcodes.hpp:4196
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_M1_M1
@ PseudoVSOXSEG6EI8_V_M1_M1
Definition riscv/opcodes.hpp:9651
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E64
@ PseudoVFREDMAX_VS_M8_E64
Definition riscv/opcodes.hpp:2957
LIEF::assembly::riscv::OPCODE::FNMADD_S_INX
@ FNMADD_S_INX
Definition riscv/opcodes.hpp:12742
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_MF2_MF4
@ PseudoVSM4R_VS_MF2_MF4
Definition riscv/opcodes.hpp:8957
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF8_MASK
@ PseudoVLSSEG3E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5461
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_MF2
@ PseudoVLOXSEG8EI32_V_M2_MF2
Definition riscv/opcodes.hpp:4958
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M2_MASK
@ PseudoVLOXEI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4223
LIEF::assembly::riscv::OPCODE::AES32DSI
@ AES32DSI
Definition riscv/opcodes.hpp:11936
LIEF::assembly::riscv::OPCODE::PseudoLWU
@ PseudoLWU
Definition riscv/opcodes.hpp:400
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF2_MASK
@ PseudoVROR_VV_MF2_MASK
Definition riscv/opcodes.hpp:8557
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_MF2
@ PseudoVC_V_IVV_SE_MF2
Definition riscv/opcodes.hpp:1259
LIEF::assembly::riscv::OPCODE::VLSEG3E16FF_V
@ VLSEG3E16FF_V
Definition riscv/opcodes.hpp:13376
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M4_E32_MASK
@ PseudoVFWSUB_WFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:4006
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M1_MASK
@ PseudoVLUXEI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5613
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_M1_MASK
@ PseudoVLUXSEG6EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6211
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF8
@ PseudoVSSEG4E8_V_MF8
Definition riscv/opcodes.hpp:10081
LIEF::assembly::riscv::OPCODE::FMUL_S
@ FMUL_S
Definition riscv/opcodes.hpp:12725
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M2_MASK
@ PseudoVLOXSEG3EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:4551
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E16_MASK
@ PseudoVREDMIN_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:7909
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M1_MASK
@ PseudoVMSEQ_VV_M1_MASK
Definition riscv/opcodes.hpp:6967
LIEF::assembly::riscv::OPCODE::PseudoVMV_S_X
@ PseudoVMV_S_X
Definition riscv/opcodes.hpp:7389
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M1
@ PseudoVLUXSEG3EI64_V_M2_M1
Definition riscv/opcodes.hpp:5926
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E8_MASK
@ PseudoVREDMIN_VS_MF2_E8_MASK
Definition riscv/opcodes.hpp:7913
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B64
@ PseudoVMSOF_M_B64
Definition riscv/opcodes.hpp:7273
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF4_MASK
@ PseudoVSUXSEG7EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:11252
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M1
@ PseudoVAADDU_VV_M1
Definition riscv/opcodes.hpp:521
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_MF4_MASK
@ PseudoVFSLIDE1UP_VFPR16_MF4_MASK
Definition riscv/opcodes.hpp:3342
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M4
@ PseudoVSOXEI8_V_M1_M4
Definition riscv/opcodes.hpp:9115
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_M1
@ PseudoVSSEG6E8_V_M1
Definition riscv/opcodes.hpp:10115
LIEF::assembly::riscv::OPCODE::PseudoFROUND_H_INX
@ PseudoFROUND_H_INX
Definition riscv/opcodes.hpp:378
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF4_MASK
@ PseudoVMSNE_VX_MF4_MASK
Definition riscv/opcodes.hpp:7260
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_MF2_MASK
@ PseudoVSUXSEG7EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11240
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M4_MASK
@ PseudoVSRA_VI_M4_MASK
Definition riscv/opcodes.hpp:9868
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_M1_M1_MASK
@ PseudoVSUXSEG6EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11156
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E16_MASK
@ PseudoVFWMSAC_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3798
LIEF::assembly::riscv::OPCODE::CV_SW_rr_inc
@ CV_SW_rr_inc
Definition riscv/opcodes.hpp:12466
LIEF::assembly::riscv::OPCODE::G_INTRINSIC
@ G_INTRINSIC
Definition riscv/opcodes.hpp:145
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF4
@ PseudoVRGATHEREI16_VV_MF2_E16_MF4
Definition riscv/opcodes.hpp:8398
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M1_MASK
@ PseudoVLOXSEG2EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4379
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M8_E64_MASK
@ PseudoVFNMSAC_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2764
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF2_MASK
@ PseudoVLUXSEG8EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:6397
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF2_MASK
@ PseudoVSUXSEG7EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11198
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E32_MASK
@ PseudoVFWNMACC_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3868
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_MF2
@ PseudoVMSBC_VV_MF2
Definition riscv/opcodes.hpp:6921
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF2_E16_MASK
@ PseudoVFMUL_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2321
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF2
@ PseudoVSSEG8E16_V_MF2
Definition riscv/opcodes.hpp:10145
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF2_MASK
@ PseudoVLSEG7E16FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5321
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8
@ PseudoVWADD_WV_MF8
Definition riscv/opcodes.hpp:11439
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_M1
@ PseudoVLUXSEG8EI16_V_MF4_M1
Definition riscv/opcodes.hpp:6334
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E16_MASK
@ PseudoVFREC7_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:2930
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_M1
@ PseudoVLUXSEG7EI64_V_M4_M1
Definition riscv/opcodes.hpp:6296
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF8
@ PseudoVLOXSEG7EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:4928
LIEF::assembly::riscv::OPCODE::G_IMPLICIT_DEF
@ G_IMPLICIT_DEF
Definition riscv/opcodes.hpp:87
LIEF::assembly::riscv::OPCODE::CV_CMPNE_SCI_H
@ CV_CMPNE_SCI_H
Definition riscv/opcodes.hpp:12268
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E32
@ PseudoVFWMACCBF16_VV_MF2_E32
Definition riscv/opcodes.hpp:3721
LIEF::assembly::riscv::OPCODE::VLE16_V
@ VLE16_V
Definition riscv/opcodes.hpp:13324
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF4_E16_MASK
@ PseudoVFSUB_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3450
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M4
@ PseudoVWSUBU_WX_M4
Definition riscv/opcodes.hpp:11771
LIEF::assembly::riscv::OPCODE::VAADDU_VX
@ VAADDU_VX
Definition riscv/opcodes.hpp:13132
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E16
@ PseudoVFWREDOSUM_VS_MF2_E16
Definition riscv/opcodes.hpp:3927
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF8
@ PseudoVROL_VV_MF8
Definition riscv/opcodes.hpp:8518
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF4
@ PseudoVOR_VV_MF4
Definition riscv/opcodes.hpp:7650
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M2
@ PseudoVLUXEI16_V_M2_M2
Definition riscv/opcodes.hpp:5580
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF2_MASK
@ PseudoVLSEG3E8FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5167
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E8
@ PseudoVRGATHER_VV_M8_E8
Definition riscv/opcodes.hpp:8478
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF4_MASK
@ PseudoVSOXSEG5EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9556
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M1
@ PseudoVLOXSEG4EI8_V_MF4_M1
Definition riscv/opcodes.hpp:4674
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF4
@ PseudoVSOXSEG5EI32_V_M1_MF4
Definition riscv/opcodes.hpp:9535
LIEF::assembly::riscv::OPCODE::G_SEXTLOAD
@ G_SEXTLOAD
Definition riscv/opcodes.hpp:114
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M2_MASK
@ PseudoVSUXSEG3EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:10892
LIEF::assembly::riscv::OPCODE::VLSSEG8E16_V
@ VLSSEG8E16_V
Definition riscv/opcodes.hpp:13448
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF8_MASK
@ PseudoVLOXSEG6EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:4849
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_MF8
@ PseudoVC_V_VVW_MF8
Definition riscv/opcodes.hpp:1321
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M8
@ PseudoVMFLE_VV_M8
Definition riscv/opcodes.hpp:6736
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF2
@ PseudoVLUXSEG3EI64_V_M1_MF2
Definition riscv/opcodes.hpp:5920
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M4_MASK
@ PseudoVAND_VI_M4_MASK
Definition riscv/opcodes.hpp:823
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M4
@ PseudoVLUXSEG2EI8_V_M1_M4
Definition riscv/opcodes.hpp:5830
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B8_MASK
@ PseudoVMSOF_M_B8_MASK
Definition riscv/opcodes.hpp:7276
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E32_MASK
@ PseudoVFSGNJ_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3280
LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R_DIV2
@ CV_CPLXMUL_R_DIV2
Definition riscv/opcodes.hpp:12278
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M1_E16_MASK
@ PseudoVFWSUB_WFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3992
LIEF::assembly::riscv::OPCODE::G_FCONSTANT
@ G_FCONSTANT
Definition riscv/opcodes.hpp:152
LIEF::assembly::riscv::OPCODE::VLSEG8E16FF_V
@ VLSEG8E16FF_V
Definition riscv/opcodes.hpp:13416
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M1
@ PseudoVMFGE_VFPR32_M1
Definition riscv/opcodes.hpp:6652
LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_2x8x2_M4
@ PseudoVQMACCUS_2x8x2_M4
Definition riscv/opcodes.hpp:7678
LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B4
@ PseudoVLM_V_B4
Definition riscv/opcodes.hpp:4175
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M2_MASK
@ PseudoVRGATHEREI16_VV_M4_E16_M2_MASK
Definition riscv/opcodes.hpp:8341
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_UMAX
@ G_VECREDUCE_UMAX
Definition riscv/opcodes.hpp:315
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF2
@ PseudoVSOXSEG7EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:9685
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF4
@ PseudoVSLL_VV_MF4
Definition riscv/opcodes.hpp:8902
LIEF::assembly::riscv::OPCODE::VSSSEG8E32_V
@ VSSSEG8E32_V
Definition riscv/opcodes.hpp:13761
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M4_MASK
@ PseudoVSLL_VV_M4_MASK
Definition riscv/opcodes.hpp:8897
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E32_MASK
@ PseudoVFSQRT_V_M2_E32_MASK
Definition riscv/opcodes.hpp:3370
LIEF::assembly::riscv::OPCODE::VSSEG8E32_V
@ VSSEG8E32_V
Definition riscv/opcodes.hpp:13727
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_M1
@ PseudoVLSEG7E16FF_V_M1
Definition riscv/opcodes.hpp:5318
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_M1
@ PseudoVLUXEI32_V_MF2_M1
Definition riscv/opcodes.hpp:5642
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E32
@ PseudoVFCVT_RM_F_XU_V_M4_E32
Definition riscv/opcodes.hpp:1745
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M4_MASK
@ PseudoVLOXEI16_V_M4_M4_MASK
Definition riscv/opcodes.hpp:4197
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E64
@ PseudoVREDMIN_VS_M2_E64
Definition riscv/opcodes.hpp:7888
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M1
@ PseudoVSUXSEG4EI8_V_MF4_M1
Definition riscv/opcodes.hpp:10999
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E32_MASK
@ PseudoVFMSAC_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:2237
LIEF::assembly::riscv::OPCODE::PseudoVSETVLI
@ PseudoVSETVLI
Definition riscv/opcodes.hpp:8747
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF4_MASK
@ PseudoVMINU_VV_MF4_MASK
Definition riscv/opcodes.hpp:6837
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M4_M4_MASK
@ PseudoVSOXSEG2EI8_V_M4_M4_MASK
Definition riscv/opcodes.hpp:9266
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_M2
@ PseudoVSM4R_VS_M2_M2
Definition riscv/opcodes.hpp:8940
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E8_MASK
@ PseudoVDIV_VX_MF4_E8_MASK
Definition riscv/opcodes.hpp:1596
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M2
@ PseudoVSUXSEG4EI64_V_M8_M2
Definition riscv/opcodes.hpp:10985
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_MF8
@ PseudoVC_V_XVV_MF8
Definition riscv/opcodes.hpp:1348
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E8
@ PseudoVDIVU_VX_M1_E8
Definition riscv/opcodes.hpp:1473
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M2
@ PseudoVLOXSEG2EI64_V_M2_M2
Definition riscv/opcodes.hpp:4414
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M1_E16
@ PseudoVFWSUB_WFPR16_M1_E16
Definition riscv/opcodes.hpp:3991
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E8
@ PseudoVREDMINU_VS_M1_E8
Definition riscv/opcodes.hpp:7838
LIEF::assembly::riscv::OPCODE::FCVT_W_S
@ FCVT_W_S
Definition riscv/opcodes.hpp:12641
LIEF::assembly::riscv::OPCODE::TH_FLRD
@ TH_FLRD
Definition riscv/opcodes.hpp:13046
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M4_E16
@ PseudoVFWSUB_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3959
LIEF::assembly::riscv::OPCODE::G_MEMSET
@ G_MEMSET
Definition riscv/opcodes.hpp:295
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_M1
@ PseudoVSOXSEG4EI64_V_M1_M1
Definition riscv/opcodes.hpp:9457
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_M1_M1_MASK
@ PseudoVLUXSEG7EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6303
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M1_MASK
@ PseudoVLSE16_V_M1_MASK
Definition riscv/opcodes.hpp:5011
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF4_MASK
@ PseudoVAADD_VV_MF4_MASK
Definition riscv/opcodes.hpp:560
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E32
@ PseudoVFDIV_VV_M8_E32
Definition riscv/opcodes.hpp:1913
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_MF4
@ PseudoVC_V_VVV_SE_MF4
Definition riscv/opcodes.hpp:1314
LIEF::assembly::riscv::OPCODE::ADJCALLSTACKUP
@ ADJCALLSTACKUP
Definition riscv/opcodes.hpp:320
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M4
@ PseudoVMSNE_VI_M4
Definition riscv/opcodes.hpp:7225
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E64
@ PseudoVFNMADD_VV_M4_E64
Definition riscv/opcodes.hpp:2721
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_MF8
@ PseudoVRELOAD4_MF8
Definition riscv/opcodes.hpp:8067
LIEF::assembly::riscv::OPCODE::G_FREM
@ G_FREM
Definition riscv/opcodes.hpp:202
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E16_MASK
@ PseudoVFMSAC_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:2247
LIEF::assembly::riscv::OPCODE::CV_SLL_B
@ CV_SLL_B
Definition riscv/opcodes.hpp:12425
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF4_MASK
@ PseudoVLOXEI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4263
LIEF::assembly::riscv::OPCODE::VMSIF_M
@ VMSIF_M
Definition riscv/opcodes.hpp:13533
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2_MASK
@ PseudoVWSUB_WV_MF2_MASK
Definition riscv/opcodes.hpp:11816
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M4_E16
@ PseudoVFDIV_VFPR16_M4_E16
Definition riscv/opcodes.hpp:1867
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M8_M1_MASK
@ PseudoVSUXSEG5EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:11074
LIEF::assembly::riscv::OPCODE::G_FPOWI
@ G_FPOWI
Definition riscv/opcodes.hpp:204
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_M1_MASK
@ PseudoVLUXSEG4EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6021
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_M1
@ PseudoVSOXSEG5EI32_V_MF2_M1
Definition riscv/opcodes.hpp:9543
LIEF::assembly::riscv::OPCODE::VRGATHER_VX
@ VRGATHER_VX
Definition riscv/opcodes.hpp:13610
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_M1
@ PseudoVC_V_VV_SE_M1
Definition riscv/opcodes.hpp:1335
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M2
@ PseudoVLSEG4E32_V_M2
Definition riscv/opcodes.hpp:5206
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M2
@ PseudoVWSUBU_WX_M2
Definition riscv/opcodes.hpp:11769
LIEF::assembly::riscv::OPCODE::SM3P1
@ SM3P1
Definition riscv/opcodes.hpp:12992
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF8
@ PseudoVSUXSEG8EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:11273
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF2_MASK
@ PseudoVSSEG3E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10050
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M8_MASK
@ PseudoVMFLT_VFPR64_M8_MASK
Definition riscv/opcodes.hpp:6771
LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M2
@ PseudoVLE64_V_M2
Definition riscv/opcodes.hpp:4137
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M2
@ PseudoVWADD_WX_M2
Definition riscv/opcodes.hpp:11445
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M4
@ PseudoVSSUB_VV_M4
Definition riscv/opcodes.hpp:10451
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E64
@ PseudoVFNMACC_VV_M4_E64
Definition riscv/opcodes.hpp:2661
LIEF::assembly::riscv::OPCODE::G_SDIVREM
@ G_SDIVREM
Definition riscv/opcodes.hpp:82
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E16_MASK
@ PseudoVFWNMSAC_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3898
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF2_MASK
@ PseudoVSOXSEG2EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9228
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E64_MASK
@ PseudoVREDMINU_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:7837
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M1_E16_MASK
@ PseudoVFMAX_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:2058
LIEF::assembly::riscv::OPCODE::VLSSEG5E64_V
@ VLSSEG5E64_V
Definition riscv/opcodes.hpp:13438
LIEF::assembly::riscv::OPCODE::FCLASS_H
@ FCLASS_H
Definition riscv/opcodes.hpp:12568
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF4_MASK
@ PseudoVLOXSEG4EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4641
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF8
@ PseudoVLUXSEG6EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:6240
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E16_MASK
@ PseudoVREDSUM_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:7981
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF2
@ PseudoVZEXT_VF2_MF2
Definition riscv/opcodes.hpp:11889
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M8_MASK
@ PseudoVSOXEI8_V_M1_M8_MASK
Definition riscv/opcodes.hpp:9118
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E64
@ PseudoVFREDOSUM_VS_M8_E64
Definition riscv/opcodes.hpp:3017
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_MF2_E32
@ PseudoVFRDIV_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2895
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M4_MASK
@ PseudoVLOXSEG2EI32_V_M2_M4_MASK
Definition riscv/opcodes.hpp:4383
LIEF::assembly::riscv::OPCODE::FMSUB_H
@ FMSUB_H
Definition riscv/opcodes.hpp:12716
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M2_MASK
@ PseudoVMFGE_VFPR64_M2_MASK
Definition riscv/opcodes.hpp:6665
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E32_MASK
@ PseudoVFSGNJ_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:3292
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF2
@ PseudoVMSGT_VX_MF2
Definition riscv/opcodes.hpp:7059
LIEF::assembly::riscv::OPCODE::BEXTI
@ BEXTI
Definition riscv/opcodes.hpp:12123
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M2
@ PseudoVLSSEG2E16_V_M2
Definition riscv/opcodes.hpp:5400
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF4_MASK
@ PseudoVMSLE_VX_MF4_MASK
Definition riscv/opcodes.hpp:7160
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF2_MASK
@ PseudoVSSRA_VX_MF2_MASK
Definition riscv/opcodes.hpp:10200
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M1_MASK
@ PseudoVLOXSEG2EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4455
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF8_MASK
@ PseudoVSUXEI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:10658
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_MF2_MASK
@ PseudoVSSSEG4E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10324
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M1
@ PseudoVFCVT_X_F_V_M1
Definition riscv/opcodes.hpp:1851
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF8
@ PseudoVMSLE_VI_MF8
Definition riscv/opcodes.hpp:7133
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF4_MASK
@ PseudoVSADD_VX_MF4_MASK
Definition riscv/opcodes.hpp:8685
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M2_MASK
@ PseudoVSOXSEG2EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9158
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK
@ PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK
Definition riscv/opcodes.hpp:8413
LIEF::assembly::riscv::OPCODE::CV_CMPGE_B
@ CV_CMPGE_B
Definition riscv/opcodes.hpp:12223
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M2
@ PseudoVLUXEI8_V_MF4_M2
Definition riscv/opcodes.hpp:5712
LIEF::assembly::riscv::OPCODE::FCVT_S_L_INX
@ FCVT_S_L_INX
Definition riscv/opcodes.hpp:12624
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_M1_MASK
@ PseudoVLOXSEG3EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4519
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E8
@ PseudoVREDMIN_VS_MF4_E8
Definition riscv/opcodes.hpp:7916
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16_MASK
@ PseudoVFWSUB_WV_M2_E16_MASK
Definition riscv/opcodes.hpp:4018
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF2
@ PseudoVROR_VX_MF2
Definition riscv/opcodes.hpp:8570
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF2
@ PseudoVLOXSEG2EI64_V_M1_MF2
Definition riscv/opcodes.hpp:4406
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E16_MASK
@ PseudoVREDAND_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:7717
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M8_MASK
@ PseudoVSOXEI8_V_M2_M8_MASK
Definition riscv/opcodes.hpp:9124
LIEF::assembly::riscv::OPCODE::WFI
@ WFI
Definition riscv/opcodes.hpp:13844
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF2
@ PseudoVLSSEG5E8_V_MF2
Definition riscv/opcodes.hpp:5504
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF4_MASK
@ PseudoVSUXEI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:10650
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M1
@ PseudoVMSLE_VV_M1
Definition riscv/opcodes.hpp:7135
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF8_MASK
@ PseudoVWMACC_VX_MF8_MASK
Definition riscv/opcodes.hpp:11538
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E32_MASK
@ PseudoVREDMAXU_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:7779
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64FF_V_M1
@ PseudoVLSEG8E64FF_V_M1
Definition riscv/opcodes.hpp:5378
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M1_E16_MASK
@ PseudoVFWNMACC_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3840
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M1
@ PseudoVSOXSEG4EI64_V_M8_M1
Definition riscv/opcodes.hpp:9479
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF4_MASK
@ PseudoVSSEG5E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10088
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M1
@ PseudoVSBC_VXM_M1
Definition riscv/opcodes.hpp:8695
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF8
@ PseudoVSUXSEG3EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:10903
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF8
@ PseudoVSUXSEG5EI64_V_M1_MF8
Definition riscv/opcodes.hpp:11061
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M4_MASK
@ PseudoVAND_VX_M4_MASK
Definition riscv/opcodes.hpp:851
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2_TIED
@ PseudoVWSUBU_WV_MF2_TIED
Definition riscv/opcodes.hpp:11758
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M2_E32_MASK
@ PseudoVFWSUB_WFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:4004
LIEF::assembly::riscv::OPCODE::FLT_S
@ FLT_S
Definition riscv/opcodes.hpp:12683
LIEF::assembly::riscv::OPCODE::VSUXSEG7EI16_V
@ VSUXSEG7EI16_V
Definition riscv/opcodes.hpp:13794
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF2_E32
@ PseudoVFNCVT_RM_F_X_W_MF2_E32
Definition riscv/opcodes.hpp:2521
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M1_MASK
@ PseudoVSOXSEG2EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:9250
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E64
@ PseudoVREDMINU_VS_M4_E64
Definition riscv/opcodes.hpp:7852
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF4_E16_MASK
@ PseudoVFMACC_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:1996
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M4
@ PseudoVROL_VX_M4
Definition riscv/opcodes.hpp:8524
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_M1_MASK
@ PseudoVLOXSEG8EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4997
LIEF::assembly::riscv::OPCODE::G_BRCOND
@ G_BRCOND
Definition riscv/opcodes.hpp:142
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M2_M2
@ PseudoVSOXSEG3EI8_V_M2_M2
Definition riscv/opcodes.hpp:9377
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF8_MASK
@ PseudoVRGATHER_VX_MF8_MASK
Definition riscv/opcodes.hpp:8505
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF4
@ PseudoVLSSEG4E16_V_MF4
Definition riscv/opcodes.hpp:5468
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M2_MASK
@ PseudoVSUXEI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10520
LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ
@ CV_SUBROTMJ
Definition riscv/opcodes.hpp:12447
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M2
@ PseudoVLUXSEG3EI32_V_M2_M2
Definition riscv/opcodes.hpp:5900
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF8_MASK
@ PseudoVLOXEI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:4257
LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_M4
@ PseudoVC_IVV_SE_M4
Definition riscv/opcodes.hpp:1121
LIEF::assembly::riscv::OPCODE::VSETIVLI
@ VSETIVLI
Definition riscv/opcodes.hpp:13634
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M8_E16
@ PseudoVFMUL_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2318
LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M8
@ PseudoVADC_VIM_M8
Definition riscv/opcodes.hpp:580
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M1
@ PseudoVWADD_VX_M1
Definition riscv/opcodes.hpp:11407
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M2_M1
@ PseudoVLUXSEG8EI16_V_M2_M1
Definition riscv/opcodes.hpp:6326
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M2
@ PseudoVAND_VI_M2
Definition riscv/opcodes.hpp:820
LIEF::assembly::riscv::OPCODE::G_BLOCK_ADDR
@ G_BLOCK_ADDR
Definition riscv/opcodes.hpp:277
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF2_E16_MASK
@ PseudoVFRDIV_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2884
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_M1
@ PseudoVLOXSEG7EI16_V_MF2_M1
Definition riscv/opcodes.hpp:4856
LIEF::assembly::riscv::OPCODE::G_UDIV
@ G_UDIV
Definition riscv/opcodes.hpp:79
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M1
@ PseudoVLUXSEG2EI8_V_MF4_M1
Definition riscv/opcodes.hpp:5846
LIEF::assembly::riscv::OPCODE::CV_CMPGE_SC_H
@ CV_CMPGE_SC_H
Definition riscv/opcodes.hpp:12228
LIEF::assembly::riscv::OPCODE::XORI
@ XORI
Definition riscv/opcodes.hpp:13849
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M1
@ PseudoVSOXSEG4EI8_V_MF2_M1
Definition riscv/opcodes.hpp:9489
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_MF2
@ PseudoVLSSEG2E32_V_MF2
Definition riscv/opcodes.hpp:5414
LIEF::assembly::riscv::OPCODE::AMOSWAP_H
@ AMOSWAP_H
Definition riscv/opcodes.hpp:12091
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E32
@ PseudoVFWREDOSUM_VS_M1_E32
Definition riscv/opcodes.hpp:3913
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M4_E32_MASK
@ PseudoVFMSAC_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2209
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF4_E16
@ PseudoVFWCVT_F_F_V_MF4_E16
Definition riscv/opcodes.hpp:3575
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF2
@ PseudoVSUXSEG7EI64_V_M2_MF2
Definition riscv/opcodes.hpp:11225
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_M1
@ PseudoVSUXSEG3EI8_V_MF8_M1
Definition riscv/opcodes.hpp:10897
LIEF::assembly::riscv::OPCODE::DIVUW
@ DIVUW
Definition riscv/opcodes.hpp:12553
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M2_MASK
@ PseudoVSSE8_V_M2_MASK
Definition riscv/opcodes.hpp:9980
LIEF::assembly::riscv::OPCODE::G_UMAX
@ G_UMAX
Definition riscv/opcodes.hpp:241
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M2
@ PseudoVLUXSEG4EI16_V_MF2_M2
Definition riscv/opcodes.hpp:5986
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E16
@ PseudoVWREDSUM_VS_MF2_E16
Definition riscv/opcodes.hpp:11671
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M1_MASK
@ PseudoVSOXSEG3EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9292
LIEF::assembly::riscv::OPCODE::G_VAARG
@ G_VAARG
Definition riscv/opcodes.hpp:154
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M8
@ PseudoVMFEQ_VFPR16_M8
Definition riscv/opcodes.hpp:6604
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E16
@ PseudoVDIV_VV_MF2_E16
Definition riscv/opcodes.hpp:1543
LIEF::assembly::riscv::OPCODE::VMULH_VX
@ VMULH_VX
Definition riscv/opcodes.hpp:13553
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E16_MASK
@ PseudoVFWMSAC_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3790
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_M1_MASK
@ PseudoVSOXSEG5EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9552
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E32
@ PseudoVCOMPRESS_VM_M1_E32
Definition riscv/opcodes.hpp:1015
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_MF4
@ PseudoVAESZ_VS_M1_MF4
Definition riscv/opcodes.hpp:768
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M1
@ PseudoVLUXSEG2EI64_V_M8_M1
Definition riscv/opcodes.hpp:5820
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_MF2
@ PseudoVFMERGE_VFPR16M_MF2
Definition riscv/opcodes.hpp:2121
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VW_SE_M8
@ PseudoVC_FPR32VW_SE_M8
Definition riscv/opcodes.hpp:1104
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_MF8
@ PseudoVC_V_IV_SE_MF8
Definition riscv/opcodes.hpp:1287
LIEF::assembly::riscv::OPCODE::FCVT_D_S_INX
@ FCVT_D_S_INX
Definition riscv/opcodes.hpp:12583
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M1
@ PseudoVAESEF_VV_M1
Definition riscv/opcodes.hpp:722
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_M1
@ PseudoVC_V_XVW_SE_M1
Definition riscv/opcodes.hpp:1362
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M8_MASK
@ PseudoVFSLIDE1DOWN_VFPR32_M8_MASK
Definition riscv/opcodes.hpp:3320
LIEF::assembly::riscv::OPCODE::SRL
@ SRL
Definition riscv/opcodes.hpp:13000
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF4
@ PseudoVCLMUL_VV_MF4
Definition riscv/opcodes.hpp:982
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E16
@ PseudoVDIV_VX_MF2_E16
Definition riscv/opcodes.hpp:1587
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E64_MASK
@ PseudoVFREDOSUM_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:3018
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M4
@ PseudoVSSE8_V_M4
Definition riscv/opcodes.hpp:9981
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF8_MASK
@ PseudoVSMUL_VX_MF8_MASK
Definition riscv/opcodes.hpp:8991
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF4_MASK
@ PseudoVLSEG6E16FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5283
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF4_E16_MASK
@ PseudoVFMIN_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2143
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF8_MASK
@ PseudoVANDN_VV_MF8_MASK
Definition riscv/opcodes.hpp:803
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_MF8
@ PseudoVAESZ_VS_M2_MF8
Definition riscv/opcodes.hpp:774
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_M2
@ PseudoVC_V_IV_SE_M2
Definition riscv/opcodes.hpp:1282
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_M1_MASK
@ PseudoVSUXSEG7EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:11188
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32V_SE_M8
@ PseudoVC_FPR32V_SE_M8
Definition riscv/opcodes.hpp:1109
LIEF::assembly::riscv::OPCODE::QK_C_SHSP
@ QK_C_SHSP
Definition riscv/opcodes.hpp:12923
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_M1_M1
@ PseudoVLUXSEG5EI8_V_M1_M1
Definition riscv/opcodes.hpp:6142
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E64
@ PseudoVRGATHER_VV_M4_E64
Definition riscv/opcodes.hpp:8468
LIEF::assembly::riscv::OPCODE::C_FSDSP
@ C_FSDSP
Definition riscv/opcodes.hpp:12494
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF8_MASK
@ PseudoVSOXSEG6EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:9638
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E32
@ PseudoVFNCVTBF16_F_F_W_M1_E32
Definition riscv/opcodes.hpp:2419
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E8
@ PseudoVREDOR_VS_MF2_E8
Definition riscv/opcodes.hpp:7956
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF2
@ PseudoVSLIDEDOWN_VI_MF2
Definition riscv/opcodes.hpp:8830
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF4_MASK
@ PseudoVLSEG2E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5073
LIEF::assembly::riscv::OPCODE::CV_ADD_SC_B
@ CV_ADD_SC_B
Definition riscv/opcodes.hpp:12179
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_MF2_MASK
@ PseudoVLUXSEG8EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:6351
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF2
@ PseudoVRGATHEREI16_VV_MF4_E16_MF2
Definition riscv/opcodes.hpp:8418
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF8_MASK
@ PseudoVRGATHER_VI_MF8_MASK
Definition riscv/opcodes.hpp:8447
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M2
@ PseudoVSOXSEG2EI64_V_M8_M2
Definition riscv/opcodes.hpp:9251
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M4_MASK
@ PseudoVLOXEI16_V_M1_M4_MASK
Definition riscv/opcodes.hpp:4183
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_M1_M1
@ PseudoVLOXSEG6EI8_V_M1_M1
Definition riscv/opcodes.hpp:4830
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF4_MASK
@ PseudoVSSEG7E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10140
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M2
@ PseudoVLUXSEG2EI8_V_M1_M2
Definition riscv/opcodes.hpp:5828
LIEF::assembly::riscv::OPCODE::MOPR1
@ MOPR1
Definition riscv/opcodes.hpp:12861
LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ_DIV8
@ CV_SUBROTMJ_DIV8
Definition riscv/opcodes.hpp:12450
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E16
@ PseudoVREDSUM_VS_M1_E16
Definition riscv/opcodes.hpp:7964
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_MF2_MF4
@ PseudoVAESDF_VS_MF2_MF4
Definition riscv/opcodes.hpp:662
LIEF::assembly::riscv::OPCODE::CV_CMPGT_H
@ CV_CMPGT_H
Definition riscv/opcodes.hpp:12236
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M2_M1
@ PseudoVLUXSEG6EI16_V_M2_M1
Definition riscv/opcodes.hpp:6166
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_M1
@ PseudoVSOXSEG8EI16_V_M1_M1
Definition riscv/opcodes.hpp:9751
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF8
@ PseudoVLSEG4E8_V_MF8
Definition riscv/opcodes.hpp:5236
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_M1_MASK
@ PseudoVSUXSEG3EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:10816
LIEF::assembly::riscv::OPCODE::VSOXSEG5EI64_V
@ VSOXSEG5EI64_V
Definition riscv/opcodes.hpp:13678
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E16_MASK
@ PseudoVDIV_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:1520
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M4_MASK
@ PseudoVSADDU_VX_M4_MASK
Definition riscv/opcodes.hpp:8637
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M8_E64_MASK
@ PseudoVFRDIV_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2904
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E32_MASK
@ PseudoVFWCVT_F_XU_V_M4_E32_MASK
Definition riscv/opcodes.hpp:3592
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E8
@ PseudoVREDMIN_VS_M8_E8
Definition riscv/opcodes.hpp:7906
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E32
@ PseudoVDIV_VX_M2_E32
Definition riscv/opcodes.hpp:1565
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_MF2
@ PseudoVLUXSEG4EI64_V_M4_MF2
Definition riscv/opcodes.hpp:6048
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M1_MASK
@ PseudoVSUXSEG4EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10934
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M4
@ PseudoVLUXEI16_V_M1_M4
Definition riscv/opcodes.hpp:5574
LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_M1
@ PseudoVC_XV_SE_M1
Definition riscv/opcodes.hpp:1409
LIEF::assembly::riscv::OPCODE::VSRA_VV
@ VSRA_VV
Definition riscv/opcodes.hpp:13693
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF2
@ PseudoVWMACCU_VX_MF2
Definition riscv/opcodes.hpp:11509
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M4
@ PseudoVWADDU_VX_M4
Definition riscv/opcodes.hpp:11351
LIEF::assembly::riscv::OPCODE::VSSRL_VV
@ VSSRL_VV
Definition riscv/opcodes.hpp:13734
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S_M4
@ PseudoVFMV_FPR32_S_M4
Definition riscv/opcodes.hpp:2380
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E8
@ PseudoVREDOR_VS_M2_E8
Definition riscv/opcodes.hpp:7934
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M1
@ PseudoVMSBC_VVM_M1
Definition riscv/opcodes.hpp:6910
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF4
@ PseudoVMAX_VX_MF4
Definition riscv/opcodes.hpp:6566
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M1_E16_MASK
@ PseudoVFWMSAC_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3768
LIEF::assembly::riscv::OPCODE::FCVT_H_W_INX
@ FCVT_H_W_INX
Definition riscv/opcodes.hpp:12602
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M4_M2
@ PseudoVSOXSEG4EI16_V_M4_M2
Definition riscv/opcodes.hpp:9411
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VV_SE_M8
@ PseudoVC_FPR32VV_SE_M8
Definition riscv/opcodes.hpp:1099
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_MF2
@ PseudoVSOXSEG3EI32_V_M2_MF2
Definition riscv/opcodes.hpp:9331
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M1_MASK
@ PseudoVSSRL_VV_M1_MASK
Definition riscv/opcodes.hpp:10220
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_M1_MASK
@ PseudoVLUXSEG5EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6145
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M1_MASK
@ PseudoVADD_VX_M1_MASK
Definition riscv/opcodes.hpp:627
LIEF::assembly::riscv::OPCODE::VLUXSEG2EI16_V
@ VLUXSEG2EI16_V
Definition riscv/opcodes.hpp:13456
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M4
@ PseudoVZEXT_VF4_M4
Definition riscv/opcodes.hpp:11897
LIEF::assembly::riscv::OPCODE::VREM_VV
@ VREM_VV
Definition riscv/opcodes.hpp:13604
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF4_MASK
@ PseudoVMSNE_VV_MF4_MASK
Definition riscv/opcodes.hpp:7246
LIEF::assembly::riscv::OPCODE::C_MUL
@ C_MUL
Definition riscv/opcodes.hpp:12520
LIEF::assembly::riscv::OPCODE::G_BUILD_VECTOR_TRUNC
@ G_BUILD_VECTOR_TRUNC
Definition riscv/opcodes.hpp:98
LIEF::assembly::riscv::OPCODE::VLOXSEG4EI64_V
@ VLOXSEG4EI64_V
Definition riscv/opcodes.hpp:13346
LIEF::assembly::riscv::OPCODE::C_ADDIW
@ C_ADDIW
Definition riscv/opcodes.hpp:12479
LIEF::assembly::riscv::OPCODE::VLUXSEG4EI8_V
@ VLUXSEG4EI8_V
Definition riscv/opcodes.hpp:13467
LIEF::assembly::riscv::OPCODE::VLOXSEG7EI32_V
@ VLOXSEG7EI32_V
Definition riscv/opcodes.hpp:13357
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF2_MASK
@ PseudoVWMUL_VV_MF2_MASK
Definition riscv/opcodes.hpp:11594
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF2_MF2_MASK
@ PseudoVSOXSEG7EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9736
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF2_MASK
@ PseudoVCPOP_V_MF2_MASK
Definition riscv/opcodes.hpp:1059
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E16
@ PseudoVREDAND_VS_MF2_E16
Definition riscv/opcodes.hpp:7732
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M8_M1
@ PseudoVLUXSEG6EI64_V_M8_M1
Definition riscv/opcodes.hpp:6220
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M2
@ PseudoVSUXEI32_V_M8_M2
Definition riscv/opcodes.hpp:10569
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_M8
@ PseudoVFWMACC_4x4x4_M8
Definition riscv/opcodes.hpp:3728
LIEF::assembly::riscv::OPCODE::G_CTLZ
@ G_CTLZ
Definition riscv/opcodes.hpp:257
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF8_MASK
@ PseudoVLOXSEG2EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:4403
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF8_MASK
@ PseudoVSOXEI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:9078
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF4_MASK
@ PseudoVSOXEI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9146
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF4
@ PseudoVSSSEG2E8_V_MF4
Definition riscv/opcodes.hpp:10279
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E16_MASK
@ PseudoVFDIV_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:1900
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF4
@ PseudoVSUXSEG7EI64_V_M2_MF4
Definition riscv/opcodes.hpp:11227
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF2
@ PseudoVLSEG5E16_V_MF2
Definition riscv/opcodes.hpp:5246
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M4
@ PseudoVAESDM_VV_M4
Definition riscv/opcodes.hpp:695
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF2
@ PseudoVMSLE_VX_MF2
Definition riscv/opcodes.hpp:7157
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M2
@ PseudoVLOXEI32_V_M4_M2
Definition riscv/opcodes.hpp:4238
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E32
@ PseudoVFMAX_VV_M8_E32
Definition riscv/opcodes.hpp:2107
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M8
@ PseudoVRGATHER_VI_M8
Definition riscv/opcodes.hpp:8440
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M2_MASK
@ PseudoVLUXSEG4EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:6017
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M4
@ PseudoVNMSAC_VV_M4
Definition riscv/opcodes.hpp:7502
LIEF::assembly::riscv::OPCODE::SFENCE_W_INVAL
@ SFENCE_W_INVAL
Definition riscv/opcodes.hpp:12954
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M1
@ PseudoVSOXSEG3EI64_V_M8_M1
Definition riscv/opcodes.hpp:9369
LIEF::assembly::riscv::OPCODE::SUBREG_TO_REG
@ SUBREG_TO_REG
Definition riscv/opcodes.hpp:35
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M4
@ PseudoVMADC_VX_M4
Definition riscv/opcodes.hpp:6467
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M8_MASK
@ PseudoVSOXEI8_V_M4_M8_MASK
Definition riscv/opcodes.hpp:9128
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M8
@ PseudoVMADD_VV_M8
Definition riscv/opcodes.hpp:6478
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF4_MASK
@ PseudoVSOXSEG8EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:9828
LIEF::assembly::riscv::OPCODE::PseudoFROUND_S
@ PseudoFROUND_S
Definition riscv/opcodes.hpp:379
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M4_MASK
@ PseudoVRGATHER_VI_M4_MASK
Definition riscv/opcodes.hpp:8439
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M2_MASK
@ PseudoVLUXEI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:5599
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF2_MASK
@ PseudoVWMACCUS_VX_MF2_MASK
Definition riscv/opcodes.hpp:11486
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF2_MASK
@ PseudoVSUB_VX_MF2_MASK
Definition riscv/opcodes.hpp:10498
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E8
@ PseudoVREMU_VV_M8_E8
Definition riscv/opcodes.hpp:8114
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E32
@ PseudoVREDAND_VS_M4_E32
Definition riscv/opcodes.hpp:7718
LIEF::assembly::riscv::OPCODE::FENCE_I
@ FENCE_I
Definition riscv/opcodes.hpp:12651
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M4_MASK
@ PseudoVSRL_VI_M4_MASK
Definition riscv/opcodes.hpp:9910
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF8
@ PseudoVASUBU_VV_MF8
Definition riscv/opcodes.hpp:872
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_M1
@ PseudoVSSEG8E16_V_M1
Definition riscv/opcodes.hpp:10143
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF8_MASK
@ PseudoVWMUL_VX_MF8_MASK
Definition riscv/opcodes.hpp:11610
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M2_MASK
@ PseudoVSOXSEG3EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:9306
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF2_MASK
@ PseudoVLOXSEG3EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4487
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M4
@ PseudoVMFLT_VFPR64_M4
Definition riscv/opcodes.hpp:6768
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M2
@ PseudoVSUXSEG4EI8_V_MF2_M2
Definition riscv/opcodes.hpp:10995
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_M1
@ PseudoVLUXSEG7EI32_V_MF2_M1
Definition riscv/opcodes.hpp:6274
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E32
@ PseudoVFMUL_VV_M2_E32
Definition riscv/opcodes.hpp:2350
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M2_MASK
@ PseudoVSLIDE1DOWN_VX_M2_MASK
Definition riscv/opcodes.hpp:8797
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF2_MASK
@ PseudoVFCVT_XU_F_V_MF2_MASK
Definition riscv/opcodes.hpp:1848
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M2
@ PseudoVSSEG2E16_V_M2
Definition riscv/opcodes.hpp:9993
LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_MF2_MASK
@ PseudoVLE32_V_MF2_MASK
Definition riscv/opcodes.hpp:4126
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_MF2_MASK
@ PseudoVLSEG4E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5209
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF4
@ PseudoVSOXSEG8EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:9827
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E8
@ PseudoVREDMIN_VS_M1_E8
Definition riscv/opcodes.hpp:7882
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_M1_MASK
@ PseudoVSUXSEG5EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:11028
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M1_MASK
@ PseudoVMSLE_VI_M1_MASK
Definition riscv/opcodes.hpp:7122
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M2_E16_MASK
@ PseudoVFWADD_WFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3490
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M1_MASK
@ PseudoVLUXSEG2EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5763
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF2
@ PseudoVLOXSEG3EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:4492
LIEF::assembly::riscv::OPCODE::VFWCVT_XU_F_V
@ VFWCVT_XU_F_V
Definition riscv/opcodes.hpp:13282
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M1
@ PseudoVROL_VV_M1
Definition riscv/opcodes.hpp:8506
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_M1_MASK
@ PseudoVSOXSEG5EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9574
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_M1
@ PseudoVLOXSEG2EI16_V_MF4_M1
Definition riscv/opcodes.hpp:4362
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E32
@ PseudoVFWMSAC_VV_M4_E32
Definition riscv/opcodes.hpp:3795
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M8_MASK
@ PseudoVMAXU_VX_M8_MASK
Definition riscv/opcodes.hpp:6535
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M8_MASK
@ PseudoVSSRL_VX_M8_MASK
Definition riscv/opcodes.hpp:10240
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M1_MASK
@ PseudoVLOXSEG4EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:4659
LIEF::assembly::riscv::OPCODE::PseudoLongBLT
@ PseudoLongBLT
Definition riscv/opcodes.hpp:404
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_MF2_MASK
@ PseudoVLOXEI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:4281
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF8_MASK
@ PseudoVCLMUL_VX_MF8_MASK
Definition riscv/opcodes.hpp:999
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E64_MASK
@ PseudoVFREDMAX_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:2958
LIEF::assembly::riscv::OPCODE::CV_CMPLTU_H
@ CV_CMPLTU_H
Definition riscv/opcodes.hpp:12254
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E32_MASK
@ PseudoVFWCVT_F_X_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:3628
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_MF8
@ PseudoVRELOAD2_MF8
Definition riscv/opcodes.hpp:8057
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E8_MASK
@ PseudoVRGATHER_VV_MF4_E8_MASK
Definition riscv/opcodes.hpp:8489
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M8
@ PseudoVRGATHEREI16_VV_M8_E8_M8
Definition riscv/opcodes.hpp:8392
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_M4
@ PseudoVAESZ_VS_M4_M4
Definition riscv/opcodes.hpp:777
LIEF::assembly::riscv::OPCODE::AMOSWAP_D
@ AMOSWAP_D
Definition riscv/opcodes.hpp:12087
LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B16
@ PseudoVMSET_M_B16
Definition riscv/opcodes.hpp:6995
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF8
@ PseudoVSRA_VX_MF8
Definition riscv/opcodes.hpp:9903
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF2_E16_MASK
@ PseudoVFWMACC_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3738
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M8_MASK
@ PseudoVSLIDEDOWN_VI_M8_MASK
Definition riscv/opcodes.hpp:8829
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF4_MASK
@ PseudoVLOXSEG4EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:4687
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_MF2_MASK
@ PseudoVSUXSEG7EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11178
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF4_MASK
@ PseudoVLUXSEG6EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:6173
LIEF::assembly::riscv::OPCODE::CV_MIN_B
@ CV_MIN_B
Definition riscv/opcodes.hpp:12364
LIEF::assembly::riscv::OPCODE::QK_C_SB
@ QK_C_SB
Definition riscv/opcodes.hpp:12920
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E32
@ PseudoVFCVT_RM_F_XU_V_M1_E32
Definition riscv/opcodes.hpp:1733
LIEF::assembly::riscv::OPCODE::CBO_ZERO
@ CBO_ZERO
Definition riscv/opcodes.hpp:12137
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF8
@ PseudoVWSUB_VX_MF8
Definition riscv/opcodes.hpp:11801
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M8_M8_MASK
@ PseudoVLUXEI8_V_M8_M8_MASK
Definition riscv/opcodes.hpp:5701
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_MF2_E32
@ PseudoVFWMSAC_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3783
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF2_MASK
@ PseudoVLOXSEG8EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4945
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF8_MASK
@ PseudoVLUXSEG4EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:6027
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4_TIED
@ PseudoVWADD_WV_MF4_TIED
Definition riscv/opcodes.hpp:11438
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_M1
@ PseudoVLOXSEG8EI8_V_MF8_M1
Definition riscv/opcodes.hpp:5002
LIEF::assembly::riscv::OPCODE::AND
@ AND
Definition riscv/opcodes.hpp:12115
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_M1_MASK
@ PseudoVSSEG5E8_V_M1_MASK
Definition riscv/opcodes.hpp:10096
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF2
@ PseudoVSUXSEG4EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:10955
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF4_MASK
@ PseudoVLUXSEG2EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:5769
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E16_MASK
@ PseudoVFREDUSUM_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:3038
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_MF2_E32_MASK
@ PseudoVFNMACC_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2636
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF2_MASK
@ PseudoVLSEG8E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5393
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E16
@ PseudoVDIVU_VV_MF4_E16
Definition riscv/opcodes.hpp:1461
LIEF::assembly::riscv::OPCODE::FROUND_H
@ FROUND_H
Definition riscv/opcodes.hpp:12754
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M8_MASK
@ PseudoVNMSAC_VV_M8_MASK
Definition riscv/opcodes.hpp:7505
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M2
@ PseudoVMSLTU_VX_M2
Definition riscv/opcodes.hpp:7180
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_MF2_MASK
@ PseudoVLUXSEG3EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:5867
LIEF::assembly::riscv::OPCODE::TH_LURB
@ TH_LURB
Definition riscv/opcodes.hpp:13079
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF4
@ PseudoVLOXEI8_V_MF8_MF4
Definition riscv/opcodes.hpp:4330
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF4
@ PseudoVFNCVT_RM_XU_F_W_MF4
Definition riscv/opcodes.hpp:2533
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M1
@ PseudoVSSUBU_VV_M1
Definition riscv/opcodes.hpp:10419
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF2
@ PseudoVNMSAC_VX_MF2
Definition riscv/opcodes.hpp:7520
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E16_MASK
@ PseudoVFCVT_RM_F_X_V_M1_E16_MASK
Definition riscv/opcodes.hpp:1762
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_M1
@ PseudoVLOXSEG6EI32_V_M2_M1
Definition riscv/opcodes.hpp:4796
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E32_MASK
@ PseudoVFWCVT_F_F_V_M1_E32_MASK
Definition riscv/opcodes.hpp:3562
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M2_MASK
@ PseudoVSUXSEG3EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10826
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M4_MASK
@ PseudoVLUXEI16_V_M1_M4_MASK
Definition riscv/opcodes.hpp:5575
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M4_MASK
@ PseudoVSOXEI32_V_M8_M4_MASK
Definition riscv/opcodes.hpp:9068
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M8
@ PseudoVFMERGE_VFPR16M_M8
Definition riscv/opcodes.hpp:2120
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_MF4
@ PseudoVLUXSEG2EI32_V_M1_MF4
Definition riscv/opcodes.hpp:5768
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_M1
@ PseudoVSOXSEG6EI64_V_M2_M1
Definition riscv/opcodes.hpp:9639
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_MF2_MASK
@ PseudoVLUXSEG4EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6065
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E32
@ PseudoVREM_VX_MF2_E32
Definition riscv/opcodes.hpp:8250
LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_M2
@ PseudoVC_VV_SE_M2
Definition riscv/opcodes.hpp:1160
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF2
@ PseudoVSOXSEG4EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:9423
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E16_MASK
@ PseudoVFREDOSUM_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:3008
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E32
@ PseudoVFREDMAX_VS_M1_E32
Definition riscv/opcodes.hpp:2937
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M4
@ PseudoVMSLE_VI_M4
Definition riscv/opcodes.hpp:7125
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF8
@ PseudoVMSNE_VX_MF8
Definition riscv/opcodes.hpp:7261
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E32_MASK
@ PseudoVDIV_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:1522
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF4_MASK
@ PseudoVSOXSEG4EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9436
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E64
@ PseudoVREDMAXU_VS_M2_E64
Definition riscv/opcodes.hpp:7756
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M2_E64_MASK
@ PseudoVFSGNJ_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:3266
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M1_E64_MASK
@ PseudoVFNMACC_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2638
LIEF::assembly::riscv::OPCODE::CV_EXTBS
@ CV_EXTBS
Definition riscv/opcodes.hpp:12300
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M2
@ PseudoVSOXSEG2EI8_V_MF4_M2
Definition riscv/opcodes.hpp:9277
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M2_MASK
@ PseudoVNSRL_WV_M2_MASK
Definition riscv/opcodes.hpp:7605
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF8
@ PseudoVSUXSEG5EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:11053
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF4_MASK
@ PseudoVXOR_VI_MF4_MASK
Definition riscv/opcodes.hpp:11850
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF2
@ PseudoVSSEG2E16_V_MF2
Definition riscv/opcodes.hpp:9997
LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M2
@ PseudoVADC_VVM_M2
Definition riscv/opcodes.hpp:585
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E16_MASK
@ PseudoVFWMUL_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3834
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E16
@ PseudoVFMADD_VV_M1_E16
Definition riscv/opcodes.hpp:2027
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF4
@ PseudoVLOXSEG3EI64_V_M1_MF4
Definition riscv/opcodes.hpp:4530
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E16
@ PseudoVFMACC_VV_M1_E16
Definition riscv/opcodes.hpp:1967
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_MF2
@ PseudoVSUXSEG7EI32_V_M1_MF2
Definition riscv/opcodes.hpp:11197
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF4
@ PseudoVSE8_V_MF4
Definition riscv/opcodes.hpp:8742
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF4
@ PseudoVAADD_VV_MF4
Definition riscv/opcodes.hpp:559
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_M1_MASK
@ PseudoVLUXSEG5EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:6155
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF8_E8
@ PseudoVDIVU_VX_MF8_E8
Definition riscv/opcodes.hpp:1509
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF2
@ PseudoVSUXSEG6EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:11169
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF2
@ PseudoVLUXSEG8EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:6356
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M2
@ PseudoVLUXSEG4EI8_V_MF2_M2
Definition riscv/opcodes.hpp:6062
LIEF::assembly::riscv::OPCODE::VFSGNJX_VF
@ VFSGNJX_VF
Definition riscv/opcodes.hpp:13263
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E32
@ PseudoVDIVU_VX_M8_E32
Definition riscv/opcodes.hpp:1493
LIEF::assembly::riscv::OPCODE::FMV_X_W
@ FMV_X_W
Definition riscv/opcodes.hpp:12734
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32_M1
@ PseudoVFMV_S_FPR32_M1
Definition riscv/opcodes.hpp:2393
LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B64
@ PseudoVMCLR_M_B64
Definition riscv/opcodes.hpp:6575
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E32
@ PseudoVFSUB_VV_M1_E32
Definition riscv/opcodes.hpp:3423
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M1
@ PseudoVMULH_VX_M1
Definition riscv/opcodes.hpp:7347
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M8_MASK
@ PseudoVSE16_V_M8_MASK
Definition riscv/opcodes.hpp:8709
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M2_MASK
@ PseudoVLUXSEG3EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:5947
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M2_MASK
@ PseudoVMFLT_VFPR16_M2_MASK
Definition riscv/opcodes.hpp:6745
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M2_MASK
@ PseudoVWMACCU_VX_M2_MASK
Definition riscv/opcodes.hpp:11506
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M2_E16_MASK
@ PseudoVFSGNJ_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3244
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF2
@ PseudoVFNRCLIP_XU_F_QF_MF2
Definition riscv/opcodes.hpp:2859
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E32_MASK
@ PseudoVREDMAXU_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:7755
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B1
@ PseudoVMSIF_M_B1
Definition riscv/opcodes.hpp:7065
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M2_MASK
@ PseudoVSLIDEDOWN_VI_M2_MASK
Definition riscv/opcodes.hpp:8825
LIEF::assembly::riscv::OPCODE::VSSRA_VI
@ VSSRA_VI
Definition riscv/opcodes.hpp:13730
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E32_MASK
@ PseudoVREDMIN_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:7903
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E32
@ PseudoVFSGNJN_VV_M4_E32
Definition riscv/opcodes.hpp:3165
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF2_MASK
@ PseudoVAND_VX_MF2_MASK
Definition riscv/opcodes.hpp:855
LIEF::assembly::riscv::OPCODE::FLW
@ FLW
Definition riscv/opcodes.hpp:12685
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_MF2
@ PseudoVSSEG4E32_V_MF2
Definition riscv/opcodes.hpp:10067
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF8_MASK
@ PseudoVSUXSEG6EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:11174
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E16_MASK
@ PseudoVREDSUM_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:8003
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E16
@ PseudoVFWMACCBF16_VV_M2_E16
Definition riscv/opcodes.hpp:3711
LIEF::assembly::riscv::OPCODE::VSOXSEG8EI8_V
@ VSOXSEG8EI8_V
Definition riscv/opcodes.hpp:13691
LIEF::assembly::riscv::OPCODE::FSGNJX_D_IN32X
@ FSGNJX_D_IN32X
Definition riscv/opcodes.hpp:12765
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF4_MASK
@ PseudoVLOXSEG8EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4967
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M1
@ PseudoVMAX_VV_M1
Definition riscv/opcodes.hpp:6542
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E16
@ PseudoVFRSQRT7_V_M4_E16
Definition riscv/opcodes.hpp:3073
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M1_MASK
@ PseudoVSSEG2E16_V_M1_MASK
Definition riscv/opcodes.hpp:9992
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M4_E32
@ PseudoVFSGNJX_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3197
LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_M8
@ PseudoVMNAND_MM_M8
Definition riscv/opcodes.hpp:6885
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF4_MASK
@ PseudoVLSEG2E8FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5111
LIEF::assembly::riscv::OPCODE::G_JUMP_TABLE
@ G_JUMP_TABLE
Definition riscv/opcodes.hpp:278
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M1_MASK
@ PseudoVMSNE_VX_M1_MASK
Definition riscv/opcodes.hpp:7250
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M2
@ PseudoVSOXEI64_V_M2_M2
Definition riscv/opcodes.hpp:9089
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF4_MASK
@ PseudoVSOXSEG2EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9230
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M8_M8_MASK
@ PseudoVSOXEI8_V_M8_M8_MASK
Definition riscv/opcodes.hpp:9130
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E32
@ PseudoVFWREDUSUM_VS_M1_E32
Definition riscv/opcodes.hpp:3935
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_MF2_E32
@ PseudoVFSUB_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3411
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF2
@ PseudoVSOXEI8_V_MF8_MF2
Definition riscv/opcodes.hpp:9149
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF4_MASK
@ PseudoVSUXSEG2EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:10702
LIEF::assembly::riscv::OPCODE::TH_LBUIA
@ TH_LBUIA
Definition riscv/opcodes.hpp:13063
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M4_MASK
@ PseudoVSUXEI8_V_M4_M4_MASK
Definition riscv/opcodes.hpp:10630
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E64_MASK
@ PseudoVREDMIN_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:7889
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M4
@ PseudoVLOXEI32_V_M8_M4
Definition riscv/opcodes.hpp:4246
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_MF2
@ PseudoVSOXSEG4EI32_V_M2_MF2
Definition riscv/opcodes.hpp:9441
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M2_MASK
@ PseudoVMFGT_VFPR64_M2_MASK
Definition riscv/opcodes.hpp:6695
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF2_MASK
@ PseudoVSUXSEG5EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11058
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E32_MASK
@ PseudoVFMADD_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:2036
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_M1
@ PseudoVLOXSEG4EI64_V_M1_M1
Definition riscv/opcodes.hpp:4636
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_MF2
@ PseudoVMFLT_VFPR32_MF2
Definition riscv/opcodes.hpp:6762
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF2_MASK
@ PseudoVSADDU_VI_MF2_MASK
Definition riscv/opcodes.hpp:8613
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_M1
@ PseudoVSUXSEG2EI32_V_MF2_M1
Definition riscv/opcodes.hpp:10721
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M1
@ PseudoVSOXEI64_V_M2_M1
Definition riscv/opcodes.hpp:9087
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M4_MASK
@ PseudoVSOXEI16_V_M8_M4_MASK
Definition riscv/opcodes.hpp:9022
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M1
@ PseudoVWMACC_VX_M1
Definition riscv/opcodes.hpp:11527
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M4
@ PseudoVMFEQ_VFPR16_M4
Definition riscv/opcodes.hpp:6602
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_M1_MASK
@ PseudoVLUXEI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:5719
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF2
@ PseudoVAND_VX_MF2
Definition riscv/opcodes.hpp:854
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_MF2
@ PseudoVSUXSEG4EI64_V_M4_MF2
Definition riscv/opcodes.hpp:10981
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M2
@ PseudoVNMSAC_VX_M2
Definition riscv/opcodes.hpp:7514
LIEF::assembly::riscv::OPCODE::VIOTA_M
@ VIOTA_M
Definition riscv/opcodes.hpp:13306
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_MF2
@ PseudoVSUXSEG7EI16_V_M1_MF2
Definition riscv/opcodes.hpp:11177
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M4
@ PseudoVMSLEU_VX_M4
Definition riscv/opcodes.hpp:7111
LIEF::assembly::riscv::OPCODE::VSHA2MS_VV
@ VSHA2MS_VV
Definition riscv/opcodes.hpp:13642
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M2
@ PseudoVLUXSEG3EI8_V_MF2_M2
Definition riscv/opcodes.hpp:5952
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E32
@ PseudoVWREDSUM_VS_M8_E32
Definition riscv/opcodes.hpp:11667
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF4
@ PseudoVLSSEG3E16_V_MF4
Definition riscv/opcodes.hpp:5440
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M1
@ PseudoVLUXEI8_V_MF4_M1
Definition riscv/opcodes.hpp:5710
LIEF::assembly::riscv::OPCODE::CV_BSET
@ CV_BSET
Definition riscv/opcodes.hpp:12204
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M4_MASK
@ PseudoVSUXSEG2EI32_V_M4_M4_MASK
Definition riscv/opcodes.hpp:10716
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M2
@ PseudoVSUXEI64_V_M4_M2
Definition riscv/opcodes.hpp:10601
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_MF8
@ PseudoVSM4R_VS_M8_MF8
Definition riscv/opcodes.hpp:8955
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF4_MASK
@ PseudoVSOXSEG3EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9352
LIEF::assembly::riscv::OPCODE::FLE_S
@ FLE_S
Definition riscv/opcodes.hpp:12669
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M8
@ PseudoVIOTA_M_M8
Definition riscv/opcodes.hpp:4075
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF8
@ PseudoVBREV8_V_MF8
Definition riscv/opcodes.hpp:928
LIEF::assembly::riscv::OPCODE::CV_MIN_SC_B
@ CV_MIN_SC_B
Definition riscv/opcodes.hpp:12368
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E8_MASK
@ PseudoVREDMAXU_VS_M8_E8_MASK
Definition riscv/opcodes.hpp:7775
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF8
@ PseudoVLOXSEG3EI64_V_M1_MF8
Definition riscv/opcodes.hpp:4532
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_M1_MASK
@ PseudoVSOXSEG8EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:9824
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E32_MASK
@ PseudoVFCVT_F_XU_V_M8_E32_MASK
Definition riscv/opcodes.hpp:1692
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF8_MASK
@ PseudoVMULH_VV_MF8_MASK
Definition riscv/opcodes.hpp:7346
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E8_MASK
@ PseudoVFWCVT_F_X_V_MF4_E8_MASK
Definition riscv/opcodes.hpp:3634
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_M1_MASK
@ PseudoVLUXSEG5EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6123
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M2
@ PseudoVSUXSEG2EI16_V_M4_M2
Definition riscv/opcodes.hpp:10673
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_MF8
@ PseudoVMV_V_I_MF8
Definition riscv/opcodes.hpp:7396
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M8
@ PseudoVSUXEI32_V_M8_M8
Definition riscv/opcodes.hpp:10573
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF2
@ PseudoVRGATHEREI16_VV_MF2_E16_MF2
Definition riscv/opcodes.hpp:8396
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E16_MASK
@ PseudoVFWMUL_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3830
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF4
@ PseudoVNCLIP_WX_MF4
Definition riscv/opcodes.hpp:7494
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_MF2_MASK
@ PseudoVLOXSEG7EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4853
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E32_MASK
@ PseudoVFNCVT_F_F_W_M4_E32_MASK
Definition riscv/opcodes.hpp:2446
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF2
@ PseudoVMSNE_VI_MF2
Definition riscv/opcodes.hpp:7229
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M4
@ PseudoVXOR_VX_M4
Definition riscv/opcodes.hpp:11871
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E32_MASK
@ PseudoVFREDMIN_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:2974
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E8
@ PseudoVDIV_VX_M2_E8
Definition riscv/opcodes.hpp:1569
LIEF::assembly::riscv::OPCODE::C_ADDW
@ C_ADDW
Definition riscv/opcodes.hpp:12482
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF4
@ PseudoVLSE16_V_MF4
Definition riscv/opcodes.hpp:5020
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_MF4
@ PseudoVAESDM_VS_M1_MF4
Definition riscv/opcodes.hpp:671
LIEF::assembly::riscv::OPCODE::CV_SH_ri_inc
@ CV_SH_ri_inc
Definition riscv/opcodes.hpp:12420
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF2_MASK
@ PseudoVSRA_VV_MF2_MASK
Definition riscv/opcodes.hpp:9886
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B8_MASK
@ PseudoVCPOP_M_B8_MASK
Definition riscv/opcodes.hpp:1049
LIEF::assembly::riscv::OPCODE::VC_V_IV
@ VC_V_IV
Definition riscv/opcodes.hpp:13186
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF8_MASK
@ PseudoVLUXSEG2EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:5803
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M8
@ PseudoVLOXEI16_V_M2_M8
Definition riscv/opcodes.hpp:4192
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_M8
@ PseudoVC_V_XVV_SE_M8
Definition riscv/opcodes.hpp:1352
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M8
@ PseudoVMSNE_VI_M8
Definition riscv/opcodes.hpp:7227
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E16_MASK
@ PseudoVDIV_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:1544
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M8_MASK
@ PseudoVSSRA_VX_M8_MASK
Definition riscv/opcodes.hpp:10198
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M1_MASK
@ PseudoVLSSEG4E64_V_M1_MASK
Definition riscv/opcodes.hpp:5477
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF8
@ PseudoVWADDU_VV_MF8
Definition riscv/opcodes.hpp:11345
LIEF::assembly::riscv::OPCODE::AMOXOR_W_AQ
@ AMOXOR_W_AQ
Definition riscv/opcodes.hpp:12112
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF8_MASK
@ PseudoVSUXEI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:10582
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_M1
@ PseudoVAESDF_VS_M4_M1
Definition riscv/opcodes.hpp:649
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF8
@ PseudoVSOXSEG7EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:9749
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E16
@ PseudoVFNMADD_VV_M8_E16
Definition riscv/opcodes.hpp:2723
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M8_MASK
@ PseudoVBREV8_V_M8_MASK
Definition riscv/opcodes.hpp:923
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK
@ PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK
Definition riscv/opcodes.hpp:2576
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M8
@ PseudoVMSLEU_VI_M8
Definition riscv/opcodes.hpp:7085
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF2
@ PseudoVLOXSEG6EI64_V_M2_MF2
Definition riscv/opcodes.hpp:4820
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M4
@ PseudoVMULHU_VX_M4
Definition riscv/opcodes.hpp:7323
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E16_MASK
@ PseudoVREMU_VX_M1_E16_MASK
Definition riscv/opcodes.hpp:8129
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_SE_M8
@ PseudoVC_V_FPR64VV_SE_M8
Definition riscv/opcodes.hpp:1239
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M8_E16_MASK
@ PseudoVFSGNJN_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:3128
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E16
@ PseudoVFSUB_VV_MF2_E16
Definition riscv/opcodes.hpp:3445
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF4
@ PseudoVSUB_VV_MF4
Definition riscv/opcodes.hpp:10485
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M4
@ PseudoVLUXEI16_V_M8_M4
Definition riscv/opcodes.hpp:5592
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M1
@ PseudoVCPOP_V_M1
Definition riscv/opcodes.hpp:1050
LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M4_MASK
@ PseudoVLE64_V_M4_MASK
Definition riscv/opcodes.hpp:4140
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_M1_MASK
@ PseudoVSOXSEG5EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9512
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M4
@ PseudoVLOXEI8_V_M2_M4
Definition riscv/opcodes.hpp:4300
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M4_MASK
@ PseudoVNSRA_WV_M4_MASK
Definition riscv/opcodes.hpp:7571
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E16_MASK
@ PseudoVFNCVT_F_F_W_M4_E16_MASK
Definition riscv/opcodes.hpp:2444
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M1
@ PseudoVMUL_VV_M1
Definition riscv/opcodes.hpp:7361
LIEF::assembly::riscv::OPCODE::CM_JALT
@ CM_JALT
Definition riscv/opcodes.hpp:12143
LIEF::assembly::riscv::OPCODE::G_INTRINSIC_LRINT
@ G_INTRINSIC_LRINT
Definition riscv/opcodes.hpp:108
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M1
@ PseudoTHVdotVMAQAUS_VX_M1
Definition riscv/opcodes.hpp:470
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF2_MASK
@ PseudoVSOXSEG3EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9390
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF2_MASK
@ PseudoVSUXSEG5EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:11084
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M1_E16_MASK
@ PseudoVFMUL_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:2313
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF4_E16
@ PseudoVFDIV_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:1873
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M1_MASK
@ PseudoVLSEG3E16FF_V_M1_MASK
Definition riscv/opcodes.hpp:5127
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E16_MASK
@ PseudoVFNCVT_F_XU_W_M2_E16_MASK
Definition riscv/opcodes.hpp:2458
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M4_M4_MASK
@ PseudoVSUXSEG2EI8_V_M4_M4_MASK
Definition riscv/opcodes.hpp:10770
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF4
@ PseudoVLUXSEG7EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:6312
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_M1
@ PseudoVC_V_FPR16V_M1
Definition riscv/opcodes.hpp:1190
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M8_E64
@ PseudoVFMUL_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2340
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF2
@ PseudoVSSEG3E8_V_MF2
Definition riscv/opcodes.hpp:10049
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF8_MASK
@ PseudoVSOXEI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:9086
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M4
@ PseudoVLSEG2E32FF_V_M4
Definition riscv/opcodes.hpp:5078
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E32
@ PseudoVFMSAC_VV_MF2_E32
Definition riscv/opcodes.hpp:2248
LIEF::assembly::riscv::OPCODE::SF_CDISCARD_D_L1
@ SF_CDISCARD_D_L1
Definition riscv/opcodes.hpp:12955
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M1
@ PseudoVASUBU_VV_M1
Definition riscv/opcodes.hpp:860
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF4_MASK
@ PseudoVMSLEU_VI_MF4_MASK
Definition riscv/opcodes.hpp:7090
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF4_MASK
@ PseudoVLOXSEG6EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4815
LIEF::assembly::riscv::OPCODE::AES32ESI
@ AES32ESI
Definition riscv/opcodes.hpp:11938
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_MF2
@ PseudoVRGATHEREI16_VV_M2_E32_MF2
Definition riscv/opcodes.hpp:8320
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF4_E16
@ PseudoVFNCVT_RM_F_X_W_MF4_E16
Definition riscv/opcodes.hpp:2523
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF4
@ PseudoVLUXSEG6EI64_V_M2_MF4
Definition riscv/opcodes.hpp:6214
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M2
@ PseudoVLUXSEG2EI64_V_M4_M2
Definition riscv/opcodes.hpp:5814
LIEF::assembly::riscv::OPCODE::VSSUBU_VV
@ VSSUBU_VV
Definition riscv/opcodes.hpp:13764
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF4
@ PseudoVLOXSEG4EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:4680
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF4
@ PseudoVSOXSEG3EI64_V_M1_MF4
Definition riscv/opcodes.hpp:9351
LIEF::assembly::riscv::OPCODE::FMADD_D_INX
@ FMADD_D_INX
Definition riscv/opcodes.hpp:12688
LIEF::assembly::riscv::OPCODE::G_INSERT
@ G_INSERT
Definition riscv/opcodes.hpp:95
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF2_MASK
@ PseudoVSOXSEG4EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9434
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M4_MASK
@ PseudoVLOXSEG2EI64_V_M4_M4_MASK
Definition riscv/opcodes.hpp:4425
LIEF::assembly::riscv::OPCODE::FSGNJX_D_INX
@ FSGNJX_D_INX
Definition riscv/opcodes.hpp:12766
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E64
@ PseudoVFMACC_VV_M1_E64
Definition riscv/opcodes.hpp:1971
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M2
@ PseudoVWMUL_VV_M2
Definition riscv/opcodes.hpp:11589
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M8_M1
@ PseudoVLOXSEG6EI64_V_M8_M1
Definition riscv/opcodes.hpp:4828
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_M1_MASK
@ PseudoVLUXSEG4EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6029
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M8
@ PseudoVSEXT_VF4_M8
Definition riscv/opcodes.hpp:8767
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M4_MASK
@ PseudoVLUXSEG2EI8_V_M1_M4_MASK
Definition riscv/opcodes.hpp:5831
LIEF::assembly::riscv::OPCODE::VLUXEI8_V
@ VLUXEI8_V
Definition riscv/opcodes.hpp:13455
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E64_MASK
@ PseudoVFNMSAC_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:2782
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M1_MASK
@ PseudoVFNCVT_RM_X_F_W_M1_MASK
Definition riscv/opcodes.hpp:2538
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_MF8
@ PseudoVAESZ_VS_M1_MF8
Definition riscv/opcodes.hpp:769
LIEF::assembly::riscv::OPCODE::CV_AND_SCI_B
@ CV_AND_SCI_B
Definition riscv/opcodes.hpp:12183
LIEF::assembly::riscv::OPCODE::CV_EXTRACTR
@ CV_EXTRACTR
Definition riscv/opcodes.hpp:12305
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M2_E32
@ PseudoVFWNMSAC_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3887
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E32
@ PseudoVFADD_VV_M2_E32
Definition riscv/opcodes.hpp:1637
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E32
@ PseudoVREMU_VX_M1_E32
Definition riscv/opcodes.hpp:8130
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M1_E32
@ PseudoVFMSAC_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2204
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M2
@ PseudoVLOXSEG4EI32_V_M4_M2
Definition riscv/opcodes.hpp:4624
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF4
@ PseudoVSUXSEG3EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:10901
LIEF::assembly::riscv::OPCODE::VSM3C_VI
@ VSM3C_VI
Definition riscv/opcodes.hpp:13652
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_SE_M1
@ PseudoVC_V_FPR32VW_SE_M1
Definition riscv/opcodes.hpp:1217
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF4
@ PseudoVWSLL_VI_MF4
Definition riscv/opcodes.hpp:11691
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF4
@ PseudoVSOXSEG7EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:9687
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32
@ PseudoVFWADD_WV_M2_E32
Definition riscv/opcodes.hpp:3517
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VV_SE_M1
@ PseudoVC_FPR32VV_SE_M1
Definition riscv/opcodes.hpp:1096
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M2
@ PseudoVLOXSEG4EI8_V_MF4_M2
Definition riscv/opcodes.hpp:4676
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF8_MASK_TIED
@ PseudoVWADD_WV_MF8_MASK_TIED
Definition riscv/opcodes.hpp:11441
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_MF2_MF2
@ PseudoVAESEF_VS_MF2_MF2
Definition riscv/opcodes.hpp:719
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M4_MASK
@ PseudoVLOXSEG2EI16_V_M4_M4_MASK
Definition riscv/opcodes.hpp:4351
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK
@ PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK
Definition riscv/opcodes.hpp:8337
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF4
@ PseudoVSUXSEG4EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:10957
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M2_MASK
@ PseudoVSRA_VV_M2_MASK
Definition riscv/opcodes.hpp:9880
LIEF::assembly::riscv::OPCODE::CV_SW_ri_inc
@ CV_SW_ri_inc
Definition riscv/opcodes.hpp:12464
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF4_MASK
@ PseudoVFCVT_X_F_V_MF4_MASK
Definition riscv/opcodes.hpp:1862
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M2_MASK
@ PseudoVLUXSEG2EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:5849
LIEF::assembly::riscv::OPCODE::VLSSEG8E32_V
@ VLSSEG8E32_V
Definition riscv/opcodes.hpp:13449
LIEF::assembly::riscv::OPCODE::VMUL_VV
@ VMUL_VV
Definition riscv/opcodes.hpp:13554
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF8_MASK
@ PseudoVLOXSEG2EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:4411
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E16_MASK
@ PseudoVFWREDUSUM_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:3938
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E16_MASK
@ PseudoVREDXOR_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:8017
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_MF2_MASK
@ PseudoVLSSEG2E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5415
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M8_E32_MASK
@ PseudoVFDIV_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:1882
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M2_MASK
@ PseudoVSSSEG3E64_V_M2_MASK
Definition riscv/opcodes.hpp:10300
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF2
@ PseudoVSOXSEG7EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:9679
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M4_E16_MASK
@ PseudoVFRSUB_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3096
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_M1
@ PseudoVSOXSEG7EI16_V_M1_M1
Definition riscv/opcodes.hpp:9671
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M1
@ PseudoVSUXEI16_V_MF2_M1
Definition riscv/opcodes.hpp:10529
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF8_MASK
@ PseudoVNCLIP_WV_MF8_MASK
Definition riscv/opcodes.hpp:7485
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_MF2_MASK
@ PseudoVLUXSEG8EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6325
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E16_MASK
@ PseudoVFWREDUSUM_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:3946
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF8_E8
@ PseudoVREDMAXU_VS_MF8_E8
Definition riscv/opcodes.hpp:7786
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M4
@ PseudoVFNCVT_RTZ_X_F_W_M4
Definition riscv/opcodes.hpp:2583
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M2_MASK
@ PseudoVLSSEG2E32_V_M2_MASK
Definition riscv/opcodes.hpp:5411
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_M1_MASK
@ PseudoVLOXSEG7EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:4923
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M4_MASK
@ PseudoVNSRL_WX_M4_MASK
Definition riscv/opcodes.hpp:7619
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M8
@ PseudoVSRA_VX_M8
Definition riscv/opcodes.hpp:9897
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_M4
@ PseudoVC_V_IV_SE_M4
Definition riscv/opcodes.hpp:1283
LIEF::assembly::riscv::OPCODE::AMOMAX_B
@ AMOMAX_B
Definition riscv/opcodes.hpp:12019
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M8
@ PseudoVRGATHEREI16_VV_M8_E64_M8
Definition riscv/opcodes.hpp:8386
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E32_MASK
@ PseudoVFNCVT_F_XU_W_M4_E32_MASK
Definition riscv/opcodes.hpp:2464
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E16
@ PseudoVFMIN_VV_M1_E16
Definition riscv/opcodes.hpp:2162
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF4
@ PseudoVWMUL_VX_MF4
Definition riscv/opcodes.hpp:11607
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_MF2_MASK
@ PseudoVLOXSEG6EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:4827
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF8_E8_MASK
@ PseudoVREDMAXU_VS_MF8_E8_MASK
Definition riscv/opcodes.hpp:7787
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E32
@ PseudoVFNMSAC_VV_M8_E32
Definition riscv/opcodes.hpp:2785
LIEF::assembly::riscv::OPCODE::VSSEG8E64_V
@ VSSEG8E64_V
Definition riscv/opcodes.hpp:13728
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF8
@ PseudoVNMSUB_VX_MF8
Definition riscv/opcodes.hpp:7552
LIEF::assembly::riscv::OPCODE::VLUXSEG7EI64_V
@ VLUXSEG7EI64_V
Definition riscv/opcodes.hpp:13478
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M2_MASK
@ PseudoVCLMULH_VV_M2_MASK
Definition riscv/opcodes.hpp:947
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M1_E16
@ PseudoVFWMACCBF16_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3697
LIEF::assembly::riscv::OPCODE::AMOADD_B_AQ
@ AMOADD_B_AQ
Definition riscv/opcodes.hpp:11948
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E32_MASK
@ PseudoVFWMACCBF16_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3710
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF2
@ PseudoVLUXSEG2EI64_V_M2_MF2
Definition riscv/opcodes.hpp:5808
LIEF::assembly::riscv::OPCODE::AMOXOR_H_AQ
@ AMOXOR_H_AQ
Definition riscv/opcodes.hpp:12108
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M8
@ PseudoVCLMULH_VV_M8
Definition riscv/opcodes.hpp:950
LIEF::assembly::riscv::OPCODE::AMOMAXU_B_RL
@ AMOMAXU_B_RL
Definition riscv/opcodes.hpp:12006
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF2
@ PseudoVSSSEG5E8_V_MF2
Definition riscv/opcodes.hpp:10353
LIEF::assembly::riscv::OPCODE::VLUXSEG8EI64_V
@ VLUXSEG8EI64_V
Definition riscv/opcodes.hpp:13482
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E16
@ PseudoVREDOR_VS_MF2_E16
Definition riscv/opcodes.hpp:7952
LIEF::assembly::riscv::OPCODE::TH_DCACHE_CALL
@ TH_DCACHE_CALL
Definition riscv/opcodes.hpp:13028
LIEF::assembly::riscv::OPCODE::AMOSWAP_B_RL
@ AMOSWAP_B_RL
Definition riscv/opcodes.hpp:12086
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M1_E32
@ PseudoVFWADD_WFPR32_M1_E32
Definition riscv/opcodes.hpp:3497
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF2
@ PseudoVSOXEI64_V_M2_MF2
Definition riscv/opcodes.hpp:9091
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E16
@ PseudoVFWCVT_F_X_V_MF4_E16
Definition riscv/opcodes.hpp:3631
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M4
@ PseudoVSOXEI32_V_M4_M4
Definition riscv/opcodes.hpp:9061
LIEF::assembly::riscv::OPCODE::VASUB_VX
@ VASUB_VX
Definition riscv/opcodes.hpp:13160
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF2_MASK
@ PseudoVSSSEG6E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10374
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M2
@ PseudoVLUXSEG2EI32_V_M1_M2
Definition riscv/opcodes.hpp:5764
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF2_MASK
@ PseudoVLUXSEG3EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:5961
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E64
@ PseudoVFMUL_VV_M1_E64
Definition riscv/opcodes.hpp:2346
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M2
@ PseudoVFSLIDE1UP_VFPR32_M2
Definition riscv/opcodes.hpp:3345
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF2
@ PseudoVSSE16_V_MF2
Definition riscv/opcodes.hpp:9955
LIEF::assembly::riscv::OPCODE::C_XOR
@ C_XOR
Definition riscv/opcodes.hpp:12547
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF8
@ PseudoVSSUBU_VX_MF8
Definition riscv/opcodes.hpp:10445
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E32
@ PseudoVREDMIN_VS_M8_E32
Definition riscv/opcodes.hpp:7902
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF4
@ PseudoVLUXSEG7EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:6318
LIEF::assembly::riscv::OPCODE::CV_MACHHSRN
@ CV_MACHHSRN
Definition riscv/opcodes.hpp:12335
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E64
@ PseudoVDIVU_VX_M2_E64
Definition riscv/opcodes.hpp:1479
LIEF::assembly::riscv::OPCODE::AMOSWAP_H_RL
@ AMOSWAP_H_RL
Definition riscv/opcodes.hpp:12094
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF4
@ PseudoVLUXSEG3EI64_V_M1_MF4
Definition riscv/opcodes.hpp:5922
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF4
@ PseudoVSOXSEG4EI64_V_M1_MF4
Definition riscv/opcodes.hpp:9461
LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32_AQ_RL
@ AMOCAS_D_RV32_AQ_RL
Definition riscv/opcodes.hpp:11985
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_M1_MASK
@ PseudoVLUXSEG2EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5797
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF8_MASK
@ PseudoVSSSEG4E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10338
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF4_MASK
@ PseudoVSUXSEG8EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:11272
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_MF2
@ PseudoVLSEG6E32_V_MF2
Definition riscv/opcodes.hpp:5296
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF4_E16_MASK
@ PseudoVFRDIV_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2886
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M2_MASK
@ PseudoVLUXEI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:5637
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M2_MASK
@ PseudoVLOXEI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4299
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M8
@ PseudoVMADC_VX_M8
Definition riscv/opcodes.hpp:6468
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M4_MASK
@ PseudoVWSUBU_VX_M4_MASK
Definition riscv/opcodes.hpp:11736
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_MF4
@ PseudoVMADC_VI_MF4
Definition riscv/opcodes.hpp:6442
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_MF2
@ PseudoVLSEG4E32_V_MF2
Definition riscv/opcodes.hpp:5208
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M2_MASK
@ PseudoVLOXEI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4189
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M4
@ PseudoVMACC_VV_M4
Definition riscv/opcodes.hpp:6406
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E32
@ PseudoVFRSQRT7_V_M4_E32
Definition riscv/opcodes.hpp:3075
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M1
@ PseudoVLUXSEG3EI8_V_MF4_M1
Definition riscv/opcodes.hpp:5956
LIEF::assembly::riscv::OPCODE::G_SELECT
@ G_SELECT
Definition riscv/opcodes.hpp:169
LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I_DIV4
@ CV_CPLXMUL_I_DIV4
Definition riscv/opcodes.hpp:12275
LIEF::assembly::riscv::OPCODE::MOPRR0
@ MOPRR0
Definition riscv/opcodes.hpp:12892
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E64_MASK
@ PseudoVFCVT_F_XU_V_M2_E64_MASK
Definition riscv/opcodes.hpp:1682
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF2
@ PseudoVSUXSEG7EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:11183
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_M4
@ PseudoVC_V_FPR16VV_SE_M4
Definition riscv/opcodes.hpp:1174
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF4
@ PseudoVLSEG2E8FF_V_MF4
Definition riscv/opcodes.hpp:5110
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M1_MASK
@ PseudoVAADD_VV_M1_MASK
Definition riscv/opcodes.hpp:550
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF4_MASK
@ PseudoVSOXSEG7EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9696
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF4
@ PseudoVFWCVT_XU_F_V_MF4
Definition riscv/opcodes.hpp:3685
LIEF::assembly::riscv::OPCODE::REMW
@ REMW
Definition riscv/opcodes.hpp:12927
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E16_MASK
@ PseudoVFWCVT_F_F_V_M2_E16_MASK
Definition riscv/opcodes.hpp:3564
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M1
@ PseudoVSUXSEG2EI64_V_M8_M1
Definition riscv/opcodes.hpp:10753
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF8_E8
@ PseudoVWREDSUMU_VS_MF8_E8
Definition riscv/opcodes.hpp:11645
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_M1_MASK
@ PseudoVLUXSEG6EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6163
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_M1_MASK
@ PseudoVSUXSEG5EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11056
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_M1_MASK
@ PseudoVSSSEG8E16_V_M1_MASK
Definition riscv/opcodes.hpp:10400
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M4
@ PseudoVFMERGE_VFPR64M_M4
Definition riscv/opcodes.hpp:2130
LIEF::assembly::riscv::OPCODE::CV_DOTUSP_H
@ CV_DOTUSP_H
Definition riscv/opcodes.hpp:12294
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_M1_MASK
@ PseudoVLSEG5E16FF_V_M1_MASK
Definition riscv/opcodes.hpp:5239
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M4
@ PseudoVLOXEI8_V_M1_M4
Definition riscv/opcodes.hpp:4294
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF4_MASK
@ PseudoVSOXEI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9084
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF2_MASK
@ PseudoVLOXSEG3EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4569
LIEF::assembly::riscv::OPCODE::JUMP_TABLE_DEBUG_INFO
@ JUMP_TABLE_DEBUG_INFO
Definition riscv/opcodes.hpp:67
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E16_MASK
@ PseudoVREM_VX_MF2_E16_MASK
Definition riscv/opcodes.hpp:8249
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E32
@ PseudoVFREC7_V_M1_E32
Definition riscv/opcodes.hpp:2907
LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M4
@ PseudoVSHA2CL_VV_M4
Definition riscv/opcodes.hpp:8786
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M2_MASK
@ PseudoVLUXSEG3EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:5959
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E32
@ PseudoVFRSQRT7_V_M8_E32
Definition riscv/opcodes.hpp:3081
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_MF2
@ PseudoVAESEM_VS_M8_MF2
Definition riscv/opcodes.hpp:745
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M2
@ PseudoVSADDU_VX_M2
Definition riscv/opcodes.hpp:8634
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF4_MASK
@ PseudoVSUXSEG4EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:10924
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF4_MASK
@ PseudoVSOXSEG8EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9796
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_MF2
@ PseudoVLUXSEG5EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:6146
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF8_MASK
@ PseudoVLUXEI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:5649
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF2
@ PseudoVSRA_VV_MF2
Definition riscv/opcodes.hpp:9885
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_M2
@ PseudoVC_V_IVV_SE_M2
Definition riscv/opcodes.hpp:1256
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF2_MASK
@ PseudoVSADDU_VX_MF2_MASK
Definition riscv/opcodes.hpp:8641
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF2
@ PseudoVNCLIPU_WX_MF2
Definition riscv/opcodes.hpp:7456
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M8_MASK
@ PseudoVASUB_VX_M8_MASK
Definition riscv/opcodes.hpp:909
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_M4
@ PseudoVAESEM_VS_M4_M4
Definition riscv/opcodes.hpp:738
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M2_MASK
@ PseudoVWSUBU_VX_M2_MASK
Definition riscv/opcodes.hpp:11734
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF4_MASK
@ PseudoVLSEG8E16FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5363
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M4
@ PseudoVMIN_VV_M4
Definition riscv/opcodes.hpp:6858
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_MF4
@ PseudoVMSBC_VVM_MF4
Definition riscv/opcodes.hpp:6915
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF2_MASK
@ PseudoVLOXSEG5EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4699
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M4_M1_MASK
@ PseudoVLUXSEG7EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:6297
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF8_MASK
@ PseudoVMACC_VX_MF8_MASK
Definition riscv/opcodes.hpp:6429
LIEF::assembly::riscv::OPCODE::G_ZEXT
@ G_ZEXT
Definition riscv/opcodes.hpp:157
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF4_MASK
@ PseudoVZEXT_VF2_MF4_MASK
Definition riscv/opcodes.hpp:11892
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E32_MASK
@ PseudoVREM_VX_M1_E32_MASK
Definition riscv/opcodes.hpp:8219
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M2_MASK
@ PseudoVWMULSU_VV_M2_MASK
Definition riscv/opcodes.hpp:11542
LIEF::assembly::riscv::OPCODE::QK_C_LHUSP
@ QK_C_LHUSP
Definition riscv/opcodes.hpp:12919
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M2
@ PseudoVMSGT_VI_M2
Definition riscv/opcodes.hpp:7039
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_M4
@ PseudoVC_V_FPR64VV_M4
Definition riscv/opcodes.hpp:1234
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M2
@ PseudoVFSLIDE1DOWN_VFPR64_M2
Definition riscv/opcodes.hpp:3325
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16_MASK
@ PseudoVFWADD_WV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3530
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M8
@ PseudoVSUXEI8_V_M4_M8
Definition riscv/opcodes.hpp:10631
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E16
@ PseudoVFREDOSUM_VS_MF2_E16
Definition riscv/opcodes.hpp:3019
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_MF2
@ PseudoVC_V_IV_MF2
Definition riscv/opcodes.hpp:1278
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32
@ PseudoVFWSUB_WV_M2_E32
Definition riscv/opcodes.hpp:4021
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M2
@ PseudoVSUXSEG3EI32_V_M4_M2
Definition riscv/opcodes.hpp:10839
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E16_MASK
@ PseudoVFNCVT_F_X_W_M4_E16_MASK
Definition riscv/opcodes.hpp:2480
LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_MF8
@ PseudoVSPILL5_MF8
Definition riscv/opcodes.hpp:9850
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E64_MASK
@ PseudoVDIVU_VX_M4_E64_MASK
Definition riscv/opcodes.hpp:1488
LIEF::assembly::riscv::OPCODE::G_ROTR
@ G_ROTR
Definition riscv/opcodes.hpp:163
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_MF4
@ PseudoVC_V_IVV_SE_MF4
Definition riscv/opcodes.hpp:1260
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1_MASK_TIED
@ PseudoVWADD_WV_M1_MASK_TIED
Definition riscv/opcodes.hpp:11421
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF2_MASK
@ PseudoVLOXSEG7EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4873
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M2_MASK
@ PseudoVLE8FF_V_M2_MASK
Definition riscv/opcodes.hpp:4146
LIEF::assembly::riscv::OPCODE::AMOMINU_B_AQ
@ AMOMINU_B_AQ
Definition riscv/opcodes.hpp:12036
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M4_MASK
@ PseudoVLOXEI16_V_M8_M4_MASK
Definition riscv/opcodes.hpp:4201
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M4_E16_MASK
@ PseudoVFWMACC_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3736
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M1_MASK
@ PseudoVSUXSEG2EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:10712
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E16
@ PseudoVFSGNJ_VV_M2_E16
Definition riscv/opcodes.hpp:3277
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M8_MASK
@ PseudoVMSEQ_VI_M8_MASK
Definition riscv/opcodes.hpp:6959
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF2
@ PseudoVRSUB_VI_MF2
Definition riscv/opcodes.hpp:8584
LIEF::assembly::riscv::OPCODE::SSAMOSWAP_D_AQ_RL
@ SSAMOSWAP_D_AQ_RL
Definition riscv/opcodes.hpp:13006
LIEF::assembly::riscv::OPCODE::G_USUBE
@ G_USUBE
Definition riscv/opcodes.hpp:173
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E64
@ PseudoVFCVT_F_X_V_M8_E64
Definition riscv/opcodes.hpp:1723
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M2_MASK
@ PseudoVLSEG2E8FF_V_M2_MASK
Definition riscv/opcodes.hpp:5105
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M8_E16
@ PseudoVFDIV_VFPR16_M8_E16
Definition riscv/opcodes.hpp:1869
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_M1_MASK
@ PseudoVSOXSEG7EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9684
LIEF::assembly::riscv::OPCODE::CV_CLIP
@ CV_CLIP
Definition riscv/opcodes.hpp:12207
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M4_MASK
@ PseudoVSEXT_VF8_M4_MASK
Definition riscv/opcodes.hpp:8776
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M1
@ PseudoVLUXEI32_V_M2_M1
Definition riscv/opcodes.hpp:5620
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E32
@ PseudoVFWMACC_VV_M1_E32
Definition riscv/opcodes.hpp:3751
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF4
@ PseudoVWADD_VV_MF4
Definition riscv/opcodes.hpp:11403
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M4_M2_MASK
@ PseudoVSOXSEG3EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9302
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF2
@ PseudoVSUXSEG2EI64_V_M1_MF2
Definition riscv/opcodes.hpp:10731
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E16_MASK
@ PseudoVFMADD_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:2040
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK
@ PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK
Definition riscv/opcodes.hpp:2490
LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_M2
@ PseudoVSPILL3_M2
Definition riscv/opcodes.hpp:9838
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_MF2_MASK
@ PseudoVLUXSEG3EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:5939
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_MF2
@ PseudoVC_V_XVW_SE_MF2
Definition riscv/opcodes.hpp:1365
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M1_MASK
@ PseudoVROR_VV_M1_MASK
Definition riscv/opcodes.hpp:8549
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF2_MASK
@ PseudoVMULHSU_VX_MF2_MASK
Definition riscv/opcodes.hpp:7300
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E16
@ PseudoVFMADD_VV_M4_E16
Definition riscv/opcodes.hpp:2039
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E32_MASK
@ PseudoVFWCVTBF16_F_F_V_M4_E32_MASK
Definition riscv/opcodes.hpp:3552
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_M1_MASK
@ PseudoVSUXSEG8EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:11268
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E32_MASK
@ PseudoVFWMACC_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3764
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E32_MASK
@ PseudoVFREDOSUM_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:3004
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E16
@ PseudoVFNCVT_F_XU_W_M1_E16
Definition riscv/opcodes.hpp:2453
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E64_MASK
@ PseudoVREDSUM_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:7993
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_M1
@ PseudoVLOXSEG5EI16_V_MF4_M1
Definition riscv/opcodes.hpp:4702
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M1
@ PseudoVSUXSEG3EI16_V_M2_M1
Definition riscv/opcodes.hpp:10801
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E32
@ PseudoVWREDSUMU_VS_M1_E32
Definition riscv/opcodes.hpp:11613
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M2
@ PseudoVMUL_VX_M2
Definition riscv/opcodes.hpp:7377
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B64_MASK
@ PseudoVCPOP_M_B64_MASK
Definition riscv/opcodes.hpp:1047
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E32
@ PseudoVFSUB_VV_MF2_E32
Definition riscv/opcodes.hpp:3447
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1_MASK
@ PseudoVWADD_WV_M1_MASK
Definition riscv/opcodes.hpp:11420
LIEF::assembly::riscv::OPCODE::TH_LWUD
@ TH_LWUD
Definition riscv/opcodes.hpp:13089
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF8
@ PseudoVSSSEG8E8_V_MF8
Definition riscv/opcodes.hpp:10417
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_M1
@ PseudoVLOXSEG6EI16_V_M1_M1
Definition riscv/opcodes.hpp:4770
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF8
@ PseudoVWMACCU_VV_MF8
Definition riscv/opcodes.hpp:11501
LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_M1
@ PseudoVC_XVW_SE_M1
Definition riscv/opcodes.hpp:1403
LIEF::assembly::riscv::OPCODE::CV_MIN
@ CV_MIN
Definition riscv/opcodes.hpp:12356
LIEF::assembly::riscv::OPCODE::SM4ED
@ SM4ED
Definition riscv/opcodes.hpp:12993
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M1
@ PseudoVSSSEG2E8_V_M1
Definition riscv/opcodes.hpp:10271
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF2_MASK
@ PseudoVNMSAC_VV_MF2_MASK
Definition riscv/opcodes.hpp:7507
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_M1_MASK
@ PseudoVLOXSEG6EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4803
LIEF::assembly::riscv::OPCODE::VSOXSEG6EI64_V
@ VSOXSEG6EI64_V
Definition riscv/opcodes.hpp:13682
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M2_MASK
@ PseudoVSSEG3E16_V_M2_MASK
Definition riscv/opcodes.hpp:10030
LIEF::assembly::riscv::OPCODE::VSUXSEG8EI64_V
@ VSUXSEG8EI64_V
Definition riscv/opcodes.hpp:13800
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF2
@ PseudoVSSEG3E16_V_MF2
Definition riscv/opcodes.hpp:10031
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M8_M1_MASK
@ PseudoVLOXSEG6EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:4829
LIEF::assembly::riscv::OPCODE::C_SD
@ C_SD
Definition riscv/opcodes.hpp:12528
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF4
@ PseudoVLSSEG8E16_V_MF4
Definition riscv/opcodes.hpp:5554
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF2_MASK
@ PseudoVFCVT_RTZ_X_F_V_MF2_MASK
Definition riscv/opcodes.hpp:1836
LIEF::assembly::riscv::OPCODE::VLSEG4E8FF_V
@ VLSEG4E8FF_V
Definition riscv/opcodes.hpp:13390
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M1_MASK
@ PseudoVANDN_VV_M1_MASK
Definition riscv/opcodes.hpp:791
LIEF::assembly::riscv::OPCODE::VLSEG4E16_V
@ VLSEG4E16_V
Definition riscv/opcodes.hpp:13385
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M8_E16
@ PseudoVFRSUB_VFPR16_M8_E16
Definition riscv/opcodes.hpp:3097
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E32_MASK
@ PseudoVFADD_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:1644
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF2_MASK
@ PseudoVSUXSEG8EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:11324
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M4_MASK
@ PseudoVLUXEI32_V_M4_M4_MASK
Definition riscv/opcodes.hpp:5633
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF4_E16_MASK
@ PseudoVFRSUB_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3102
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_MF2
@ PseudoVLUXSEG8EI32_V_M2_MF2
Definition riscv/opcodes.hpp:6350
LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_MF4
@ PseudoVC_IVW_SE_MF4
Definition riscv/opcodes.hpp:1130
LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_M1
@ PseudoVSPILL4_M1
Definition riscv/opcodes.hpp:9842
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E32
@ PseudoVFREDMIN_VS_M1_E32
Definition riscv/opcodes.hpp:2967
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M8_MASK
@ PseudoVMSLE_VV_M8_MASK
Definition riscv/opcodes.hpp:7142
LIEF::assembly::riscv::OPCODE::AMOMINU_H_AQ_RL
@ AMOMINU_H_AQ_RL
Definition riscv/opcodes.hpp:12045
LIEF::assembly::riscv::OPCODE::CV_MACHHURN
@ CV_MACHHURN
Definition riscv/opcodes.hpp:12337
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF2
@ PseudoVMULHSU_VV_MF2
Definition riscv/opcodes.hpp:7285
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M4_E32_MASK
@ PseudoVFNMACC_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2632
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M2
@ PseudoVSSUB_VX_M2
Definition riscv/opcodes.hpp:10463
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M1_MASK
@ PseudoVSUXSEG4EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:10978
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M1
@ PseudoVMULHU_VX_M1
Definition riscv/opcodes.hpp:7319
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E16_MASK
@ PseudoVFWNMSAC_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3906
LIEF::assembly::riscv::OPCODE::VSOXSEG4EI32_V
@ VSOXSEG4EI32_V
Definition riscv/opcodes.hpp:13673
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M1_MASK
@ PseudoVRGATHER_VX_M1_MASK
Definition riscv/opcodes.hpp:8493
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E16
@ PseudoVREDSUM_VS_M2_E16
Definition riscv/opcodes.hpp:7972
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E16_MASK
@ PseudoVFMSUB_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:2307
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF4_MASK
@ PseudoVLUXSEG8EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:6347
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E8_MASK
@ PseudoVREDMINU_VS_M4_E8_MASK
Definition riscv/opcodes.hpp:7855
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M1_MASK
@ PseudoVSSSEG3E8_V_M1_MASK
Definition riscv/opcodes.hpp:10302
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M8_MASK
@ PseudoVSADD_VI_M8_MASK
Definition riscv/opcodes.hpp:8653
LIEF::assembly::riscv::OPCODE::VFMSUB_VF
@ VFMSUB_VF
Definition riscv/opcodes.hpp:13227
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E16_MASK
@ PseudoVREDAND_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:7701
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF2
@ PseudoVSUXSEG5EI64_V_M2_MF2
Definition riscv/opcodes.hpp:11065
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M8
@ PseudoVFSLIDE1DOWN_VFPR64_M8
Definition riscv/opcodes.hpp:3329
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E16
@ PseudoVFMADD_VV_MF2_E16
Definition riscv/opcodes.hpp:2051
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M2_MF2
@ PseudoVSUXSEG5EI32_V_M2_MF2
Definition riscv/opcodes.hpp:11043
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_MF2
@ PseudoVLUXSEG3EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:5954
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M8_E64
@ PseudoVFRDIV_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2903
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M4
@ PseudoVSADDU_VI_M4
Definition riscv/opcodes.hpp:8608
LIEF::assembly::riscv::OPCODE::C_MOP15
@ C_MOP15
Definition riscv/opcodes.hpp:12515
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M1_MASK
@ PseudoVLE16FF_V_M1_MASK
Definition riscv/opcodes.hpp:4084
LIEF::assembly::riscv::OPCODE::CV_CMPLT_SCI_H
@ CV_CMPLT_SCI_H
Definition riscv/opcodes.hpp:12262
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E16_MASK
@ PseudoVFCVT_F_XU_V_M4_E16_MASK
Definition riscv/opcodes.hpp:1684
LIEF::assembly::riscv::OPCODE::FMAX_D_INX
@ FMAX_D_INX
Definition riscv/opcodes.hpp:12698
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M2_M1_MASK
@ PseudoVSUXSEG5EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11020
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF2_MASK
@ PseudoVFNCVT_X_F_W_MF2_MASK
Definition riscv/opcodes.hpp:2610
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M1
@ PseudoVLOXSEG2EI16_V_M1_M1
Definition riscv/opcodes.hpp:4334
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M1_E16_MASK
@ PseudoVFSGNJN_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3122
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M2_MASK
@ PseudoVLSEG4E32_V_M2_MASK
Definition riscv/opcodes.hpp:5207
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF4
@ PseudoVLOXSEG2EI64_V_M2_MF4
Definition riscv/opcodes.hpp:4418
LIEF::assembly::riscv::OPCODE::VLOXSEG8EI8_V
@ VLOXSEG8EI8_V
Definition riscv/opcodes.hpp:13363
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M4
@ PseudoVASUBU_VX_M4
Definition riscv/opcodes.hpp:878
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_M1
@ PseudoVSSSEG4E8_V_M1
Definition riscv/opcodes.hpp:10329
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_MF2
@ PseudoVC_V_FPR16V_SE_MF2
Definition riscv/opcodes.hpp:1200
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF4_MASK
@ PseudoVIOTA_M_MF4_MASK
Definition riscv/opcodes.hpp:4080
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF4
@ PseudoVWADD_VX_MF4
Definition riscv/opcodes.hpp:11415
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF4_MASK
@ PseudoVSOXSEG7EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9716
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_MF8
@ PseudoVSM4R_VS_M2_MF8
Definition riscv/opcodes.hpp:8943
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF4
@ PseudoVLOXSEG7EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:4860
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M1
@ PseudoVSUXSEG3EI64_V_M2_M1
Definition riscv/opcodes.hpp:10859
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF2
@ PseudoVSRL_VX_MF2
Definition riscv/opcodes.hpp:9941
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M2
@ PseudoVLOXEI16_V_MF2_M2
Definition riscv/opcodes.hpp:4206
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF4
@ PseudoVSUXSEG5EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:11085
LIEF::assembly::riscv::OPCODE::TH_REV
@ TH_REV
Definition riscv/opcodes.hpp:13100
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF4_MASK
@ PseudoVLOXSEG2EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:4467
LIEF::assembly::riscv::OPCODE::VC_V_IVV
@ VC_V_IVV
Definition riscv/opcodes.hpp:13187
LIEF::assembly::riscv::OPCODE::MOPRR3
@ MOPRR3
Definition riscv/opcodes.hpp:12895
LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M2
@ PseudoVADC_VIM_M2
Definition riscv/opcodes.hpp:578
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E16_MASK
@ PseudoVFMSAC_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:2235
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16
@ PseudoVFWADD_WV_MF4_E16
Definition riscv/opcodes.hpp:3537
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_SE_M4
@ PseudoVC_V_FPR32VV_SE_M4
Definition riscv/opcodes.hpp:1209
LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_MF8
@ PseudoVSPILL6_MF8
Definition riscv/opcodes.hpp:9854
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E8_MASK
@ PseudoVREDMINU_VS_M8_E8_MASK
Definition riscv/opcodes.hpp:7863
LIEF::assembly::riscv::OPCODE::G_LOAD
@ G_LOAD
Definition riscv/opcodes.hpp:113
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_M1_M1
@ PseudoVSUXSEG6EI8_V_M1_M1
Definition riscv/opcodes.hpp:11155
LIEF::assembly::riscv::OPCODE::BREV8
@ BREV8
Definition riscv/opcodes.hpp:12131
LIEF::assembly::riscv::OPCODE::ROL
@ ROL
Definition riscv/opcodes.hpp:12930
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF4_E16_MASK
@ PseudoVFRSQRT7_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:3090
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M8_MASK
@ PseudoVMUL_VV_M8_MASK
Definition riscv/opcodes.hpp:7368
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E16
@ PseudoVFMUL_VV_M2_E16
Definition riscv/opcodes.hpp:2348
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E32
@ PseudoVFMAX_VV_M2_E32
Definition riscv/opcodes.hpp:2095
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF4
@ PseudoVRGATHEREI16_VV_MF4_E16_MF4
Definition riscv/opcodes.hpp:8420
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M2_E32_MASK
@ PseudoVFADD_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:1614
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_M1_MASK
@ PseudoVSUXSEG3EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10852
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E64_MASK
@ PseudoVFSGNJ_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:3276
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_M1_M1_MASK
@ PseudoVSOXSEG7EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9732
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF4_E16
@ PseudoVFREDOSUM_VS_MF4_E16
Definition riscv/opcodes.hpp:3023
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_M1_MASK
@ PseudoVSOXSEG4EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9458
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M4
@ PseudoVMINU_VV_M4
Definition riscv/opcodes.hpp:6830
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF8_MASK
@ PseudoVMADD_VV_MF8_MASK
Definition riscv/opcodes.hpp:6485
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M4_MASK
@ PseudoVSOXSEG2EI16_V_M2_M4_MASK
Definition riscv/opcodes.hpp:9168
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_M1_MASK
@ PseudoVLUXEI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:5605
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_MF4
@ PseudoVAESZ_VS_M8_MF4
Definition riscv/opcodes.hpp:785
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M4_E32
@ PseudoVFNMADD_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2691
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M1
@ PseudoVRGATHEREI16_VV_M1_E64_M1
Definition riscv/opcodes.hpp:8290
LIEF::assembly::riscv::OPCODE::VFSLIDE1DOWN_VF
@ VFSLIDE1DOWN_VF
Definition riscv/opcodes.hpp:13267
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF2_MASK
@ PseudoVWSUB_WX_MF2_MASK
Definition riscv/opcodes.hpp:11834
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF4_MASK
@ PseudoVLUXSEG8EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:6359
LIEF::assembly::riscv::OPCODE::VLSSEG2E8_V
@ VLSSEG2E8_V
Definition riscv/opcodes.hpp:13427
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF4
@ PseudoVSUXSEG6EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:11105
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M1
@ PseudoVSEXT_VF8_M1
Definition riscv/opcodes.hpp:8771
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK
@ PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK
Definition riscv/opcodes.hpp:8403
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF2_MASK
@ PseudoVSOXSEG4EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9460
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E64_MASK
@ PseudoVFRSQRT7_V_M8_E64_MASK
Definition riscv/opcodes.hpp:3084
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_MF2_MASK
@ PseudoVSUXEI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:10560
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E16_MASK
@ PseudoVFWCVT_F_X_V_M4_E16_MASK
Definition riscv/opcodes.hpp:3620
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E16
@ PseudoVFWNMACC_VV_M1_E16
Definition riscv/opcodes.hpp:3857
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_MF2
@ PseudoVSUXSEG8EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:11319
LIEF::assembly::riscv::OPCODE::PseudoFSW
@ PseudoFSW
Definition riscv/opcodes.hpp:383
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M1
@ PseudoVXOR_VX_M1
Definition riscv/opcodes.hpp:11867
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_MF2
@ PseudoVLUXSEG8EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:6386
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF4
@ PseudoVNMSUB_VX_MF4
Definition riscv/opcodes.hpp:7550
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E32_MASK
@ PseudoVFMADD_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:2030
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M4_M2_MASK
@ PseudoVLOXSEG3EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4481
LIEF::assembly::riscv::OPCODE::ZEXT_H_RV32
@ ZEXT_H_RV32
Definition riscv/opcodes.hpp:13852
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M1_MASK
@ PseudoVSE16_V_M1_MASK
Definition riscv/opcodes.hpp:8703
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M1_MASK
@ PseudoVROL_VX_M1_MASK
Definition riscv/opcodes.hpp:8521
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF4_E16
@ PseudoVFMAX_VV_MF4_E16
Definition riscv/opcodes.hpp:2115
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M1
@ PseudoVLUXSEG3EI8_V_M1_M1
Definition riscv/opcodes.hpp:5944
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1_MASK
@ PseudoVWSUB_WV_M1_MASK
Definition riscv/opcodes.hpp:11804
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E32
@ PseudoVWREDSUM_VS_M1_E32
Definition riscv/opcodes.hpp:11649
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF4_MASK
@ PseudoVLOXEI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4325
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_M2
@ PseudoVC_V_VVW_M2
Definition riscv/opcodes.hpp:1317
LIEF::assembly::riscv::OPCODE::FLD
@ FLD
Definition riscv/opcodes.hpp:12660
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4_TIED
@ PseudoVWADD_WV_M4_TIED
Definition riscv/opcodes.hpp:11430
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_M1
@ PseudoVRELOAD8_M1
Definition riscv/opcodes.hpp:8080
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_M4
@ PseudoVC_V_IVV_SE_M4
Definition riscv/opcodes.hpp:1257
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF8
@ PseudoVNSRA_WV_MF8
Definition riscv/opcodes.hpp:7576
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M1
@ PseudoVSUXSEG3EI32_V_M2_M1
Definition riscv/opcodes.hpp:10831
LIEF::assembly::riscv::OPCODE::VWMUL_VV
@ VWMUL_VV
Definition riscv/opcodes.hpp:13823
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF4
@ PseudoVRGATHEREI16_VV_MF2_E8_MF4
Definition riscv/opcodes.hpp:8414
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E16
@ PseudoVFMSAC_VV_MF2_E16
Definition riscv/opcodes.hpp:2246
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M1
@ PseudoVMFNE_VFPR32_M1
Definition riscv/opcodes.hpp:6796
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_M1_MASK
@ PseudoVLOXSEG6EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4819
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF8
@ PseudoVAND_VX_MF8
Definition riscv/opcodes.hpp:858
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M1_E32_MASK
@ PseudoVFADD_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:1612
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF4
@ PseudoVSSEG5E8_V_MF4
Definition riscv/opcodes.hpp:10099
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M4_MASK
@ PseudoVWMACCU_VV_M4_MASK
Definition riscv/opcodes.hpp:11496
LIEF::assembly::riscv::OPCODE::FLE_H
@ FLE_H
Definition riscv/opcodes.hpp:12667
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E32
@ PseudoVDIVU_VX_M1_E32
Definition riscv/opcodes.hpp:1469
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_MF2
@ PseudoTHVdotVMAQA_VV_MF2
Definition riscv/opcodes.hpp:508
LIEF::assembly::riscv::OPCODE::VSUB_VX
@ VSUB_VX
Definition riscv/opcodes.hpp:13769
LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_M4
@ PseudoVMOR_MM_M4
Definition riscv/opcodes.hpp:6905
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK
@ PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:3558
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF4_E16_MASK
@ PseudoVFCVT_F_X_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:1730
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF2_MASK
@ PseudoVSUXEI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10534
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M1_MASK
@ PseudoVSSSEG2E8_V_M1_MASK
Definition riscv/opcodes.hpp:10272
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M2
@ PseudoVRSUB_VI_M2
Definition riscv/opcodes.hpp:8578
LIEF::assembly::riscv::OPCODE::CV_MIN_SCI_H
@ CV_MIN_SCI_H
Definition riscv/opcodes.hpp:12367
LIEF::assembly::riscv::OPCODE::FLT_H
@ FLT_H
Definition riscv/opcodes.hpp:12681
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M1_MASK
@ PseudoVBREV_V_M1_MASK
Definition riscv/opcodes.hpp:931
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M1
@ PseudoVROL_VX_M1
Definition riscv/opcodes.hpp:8520
LIEF::assembly::riscv::OPCODE::FSQRT_S
@ FSQRT_S
Definition riscv/opcodes.hpp:12784
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF4
@ PseudoVLOXSEG8EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:4940
LIEF::assembly::riscv::OPCODE::LR_W_RL
@ LR_W_RL
Definition riscv/opcodes.hpp:12850
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M1_MASK
@ PseudoVAADDU_VX_M1_MASK
Definition riscv/opcodes.hpp:536
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF2_MASK
@ PseudoVSSSEG7E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10382
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E16
@ PseudoVFWSUB_VV_M4_E16
Definition riscv/opcodes.hpp:3981
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF8_MASK
@ PseudoVSUXSEG3EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:10904
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF8
@ PseudoVAADD_VX_MF8
Definition riscv/opcodes.hpp:575
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E64_MASK
@ PseudoVFNMADD_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:2716
LIEF::assembly::riscv::OPCODE::VMV1R_V
@ VMV1R_V
Definition riscv/opcodes.hpp:13556
LIEF::assembly::riscv::OPCODE::VLOXSEG5EI8_V
@ VLOXSEG5EI8_V
Definition riscv/opcodes.hpp:13351
LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_MF4
@ PseudoVSPILL6_MF4
Definition riscv/opcodes.hpp:9853
LIEF::assembly::riscv::OPCODE::CV_CMPLT_SCI_B
@ CV_CMPLT_SCI_B
Definition riscv/opcodes.hpp:12261
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M2
@ PseudoVSOXSEG4EI64_V_M2_M2
Definition riscv/opcodes.hpp:9467
LIEF::assembly::riscv::OPCODE::VNSRA_WV
@ VNSRA_WV
Definition riscv/opcodes.hpp:13578
LIEF::assembly::riscv::OPCODE::VLOXSEG6EI64_V
@ VLOXSEG6EI64_V
Definition riscv/opcodes.hpp:13354
LIEF::assembly::riscv::OPCODE::SEXT_H
@ SEXT_H
Definition riscv/opcodes.hpp:12951
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF4_E16
@ PseudoVFWMACCBF16_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3705
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M2
@ PseudoVLOXEI32_V_M2_M2
Definition riscv/opcodes.hpp:4230
LIEF::assembly::riscv::OPCODE::C_ZEXT_W
@ C_ZEXT_W
Definition riscv/opcodes.hpp:12550
LIEF::assembly::riscv::OPCODE::CM_PUSH
@ CM_PUSH
Definition riscv/opcodes.hpp:12150
LIEF::assembly::riscv::OPCODE::VSADD_VI
@ VSADD_VI
Definition riscv/opcodes.hpp:13625
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_MF2_MASK
@ PseudoVLUXSEG8EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6387
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M1_MASK
@ PseudoVSSSEG2E64_V_M1_MASK
Definition riscv/opcodes.hpp:10266
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF4
@ PseudoVSOXSEG5EI64_V_M1_MF4
Definition riscv/opcodes.hpp:9555
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E64
@ PseudoVREM_VX_M2_E64
Definition riscv/opcodes.hpp:8228
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M1
@ PseudoVMFEQ_VFPR64_M1
Definition riscv/opcodes.hpp:6620
LIEF::assembly::riscv::OPCODE::VLOXSEG8EI32_V
@ VLOXSEG8EI32_V
Definition riscv/opcodes.hpp:13361
LIEF::assembly::riscv::OPCODE::CV_SUBURNR
@ CV_SUBURNR
Definition riscv/opcodes.hpp:12454
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF4_E16
@ PseudoVFMADD_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2007
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_MF2_MF8
@ PseudoVSM4R_VS_MF2_MF8
Definition riscv/opcodes.hpp:8958
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E16_MASK
@ PseudoVFREDMIN_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:2984
LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B1
@ PseudoVMCLR_M_B1
Definition riscv/opcodes.hpp:6570
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M1_MASK
@ PseudoVNSRA_WV_M1_MASK
Definition riscv/opcodes.hpp:7567
LIEF::assembly::riscv::OPCODE::FCVT_H_D
@ FCVT_H_D
Definition riscv/opcodes.hpp:12590
LIEF::assembly::riscv::OPCODE::VLSEG7E8FF_V
@ VLSEG7E8FF_V
Definition riscv/opcodes.hpp:13414
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M4
@ PseudoVSADDU_VX_M4
Definition riscv/opcodes.hpp:8636
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M4
@ PseudoVWSLL_VV_M4
Definition riscv/opcodes.hpp:11699
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M4_MASK
@ PseudoVRGATHEREI16_VV_M8_E8_M4_MASK
Definition riscv/opcodes.hpp:8391
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF2_MASK
@ PseudoVXOR_VI_MF2_MASK
Definition riscv/opcodes.hpp:11848
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M8_M4_MASK
@ PseudoVSUXSEG2EI16_V_M8_M4_MASK
Definition riscv/opcodes.hpp:10678
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E8_MASK
@ PseudoVREDXOR_VS_M4_E8_MASK
Definition riscv/opcodes.hpp:8031
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M1
@ PseudoVMAXU_VX_M1
Definition riscv/opcodes.hpp:6528
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_M8
@ PseudoVC_V_FPR32VW_M8
Definition riscv/opcodes.hpp:1215
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M1
@ PseudoVSOXEI32_V_M2_M1
Definition riscv/opcodes.hpp:9049
LIEF::assembly::riscv::OPCODE::VWMACC_VV
@ VWMACC_VV
Definition riscv/opcodes.hpp:13817
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M1
@ PseudoVLSEG3E64_V_M1
Definition riscv/opcodes.hpp:5158
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF4_E16_MASK
@ PseudoVFMUL_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2323
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M1_MASK
@ PseudoVLOXSEG4EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4581
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF2_E32
@ PseudoVFWMSAC_VV_MF2_E32
Definition riscv/opcodes.hpp:3799
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E8_MASK
@ PseudoVDIV_VX_MF2_E8_MASK
Definition riscv/opcodes.hpp:1592
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E16
@ PseudoVFWNMSAC_VV_M2_E16
Definition riscv/opcodes.hpp:3897
LIEF::assembly::riscv::OPCODE::FDIV_S_INX
@ FDIV_S_INX
Definition riscv/opcodes.hpp:12649
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF2_MASK
@ PseudoVSUXSEG6EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11138
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_MF4_MASK
@ PseudoVLSE16_V_MF4_MASK
Definition riscv/opcodes.hpp:5021
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M1_E16
@ PseudoVCOMPRESS_VM_M1_E16
Definition riscv/opcodes.hpp:1014
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E8
@ PseudoVDIVU_VX_M4_E8
Definition riscv/opcodes.hpp:1489
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E64_V_M1_MASK
@ PseudoVSSSEG5E64_V_M1_MASK
Definition riscv/opcodes.hpp:10350
LIEF::assembly::riscv::OPCODE::FCVT_D_LU
@ FCVT_D_LU
Definition riscv/opcodes.hpp:12578
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E32_MASK
@ PseudoVFNCVT_F_XU_W_M1_E32_MASK
Definition riscv/opcodes.hpp:2456
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_MF2_MASK
@ PseudoVSOXSEG6EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9656
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_M1_MASK
@ PseudoVSUXSEG7EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:11242
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M8_E32_MASK
@ PseudoVFMSAC_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2211
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E16_MASK
@ PseudoVFCVT_F_X_V_M2_E16_MASK
Definition riscv/opcodes.hpp:1708
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_M1_MASK
@ PseudoVLUXSEG7EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:6315
LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M4_MASK
@ PseudoVSE64_V_M4_MASK
Definition riscv/opcodes.hpp:8729
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF8
@ PseudoVSOXSEG4EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:9455
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M1
@ PseudoVLOXSEG3EI32_V_M1_M1
Definition riscv/opcodes.hpp:4498
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E8
@ PseudoVDIVU_VV_M2_E8
Definition riscv/opcodes.hpp:1437
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M4_MASK
@ PseudoVMINU_VV_M4_MASK
Definition riscv/opcodes.hpp:6831
LIEF::assembly::riscv::OPCODE::PseudoLA_TLSDESC
@ PseudoLA_TLSDESC
Definition riscv/opcodes.hpp:387
LIEF::assembly::riscv::OPCODE::G_STRICT_FADD
@ G_STRICT_FADD
Definition riscv/opcodes.hpp:282
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_MF2_MASK
@ PseudoVLOXSEG6EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4799
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_MF2_MASK
@ PseudoVLUXSEG2EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:5777
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_MF4
@ PseudoVC_V_X_SE_MF4
Definition riscv/opcodes.hpp:1394
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_M8
@ PseudoVC_V_VVV_SE_M8
Definition riscv/opcodes.hpp:1312
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E16_MASK
@ PseudoVFRSQRT7_V_M2_E16_MASK
Definition riscv/opcodes.hpp:3068
LIEF::assembly::riscv::OPCODE::VSUXSEG2EI64_V
@ VSUXSEG2EI64_V
Definition riscv/opcodes.hpp:13776
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M4_MASK
@ PseudoVSOXEI8_V_M1_M4_MASK
Definition riscv/opcodes.hpp:9116
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_MF4_MASK
@ PseudoVSUXSEG7EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:11228
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E64
@ PseudoVFSQRT_V_M2_E64
Definition riscv/opcodes.hpp:3371
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M2
@ PseudoVROR_VX_M2
Definition riscv/opcodes.hpp:8564
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E64
@ PseudoVREMU_VX_M2_E64
Definition riscv/opcodes.hpp:8140
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF4
@ PseudoVSOXSEG6EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:9627
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF2
@ PseudoVSLIDE1DOWN_VX_MF2
Definition riscv/opcodes.hpp:8802
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_MF2_E32
@ PseudoVFMIN_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2152
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M1
@ PseudoVLUXEI8_V_M1_M1
Definition riscv/opcodes.hpp:5682
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF8_MASK
@ PseudoVLOXSEG5EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:4729
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M1_MASK
@ PseudoVMSLT_VV_M1_MASK
Definition riscv/opcodes.hpp:7194
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E32
@ PseudoVFREC7_V_M8_E32
Definition riscv/opcodes.hpp:2925
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E32_MASK
@ PseudoVFCVT_RM_F_XU_V_M4_E32_MASK
Definition riscv/opcodes.hpp:1746
LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_4x8x4_M4
@ PseudoVQMACCUS_4x8x4_M4
Definition riscv/opcodes.hpp:7682
LIEF::assembly::riscv::OPCODE::AUIPC
@ AUIPC
Definition riscv/opcodes.hpp:12118
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_M1_MASK
@ PseudoVSOXSEG3EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9312
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M4_MASK
@ PseudoVOR_VX_M4_MASK
Definition riscv/opcodes.hpp:7659
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF2
@ PseudoVLUXSEG5EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:6116
LIEF::assembly::riscv::OPCODE::Select_FPR32INX_Using_CC_GPR
@ Select_FPR32INX_Using_CC_GPR
Definition riscv/opcodes.hpp:11918
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M1_MASK
@ PseudoVLOXSEG3EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4553
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M2_MASK
@ PseudoVSRL_VX_M2_MASK
Definition riscv/opcodes.hpp:9936
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF4
@ PseudoVLOXSEG7EI64_V_M1_MF4
Definition riscv/opcodes.hpp:4894
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK
@ PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK
Definition riscv/opcodes.hpp:3664
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M4
@ PseudoVLOXSEG2EI8_V_MF2_M4
Definition riscv/opcodes.hpp:4450
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF4_E16_MASK
@ PseudoVFNCVT_F_F_W_MF4_E16_MASK
Definition riscv/opcodes.hpp:2452
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF2_E16
@ PseudoVFCVT_RM_F_X_V_MF2_E16
Definition riscv/opcodes.hpp:1785
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M1
@ PseudoVSOXSEG4EI8_V_M1_M1
Definition riscv/opcodes.hpp:9483
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E32
@ PseudoVREM_VV_MF2_E32
Definition riscv/opcodes.hpp:8206
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF4_E16
@ PseudoVFWMUL_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3811
LIEF::assembly::riscv::OPCODE::VMULHSU_VV
@ VMULHSU_VV
Definition riscv/opcodes.hpp:13548
LIEF::assembly::riscv::OPCODE::VS8R_V
@ VS8R_V
Definition riscv/opcodes.hpp:13621
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF4
@ PseudoVSLIDEDOWN_VX_MF4
Definition riscv/opcodes.hpp:8846
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF2_MASK
@ PseudoVMUL_VX_MF2_MASK
Definition riscv/opcodes.hpp:7384
LIEF::assembly::riscv::OPCODE::FCLASS_D_IN32X
@ FCLASS_D_IN32X
Definition riscv/opcodes.hpp:12566
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_M1
@ PseudoVLUXSEG6EI8_V_MF2_M1
Definition riscv/opcodes.hpp:6224
LIEF::assembly::riscv::OPCODE::FCLASS_S
@ FCLASS_S
Definition riscv/opcodes.hpp:12570
LIEF::assembly::riscv::OPCODE::VSOXSEG4EI64_V
@ VSOXSEG4EI64_V
Definition riscv/opcodes.hpp:13674
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M1_MASK
@ PseudoVXOR_VI_M1_MASK
Definition riscv/opcodes.hpp:11840
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M2
@ PseudoVSEXT_VF8_M2
Definition riscv/opcodes.hpp:8773
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M1_MASK
@ PseudoVFSLIDE1DOWN_VFPR64_M1_MASK
Definition riscv/opcodes.hpp:3324
LIEF::assembly::riscv::OPCODE::G_SSUBO
@ G_SSUBO
Definition riscv/opcodes.hpp:176
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M2_MASK
@ PseudoVSSUBU_VV_M2_MASK
Definition riscv/opcodes.hpp:10422
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M2
@ PseudoVFNCVT_RM_X_F_W_M2
Definition riscv/opcodes.hpp:2539
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF8
@ PseudoVSSEG6E8_V_MF8
Definition riscv/opcodes.hpp:10121
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E64_MASK
@ PseudoVDIVU_VX_M2_E64_MASK
Definition riscv/opcodes.hpp:1480
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_M2
@ PseudoVAESZ_VS_M2_M2
Definition riscv/opcodes.hpp:771
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M1_MASK
@ PseudoVROR_VI_M1_MASK
Definition riscv/opcodes.hpp:8535
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_MF2_MASK
@ PseudoVLUXSEG2EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:5733
LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_MF8
@ PseudoVC_IV_SE_MF8
Definition riscv/opcodes.hpp:1138
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M2_MASK
@ PseudoVSUXSEG2EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:10682
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M8
@ PseudoVSMUL_VV_M8
Definition riscv/opcodes.hpp:8970
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_M1_M1_MASK
@ PseudoVLOXSEG7EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4911
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M8
@ PseudoVSMUL_VX_M8
Definition riscv/opcodes.hpp:8984
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M4
@ PseudoVLSEG2E8_V_M4
Definition riscv/opcodes.hpp:5118
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M4_MASK
@ PseudoVLUXSEG2EI8_V_MF2_M4_MASK
Definition riscv/opcodes.hpp:5843
LIEF::assembly::riscv::OPCODE::FSUB_D_IN32X
@ FSUB_D_IN32X
Definition riscv/opcodes.hpp:12787
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_M1_MASK
@ PseudoVLOXSEG6EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4837
LIEF::assembly::riscv::OPCODE::VWMACC_VX
@ VWMACC_VX
Definition riscv/opcodes.hpp:13818
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_M1_M1_MASK
@ PseudoVSOXSEG8EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9812
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M2_MASK
@ PseudoVLOXEI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4231
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF2
@ PseudoVWMULSU_VX_MF2
Definition riscv/opcodes.hpp:11557
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF4
@ PseudoVSSSEG5E8_V_MF4
Definition riscv/opcodes.hpp:10355
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF4_E16_MASK
@ PseudoVFWMACC_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3740
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M1_MASK
@ PseudoVSOXSEG2EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9242
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF4_MASK
@ PseudoVSUXSEG7EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:11246
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_MF2
@ PseudoVSUXSEG4EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:10997
LIEF::assembly::riscv::OPCODE::AMOCAS_W_AQ
@ AMOCAS_W_AQ
Definition riscv/opcodes.hpp:12000
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M8_MASK
@ PseudoVCLZ_V_M8_MASK
Definition riscv/opcodes.hpp:1007
LIEF::assembly::riscv::OPCODE::AMOAND_D
@ AMOAND_D
Definition riscv/opcodes.hpp:11967
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M8
@ PseudoVMULH_VX_M8
Definition riscv/opcodes.hpp:7353
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF2
@ PseudoVSOXEI64_V_M1_MF2
Definition riscv/opcodes.hpp:9081
LIEF::assembly::riscv::OPCODE::SLLI
@ SLLI
Definition riscv/opcodes.hpp:12983
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF4_E16
@ PseudoVFNMSUB_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2805
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M8_E32
@ PseudoVFDIV_VFPR32_M8_E32
Definition riscv/opcodes.hpp:1881
LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SCI_B
@ CV_CMPEQ_SCI_B
Definition riscv/opcodes.hpp:12213
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M1_E16_MASK
@ PseudoVFWSUB_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3956
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M2
@ PseudoVMFNE_VFPR64_M2
Definition riscv/opcodes.hpp:6808
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M8
@ PseudoVSUXEI8_V_M1_M8
Definition riscv/opcodes.hpp:10621
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF4_MASK
@ PseudoVSSEG8E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10148
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_MF2
@ PseudoVLOXEI64_V_M4_MF2
Definition riscv/opcodes.hpp:4280
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_MF2_MASK
@ PseudoVLUXEI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:5577
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E32
@ PseudoVFNCVT_ROD_F_F_W_M4_E32
Definition riscv/opcodes.hpp:2559
LIEF::assembly::riscv::OPCODE::CV_EXTRACTU_B
@ CV_EXTRACTU_B
Definition riscv/opcodes.hpp:12308
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_MF2_MASK
@ PseudoVSUXSEG2EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:10710
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M2_MASK
@ PseudoVSOXSEG2EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:9252
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_MF2
@ PseudoVC_V_I_MF2
Definition riscv/opcodes.hpp:1292
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_M1_MASK
@ PseudoVLUXSEG6EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6195
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M2
@ PseudoVCTZ_V_M2
Definition riscv/opcodes.hpp:1066
LIEF::assembly::riscv::OPCODE::C_ANDI
@ C_ANDI
Definition riscv/opcodes.hpp:12485
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF2
@ PseudoVLSEG2E16FF_V_MF2
Definition riscv/opcodes.hpp:5060
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF8_MASK
@ PseudoVSUXSEG2EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:10794
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M1
@ PseudoVSLL_VI_M1
Definition riscv/opcodes.hpp:8878
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M4_MASK
@ PseudoVSADD_VI_M4_MASK
Definition riscv/opcodes.hpp:8651
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF2
@ PseudoVSADD_VX_MF2
Definition riscv/opcodes.hpp:8682
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_MF4
@ PseudoVC_V_FPR16VW_SE_MF4
Definition riscv/opcodes.hpp:1189
LIEF::assembly::riscv::OPCODE::TH_EXT
@ TH_EXT
Definition riscv/opcodes.hpp:13042
LIEF::assembly::riscv::OPCODE::FCVT_L_D_INX
@ FCVT_L_D_INX
Definition riscv/opcodes.hpp:12610
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_M1
@ PseudoVLUXSEG3EI32_V_MF2_M1
Definition riscv/opcodes.hpp:5910
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_M1
@ PseudoVLUXSEG8EI32_V_MF2_M1
Definition riscv/opcodes.hpp:6354
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_MF2_MASK
@ PseudoVLOXSEG3EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4563
LIEF::assembly::riscv::OPCODE::FCVT_W_D
@ FCVT_W_D
Definition riscv/opcodes.hpp:12636
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M1
@ PseudoVADD_VI_M1
Definition riscv/opcodes.hpp:598
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E64_V_M1
@ PseudoVLSSEG5E64_V_M1
Definition riscv/opcodes.hpp:5500
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF2
@ PseudoVLSSEG6E8_V_MF2
Definition riscv/opcodes.hpp:5524
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF8
@ PseudoVLUXSEG5EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:6100
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF4_MASK
@ PseudoVLOXSEG4EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4633
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M8
@ PseudoVRGATHER_VX_M8
Definition riscv/opcodes.hpp:8498
LIEF::assembly::riscv::OPCODE::G_STRICT_FMA
@ G_STRICT_FMA
Definition riscv/opcodes.hpp:287
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E16
@ PseudoVFRSQRT7_V_M1_E16
Definition riscv/opcodes.hpp:3061
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF2
@ PseudoVSOXSEG6EI32_V_M1_MF2
Definition riscv/opcodes.hpp:9613
LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_MF8
@ PseudoVMXNOR_MM_MF8
Definition riscv/opcodes.hpp:7418
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M4_MASK
@ PseudoVRGATHEREI16_VV_M4_E32_M4_MASK
Definition riscv/opcodes.hpp:8351
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_M1_MASK
@ PseudoVLSEG6E16_V_M1_MASK
Definition riscv/opcodes.hpp:5285
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M2
@ PseudoVSSSEG4E64_V_M2
Definition riscv/opcodes.hpp:10327
LIEF::assembly::riscv::OPCODE::VNCLIPU_WX
@ VNCLIPU_WX
Definition riscv/opcodes.hpp:13569
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF8
@ PseudoVWADD_VX_MF8
Definition riscv/opcodes.hpp:11417
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E16
@ PseudoVWREDSUMU_VS_M2_E16
Definition riscv/opcodes.hpp:11617
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M2
@ PseudoVLSEG2E8_V_M2
Definition riscv/opcodes.hpp:5116
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M2
@ PseudoVLOXSEG2EI8_V_MF4_M2
Definition riscv/opcodes.hpp:4456
LIEF::assembly::riscv::OPCODE::VAND_VV
@ VAND_VV
Definition riscv/opcodes.hpp:13155
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M2_MASK
@ PseudoVSOXSEG3EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9336
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_M1
@ PseudoVLUXSEG7EI64_V_M1_M1
Definition riscv/opcodes.hpp:6282
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF2_MASK
@ PseudoVLUXSEG6EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6185
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF8_MASK
@ PseudoVWMULU_VV_MF8_MASK
Definition riscv/opcodes.hpp:11574
LIEF::assembly::riscv::OPCODE::VLOXEI8_V
@ VLOXEI8_V
Definition riscv/opcodes.hpp:13335
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E16
@ PseudoVFREC7_V_MF2_E16
Definition riscv/opcodes.hpp:2929
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_MF4
@ PseudoVSBC_VXM_MF4
Definition riscv/opcodes.hpp:8700
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M1
@ PseudoVLOXSEG3EI64_V_M2_M1
Definition riscv/opcodes.hpp:4534
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_M1_MASK
@ PseudoVSOXSEG2EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9184
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF4
@ PseudoVFNCVT_RTZ_XU_F_W_MF4
Definition riscv/opcodes.hpp:2575
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E64_MASK
@ PseudoVREMU_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:8097
LIEF::assembly::riscv::OPCODE::VSADDU_VX
@ VSADDU_VX
Definition riscv/opcodes.hpp:13624
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_M1_MASK
@ PseudoVLOXSEG5EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4753
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E16_MASK
@ PseudoVFSGNJX_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:3230
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF8_MASK
@ PseudoVOR_VX_MF8_MASK
Definition riscv/opcodes.hpp:7667
LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_MF4
@ PseudoVADC_VIM_MF4
Definition riscv/opcodes.hpp:582
LIEF::assembly::riscv::OPCODE::InsnCA
@ InsnCA
Definition riscv/opcodes.hpp:12814
LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_M1
@ PseudoVMNAND_MM_M1
Definition riscv/opcodes.hpp:6882
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF2_MASK
@ PseudoVXOR_VV_MF2_MASK
Definition riscv/opcodes.hpp:11862
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF4
@ PseudoVSUXEI32_V_M1_MF4
Definition riscv/opcodes.hpp:10551
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_M1_MASK
@ PseudoVLSEG8E16_V_M1_MASK
Definition riscv/opcodes.hpp:5365
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M8_MASK
@ PseudoVMFEQ_VFPR16_M8_MASK
Definition riscv/opcodes.hpp:6605
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_MF2_E32_MASK
@ PseudoVFDIV_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:1884
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M2
@ PseudoVMFGT_VFPR32_M2
Definition riscv/opcodes.hpp:6684
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M1
@ PseudoVMV_V_V_M1
Definition riscv/opcodes.hpp:7397
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_MF2_MASK
@ PseudoVSOXSEG2EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9274
LIEF::assembly::riscv::OPCODE::FCVT_L_S
@ FCVT_L_S
Definition riscv/opcodes.hpp:12613
LIEF::assembly::riscv::OPCODE::VAADDU_VV
@ VAADDU_VV
Definition riscv/opcodes.hpp:13131
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF8_MASK
@ PseudoVLUXSEG7EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:6261
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E16_MASK
@ PseudoVFWMACCBF16_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3720
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M2
@ PseudoVSOXSEG3EI64_V_M8_M2
Definition riscv/opcodes.hpp:9371
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF8
@ PseudoVSSUBU_VV_MF8
Definition riscv/opcodes.hpp:10431
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M4_MASK
@ PseudoVLOXSEG2EI64_V_M8_M4_MASK
Definition riscv/opcodes.hpp:4433
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF2_MASK
@ PseudoVSRA_VI_MF2_MASK
Definition riscv/opcodes.hpp:9872
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E16_MASK
@ PseudoVFMSUB_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:2289
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_M1
@ PseudoVLOXEI8_V_MF8_M1
Definition riscv/opcodes.hpp:4326
LIEF::assembly::riscv::OPCODE::VFNMADD_VF
@ VFNMADD_VF
Definition riscv/opcodes.hpp:13245
LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M2
@ PseudoVLE32_V_M2
Definition riscv/opcodes.hpp:4119
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M2_MASK
@ PseudoVLUXEI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:5573
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E8_MASK
@ PseudoVREMU_VV_MF2_E8_MASK
Definition riscv/opcodes.hpp:8121
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_M8
@ PseudoVMV_V_I_M8
Definition riscv/opcodes.hpp:7393
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF2
@ PseudoVSUXSEG5EI32_V_M1_MF2
Definition riscv/opcodes.hpp:11037
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E32_MASK
@ PseudoVREDOR_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:7955
LIEF::assembly::riscv::OPCODE::VL8RE64_V
@ VL8RE64_V
Definition riscv/opcodes.hpp:13321
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2_MASK_TIED
@ PseudoVWSUB_WV_M2_MASK_TIED
Definition riscv/opcodes.hpp:11809
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_MF2_MASK
@ PseudoVSUXSEG6EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11104
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E64_MASK
@ PseudoVFNMSUB_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:2830
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E32
@ PseudoVFREDOSUM_VS_M4_E32
Definition riscv/opcodes.hpp:3009
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF4_MASK
@ PseudoVFCLASS_V_MF4_MASK
Definition riscv/opcodes.hpp:1670
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF4_E16
@ PseudoVFWNMACC_VV_MF4_E16
Definition riscv/opcodes.hpp:3873
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E64_V_M1
@ PseudoVSSEG8E64_V_M1
Definition riscv/opcodes.hpp:10153
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF8
@ PseudoVMSEQ_VV_MF8
Definition riscv/opcodes.hpp:6978
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_M1_MASK
@ PseudoVLOXSEG6EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4811
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF4_E16_MASK
@ PseudoVFNMADD_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2686
LIEF::assembly::riscv::OPCODE::VID_V
@ VID_V
Definition riscv/opcodes.hpp:13305
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E32_MASK
@ PseudoVDIVU_VX_M2_E32_MASK
Definition riscv/opcodes.hpp:1478
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E16
@ PseudoVFSUB_VV_M1_E16
Definition riscv/opcodes.hpp:3421
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF8
@ PseudoVSSSEG6E8_V_MF8
Definition riscv/opcodes.hpp:10377
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF2
@ PseudoVSSSEG8E8_V_MF2
Definition riscv/opcodes.hpp:10413
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF4
@ PseudoVWMACCUS_VX_MF4
Definition riscv/opcodes.hpp:11487
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_M1_MASK
@ PseudoVSUXSEG8EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11304
LIEF::assembly::riscv::OPCODE::VMADD_VV
@ VMADD_VV
Definition riscv/opcodes.hpp:13492
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF2_MASK
@ PseudoVLSEG6E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5287
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF4_MASK
@ PseudoVSUXSEG3EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:10896
LIEF::assembly::riscv::OPCODE::PseudoRVVInitUndefM8
@ PseudoRVVInitUndefM8
Definition riscv/opcodes.hpp:438
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF2
@ PseudoVLUXSEG5EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:6096
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF4
@ PseudoVSOXSEG8EI32_V_M1_MF4
Definition riscv/opcodes.hpp:9775
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M4
@ PseudoVSOXSEG2EI16_V_M1_M4
Definition riscv/opcodes.hpp:9159
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF4
@ PseudoVSSEG5E16_V_MF4
Definition riscv/opcodes.hpp:10087
LIEF::assembly::riscv::OPCODE::VFWNMACC_VV
@ VFWNMACC_VV
Definition riscv/opcodes.hpp:13294
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M1_E16_MASK
@ PseudoVFNCVTBF16_F_F_W_M1_E16_MASK
Definition riscv/opcodes.hpp:2418
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF2_MASK
@ PseudoVSSSEG5E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10342
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M2
@ PseudoVMV_V_V_M2
Definition riscv/opcodes.hpp:7398
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M2_E32
@ PseudoVFADD_VFPR32_M2_E32
Definition riscv/opcodes.hpp:1613
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E32_MASK
@ PseudoVFNMSUB_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:2828
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_MF2
@ PseudoVSUXSEG5EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:11079
LIEF::assembly::riscv::OPCODE::Insn32
@ Insn32
Definition riscv/opcodes.hpp:12812
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF4_E16_MASK
@ PseudoVFADD_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:1610
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E32_MASK
@ PseudoVFNCVT_F_F_W_MF2_E32_MASK
Definition riscv/opcodes.hpp:2450
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M8
@ PseudoVFSLIDE1UP_VFPR64_M8
Definition riscv/opcodes.hpp:3359
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_M1
@ PseudoVSOXSEG2EI64_V_M1_M1
Definition riscv/opcodes.hpp:9225
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E32_MASK
@ PseudoVREDXOR_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:8035
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M4_MASK
@ PseudoVMFEQ_VFPR64_M4_MASK
Definition riscv/opcodes.hpp:6625
LIEF::assembly::riscv::OPCODE::TH_LRHU
@ TH_LRHU
Definition riscv/opcodes.hpp:13076
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF4_MASK
@ PseudoVWSUB_VV_MF4_MASK
Definition riscv/opcodes.hpp:11788
LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B2
@ PseudoVMCLR_M_B2
Definition riscv/opcodes.hpp:6572
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M8_MASK
@ PseudoVMULH_VV_M8_MASK
Definition riscv/opcodes.hpp:7340
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E16
@ PseudoVREDMINU_VS_M4_E16
Definition riscv/opcodes.hpp:7848
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M1_MASK
@ PseudoVFSLIDE1UP_VFPR16_M1_MASK
Definition riscv/opcodes.hpp:3332
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF2
@ PseudoVLSEG3E16FF_V_MF2
Definition riscv/opcodes.hpp:5130
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_M1
@ PseudoVLOXSEG5EI64_V_M2_M1
Definition riscv/opcodes.hpp:4738
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF2
@ PseudoVADD_VV_MF2
Definition riscv/opcodes.hpp:620
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF2
@ PseudoVNCLIP_WI_MF2
Definition riscv/opcodes.hpp:7468
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_M8
@ PseudoVC_V_XV_M8
Definition riscv/opcodes.hpp:1371
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M8
@ PseudoVSBC_VVM_M8
Definition riscv/opcodes.hpp:8691
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_MF2
@ PseudoTHVdotVMAQASU_VV_MF2
Definition riscv/opcodes.hpp:458
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M1_E32_MASK
@ PseudoVFSUB_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3404
LIEF::assembly::riscv::OPCODE::G_FSINH
@ G_FSINH
Definition riscv/opcodes.hpp:270
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF8_E8
@ PseudoVREDMINU_VS_MF8_E8
Definition riscv/opcodes.hpp:7874
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M4
@ PseudoVMSNE_VV_M4
Definition riscv/opcodes.hpp:7239
LIEF::assembly::riscv::OPCODE::AMOSWAP_D_RL
@ AMOSWAP_D_RL
Definition riscv/opcodes.hpp:12090
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_M1_MASK
@ PseudoVSOXSEG5EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9518
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M2_E16_MASK
@ PseudoVFMUL_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2315
LIEF::assembly::riscv::OPCODE::ORN
@ ORN
Definition riscv/opcodes.hpp:12909
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E16
@ PseudoVFREDMAX_VS_M4_E16
Definition riscv/opcodes.hpp:2947
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E64_MASK
@ PseudoVFSUB_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:3444
LIEF::assembly::riscv::OPCODE::CV_ADDUNR
@ CV_ADDUNR
Definition riscv/opcodes.hpp:12169
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M1
@ PseudoVLOXEI64_V_M8_M1
Definition riscv/opcodes.hpp:4282
LIEF::assembly::riscv::OPCODE::VSUXSEG6EI16_V
@ VSUXSEG6EI16_V
Definition riscv/opcodes.hpp:13790
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF2_MASK
@ PseudoVLUXSEG2EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:5799
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M2
@ PseudoVSUXSEG2EI8_V_M1_M2
Definition riscv/opcodes.hpp:10761
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF8
@ PseudoVSOXSEG4EI64_V_M1_MF8
Definition riscv/opcodes.hpp:9463
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF4_MASK
@ PseudoVLUXSEG7EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:6279
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF4_MASK
@ PseudoVSSEG2E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10000
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF8
@ PseudoVSOXSEG6EI64_V_M1_MF8
Definition riscv/opcodes.hpp:9637
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E8_MASK
@ PseudoVREDMAX_VS_M2_E8_MASK
Definition riscv/opcodes.hpp:7803
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E16
@ PseudoVFCVT_F_X_V_M1_E16
Definition riscv/opcodes.hpp:1701
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF4_E16
@ PseudoVFADD_VV_MF4_E16
Definition riscv/opcodes.hpp:1657
LIEF::assembly::riscv::OPCODE::VSSE64_V
@ VSSE64_V
Definition riscv/opcodes.hpp:13700
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E8
@ PseudoVDIVU_VV_MF4_E8
Definition riscv/opcodes.hpp:1463
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_M8
@ PseudoVC_V_FPR16VV_SE_M8
Definition riscv/opcodes.hpp:1175
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E64_MASK
@ PseudoVREDXOR_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:8013
LIEF::assembly::riscv::OPCODE::CV_DOTUP_SC_B
@ CV_DOTUP_SC_B
Definition riscv/opcodes.hpp:12291
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M4
@ PseudoVROR_VI_M4
Definition riscv/opcodes.hpp:8538
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E8_MASK
@ PseudoVREMU_VX_MF4_E8_MASK
Definition riscv/opcodes.hpp:8169
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M1
@ PseudoVMSLEU_VV_M1
Definition riscv/opcodes.hpp:7093
LIEF::assembly::riscv::OPCODE::AMOOR_W_AQ
@ AMOOR_W_AQ
Definition riscv/opcodes.hpp:12080
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M2_MASK
@ PseudoVSOXSEG3EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9376
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M2
@ PseudoVLOXSEG3EI16_V_M2_M2
Definition riscv/opcodes.hpp:4478
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M8_MASK
@ PseudoVRGATHEREI16_VV_M4_E16_M8_MASK
Definition riscv/opcodes.hpp:8345
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF8
@ PseudoVLUXSEG3EI64_V_M1_MF8
Definition riscv/opcodes.hpp:5924
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E16
@ PseudoVFWCVT_F_F_V_M4_E16
Definition riscv/opcodes.hpp:3567
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M1_MASK
@ PseudoVFCVT_XU_F_V_M1_MASK
Definition riscv/opcodes.hpp:1840
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M4
@ PseudoVSBC_VXM_M4
Definition riscv/opcodes.hpp:8697
LIEF::assembly::riscv::OPCODE::VSUXSEG2EI16_V
@ VSUXSEG2EI16_V
Definition riscv/opcodes.hpp:13774
LIEF::assembly::riscv::OPCODE::VMSBF_M
@ VMSBF_M
Definition riscv/opcodes.hpp:13525
LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_4x8x4_MF2
@ PseudoVQMACCU_4x8x4_MF2
Definition riscv/opcodes.hpp:7691
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M4
@ PseudoVMFLT_VV_M4
Definition riscv/opcodes.hpp:6776
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E32_MASK
@ PseudoVFNCVT_F_XU_W_MF2_E32_MASK
Definition riscv/opcodes.hpp:2468
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E32
@ PseudoVFMADD_VV_MF2_E32
Definition riscv/opcodes.hpp:2053
LIEF::assembly::riscv::OPCODE::G_FRINT
@ G_FRINT
Definition riscv/opcodes.hpp:274
LIEF::assembly::riscv::OPCODE::TH_SWIB
@ TH_SWIB
Definition riscv/opcodes.hpp:13122
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF2
@ PseudoVMFLE_VV_MF2
Definition riscv/opcodes.hpp:6738
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M1_E32_MASK
@ PseudoVFRSUB_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3104
LIEF::assembly::riscv::OPCODE::FDIV_S
@ FDIV_S
Definition riscv/opcodes.hpp:12648
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M2_MASK
@ PseudoVMSEQ_VI_M2_MASK
Definition riscv/opcodes.hpp:6955
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF8_MASK
@ PseudoVFNRCLIP_XU_F_QF_MF8_MASK
Definition riscv/opcodes.hpp:2864
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M1_E16
@ PseudoVFNMACC_VFPR16_M1_E16
Definition riscv/opcodes.hpp:2615
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M1_M1
@ PseudoVSUXSEG7EI16_V_M1_M1
Definition riscv/opcodes.hpp:11175
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M1_MASK
@ PseudoVRGATHEREI16_VV_M4_E64_M1_MASK
Definition riscv/opcodes.hpp:8355
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_M1_MASK
@ PseudoVLOXSEG7EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4899
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M4
@ PseudoVLE16FF_V_M4
Definition riscv/opcodes.hpp:4087
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M2
@ PseudoVSSRL_VI_M2
Definition riscv/opcodes.hpp:10207
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF2_MASK
@ PseudoVLUXSEG8EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6345
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E16
@ PseudoVREDMIN_VS_MF4_E16
Definition riscv/opcodes.hpp:7914
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF4
@ PseudoVLSEG2E16_V_MF4
Definition riscv/opcodes.hpp:5072
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_M1
@ PseudoVLOXSEG8EI64_V_M1_M1
Definition riscv/opcodes.hpp:4970
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_MF4_MASK
@ PseudoVFCVT_RM_X_F_V_MF4_MASK
Definition riscv/opcodes.hpp:1814
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_M1_MASK
@ PseudoVLUXSEG4EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:6075
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M8
@ PseudoVRGATHEREI16_VV_M4_E32_M8
Definition riscv/opcodes.hpp:8352
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF8_MASK
@ PseudoVSSUBU_VX_MF8_MASK
Definition riscv/opcodes.hpp:10446
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF4_MASK
@ PseudoVLSEG4E8FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5225
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2_MASK_TIED
@ PseudoVWSUB_WV_MF2_MASK_TIED
Definition riscv/opcodes.hpp:11817
LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_M1
@ PseudoVSPILL2_M1
Definition riscv/opcodes.hpp:9831
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_XOR
@ G_ATOMICRMW_XOR
Definition riscv/opcodes.hpp:129
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E8_MASK
@ PseudoVREM_VV_M8_E8_MASK
Definition riscv/opcodes.hpp:8203
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E16
@ PseudoVFWREDOSUM_VS_M1_E16
Definition riscv/opcodes.hpp:3911
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF4
@ PseudoVCPOP_V_MF4
Definition riscv/opcodes.hpp:1060
LIEF::assembly::riscv::OPCODE::CV_MACHHSN
@ CV_MACHHSN
Definition riscv/opcodes.hpp:12334
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_M1_MASK
@ PseudoVSUXSEG8EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11318
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E64_MASK
@ PseudoVFMSUB_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:2287
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF8_MASK
@ PseudoVSSE8_V_MF8_MASK
Definition riscv/opcodes.hpp:9990
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF8
@ PseudoVWSUBU_VV_MF8
Definition riscv/opcodes.hpp:11729
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M4
@ PseudoVSLIDE1UP_VX_M4
Definition riscv/opcodes.hpp:8812
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M4_MASK
@ PseudoVSUXEI64_V_M8_M4_MASK
Definition riscv/opcodes.hpp:10612
LIEF::assembly::riscv::OPCODE::AMOOR_W_RL
@ AMOOR_W_RL
Definition riscv/opcodes.hpp:12082
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E16
@ PseudoVREDMIN_VS_MF2_E16
Definition riscv/opcodes.hpp:7908
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M1
@ PseudoVLOXSEG3EI32_V_M2_M1
Definition riscv/opcodes.hpp:4506
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF4_MASK
@ PseudoVMULH_VV_MF4_MASK
Definition riscv/opcodes.hpp:7344
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M8_E64
@ PseudoVFRSUB_VFPR64_M8_E64
Definition riscv/opcodes.hpp:3119
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M2_MASK
@ PseudoVLOXSEG2EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4373
LIEF::assembly::riscv::OPCODE::CV_SRL_SCI_B
@ CV_SRL_SCI_B
Definition riscv/opcodes.hpp:12439
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_M1
@ PseudoVSSSEG5E16_V_M1
Definition riscv/opcodes.hpp:10339
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M4_MASK
@ PseudoVSADD_VX_M4_MASK
Definition riscv/opcodes.hpp:8679
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M1_MASK
@ PseudoVZEXT_VF2_M1_MASK
Definition riscv/opcodes.hpp:11882
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M8_E16_MASK
@ PseudoVFNMSUB_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2802
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF2
@ PseudoVSUXSEG2EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:10689
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M2_M1
@ PseudoVSUXSEG8EI16_V_M2_M1
Definition riscv/opcodes.hpp:11259
LIEF::assembly::riscv::OPCODE::PseudoLGA
@ PseudoLGA
Definition riscv/opcodes.hpp:393
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK
@ PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK
Definition riscv/opcodes.hpp:8421
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_M4
@ PseudoVC_FPR16VW_SE_M4
Definition riscv/opcodes.hpp:1086
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M2_E16
@ PseudoVFWADD_WFPR16_M2_E16
Definition riscv/opcodes.hpp:3489
LIEF::assembly::riscv::OPCODE::InsnR
@ InsnR
Definition riscv/opcodes.hpp:12826
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E64
@ PseudoVFNMACC_VV_M2_E64
Definition riscv/opcodes.hpp:2655
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF4
@ PseudoVMFGE_VFPR16_MF4
Definition riscv/opcodes.hpp:6650
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF4_MASK
@ PseudoVAND_VI_MF4_MASK
Definition riscv/opcodes.hpp:829
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E64
@ PseudoVFSGNJX_VV_M1_E64
Definition riscv/opcodes.hpp:3215
LIEF::assembly::riscv::OPCODE::VFNMSAC_VF
@ VFNMSAC_VF
Definition riscv/opcodes.hpp:13247
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32_M8
@ PseudoVFMV_S_FPR32_M8
Definition riscv/opcodes.hpp:2396
LIEF::assembly::riscv::OPCODE::G_INTRINSIC_ROUND
@ G_INTRINSIC_ROUND
Definition riscv/opcodes.hpp:107
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M4
@ PseudoVMSGTU_VI_M4
Definition riscv/opcodes.hpp:7013
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M2
@ PseudoTHVdotVMAQA_VV_M2
Definition riscv/opcodes.hpp:502
LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B4
@ PseudoVMSET_M_B4
Definition riscv/opcodes.hpp:6998
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M8_MASK
@ PseudoVROR_VX_M8_MASK
Definition riscv/opcodes.hpp:8569
LIEF::assembly::riscv::OPCODE::CV_SUB_DIV8
@ CV_SUB_DIV8
Definition riscv/opcodes.hpp:12458
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E32_MASK
@ PseudoVFCVT_F_XU_V_M1_E32_MASK
Definition riscv/opcodes.hpp:1674
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M4
@ PseudoVWMACCU_VV_M4
Definition riscv/opcodes.hpp:11495
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF4
@ PseudoVMSLE_VI_MF4
Definition riscv/opcodes.hpp:7131
LIEF::assembly::riscv::OPCODE::VZEXT_VF4
@ VZEXT_VF4
Definition riscv/opcodes.hpp:13842
LIEF::assembly::riscv::OPCODE::FENCE
@ FENCE
Definition riscv/opcodes.hpp:12650
LIEF::assembly::riscv::OPCODE::G_SMULFIXSAT
@ G_SMULFIXSAT
Definition riscv/opcodes.hpp:190
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M1_E16_MASK
@ PseudoVFRSUB_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3092
LIEF::assembly::riscv::OPCODE::VROL_VV
@ VROL_VV
Definition riscv/opcodes.hpp:13611
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF2_MASK
@ PseudoVSSEG4E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10078
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E32_MASK
@ PseudoVFNMSAC_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:2774
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF2_MASK
@ PseudoVLUXSEG7EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:6317
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E32
@ PseudoVFWMACCBF16_VV_M2_E32
Definition riscv/opcodes.hpp:3713
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E64_MASK
@ PseudoVFREC7_V_M4_E64_MASK
Definition riscv/opcodes.hpp:2922
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF8_MASK
@ PseudoVSUXSEG2EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:10728
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E32_MASK
@ PseudoVDIV_VX_M1_E32_MASK
Definition riscv/opcodes.hpp:1558
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M4
@ PseudoVBREV8_V_M4
Definition riscv/opcodes.hpp:920
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF8_MASK
@ PseudoVSUXSEG3EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:10822
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_M1_MASK
@ PseudoVLOXSEG7EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4877
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M2
@ PseudoVSUXSEG2EI8_V_MF2_M2
Definition riscv/opcodes.hpp:10773
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E32_MASK
@ PseudoVWREDSUMU_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:11614
LIEF::assembly::riscv::OPCODE::InsnCR
@ InsnCR
Definition riscv/opcodes.hpp:12820
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E8_MASK
@ PseudoVREM_VV_M4_E8_MASK
Definition riscv/opcodes.hpp:8195
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF8
@ PseudoVLE8FF_V_MF8
Definition riscv/opcodes.hpp:4155
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E64_MASK
@ PseudoVFNMADD_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:2728
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF4
@ PseudoVLOXSEG2EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:4360
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_MF2
@ PseudoVFSLIDE1UP_VFPR32_MF2
Definition riscv/opcodes.hpp:3351
LIEF::assembly::riscv::OPCODE::PseudoCCMOVGPRNoX0
@ PseudoCCMOVGPRNoX0
Definition riscv/opcodes.hpp:348
LIEF::assembly::riscv::OPCODE::CV_MAXU_B
@ CV_MAXU_B
Definition riscv/opcodes.hpp:12344
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E16_MASK
@ PseudoVFSGNJ_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3296
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M2
@ PseudoVMADD_VV_M2
Definition riscv/opcodes.hpp:6474
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M8
@ PseudoVSRL_VV_M8
Definition riscv/opcodes.hpp:9925
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M4_MASK
@ PseudoVSUXSEG2EI8_V_MF2_M4_MASK
Definition riscv/opcodes.hpp:10776
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF2
@ PseudoVLOXSEG7EI64_V_M2_MF2
Definition riscv/opcodes.hpp:4900
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_M1_MASK
@ PseudoVLUXSEG7EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6249
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M8_M2
@ PseudoVLUXSEG4EI32_V_M8_M2
Definition riscv/opcodes.hpp:6018
LIEF::assembly::riscv::OPCODE::VFMADD_VF
@ VFMADD_VF
Definition riscv/opcodes.hpp:13218
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_MF8
@ PseudoVC_V_IVV_MF8
Definition riscv/opcodes.hpp:1254
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M1
@ PseudoVSSEG4E32_V_M1
Definition riscv/opcodes.hpp:10063
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M1_E64
@ PseudoVFMSUB_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2274
LIEF::assembly::riscv::OPCODE::G_UCMP
@ G_UCMP
Definition riscv/opcodes.hpp:168
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF2_MASK
@ PseudoVLSEG2E8FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5109
LIEF::assembly::riscv::OPCODE::VSSEG5E64_V
@ VSSEG5E64_V
Definition riscv/opcodes.hpp:13716
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E32_MASK
@ PseudoVREM_VX_MF2_E32_MASK
Definition riscv/opcodes.hpp:8251
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E16_MASK
@ PseudoVDIVU_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:1424
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E64
@ PseudoVFCVT_RM_F_X_V_M8_E64
Definition riscv/opcodes.hpp:1783
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M2
@ PseudoVLOXSEG4EI8_V_M1_M2
Definition riscv/opcodes.hpp:4664
LIEF::assembly::riscv::OPCODE::CV_CMPGT_B
@ CV_CMPGT_B
Definition riscv/opcodes.hpp:12235
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M2
@ PseudoVAADD_VX_M2
Definition riscv/opcodes.hpp:565
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M1_MASK
@ PseudoVLOXSEG2EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4435
LIEF::assembly::riscv::OPCODE::VLSEG5E8FF_V
@ VLSEG5E8FF_V
Definition riscv/opcodes.hpp:13398
LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M2
@ PseudoVSM4K_VI_M2
Definition riscv/opcodes.hpp:8931
LIEF::assembly::riscv::OPCODE::TH_LURHU
@ TH_LURHU
Definition riscv/opcodes.hpp:13083
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF2
@ PseudoVLUXEI64_V_M2_MF2
Definition riscv/opcodes.hpp:5662
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF4_MASK
@ PseudoVSUXSEG2EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:10744
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_M1_MASK
@ PseudoVSSEG8E16_V_M1_MASK
Definition riscv/opcodes.hpp:10144
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M2_E64
@ PseudoVFSUB_VFPR64_M2_E64
Definition riscv/opcodes.hpp:3415
LIEF::assembly::riscv::OPCODE::PseudoVID_V_M1_MASK
@ PseudoVID_V_M1_MASK
Definition riscv/opcodes.hpp:4056
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M4_E16_MASK
@ PseudoVFMUL_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2317
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E32_MASK
@ PseudoVREDSUM_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:7999
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E16_MASK
@ PseudoVDIV_VX_MF2_E16_MASK
Definition riscv/opcodes.hpp:1588
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M2_M2_MASK
@ PseudoVLOXSEG4EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4667
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF2_MASK
@ PseudoVLSEG6E16FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5281
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_M1_MASK
@ PseudoVSUXSEG6EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:11108
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_M2
@ PseudoVLUXSEG4EI32_V_M2_M2
Definition riscv/opcodes.hpp:6010
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M2
@ PseudoVSOXEI64_V_M4_M2
Definition riscv/opcodes.hpp:9097
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF2_MASK
@ PseudoVLOXSEG4EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4639
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M4_E16
@ PseudoVFWMSAC_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3771
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E32_MASK
@ PseudoVDIVU_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:1442
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF8_E8_MASK
@ PseudoVWREDSUM_VS_MF8_E8_MASK
Definition riscv/opcodes.hpp:11682
LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_2x8x2_M8
@ PseudoVQMACCSU_2x8x2_M8
Definition riscv/opcodes.hpp:7671
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF4
@ PseudoVNMSAC_VX_MF4
Definition riscv/opcodes.hpp:7522
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_M1
@ PseudoVSUXSEG2EI64_V_M1_M1
Definition riscv/opcodes.hpp:10729
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E32
@ PseudoVFREDMAX_VS_MF2_E32
Definition riscv/opcodes.hpp:2961
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M1
@ PseudoVSADD_VX_M1
Definition riscv/opcodes.hpp:8674
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF8_MASK
@ PseudoVWSUBU_WX_MF8_MASK
Definition riscv/opcodes.hpp:11778
LIEF::assembly::riscv::OPCODE::VSUXSEG8EI16_V
@ VSUXSEG8EI16_V
Definition riscv/opcodes.hpp:13798
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF4_MASK
@ PseudoVMINU_VX_MF4_MASK
Definition riscv/opcodes.hpp:6851
LIEF::assembly::riscv::OPCODE::VFCVT_F_X_V
@ VFCVT_F_X_V
Definition riscv/opcodes.hpp:13208
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_M1_MASK
@ PseudoVLOXSEG7EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4913
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M1_MASK
@ PseudoVNCLIP_WX_M1_MASK
Definition riscv/opcodes.hpp:7487
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M4_E64
@ PseudoVFSGNJX_VFPR64_M4_E64
Definition riscv/opcodes.hpp:3207
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF8
@ PseudoVMULH_VV_MF8
Definition riscv/opcodes.hpp:7345
LIEF::assembly::riscv::OPCODE::AMOSWAP_H_AQ_RL
@ AMOSWAP_H_AQ_RL
Definition riscv/opcodes.hpp:12093
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF2
@ PseudoVLUXSEG2EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:5756
LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_MF2
@ PseudoVSPILL6_MF2
Definition riscv/opcodes.hpp:9852
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M2
@ PseudoVSADD_VX_M2
Definition riscv/opcodes.hpp:8676
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M2_E16
@ PseudoVFWADD_VV_M2_E16
Definition riscv/opcodes.hpp:3473
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF8_MASK
@ PseudoVLOXSEG6EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:4817
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF2_MASK
@ PseudoVWADD_WX_MF2_MASK
Definition riscv/opcodes.hpp:11450
LIEF::assembly::riscv::OPCODE::VFWMUL_VF
@ VFWMUL_VF
Definition riscv/opcodes.hpp:13291
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK
@ PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK
Definition riscv/opcodes.hpp:2494
LIEF::assembly::riscv::OPCODE::CV_SLET
@ CV_SLET
Definition riscv/opcodes.hpp:12423
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E32_MASK
@ PseudoVFDIV_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:1920
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF2_MASK
@ PseudoVNCLIP_WX_MF2_MASK
Definition riscv/opcodes.hpp:7493
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_MF2_E16_MASK
@ PseudoVFMIN_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2141
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E16_MASK
@ PseudoVREDMINU_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:7857
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF8
@ PseudoVXOR_VI_MF8
Definition riscv/opcodes.hpp:11851
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M8_E32
@ PseudoVFMSAC_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2210
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E32
@ PseudoVFMADD_VV_M1_E32
Definition riscv/opcodes.hpp:2029
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF4_E16_MASK
@ PseudoVFSQRT_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:3390
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M4
@ PseudoVLOXSEG2EI32_V_M4_M4
Definition riscv/opcodes.hpp:4390
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16
@ PseudoVFWSUB_WV_M2_E16
Definition riscv/opcodes.hpp:4017
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E16
@ PseudoVFCVT_RM_F_X_V_M1_E16
Definition riscv/opcodes.hpp:1761
LIEF::assembly::riscv::OPCODE::VC_V_XVW
@ VC_V_XVW
Definition riscv/opcodes.hpp:13195
LIEF::assembly::riscv::OPCODE::AMOMAXU_B_AQ
@ AMOMAXU_B_AQ
Definition riscv/opcodes.hpp:12004
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M2_MASK
@ PseudoVSUXSEG3EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10862
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M4_MASK
@ PseudoVADD_VX_M4_MASK
Definition riscv/opcodes.hpp:631
LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_D_IN32X
@ PseudoQuietFLE_D_IN32X
Definition riscv/opcodes.hpp:419
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M2_E64_MASK
@ PseudoVFMAX_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2082
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M1_MASK
@ PseudoVLOXSEG3EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4535
LIEF::assembly::riscv::OPCODE::CV_SB_rr
@ CV_SB_rr
Definition riscv/opcodes.hpp:12391
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF2_MASK
@ PseudoVNCLIP_WV_MF2_MASK
Definition riscv/opcodes.hpp:7481
LIEF::assembly::riscv::OPCODE::FCVT_H_L_INX
@ FCVT_H_L_INX
Definition riscv/opcodes.hpp:12596
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E64_MASK
@ PseudoVRGATHER_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:8477
LIEF::assembly::riscv::OPCODE::AMOXOR_W_RL
@ AMOXOR_W_RL
Definition riscv/opcodes.hpp:12114
LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B2
@ PseudoVSM_V_B2
Definition riscv/opcodes.hpp:8994
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E16
@ PseudoVREDSUM_VS_MF2_E16
Definition riscv/opcodes.hpp:7996
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M4_MASK
@ PseudoVLOXSEG2EI16_V_M1_M4_MASK
Definition riscv/opcodes.hpp:4339
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF8_MASK
@ PseudoVLSSEG6E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5529
LIEF::assembly::riscv::OPCODE::VWMULU_VV
@ VWMULU_VV
Definition riscv/opcodes.hpp:13821
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M2_MASK
@ PseudoVSSEG4E16_V_M2_MASK
Definition riscv/opcodes.hpp:10058
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M4_E16
@ PseudoVFMIN_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2136
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF2_MASK
@ PseudoVMSGT_VX_MF2_MASK
Definition riscv/opcodes.hpp:7060
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M2_E32
@ PseudoVFWSUB_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3967
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF2
@ PseudoVMIN_VX_MF2
Definition riscv/opcodes.hpp:6876
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M1
@ PseudoVANDN_VV_M1
Definition riscv/opcodes.hpp:790
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M4_E16
@ PseudoVFNMACC_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2619
LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_MF4
@ PseudoVC_IVV_SE_MF4
Definition riscv/opcodes.hpp:1124
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF8_MASK
@ PseudoVCTZ_V_MF8_MASK
Definition riscv/opcodes.hpp:1077
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M2_E32_MASK
@ PseudoVFMADD_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2012
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF2_MASK
@ PseudoVCLMUL_VX_MF2_MASK
Definition riscv/opcodes.hpp:995
LIEF::assembly::riscv::OPCODE::REV8_RV64
@ REV8_RV64
Definition riscv/opcodes.hpp:12929
LIEF::assembly::riscv::OPCODE::FROUND_D
@ FROUND_D
Definition riscv/opcodes.hpp:12753
LIEF::assembly::riscv::OPCODE::AMOMAX_H
@ AMOMAX_H
Definition riscv/opcodes.hpp:12027
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E8
@ PseudoVFWCVT_F_X_V_MF2_E8
Definition riscv/opcodes.hpp:3629
LIEF::assembly::riscv::OPCODE::VFMAX_VF
@ VFMAX_VF
Definition riscv/opcodes.hpp:13220
LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SC_H
@ CV_CMPGEU_SC_H
Definition riscv/opcodes.hpp:12222
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF4
@ PseudoVSOXSEG3EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:9343
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E16
@ PseudoVREDMAXU_VS_M2_E16
Definition riscv/opcodes.hpp:7752
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M4_M1
@ PseudoVSUXSEG6EI32_V_M4_M1
Definition riscv/opcodes.hpp:11125
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M1_MASK
@ PseudoVLUXSEG3EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:5905
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M4_E16_MASK
@ PseudoVFMADD_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2002
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF4
@ PseudoVMULHU_VX_MF4
Definition riscv/opcodes.hpp:7329
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M4
@ PseudoVLOXEI32_V_M2_M4
Definition riscv/opcodes.hpp:4232
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E32
@ PseudoVREDMAX_VS_M1_E32
Definition riscv/opcodes.hpp:7790
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF4_E16
@ PseudoVFMSAC_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2202
LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M4_MASK
@ PseudoVLSE32_V_M4_MASK
Definition riscv/opcodes.hpp:5027
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M8
@ PseudoVSUXEI16_V_M4_M8
Definition riscv/opcodes.hpp:10523
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF4_MASK
@ PseudoVREV8_V_MF4_MASK
Definition riscv/opcodes.hpp:8271
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_M1
@ PseudoVFWMACC_4x4x4_M1
Definition riscv/opcodes.hpp:3725
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M2
@ PseudoVFSLIDE1UP_VFPR64_M2
Definition riscv/opcodes.hpp:3355
LIEF::assembly::riscv::OPCODE::VSOXSEG7EI16_V
@ VSOXSEG7EI16_V
Definition riscv/opcodes.hpp:13684
LIEF::assembly::riscv::OPCODE::G_SHL
@ G_SHL
Definition riscv/opcodes.hpp:158
LIEF::assembly::riscv::OPCODE::PseudoFROUND_H
@ PseudoFROUND_H
Definition riscv/opcodes.hpp:377
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M4_MASK
@ PseudoVLOXEI8_V_MF2_M4_MASK
Definition riscv/opcodes.hpp:4315
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF8
@ PseudoVWMUL_VV_MF8
Definition riscv/opcodes.hpp:11597
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E16
@ PseudoVFMUL_VV_MF2_E16
Definition riscv/opcodes.hpp:2366
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E16_MASK
@ PseudoVFWMACC_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3750
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF2_E32
@ PseudoVFNCVT_RM_F_XU_W_MF2_E32
Definition riscv/opcodes.hpp:2503
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M2_MASK
@ PseudoVSUXSEG4EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:10996
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF8_MASK
@ PseudoVLUXSEG8EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:6361
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M1_MASK
@ PseudoVSOXSEG2EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9268
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_M1
@ PseudoVAESDF_VS_M1_M1
Definition riscv/opcodes.hpp:640
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E32_MASK
@ PseudoVREM_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:8191
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF4_MASK
@ PseudoVLUXSEG3EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:5969
LIEF::assembly::riscv::OPCODE::VSUXEI32_V
@ VSUXEI32_V
Definition riscv/opcodes.hpp:13771
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_M1
@ PseudoVSOXSEG5EI64_V_M1_M1
Definition riscv/opcodes.hpp:9551
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF8_MASK
@ PseudoVWADD_WX_MF8_MASK
Definition riscv/opcodes.hpp:11454
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF4
@ PseudoVLOXSEG8EI64_V_M1_MF4
Definition riscv/opcodes.hpp:4974
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF2_MASK
@ PseudoVWADDU_VX_MF2_MASK
Definition riscv/opcodes.hpp:11354
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E64
@ PseudoVFRSQRT7_V_M4_E64
Definition riscv/opcodes.hpp:3077
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M4
@ PseudoVADD_VV_M4
Definition riscv/opcodes.hpp:616
LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_M1
@ PseudoVC_VVW_SE_M1
Definition riscv/opcodes.hpp:1153
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_MF4
@ PseudoVC_V_FPR16VW_MF4
Definition riscv/opcodes.hpp:1183
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E16
@ PseudoVDIV_VX_M4_E16
Definition riscv/opcodes.hpp:1571
LIEF::assembly::riscv::OPCODE::PseudoAddTPRel
@ PseudoAddTPRel
Definition riscv/opcodes.hpp:329
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M4_M1
@ PseudoVLUXSEG6EI32_V_M4_M1
Definition riscv/opcodes.hpp:6192
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_M1
@ PseudoVLSEG6E32_V_M1
Definition riscv/opcodes.hpp:5294
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M1
@ PseudoVSUXSEG4EI32_V_M4_M1
Definition riscv/opcodes.hpp:10947
LIEF::assembly::riscv::OPCODE::PseudoCCSLL
@ PseudoCCSLL
Definition riscv/opcodes.hpp:352
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF4_MASK
@ PseudoVMSLE_VV_MF4_MASK
Definition riscv/opcodes.hpp:7146
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M8
@ PseudoVROR_VI_M8
Definition riscv/opcodes.hpp:8540
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VW_SE_MF2
@ PseudoVC_FPR32VW_SE_MF2
Definition riscv/opcodes.hpp:1105
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_MF2_MASK
@ PseudoVFCVT_RM_XU_F_V_MF2_MASK
Definition riscv/opcodes.hpp:1800
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF2
@ PseudoVLOXSEG6EI32_V_M1_MF2
Definition riscv/opcodes.hpp:4792
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_M1
@ PseudoVLUXSEG4EI8_V_MF8_M1
Definition riscv/opcodes.hpp:6074
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E16
@ PseudoVFCVT_RM_F_XU_V_M2_E16
Definition riscv/opcodes.hpp:1737
LIEF::assembly::riscv::OPCODE::TH_ICACHE_IALL
@ TH_ICACHE_IALL
Definition riscv/opcodes.hpp:13054
LIEF::assembly::riscv::OPCODE::VSHA2CL_VV
@ VSHA2CL_VV
Definition riscv/opcodes.hpp:13641
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M4_MASK
@ PseudoVLUXEI64_V_M4_M4_MASK
Definition riscv/opcodes.hpp:5671
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF2_MASK
@ PseudoVNCLIPU_WV_MF2_MASK
Definition riscv/opcodes.hpp:7445
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF4
@ PseudoVSSEG3E16_V_MF4
Definition riscv/opcodes.hpp:10033
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF2
@ PseudoVSLIDEUP_VX_MF2
Definition riscv/opcodes.hpp:8872
LIEF::assembly::riscv::OPCODE::XPERM4
@ XPERM4
Definition riscv/opcodes.hpp:13850
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF2
@ PseudoVLUXSEG4EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:5994
LIEF::assembly::riscv::OPCODE::AMOMAX_W_AQ_RL
@ AMOMAX_W_AQ_RL
Definition riscv/opcodes.hpp:12033
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E64_MASK
@ PseudoVFREC7_V_M1_E64_MASK
Definition riscv/opcodes.hpp:2910
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF2
@ PseudoVNSRA_WV_MF2
Definition riscv/opcodes.hpp:7572
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M8_E16_MASK
@ PseudoVFRDIV_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2882
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M1
@ PseudoVLUXSEG2EI32_V_M1_M1
Definition riscv/opcodes.hpp:5762
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M2_MASK
@ PseudoVMFNE_VFPR32_M2_MASK
Definition riscv/opcodes.hpp:6799
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M4_M1_MASK
@ PseudoVSOXSEG5EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9542
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK
@ PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK
Definition riscv/opcodes.hpp:8399
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF4_E16
@ PseudoVFNCVT_F_F_W_MF4_E16
Definition riscv/opcodes.hpp:2451
LIEF::assembly::riscv::OPCODE::FEQ_S
@ FEQ_S
Definition riscv/opcodes.hpp:12658
LIEF::assembly::riscv::OPCODE::TH_LDD
@ TH_LDD
Definition riscv/opcodes.hpp:13065
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF4_MASK
@ PseudoVWSLL_VX_MF4_MASK
Definition riscv/opcodes.hpp:11716
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M1_MASK
@ PseudoVSSEG2E32_V_M1_MASK
Definition riscv/opcodes.hpp:10002
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M1
@ PseudoVSSSEG3E32_V_M1
Definition riscv/opcodes.hpp:10291
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M1_MASK
@ PseudoVWSUB_WX_M1_MASK
Definition riscv/opcodes.hpp:11828
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M4
@ PseudoVMV_V_X_M4
Definition riscv/opcodes.hpp:7406
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_M1
@ PseudoVSUXSEG6EI16_V_MF2_M1
Definition riscv/opcodes.hpp:11101
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_MF2
@ PseudoVMSBC_VX_MF2
Definition riscv/opcodes.hpp:6935
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M4_MASK
@ PseudoVSLIDEUP_VX_M4_MASK
Definition riscv/opcodes.hpp:8869
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M4
@ PseudoVWMACCSU_VV_M4
Definition riscv/opcodes.hpp:11459
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E8_MASK
@ PseudoVDIVU_VX_M8_E8_MASK
Definition riscv/opcodes.hpp:1498
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M2_MASK
@ PseudoVSOXSEG2EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9170
LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M2
@ PseudoVAESKF1_VI_M2
Definition riscv/opcodes.hpp:757
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M2_MASK
@ PseudoVFNCVT_X_F_W_M2_MASK
Definition riscv/opcodes.hpp:2606
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M1_E32
@ PseudoVFMADD_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2009
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E16_MASK
@ PseudoVFWCVT_F_XU_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:3602
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M4_MASK
@ PseudoVMFNE_VFPR32_M4_MASK
Definition riscv/opcodes.hpp:6801
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF4_MASK
@ PseudoVSADDU_VX_MF4_MASK
Definition riscv/opcodes.hpp:8643
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_MF4
@ PseudoVWADDU_VX_MF4
Definition riscv/opcodes.hpp:11355
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF2_MASK
@ PseudoVLSSEG7E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5545
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF4
@ PseudoVSSEG2E16_V_MF4
Definition riscv/opcodes.hpp:9999
LIEF::assembly::riscv::OPCODE::MOPR12
@ MOPR12
Definition riscv/opcodes.hpp:12864
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E32
@ PseudoVFMUL_VV_MF2_E32
Definition riscv/opcodes.hpp:2368
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M8_MASK
@ PseudoVNMSUB_VV_M8_MASK
Definition riscv/opcodes.hpp:7533
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M2
@ PseudoVFCLASS_V_M2
Definition riscv/opcodes.hpp:1661
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M1_MASK
@ PseudoVSOXSEG4EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9402
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M2_E32_MASK
@ PseudoVFDIV_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:1878
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF8
@ PseudoVROR_VV_MF8
Definition riscv/opcodes.hpp:8560
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M4
@ PseudoVSSEG2E16_V_M4
Definition riscv/opcodes.hpp:9995
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M8
@ PseudoVADD_VV_M8
Definition riscv/opcodes.hpp:618
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E16_MASK
@ PseudoVFNMACC_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:2670
LIEF::assembly::riscv::OPCODE::VLSEG3E64FF_V
@ VLSEG3E64FF_V
Definition riscv/opcodes.hpp:13380
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF8_MASK
@ PseudoVCPOP_V_MF8_MASK
Definition riscv/opcodes.hpp:1063
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF4
@ PseudoVSSEG6E8_V_MF4
Definition riscv/opcodes.hpp:10119
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M1_MASK
@ PseudoVSUXSEG2EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:10780
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF2_MASK
@ PseudoVMFGT_VFPR16_MF2_MASK
Definition riscv/opcodes.hpp:6679
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E8
@ PseudoVRGATHER_VV_MF2_E8
Definition riscv/opcodes.hpp:8484
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_M1_MASK
@ PseudoVLSEG7E8_V_M1_MASK
Definition riscv/opcodes.hpp:5351
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M2_MASK
@ PseudoVCLMUL_VX_M2_MASK
Definition riscv/opcodes.hpp:989
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64FF_V_M1_MASK
@ PseudoVLSEG7E64FF_V_M1_MASK
Definition riscv/opcodes.hpp:5339
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_M1
@ PseudoVLUXSEG8EI64_V_M2_M1
Definition riscv/opcodes.hpp:6370
LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_MF2
@ PseudoVSM3ME_VV_MF2
Definition riscv/opcodes.hpp:8929
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF4_MASK
@ PseudoVMIN_VV_MF4_MASK
Definition riscv/opcodes.hpp:6865
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M1
@ PseudoVRGATHEREI16_VV_M1_E16_M1
Definition riscv/opcodes.hpp:8274
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2_MASK_TIED
@ PseudoVWSUBU_WV_M2_MASK_TIED
Definition riscv/opcodes.hpp:11749
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF2
@ PseudoVMAX_VX_MF2
Definition riscv/opcodes.hpp:6564
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E16
@ PseudoVFCVT_F_X_V_M4_E16
Definition riscv/opcodes.hpp:1713
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M1_MASK
@ PseudoVSUXEI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10616
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF2_E16
@ PseudoVFWMUL_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3809
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_MF2_MASK
@ PseudoVSOXSEG6EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9620
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF4_MASK
@ PseudoVLUXEI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:5609
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF2_MASK
@ PseudoVSUXSEG7EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11210
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E32
@ PseudoVFSQRT_V_M1_E32
Definition riscv/opcodes.hpp:3363
LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M8
@ PseudoVSHA2MS_VV_M8
Definition riscv/opcodes.hpp:8792
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E32
@ PseudoVFADD_VV_M1_E32
Definition riscv/opcodes.hpp:1631
LIEF::assembly::riscv::OPCODE::VLE32_V
@ VLE32_V
Definition riscv/opcodes.hpp:13326
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E64_MASK
@ PseudoVFCVT_RM_F_XU_V_M2_E64_MASK
Definition riscv/opcodes.hpp:1742
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF8
@ PseudoVWSLL_VX_MF8
Definition riscv/opcodes.hpp:11717
LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_MF2
@ PseudoVMNAND_MM_MF2
Definition riscv/opcodes.hpp:6886
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E16_MASK
@ PseudoVFWSUB_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3986
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF4_MASK
@ PseudoVLUXSEG5EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:6119
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_MF2
@ PseudoVLOXSEG5EI32_V_M2_MF2
Definition riscv/opcodes.hpp:4718
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF4
@ PseudoVSOXSEG7EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:9707
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E64_MASK
@ PseudoVFMADD_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:2032
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M2_MASK
@ PseudoVSSSEG2E16_V_M2_MASK
Definition riscv/opcodes.hpp:10250
LIEF::assembly::riscv::OPCODE::FADD_H_INX
@ FADD_H_INX
Definition riscv/opcodes.hpp:12562
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M1
@ PseudoVLSEG3E64FF_V_M1
Definition riscv/opcodes.hpp:5154
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M2
@ PseudoVFWCVT_RM_X_F_V_M2
Definition riscv/opcodes.hpp:3649
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E8_MASK
@ PseudoVREDAND_VS_MF2_E8_MASK
Definition riscv/opcodes.hpp:7737
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E32_MASK
@ PseudoVFNMACC_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:2648
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E64
@ PseudoVFCVT_F_XU_V_M4_E64
Definition riscv/opcodes.hpp:1687
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_M1_MASK
@ PseudoVLOXSEG7EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4857
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M1_MASK
@ PseudoVSUXSEG4EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10942
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E32_MASK
@ PseudoVFMADD_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:2048
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF4_MASK
@ PseudoVXOR_VX_MF4_MASK
Definition riscv/opcodes.hpp:11878
LIEF::assembly::riscv::OPCODE::VFMV_F_S
@ VFMV_F_S
Definition riscv/opcodes.hpp:13231
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E8_MASK
@ PseudoVREDMAXU_VS_M2_E8_MASK
Definition riscv/opcodes.hpp:7759
LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32
@ AMOCAS_D_RV32
Definition riscv/opcodes.hpp:11983
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M2_MASK
@ PseudoVROR_VV_M2_MASK
Definition riscv/opcodes.hpp:8551
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF4_E16_MASK
@ PseudoVFNMACC_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:2674
LIEF::assembly::riscv::OPCODE::FLH
@ FLH
Definition riscv/opcodes.hpp:12671
LIEF::assembly::riscv::OPCODE::VMXNOR_MM
@ VMXNOR_MM
Definition riscv/opcodes.hpp:13565
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M1
@ PseudoVLOXSEG2EI32_V_M2_M1
Definition riscv/opcodes.hpp:4378
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M4_MASK
@ PseudoVROL_VX_M4_MASK
Definition riscv/opcodes.hpp:8525
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E8
@ PseudoVDIV_VV_M2_E8
Definition riscv/opcodes.hpp:1525
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_MF4
@ PseudoVRELOAD6_MF4
Definition riscv/opcodes.hpp:8074
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF2_MASK
@ PseudoVSE8_V_MF2_MASK
Definition riscv/opcodes.hpp:8741
LIEF::assembly::riscv::OPCODE::G_DEBUGTRAP
@ G_DEBUGTRAP
Definition riscv/opcodes.hpp:298
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF2_E16
@ PseudoVFSUB_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3399
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E32_MASK
@ PseudoVREMU_VX_M1_E32_MASK
Definition riscv/opcodes.hpp:8131
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M1_E16
@ PseudoVFMSAC_VFPR16_M1_E16
Definition riscv/opcodes.hpp:2192
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E8_MASK
@ PseudoVREDOR_VS_M8_E8_MASK
Definition riscv/opcodes.hpp:7951
LIEF::assembly::riscv::OPCODE::CPOP
@ CPOP
Definition riscv/opcodes.hpp:12151
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M8_MASK
@ PseudoVMINU_VX_M8_MASK
Definition riscv/opcodes.hpp:6847
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF4
@ PseudoVMADD_VX_MF4
Definition riscv/opcodes.hpp:6496
LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SCI_H
@ CV_DOTUSP_SCI_H
Definition riscv/opcodes.hpp:12296
LIEF::assembly::riscv::OPCODE::VFNMADD_VV
@ VFNMADD_VV
Definition riscv/opcodes.hpp:13246
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF8
@ PseudoVNSRA_WI_MF8
Definition riscv/opcodes.hpp:7564
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_M1
@ PseudoVSUXSEG8EI16_V_MF4_M1
Definition riscv/opcodes.hpp:11267
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M1_MASK
@ PseudoVSSSEG2E32_V_M1_MASK
Definition riscv/opcodes.hpp:10258
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E64
@ PseudoVCOMPRESS_VM_M4_E64
Definition riscv/opcodes.hpp:1024
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M2_MASK
@ PseudoVRSUB_VI_M2_MASK
Definition riscv/opcodes.hpp:8579
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_M1_MASK
@ PseudoVLUXSEG5EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6103
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M4_MASK
@ PseudoVSEXT_VF2_M4_MASK
Definition riscv/opcodes.hpp:8754
LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64
@ AMOCAS_D_RV64
Definition riscv/opcodes.hpp:11987
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M2
@ PseudoVLSEG2E32FF_V_M2
Definition riscv/opcodes.hpp:5076
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M4
@ PseudoVXOR_VV_M4
Definition riscv/opcodes.hpp:11857
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF4
@ PseudoVSUXSEG4EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:11005
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M2_MASK
@ PseudoVCPOP_V_M2_MASK
Definition riscv/opcodes.hpp:1053
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_MF2
@ PseudoVLUXSEG7EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:6306
LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M2
@ PseudoVSM3ME_VV_M2
Definition riscv/opcodes.hpp:8926
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF8
@ PseudoVWMACCSU_VX_MF8
Definition riscv/opcodes.hpp:11477
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M2_MASK
@ PseudoVNCLIPU_WI_M2_MASK
Definition riscv/opcodes.hpp:7429
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF2_MASK
@ PseudoVSUXSEG4EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10938
LIEF::assembly::riscv::OPCODE::VLOXEI16_V
@ VLOXEI16_V
Definition riscv/opcodes.hpp:13332
LIEF::assembly::riscv::OPCODE::VSSSEG8E8_V
@ VSSSEG8E8_V
Definition riscv/opcodes.hpp:13763
LIEF::assembly::riscv::OPCODE::FLTQ_S
@ FLTQ_S
Definition riscv/opcodes.hpp:12677
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M4_MASK
@ PseudoVFCVT_XU_F_V_M4_MASK
Definition riscv/opcodes.hpp:1844
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M2
@ PseudoVLUXEI32_V_M2_M2
Definition riscv/opcodes.hpp:5622
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M4_MASK
@ PseudoVLSEG2E8_V_M4_MASK
Definition riscv/opcodes.hpp:5119
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF2
@ PseudoVSSSEG7E8_V_MF2
Definition riscv/opcodes.hpp:10393
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M2_MASK
@ PseudoVSUXSEG3EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10840
LIEF::assembly::riscv::OPCODE::FSUB_S_INX
@ FSUB_S_INX
Definition riscv/opcodes.hpp:12792
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B1_MASK
@ PseudoVMSBF_M_B1_MASK
Definition riscv/opcodes.hpp:6941
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF4
@ PseudoVLUXEI16_V_MF4_MF4
Definition riscv/opcodes.hpp:5608
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_MF2_MASK
@ PseudoVSSSEG3E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10296
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF4_E16
@ PseudoVFWMUL_VV_MF4_E16
Definition riscv/opcodes.hpp:3837
LIEF::assembly::riscv::OPCODE::VQMACCSU_2x8x2
@ VQMACCSU_2x8x2
Definition riscv/opcodes.hpp:13586
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M2_E16_MASK
@ PseudoVFWNMACC_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3842
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M8
@ PseudoVLE8FF_V_M8
Definition riscv/opcodes.hpp:4149
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M2
@ PseudoVSADD_VI_M2
Definition riscv/opcodes.hpp:8648
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF4_E16_MASK
@ PseudoVFWSUB_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3964
LIEF::assembly::riscv::OPCODE::VSLIDEDOWN_VX
@ VSLIDEDOWN_VX
Definition riscv/opcodes.hpp:13646
LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_M1
@ PseudoVMNOR_MM_M1
Definition riscv/opcodes.hpp:6889
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_MF8
@ PseudoVC_V_VV_SE_MF8
Definition riscv/opcodes.hpp:1341
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M2_MASK
@ PseudoVWMUL_VX_M2_MASK
Definition riscv/opcodes.hpp:11602
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_M1_MASK
@ PseudoVLOXSEG7EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4871
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_MF2
@ PseudoVSUXSEG4EI32_V_M2_MF2
Definition riscv/opcodes.hpp:10945
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF4
@ PseudoVSRA_VV_MF4
Definition riscv/opcodes.hpp:9887
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E32_MASK
@ PseudoVWREDSUM_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:11650
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF2
@ PseudoVLUXSEG6EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:6236
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF4
@ PseudoVSOXSEG8EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:9787
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_M1_MASK
@ PseudoVLSSEG5E16_V_M1_MASK
Definition riscv/opcodes.hpp:5491
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M1_MASK
@ PseudoVLOXSEG2EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4447
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_MF2_MASK
@ PseudoVSUXSEG4EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:10982
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF4_MASK
@ PseudoVROR_VI_MF4_MASK
Definition riscv/opcodes.hpp:8545
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF2_MASK
@ PseudoVMSNE_VI_MF2_MASK
Definition riscv/opcodes.hpp:7230
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_MF2_MASK
@ PseudoVLUXSEG6EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:6219
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M2_MASK
@ PseudoVWADD_WX_M2_MASK
Definition riscv/opcodes.hpp:11446
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_MF4
@ PseudoVC_V_VVV_MF4
Definition riscv/opcodes.hpp:1307
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VV_SE_M2
@ PseudoVC_FPR32VV_SE_M2
Definition riscv/opcodes.hpp:1097
LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_MF2
@ PseudoVAESKF1_VI_MF2
Definition riscv/opcodes.hpp:760
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E32
@ PseudoVDIV_VX_M1_E32
Definition riscv/opcodes.hpp:1557
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M4
@ PseudoVSOXSEG2EI32_V_M2_M4
Definition riscv/opcodes.hpp:9203
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M2_MASK
@ PseudoVSOXSEG2EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9244
LIEF::assembly::riscv::OPCODE::CV_CMPNE_SC_B
@ CV_CMPNE_SC_B
Definition riscv/opcodes.hpp:12269
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF2
@ PseudoVFCVT_X_F_V_MF2
Definition riscv/opcodes.hpp:1859
LIEF::assembly::riscv::OPCODE::CV_MIN_SCI_B
@ CV_MIN_SCI_B
Definition riscv/opcodes.hpp:12366
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF2
@ PseudoVLOXSEG8EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:5004
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E32_MASK
@ PseudoVFREDMAX_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:2944
LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_MF8
@ PseudoVC_XVV_SE_MF8
Definition riscv/opcodes.hpp:1402
LIEF::assembly::riscv::OPCODE::VFSQRT_V
@ VFSQRT_V
Definition riscv/opcodes.hpp:13269
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_MF8
@ PseudoVAESEM_VS_M1_MF8
Definition riscv/opcodes.hpp:730
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF4
@ PseudoVSSUB_VV_MF4
Definition riscv/opcodes.hpp:10457
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E64_MASK
@ PseudoVDIV_VX_M2_E64_MASK
Definition riscv/opcodes.hpp:1568
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF8_MASK
@ PseudoVFNCVT_RM_XU_F_W_MF8_MASK
Definition riscv/opcodes.hpp:2536
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF8_MASK
@ PseudoVWMACCU_VX_MF8_MASK
Definition riscv/opcodes.hpp:11514
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M8
@ PseudoVMADC_VV_M8
Definition riscv/opcodes.hpp:6454
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF2_MASK
@ PseudoVLOXSEG8EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4939
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF2
@ PseudoVSOXEI16_V_MF4_MF2
Definition riscv/opcodes.hpp:9035
LIEF::assembly::riscv::OPCODE::C_SLLI_HINT
@ C_SLLI_HINT
Definition riscv/opcodes.hpp:12535
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E16_MASK
@ PseudoVFMIN_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:2187
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_M2_MASK
@ PseudoVSUXSEG4EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:11002
LIEF::assembly::riscv::OPCODE::VLOXSEG4EI8_V
@ VLOXSEG4EI8_V
Definition riscv/opcodes.hpp:13347
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M8_MASK
@ PseudoVSEXT_VF2_M8_MASK
Definition riscv/opcodes.hpp:8756
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF4
@ PseudoVSUXSEG2EI64_V_M2_MF4
Definition riscv/opcodes.hpp:10743
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M1
@ PseudoVMIN_VX_M1
Definition riscv/opcodes.hpp:6868
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M2_MASK
@ PseudoVAND_VI_M2_MASK
Definition riscv/opcodes.hpp:821
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF4
@ PseudoVSOXSEG5EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:9581
LIEF::assembly::riscv::OPCODE::SW
@ SW
Definition riscv/opcodes.hpp:13017
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF2_MASK
@ PseudoVLOXSEG7EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4893
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E16_MASK
@ PseudoVFMSUB_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:2283
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M2_MASK
@ PseudoVSEXT_VF8_M2_MASK
Definition riscv/opcodes.hpp:8774
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_M1_M1_MASK
@ PseudoVLOXSEG5EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4751
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E64_MASK
@ PseudoVFMAX_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:2098
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M1
@ PseudoVSSEG2E8_V_M1
Definition riscv/opcodes.hpp:10015
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E64_MASK
@ PseudoVFMSUB_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:2305
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E64_MASK
@ PseudoVFMAX_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:2092
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M2_MASK
@ PseudoVLUXSEG2EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5833
LIEF::assembly::riscv::OPCODE::VT_MASKC
@ VT_MASKC
Definition riscv/opcodes.hpp:13802
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF4
@ PseudoVLSSEG5E8_V_MF4
Definition riscv/opcodes.hpp:5506
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF2_MASK
@ PseudoVSLL_VX_MF2_MASK
Definition riscv/opcodes.hpp:8915
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M8_E16
@ PseudoVFNMACC_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2621
LIEF::assembly::riscv::OPCODE::VFNCVT_ROD_F_F_W
@ VFNCVT_ROD_F_F_W
Definition riscv/opcodes.hpp:13238
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E32
@ PseudoVFREC7_V_M4_E32
Definition riscv/opcodes.hpp:2919
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M1
@ PseudoVMFNE_VV_M1
Definition riscv/opcodes.hpp:6814
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M1_MASK
@ PseudoVLUXSEG2EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:5779
LIEF::assembly::riscv::OPCODE::VLSEG4E64FF_V
@ VLSEG4E64FF_V
Definition riscv/opcodes.hpp:13388
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_M2
@ PseudoVLSEG3E8FF_V_M2
Definition riscv/opcodes.hpp:5164
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_M8_MASK
@ PseudoVAND_VI_M8_MASK
Definition riscv/opcodes.hpp:825
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF8_MASK
@ PseudoVSOXSEG7EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:9718
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF2_MASK
@ PseudoVMSLT_VX_MF2_MASK
Definition riscv/opcodes.hpp:7216
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M4_MASK
@ PseudoVCLMUL_VX_M4_MASK
Definition riscv/opcodes.hpp:991
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M4_MASK
@ PseudoVMSEQ_VX_M4_MASK
Definition riscv/opcodes.hpp:6985
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M4_E16_MASK
@ PseudoVFNCVT_RM_F_X_W_M4_E16_MASK
Definition riscv/opcodes.hpp:2516
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M1
@ PseudoTHVdotVMAQAU_VX_M1
Definition riscv/opcodes.hpp:490
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M1
@ PseudoVLUXEI16_V_MF2_M1
Definition riscv/opcodes.hpp:5596
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M1_E64_MASK
@ PseudoVFMSAC_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2215
LIEF::assembly::riscv::OPCODE::PseudoLongBGEU
@ PseudoLongBGEU
Definition riscv/opcodes.hpp:403
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF8
@ PseudoVASUBU_VX_MF8
Definition riscv/opcodes.hpp:886
LIEF::assembly::riscv::OPCODE::VSUXSEG7EI64_V
@ VSUXSEG7EI64_V
Definition riscv/opcodes.hpp:13796
LIEF::assembly::riscv::OPCODE::C_ADDI4SPN
@ C_ADDI4SPN
Definition riscv/opcodes.hpp:12478
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M4
@ PseudoVWMULSU_VV_M4
Definition riscv/opcodes.hpp:11543
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E32
@ PseudoVFSGNJ_VV_MF2_E32
Definition riscv/opcodes.hpp:3297
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M1_MASK
@ PseudoVSLL_VX_M1_MASK
Definition riscv/opcodes.hpp:8907
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF4
@ PseudoVRGATHEREI16_VV_M1_E8_MF4
Definition riscv/opcodes.hpp:8304
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M2_MASK
@ PseudoVLSEG3E16FF_V_M2_MASK
Definition riscv/opcodes.hpp:5129
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E16
@ PseudoVREDMAX_VS_M4_E16
Definition riscv/opcodes.hpp:7804
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M4_MASK
@ PseudoVWSUBU_VV_M4_MASK
Definition riscv/opcodes.hpp:11724
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_M8
@ PseudoVC_V_FPR64VV_M8
Definition riscv/opcodes.hpp:1235
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF2
@ PseudoVLUXSEG3EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:5966
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_M4
@ PseudoVAESDM_VS_M8_M4
Definition riscv/opcodes.hpp:686
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF4
@ PseudoVSMUL_VX_MF4
Definition riscv/opcodes.hpp:8988
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M1_MASK
@ PseudoVMFEQ_VFPR32_M1_MASK
Definition riscv/opcodes.hpp:6611
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E8
@ PseudoVCOMPRESS_VM_M8_E8
Definition riscv/opcodes.hpp:1029
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M1_MASK
@ PseudoVMFNE_VV_M1_MASK
Definition riscv/opcodes.hpp:6815
LIEF::assembly::riscv::OPCODE::JAL
@ JAL
Definition riscv/opcodes.hpp:12830
LIEF::assembly::riscv::OPCODE::CV_SRL_SC_B
@ CV_SRL_SC_B
Definition riscv/opcodes.hpp:12441
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E16_MASK
@ PseudoVREMU_VX_MF2_E16_MASK
Definition riscv/opcodes.hpp:8161
LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M2_MASK
@ PseudoVLE32_V_M2_MASK
Definition riscv/opcodes.hpp:4120
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_M1_MASK
@ PseudoVLSEG7E32_V_M1_MASK
Definition riscv/opcodes.hpp:5335
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_MF8
@ PseudoVAESDM_VS_M4_MF8
Definition riscv/opcodes.hpp:683
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M8
@ PseudoVMADC_VI_M8
Definition riscv/opcodes.hpp:6440
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF4
@ PseudoVLSSEG5E16_V_MF4
Definition riscv/opcodes.hpp:5494
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_SE_M2
@ PseudoVC_V_FPR32VV_SE_M2
Definition riscv/opcodes.hpp:1208
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF2_MASK
@ PseudoVMFNE_VV_MF2_MASK
Definition riscv/opcodes.hpp:6823
LIEF::assembly::riscv::OPCODE::C_MOP13
@ C_MOP13
Definition riscv/opcodes.hpp:12514
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF8_MASK
@ PseudoVSSRA_VX_MF8_MASK
Definition riscv/opcodes.hpp:10204
LIEF::assembly::riscv::OPCODE::C_FSW
@ C_FSW
Definition riscv/opcodes.hpp:12495
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF4_MASK
@ PseudoVSSEG6E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10108
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M2
@ PseudoVSOXSEG4EI16_V_M2_M2
Definition riscv/opcodes.hpp:9409
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E32
@ PseudoVFMIN_VV_M2_E32
Definition riscv/opcodes.hpp:2170
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M1_MASK
@ PseudoVMSLEU_VI_M1_MASK
Definition riscv/opcodes.hpp:7080
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M1_MASK
@ PseudoVWADDU_VX_M1_MASK
Definition riscv/opcodes.hpp:11348
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E32_MASK
@ PseudoVFNCVT_F_X_W_M4_E32_MASK
Definition riscv/opcodes.hpp:2482
LIEF::assembly::riscv::OPCODE::FCVT_S_LU_INX
@ FCVT_S_LU_INX
Definition riscv/opcodes.hpp:12623
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E8_MASK
@ PseudoVREDXOR_VS_MF4_E8_MASK
Definition riscv/opcodes.hpp:8049
LIEF::assembly::riscv::OPCODE::VRSUB_VX
@ VRSUB_VX
Definition riscv/opcodes.hpp:13617
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_MF2
@ PseudoVSOXSEG7EI32_V_M2_MF2
Definition riscv/opcodes.hpp:9699
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E8_MASK
@ PseudoVDIVU_VX_M2_E8_MASK
Definition riscv/opcodes.hpp:1482
LIEF::assembly::riscv::OPCODE::FCVT_D_H_INX
@ FCVT_D_H_INX
Definition riscv/opcodes.hpp:12576
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M4_MASK
@ PseudoVSRA_VX_M4_MASK
Definition riscv/opcodes.hpp:9896
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF4_MASK
@ PseudoVSOXEI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9038
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E16_MASK
@ PseudoVWREDSUMU_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:11624
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E32_MASK
@ PseudoVFWCVT_F_XU_V_M1_E32_MASK
Definition riscv/opcodes.hpp:3580
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E8
@ PseudoVREM_VV_MF4_E8
Definition riscv/opcodes.hpp:8212
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF4
@ PseudoVIOTA_M_MF4
Definition riscv/opcodes.hpp:4079
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M2
@ PseudoVLOXSEG3EI8_V_MF2_M2
Definition riscv/opcodes.hpp:4560
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF8_MASK
@ PseudoVSRL_VI_MF8_MASK
Definition riscv/opcodes.hpp:9918
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M1
@ PseudoVSSRA_VV_M1
Definition riscv/opcodes.hpp:10177
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF2
@ PseudoVOR_VV_MF2
Definition riscv/opcodes.hpp:7648
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M1_MASK
@ PseudoVSRL_VV_M1_MASK
Definition riscv/opcodes.hpp:9920
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_MF2_MASK
@ PseudoVSEXT_VF4_MF2_MASK
Definition riscv/opcodes.hpp:8770
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E64_MASK
@ PseudoVFADD_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:1652
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_MF4
@ PseudoVMERGE_VIM_MF4
Definition riscv/opcodes.hpp:6582
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M2
@ PseudoVFSLIDE1UP_VFPR16_M2
Definition riscv/opcodes.hpp:3333
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M2
@ PseudoVLOXSEG4EI16_V_M2_M2
Definition riscv/opcodes.hpp:4588
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M8
@ PseudoVXOR_VI_M8
Definition riscv/opcodes.hpp:11845
LIEF::assembly::riscv::OPCODE::VMFGE_VF
@ VMFGE_VF
Definition riscv/opcodes.hpp:13505
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_SUB
@ G_ATOMICRMW_SUB
Definition riscv/opcodes.hpp:125
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M8_M2_MASK
@ PseudoVSUXSEG3EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:10842
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M2_MASK
@ PseudoVSSSEG2E8_V_M2_MASK
Definition riscv/opcodes.hpp:10274
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_MF2
@ PseudoVAESDM_VS_M4_MF2
Definition riscv/opcodes.hpp:681
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF8_MASK
@ PseudoVWSUBU_VV_MF8_MASK
Definition riscv/opcodes.hpp:11730
LIEF::assembly::riscv::OPCODE::VFNMSAC_VV
@ VFNMSAC_VV
Definition riscv/opcodes.hpp:13248
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M4_MASK
@ PseudoVSSE8_V_M4_MASK
Definition riscv/opcodes.hpp:9982
LIEF::assembly::riscv::OPCODE::VFMACC_VF
@ VFMACC_VF
Definition riscv/opcodes.hpp:13216
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E32_MASK
@ PseudoVFWREDUSUM_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:3936
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_M1
@ PseudoVSOXSEG5EI8_V_MF8_M1
Definition riscv/opcodes.hpp:9583
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M1
@ PseudoVLOXSEG4EI16_V_MF2_M1
Definition riscv/opcodes.hpp:4592
LIEF::assembly::riscv::OPCODE::BINVI
@ BINVI
Definition riscv/opcodes.hpp:12127
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E64
@ PseudoVFMADD_VV_M2_E64
Definition riscv/opcodes.hpp:2037
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF8
@ PseudoVSLL_VI_MF8
Definition riscv/opcodes.hpp:8890
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M1
@ PseudoVSSEG2E64_V_M1
Definition riscv/opcodes.hpp:10009
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_M1_MASK
@ PseudoVSSSEG8E8_V_M1_MASK
Definition riscv/opcodes.hpp:10412
LIEF::assembly::riscv::OPCODE::MOPR30
@ MOPR30
Definition riscv/opcodes.hpp:12884
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E64_MASK
@ PseudoVFADD_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:1634
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M1_E32
@ PseudoVFRSUB_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3103
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E16_MASK
@ PseudoVFNMADD_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:2706
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M1_MASK
@ PseudoVSUXSEG3EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10796
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E16_MASK
@ PseudoVRGATHER_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:8465
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B4_MASK
@ PseudoVMSIF_M_B4_MASK
Definition riscv/opcodes.hpp:7074
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M4
@ PseudoVMFNE_VFPR64_M4
Definition riscv/opcodes.hpp:6810
LIEF::assembly::riscv::OPCODE::SwapFRMImm
@ SwapFRMImm
Definition riscv/opcodes.hpp:11926
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF2
@ PseudoVWMACC_VX_MF2
Definition riscv/opcodes.hpp:11533
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M2_MASK
@ PseudoVSUXEI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10556
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M8
@ PseudoVSOXEI8_V_M1_M8
Definition riscv/opcodes.hpp:9117
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M2_MASK
@ PseudoVSUXEI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10602
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_M4
@ PseudoVC_FPR16VV_SE_M4
Definition riscv/opcodes.hpp:1080
LIEF::assembly::riscv::OPCODE::TH_L2CACHE_IALL
@ TH_L2CACHE_IALL
Definition riscv/opcodes.hpp:13060
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF4
@ PseudoVSOXSEG2EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:9181
LIEF::assembly::riscv::OPCODE::VSOXSEG2EI64_V
@ VSOXSEG2EI64_V
Definition riscv/opcodes.hpp:13666
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M2
@ PseudoVFNCVT_X_F_W_M2
Definition riscv/opcodes.hpp:2605
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M4_M2
@ PseudoVSOXSEG3EI16_V_M4_M2
Definition riscv/opcodes.hpp:9301
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF4
@ PseudoVREV8_V_MF4
Definition riscv/opcodes.hpp:8270
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M4_E32
@ PseudoVFWMSAC_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3781
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF8
@ PseudoVNMSAC_VX_MF8
Definition riscv/opcodes.hpp:7524
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF8_MASK
@ PseudoVWSUB_VX_MF8_MASK
Definition riscv/opcodes.hpp:11802
LIEF::assembly::riscv::OPCODE::FLT_S_INX
@ FLT_S_INX
Definition riscv/opcodes.hpp:12684
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_M1
@ PseudoVSSEG5E16_V_M1
Definition riscv/opcodes.hpp:10083
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M2_MASK
@ PseudoVASUBU_VV_M2_MASK
Definition riscv/opcodes.hpp:863
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF8
@ PseudoVSUXSEG7EI64_V_M1_MF8
Definition riscv/opcodes.hpp:11221
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M1_E64_MASK
@ PseudoVFSGNJ_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:3264
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E32_MASK
@ PseudoVFREC7_V_M8_E32_MASK
Definition riscv/opcodes.hpp:2926
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_M1_MASK
@ PseudoVLOXSEG5EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4723
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E16
@ PseudoVFMADD_VV_M2_E16
Definition riscv/opcodes.hpp:2033
LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M8_MASK
@ PseudoVLE64FF_V_M8_MASK
Definition riscv/opcodes.hpp:4134
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E8
@ PseudoVDIV_VV_MF4_E8
Definition riscv/opcodes.hpp:1551
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_MF2
@ PseudoVLOXSEG4EI32_V_M2_MF2
Definition riscv/opcodes.hpp:4620
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M2_MASK
@ PseudoVMFEQ_VV_M2_MASK
Definition riscv/opcodes.hpp:6631
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M2_M1
@ PseudoVSOXSEG7EI16_V_M2_M1
Definition riscv/opcodes.hpp:9675
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF8
@ PseudoVSOXEI16_V_MF4_MF8
Definition riscv/opcodes.hpp:9039
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M2_E16_MASK
@ PseudoVFNMADD_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2678
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E32_MASK
@ PseudoVREDMIN_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:7895
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E16
@ PseudoVFADD_VV_M4_E16
Definition riscv/opcodes.hpp:1641
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M1
@ PseudoVLUXSEG2EI16_V_MF2_M1
Definition riscv/opcodes.hpp:5746
LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SC_H
@ CV_SDOTUSP_SC_H
Definition riscv/opcodes.hpp:12410
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M4_MASK
@ PseudoVMFEQ_VFPR32_M4_MASK
Definition riscv/opcodes.hpp:6615
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_M1_M1
@ PseudoVSOXSEG5EI8_V_M1_M1
Definition riscv/opcodes.hpp:9571
LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SC_B
@ CV_CMPGTU_SC_B
Definition riscv/opcodes.hpp:12233
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M8
@ PseudoVLUXEI8_V_M4_M8
Definition riscv/opcodes.hpp:5698
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M8
@ PseudoVMIN_VV_M8
Definition riscv/opcodes.hpp:6860
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M2_MASK
@ PseudoVLOXSEG2EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4389
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF4_MASK
@ PseudoVFNRCLIP_XU_F_QF_MF4_MASK
Definition riscv/opcodes.hpp:2862
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M1
@ PseudoVLOXEI16_V_MF2_M1
Definition riscv/opcodes.hpp:4204
LIEF::assembly::riscv::OPCODE::VLSEG5E8_V
@ VLSEG5E8_V
Definition riscv/opcodes.hpp:13399
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M1_MASK
@ PseudoVLSEG3E8_V_M1_MASK
Definition riscv/opcodes.hpp:5173
LIEF::assembly::riscv::OPCODE::MOPR5
@ MOPR5
Definition riscv/opcodes.hpp:12887
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_M1
@ PseudoVLSEG7E8FF_V_M1
Definition riscv/opcodes.hpp:5342
LIEF::assembly::riscv::OPCODE::VSEXT_VF8
@ VSEXT_VF8
Definition riscv/opcodes.hpp:13639
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M1
@ PseudoVWMACCUS_VX_M1
Definition riscv/opcodes.hpp:11479
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M1_MASK
@ PseudoVLOXSEG3EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:4549
LIEF::assembly::riscv::OPCODE::LW_AQ_RL
@ LW_AQ_RL
Definition riscv/opcodes.hpp:12855
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M2_MASK
@ PseudoVMFLE_VFPR16_M2_MASK
Definition riscv/opcodes.hpp:6703
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_MF2
@ PseudoVLSEG8E32FF_V_MF2
Definition riscv/opcodes.hpp:5372
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E32
@ PseudoVFWSUB_VV_MF2_E32
Definition riscv/opcodes.hpp:3987
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK
@ PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK
Definition riscv/opcodes.hpp:2552
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF2_MASK
@ PseudoVLOXEI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:4329
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF4_MASK
@ PseudoVNCLIP_WI_MF4_MASK
Definition riscv/opcodes.hpp:7471
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M1_E16
@ PseudoVFRDIV_VFPR16_M1_E16
Definition riscv/opcodes.hpp:2875
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M1
@ PseudoVFWCVT_RTZ_XU_F_V_M1
Definition riscv/opcodes.hpp:3657
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_M1
@ PseudoVLOXSEG7EI8_V_MF8_M1
Definition riscv/opcodes.hpp:4922
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M2
@ PseudoVLSEG3E16_V_M2
Definition riscv/opcodes.hpp:5136
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E32
@ PseudoVFNCVTBF16_F_F_W_MF2_E32
Definition riscv/opcodes.hpp:2431
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M4
@ PseudoVRGATHEREI16_VV_M4_E8_M4
Definition riscv/opcodes.hpp:8366
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E64
@ PseudoVFCVT_F_X_V_M2_E64
Definition riscv/opcodes.hpp:1711
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF2_MASK
@ PseudoVSUXSEG8EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11264
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M4_E32
@ PseudoVFNMSUB_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2811
LIEF::assembly::riscv::OPCODE::C_SRLI
@ C_SRLI
Definition riscv/opcodes.hpp:12538
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_MF2_MASK
@ PseudoVLOXSEG8EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4995
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M2_MASK
@ PseudoVSADD_VI_M2_MASK
Definition riscv/opcodes.hpp:8649
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E16
@ PseudoVFNMADD_VV_M4_E16
Definition riscv/opcodes.hpp:2717
LIEF::assembly::riscv::OPCODE::VSSE32_V
@ VSSE32_V
Definition riscv/opcodes.hpp:13699
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF8_E8
@ PseudoVRGATHER_VV_MF8_E8
Definition riscv/opcodes.hpp:8490
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M8_MASK
@ PseudoVROL_VX_M8_MASK
Definition riscv/opcodes.hpp:8527
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_MF2_MASK
@ PseudoVLOXSEG5EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4755
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF8_MASK
@ PseudoVLOXSEG6EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:4789
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M2
@ PseudoVSOXSEG3EI8_V_MF4_M2
Definition riscv/opcodes.hpp:9387
LIEF::assembly::riscv::OPCODE::TH_SFENCE_VMAS
@ TH_SFENCE_VMAS
Definition riscv/opcodes.hpp:13107
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E16
@ PseudoVWREDSUMU_VS_MF2_E16
Definition riscv/opcodes.hpp:11635
LIEF::assembly::riscv::OPCODE::PseudoMovImm
@ PseudoMovImm
Definition riscv/opcodes.hpp:417
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_MF2
@ PseudoVC_V_IVW_MF2
Definition riscv/opcodes.hpp:1265
LIEF::assembly::riscv::OPCODE::TH_MULA
@ TH_MULA
Definition riscv/opcodes.hpp:13092
LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_MF2
@ PseudoVSM3C_VI_MF2
Definition riscv/opcodes.hpp:8924
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_M1
@ PseudoVAESEF_VS_M4_M1
Definition riscv/opcodes.hpp:707
LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SC_B
@ CV_CMPLTU_SC_B
Definition riscv/opcodes.hpp:12257
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M1_MASK
@ PseudoVSUXSEG3EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:10874
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M2_MASK
@ PseudoVMSLE_VI_M2_MASK
Definition riscv/opcodes.hpp:7124
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF8
@ PseudoVSSUB_VV_MF8
Definition riscv/opcodes.hpp:10459
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M1_MASK
@ PseudoVWADD_WX_M1_MASK
Definition riscv/opcodes.hpp:11444
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E8_MASK
@ PseudoVREMU_VX_M4_E8_MASK
Definition riscv/opcodes.hpp:8151
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_MF4
@ PseudoVAESDM_VS_M2_MF4
Definition riscv/opcodes.hpp:676
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_MF2
@ PseudoVSUXSEG6EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:11159
LIEF::assembly::riscv::OPCODE::HINVAL_VVMA
@ HINVAL_VVMA
Definition riscv/opcodes.hpp:12797
LIEF::assembly::riscv::OPCODE::VS2R_V
@ VS2R_V
Definition riscv/opcodes.hpp:13619
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF8_MASK
@ PseudoVLOXSEG8EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:4949
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_M1_MASK
@ PseudoVLSEG5E8_V_M1_MASK
Definition riscv/opcodes.hpp:5271
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_MF8
@ PseudoVC_V_I_SE_MF8
Definition riscv/opcodes.hpp:1301
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_MF2_MASK
@ PseudoVNSRA_WX_MF2_MASK
Definition riscv/opcodes.hpp:7585
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_M2
@ PseudoVC_V_FPR16V_SE_M2
Definition riscv/opcodes.hpp:1197
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M1_MASK
@ PseudoVSRA_VV_M1_MASK
Definition riscv/opcodes.hpp:9878
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M2
@ PseudoVSSEG2E64_V_M2
Definition riscv/opcodes.hpp:10011
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M8
@ PseudoVBREV8_V_M8
Definition riscv/opcodes.hpp:922
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M2_E32_MASK
@ PseudoVFSGNJ_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3256
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M4
@ PseudoVNSRL_WI_M4
Definition riscv/opcodes.hpp:7594
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M4
@ PseudoVMFLT_VFPR16_M4
Definition riscv/opcodes.hpp:6746
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M2_MASK
@ PseudoVSSEG4E8_V_M2_MASK
Definition riscv/opcodes.hpp:10076
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E16
@ PseudoVFSQRT_V_M2_E16
Definition riscv/opcodes.hpp:3367
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M4_MASK
@ PseudoVLSEG2E32_V_M4_MASK
Definition riscv/opcodes.hpp:5087
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M2
@ PseudoVLUXSEG2EI16_V_M4_M2
Definition riscv/opcodes.hpp:5740
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF4_MASK
@ PseudoVLSEG5E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5249
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M2
@ PseudoVMSLEU_VV_M2
Definition riscv/opcodes.hpp:7095
LIEF::assembly::riscv::OPCODE::VLSEG6E16_V
@ VLSEG6E16_V
Definition riscv/opcodes.hpp:13401
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF2
@ PseudoVLSEG8E16FF_V_MF2
Definition riscv/opcodes.hpp:5360
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF4_MASK
@ PseudoVCLMULH_VX_MF4_MASK
Definition riscv/opcodes.hpp:969
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E32_MASK
@ PseudoVFSGNJN_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:3172
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF8
@ PseudoVMADD_VV_MF8
Definition riscv/opcodes.hpp:6484
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M2_MASK
@ PseudoVLSEG4E16FF_V_M2_MASK
Definition riscv/opcodes.hpp:5185
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR64M_M2
@ PseudoVFMERGE_VFPR64M_M2
Definition riscv/opcodes.hpp:2129
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M4_MASK
@ PseudoVWMULSU_VX_M4_MASK
Definition riscv/opcodes.hpp:11556
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_M1_M1_MASK
@ PseudoVLUXSEG5EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6143
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M1
@ PseudoVFMV_V_FPR16_M1
Definition riscv/opcodes.hpp:2402
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E8
@ PseudoVFWCVT_F_X_V_M4_E8
Definition riscv/opcodes.hpp:3623
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF8_MASK
@ PseudoVMSLT_VX_MF8_MASK
Definition riscv/opcodes.hpp:7220
LIEF::assembly::riscv::OPCODE::VLUXEI16_V
@ VLUXEI16_V
Definition riscv/opcodes.hpp:13452
LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M1_MASK
@ PseudoVSE64_V_M1_MASK
Definition riscv/opcodes.hpp:8725
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M4
@ PseudoVWMACCUS_VX_M4
Definition riscv/opcodes.hpp:11483
LIEF::assembly::riscv::OPCODE::CV_ABS
@ CV_ABS
Definition riscv/opcodes.hpp:12161
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E64
@ PseudoVREDSUM_VS_M4_E64
Definition riscv/opcodes.hpp:7984
LIEF::assembly::riscv::OPCODE::AMOMINU_W
@ AMOMINU_W
Definition riscv/opcodes.hpp:12047
LIEF::assembly::riscv::OPCODE::SB_RL
@ SB_RL
Definition riscv/opcodes.hpp:12938
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF4_E16
@ PseudoVFMADD_VV_MF4_E16
Definition riscv/opcodes.hpp:2055
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF4_MASK
@ PseudoVWADD_VX_MF4_MASK
Definition riscv/opcodes.hpp:11416
LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_M1
@ PseudoVC_VVV_SE_M1
Definition riscv/opcodes.hpp:1146
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M1_MASK
@ PseudoVLSSEG3E32_V_M1_MASK
Definition riscv/opcodes.hpp:5443
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF8_MASK
@ PseudoVSSRA_VV_MF8_MASK
Definition riscv/opcodes.hpp:10190
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E32
@ PseudoVFCVT_F_X_V_MF2_E32
Definition riscv/opcodes.hpp:1727
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF4
@ PseudoVANDN_VV_MF4
Definition riscv/opcodes.hpp:800
LIEF::assembly::riscv::OPCODE::VAESDF_VV
@ VAESDF_VV
Definition riscv/opcodes.hpp:13142
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M2_MASK
@ PseudoVMSGTU_VX_M2_MASK
Definition riscv/opcodes.hpp:7026
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF4_MASK
@ PseudoVLOXEI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4255
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_MF2
@ PseudoVLSEG2E16_V_MF2
Definition riscv/opcodes.hpp:5070
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M2_MASK
@ PseudoVSLIDEUP_VX_M2_MASK
Definition riscv/opcodes.hpp:8867
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M2_M1
@ PseudoVLUXSEG6EI32_V_M2_M1
Definition riscv/opcodes.hpp:6188
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M2_MASK
@ PseudoVWSUB_WX_M2_MASK
Definition riscv/opcodes.hpp:11830
LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M8
@ PseudoVLE32_V_M8
Definition riscv/opcodes.hpp:4123
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M8
@ PseudoVLUXEI16_V_M8_M8
Definition riscv/opcodes.hpp:5594
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M2_M2
@ PseudoVLUXSEG4EI16_V_M2_M2
Definition riscv/opcodes.hpp:5980
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF4_MASK
@ PseudoVSUXSEG8EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:11280
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF8_MASK
@ PseudoVFNCVT_X_F_W_MF8_MASK
Definition riscv/opcodes.hpp:2614
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF2
@ PseudoVSUXSEG7EI64_V_M1_MF2
Definition riscv/opcodes.hpp:11217
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E64
@ PseudoVREDAND_VS_M8_E64
Definition riscv/opcodes.hpp:7728
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_M1
@ PseudoVLOXSEG8EI32_V_M1_M1
Definition riscv/opcodes.hpp:4950
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M1_MF2
@ PseudoVSOXSEG5EI16_V_M1_MF2
Definition riscv/opcodes.hpp:9513
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_M1
@ PseudoVSOXSEG6EI32_V_MF2_M1
Definition riscv/opcodes.hpp:9623
LIEF::assembly::riscv::OPCODE::VSOXEI64_V
@ VSOXEI64_V
Definition riscv/opcodes.hpp:13662
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E8_MASK
@ PseudoVREDOR_VS_M2_E8_MASK
Definition riscv/opcodes.hpp:7935
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M4_MASK
@ PseudoVLUXSEG2EI16_V_M2_M4_MASK
Definition riscv/opcodes.hpp:5739
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF4
@ PseudoVLOXSEG6EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:4846
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M4_MASK
@ PseudoVOR_VI_M4_MASK
Definition riscv/opcodes.hpp:7631
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M1_E64_MASK
@ PseudoVFNMSUB_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2818
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF2_MASK
@ PseudoVMSLT_VV_MF2_MASK
Definition riscv/opcodes.hpp:7202
LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_MF2
@ PseudoVADC_VVM_MF2
Definition riscv/opcodes.hpp:588
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M4_E16_MASK
@ PseudoVFMIN_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2137
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_M2_MASK
@ PseudoVLOXSEG3EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4501
LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W
@ SSAMOSWAP_W
Definition riscv/opcodes.hpp:13008
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8
@ PseudoVWSUBU_WV_MF8
Definition riscv/opcodes.hpp:11763
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_UMIN
@ G_VECREDUCE_UMIN
Definition riscv/opcodes.hpp:316
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M8_MASK
@ PseudoVMSNE_VX_M8_MASK
Definition riscv/opcodes.hpp:7256
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF4_MASK
@ PseudoVLOXSEG6EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4787
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_MF2_MASK
@ PseudoVSOXEI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:9102
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M1_MASK
@ PseudoVSOXSEG4EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9496
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E16_MASK
@ PseudoVFWNMSAC_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3894
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E64
@ PseudoVREMU_VV_M4_E64
Definition riscv/opcodes.hpp:8104
LIEF::assembly::riscv::OPCODE::VSSUB_VV
@ VSSUB_VV
Definition riscv/opcodes.hpp:13766
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4_MASK_TIED
@ PseudoVWSUBU_WV_MF4_MASK_TIED
Definition riscv/opcodes.hpp:11761
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_MF2_MASK
@ PseudoVSSEG2E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10008
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF4
@ PseudoVLOXSEG3EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:4522
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E64_V_M1
@ PseudoVSSSEG5E64_V_M1
Definition riscv/opcodes.hpp:10349
LIEF::assembly::riscv::OPCODE::PHI
@ PHI
Definition riscv/opcodes.hpp:24
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M2_MASK
@ PseudoVLUXSEG2EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:5729
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M4_MASK
@ PseudoVNCLIP_WX_M4_MASK
Definition riscv/opcodes.hpp:7491
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF4_MASK
@ PseudoVROR_VV_MF4_MASK
Definition riscv/opcodes.hpp:8559
LIEF::assembly::riscv::OPCODE::PseudoVSPILL6_M1
@ PseudoVSPILL6_M1
Definition riscv/opcodes.hpp:9851
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_M4
@ PseudoVFMV_S_FPR16_M4
Definition riscv/opcodes.hpp:2389
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E8
@ PseudoVWREDSUM_VS_M8_E8
Definition riscv/opcodes.hpp:11669
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M8
@ PseudoVSSRA_VX_M8
Definition riscv/opcodes.hpp:10197
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M4
@ PseudoVZEXT_VF8_M4
Definition riscv/opcodes.hpp:11907
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M1
@ PseudoVMINU_VX_M1
Definition riscv/opcodes.hpp:6840
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_MF4
@ PseudoVLUXSEG3EI32_V_M1_MF4
Definition riscv/opcodes.hpp:5896
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M1_E16
@ PseudoVFWADD_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3451
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF4_MASK
@ PseudoVLSEG4E16FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5189
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M1_MASK
@ PseudoVSLIDE1UP_VX_M1_MASK
Definition riscv/opcodes.hpp:8809
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M2
@ PseudoVLSSEG4E64_V_M2
Definition riscv/opcodes.hpp:5478
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_M1
@ PseudoVAESDM_VS_M4_M1
Definition riscv/opcodes.hpp:678
LIEF::assembly::riscv::OPCODE::VRGATHER_VV
@ VRGATHER_VV
Definition riscv/opcodes.hpp:13609
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E32
@ PseudoVFMSUB_VV_M4_E32
Definition riscv/opcodes.hpp:2296
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF8
@ PseudoVFNCVT_XU_F_W_MF8
Definition riscv/opcodes.hpp:2601
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF4
@ PseudoVSRL_VV_MF4
Definition riscv/opcodes.hpp:9929
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E32
@ PseudoVDIV_VX_M8_E32
Definition riscv/opcodes.hpp:1581
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF2_MASK
@ PseudoVLOXSEG8EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4981
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E64_V_M1_MASK
@ PseudoVSSEG8E64_V_M1_MASK
Definition riscv/opcodes.hpp:10154
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M1
@ PseudoVLOXEI32_V_M4_M1
Definition riscv/opcodes.hpp:4236
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32_M2
@ PseudoVFMV_S_FPR32_M2
Definition riscv/opcodes.hpp:2394
LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M8
@ PseudoVLE64FF_V_M8
Definition riscv/opcodes.hpp:4133
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M4_E16
@ PseudoVFNMADD_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2679
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_M1_MASK
@ PseudoVLUXSEG7EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6269
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M2_MASK
@ PseudoVMAX_VV_M2_MASK
Definition riscv/opcodes.hpp:6545
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E8
@ PseudoVREM_VX_M8_E8
Definition riscv/opcodes.hpp:8246
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M1
@ PseudoVWSUB_VX_M1
Definition riscv/opcodes.hpp:11791
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E64
@ PseudoVREM_VV_M4_E64
Definition riscv/opcodes.hpp:8192
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF4
@ PseudoVMSGT_VI_MF4
Definition riscv/opcodes.hpp:7047
LIEF::assembly::riscv::OPCODE::AMOCAS_Q
@ AMOCAS_Q
Definition riscv/opcodes.hpp:11995
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_MF2
@ PseudoVSM4R_VS_M8_MF2
Definition riscv/opcodes.hpp:8953
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF4_MASK
@ PseudoVWMACC_VV_MF4_MASK
Definition riscv/opcodes.hpp:11524
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF8_MASK
@ PseudoVWADD_VX_MF8_MASK
Definition riscv/opcodes.hpp:11418
LIEF::assembly::riscv::OPCODE::MOPR17
@ MOPR17
Definition riscv/opcodes.hpp:12869
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF8
@ PseudoVLSSEG2E8_V_MF8
Definition riscv/opcodes.hpp:5432
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF2
@ PseudoVSADDU_VV_MF2
Definition riscv/opcodes.hpp:8626
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M8_MASK
@ PseudoVMULH_VX_M8_MASK
Definition riscv/opcodes.hpp:7354
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M1_MASK
@ PseudoVNMSUB_VX_M1_MASK
Definition riscv/opcodes.hpp:7541
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E64_MASK
@ PseudoVFREDOSUM_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:3000
LIEF::assembly::riscv::OPCODE::CM_MVSA01
@ CM_MVSA01
Definition riscv/opcodes.hpp:12146
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E32_MASK
@ PseudoVFWCVT_F_X_V_M1_E32_MASK
Definition riscv/opcodes.hpp:3610
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_MF8
@ PseudoVSSSEG2E8_V_MF8
Definition riscv/opcodes.hpp:10281
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF2_MASK
@ PseudoVADD_VV_MF2_MASK
Definition riscv/opcodes.hpp:621
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M2_MASK
@ PseudoVWSUBU_VV_M2_MASK
Definition riscv/opcodes.hpp:11722
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF4
@ PseudoVLOXSEG8EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:4946
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M4
@ PseudoVMFGE_VFPR32_M4
Definition riscv/opcodes.hpp:6656
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF2
@ PseudoVSUXSEG6EI64_V_M2_MF2
Definition riscv/opcodes.hpp:11145
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M2_MASK
@ PseudoVSLIDEDOWN_VX_M2_MASK
Definition riscv/opcodes.hpp:8839
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M2_E32
@ PseudoVFMIN_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2146
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M8_MASK
@ PseudoVRGATHEREI16_VV_M8_E32_M8_MASK
Definition riscv/opcodes.hpp:8381
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF2_MASK
@ PseudoVSOXEI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9092
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF4
@ PseudoVSOXSEG5EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:9527
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M2
@ PseudoVSSSEG2E16_V_M2
Definition riscv/opcodes.hpp:10249
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M2_E16
@ PseudoVFSUB_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3393
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E64_MASK
@ PseudoVREM_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:8201
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M8_E16_MASK
@ PseudoVFRSQRT7_V_M8_E16_MASK
Definition riscv/opcodes.hpp:3080
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M2_MASK
@ PseudoVSUXSEG4EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:10920
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E32
@ PseudoVFNCVT_F_XU_W_MF2_E32
Definition riscv/opcodes.hpp:2467
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF4
@ PseudoVWMACC_VX_MF4
Definition riscv/opcodes.hpp:11535
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M2_M2_MASK
@ PseudoVLOXSEG3EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4557
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF4
@ PseudoVLOXSEG8EI64_V_M2_MF4
Definition riscv/opcodes.hpp:4982
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF4_MASK
@ PseudoVSOXEI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:9094
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_MF4
@ PseudoVMSNE_VI_MF4
Definition riscv/opcodes.hpp:7231
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M2_MASK
@ PseudoVSUXEI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10548
LIEF::assembly::riscv::OPCODE::FSGNJN_D_INX
@ FSGNJN_D_INX
Definition riscv/opcodes.hpp:12759
LIEF::assembly::riscv::OPCODE::PseudoMovAddr
@ PseudoMovAddr
Definition riscv/opcodes.hpp:416
LIEF::assembly::riscv::OPCODE::HLV_BU
@ HLV_BU
Definition riscv/opcodes.hpp:12801
LIEF::assembly::riscv::OPCODE::MOPR25
@ MOPR25
Definition riscv/opcodes.hpp:12878
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E16_MASK
@ PseudoVFNMACC_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:2652
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF2
@ PseudoVSSSEG7E16_V_MF2
Definition riscv/opcodes.hpp:10381
LIEF::assembly::riscv::OPCODE::DIVW
@ DIVW
Definition riscv/opcodes.hpp:12554
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M1
@ PseudoVSUXSEG2EI32_V_M2_M1
Definition riscv/opcodes.hpp:10703
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M2_MASK
@ PseudoVLUXSEG4EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:6069
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M1
@ PseudoVLOXSEG2EI8_V_MF4_M1
Definition riscv/opcodes.hpp:4454
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M1_E16
@ PseudoVFMAX_VFPR16_M1_E16
Definition riscv/opcodes.hpp:2057
LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_H_INX
@ PseudoQuietFLE_H_INX
Definition riscv/opcodes.hpp:422
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF4_MASK
@ PseudoVSSUBU_VV_MF4_MASK
Definition riscv/opcodes.hpp:10430
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B4
@ PseudoVMSBF_M_B4
Definition riscv/opcodes.hpp:6946
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_MF2_MASK
@ PseudoVSUXSEG7EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:11232
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M8
@ PseudoVASUBU_VX_M8
Definition riscv/opcodes.hpp:880
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF4_MASK
@ PseudoVLSEG2E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5123
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_MF2
@ PseudoVC_V_IV_SE_MF2
Definition riscv/opcodes.hpp:1285
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_M1
@ PseudoVSOXSEG8EI16_V_MF4_M1
Definition riscv/opcodes.hpp:9763
LIEF::assembly::riscv::OPCODE::TH_FLURD
@ TH_FLURD
Definition riscv/opcodes.hpp:13048
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M1
@ PseudoVFNCVT_XU_F_W_M1
Definition riscv/opcodes.hpp:2591
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E32
@ PseudoVFNCVTBF16_F_F_W_M4_E32
Definition riscv/opcodes.hpp:2427
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E32
@ PseudoVREM_VV_M4_E32
Definition riscv/opcodes.hpp:8190
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF8_MASK
@ PseudoVNMSUB_VX_MF8_MASK
Definition riscv/opcodes.hpp:7553
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M4
@ PseudoVMSLT_VV_M4
Definition riscv/opcodes.hpp:7197
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M2_MASK
@ PseudoVLOXSEG2EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4349
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E32
@ PseudoVREMU_VV_M1_E32
Definition riscv/opcodes.hpp:8086
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M2_E16
@ PseudoVFMSUB_VFPR16_M2_E16
Definition riscv/opcodes.hpp:2254
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M2
@ PseudoVSLIDEUP_VX_M2
Definition riscv/opcodes.hpp:8866
LIEF::assembly::riscv::OPCODE::VAND_VI
@ VAND_VI
Definition riscv/opcodes.hpp:13154
LIEF::assembly::riscv::OPCODE::G_UMULFIXSAT
@ G_UMULFIXSAT
Definition riscv/opcodes.hpp:191
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M2
@ PseudoVMFLT_VFPR16_M2
Definition riscv/opcodes.hpp:6744
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M4_MASK
@ PseudoTHVdotVMAQASU_VV_M4_MASK
Definition riscv/opcodes.hpp:455
LIEF::assembly::riscv::OPCODE::VXOR_VX
@ VXOR_VX
Definition riscv/opcodes.hpp:13840
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_M1
@ PseudoVSUXSEG3EI64_V_M1_M1
Definition riscv/opcodes.hpp:10851
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M2_MASK
@ PseudoVSOXSEG4EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9432
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF2_MASK
@ PseudoVSUXSEG8EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11290
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_M1
@ PseudoVSOXSEG8EI8_V_MF8_M1
Definition riscv/opcodes.hpp:9823
LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_M1
@ PseudoVSPILL3_M1
Definition riscv/opcodes.hpp:9837
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF8_E8
@ PseudoVREDMAX_VS_MF8_E8
Definition riscv/opcodes.hpp:7830
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF4_MASK
@ PseudoVSUXSEG5EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:11052
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M8
@ PseudoVOR_VI_M8
Definition riscv/opcodes.hpp:7632
LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SCI_B
@ CV_CMPLEU_SCI_B
Definition riscv/opcodes.hpp:12243
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF4_MASK
@ PseudoVSMUL_VX_MF4_MASK
Definition riscv/opcodes.hpp:8989
LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_MF4_MASK
@ PseudoVFROUND_NOEXCEPT_V_MF4_MASK
Definition riscv/opcodes.hpp:3060
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M8_M1
@ PseudoVSUXSEG8EI64_V_M8_M1
Definition riscv/opcodes.hpp:11313
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M1
@ PseudoVSSSEG2E16_V_M1
Definition riscv/opcodes.hpp:10247
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF4
@ PseudoVWMACCU_VV_MF4
Definition riscv/opcodes.hpp:11499
LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M4
@ PseudoVLE64FF_V_M4
Definition riscv/opcodes.hpp:4131
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M4_MASK
@ PseudoVIOTA_M_M4_MASK
Definition riscv/opcodes.hpp:4074
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_M1_MASK
@ PseudoVSOXSEG5EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9532
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M1
@ PseudoVAND_VX_M1
Definition riscv/opcodes.hpp:846
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF2
@ PseudoVSSSEG5E16_V_MF2
Definition riscv/opcodes.hpp:10341
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF2_MASK
@ PseudoVSUXEI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:10596
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B8_MASK
@ PseudoVFIRST_M_B8_MASK
Definition riscv/opcodes.hpp:1936
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M2_MASK
@ PseudoVASUBU_VX_M2_MASK
Definition riscv/opcodes.hpp:877
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_M1
@ PseudoVAESDF_VS_M8_M1
Definition riscv/opcodes.hpp:655
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M2_MASK
@ PseudoVSOXSEG3EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9322
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF8_E8_MASK
@ PseudoVREMU_VV_MF8_E8_MASK
Definition riscv/opcodes.hpp:8127
LIEF::assembly::riscv::OPCODE::FCVT_L_H
@ FCVT_L_H
Definition riscv/opcodes.hpp:12611
LIEF::assembly::riscv::OPCODE::TH_LWD
@ TH_LWD
Definition riscv/opcodes.hpp:13086
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF4_MASK
@ PseudoVSUXSEG3EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:10820
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M8_MASK
@ PseudoVMSLE_VX_M8_MASK
Definition riscv/opcodes.hpp:7156
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_M1
@ PseudoVSOXSEG6EI64_V_M4_M1
Definition riscv/opcodes.hpp:9645
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M2_MASK
@ PseudoVLOXEI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4239
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF2_MASK
@ PseudoVLUXEI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:5721
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M4_E32
@ PseudoVFMIN_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2148
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E32
@ PseudoVFMSUB_VV_MF2_E32
Definition riscv/opcodes.hpp:2308
LIEF::assembly::riscv::OPCODE::TH_MULS
@ TH_MULS
Definition riscv/opcodes.hpp:13095
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF4_MASK
@ PseudoVLOXSEG8EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4955
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M4_MASK
@ PseudoVSLIDE1DOWN_VX_M4_MASK
Definition riscv/opcodes.hpp:8799
LIEF::assembly::riscv::OPCODE::FSQRT_S_INX
@ FSQRT_S_INX
Definition riscv/opcodes.hpp:12785
LIEF::assembly::riscv::OPCODE::UNIMP
@ UNIMP
Definition riscv/opcodes.hpp:13129
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_MF2
@ PseudoVC_V_FPR16VV_SE_MF2
Definition riscv/opcodes.hpp:1176
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M8
@ PseudoVSSRL_VI_M8
Definition riscv/opcodes.hpp:10211
LIEF::assembly::riscv::OPCODE::VLSEG8E32_V
@ VLSEG8E32_V
Definition riscv/opcodes.hpp:13419
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M4_E16
@ PseudoVFWMACCBF16_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3701
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M4_MASK
@ PseudoVAADD_VX_M4_MASK
Definition riscv/opcodes.hpp:568
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M4
@ PseudoVAADD_VV_M4
Definition riscv/opcodes.hpp:553
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E32_MASK_TIED
@ PseudoVFWADD_WV_M2_E32_MASK_TIED
Definition riscv/opcodes.hpp:3519
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M4
@ PseudoVSSUBU_VV_M4
Definition riscv/opcodes.hpp:10423
LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M4
@ PseudoVADC_VIM_M4
Definition riscv/opcodes.hpp:579
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_MF2
@ PseudoVMV_V_X_MF2
Definition riscv/opcodes.hpp:7408
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_M1
@ PseudoVLUXSEG6EI16_V_M1_M1
Definition riscv/opcodes.hpp:6162
LIEF::assembly::riscv::OPCODE::SD_RL
@ SD_RL
Definition riscv/opcodes.hpp:12949
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E16_MASK
@ PseudoVDIV_VX_M4_E16_MASK
Definition riscv/opcodes.hpp:1572
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M1
@ PseudoVLSEG4E64FF_V_M1
Definition riscv/opcodes.hpp:5210
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E16_MASK
@ PseudoVFWSUB_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3982
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E16
@ PseudoVFADD_VV_M1_E16
Definition riscv/opcodes.hpp:1629
LIEF::assembly::riscv::OPCODE::VSSEG2E8_V
@ VSSEG2E8_V
Definition riscv/opcodes.hpp:13705
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M4
@ PseudoVSSRL_VI_M4
Definition riscv/opcodes.hpp:10209
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M2_MASK
@ PseudoVLUXSEG3EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:5943
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M1
@ PseudoVMIN_VV_M1
Definition riscv/opcodes.hpp:6854
LIEF::assembly::riscv::OPCODE::VLSSEG6E32_V
@ VLSSEG6E32_V
Definition riscv/opcodes.hpp:13441
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF4_MASK
@ PseudoVAADD_VX_MF4_MASK
Definition riscv/opcodes.hpp:574
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_M1
@ PseudoVSUXSEG7EI32_V_MF2_M1
Definition riscv/opcodes.hpp:11207
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M2_MASK
@ PseudoVSRA_VX_M2_MASK
Definition riscv/opcodes.hpp:9894
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M8_M8_MASK
@ PseudoVLOXEI8_V_M8_M8_MASK
Definition riscv/opcodes.hpp:4309
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M4_MASK
@ PseudoVANDN_VX_M4_MASK
Definition riscv/opcodes.hpp:809
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E16
@ PseudoVFREDMAX_VS_M1_E16
Definition riscv/opcodes.hpp:2935
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E8_MASK
@ PseudoVREM_VX_M4_E8_MASK
Definition riscv/opcodes.hpp:8239
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E32
@ PseudoVFREC7_V_MF2_E32
Definition riscv/opcodes.hpp:2931
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M8_E64_MASK
@ PseudoVFDIV_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:1892
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M1_MASK
@ PseudoVLSEG4E32FF_V_M1_MASK
Definition riscv/opcodes.hpp:5199
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M2
@ PseudoVRGATHEREI16_VV_M8_E16_M2
Definition riscv/opcodes.hpp:8370
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M4_MASK
@ PseudoVNSRL_WV_M4_MASK
Definition riscv/opcodes.hpp:7607
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E64
@ PseudoVFNMSAC_VV_M4_E64
Definition riscv/opcodes.hpp:2781
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF4_MASK
@ PseudoVLOXEI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4227
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E64_MASK
@ PseudoVREDOR_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:7949
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M2_MASK
@ PseudoVLSSEG3E32_V_M2_MASK
Definition riscv/opcodes.hpp:5445
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E32
@ PseudoVFWNMACC_VV_M2_E32
Definition riscv/opcodes.hpp:3863
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M8_E64_MASK
@ PseudoVFSGNJN_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:3150
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E16
@ PseudoVREDMIN_VS_M4_E16
Definition riscv/opcodes.hpp:7892
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M1
@ PseudoVNSRL_WV_M1
Definition riscv/opcodes.hpp:7602
LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_MF4
@ PseudoVMNAND_MM_MF4
Definition riscv/opcodes.hpp:6887
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M4
@ PseudoVLOXEI64_V_M4_M4
Definition riscv/opcodes.hpp:4278
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M4
@ PseudoVLUXSEG2EI32_V_M8_M4
Definition riscv/opcodes.hpp:5786
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M4
@ PseudoVWSUB_VX_M4
Definition riscv/opcodes.hpp:11795
LIEF::assembly::riscv::OPCODE::CPOPW
@ CPOPW
Definition riscv/opcodes.hpp:12152
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_M1_MASK
@ PseudoVLOXSEG2EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4363
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M1
@ PseudoVFNCVT_RTZ_X_F_W_M1
Definition riscv/opcodes.hpp:2579
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_M4
@ PseudoVC_V_FPR32VW_M4
Definition riscv/opcodes.hpp:1214
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M1_MASK
@ PseudoVMSEQ_VX_M1_MASK
Definition riscv/opcodes.hpp:6981
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M1_MASK
@ PseudoVMIN_VV_M1_MASK
Definition riscv/opcodes.hpp:6855
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF4_MASK
@ PseudoVLSEG7E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5355
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E64
@ PseudoVFMUL_VV_M2_E64
Definition riscv/opcodes.hpp:2352
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M4
@ PseudoVFNCVT_RM_XU_F_W_M4
Definition riscv/opcodes.hpp:2529
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E8_MASK
@ PseudoVDIV_VV_MF4_E8_MASK
Definition riscv/opcodes.hpp:1552
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M8_MASK
@ PseudoVMSGT_VX_M8_MASK
Definition riscv/opcodes.hpp:7058
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_M1_MASK
@ PseudoVSSSEG7E16_V_M1_MASK
Definition riscv/opcodes.hpp:10380
LIEF::assembly::riscv::OPCODE::C_MOP3
@ C_MOP3
Definition riscv/opcodes.hpp:12516
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF2_MASK
@ PseudoVSSRL_VX_MF2_MASK
Definition riscv/opcodes.hpp:10242
LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_MF4
@ PseudoVC_XVV_SE_MF4
Definition riscv/opcodes.hpp:1401
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF8
@ PseudoVSOXSEG2EI64_V_M1_MF8
Definition riscv/opcodes.hpp:9231
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M4_E32
@ PseudoVFNCVT_RM_F_X_W_M4_E32
Definition riscv/opcodes.hpp:2517
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E32
@ PseudoVREDMAXU_VS_M4_E32
Definition riscv/opcodes.hpp:7762
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E8_MASK
@ PseudoVDIV_VV_M4_E8_MASK
Definition riscv/opcodes.hpp:1534
LIEF::assembly::riscv::OPCODE::FENCE_TSO
@ FENCE_TSO
Definition riscv/opcodes.hpp:12652
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK
@ PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3706
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E32
@ PseudoVFNCVT_F_F_W_M1_E32
Definition riscv/opcodes.hpp:2437
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E16_MASK
@ PseudoVFNCVT_F_XU_W_M4_E16_MASK
Definition riscv/opcodes.hpp:2462
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M1_E16_MASK
@ PseudoVFMSAC_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:2193
LIEF::assembly::riscv::OPCODE::VREMU_VV
@ VREMU_VV
Definition riscv/opcodes.hpp:13602
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_M1_MASK
@ PseudoVLUXSEG5EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6109
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF4_MASK
@ PseudoVSOXSEG2EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:9288
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M1_MASK
@ PseudoVMSLTU_VX_M1_MASK
Definition riscv/opcodes.hpp:7179
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_MF4
@ PseudoVMADC_VIM_MF4
Definition riscv/opcodes.hpp:6435
LIEF::assembly::riscv::OPCODE::C_JALR
@ C_JALR
Definition riscv/opcodes.hpp:12499
LIEF::assembly::riscv::OPCODE::CM_JT
@ CM_JT
Definition riscv/opcodes.hpp:12144
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M1
@ PseudoVASUB_VV_M1
Definition riscv/opcodes.hpp:888
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M1_MASK
@ PseudoVFCVT_RTZ_X_F_V_M1_MASK
Definition riscv/opcodes.hpp:1828
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E32
@ PseudoVREDMIN_VS_M2_E32
Definition riscv/opcodes.hpp:7886
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M8_E16
@ PseudoVFRDIV_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2881
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_M1
@ PseudoVSSSEG6E8_V_M1
Definition riscv/opcodes.hpp:10371
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF2
@ PseudoVWMACCSU_VV_MF2
Definition riscv/opcodes.hpp:11461
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E8
@ PseudoVDIVU_VX_M2_E8
Definition riscv/opcodes.hpp:1481
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF8
@ PseudoVSOXSEG6EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:9609
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_MF4
@ PseudoVAESZ_VS_M2_MF4
Definition riscv/opcodes.hpp:773
LIEF::assembly::riscv::OPCODE::CV_OR_SCI_B
@ CV_OR_SCI_B
Definition riscv/opcodes.hpp:12381
LIEF::assembly::riscv::OPCODE::AMOCAS_H_AQ
@ AMOCAS_H_AQ
Definition riscv/opcodes.hpp:11992
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M2
@ PseudoVLOXSEG3EI64_V_M4_M2
Definition riscv/opcodes.hpp:4544
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M4
@ PseudoVFWCVT_RTZ_X_F_V_M4
Definition riscv/opcodes.hpp:3671
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF2_MASK
@ PseudoVSOXSEG6EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9642
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M8_E64_MASK
@ PseudoVFNMSUB_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2824
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF8
@ PseudoVLOXSEG4EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:4606
LIEF::assembly::riscv::OPCODE::VSSSEG7E8_V
@ VSSSEG7E8_V
Definition riscv/opcodes.hpp:13759
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_M8
@ PseudoVMERGE_VXM_M8
Definition riscv/opcodes.hpp:6594
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_MF4
@ PseudoVC_V_IVW_MF4
Definition riscv/opcodes.hpp:1266
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF4
@ PseudoVLUXEI64_V_M2_MF4
Definition riscv/opcodes.hpp:5664
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF8
@ PseudoVSADDU_VX_MF8
Definition riscv/opcodes.hpp:8644
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M2_MASK
@ PseudoVLSSEG2E64_V_M2_MASK
Definition riscv/opcodes.hpp:5419
LIEF::assembly::riscv::OPCODE::SHA256SIG0
@ SHA256SIG0
Definition riscv/opcodes.hpp:12965
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M8_E64_MASK
@ PseudoVFSGNJ_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:3270
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF4
@ PseudoVLOXSEG7EI32_V_M1_MF4
Definition riscv/opcodes.hpp:4874
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M8_MASK
@ PseudoVSLL_VX_M8_MASK
Definition riscv/opcodes.hpp:8913
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF2_MASK
@ PseudoVSSEG6E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10106
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF2_MASK
@ PseudoVSOXSEG7EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9714
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64FF_V_M1_MASK
@ PseudoVLSEG5E64FF_V_M1_MASK
Definition riscv/opcodes.hpp:5259
LIEF::assembly::riscv::OPCODE::VMIN_VX
@ VMIN_VX
Definition riscv/opcodes.hpp:13516
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF2_E32_MASK
@ PseudoVFREC7_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:2932
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF4_E16
@ PseudoVFSGNJX_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3191
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_M1_MASK
@ PseudoVSUXSEG6EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:11150
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF4_MASK
@ PseudoVSOXSEG4EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:9472
LIEF::assembly::riscv::OPCODE::FSGNJ_H
@ FSGNJ_H
Definition riscv/opcodes.hpp:12774
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E32_MASK
@ PseudoVREDAND_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:7703
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF2
@ PseudoVLOXSEG4EI64_V_M2_MF2
Definition riscv/opcodes.hpp:4648
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF2_E8
@ PseudoVCOMPRESS_VM_MF2_E8
Definition riscv/opcodes.hpp:1032
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M1
@ PseudoVLUXSEG3EI16_V_M2_M1
Definition riscv/opcodes.hpp:5868
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF8_MASK
@ PseudoVMIN_VV_MF8_MASK
Definition riscv/opcodes.hpp:6867
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF8
@ PseudoVWADD_WX_MF8
Definition riscv/opcodes.hpp:11453
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_M1_MASK
@ PseudoVSUXSEG6EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11128
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E16
@ PseudoVCOMPRESS_VM_M4_E16
Definition riscv/opcodes.hpp:1022
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M1_E32_MASK
@ PseudoVFSGNJN_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3134
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M2
@ PseudoVFWCVT_RM_XU_F_V_M2
Definition riscv/opcodes.hpp:3639
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M1
@ PseudoVWMACCU_VX_M1
Definition riscv/opcodes.hpp:11503
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M1_MASK
@ PseudoVLOXEI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4205
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E16_MASK
@ PseudoVFMACC_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:1986
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_MF4_MASK
@ PseudoVLSEG3E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5141
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M4
@ PseudoVADD_VI_M4
Definition riscv/opcodes.hpp:602
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M4_E64
@ PseudoVFMADD_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2023
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF8_MASK
@ PseudoVSSEG8E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10162
LIEF::assembly::riscv::OPCODE::AMOMINU_B_RL
@ AMOMINU_B_RL
Definition riscv/opcodes.hpp:12038
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF2_MASK
@ PseudoVLUXSEG5EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6091
LIEF::assembly::riscv::OPCODE::G_INDEXED_SEXTLOAD
@ G_INDEXED_SEXTLOAD
Definition riscv/opcodes.hpp:117
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_M1_MASK
@ PseudoVFNRCLIP_X_F_QF_M1_MASK
Definition riscv/opcodes.hpp:2866
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF4_MASK
@ PseudoVLUXSEG5EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:6153
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M1
@ PseudoVMSGT_VI_M1
Definition riscv/opcodes.hpp:7037
LIEF::assembly::riscv::OPCODE::AMOAND_W_AQ
@ AMOAND_W_AQ
Definition riscv/opcodes.hpp:11976
LIEF::assembly::riscv::OPCODE::VMSBC_VXM
@ VMSBC_VXM
Definition riscv/opcodes.hpp:13524
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E16_MASK
@ PseudoVFWNMACC_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3858
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M4_MASK
@ PseudoVSOXEI32_V_M4_M4_MASK
Definition riscv/opcodes.hpp:9062
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M2_MASK
@ PseudoVSLL_VV_M2_MASK
Definition riscv/opcodes.hpp:8895
LIEF::assembly::riscv::OPCODE::FCVT_W_S_INX
@ FCVT_W_S_INX
Definition riscv/opcodes.hpp:12642
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E16
@ PseudoVFREDMAX_VS_M8_E16
Definition riscv/opcodes.hpp:2953
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_MF2_MASK
@ PseudoVSUXSEG6EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:11152
LIEF::assembly::riscv::OPCODE::TH_LBIA
@ TH_LBIA
Definition riscv/opcodes.hpp:13061
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF4
@ PseudoVLOXSEG2EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:4460
LIEF::assembly::riscv::OPCODE::PseudoCCSRAI
@ PseudoCCSRAI
Definition riscv/opcodes.hpp:357
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M4
@ PseudoVFWCVT_RM_X_F_V_M4
Definition riscv/opcodes.hpp:3651
LIEF::assembly::riscv::OPCODE::AMOAND_D_AQ_RL
@ AMOAND_D_AQ_RL
Definition riscv/opcodes.hpp:11969
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E16_MASK
@ PseudoVFREC7_V_M8_E16_MASK
Definition riscv/opcodes.hpp:2924
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M8_MASK
@ PseudoVMULHSU_VV_M8_MASK
Definition riscv/opcodes.hpp:7284
LIEF::assembly::riscv::OPCODE::VC_IVV
@ VC_IVV
Definition riscv/opcodes.hpp:13177
LIEF::assembly::riscv::OPCODE::VSSEG6E8_V
@ VSSEG6E8_V
Definition riscv/opcodes.hpp:13721
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E32
@ PseudoVREDXOR_VS_MF2_E32
Definition riscv/opcodes.hpp:8042
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E64_MASK
@ PseudoVFMIN_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:2167
LIEF::assembly::riscv::OPCODE::PseudoRV32ZdinxSD
@ PseudoRV32ZdinxSD
Definition riscv/opcodes.hpp:434
LIEF::assembly::riscv::OPCODE::PseudoBRINDX7
@ PseudoBRINDX7
Definition riscv/opcodes.hpp:335
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF8_MASK
@ PseudoVSSSEG8E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10418
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E32_MASK
@ PseudoVFREDOSUM_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:3016
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_M1_MASK
@ PseudoVRGATHEREI16_VV_M1_E64_M1_MASK
Definition riscv/opcodes.hpp:8291
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M1_MASK
@ PseudoVMAXU_VV_M1_MASK
Definition riscv/opcodes.hpp:6515
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF4_MASK
@ PseudoVSSSEG6E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10364
LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M2
@ PseudoVAESKF2_VI_M2
Definition riscv/opcodes.hpp:762
LIEF::assembly::riscv::OPCODE::FNMSUB_D_IN32X
@ FNMSUB_D_IN32X
Definition riscv/opcodes.hpp:12744
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_MF2
@ PseudoVFWCVT_RM_XU_F_V_MF2
Definition riscv/opcodes.hpp:3643
LIEF::assembly::riscv::OPCODE::VFNCVT_XU_F_W
@ VFNCVT_XU_F_W
Definition riscv/opcodes.hpp:13241
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M1
@ PseudoVMADC_VXM_M1
Definition riscv/opcodes.hpp:6458
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M4
@ PseudoVLOXEI16_V_M8_M4
Definition riscv/opcodes.hpp:4200
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M2
@ PseudoVLUXSEG4EI32_V_M4_M2
Definition riscv/opcodes.hpp:6016
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF4_MASK
@ PseudoVLSSEG8E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5555
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M1
@ PseudoVLUXSEG4EI8_V_M1_M1
Definition riscv/opcodes.hpp:6054
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M1
@ PseudoVREV8_V_M1
Definition riscv/opcodes.hpp:8260
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF8_MASK
@ PseudoVLSEG8E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5397
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E8_MASK
@ PseudoVREDMIN_VS_M1_E8_MASK
Definition riscv/opcodes.hpp:7883
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF8_MASK
@ PseudoVSOXSEG2EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:9290
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF8_MASK
@ PseudoVMSGT_VI_MF8_MASK
Definition riscv/opcodes.hpp:7050
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M2
@ PseudoVSOXSEG3EI64_V_M4_M2
Definition riscv/opcodes.hpp:9365
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF2_MASK
@ PseudoVSRA_VX_MF2_MASK
Definition riscv/opcodes.hpp:9900
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_MF8
@ PseudoVMADC_VI_MF8
Definition riscv/opcodes.hpp:6443
LIEF::assembly::riscv::OPCODE::C_LBU
@ C_LBU
Definition riscv/opcodes.hpp:12501
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M8_MASK
@ PseudoVMADD_VV_M8_MASK
Definition riscv/opcodes.hpp:6479
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M4_MASK
@ PseudoVRGATHEREI16_VV_M4_E16_M4_MASK
Definition riscv/opcodes.hpp:8343
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_M1_MASK
@ PseudoVLSEG7E16FF_V_M1_MASK
Definition riscv/opcodes.hpp:5319
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_MF2
@ PseudoVFMERGE_VFPR32M_MF2
Definition riscv/opcodes.hpp:2127
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M4_MASK
@ PseudoVMINU_VX_M4_MASK
Definition riscv/opcodes.hpp:6845
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E8_MASK
@ PseudoVREDOR_VS_M4_E8_MASK
Definition riscv/opcodes.hpp:7943
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M1
@ PseudoVWADDU_WX_M1
Definition riscv/opcodes.hpp:11383
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF4_MASK
@ PseudoVLOXSEG5EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4707
LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_MF8
@ PseudoVMORN_MM_MF8
Definition riscv/opcodes.hpp:6902
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_M1_MASK
@ PseudoVSOXSEG6EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9624
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF2
@ PseudoVMSEQ_VI_MF2
Definition riscv/opcodes.hpp:6960
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M4
@ PseudoVMFGE_VFPR64_M4
Definition riscv/opcodes.hpp:6666
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M2
@ PseudoVLOXSEG2EI64_V_M8_M2
Definition riscv/opcodes.hpp:4430
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF8
@ PseudoVSUXSEG8EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:11333
LIEF::assembly::riscv::OPCODE::G_FABS
@ G_FABS
Definition riscv/opcodes.hpp:220
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_MF8
@ PseudoVSUXSEG2EI64_V_M1_MF8
Definition riscv/opcodes.hpp:10735
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_M2_MASK
@ PseudoVLOXSEG2EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4415
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF2_MASK
@ PseudoVSOXSEG8EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9820
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E64_MASK
@ PseudoVFREDOSUM_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:3006
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E32_MASK
@ PseudoVDIV_VX_M2_E32_MASK
Definition riscv/opcodes.hpp:1566
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M4_M1
@ PseudoVSOXSEG6EI32_V_M4_M1
Definition riscv/opcodes.hpp:9621
LIEF::assembly::riscv::OPCODE::VWSUBU_WV
@ VWSUBU_WV
Definition riscv/opcodes.hpp:13832
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_M1
@ PseudoVLOXSEG5EI64_V_M4_M1
Definition riscv/opcodes.hpp:4744
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M4
@ PseudoVSUXEI64_V_M4_M4
Definition riscv/opcodes.hpp:10603
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E8_MASK
@ PseudoVWREDSUMU_VS_M8_E8_MASK
Definition riscv/opcodes.hpp:11634
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M1_MASK
@ PseudoVLUXSEG2EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:5821
LIEF::assembly::riscv::OPCODE::Select_FPR16INX_Using_CC_GPR
@ Select_FPR16INX_Using_CC_GPR
Definition riscv/opcodes.hpp:11916
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M8_E32_MASK
@ PseudoVFSGNJ_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:3260
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF4_MASK
@ PseudoVLOXSEG6EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:4847
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M2
@ PseudoVFCVT_RM_XU_F_V_M2
Definition riscv/opcodes.hpp:1793
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M1_MASK
@ PseudoVNCLIP_WV_M1_MASK
Definition riscv/opcodes.hpp:7475
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M1
@ PseudoVSOXSEG2EI32_V_M2_M1
Definition riscv/opcodes.hpp:9199
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E8_MASK
@ PseudoVREDMAX_VS_M1_E8_MASK
Definition riscv/opcodes.hpp:7795
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_MF2_E32_MASK
@ PseudoVFNMSAC_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2756
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E16_MASK
@ PseudoVREDXOR_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:8025
LIEF::assembly::riscv::OPCODE::VSOXEI16_V
@ VSOXEI16_V
Definition riscv/opcodes.hpp:13660
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF4
@ PseudoVWSUB_VX_MF4
Definition riscv/opcodes.hpp:11799
LIEF::assembly::riscv::OPCODE::VSOXSEG7EI32_V
@ VSOXSEG7EI32_V
Definition riscv/opcodes.hpp:13685
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_M1
@ PseudoVLSEG8E32FF_V_M1
Definition riscv/opcodes.hpp:5370
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_MF8
@ PseudoVAESEM_VS_M4_MF8
Definition riscv/opcodes.hpp:741
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M1
@ PseudoVSUXEI32_V_M1_M1
Definition riscv/opcodes.hpp:10545
LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_H
@ CV_SDOTUSP_H
Definition riscv/opcodes.hpp:12406
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M1_MASK
@ PseudoVMINU_VX_M1_MASK
Definition riscv/opcodes.hpp:6841
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M4_MASK
@ PseudoVMFNE_VFPR64_M4_MASK
Definition riscv/opcodes.hpp:6811
LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64_AQ_RL
@ AMOCAS_D_RV64_AQ_RL
Definition riscv/opcodes.hpp:11989
LIEF::assembly::riscv::OPCODE::VSUXSEG4EI8_V
@ VSUXSEG4EI8_V
Definition riscv/opcodes.hpp:13785
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E16_MASK
@ PseudoVFREDMAX_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:2936
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF8_MASK
@ PseudoVNCLIP_WX_MF8_MASK
Definition riscv/opcodes.hpp:7497
LIEF::assembly::riscv::OPCODE::Select_FPR64IN32X_Using_CC_GPR
@ Select_FPR64IN32X_Using_CC_GPR
Definition riscv/opcodes.hpp:11920
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M4_E16
@ PseudoVFWSUB_WFPR16_M4_E16
Definition riscv/opcodes.hpp:3995
LIEF::assembly::riscv::OPCODE::CV_SHUFFLE_H
@ CV_SHUFFLE_H
Definition riscv/opcodes.hpp:12418
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF2
@ PseudoVSOXSEG4EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:9499
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF2
@ PseudoVSOXSEG5EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:9579
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E16
@ PseudoVFWSUB_VV_M2_E16
Definition riscv/opcodes.hpp:3977
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M2_MASK
@ PseudoVLUXSEG4EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:5987
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E8_MASK
@ PseudoVWREDSUM_VS_MF4_E8_MASK
Definition riscv/opcodes.hpp:11680
LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M4
@ PseudoVLE64_V_M4
Definition riscv/opcodes.hpp:4139
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E32_MASK
@ PseudoVFWMUL_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3828
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_M1_MASK
@ PseudoVLUXSEG6EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6169
LIEF::assembly::riscv::OPCODE::G_GLOBAL_VALUE
@ G_GLOBAL_VALUE
Definition riscv/opcodes.hpp:90
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M1
@ PseudoVSSRL_VX_M1
Definition riscv/opcodes.hpp:10233
LIEF::assembly::riscv::OPCODE::VSSSEG7E64_V
@ VSSSEG7E64_V
Definition riscv/opcodes.hpp:13758
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_M1
@ PseudoVLOXSEG8EI8_V_MF4_M1
Definition riscv/opcodes.hpp:4996
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M8_E32_MASK
@ PseudoVFNMADD_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2694
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M2_MASK
@ PseudoVSSEG2E16_V_M2_MASK
Definition riscv/opcodes.hpp:9994
LIEF::assembly::riscv::OPCODE::C_FLDSP
@ C_FLDSP
Definition riscv/opcodes.hpp:12490
LIEF::assembly::riscv::OPCODE::CV_CMPLEU_H
@ CV_CMPLEU_H
Definition riscv/opcodes.hpp:12242
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF4_E16
@ PseudoVFSGNJN_VV_MF4_E16
Definition riscv/opcodes.hpp:3179
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_MF2
@ PseudoVLOXEI8_V_MF2_MF2
Definition riscv/opcodes.hpp:4316
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M4_MASK
@ PseudoVMSEQ_VV_M4_MASK
Definition riscv/opcodes.hpp:6971
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M1
@ PseudoVFSLIDE1DOWN_VFPR64_M1
Definition riscv/opcodes.hpp:3323
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M4
@ PseudoVLOXEI16_V_M1_M4
Definition riscv/opcodes.hpp:4182
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF4_MASK
@ PseudoVSOXSEG5EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9528
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_MF4_MASK
@ PseudoVLUXEI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:5665
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E32_MASK
@ PseudoVREDSUM_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:7991
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M2_MASK
@ PseudoVWMULU_VX_M2_MASK
Definition riscv/opcodes.hpp:11578
LIEF::assembly::riscv::OPCODE::SLTI
@ SLTI
Definition riscv/opcodes.hpp:12988
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF8_MASK
@ PseudoVASUB_VV_MF8_MASK
Definition riscv/opcodes.hpp:901
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF8
@ PseudoVSOXSEG5EI64_V_M1_MF8
Definition riscv/opcodes.hpp:9557
LIEF::assembly::riscv::OPCODE::VSEXT_VF4
@ VSEXT_VF4
Definition riscv/opcodes.hpp:13638
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M8_E16
@ PseudoVFNMSAC_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2741
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_MF8
@ PseudoVC_V_XVV_SE_MF8
Definition riscv/opcodes.hpp:1355
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M4_MASK
@ PseudoVSOXSEG2EI32_V_M4_M4_MASK
Definition riscv/opcodes.hpp:9212
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF8_MASK
@ PseudoVWSLL_VI_MF8_MASK
Definition riscv/opcodes.hpp:11694
LIEF::assembly::riscv::OPCODE::PseudoVQMACC_4x8x4_M2
@ PseudoVQMACC_4x8x4_M2
Definition riscv/opcodes.hpp:7697
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E32
@ PseudoVREMU_VX_MF2_E32
Definition riscv/opcodes.hpp:8162
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF4_MASK
@ PseudoVLOXSEG4EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4605
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF4
@ PseudoVSOXSEG6EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:9601
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B8
@ PseudoVFIRST_M_B8
Definition riscv/opcodes.hpp:1935
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M1
@ PseudoVLUXSEG3EI64_V_M4_M1
Definition riscv/opcodes.hpp:5934
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF2
@ PseudoVSOXSEG5EI64_V_M2_MF2
Definition riscv/opcodes.hpp:9561
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E32_MASK
@ PseudoVFMSUB_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:2309
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M2_E64_MASK
@ PseudoVFNMACC_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2640
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M8_E16
@ PseudoVFSUB_VFPR16_M8_E16
Definition riscv/opcodes.hpp:3397
LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M8_MASK
@ PseudoVLE32_V_M8_MASK
Definition riscv/opcodes.hpp:4124
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M1_MF2
@ PseudoVSUXSEG8EI16_V_M1_MF2
Definition riscv/opcodes.hpp:11257
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M2
@ PseudoVSOXEI32_V_M8_M2
Definition riscv/opcodes.hpp:9065
LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_2x8x2_M1
@ PseudoVQMACCU_2x8x2_M1
Definition riscv/opcodes.hpp:7684
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_M2_MASK
@ PseudoVSUXSEG2EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:10774
LIEF::assembly::riscv::OPCODE::ReadCounterWide
@ ReadCounterWide
Definition riscv/opcodes.hpp:11913
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF4_MASK
@ PseudoVLOXSEG5EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:4767
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M2_MASK
@ PseudoVMSNE_VI_M2_MASK
Definition riscv/opcodes.hpp:7224
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF4_MASK
@ PseudoVLUXSEG2EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:5853
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E32
@ PseudoVFWCVT_F_F_V_M2_E32
Definition riscv/opcodes.hpp:3565
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E32_MASK
@ PseudoVFWMUL_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3836
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M1
@ PseudoVSOXSEG2EI8_V_MF2_M1
Definition riscv/opcodes.hpp:9267
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_MF2_MASK
@ PseudoVLUXSEG2EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:5845
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E16
@ PseudoVFWNMSAC_VV_M1_E16
Definition riscv/opcodes.hpp:3893
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E32_MASK
@ PseudoVREDMINU_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:7859
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF4_MASK
@ PseudoVNSRA_WV_MF4_MASK
Definition riscv/opcodes.hpp:7575
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF4_MASK
@ PseudoVLUXSEG2EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:5859
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M4_MASK
@ PseudoVSEXT_VF4_M4_MASK
Definition riscv/opcodes.hpp:8766
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_MF4
@ PseudoVLUXSEG7EI64_V_M2_MF4
Definition riscv/opcodes.hpp:6294
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_M1_MASK
@ PseudoVSSSEG7E8_V_M1_MASK
Definition riscv/opcodes.hpp:10392
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M2
@ PseudoVSSUBU_VV_M2
Definition riscv/opcodes.hpp:10421
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF8_MASK
@ PseudoVSADDU_VX_MF8_MASK
Definition riscv/opcodes.hpp:8645
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M4_MASK
@ PseudoVSRA_VV_M4_MASK
Definition riscv/opcodes.hpp:9882
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E64
@ PseudoVFMIN_VV_M4_E64
Definition riscv/opcodes.hpp:2178
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M1_M2_MASK
@ PseudoVLUXSEG2EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:5765
LIEF::assembly::riscv::OPCODE::PseudoFROUND_D_INX
@ PseudoFROUND_D_INX
Definition riscv/opcodes.hpp:376
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMAXIMUM
@ G_VECREDUCE_FMAXIMUM
Definition riscv/opcodes.hpp:306
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M4_MASK
@ PseudoVLSEG2E8FF_V_M4_MASK
Definition riscv/opcodes.hpp:5107
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M2_MASK
@ PseudoVLOXSEG2EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4423
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E16
@ PseudoVFMIN_VV_M4_E16
Definition riscv/opcodes.hpp:2174
LIEF::assembly::riscv::OPCODE::VREDMAXU_VS
@ VREDMAXU_VS
Definition riscv/opcodes.hpp:13595
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M1
@ PseudoVSOXSEG2EI32_V_M1_M1
Definition riscv/opcodes.hpp:9191
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M8
@ PseudoVMULH_VV_M8
Definition riscv/opcodes.hpp:7339
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF4_MASK
@ PseudoVLOXSEG2EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4461
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_MF4
@ PseudoVLOXSEG5EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:4760
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M1_MASK
@ PseudoVLSEG2E32FF_V_M1_MASK
Definition riscv/opcodes.hpp:5075
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M8_MASK
@ PseudoVLUXEI16_V_M2_M8_MASK
Definition riscv/opcodes.hpp:5585
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF8_MASK
@ PseudoVSUXSEG8EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:11302
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_M1
@ PseudoVAESDM_VS_M2_M1
Definition riscv/opcodes.hpp:673
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M1_MASK
@ PseudoVMACC_VX_M1_MASK
Definition riscv/opcodes.hpp:6417
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E32_MASK
@ PseudoVFNCVT_F_X_W_M2_E32_MASK
Definition riscv/opcodes.hpp:2478
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M2
@ PseudoVSOXSEG2EI32_V_M2_M2
Definition riscv/opcodes.hpp:9201
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M1_MASK
@ PseudoVSEXT_VF2_M1_MASK
Definition riscv/opcodes.hpp:8750
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E32
@ PseudoVFNCVT_F_X_W_M2_E32
Definition riscv/opcodes.hpp:2477
LIEF::assembly::riscv::OPCODE::CV_CMPLT_SC_H
@ CV_CMPLT_SC_H
Definition riscv/opcodes.hpp:12264
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M1
@ PseudoVFWCVT_X_F_V_M1
Definition riscv/opcodes.hpp:3687
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B4
@ PseudoVCPOP_M_B4
Definition riscv/opcodes.hpp:1044
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E64_MASK
@ PseudoVFMADD_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:2038
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M1
@ PseudoVLSSEG3E8_V_M1
Definition riscv/opcodes.hpp:5452
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M4_MASK
@ PseudoVXOR_VI_M4_MASK
Definition riscv/opcodes.hpp:11844
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF4_E16_MASK
@ PseudoVFWREDUSUM_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:3954
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF4_MASK
@ PseudoVLUXSEG4EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:6007
LIEF::assembly::riscv::OPCODE::CV_ADD_DIV4
@ CV_ADD_DIV4
Definition riscv/opcodes.hpp:12174
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M2_MASK
@ PseudoVFNCVT_RM_X_F_W_M2_MASK
Definition riscv/opcodes.hpp:2540
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E64
@ PseudoVREMU_VX_M4_E64
Definition riscv/opcodes.hpp:8148
LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF2_MASK
@ PseudoVID_V_MF2_MASK
Definition riscv/opcodes.hpp:4064
LIEF::assembly::riscv::OPCODE::SB_AQ_RL
@ SB_AQ_RL
Definition riscv/opcodes.hpp:12937
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_MF2
@ PseudoVMADC_VV_MF2
Definition riscv/opcodes.hpp:6455
LIEF::assembly::riscv::OPCODE::VSRL_VX
@ VSRL_VX
Definition riscv/opcodes.hpp:13697
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M2_MASK
@ PseudoVMADD_VX_M2_MASK
Definition riscv/opcodes.hpp:6489
LIEF::assembly::riscv::OPCODE::VSE32_V
@ VSE32_V
Definition riscv/opcodes.hpp:13631
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E16_MASK
@ PseudoVREDAND_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:7733
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_M1
@ PseudoVSOXSEG7EI8_V_MF4_M1
Definition riscv/opcodes.hpp:9737
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E32
@ PseudoVRGATHER_VV_M4_E32
Definition riscv/opcodes.hpp:8466
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M8
@ PseudoVLUXEI32_V_M4_M8
Definition riscv/opcodes.hpp:5634
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_M1_MASK
@ PseudoVLUXSEG5EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:6149
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M1_E64_MASK
@ PseudoVFADD_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:1622
LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI3_SCI_B
@ CV_SHUFFLEI3_SCI_B
Definition riscv/opcodes.hpp:12416
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M1_MASK
@ PseudoVSSEG3E64_V_M1_MASK
Definition riscv/opcodes.hpp:10042
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_MF2
@ PseudoVSM4R_VS_M2_MF2
Definition riscv/opcodes.hpp:8941
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M4_MASK
@ PseudoVWSLL_VX_M4_MASK
Definition riscv/opcodes.hpp:11712
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M4
@ PseudoVSSSEG2E16_V_M4
Definition riscv/opcodes.hpp:10251
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E16_MASK
@ PseudoVFMACC_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:1992
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M1_MASK
@ PseudoVMFGE_VFPR32_M1_MASK
Definition riscv/opcodes.hpp:6653
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_M1_MASK
@ PseudoVSUXSEG5EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11022
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M1_E16_MASK
@ PseudoVFMADD_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:1998
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E32_MASK
@ PseudoVFWADD_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3472
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M1
@ PseudoVMAX_VX_M1
Definition riscv/opcodes.hpp:6556
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF8_MASK
@ PseudoVNSRL_WX_MF8_MASK
Definition riscv/opcodes.hpp:7625
LIEF::assembly::riscv::OPCODE::AMOMINU_H_AQ
@ AMOMINU_H_AQ
Definition riscv/opcodes.hpp:12044
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M8_MASK
@ PseudoVASUBU_VX_M8_MASK
Definition riscv/opcodes.hpp:881
LIEF::assembly::riscv::OPCODE::VLSEG6E8_V
@ VLSEG6E8_V
Definition riscv/opcodes.hpp:13407
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF4_MASK
@ PseudoVMFLE_VFPR16_MF4_MASK
Definition riscv/opcodes.hpp:6711
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF2
@ PseudoVLSEG8E16_V_MF2
Definition riscv/opcodes.hpp:5366
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF4
@ PseudoVWSUB_WX_MF4
Definition riscv/opcodes.hpp:11835
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M1_E16_MASK
@ PseudoVFMADD_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:2028
LIEF::assembly::riscv::OPCODE::VLUXSEG6EI16_V
@ VLUXSEG6EI16_V
Definition riscv/opcodes.hpp:13472
LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M8_MASK
@ PseudoVSE64_V_M8_MASK
Definition riscv/opcodes.hpp:8731
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E16_MASK
@ PseudoVFWMACC_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3758
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E32_MASK
@ PseudoVWREDSUM_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:11662
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M2_MASK
@ PseudoVBREV8_V_M2_MASK
Definition riscv/opcodes.hpp:919
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_MF2_MF2
@ PseudoVAESDM_VS_MF2_MF2
Definition riscv/opcodes.hpp:690
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF2
@ PseudoVLUXSEG3EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:5884
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF2
@ PseudoVLUXSEG4EI64_V_M2_MF2
Definition riscv/opcodes.hpp:6040
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M8
@ PseudoVFSLIDE1DOWN_VFPR16_M8
Definition riscv/opcodes.hpp:3307
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E16
@ PseudoVFWADD_VV_MF2_E16
Definition riscv/opcodes.hpp:3481
LIEF::assembly::riscv::OPCODE::FMAXM_D
@ FMAXM_D
Definition riscv/opcodes.hpp:12693
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_MF4
@ PseudoVFWCVT_RM_XU_F_V_MF4
Definition riscv/opcodes.hpp:3645
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF4
@ PseudoVSUXSEG5EI64_V_M1_MF4
Definition riscv/opcodes.hpp:11059
LIEF::assembly::riscv::OPCODE::G_INVOKE_REGION_START
@ G_INVOKE_REGION_START
Definition riscv/opcodes.hpp:144
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M1_MASK
@ PseudoVSUXEI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10554
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E64_V_M1_MASK
@ PseudoVSSSEG6E64_V_M1_MASK
Definition riscv/opcodes.hpp:10370
LIEF::assembly::riscv::OPCODE::SHA512SUM1
@ SHA512SUM1
Definition riscv/opcodes.hpp:12977
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_MF8
@ PseudoVAESEF_VS_M4_MF8
Definition riscv/opcodes.hpp:712
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M1_MASK
@ PseudoVMFLE_VFPR64_M1_MASK
Definition riscv/opcodes.hpp:6723
LIEF::assembly::riscv::OPCODE::VLSSEG7E64_V
@ VLSSEG7E64_V
Definition riscv/opcodes.hpp:13446
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK
@ PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK
Definition riscv/opcodes.hpp:8405
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF4
@ PseudoVSADDU_VX_MF4
Definition riscv/opcodes.hpp:8642
LIEF::assembly::riscv::OPCODE::VMV_S_X
@ VMV_S_X
Definition riscv/opcodes.hpp:13560
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E16_MASK
@ PseudoVFNMADD_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:2730
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M4_M2_MASK
@ PseudoVLOXSEG4EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4591
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E32_MASK
@ PseudoVFCVT_RM_F_XU_V_M8_E32_MASK
Definition riscv/opcodes.hpp:1752
LIEF::assembly::riscv::OPCODE::G_SADDO
@ G_SADDO
Definition riscv/opcodes.hpp:174
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M4
@ PseudoVSOXSEG2EI8_V_MF2_M4
Definition riscv/opcodes.hpp:9271
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M1
@ PseudoVSUXSEG4EI64_V_M8_M1
Definition riscv/opcodes.hpp:10983
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M4_E32_MASK
@ PseudoVFMUL_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2329
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M1
@ PseudoVMADD_VV_M1
Definition riscv/opcodes.hpp:6472
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M2_MASK
@ PseudoVSADDU_VI_M2_MASK
Definition riscv/opcodes.hpp:8607
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF4_MASK
@ PseudoVSUXEI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:10552
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B64_MASK
@ PseudoVMSBF_M_B64_MASK
Definition riscv/opcodes.hpp:6949
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF2
@ PseudoVLSSEG8E8_V_MF2
Definition riscv/opcodes.hpp:5564
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF4
@ PseudoVSOXSEG6EI64_V_M1_MF4
Definition riscv/opcodes.hpp:9635
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M8_MASK
@ PseudoVSLIDEUP_VI_M8_MASK
Definition riscv/opcodes.hpp:8857
LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadNand32
@ PseudoAtomicLoadNand32
Definition riscv/opcodes.hpp:330
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M4_M2
@ PseudoVSUXSEG3EI16_V_M4_M2
Definition riscv/opcodes.hpp:10805
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_M4
@ PseudoVC_V_IVV_M4
Definition riscv/opcodes.hpp:1250
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF8_MASK
@ PseudoVLOXSEG4EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:4689
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M2
@ PseudoVMSNE_VX_M2
Definition riscv/opcodes.hpp:7251
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M2
@ PseudoVMFGT_VFPR16_M2
Definition riscv/opcodes.hpp:6672
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF2
@ PseudoVSUXSEG2EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:10789
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF2
@ PseudoVMSLE_VI_MF2
Definition riscv/opcodes.hpp:7129
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_MF2
@ PseudoVSOXSEG3EI16_V_M1_MF2
Definition riscv/opcodes.hpp:9295
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E8
@ PseudoVREDMAX_VS_M1_E8
Definition riscv/opcodes.hpp:7794
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E8
@ PseudoVCOMPRESS_VM_M4_E8
Definition riscv/opcodes.hpp:1025
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M2_E32_MASK
@ PseudoVFSUB_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3406
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M4_E64
@ PseudoVFMUL_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2338
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M2_MASK
@ PseudoVCLMULH_VX_M2_MASK
Definition riscv/opcodes.hpp:961
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M8
@ PseudoVZEXT_VF8_M8
Definition riscv/opcodes.hpp:11909
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_M1_MASK
@ PseudoVSUXSEG8EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11288
LIEF::assembly::riscv::OPCODE::VSSSEG2E32_V
@ VSSSEG2E32_V
Definition riscv/opcodes.hpp:13737
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF8
@ PseudoVMADD_VX_MF8
Definition riscv/opcodes.hpp:6498
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF4_MASK
@ PseudoVSUXSEG2EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:10692
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E16
@ PseudoVFSGNJX_VV_MF2_E16
Definition riscv/opcodes.hpp:3235
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M2
@ PseudoVWADDU_VX_M2
Definition riscv/opcodes.hpp:11349
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M1_E32
@ PseudoVFWSUB_WFPR32_M1_E32
Definition riscv/opcodes.hpp:4001
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_MF2
@ PseudoVSUXSEG6EI16_V_M1_MF2
Definition riscv/opcodes.hpp:11097
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M2
@ PseudoVSUXEI64_V_M2_M2
Definition riscv/opcodes.hpp:10593
LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV32_RL
@ AMOCAS_D_RV32_RL
Definition riscv/opcodes.hpp:11986
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_MF2
@ PseudoVAESDM_VV_MF2
Definition riscv/opcodes.hpp:697
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M2_MASK
@ PseudoVFSLIDE1UP_VFPR64_M2_MASK
Definition riscv/opcodes.hpp:3356
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M8_E32
@ PseudoVFSUB_VFPR32_M8_E32
Definition riscv/opcodes.hpp:3409
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M1
@ PseudoVWMULU_VV_M1
Definition riscv/opcodes.hpp:11563
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M4_MASK
@ PseudoVMSNE_VI_M4_MASK
Definition riscv/opcodes.hpp:7226
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF4
@ PseudoVSUXSEG5EI64_V_M2_MF4
Definition riscv/opcodes.hpp:11067
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_M1_MASK
@ PseudoVLSEG8E32_V_M1_MASK
Definition riscv/opcodes.hpp:5375
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M1
@ PseudoVLSSEG4E64_V_M1
Definition riscv/opcodes.hpp:5476
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M4_MASK
@ PseudoVLOXSEG2EI8_V_MF2_M4_MASK
Definition riscv/opcodes.hpp:4451
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF2_MASK
@ PseudoVSSUB_VX_MF2_MASK
Definition riscv/opcodes.hpp:10470
LIEF::assembly::riscv::OPCODE::CV_DOTUSP_B
@ CV_DOTUSP_B
Definition riscv/opcodes.hpp:12293
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF8
@ PseudoVCLMULH_VX_MF8
Definition riscv/opcodes.hpp:970
LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M2
@ PseudoVSE64_V_M2
Definition riscv/opcodes.hpp:8726
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M2_MASK
@ PseudoVLOXSEG4EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4665
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_M1
@ PseudoVLUXSEG2EI16_V_MF4_M1
Definition riscv/opcodes.hpp:5754
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF4_MASK
@ PseudoVLOXSEG8EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:5007
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF2
@ PseudoVSOXSEG5EI64_V_M1_MF2
Definition riscv/opcodes.hpp:9553
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M8
@ PseudoVMAXU_VV_M8
Definition riscv/opcodes.hpp:6520
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF2
@ PseudoVLOXSEG7EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:4864
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M2
@ PseudoVMFEQ_VFPR32_M2
Definition riscv/opcodes.hpp:6612
LIEF::assembly::riscv::OPCODE::CV_EXTBZ
@ CV_EXTBZ
Definition riscv/opcodes.hpp:12301
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF4
@ PseudoVROL_VV_MF4
Definition riscv/opcodes.hpp:8516
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M2
@ PseudoVMFLE_VFPR16_M2
Definition riscv/opcodes.hpp:6702
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M8_MASK
@ PseudoVCLMULH_VV_M8_MASK
Definition riscv/opcodes.hpp:951
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF2
@ PseudoVSUXSEG4EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:10927
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M8
@ PseudoVMFLT_VFPR16_M8
Definition riscv/opcodes.hpp:6748
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF4_E16
@ PseudoVFNCVT_F_X_W_MF4_E16
Definition riscv/opcodes.hpp:2487
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_M1
@ PseudoVSSEG5E32_V_M1
Definition riscv/opcodes.hpp:10089
LIEF::assembly::riscv::OPCODE::VADC_VIM
@ VADC_VIM
Definition riscv/opcodes.hpp:13135
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M2_E16_MASK
@ PseudoVFMACC_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:1940
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF2_M1
@ PseudoVSOXSEG6EI8_V_MF2_M1
Definition riscv/opcodes.hpp:9653
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_MF2
@ PseudoVAESDF_VS_M2_MF2
Definition riscv/opcodes.hpp:646
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_MF2_E32_MASK
@ PseudoVFSUB_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3448
LIEF::assembly::riscv::OPCODE::VSUXSEG5EI64_V
@ VSUXSEG5EI64_V
Definition riscv/opcodes.hpp:13788
LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VX_M_T
@ PseudoVMSGE_VX_M_T
Definition riscv/opcodes.hpp:7008
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_MF2_E16_MASK
@ PseudoVFSGNJ_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3250
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF8_MASK
@ PseudoVAND_VV_MF8_MASK
Definition riscv/opcodes.hpp:845
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_M1_MASK
@ PseudoVLOXEI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4259
LIEF::assembly::riscv::OPCODE::AMOAND_B_RL
@ AMOAND_B_RL
Definition riscv/opcodes.hpp:11966
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E8
@ PseudoVDIVU_VX_M8_E8
Definition riscv/opcodes.hpp:1497
LIEF::assembly::riscv::OPCODE::CLZW
@ CLZW
Definition riscv/opcodes.hpp:12142
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_MF2
@ PseudoVLUXEI8_V_MF2_MF2
Definition riscv/opcodes.hpp:5708
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E16_MASK
@ PseudoVFREDUSUM_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:3044
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M2
@ PseudoVNSRA_WI_M2
Definition riscv/opcodes.hpp:7556
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF2_MASK
@ PseudoVMFEQ_VFPR16_MF2_MASK
Definition riscv/opcodes.hpp:6607
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M2_MASK
@ PseudoVFCVT_RTZ_X_F_V_M2_MASK
Definition riscv/opcodes.hpp:1830
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M4_MASK
@ PseudoVRSUB_VX_M4_MASK
Definition riscv/opcodes.hpp:8595
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF2
@ PseudoVCLMUL_VV_MF2
Definition riscv/opcodes.hpp:980
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E32
@ PseudoVFWMSAC_VV_M2_E32
Definition riscv/opcodes.hpp:3791
LIEF::assembly::riscv::OPCODE::VSUXSEG3EI64_V
@ VSUXSEG3EI64_V
Definition riscv/opcodes.hpp:13780
LIEF::assembly::riscv::OPCODE::TH_SBIB
@ TH_SBIB
Definition riscv/opcodes.hpp:13103
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M2_MASK
@ PseudoVSUXSEG3EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10804
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF2_MASK
@ PseudoVLUXSEG2EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:5757
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF8
@ PseudoVWMACCSU_VV_MF8
Definition riscv/opcodes.hpp:11465
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M1_MASK
@ PseudoVLUXSEG3EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:5957
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_M1
@ PseudoVC_V_VVW_SE_M1
Definition riscv/opcodes.hpp:1322
LIEF::assembly::riscv::OPCODE::CV_ADDNR
@ CV_ADDNR
Definition riscv/opcodes.hpp:12165
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF4_E16_MASK
@ PseudoVREDMINU_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:7871
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E64_MASK
@ PseudoVFMIN_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:2179
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_M1
@ PseudoVSSSEG8E32_V_M1
Definition riscv/opcodes.hpp:10405
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_M1
@ PseudoVLSSEG5E32_V_M1
Definition riscv/opcodes.hpp:5496
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M2
@ PseudoVWSUBU_VV_M2
Definition riscv/opcodes.hpp:11721
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF4_MASK
@ PseudoVLE8_V_MF4_MASK
Definition riscv/opcodes.hpp:4168
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_MF2_MASK
@ PseudoVSUXSEG4EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10998
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M4_M8_MASK
@ PseudoVSOXEI16_V_M4_M8_MASK
Definition riscv/opcodes.hpp:9020
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M4
@ PseudoVLUXSEG2EI32_V_M4_M4
Definition riscv/opcodes.hpp:5782
LIEF::assembly::riscv::OPCODE::AMOAND_H
@ AMOAND_H
Definition riscv/opcodes.hpp:11971
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_MF2
@ PseudoVLOXSEG6EI32_V_M2_MF2
Definition riscv/opcodes.hpp:4798
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E16_MASK
@ PseudoVFWCVTBF16_F_F_V_M1_E16_MASK
Definition riscv/opcodes.hpp:3542
LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M1
@ PseudoVLE64_V_M1
Definition riscv/opcodes.hpp:4135
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_MF2_MASK
@ PseudoVSOXSEG8EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:9808
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_MF2
@ PseudoVSOXSEG8EI16_V_M1_MF2
Definition riscv/opcodes.hpp:9753
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_M1_MASK
@ PseudoVSOXSEG5EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:9584
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_M1_MASK
@ PseudoVSOXSEG5EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9538
LIEF::assembly::riscv::OPCODE::VFWMUL_VV
@ VFWMUL_VV
Definition riscv/opcodes.hpp:13292
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M4_E64
@ PseudoVFADD_VFPR64_M4_E64
Definition riscv/opcodes.hpp:1625
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E8_MASK
@ PseudoVRGATHER_VV_MF2_E8_MASK
Definition riscv/opcodes.hpp:8485
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_M1
@ PseudoVLUXSEG5EI64_V_M4_M1
Definition riscv/opcodes.hpp:6136
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M2_MASK
@ PseudoVSOXEI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:9066
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E32_MASK
@ PseudoVDIVU_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:1458
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF2
@ PseudoVLOXSEG3EI32_V_M1_MF2
Definition riscv/opcodes.hpp:4502
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF2_MASK
@ PseudoVLOXEI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4271
LIEF::assembly::riscv::OPCODE::VAESDM_VV
@ VAESDM_VV
Definition riscv/opcodes.hpp:13144
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E32_MASK
@ PseudoVFREDUSUM_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:3046
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF8
@ PseudoVSMUL_VX_MF8
Definition riscv/opcodes.hpp:8990
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B1
@ PseudoVMSOF_M_B1
Definition riscv/opcodes.hpp:7263
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M8
@ PseudoVMAX_VV_M8
Definition riscv/opcodes.hpp:6548
LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_M4
@ PseudoVMNOR_MM_M4
Definition riscv/opcodes.hpp:6891
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M2_M2
@ PseudoVSUXSEG3EI8_V_M2_M2
Definition riscv/opcodes.hpp:10881
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF4_MASK
@ PseudoVSRL_VX_MF4_MASK
Definition riscv/opcodes.hpp:9944
LIEF::assembly::riscv::OPCODE::G_FLOG
@ G_FLOG
Definition riscv/opcodes.hpp:208
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_M1
@ PseudoVSSEG8E32_V_M1
Definition riscv/opcodes.hpp:10149
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E16_MASK
@ PseudoVREDSUM_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:7965
LIEF::assembly::riscv::OPCODE::C_LHU
@ C_LHU
Definition riscv/opcodes.hpp:12505
LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_H
@ PseudoQuietFLT_H
Definition riscv/opcodes.hpp:428
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E64
@ PseudoVREDAND_VS_M1_E64
Definition riscv/opcodes.hpp:7704
LIEF::assembly::riscv::OPCODE::CV_CPLXCONJ
@ CV_CPLXCONJ
Definition riscv/opcodes.hpp:12272
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF8_MASK
@ PseudoVSSUB_VV_MF8_MASK
Definition riscv/opcodes.hpp:10460
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF4_MASK
@ PseudoVSOXSEG6EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:9644
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF8_MASK
@ PseudoVSUXEI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:10544
LIEF::assembly::riscv::OPCODE::FCVT_D_LU_INX
@ FCVT_D_LU_INX
Definition riscv/opcodes.hpp:12579
LIEF::assembly::riscv::OPCODE::CV_MULURN
@ CV_MULURN
Definition riscv/opcodes.hpp:12378
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M1
@ PseudoVXOR_VI_M1
Definition riscv/opcodes.hpp:11839
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M1
@ PseudoVASUB_VX_M1
Definition riscv/opcodes.hpp:902
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E16
@ PseudoVFWREDOSUM_VS_M2_E16
Definition riscv/opcodes.hpp:3915
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M2
@ PseudoVLSEG4E64_V_M2
Definition riscv/opcodes.hpp:5216
LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M4
@ PseudoVLE32FF_V_M4
Definition riscv/opcodes.hpp:4111
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M4_E32
@ PseudoVFWSUB_WFPR32_M4_E32
Definition riscv/opcodes.hpp:4005
LIEF::assembly::riscv::OPCODE::TH_FSURW
@ TH_FSURW
Definition riscv/opcodes.hpp:13053
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_M1
@ PseudoVSUXSEG2EI8_V_MF4_M1
Definition riscv/opcodes.hpp:10779
LIEF::assembly::riscv::OPCODE::G_FRAME_INDEX
@ G_FRAME_INDEX
Definition riscv/opcodes.hpp:89
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF2_MASK
@ PseudoVLUXSEG3EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:5879
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_MF4
@ PseudoVMV_V_V_MF4
Definition riscv/opcodes.hpp:7402
LIEF::assembly::riscv::OPCODE::FCLASS_D
@ FCLASS_D
Definition riscv/opcodes.hpp:12565
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF8
@ PseudoVLSEG2E8FF_V_MF8
Definition riscv/opcodes.hpp:5112
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF2_MASK
@ PseudoVLSSEG8E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5553
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF4_MASK
@ PseudoVMAX_VV_MF4_MASK
Definition riscv/opcodes.hpp:6553
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M2
@ PseudoVSOXEI8_V_MF2_M2
Definition riscv/opcodes.hpp:9133
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M1
@ PseudoVWSLL_VI_M1
Definition riscv/opcodes.hpp:11683
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M4_MASK
@ PseudoVSSRA_VV_M4_MASK
Definition riscv/opcodes.hpp:10182
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF4_MASK
@ PseudoVLOXSEG4EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4681
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E64_MASK
@ PseudoVREDAND_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:7729
LIEF::assembly::riscv::OPCODE::CV_EXTRACT
@ CV_EXTRACT
Definition riscv/opcodes.hpp:12304
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK
@ PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK
Definition riscv/opcodes.hpp:3312
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF4_E16_MASK
@ PseudoVFDIV_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:1922
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_MF2
@ PseudoVSOXSEG4EI16_V_M1_MF2
Definition riscv/opcodes.hpp:9405
LIEF::assembly::riscv::OPCODE::VWSLL_VV
@ VWSLL_VV
Definition riscv/opcodes.hpp:13828
LIEF::assembly::riscv::OPCODE::MAXU
@ MAXU
Definition riscv/opcodes.hpp:12857
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_M1
@ PseudoVLOXSEG8EI32_V_M2_M1
Definition riscv/opcodes.hpp:4956
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M4_MASK
@ PseudoVMFGE_VFPR64_M4_MASK
Definition riscv/opcodes.hpp:6667
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M1_MASK
@ PseudoVLSEG3E32_V_M1_MASK
Definition riscv/opcodes.hpp:5149
LIEF::assembly::riscv::OPCODE::TH_MULSH
@ TH_MULSH
Definition riscv/opcodes.hpp:13096
LIEF::assembly::riscv::OPCODE::CV_CMPLE_SCI_H
@ CV_CMPLE_SCI_H
Definition riscv/opcodes.hpp:12250
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF8_E8
@ PseudoVDIV_VV_MF8_E8
Definition riscv/opcodes.hpp:1553
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF8
@ PseudoVSADDU_VV_MF8
Definition riscv/opcodes.hpp:8630
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M4
@ PseudoVCLMUL_VX_M4
Definition riscv/opcodes.hpp:990
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M2_MASK
@ PseudoVFCVT_XU_F_V_M2_MASK
Definition riscv/opcodes.hpp:1842
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E16_MASK
@ PseudoVREDMIN_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:7877
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF4_E16
@ PseudoVFDIV_VV_MF4_E16
Definition riscv/opcodes.hpp:1921
LIEF::assembly::riscv::OPCODE::PseudoFLW
@ PseudoFLW
Definition riscv/opcodes.hpp:373
LIEF::assembly::riscv::OPCODE::C_ADD_HINT
@ C_ADD_HINT
Definition riscv/opcodes.hpp:12483
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M2
@ PseudoVBREV8_V_M2
Definition riscv/opcodes.hpp:918
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M2_M2
@ PseudoVLOXSEG4EI8_V_M2_M2
Definition riscv/opcodes.hpp:4666
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M8_MASK
@ PseudoVSE8_V_M8_MASK
Definition riscv/opcodes.hpp:8739
LIEF::assembly::riscv::OPCODE::SHA256SIG1
@ SHA256SIG1
Definition riscv/opcodes.hpp:12966
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF4_E16_MASK
@ PseudoVFMSUB_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:2311
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M4_E16_MASK
@ PseudoVFNMSAC_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2740
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF4
@ PseudoVSUXSEG3EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:10847
LIEF::assembly::riscv::OPCODE::VSOXSEG6EI8_V
@ VSOXSEG6EI8_V
Definition riscv/opcodes.hpp:13683
LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VX_M_T
@ PseudoVMSGEU_VX_M_T
Definition riscv/opcodes.hpp:7004
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_MF2
@ PseudoVSSEG2E32_V_MF2
Definition riscv/opcodes.hpp:10007
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_MF2
@ PseudoVROL_VV_MF2
Definition riscv/opcodes.hpp:8514
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF8
@ PseudoVCLMUL_VX_MF8
Definition riscv/opcodes.hpp:998
LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_MF2
@ PseudoVC_VVW_SE_MF2
Definition riscv/opcodes.hpp:1156
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M2_E32
@ PseudoVFNCVT_RM_F_X_W_M2_E32
Definition riscv/opcodes.hpp:2513
LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_M4
@ PseudoVMXNOR_MM_M4
Definition riscv/opcodes.hpp:7414
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E16
@ PseudoVFNMSUB_VV_M2_E16
Definition riscv/opcodes.hpp:2831
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E16_MASK
@ PseudoVFNMSAC_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:2772
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M8_M2
@ PseudoVSUXSEG3EI32_V_M8_M2
Definition riscv/opcodes.hpp:10841
LIEF::assembly::riscv::OPCODE::VAESKF2_VI
@ VAESKF2_VI
Definition riscv/opcodes.hpp:13150
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M2_MASK
@ PseudoVMUL_VX_M2_MASK
Definition riscv/opcodes.hpp:7378
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E16
@ PseudoVDIV_VV_M8_E16
Definition riscv/opcodes.hpp:1535
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_M1_M1
@ PseudoVSUXSEG5EI8_V_M1_M1
Definition riscv/opcodes.hpp:11075
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E32
@ PseudoVREDMINU_VS_M8_E32
Definition riscv/opcodes.hpp:7858
LIEF::assembly::riscv::OPCODE::TH_DCACHE_CIVA
@ TH_DCACHE_CIVA
Definition riscv/opcodes.hpp:13032
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M1_MASK
@ PseudoVSUXSEG4EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10912
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M1
@ PseudoVLSEG3E32FF_V_M1
Definition riscv/opcodes.hpp:5142
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF2
@ PseudoVLOXSEG5EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:4724
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E32
@ PseudoVFMACC_VV_M2_E32
Definition riscv/opcodes.hpp:1975
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M2_MASK
@ PseudoVSOXSEG2EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:9270
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF4_MASK
@ PseudoVLSEG4E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5197
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF4_E16
@ PseudoVFMSUB_VV_MF4_E16
Definition riscv/opcodes.hpp:2310
LIEF::assembly::riscv::OPCODE::G_BUILD_VECTOR
@ G_BUILD_VECTOR
Definition riscv/opcodes.hpp:97
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E64
@ PseudoVFMIN_VV_M8_E64
Definition riscv/opcodes.hpp:2184
LIEF::assembly::riscv::OPCODE::VFWMACC_4x4x4
@ VFWMACC_4x4x4
Definition riscv/opcodes.hpp:13286
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF2
@ PseudoVSUXSEG3EI64_V_M1_MF2
Definition riscv/opcodes.hpp:10853
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF4_E16
@ PseudoVFWMACC_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3739
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E16_MASK
@ PseudoVREDOR_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:7937
LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_D
@ PseudoQuietFLE_D
Definition riscv/opcodes.hpp:418
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E32_MASK
@ PseudoVREDAND_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:7735
LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_MF8
@ PseudoVC_XVW_SE_MF8
Definition riscv/opcodes.hpp:1408
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E32
@ PseudoVFWCVT_F_F_V_M1_E32
Definition riscv/opcodes.hpp:3561
LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_M8
@ PseudoVC_VVV_SE_M8
Definition riscv/opcodes.hpp:1149
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF4_MASK
@ PseudoVSLL_VI_MF4_MASK
Definition riscv/opcodes.hpp:8889
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF8
@ PseudoVMSEQ_VI_MF8
Definition riscv/opcodes.hpp:6964
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_MF2_MASK
@ PseudoVLUXSEG5EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:6139
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF2_MASK
@ PseudoVMSLE_VX_MF2_MASK
Definition riscv/opcodes.hpp:7158
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_M1
@ PseudoVSUXSEG5EI8_V_MF4_M1
Definition riscv/opcodes.hpp:11081
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF2
@ PseudoVLUXSEG6EI64_V_M1_MF2
Definition riscv/opcodes.hpp:6204
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF4_MASK
@ PseudoVLOXSEG4EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:4651
LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_MF2
@ PseudoVGHSH_VV_MF2
Definition riscv/opcodes.hpp:4049
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32_MASK
@ PseudoVFWSUB_WV_M1_E32_MASK
Definition riscv/opcodes.hpp:4014
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M2_MASK
@ PseudoVMULH_VV_M2_MASK
Definition riscv/opcodes.hpp:7336
LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M1_MASK
@ PseudoVLE64_V_M1_MASK
Definition riscv/opcodes.hpp:4136
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_MF4_E16_MASK
@ PseudoVFREC7_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:2934
LIEF::assembly::riscv::OPCODE::FMADD_S
@ FMADD_S
Definition riscv/opcodes.hpp:12691
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M8_MASK
@ PseudoVMFLT_VV_M8_MASK
Definition riscv/opcodes.hpp:6779
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E32
@ PseudoVFSQRT_V_M4_E32
Definition riscv/opcodes.hpp:3375
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_MF4
@ PseudoVSM4R_VS_M8_MF4
Definition riscv/opcodes.hpp:8954
LIEF::assembly::riscv::OPCODE::GC_LABEL
@ GC_LABEL
Definition riscv/opcodes.hpp:29
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E32_MASK
@ PseudoVFMACC_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:1970
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M2
@ PseudoVLSSEG4E16_V_M2
Definition riscv/opcodes.hpp:5464
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF4
@ PseudoVLUXSEG8EI32_V_M1_MF4
Definition riscv/opcodes.hpp:6346
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M4_MASK
@ PseudoVLSEG2E32FF_V_M4_MASK
Definition riscv/opcodes.hpp:5079
LIEF::assembly::riscv::OPCODE::VC_IVW
@ VC_IVW
Definition riscv/opcodes.hpp:13178
LIEF::assembly::riscv::OPCODE::MOPRR4
@ MOPRR4
Definition riscv/opcodes.hpp:12896
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E64_MASK
@ PseudoVREDMAXU_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:7749
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M1_MASK
@ PseudoTHVdotVMAQA_VV_M1_MASK
Definition riscv/opcodes.hpp:501
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M2_MASK
@ PseudoVMSGTU_VI_M2_MASK
Definition riscv/opcodes.hpp:7012
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M8
@ PseudoVASUBU_VV_M8
Definition riscv/opcodes.hpp:866
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M4_MASK
@ PseudoVFWCVT_RTZ_X_F_V_M4_MASK
Definition riscv/opcodes.hpp:3672
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_MF2
@ PseudoVSOXSEG3EI64_V_M4_MF2
Definition riscv/opcodes.hpp:9367
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF4_MASK
@ PseudoVMULHU_VV_MF4_MASK
Definition riscv/opcodes.hpp:7316
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_MF2
@ PseudoVRGATHEREI16_VV_M2_E64_MF2
Definition riscv/opcodes.hpp:8328
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK
@ PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK
Definition riscv/opcodes.hpp:8329
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E16_MASK
@ PseudoVREDOR_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:7959
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF2_MASK
@ PseudoVWSUBU_WV_MF2_MASK
Definition riscv/opcodes.hpp:11756
LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_D_INX
@ PseudoQuietFLT_D_INX
Definition riscv/opcodes.hpp:427
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_MF2
@ PseudoVMV_V_V_MF2
Definition riscv/opcodes.hpp:7401
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF4
@ PseudoVWSUBU_VX_MF4
Definition riscv/opcodes.hpp:11739
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_M1
@ PseudoVC_V_VVV_SE_M1
Definition riscv/opcodes.hpp:1309
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_MF2
@ PseudoVLUXSEG7EI32_V_M2_MF2
Definition riscv/opcodes.hpp:6270
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF8_MASK
@ PseudoVSADD_VX_MF8_MASK
Definition riscv/opcodes.hpp:8687
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK
@ PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK
Definition riscv/opcodes.hpp:8423
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF4
@ PseudoVWMACC_VV_MF4
Definition riscv/opcodes.hpp:11523
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M1_MASK
@ PseudoVSMUL_VX_M1_MASK
Definition riscv/opcodes.hpp:8979
LIEF::assembly::riscv::OPCODE::TH_LRWU
@ TH_LRWU
Definition riscv/opcodes.hpp:13078
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M4_E64_MASK
@ PseudoVFADD_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:1626
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_M1
@ PseudoVSOXSEG7EI64_V_M2_M1
Definition riscv/opcodes.hpp:9719
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M4_MASK
@ PseudoVRGATHEREI16_VV_M4_E64_M4_MASK
Definition riscv/opcodes.hpp:8359
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M4
@ PseudoVWMACCU_VX_M4
Definition riscv/opcodes.hpp:11507
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF4_MASK
@ PseudoVSSSEG8E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10416
LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_M4
@ PseudoVC_IVW_SE_M4
Definition riscv/opcodes.hpp:1128
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E32_MASK
@ PseudoVFNCVTBF16_F_F_W_M2_E32_MASK
Definition riscv/opcodes.hpp:2424
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF2
@ PseudoVSUXSEG8EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:11329
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E32
@ PseudoVREDMAX_VS_M2_E32
Definition riscv/opcodes.hpp:7798
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF8_MASK
@ PseudoVADD_VX_MF8_MASK
Definition riscv/opcodes.hpp:639
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M4_E64_MASK
@ PseudoVFSUB_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:3418
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF2
@ PseudoVSUXSEG2EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:10783
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M1_MASK
@ PseudoVSLIDEUP_VI_M1_MASK
Definition riscv/opcodes.hpp:8851
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E16_MASK
@ PseudoVRGATHER_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:8473
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M4_E32_MASK
@ PseudoVFNMSUB_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2812
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E16
@ PseudoVWREDSUM_VS_M1_E16
Definition riscv/opcodes.hpp:11647
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E64
@ PseudoVFREDMIN_VS_M2_E64
Definition riscv/opcodes.hpp:2975
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M2_E64_MASK
@ PseudoVFRSUB_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:3116
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M1
@ PseudoVLOXSEG3EI64_V_M4_M1
Definition riscv/opcodes.hpp:4542
LIEF::assembly::riscv::OPCODE::PseudoRVVInitUndefM4
@ PseudoRVVInitUndefM4
Definition riscv/opcodes.hpp:437
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E8_MASK
@ PseudoVREDMAXU_VS_MF2_E8_MASK
Definition riscv/opcodes.hpp:7781
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF2_MASK
@ PseudoVLSEG4E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5195
LIEF::assembly::riscv::OPCODE::VSSRL_VI
@ VSSRL_VI
Definition riscv/opcodes.hpp:13733
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF2_MASK
@ PseudoVLOXSEG7EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:4925
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M8_E64_MASK
@ PseudoVFMUL_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2341
LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M2_MASK
@ PseudoVSSE64_V_M2_MASK
Definition riscv/opcodes.hpp:9972
LIEF::assembly::riscv::OPCODE::VSUXEI8_V
@ VSUXEI8_V
Definition riscv/opcodes.hpp:13773
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M4_MASK
@ PseudoVSSRA_VI_M4_MASK
Definition riscv/opcodes.hpp:10168
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M2
@ PseudoVMFNE_VFPR32_M2
Definition riscv/opcodes.hpp:6798
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF2
@ PseudoVMSGTU_VI_MF2
Definition riscv/opcodes.hpp:7017
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF4_MASK
@ PseudoVADD_VX_MF4_MASK
Definition riscv/opcodes.hpp:637
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M1
@ PseudoVNSRA_WI_M1
Definition riscv/opcodes.hpp:7554
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF2
@ PseudoVSUXSEG8EI64_V_M1_MF2
Definition riscv/opcodes.hpp:11297
LIEF::assembly::riscv::OPCODE::VSOXEI32_V
@ VSOXEI32_V
Definition riscv/opcodes.hpp:13661
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M1_MASK
@ PseudoVLE8_V_M1_MASK
Definition riscv/opcodes.hpp:4158
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF2_E16_MASK
@ PseudoVFSGNJX_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3190
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M4_MASK
@ PseudoVSOXEI16_V_M2_M4_MASK
Definition riscv/opcodes.hpp:9012
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M1_MASK
@ PseudoVRGATHEREI16_VV_M1_E32_M1_MASK
Definition riscv/opcodes.hpp:8283
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M1
@ PseudoVSOXSEG2EI16_V_M1_M1
Definition riscv/opcodes.hpp:9155
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M4_M1_MASK
@ PseudoVLOXSEG5EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4745
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_MF2
@ PseudoVRELOAD7_MF2
Definition riscv/opcodes.hpp:8077
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF2_E16
@ PseudoVFNMACC_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2623
LIEF::assembly::riscv::OPCODE::FSW
@ FSW
Definition riscv/opcodes.hpp:12793
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M2_MASK
@ PseudoVWADD_VV_M2_MASK
Definition riscv/opcodes.hpp:11398
LIEF::assembly::riscv::OPCODE::CV_SLL_H
@ CV_SLL_H
Definition riscv/opcodes.hpp:12426
LIEF::assembly::riscv::OPCODE::VREMU_VX
@ VREMU_VX
Definition riscv/opcodes.hpp:13603
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_M1
@ PseudoVC_V_FPR16V_SE_M1
Definition riscv/opcodes.hpp:1196
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_MF2_E32_MASK
@ PseudoVFNMSUB_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2816
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF2
@ PseudoVLUXSEG6EI64_V_M2_MF2
Definition riscv/opcodes.hpp:6212
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF8_MASK
@ PseudoVLSEG2E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5125
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E16
@ PseudoVFWCVT_F_X_V_M2_E16
Definition riscv/opcodes.hpp:3613
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF8
@ PseudoVMAXU_VV_MF8
Definition riscv/opcodes.hpp:6526
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E64_V_M1_MASK
@ PseudoVLSSEG8E64_V_M1_MASK
Definition riscv/opcodes.hpp:5561
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M4
@ PseudoVMUL_VV_M4
Definition riscv/opcodes.hpp:7365
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF2
@ PseudoVSOXSEG2EI64_V_M1_MF2
Definition riscv/opcodes.hpp:9227
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M1
@ PseudoVANDN_VX_M1
Definition riscv/opcodes.hpp:804
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF2_MASK
@ PseudoVFCLASS_V_MF2_MASK
Definition riscv/opcodes.hpp:1668
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF4
@ PseudoVLSEG4E8_V_MF4
Definition riscv/opcodes.hpp:5234
LIEF::assembly::riscv::OPCODE::INSTRUCTION_LIST_END
@ INSTRUCTION_LIST_END
Definition riscv/opcodes.hpp:13855
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF8
@ PseudoVWMULSU_VX_MF8
Definition riscv/opcodes.hpp:11561
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF4_MASK
@ PseudoVLUXSEG6EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:6179
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E8_MASK
@ PseudoVREDMAXU_VS_M1_E8_MASK
Definition riscv/opcodes.hpp:7751
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E16_MASK
@ PseudoVFMIN_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:2169
LIEF::assembly::riscv::OPCODE::VWADD_VX
@ VWADD_VX
Definition riscv/opcodes.hpp:13809
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E16
@ PseudoVFCVT_F_X_V_M8_E16
Definition riscv/opcodes.hpp:1719
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32V_SE_M1
@ PseudoVC_FPR32V_SE_M1
Definition riscv/opcodes.hpp:1106
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E16_MASK
@ PseudoVFNMADD_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:2712
LIEF::assembly::riscv::OPCODE::AMOMINU_H
@ AMOMINU_H
Definition riscv/opcodes.hpp:12043
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M2_E16
@ PseudoVFWREDUSUM_VS_M2_E16
Definition riscv/opcodes.hpp:3937
LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M4_MASK
@ PseudoVLSE64_V_M4_MASK
Definition riscv/opcodes.hpp:5037
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M1_MASK
@ PseudoVLSSEG2E64_V_M1_MASK
Definition riscv/opcodes.hpp:5417
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF4_E16_MASK
@ PseudoVFREDUSUM_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:3054
LIEF::assembly::riscv::OPCODE::SC_D_AQ_RL
@ SC_D_AQ_RL
Definition riscv/opcodes.hpp:12941
LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I
@ CV_CPLXMUL_I
Definition riscv/opcodes.hpp:12273
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M1_MASK
@ PseudoTHVdotVMAQA_VX_M1_MASK
Definition riscv/opcodes.hpp:511
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M2_MASK
@ PseudoVSOXEI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9052
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E32_MASK
@ PseudoVDIVU_VX_M1_E32_MASK
Definition riscv/opcodes.hpp:1470
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M1
@ PseudoVMFGT_VFPR32_M1
Definition riscv/opcodes.hpp:6682
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E16_MASK
@ PseudoVFNMSUB_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:2832
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_M1_MASK
@ PseudoVLSSEG6E32_V_M1_MASK
Definition riscv/opcodes.hpp:5517
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E32
@ PseudoVFREDMIN_VS_M8_E32
Definition riscv/opcodes.hpp:2985
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_M2
@ PseudoVC_V_XVW_M2
Definition riscv/opcodes.hpp:1357
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E16_MASK
@ PseudoVFSGNJN_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3164
LIEF::assembly::riscv::OPCODE::VLOXEI64_V
@ VLOXEI64_V
Definition riscv/opcodes.hpp:13334
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_MF2
@ PseudoVLOXSEG6EI64_V_M4_MF2
Definition riscv/opcodes.hpp:4826
LIEF::assembly::riscv::OPCODE::G_IS_FPCLASS
@ G_IS_FPCLASS
Definition riscv/opcodes.hpp:222
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M2
@ PseudoVLUXSEG2EI8_V_MF4_M2
Definition riscv/opcodes.hpp:5848
LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SC_B
@ CV_SDOTUP_SC_B
Definition riscv/opcodes.hpp:12403
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF8
@ PseudoVLOXSEG2EI64_V_M1_MF8
Definition riscv/opcodes.hpp:4410
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF2_MASK
@ PseudoVLSEG7E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5353
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E8
@ PseudoVREDMAX_VS_MF2_E8
Definition riscv/opcodes.hpp:7824
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF8
@ PseudoVMSNE_VV_MF8
Definition riscv/opcodes.hpp:7247
LIEF::assembly::riscv::OPCODE::CV_SUBUN
@ CV_SUBUN
Definition riscv/opcodes.hpp:12451
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF2_MASK
@ PseudoVSUXSEG3EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10812
LIEF::assembly::riscv::OPCODE::VFNMSUB_VF
@ VFNMSUB_VF
Definition riscv/opcodes.hpp:13249
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_M2
@ PseudoVC_V_XVV_M2
Definition riscv/opcodes.hpp:1343
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B16_MASK
@ PseudoVFIRST_M_B16_MASK
Definition riscv/opcodes.hpp:1925
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_MF2
@ PseudoVSUXSEG2EI16_V_M1_MF2
Definition riscv/opcodes.hpp:10665
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M8_E32_MASK
@ PseudoVFNMACC_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2634
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4_TIED
@ PseudoVWSUB_WV_MF4_TIED
Definition riscv/opcodes.hpp:11822
LIEF::assembly::riscv::OPCODE::MOPR24
@ MOPR24
Definition riscv/opcodes.hpp:12877
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E16_MASK
@ PseudoVFCVT_RM_F_X_V_M4_E16_MASK
Definition riscv/opcodes.hpp:1774
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M4_E64_MASK
@ PseudoVFRDIV_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2902
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M4_MASK
@ PseudoVMSLE_VI_M4_MASK
Definition riscv/opcodes.hpp:7126
LIEF::assembly::riscv::OPCODE::PseudoLB
@ PseudoLB
Definition riscv/opcodes.hpp:390
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF8
@ PseudoVLUXSEG6EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:6180
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF2
@ PseudoVSSEG7E8_V_MF2
Definition riscv/opcodes.hpp:10137
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E16_MASK
@ PseudoVFREDOSUM_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:2996
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M1_MASK
@ PseudoVMULHU_VV_M1_MASK
Definition riscv/opcodes.hpp:7306
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_M1_MASK
@ PseudoVLUXSEG6EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6203
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF2
@ PseudoVLSEG7E8FF_V_MF2
Definition riscv/opcodes.hpp:5344
LIEF::assembly::riscv::OPCODE::FCVT_S_L
@ FCVT_S_L
Definition riscv/opcodes.hpp:12621
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M8_MASK
@ PseudoVSLL_VV_M8_MASK
Definition riscv/opcodes.hpp:8899
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1
@ PseudoVWADD_WV_M1
Definition riscv/opcodes.hpp:11419
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M8
@ PseudoVSOXEI32_V_M8_M8
Definition riscv/opcodes.hpp:9069
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E64_MASK
@ PseudoVFREDMIN_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:2982
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF2
@ PseudoVIOTA_M_MF2
Definition riscv/opcodes.hpp:4077
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF8
@ PseudoVLUXSEG2EI64_V_M1_MF8
Definition riscv/opcodes.hpp:5802
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M1_MASK
@ PseudoVSSE8_V_M1_MASK
Definition riscv/opcodes.hpp:9978
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M2
@ PseudoVRSUB_VX_M2
Definition riscv/opcodes.hpp:8592
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_M1
@ PseudoVSUXEI16_V_MF4_M1
Definition riscv/opcodes.hpp:10537
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF8
@ PseudoVSUB_VX_MF8
Definition riscv/opcodes.hpp:10501
LIEF::assembly::riscv::OPCODE::G_FPEXT
@ G_FPEXT
Definition riscv/opcodes.hpp:214
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M1_MASK
@ PseudoVMADD_VX_M1_MASK
Definition riscv/opcodes.hpp:6487
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M8_M8
@ PseudoVSUXEI8_V_M8_M8
Definition riscv/opcodes.hpp:10633
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E8_MASK
@ PseudoVWREDSUMU_VS_M4_E8_MASK
Definition riscv/opcodes.hpp:11628
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M1_E64_MASK
@ PseudoVFSGNJN_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:3144
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M2
@ PseudoVWMUL_VX_M2
Definition riscv/opcodes.hpp:11601
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M1_E64
@ PseudoVFNMSUB_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2817
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M1
@ PseudoVSSUB_VV_M1
Definition riscv/opcodes.hpp:10447
LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_MF4
@ PseudoVSPILL2_MF4
Definition riscv/opcodes.hpp:9835
LIEF::assembly::riscv::OPCODE::VLOXSEG7EI8_V
@ VLOXSEG7EI8_V
Definition riscv/opcodes.hpp:13359
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M1
@ PseudoVSOXSEG3EI8_V_MF4_M1
Definition riscv/opcodes.hpp:9385
LIEF::assembly::riscv::OPCODE::VFSUB_VF
@ VFSUB_VF
Definition riscv/opcodes.hpp:13270
LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M2_MASK
@ PseudoVSE64_V_M2_MASK
Definition riscv/opcodes.hpp:8727
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_MF2_MASK
@ PseudoVSSSEG7E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10388
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_M2_MASK
@ PseudoVLUXSEG4EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:6063
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E16
@ PseudoVDIVU_VV_MF2_E16
Definition riscv/opcodes.hpp:1455
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E16
@ PseudoVFNCVT_F_F_W_M2_E16
Definition riscv/opcodes.hpp:2439
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M1_MASK
@ PseudoVRGATHEREI16_VV_M4_E8_M1_MASK
Definition riscv/opcodes.hpp:8363
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M1_MASK
@ PseudoVSSRA_VV_M1_MASK
Definition riscv/opcodes.hpp:10178
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M1
@ PseudoVSADDU_VX_M1
Definition riscv/opcodes.hpp:8632
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E64
@ PseudoVFMACC_VV_M2_E64
Definition riscv/opcodes.hpp:1977
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M2_MASK
@ PseudoVSOXEI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9044
LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_M2
@ PseudoVC_I_SE_M2
Definition riscv/opcodes.hpp:1140
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_MF2
@ PseudoVAESDM_VS_M2_MF2
Definition riscv/opcodes.hpp:675
LIEF::assembly::riscv::OPCODE::AES64KS2
@ AES64KS2
Definition riscv/opcodes.hpp:11946
LIEF::assembly::riscv::OPCODE::VLUXSEG5EI64_V
@ VLUXSEG5EI64_V
Definition riscv/opcodes.hpp:13470
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF2_MASK
@ PseudoVLOXSEG3EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4493
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_MF2
@ PseudoVSADDU_VX_MF2
Definition riscv/opcodes.hpp:8640
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M8
@ PseudoVSLIDEUP_VX_M8
Definition riscv/opcodes.hpp:8870
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_MF4
@ PseudoVSUXSEG3EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:10813
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_M1
@ PseudoVSUXSEG7EI8_V_MF8_M1
Definition riscv/opcodes.hpp:11247
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_MF2_MASK
@ PseudoVFSLIDE1UP_VFPR32_MF2_MASK
Definition riscv/opcodes.hpp:3352
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_MF2
@ PseudoVSSEG8E32_V_MF2
Definition riscv/opcodes.hpp:10151
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M8
@ PseudoTHVdotVMAQA_VX_M8
Definition riscv/opcodes.hpp:516
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_MF2
@ PseudoVSOXSEG4EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:9493
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_MF2_E32
@ PseudoVFMAX_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2077
LIEF::assembly::riscv::OPCODE::AMOMAX_D
@ AMOMAX_D
Definition riscv/opcodes.hpp:12023
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_MF4
@ PseudoVRELOAD3_MF4
Definition riscv/opcodes.hpp:8061
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E64_MASK
@ PseudoVREDMAXU_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:7757
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M2_MASK_TIED
@ PseudoVWADDU_WV_M2_MASK_TIED
Definition riscv/opcodes.hpp:11365
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M8_M1
@ PseudoVLOXSEG3EI64_V_M8_M1
Definition riscv/opcodes.hpp:4548
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK
@ PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK
Definition riscv/opcodes.hpp:3322
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_M1
@ PseudoVLUXSEG6EI64_V_M4_M1
Definition riscv/opcodes.hpp:6216
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF2_MASK
@ PseudoVMSEQ_VX_MF2_MASK
Definition riscv/opcodes.hpp:6989
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF4_MASK
@ PseudoVSSRL_VX_MF4_MASK
Definition riscv/opcodes.hpp:10244
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF4_E16
@ PseudoVFMACC_VV_MF4_E16
Definition riscv/opcodes.hpp:1995
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF2_MASK
@ PseudoVLOXSEG3EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4503
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4_TIED
@ PseudoVWADDU_WV_MF4_TIED
Definition riscv/opcodes.hpp:11378
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF2_MASK
@ PseudoVLUXSEG4EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:5989
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF8_MASK
@ PseudoVSRA_VV_MF8_MASK
Definition riscv/opcodes.hpp:9890
LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SC_H
@ CV_SDOTUP_SC_H
Definition riscv/opcodes.hpp:12404
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_MF2
@ PseudoVSOXSEG2EI64_V_M4_MF2
Definition riscv/opcodes.hpp:9247
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M4_MASK
@ PseudoVLSSEG2E16_V_M4_MASK
Definition riscv/opcodes.hpp:5403
LIEF::assembly::riscv::OPCODE::FSGNJN_S
@ FSGNJN_S
Definition riscv/opcodes.hpp:12762
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF2_MASK
@ PseudoVLE8FF_V_MF2_MASK
Definition riscv/opcodes.hpp:4152
LIEF::assembly::riscv::OPCODE::AMOMAX_W_AQ
@ AMOMAX_W_AQ
Definition riscv/opcodes.hpp:12032
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_MF2
@ PseudoVSUXSEG3EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:10887
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF4
@ PseudoVSSEG2E8_V_MF4
Definition riscv/opcodes.hpp:10023
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E64
@ PseudoVREDMIN_VS_M8_E64
Definition riscv/opcodes.hpp:7904
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M2_MASK
@ PseudoVLUXEI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5691
LIEF::assembly::riscv::OPCODE::CV_CMPGE_SCI_B
@ CV_CMPGE_SCI_B
Definition riscv/opcodes.hpp:12225
LIEF::assembly::riscv::OPCODE::TH_SYNC
@ TH_SYNC
Definition riscv/opcodes.hpp:13123
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M4
@ PseudoVWSUBU_VV_M4
Definition riscv/opcodes.hpp:11723
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M4_MASK
@ PseudoVLUXEI16_V_M8_M4_MASK
Definition riscv/opcodes.hpp:5593
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M1_MASK
@ PseudoVLOXSEG4EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4623
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M8_MASK
@ PseudoTHVdotVMAQA_VX_M8_MASK
Definition riscv/opcodes.hpp:517
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M4_MASK
@ PseudoVSRL_VX_M4_MASK
Definition riscv/opcodes.hpp:9938
LIEF::assembly::riscv::OPCODE::PseudoCCADDI
@ PseudoCCADDI
Definition riscv/opcodes.hpp:341
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF4
@ PseudoVLSEG2E8_V_MF4
Definition riscv/opcodes.hpp:5122
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M1_E16_MASK
@ PseudoVFADD_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:1630
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF4_E16
@ PseudoVREM_VV_MF4_E16
Definition riscv/opcodes.hpp:8210
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF2
@ PseudoVRGATHEREI16_VV_M1_E16_MF2
Definition riscv/opcodes.hpp:8278
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E16
@ PseudoVFSUB_VV_M4_E16
Definition riscv/opcodes.hpp:3433
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF8
@ PseudoVMUL_VX_MF8
Definition riscv/opcodes.hpp:7387
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF8_MASK
@ PseudoVSUXSEG8EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:11334
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M8
@ PseudoTHVdotVMAQASU_VV_M8
Definition riscv/opcodes.hpp:456
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF4
@ PseudoVSUXSEG8EI64_V_M1_MF4
Definition riscv/opcodes.hpp:11299
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64V_SE_M1
@ PseudoVC_FPR64V_SE_M1
Definition riscv/opcodes.hpp:1115
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF8_MASK
@ PseudoVLSEG3E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5181
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M4
@ PseudoVSOXEI64_V_M4_M4
Definition riscv/opcodes.hpp:9099
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E64_MASK
@ PseudoVFCVT_F_X_V_M4_E64_MASK
Definition riscv/opcodes.hpp:1718
LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_M2
@ PseudoVC_IVW_SE_M2
Definition riscv/opcodes.hpp:1127
LIEF::assembly::riscv::OPCODE::FNMADD_D_INX
@ FNMADD_D_INX
Definition riscv/opcodes.hpp:12738
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E16
@ PseudoVREDAND_VS_M1_E16
Definition riscv/opcodes.hpp:7700
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M2_E64
@ PseudoVFNMSAC_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2759
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_M1_MASK
@ PseudoVSOXSEG4EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:9504
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M1_MASK
@ PseudoVLOXEI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4237
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF8_MASK
@ PseudoVFNCVT_RTZ_X_F_W_MF8_MASK
Definition riscv/opcodes.hpp:2590
LIEF::assembly::riscv::OPCODE::VLOXSEG5EI32_V
@ VLOXSEG5EI32_V
Definition riscv/opcodes.hpp:13349
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E32
@ PseudoVFREC7_V_M2_E32
Definition riscv/opcodes.hpp:2913
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M4
@ PseudoVLUXSEG2EI8_V_M2_M4
Definition riscv/opcodes.hpp:5834
LIEF::assembly::riscv::OPCODE::TH_LBUIB
@ TH_LBUIB
Definition riscv/opcodes.hpp:13064
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E16
@ PseudoVRGATHER_VV_M8_E16
Definition riscv/opcodes.hpp:8472
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_MF2_E32_MASK
@ PseudoVFMIN_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2153
LIEF::assembly::riscv::OPCODE::VFWREDOSUM_VS
@ VFWREDOSUM_VS
Definition riscv/opcodes.hpp:13297
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_M1
@ PseudoVC_V_IVV_M1
Definition riscv/opcodes.hpp:1248
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M8
@ PseudoVZEXT_VF4_M8
Definition riscv/opcodes.hpp:11899
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M2_MASK
@ PseudoVLSEG3E32_V_M2_MASK
Definition riscv/opcodes.hpp:5151
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_M1_MASK
@ PseudoVSUXSEG2EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:10688
LIEF::assembly::riscv::OPCODE::PseudoVADC_VVM_M8
@ PseudoVADC_VVM_M8
Definition riscv/opcodes.hpp:587
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M1_MASK
@ PseudoVLSEG2E32_V_M1_MASK
Definition riscv/opcodes.hpp:5083
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E8_MASK
@ PseudoVREM_VX_MF2_E8_MASK
Definition riscv/opcodes.hpp:8253
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E32
@ PseudoVFWNMACC_VV_MF2_E32
Definition riscv/opcodes.hpp:3871
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E32_MASK
@ PseudoVFWCVT_F_F_V_M2_E32_MASK
Definition riscv/opcodes.hpp:3566
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M2_MASK
@ PseudoVSLIDE1UP_VX_M2_MASK
Definition riscv/opcodes.hpp:8811
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF2
@ PseudoVSOXSEG6EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:9599
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E64_V_M1
@ PseudoVSSEG3E64_V_M1
Definition riscv/opcodes.hpp:10041
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M4_M2
@ PseudoVSOXSEG2EI64_V_M4_M2
Definition riscv/opcodes.hpp:9243
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF4_MASK
@ PseudoVLUXSEG2EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:5793
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E16
@ PseudoVREDMAX_VS_M1_E16
Definition riscv/opcodes.hpp:7788
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF4
@ PseudoVSSRL_VI_MF4
Definition riscv/opcodes.hpp:10215
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E32_MASK
@ PseudoVFWMACCBF16_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3714
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M4_MASK
@ PseudoVMULH_VX_M4_MASK
Definition riscv/opcodes.hpp:7352
LIEF::assembly::riscv::OPCODE::CV_MULSRN
@ CV_MULSRN
Definition riscv/opcodes.hpp:12376
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_MF2_MASK
@ PseudoVSOXSEG5EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9580
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E8_MASK
@ PseudoVREDMIN_VS_M8_E8_MASK
Definition riscv/opcodes.hpp:7907
LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M8
@ PseudoVSE64_V_M8
Definition riscv/opcodes.hpp:8730
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF4
@ PseudoVLSEG5E8_V_MF4
Definition riscv/opcodes.hpp:5274
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF8_MASK
@ PseudoVLOXSEG2EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:4369
LIEF::assembly::riscv::OPCODE::VSSEG3E64_V
@ VSSEG3E64_V
Definition riscv/opcodes.hpp:13708
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M4_E16
@ PseudoVFSGNJ_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3245
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF4_MASK
@ PseudoVLSEG6E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5289
LIEF::assembly::riscv::OPCODE::TH_REVW
@ TH_REVW
Definition riscv/opcodes.hpp:13101
LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_MF4
@ PseudoVMAND_MM_MF4
Definition riscv/opcodes.hpp:6512
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M8_E64
@ PseudoVFSGNJ_VFPR64_M8_E64
Definition riscv/opcodes.hpp:3269
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_MF2
@ PseudoVSUXSEG7EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:11239
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF8
@ PseudoVSSUB_VX_MF8
Definition riscv/opcodes.hpp:10473
LIEF::assembly::riscv::OPCODE::VSSEG2E16_V
@ VSSEG2E16_V
Definition riscv/opcodes.hpp:13702
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF8
@ PseudoVLUXEI32_V_MF2_MF8
Definition riscv/opcodes.hpp:5648
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M4
@ PseudoVLSSEG2E64_V_M4
Definition riscv/opcodes.hpp:5420
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF4_MASK
@ PseudoVLSEG3E8FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5169
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_M1
@ PseudoVC_V_VVW_M1
Definition riscv/opcodes.hpp:1316
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_M1
@ PseudoVSOXEI32_V_MF2_M1
Definition riscv/opcodes.hpp:9071
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF2_MASK
@ PseudoVLUXSEG6EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:6237
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M2
@ PseudoVSOXSEG3EI32_V_M4_M2
Definition riscv/opcodes.hpp:9335
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK
@ PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK
Definition riscv/opcodes.hpp:2492
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M2_MASK
@ PseudoVLOXSEG3EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4537
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_OR
@ G_ATOMICRMW_OR
Definition riscv/opcodes.hpp:128
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M8
@ PseudoVMFGT_VFPR32_M8
Definition riscv/opcodes.hpp:6688
LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M2
@ PseudoVLE32FF_V_M2
Definition riscv/opcodes.hpp:4109
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF2
@ PseudoVSUXSEG3EI32_V_M1_MF2
Definition riscv/opcodes.hpp:10827
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_MF2
@ PseudoVLOXSEG7EI32_V_M2_MF2
Definition riscv/opcodes.hpp:4878
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_M1
@ PseudoVSUXSEG6EI32_V_MF2_M1
Definition riscv/opcodes.hpp:11127
LIEF::assembly::riscv::OPCODE::VSSEG7E16_V
@ VSSEG7E16_V
Definition riscv/opcodes.hpp:13722
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M1_E64_MASK
@ PseudoVFSGNJX_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:3204
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E16_MASK
@ PseudoVREM_VX_MF4_E16_MASK
Definition riscv/opcodes.hpp:8255
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M8_E64_MASK
@ PseudoVFSGNJX_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:3210
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E32_MASK
@ PseudoVFNCVT_F_XU_W_M2_E32_MASK
Definition riscv/opcodes.hpp:2460
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_MF8_MASK
@ PseudoVSOXSEG5EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:9530
LIEF::assembly::riscv::OPCODE::G_EXTRACT
@ G_EXTRACT
Definition riscv/opcodes.hpp:93
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF4
@ PseudoVSUXSEG3EI32_V_M1_MF4
Definition riscv/opcodes.hpp:10829
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF4_MASK
@ PseudoVSUXSEG6EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:11148
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E32
@ PseudoVWREDSUM_VS_M4_E32
Definition riscv/opcodes.hpp:11661
LIEF::assembly::riscv::OPCODE::C_LD
@ C_LD
Definition riscv/opcodes.hpp:12502
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF2_MASK
@ PseudoVMSNE_VX_MF2_MASK
Definition riscv/opcodes.hpp:7258
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E16_MASK
@ PseudoVFREDMAX_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:2960
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF8
@ PseudoVSUXEI32_V_MF2_MF8
Definition riscv/opcodes.hpp:10581
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_M1
@ PseudoVSOXSEG6EI32_V_M1_M1
Definition riscv/opcodes.hpp:9611
LIEF::assembly::riscv::OPCODE::VLSEG2E8_V
@ VLSEG2E8_V
Definition riscv/opcodes.hpp:13375
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M2_E32
@ PseudoVFSUB_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3405
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_MF2_MASK
@ PseudoVMFGE_VFPR16_MF2_MASK
Definition riscv/opcodes.hpp:6649
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E8_MASK
@ PseudoVREDSUM_VS_M1_E8_MASK
Definition riscv/opcodes.hpp:7971
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF4_MASK
@ PseudoVSUXSEG4EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:10966
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF4
@ PseudoVSUB_VX_MF4
Definition riscv/opcodes.hpp:10499
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M2_MASK
@ PseudoVSUXEI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:10610
LIEF::assembly::riscv::OPCODE::G_VECTOR_COMPRESS
@ G_VECTOR_COMPRESS
Definition riscv/opcodes.hpp:254
LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M4_MASK
@ PseudoVSSE32_V_M4_MASK
Definition riscv/opcodes.hpp:9964
LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W_AQ_RL
@ SSAMOSWAP_W_AQ_RL
Definition riscv/opcodes.hpp:13010
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S_M2
@ PseudoVFMV_FPR32_S_M2
Definition riscv/opcodes.hpp:2379
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF2_MASK
@ PseudoVOR_VV_MF2_MASK
Definition riscv/opcodes.hpp:7649
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E8
@ PseudoVFWCVT_F_XU_V_M2_E8
Definition riscv/opcodes.hpp:3587
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_MF2_MF4
@ PseudoVAESEM_VS_MF2_MF4
Definition riscv/opcodes.hpp:749
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_M1_MASK
@ PseudoVLSEG5E8FF_V_M1_MASK
Definition riscv/opcodes.hpp:5263
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M2
@ PseudoVSOXEI32_V_M4_M2
Definition riscv/opcodes.hpp:9059
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16
@ PseudoVFWSUB_WV_M1_E16
Definition riscv/opcodes.hpp:4009
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M1
@ PseudoVLUXSEG3EI8_V_MF2_M1
Definition riscv/opcodes.hpp:5950
LIEF::assembly::riscv::OPCODE::FMINM_S
@ FMINM_S
Definition riscv/opcodes.hpp:12705
LIEF::assembly::riscv::OPCODE::VWSUB_VV
@ VWSUB_VV
Definition riscv/opcodes.hpp:13834
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF4_E16
@ PseudoVFWSUB_WFPR16_MF4_E16
Definition riscv/opcodes.hpp:3999
LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_MF8
@ PseudoVADC_VIM_MF8
Definition riscv/opcodes.hpp:583
LIEF::assembly::riscv::OPCODE::G_FSQRT
@ G_FSQRT
Definition riscv/opcodes.hpp:272
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M8_M1
@ PseudoVLUXSEG5EI64_V_M8_M1
Definition riscv/opcodes.hpp:6140
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_M1
@ PseudoVLUXSEG8EI64_V_M1_M1
Definition riscv/opcodes.hpp:6362
LIEF::assembly::riscv::OPCODE::VLSEG2E32_V
@ VLSEG2E32_V
Definition riscv/opcodes.hpp:13371
LIEF::assembly::riscv::OPCODE::CV_LB_rr
@ CV_LB_rr
Definition riscv/opcodes.hpp:12322
LIEF::assembly::riscv::OPCODE::VMSOF_M
@ VMSOF_M
Definition riscv/opcodes.hpp:13547
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF2
@ PseudoVLOXSEG2EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:4364
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_M1
@ PseudoVC_V_X_M1
Definition riscv/opcodes.hpp:1382
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF8_MASK
@ PseudoVSOXSEG7EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:9690
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E32
@ PseudoVREDMAX_VS_MF2_E32
Definition riscv/opcodes.hpp:7822
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_MF2
@ PseudoVWSUB_VX_MF2
Definition riscv/opcodes.hpp:11797
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK
@ PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:3554
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M8_MASK
@ PseudoVRGATHEREI16_VV_M4_E8_M8_MASK
Definition riscv/opcodes.hpp:8369
LIEF::assembly::riscv::OPCODE::VLSSEG5E32_V
@ VLSSEG5E32_V
Definition riscv/opcodes.hpp:13437
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E32
@ PseudoVFMADD_VV_M2_E32
Definition riscv/opcodes.hpp:2035
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M2_MASK
@ PseudoVWADDU_WX_M2_MASK
Definition riscv/opcodes.hpp:11386
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF2
@ PseudoVSSUB_VV_MF2
Definition riscv/opcodes.hpp:10455
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_M1_MASK
@ PseudoVLOXSEG7EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4883
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E16
@ PseudoVFSGNJX_VV_M8_E16
Definition riscv/opcodes.hpp:3229
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E64_MASK
@ PseudoVFCVT_F_X_V_M2_E64_MASK
Definition riscv/opcodes.hpp:1712
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M1_MASK
@ PseudoVSUXSEG3EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10884
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M2_MASK
@ PseudoVWMULSU_VX_M2_MASK
Definition riscv/opcodes.hpp:11554
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF4
@ PseudoVSOXSEG2EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:9187
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E16_MASK
@ PseudoVFWREDOSUM_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:3924
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF8_MASK
@ PseudoVSUXEI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:10590
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_M8
@ PseudoVC_V_IVV_M8
Definition riscv/opcodes.hpp:1251
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF8
@ PseudoVNCLIPU_WV_MF8
Definition riscv/opcodes.hpp:7448
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E32
@ PseudoVFWSUB_WV_M1_E32
Definition riscv/opcodes.hpp:4013
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E16_MASK
@ PseudoVDIV_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:1528
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF2
@ PseudoVLE16FF_V_MF2
Definition riscv/opcodes.hpp:4091
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_M1_MASK
@ PseudoVLOXSEG7EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4905
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF4_MASK
@ PseudoVSEXT_VF2_MF4_MASK
Definition riscv/opcodes.hpp:8760
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E32_MASK
@ PseudoVWREDSUMU_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:11632
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_M1
@ PseudoVLSEG5E16FF_V_M1
Definition riscv/opcodes.hpp:5238
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M8_E64_MASK
@ PseudoVFMIN_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2161
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_M1_MASK
@ PseudoVSUXSEG8EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11282
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M1_MASK
@ PseudoVFNCVT_RTZ_X_F_W_M1_MASK
Definition riscv/opcodes.hpp:2580
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M2
@ PseudoVLOXSEG4EI32_V_M2_M2
Definition riscv/opcodes.hpp:4618
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E32_MASK
@ PseudoVREM_VX_M4_E32_MASK
Definition riscv/opcodes.hpp:8235
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E16_MASK
@ PseudoVFREDOSUM_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:3002
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M4
@ PseudoVLSE8_V_M4
Definition riscv/opcodes.hpp:5044
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M2_MASK
@ PseudoVADD_VX_M2_MASK
Definition riscv/opcodes.hpp:629
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M4_MASK
@ PseudoVSSRL_VX_M4_MASK
Definition riscv/opcodes.hpp:10238
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_M1_MASK
@ PseudoVLOXSEG6EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:4843
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E32_TIED
@ PseudoVFWSUB_WV_MF2_E32_TIED
Definition riscv/opcodes.hpp:4040
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF2_MASK
@ PseudoVSSSEG4E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10334
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M2
@ PseudoVSRL_VV_M2
Definition riscv/opcodes.hpp:9921
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M1_E32
@ PseudoVFNMSUB_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2807
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M1
@ PseudoVSSSEG4E32_V_M1
Definition riscv/opcodes.hpp:10319
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF4_MASK
@ PseudoVMSLEU_VX_MF4_MASK
Definition riscv/opcodes.hpp:7118
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M4_MASK
@ PseudoVMULHU_VV_M4_MASK
Definition riscv/opcodes.hpp:7310
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_MF2_MASK
@ PseudoVSOXSEG3EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9296
LIEF::assembly::riscv::OPCODE::PseudoCCANDN
@ PseudoCCANDN
Definition riscv/opcodes.hpp:346
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M1_MASK
@ PseudoVCLZ_V_M1_MASK
Definition riscv/opcodes.hpp:1001
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E64_MASK
@ PseudoVDIV_VX_M1_E64_MASK
Definition riscv/opcodes.hpp:1560
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M2_MF8
@ PseudoVAESDM_VS_M2_MF8
Definition riscv/opcodes.hpp:677
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M1
@ PseudoVOR_VI_M1
Definition riscv/opcodes.hpp:7626
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M2_MASK
@ PseudoVFCVT_RM_XU_F_V_M2_MASK
Definition riscv/opcodes.hpp:1794
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M2
@ PseudoVSOXSEG2EI32_V_M1_M2
Definition riscv/opcodes.hpp:9193
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M1_E16_MASK
@ PseudoVFDIV_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:1864
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_M1
@ PseudoVLUXSEG5EI16_V_MF4_M1
Definition riscv/opcodes.hpp:6094
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF8_MASK
@ PseudoVOR_VI_MF8_MASK
Definition riscv/opcodes.hpp:7639
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M2
@ PseudoVLUXSEG2EI16_V_M1_M2
Definition riscv/opcodes.hpp:5728
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M4
@ PseudoVSUXSEG2EI32_V_M4_M4
Definition riscv/opcodes.hpp:10715
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M1
@ PseudoVMADC_VI_M1
Definition riscv/opcodes.hpp:6437
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_M1
@ PseudoVSOXSEG5EI32_V_M1_M1
Definition riscv/opcodes.hpp:9531
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E16_MASK
@ PseudoVFREDOSUM_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:3014
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF2_MASK
@ PseudoVLUXSEG6EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6171
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF2_M1
@ PseudoVSOXSEG5EI8_V_MF2_M1
Definition riscv/opcodes.hpp:9573
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E64_MASK
@ PseudoVREDXOR_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:8029
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M1_MASK
@ PseudoVNSRA_WI_M1_MASK
Definition riscv/opcodes.hpp:7555
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF2_MASK
@ PseudoVRSUB_VX_MF2_MASK
Definition riscv/opcodes.hpp:8599
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E16_MASK
@ PseudoVDIV_VX_M2_E16_MASK
Definition riscv/opcodes.hpp:1564
LIEF::assembly::riscv::OPCODE::FCVT_D_L
@ FCVT_D_L
Definition riscv/opcodes.hpp:12577
LIEF::assembly::riscv::OPCODE::PseudoCCXORI
@ PseudoCCXORI
Definition riscv/opcodes.hpp:368
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E64_MASK
@ PseudoVFCVT_RM_F_X_V_M8_E64_MASK
Definition riscv/opcodes.hpp:1784
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B32_MASK
@ PseudoVMSBF_M_B32_MASK
Definition riscv/opcodes.hpp:6945
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M2
@ PseudoVMIN_VV_M2
Definition riscv/opcodes.hpp:6856
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M2_M1_MASK
@ PseudoVSOXSEG6EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9618
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_M4
@ PseudoVC_V_XVV_M4
Definition riscv/opcodes.hpp:1344
LIEF::assembly::riscv::OPCODE::VNSRL_WV
@ VNSRL_WV
Definition riscv/opcodes.hpp:13581
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF8_E8
@ PseudoVREDMIN_VS_MF8_E8
Definition riscv/opcodes.hpp:7918
LIEF::assembly::riscv::OPCODE::PseudoLA
@ PseudoLA
Definition riscv/opcodes.hpp:385
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF8_MASK
@ PseudoVLOXSEG7EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:4869
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M1_MASK
@ PseudoVLSEG4E8_V_M1_MASK
Definition riscv/opcodes.hpp:5229
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E8_MASK
@ PseudoVFWCVT_F_XU_V_MF2_E8_MASK
Definition riscv/opcodes.hpp:3600
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2_MASK
@ PseudoVWSUBU_WV_M2_MASK
Definition riscv/opcodes.hpp:11748
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E64
@ PseudoVFMACC_VV_M8_E64
Definition riscv/opcodes.hpp:1989
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF2_MASK
@ PseudoVFWCVT_XU_F_V_MF2_MASK
Definition riscv/opcodes.hpp:3684
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_M1
@ PseudoVRGATHEREI16_VV_MF2_E16_M1
Definition riscv/opcodes.hpp:8394
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E16
@ PseudoVRGATHER_VV_M2_E16
Definition riscv/opcodes.hpp:8456
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M8_E16_MASK
@ PseudoVFREDMAX_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:2954
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_MF8
@ PseudoVAESDM_VS_M1_MF8
Definition riscv/opcodes.hpp:672
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M1
@ PseudoVSSSEG3E8_V_M1
Definition riscv/opcodes.hpp:10301
LIEF::assembly::riscv::OPCODE::G_UADDSAT
@ G_UADDSAT
Definition riscv/opcodes.hpp:182
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF2_MASK
@ PseudoVSOXSEG2EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9280
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E64FF_V_M1
@ PseudoVLSEG5E64FF_V_M1
Definition riscv/opcodes.hpp:5258
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M2_E16
@ PseudoVFWMSAC_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3769
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF4
@ PseudoVSOXSEG8EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:9767
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M4
@ PseudoVFCVT_RM_XU_F_V_M4
Definition riscv/opcodes.hpp:1795
LIEF::assembly::riscv::OPCODE::VC_V_VVW
@ VC_V_VVW
Definition riscv/opcodes.hpp:13191
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E16_MASK
@ PseudoVREDMINU_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:7849
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M4_M1
@ PseudoVSOXSEG8EI32_V_M4_M1
Definition riscv/opcodes.hpp:9781
LIEF::assembly::riscv::OPCODE::G_SSUBE
@ G_SSUBE
Definition riscv/opcodes.hpp:177
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E16_MASK
@ PseudoVFCVT_RM_F_XU_V_M4_E16_MASK
Definition riscv/opcodes.hpp:1744
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_MF2
@ PseudoVLOXSEG7EI64_V_M4_MF2
Definition riscv/opcodes.hpp:4906
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF4_MASK
@ PseudoVSUXSEG6EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:11112
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M2_MASK
@ PseudoVNCLIP_WI_M2_MASK
Definition riscv/opcodes.hpp:7465
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M2_E32
@ PseudoVFRSUB_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3105
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_M8
@ PseudoVC_FPR16VV_SE_M8
Definition riscv/opcodes.hpp:1081
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E16_MASK
@ PseudoVREDMAX_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:7813
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E8_MASK
@ PseudoVREDMIN_VS_M2_E8_MASK
Definition riscv/opcodes.hpp:7891
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF4
@ PseudoVFNRCLIP_XU_F_QF_MF4
Definition riscv/opcodes.hpp:2861
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF4
@ PseudoVLSEG6E8_V_MF4
Definition riscv/opcodes.hpp:5314
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_XCHG
@ G_ATOMICRMW_XCHG
Definition riscv/opcodes.hpp:123
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M1
@ PseudoVSUXSEG3EI32_V_M4_M1
Definition riscv/opcodes.hpp:10837
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M1_MASK
@ PseudoVWADD_VV_M1_MASK
Definition riscv/opcodes.hpp:11396
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF4
@ PseudoVLUXSEG5EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:6158
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M1
@ PseudoVAESDM_VV_M1
Definition riscv/opcodes.hpp:693
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF4_MASK
@ PseudoVLUXSEG4EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:5991
LIEF::assembly::riscv::OPCODE::CV_OR_H
@ CV_OR_H
Definition riscv/opcodes.hpp:12380
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_M1_MASK
@ PseudoVSOXSEG6EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9640
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF8
@ PseudoVSADD_VI_MF8
Definition riscv/opcodes.hpp:8658
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M8_M8_MASK
@ PseudoVLUXEI16_V_M8_M8_MASK
Definition riscv/opcodes.hpp:5595
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M1
@ PseudoVMSLEU_VX_M1
Definition riscv/opcodes.hpp:7107
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF4
@ PseudoVRGATHEREI16_VV_M1_E16_MF4
Definition riscv/opcodes.hpp:8280
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF4_MASK
@ PseudoVSOXSEG7EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:9724
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M1
@ PseudoVMSBC_VV_M1
Definition riscv/opcodes.hpp:6917
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_M1
@ PseudoVSUXSEG7EI16_V_MF2_M1
Definition riscv/opcodes.hpp:11181
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E64
@ PseudoVDIV_VV_M8_E64
Definition riscv/opcodes.hpp:1539
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M1_MASK
@ PseudoVMIN_VX_M1_MASK
Definition riscv/opcodes.hpp:6869
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M8_MASK
@ PseudoVMSGTU_VI_M8_MASK
Definition riscv/opcodes.hpp:7016
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF4_E16_MASK
@ PseudoVFNCVT_F_XU_W_MF4_E16_MASK
Definition riscv/opcodes.hpp:2470
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_M1_MASK
@ PseudoVSOXSEG8EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9818
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M1
@ PseudoVMSGT_VX_M1
Definition riscv/opcodes.hpp:7051
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M1_MASK
@ PseudoVLSE8_V_M1_MASK
Definition riscv/opcodes.hpp:5041
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E16_MASK
@ PseudoVFNMSAC_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:2790
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B1_MASK
@ PseudoVFIRST_M_B1_MASK
Definition riscv/opcodes.hpp:1926
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M2_MASK
@ PseudoVSOXSEG4EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9410
LIEF::assembly::riscv::OPCODE::VFWADD_VV
@ VFWADD_VV
Definition riscv/opcodes.hpp:13273
LIEF::assembly::riscv::OPCODE::CV_FF1
@ CV_FF1
Definition riscv/opcodes.hpp:12312
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_M1_M1
@ PseudoVLOXSEG8EI8_V_M1_M1
Definition riscv/opcodes.hpp:4990
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK
@ PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK
Definition riscv/opcodes.hpp:2434
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF2
@ PseudoVADD_VI_MF2
Definition riscv/opcodes.hpp:606
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M2
@ PseudoVMFGE_VFPR16_M2
Definition riscv/opcodes.hpp:6642
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E16_MASK
@ PseudoVREDOR_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:7945
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_MF2_E32_MASK
@ PseudoVFRSUB_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3112
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M4_E32_MASK
@ PseudoVFWSUB_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3970
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_M1_MASK
@ PseudoVLUXSEG6EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:6175
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M4
@ PseudoVSM4R_VV_M4
Definition riscv/opcodes.hpp:8961
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_MF4
@ PseudoVFCVT_X_F_V_MF4
Definition riscv/opcodes.hpp:1861
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M1_E64_MASK
@ PseudoVFMSUB_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2275
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_M4
@ PseudoVC_V_XV_SE_M4
Definition riscv/opcodes.hpp:1377
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF4_MASK
@ PseudoVLUXSEG5EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:6127
LIEF::assembly::riscv::OPCODE::VFWCVT_F_F_V
@ VFWCVT_F_F_V
Definition riscv/opcodes.hpp:13277
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M1_MASK
@ PseudoVSUXEI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10636
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_MF2
@ PseudoVWADD_VX_MF2
Definition riscv/opcodes.hpp:11413
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E16_MASK
@ PseudoVDIVU_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:1456
LIEF::assembly::riscv::OPCODE::AMOOR_D_AQ
@ AMOOR_D_AQ
Definition riscv/opcodes.hpp:12072
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF4_MASK
@ PseudoVLOXSEG8EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4941
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF8_MASK
@ PseudoVLSE8_V_MF8_MASK
Definition riscv/opcodes.hpp:5053
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF8
@ PseudoVNSRL_WX_MF8
Definition riscv/opcodes.hpp:7624
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF4_E16_MASK
@ PseudoVFNMSUB_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2806
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M1
@ PseudoVLUXSEG2EI32_V_M2_M1
Definition riscv/opcodes.hpp:5770
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF2
@ PseudoVSOXSEG4EI64_V_M1_MF2
Definition riscv/opcodes.hpp:9459
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF4_MASK
@ PseudoVSUXSEG8EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:11308
LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_MF4
@ PseudoVC_XVW_SE_MF4
Definition riscv/opcodes.hpp:1407
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M8_MASK
@ PseudoVREV8_V_M8_MASK
Definition riscv/opcodes.hpp:8267
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M2_MASK
@ PseudoVAADDU_VV_M2_MASK
Definition riscv/opcodes.hpp:524
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_MF2
@ PseudoVSOXSEG8EI64_V_M4_MF2
Definition riscv/opcodes.hpp:9807
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B4
@ PseudoVMSOF_M_B4
Definition riscv/opcodes.hpp:7271
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF4
@ PseudoVSOXSEG7EI32_V_M1_MF4
Definition riscv/opcodes.hpp:9695
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M2
@ PseudoVSOXSEG3EI32_V_M1_M2
Definition riscv/opcodes.hpp:9321
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E16
@ PseudoVFCVT_F_XU_V_M4_E16
Definition riscv/opcodes.hpp:1683
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M1_MASK
@ PseudoVWMACCUS_VX_M1_MASK
Definition riscv/opcodes.hpp:11480
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_M8
@ PseudoVMV_V_V_M8
Definition riscv/opcodes.hpp:7400
LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_MF2
@ PseudoVSSE32_V_MF2
Definition riscv/opcodes.hpp:9967
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M4
@ PseudoVMSBC_VV_M4
Definition riscv/opcodes.hpp:6919
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M2_E32
@ PseudoVFNMACC_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2629
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF8_MASK
@ PseudoVLSEG8E8FF_V_MF8_MASK
Definition riscv/opcodes.hpp:5389
LIEF::assembly::riscv::OPCODE::SLLIW
@ SLLIW
Definition riscv/opcodes.hpp:12984
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF4_E16_MASK
@ PseudoVFREDMIN_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:2994
LIEF::assembly::riscv::OPCODE::C_LI_HINT
@ C_LI_HINT
Definition riscv/opcodes.hpp:12507
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M1_E32_MASK
@ PseudoVFNCVT_RM_F_X_W_M1_E32_MASK
Definition riscv/opcodes.hpp:2510
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M8_MASK
@ PseudoVSSE16_V_M8_MASK
Definition riscv/opcodes.hpp:9954
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_M1_E16_MASK
@ PseudoVFNMACC_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:2616
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF2_M1_MASK
@ PseudoVSUXSEG5EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11078
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_M2
@ PseudoVC_V_FPR32VW_M2
Definition riscv/opcodes.hpp:1213
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF4_MASK
@ PseudoVSUXEI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:10656
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M4
@ PseudoVANDN_VV_M4
Definition riscv/opcodes.hpp:794
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E64_MASK
@ PseudoVFSGNJ_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:3288
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E32_MASK
@ PseudoVREDOR_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:7939
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M1
@ PseudoVSMUL_VV_M1
Definition riscv/opcodes.hpp:8964
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M1
@ PseudoVLUXSEG3EI32_V_M1_M1
Definition riscv/opcodes.hpp:5890
LIEF::assembly::riscv::OPCODE::FMADD_S_INX
@ FMADD_S_INX
Definition riscv/opcodes.hpp:12692
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF4_E8
@ PseudoVCOMPRESS_VM_MF4_E8
Definition riscv/opcodes.hpp:1034
LIEF::assembly::riscv::OPCODE::FCVT_LU_D_INX
@ FCVT_LU_D_INX
Definition riscv/opcodes.hpp:12604
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF2_MASK
@ PseudoVSUXSEG4EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:11010
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E64
@ PseudoVFCVT_RM_F_XU_V_M4_E64
Definition riscv/opcodes.hpp:1747
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M2_MASK
@ PseudoVSUB_VX_M2_MASK
Definition riscv/opcodes.hpp:10492
LIEF::assembly::riscv::OPCODE::DIVU
@ DIVU
Definition riscv/opcodes.hpp:12552
LIEF::assembly::riscv::OPCODE::CV_SDOTUP_B
@ CV_SDOTUP_B
Definition riscv/opcodes.hpp:12399
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M4_E64_MASK
@ PseudoVFMAX_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2084
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF2
@ PseudoVSSSEG2E16_V_MF2
Definition riscv/opcodes.hpp:10253
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M2_MASK
@ PseudoVFSLIDE1DOWN_VFPR32_M2_MASK
Definition riscv/opcodes.hpp:3316
LIEF::assembly::riscv::OPCODE::AMOMINU_W_AQ
@ AMOMINU_W_AQ
Definition riscv/opcodes.hpp:12048
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M2
@ PseudoVFCVT_X_F_V_M2
Definition riscv/opcodes.hpp:1853
LIEF::assembly::riscv::OPCODE::VSLL_VV
@ VSLL_VV
Definition riscv/opcodes.hpp:13650
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF2_MASK
@ PseudoVSUXSEG2EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:10690
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_M1
@ PseudoVSSSEG5E8_V_M1
Definition riscv/opcodes.hpp:10351
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF2
@ PseudoVROL_VX_MF2
Definition riscv/opcodes.hpp:8528
LIEF::assembly::riscv::OPCODE::G_UADDO
@ G_UADDO
Definition riscv/opcodes.hpp:170
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF2_MASK
@ PseudoVSOXSEG3EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9308
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M2_MASK
@ PseudoVLOXSEG4EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:4595
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2
@ PseudoVWADD_WV_M2
Definition riscv/opcodes.hpp:11423
LIEF::assembly::riscv::OPCODE::G_FEXP
@ G_FEXP
Definition riscv/opcodes.hpp:205
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF2_MASK
@ PseudoVMAXU_VX_MF2_MASK
Definition riscv/opcodes.hpp:6537
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M8
@ PseudoVMSNE_VV_M8
Definition riscv/opcodes.hpp:7241
LIEF::assembly::riscv::OPCODE::INLINEASM
@ INLINEASM
Definition riscv/opcodes.hpp:25
LIEF::assembly::riscv::OPCODE::VWSLL_VX
@ VWSLL_VX
Definition riscv/opcodes.hpp:13829
LIEF::assembly::riscv::OPCODE::LB_AQ_RL
@ LB_AQ_RL
Definition riscv/opcodes.hpp:12835
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M1_MASK
@ PseudoVMFNE_VFPR16_M1_MASK
Definition riscv/opcodes.hpp:6785
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M4_E16_MASK
@ PseudoVFADD_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:1604
LIEF::assembly::riscv::OPCODE::VNCLIPU_WV
@ VNCLIPU_WV
Definition riscv/opcodes.hpp:13568
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF2_MASK
@ PseudoVLSEG5E16FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5241
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M4
@ PseudoVLUXEI16_V_M2_M4
Definition riscv/opcodes.hpp:5582
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M2_MASK
@ PseudoVMFLT_VFPR32_M2_MASK
Definition riscv/opcodes.hpp:6757
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M1_MASK
@ PseudoVSUXEI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:10600
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M2_MASK
@ PseudoVWMACC_VX_M2_MASK
Definition riscv/opcodes.hpp:11530
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M8_E64_MASK
@ PseudoVFSUB_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:3420
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M2_MASK
@ PseudoVSUXSEG2EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10740
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E16
@ PseudoVFWMACC_VV_MF2_E16
Definition riscv/opcodes.hpp:3761
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF2
@ PseudoVSOXSEG8EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:9765
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF8
@ PseudoVLUXSEG8EI64_V_M1_MF8
Definition riscv/opcodes.hpp:6368
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF2
@ PseudoVSLIDEUP_VI_MF2
Definition riscv/opcodes.hpp:8858
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF2_MASK
@ PseudoVSOXSEG4EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9424
LIEF::assembly::riscv::OPCODE::VAND_VX
@ VAND_VX
Definition riscv/opcodes.hpp:13156
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_MF2
@ PseudoVAESEF_VV_MF2
Definition riscv/opcodes.hpp:726
LIEF::assembly::riscv::OPCODE::VSM3ME_VV
@ VSM3ME_VV
Definition riscv/opcodes.hpp:13653
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF4_E16_MASK
@ PseudoVFNMSUB_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:2854
LIEF::assembly::riscv::OPCODE::AMOAND_H_RL
@ AMOAND_H_RL
Definition riscv/opcodes.hpp:11974
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E32
@ PseudoVFNMADD_VV_M1_E32
Definition riscv/opcodes.hpp:2707
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M1_MASK
@ PseudoVSMUL_VV_M1_MASK
Definition riscv/opcodes.hpp:8965
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M4
@ PseudoVRGATHEREI16_VV_M2_E16_M4
Definition riscv/opcodes.hpp:8310
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_MF2_MF4
@ PseudoVAESEF_VS_MF2_MF4
Definition riscv/opcodes.hpp:720
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M4_E64_MASK
@ PseudoVFNMSUB_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2822
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M4
@ PseudoVSOXEI16_V_M8_M4
Definition riscv/opcodes.hpp:9021
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF4_E16
@ PseudoVFWCVTBF16_F_F_V_MF4_E16
Definition riscv/opcodes.hpp:3557
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF4
@ PseudoVNSRA_WI_MF4
Definition riscv/opcodes.hpp:7562
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M2
@ PseudoVLSSEG4E8_V_M2
Definition riscv/opcodes.hpp:5482
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M4_E32_MASK
@ PseudoVFMIN_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2149
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M8_E64_MASK
@ PseudoVFNMADD_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2704
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_M1
@ PseudoVLOXSEG7EI32_V_MF2_M1
Definition riscv/opcodes.hpp:4882
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF8
@ PseudoVMSLT_VX_MF8
Definition riscv/opcodes.hpp:7219
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_MF2_E32_MASK
@ PseudoVFWMSAC_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3784
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_M1
@ PseudoVLUXSEG7EI8_V_MF8_M1
Definition riscv/opcodes.hpp:6314
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_M2_E16
@ PseudoVFRSUB_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3093
LIEF::assembly::riscv::OPCODE::VLSEG3E32FF_V
@ VLSEG3E32FF_V
Definition riscv/opcodes.hpp:13378
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E32_MASK
@ PseudoVFMUL_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:2363
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_MF2_MASK
@ PseudoVSOXSEG4EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:9478
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E32
@ PseudoVFNCVT_F_F_W_MF2_E32
Definition riscv/opcodes.hpp:2449
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M2
@ PseudoVLSEG3E32FF_V_M2
Definition riscv/opcodes.hpp:5144
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF4_MASK
@ PseudoVSUXSEG4EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:10940
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_M1
@ PseudoVLSSEG6E32_V_M1
Definition riscv/opcodes.hpp:5516
LIEF::assembly::riscv::OPCODE::VL4RE8_V
@ VL4RE8_V
Definition riscv/opcodes.hpp:13318
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF8
@ PseudoVMSLEU_VI_MF8
Definition riscv/opcodes.hpp:7091
LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_M4
@ PseudoVC_VVW_SE_M4
Definition riscv/opcodes.hpp:1155
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M4
@ PseudoVNSRA_WX_M4
Definition riscv/opcodes.hpp:7582
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M4_E32
@ PseudoVFNMSAC_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2751
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M1_MASK
@ PseudoVLSEG3E16_V_M1_MASK
Definition riscv/opcodes.hpp:5135
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M4_E32
@ PseudoVCOMPRESS_VM_M4_E32
Definition riscv/opcodes.hpp:1023
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF2_MASK
@ PseudoVLOXEI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4323
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF2_E16
@ PseudoVFNMSUB_VV_MF2_E16
Definition riscv/opcodes.hpp:2849
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M2_E16_MASK
@ PseudoVFWMUL_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3806
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M1
@ PseudoVLUXEI64_V_M4_M1
Definition riscv/opcodes.hpp:5666
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E32
@ PseudoVFSGNJN_VV_MF2_E32
Definition riscv/opcodes.hpp:3177
LIEF::assembly::riscv::OPCODE::VLOXSEG2EI16_V
@ VLOXSEG2EI16_V
Definition riscv/opcodes.hpp:13336
LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M1
@ PseudoVLSE32_V_M1
Definition riscv/opcodes.hpp:5022
LIEF::assembly::riscv::OPCODE::VMXOR_MM
@ VMXOR_MM
Definition riscv/opcodes.hpp:13566
LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_M2
@ PseudoVMAND_MM_M2
Definition riscv/opcodes.hpp:6508
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF2_MASK
@ PseudoVLSEG2E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5121
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF4
@ PseudoVLUXSEG6EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:6172
LIEF::assembly::riscv::OPCODE::SUBW
@ SUBW
Definition riscv/opcodes.hpp:13016
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF2
@ PseudoVLOXSEG4EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:4630
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF4
@ PseudoVNCLIPU_WX_MF4
Definition riscv/opcodes.hpp:7458
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E8
@ PseudoVREDXOR_VS_M8_E8
Definition riscv/opcodes.hpp:8038
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF4
@ PseudoVLOXSEG7EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:4866
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M1_E16_MASK
@ PseudoVFMSUB_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:2253
LIEF::assembly::riscv::OPCODE::MOPR7
@ MOPR7
Definition riscv/opcodes.hpp:12889
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M2
@ PseudoVSSRL_VV_M2
Definition riscv/opcodes.hpp:10221
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF4_MASK
@ PseudoVLOXEI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4211
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF2
@ PseudoVNSRA_WI_MF2
Definition riscv/opcodes.hpp:7560
LIEF::assembly::riscv::OPCODE::VREDXOR_VS
@ VREDXOR_VS
Definition riscv/opcodes.hpp:13601
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M4
@ PseudoVMADC_VV_M4
Definition riscv/opcodes.hpp:6453
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M1_MASK
@ PseudoVLUXEI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:5597
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E32_MASK
@ PseudoVFNMACC_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:2654
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF2
@ PseudoVMULH_VV_MF2
Definition riscv/opcodes.hpp:7341
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M1_MASK
@ PseudoVLOXEI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4179
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_M1
@ PseudoVLSEG5E16_V_M1
Definition riscv/opcodes.hpp:5244
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_MF4
@ PseudoVFWMACC_4x4x4_MF4
Definition riscv/opcodes.hpp:3730
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M8_MASK
@ PseudoVSSE8_V_M8_MASK
Definition riscv/opcodes.hpp:9984
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M2_M1
@ PseudoVLOXSEG5EI16_V_M2_M1
Definition riscv/opcodes.hpp:4694
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E64
@ PseudoVFADD_VV_M2_E64
Definition riscv/opcodes.hpp:1639
LIEF::assembly::riscv::OPCODE::AMOADD_W_AQ
@ AMOADD_W_AQ
Definition riscv/opcodes.hpp:11960
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E64
@ PseudoVRGATHER_VV_M1_E64
Definition riscv/opcodes.hpp:8452
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E8
@ PseudoVREMU_VX_M1_E8
Definition riscv/opcodes.hpp:8134
LIEF::assembly::riscv::OPCODE::FENTRY_CALL
@ FENTRY_CALL
Definition riscv/opcodes.hpp:50
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E32_MASK
@ PseudoVREDSUM_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:7967
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF2
@ PseudoVSE8_V_MF2
Definition riscv/opcodes.hpp:8740
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M1_MASK
@ PseudoVSUXSEG2EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10704
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_M1
@ PseudoVSBC_VVM_M1
Definition riscv/opcodes.hpp:8688
LIEF::assembly::riscv::OPCODE::CV_XOR_SCI_H
@ CV_XOR_SCI_H
Definition riscv/opcodes.hpp:12470
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M2_MASK
@ PseudoVLUXSEG2EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:5785
LIEF::assembly::riscv::OPCODE::G_FMA
@ G_FMA
Definition riscv/opcodes.hpp:199
LIEF::assembly::riscv::OPCODE::AMOCAS_W_AQ_RL
@ AMOCAS_W_AQ_RL
Definition riscv/opcodes.hpp:12001
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_M2_MASK
@ PseudoVLOXSEG4EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:4671
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M1_MASK
@ PseudoVLUXSEG4EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:5985
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF4
@ PseudoVMFEQ_VV_MF4
Definition riscv/opcodes.hpp:6638
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_MF2_MASK
@ PseudoVSSSEG2E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10264
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E32
@ PseudoVFNMSUB_VV_M2_E32
Definition riscv/opcodes.hpp:2833
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M2_MASK
@ PseudoVRGATHEREI16_VV_M4_E32_M2_MASK
Definition riscv/opcodes.hpp:8349
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M1
@ PseudoVSUXEI32_V_M2_M1
Definition riscv/opcodes.hpp:10553
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF2_MASK
@ PseudoVSOXEI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:9150
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M2_MASK
@ PseudoVLUXSEG2EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:5815
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF4_E8_MASK
@ PseudoVREDMIN_VS_MF4_E8_MASK
Definition riscv/opcodes.hpp:7917
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_M1_MASK
@ PseudoVLUXSEG2EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:5847
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E32
@ PseudoVFNMADD_VV_M8_E32
Definition riscv/opcodes.hpp:2725
LIEF::assembly::riscv::OPCODE::G_SITOFP
@ G_SITOFP
Definition riscv/opcodes.hpp:218
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_MF2_MASK
@ PseudoVLOXSEG4EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4621
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_M1_MASK
@ PseudoVLUXSEG8EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6323
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M4_MASK
@ PseudoVSOXSEG2EI64_V_M8_M4_MASK
Definition riscv/opcodes.hpp:9254
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF4
@ PseudoVOR_VI_MF4
Definition riscv/opcodes.hpp:7636
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M8
@ PseudoVASUB_VX_M8
Definition riscv/opcodes.hpp:908
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M1_MASK
@ PseudoVMSGT_VI_M1_MASK
Definition riscv/opcodes.hpp:7038
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M1
@ PseudoVSLL_VV_M1
Definition riscv/opcodes.hpp:8892
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M4
@ PseudoVLE8FF_V_M4
Definition riscv/opcodes.hpp:4147
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF4_E16
@ PseudoVFWREDOSUM_VS_MF4_E16
Definition riscv/opcodes.hpp:3931
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_M4
@ PseudoVC_V_I_SE_M4
Definition riscv/opcodes.hpp:1297
LIEF::assembly::riscv::OPCODE::FLE_S_INX
@ FLE_S_INX
Definition riscv/opcodes.hpp:12670
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF2
@ PseudoVWSUBU_VV_MF2
Definition riscv/opcodes.hpp:11725
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M1_MASK
@ PseudoVLOXEI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4311
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M1_MASK
@ PseudoVLE16_V_M1_MASK
Definition riscv/opcodes.hpp:4096
LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadMin32
@ PseudoMaskedAtomicLoadMin32
Definition riscv/opcodes.hpp:409
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E64_MASK
@ PseudoVFCVT_RM_F_X_V_M4_E64_MASK
Definition riscv/opcodes.hpp:1778
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF8
@ PseudoVSUXSEG8EI64_V_M1_MF8
Definition riscv/opcodes.hpp:11301
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E16_MASK
@ PseudoVFWSUB_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3974
LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M2_MASK
@ PseudoVSE32_V_M2_MASK
Definition riscv/opcodes.hpp:8717
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E8_MASK
@ PseudoVRGATHER_VV_M2_E8_MASK
Definition riscv/opcodes.hpp:8463
LIEF::assembly::riscv::OPCODE::AMOMIN_D_RL
@ AMOMIN_D_RL
Definition riscv/opcodes.hpp:12058
LIEF::assembly::riscv::OPCODE::InsnCSS
@ InsnCSS
Definition riscv/opcodes.hpp:12822
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_M4
@ PseudoVC_V_FPR32V_M4
Definition riscv/opcodes.hpp:1224
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8_TIED
@ PseudoVWSUB_WV_MF8_TIED
Definition riscv/opcodes.hpp:11826
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_M1_MASK
@ PseudoVLUXEI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:5643
LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_MF8
@ PseudoVSPILL3_MF8
Definition riscv/opcodes.hpp:9841
LIEF::assembly::riscv::OPCODE::CV_SRA_SC_H
@ CV_SRA_SC_H
Definition riscv/opcodes.hpp:12436
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M2
@ PseudoVSUB_VX_M2
Definition riscv/opcodes.hpp:10491
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M1
@ PseudoVMFLT_VV_M1
Definition riscv/opcodes.hpp:6772
LIEF::assembly::riscv::OPCODE::FCVT_S_W
@ FCVT_S_W
Definition riscv/opcodes.hpp:12625
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E64_MASK
@ PseudoVFMUL_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:2359
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E32_MASK
@ PseudoVREDOR_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:7923
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_MF8_MASK
@ PseudoVLOXSEG4EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:4643
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M1
@ PseudoVAADD_VV_M1
Definition riscv/opcodes.hpp:549
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF4_MASK
@ PseudoVSUXSEG6EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:11140
LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M8
@ PseudoVGHSH_VV_M8
Definition riscv/opcodes.hpp:4048
LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_MF2
@ PseudoVSPILL4_MF2
Definition riscv/opcodes.hpp:9844
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR64_M1
@ PseudoVMFNE_VFPR64_M1
Definition riscv/opcodes.hpp:6806
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_M1
@ PseudoVLOXSEG8EI16_V_M1_M1
Definition riscv/opcodes.hpp:4930
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M8_MASK
@ PseudoVROR_VV_M8_MASK
Definition riscv/opcodes.hpp:8555
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M8_MASK
@ PseudoVSRA_VI_M8_MASK
Definition riscv/opcodes.hpp:9870
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF2_MASK
@ PseudoVSOXSEG3EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9324
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M4_E32
@ PseudoVFMADD_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2013
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF8
@ PseudoVLSEG7E8FF_V_MF8
Definition riscv/opcodes.hpp:5348
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E64_MASK
@ PseudoVREMU_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:8105
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M8
@ PseudoVMINU_VX_M8
Definition riscv/opcodes.hpp:6846
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M1_MASK
@ PseudoVSOXSEG2EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9208
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M1_MASK
@ PseudoVZEXT_VF8_M1_MASK
Definition riscv/opcodes.hpp:11904
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M1_MASK
@ PseudoVSSRL_VX_M1_MASK
Definition riscv/opcodes.hpp:10234
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E64
@ PseudoVFREDUSUM_VS_M2_E64
Definition riscv/opcodes.hpp:3035
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_MF8
@ PseudoVC_V_X_SE_MF8
Definition riscv/opcodes.hpp:1395
LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_M8
@ PseudoVC_IV_SE_M8
Definition riscv/opcodes.hpp:1135
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_MF2
@ PseudoVLOXSEG2EI64_V_M4_MF2
Definition riscv/opcodes.hpp:4426
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64_V_M2
@ PseudoVLSEG3E64_V_M2
Definition riscv/opcodes.hpp:5160
LIEF::assembly::riscv::OPCODE::FLE_H_INX
@ FLE_H_INX
Definition riscv/opcodes.hpp:12668
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M2
@ PseudoVSOXSEG3EI32_V_M2_M2
Definition riscv/opcodes.hpp:9329
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64FF_V_M1_MASK
@ PseudoVLSEG6E64FF_V_M1_MASK
Definition riscv/opcodes.hpp:5299
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64VV_SE_M8
@ PseudoVC_FPR64VV_SE_M8
Definition riscv/opcodes.hpp:1114
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M2_MASK
@ PseudoVLSEG4E64FF_V_M2_MASK
Definition riscv/opcodes.hpp:5213
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M8_MASK
@ PseudoVMFGE_VFPR64_M8_MASK
Definition riscv/opcodes.hpp:6669
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E32
@ PseudoVFMUL_VV_M8_E32
Definition riscv/opcodes.hpp:2362
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M2_E64
@ PseudoVFNMADD_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2699
LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_M8
@ PseudoVMANDN_MM_M8
Definition riscv/opcodes.hpp:6503
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M2_MASK
@ PseudoVSLIDEUP_VI_M2_MASK
Definition riscv/opcodes.hpp:8853
LIEF::assembly::riscv::OPCODE::C_ZEXT_H
@ C_ZEXT_H
Definition riscv/opcodes.hpp:12549
LIEF::assembly::riscv::OPCODE::FCVT_L_H_INX
@ FCVT_L_H_INX
Definition riscv/opcodes.hpp:12612
LIEF::assembly::riscv::OPCODE::VANDN_VX
@ VANDN_VX
Definition riscv/opcodes.hpp:13153
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF4_E16
@ PseudoVFWSUB_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3963
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_M2
@ PseudoVAESDM_VS_M8_M2
Definition riscv/opcodes.hpp:685
LIEF::assembly::riscv::OPCODE::CV_MAXU_H
@ CV_MAXU_H
Definition riscv/opcodes.hpp:12345
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_MF4
@ PseudoVMERGE_VXM_MF4
Definition riscv/opcodes.hpp:6596
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E16
@ PseudoVREDXOR_VS_MF2_E16
Definition riscv/opcodes.hpp:8040
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M2_M1
@ PseudoVLOXSEG7EI32_V_M2_M1
Definition riscv/opcodes.hpp:4876
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF2_MASK
@ PseudoVMAX_VX_MF2_MASK
Definition riscv/opcodes.hpp:6565
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M4_MASK
@ PseudoVMFEQ_VFPR16_M4_MASK
Definition riscv/opcodes.hpp:6603
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M2_MASK
@ PseudoVLUXEI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:5587
LIEF::assembly::riscv::OPCODE::SH1ADD
@ SH1ADD
Definition riscv/opcodes.hpp:12959
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF4
@ PseudoVSUXSEG7EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:11245
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E8_MASK
@ PseudoVREM_VX_M1_E8_MASK
Definition riscv/opcodes.hpp:8223
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_M4
@ PseudoVAESEF_VS_M4_M4
Definition riscv/opcodes.hpp:709
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF4
@ PseudoVLOXSEG6EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:4780
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M8_MASK
@ PseudoVFSLIDE1UP_VFPR16_M8_MASK
Definition riscv/opcodes.hpp:3338
LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R_DIV8
@ CV_CPLXMUL_R_DIV8
Definition riscv/opcodes.hpp:12280
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E32
@ PseudoVREDSUM_VS_M2_E32
Definition riscv/opcodes.hpp:7974
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF4_E16_MASK
@ PseudoVFMSAC_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:2251
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M1_MASK
@ PseudoVSSEG4E32_V_M1_MASK
Definition riscv/opcodes.hpp:10064
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M1
@ PseudoVLSEG2E8FF_V_M1
Definition riscv/opcodes.hpp:5102
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E16
@ PseudoVREM_VX_M1_E16
Definition riscv/opcodes.hpp:8216
LIEF::assembly::riscv::OPCODE::PseudoVADC_VIM_M1
@ PseudoVADC_VIM_M1
Definition riscv/opcodes.hpp:577
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FSUB
@ G_ATOMICRMW_FSUB
Definition riscv/opcodes.hpp:135
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E16
@ PseudoVFWMACCBF16_VV_M1_E16
Definition riscv/opcodes.hpp:3707
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B2
@ PseudoVMSIF_M_B2
Definition riscv/opcodes.hpp:7069
LIEF::assembly::riscv::OPCODE::InsnB
@ InsnB
Definition riscv/opcodes.hpp:12813
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E64
@ PseudoVREDXOR_VS_M8_E64
Definition riscv/opcodes.hpp:8036
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_MF4
@ PseudoVLOXEI16_V_MF2_MF4
Definition riscv/opcodes.hpp:4210
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF4
@ PseudoVSLIDE1DOWN_VX_MF4
Definition riscv/opcodes.hpp:8804
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M4
@ PseudoVNCLIPU_WX_M4
Definition riscv/opcodes.hpp:7454
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16_MASK_TIED
@ PseudoVFWSUB_WV_M4_E16_MASK_TIED
Definition riscv/opcodes.hpp:4027
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_MF4_MASK
@ PseudoVLOXSEG6EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4807
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_MF2_MASK
@ PseudoVLSEG2E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5089
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF4
@ PseudoVLUXSEG3EI64_V_M2_MF4
Definition riscv/opcodes.hpp:5932
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_MF2_MASK
@ PseudoTHVdotVMAQASU_VV_MF2_MASK
Definition riscv/opcodes.hpp:459
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E64
@ PseudoVREDMINU_VS_M2_E64
Definition riscv/opcodes.hpp:7844
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E64_MASK
@ PseudoVFSUB_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:3432
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_M1
@ PseudoVRELOAD5_M1
Definition riscv/opcodes.hpp:8068
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M4_MASK
@ PseudoVSLIDEDOWN_VX_M4_MASK
Definition riscv/opcodes.hpp:8841
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M4_MASK
@ PseudoVMULHU_VX_M4_MASK
Definition riscv/opcodes.hpp:7324
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF2_E16_MASK
@ PseudoVFSGNJN_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3130
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M2_MASK
@ PseudoVLE16FF_V_M2_MASK
Definition riscv/opcodes.hpp:4086
LIEF::assembly::riscv::OPCODE::CV_CMPEQ_B
@ CV_CMPEQ_B
Definition riscv/opcodes.hpp:12211
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M2
@ PseudoVXOR_VI_M2
Definition riscv/opcodes.hpp:11841
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_M1_MASK
@ PseudoVLSEG6E16FF_V_M1_MASK
Definition riscv/opcodes.hpp:5279
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_MF8
@ PseudoVSBC_VVM_MF8
Definition riscv/opcodes.hpp:8694
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF2_MASK
@ PseudoVSUXEI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:10540
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M8_MASK
@ PseudoTHVdotVMAQAU_VX_M8_MASK
Definition riscv/opcodes.hpp:497
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF4
@ PseudoVLUXSEG8EI64_V_M1_MF4
Definition riscv/opcodes.hpp:6366
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E64
@ PseudoVDIVU_VV_M8_E64
Definition riscv/opcodes.hpp:1451
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M8_MASK
@ PseudoVFSLIDE1UP_VFPR32_M8_MASK
Definition riscv/opcodes.hpp:3350
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E32_MASK
@ PseudoVREDMAXU_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:7763
LIEF::assembly::riscv::OPCODE::VSMUL_VX
@ VSMUL_VX
Definition riscv/opcodes.hpp:13658
LIEF::assembly::riscv::OPCODE::VL2RE16_V
@ VL2RE16_V
Definition riscv/opcodes.hpp:13311
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF8_MASK
@ PseudoVSSEG2E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10026
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF2
@ PseudoVLUXSEG5EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:6156
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E16
@ PseudoVFNMSUB_VV_M1_E16
Definition riscv/opcodes.hpp:2825
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E16_MASK
@ PseudoVFMIN_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:2181
LIEF::assembly::riscv::OPCODE::AMOMIN_H_AQ_RL
@ AMOMIN_H_AQ_RL
Definition riscv/opcodes.hpp:12061
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32_TIED
@ PseudoVFWSUB_WV_M4_E32_TIED
Definition riscv/opcodes.hpp:4032
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E64
@ PseudoVFSUB_VV_M2_E64
Definition riscv/opcodes.hpp:3431
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF2
@ PseudoVSOXSEG6EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:9605
LIEF::assembly::riscv::OPCODE::VLOXEI32_V
@ VLOXEI32_V
Definition riscv/opcodes.hpp:13333
LIEF::assembly::riscv::OPCODE::SLTU
@ SLTU
Definition riscv/opcodes.hpp:12990
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E16_MASK
@ PseudoVREDMAXU_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:7745
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF4_MASK
@ PseudoVSUXSEG8EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:11292
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_MF4
@ PseudoVC_V_FPR16VV_MF4
Definition riscv/opcodes.hpp:1171
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E8
@ PseudoVREDMAXU_VS_MF2_E8
Definition riscv/opcodes.hpp:7780
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_MF2
@ PseudoVSOXSEG6EI16_V_M1_MF2
Definition riscv/opcodes.hpp:9593
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF4
@ PseudoVMSNE_VV_MF4
Definition riscv/opcodes.hpp:7245
LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_M1
@ PseudoVC_I_SE_M1
Definition riscv/opcodes.hpp:1139
LIEF::assembly::riscv::OPCODE::CSRRS
@ CSRRS
Definition riscv/opcodes.hpp:12155
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E16
@ PseudoVRGATHER_VV_M1_E16
Definition riscv/opcodes.hpp:8448
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E64_MASK
@ PseudoVFSUB_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:3426
LIEF::assembly::riscv::OPCODE::VMSLE_VI
@ VMSLE_VI
Definition riscv/opcodes.hpp:13537
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_M1
@ PseudoVFNRCLIP_XU_F_QF_M1
Definition riscv/opcodes.hpp:2855
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF2
@ PseudoVLUXSEG3EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:5878
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16_MASK
@ PseudoVFWSUB_WV_M4_E16_MASK
Definition riscv/opcodes.hpp:4026
LIEF::assembly::riscv::OPCODE::SRAW
@ SRAW
Definition riscv/opcodes.hpp:12998
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M4_MASK
@ PseudoVRGATHER_VX_M4_MASK
Definition riscv/opcodes.hpp:8497
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF4_MASK
@ PseudoVSUXSEG6EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:11172
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M2_M1
@ PseudoVLUXSEG7EI16_V_M2_M1
Definition riscv/opcodes.hpp:6246
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF8_MASK
@ PseudoVSOXEI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:9154
LIEF::assembly::riscv::OPCODE::G_PTRAUTH_GLOBAL_VALUE
@ G_PTRAUTH_GLOBAL_VALUE
Definition riscv/opcodes.hpp:91
LIEF::assembly::riscv::OPCODE::AMOMAXU_H_AQ
@ AMOMAXU_H_AQ
Definition riscv/opcodes.hpp:12012
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M1
@ PseudoVSUXEI64_V_M8_M1
Definition riscv/opcodes.hpp:10607
LIEF::assembly::riscv::OPCODE::G_FMUL
@ G_FMUL
Definition riscv/opcodes.hpp:198
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E16
@ PseudoVFWCVT_F_F_V_M1_E16
Definition riscv/opcodes.hpp:3559
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E64
@ PseudoVFNMSAC_VV_M8_E64
Definition riscv/opcodes.hpp:2787
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_M1_MASK
@ PseudoVSOXSEG5EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9560
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E16
@ PseudoVREM_VX_M4_E16
Definition riscv/opcodes.hpp:8232
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16_MASK_TIED
@ PseudoVFWSUB_WV_M2_E16_MASK_TIED
Definition riscv/opcodes.hpp:4019
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M4_E32_MASK
@ PseudoVFSUB_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3408
LIEF::assembly::riscv::OPCODE::VMNOR_MM
@ VMNOR_MM
Definition riscv/opcodes.hpp:13518
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF8_MASK
@ PseudoVLOXEI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:4219
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E8
@ PseudoVFWCVT_F_X_V_M1_E8
Definition riscv/opcodes.hpp:3611
LIEF::assembly::riscv::OPCODE::AMOCAS_H_AQ_RL
@ AMOCAS_H_AQ_RL
Definition riscv/opcodes.hpp:11993
LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M1
@ PseudoVSM3C_VI_M1
Definition riscv/opcodes.hpp:8920
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_MF2_E32_MASK
@ PseudoVFNMADD_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2696
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M4
@ PseudoVSSRA_VV_M4
Definition riscv/opcodes.hpp:10181
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_M1
@ PseudoVC_V_IVW_M1
Definition riscv/opcodes.hpp:1262
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M4_MASK
@ PseudoVNSRL_WI_M4_MASK
Definition riscv/opcodes.hpp:7595
LIEF::assembly::riscv::OPCODE::CLZ
@ CLZ
Definition riscv/opcodes.hpp:12141
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E32_MASK
@ PseudoVFDIV_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:1896
LIEF::assembly::riscv::OPCODE::G_CTLZ_ZERO_UNDEF
@ G_CTLZ_ZERO_UNDEF
Definition riscv/opcodes.hpp:258
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M1
@ PseudoVLOXSEG3EI8_V_MF4_M1
Definition riscv/opcodes.hpp:4564
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M2
@ PseudoVLOXSEG4EI64_V_M2_M2
Definition riscv/opcodes.hpp:4646
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_M1
@ PseudoVLUXSEG5EI32_V_M2_M1
Definition riscv/opcodes.hpp:6108
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF4
@ PseudoVSUXEI16_V_MF4_MF4
Definition riscv/opcodes.hpp:10541
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M1_MASK
@ PseudoVMULH_VX_M1_MASK
Definition riscv/opcodes.hpp:7348
LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SC_H
@ CV_CMPLEU_SC_H
Definition riscv/opcodes.hpp:12246
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF2_MASK
@ PseudoVSOXSEG2EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9238
LIEF::assembly::riscv::OPCODE::FMSUB_S
@ FMSUB_S
Definition riscv/opcodes.hpp:12718
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M1
@ PseudoVSOXSEG3EI16_V_MF2_M1
Definition riscv/opcodes.hpp:9303
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_MF4
@ PseudoVAESEF_VS_M8_MF4
Definition riscv/opcodes.hpp:717
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M2
@ PseudoVWSUB_WX_M2
Definition riscv/opcodes.hpp:11829
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M4_MASK
@ PseudoVSSEG2E64_V_M4_MASK
Definition riscv/opcodes.hpp:10014
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF4_MASK
@ PseudoVSUB_VV_MF4_MASK
Definition riscv/opcodes.hpp:10486
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M2
@ PseudoVLOXSEG4EI16_V_MF2_M2
Definition riscv/opcodes.hpp:4594
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M4
@ PseudoVSOXEI16_V_M2_M4
Definition riscv/opcodes.hpp:9011
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M2_MASK
@ PseudoVFWCVT_RTZ_XU_F_V_M2_MASK
Definition riscv/opcodes.hpp:3660
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M4
@ PseudoVLOXSEG2EI16_V_M4_M4
Definition riscv/opcodes.hpp:4350
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF8
@ PseudoVMACC_VV_MF8
Definition riscv/opcodes.hpp:6414
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B2
@ PseudoVMSOF_M_B2
Definition riscv/opcodes.hpp:7267
LIEF::assembly::riscv::OPCODE::G_UMIN
@ G_UMIN
Definition riscv/opcodes.hpp:240
LIEF::assembly::riscv::OPCODE::CV_ABS_B
@ CV_ABS_B
Definition riscv/opcodes.hpp:12162
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E32_MASK
@ PseudoVFWMACCBF16_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3718
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF2_MASK
@ PseudoVLSEG3E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5177
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M4_MASK
@ PseudoVSUXEI32_V_M8_M4_MASK
Definition riscv/opcodes.hpp:10572
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_MF2
@ PseudoVMADC_VX_MF2
Definition riscv/opcodes.hpp:6469
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF4_MASK
@ PseudoVSUXSEG4EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:10976
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF2
@ PseudoVSOXSEG7EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:9745
LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M8
@ PseudoVLSE32_V_M8
Definition riscv/opcodes.hpp:5028
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M1_E32_MASK
@ PseudoVFMAX_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2070
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_MF4
@ PseudoVC_V_XVW_MF4
Definition riscv/opcodes.hpp:1360
LIEF::assembly::riscv::OPCODE::ORI
@ ORI
Definition riscv/opcodes.hpp:12908
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M4_MASK
@ PseudoVMFLE_VV_M4_MASK
Definition riscv/opcodes.hpp:6735
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_M2_MASK
@ PseudoVSSEG4E32_V_M2_MASK
Definition riscv/opcodes.hpp:10066
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M2_M2_MASK
@ PseudoVLUXSEG4EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:6059
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E32_MASK
@ PseudoVFWMACC_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3760
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_M1
@ PseudoVC_V_FPR16VV_M1
Definition riscv/opcodes.hpp:1166
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E32_MASK
@ PseudoVFWCVT_F_F_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:3574
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_MF4
@ PseudoVSUXSEG3EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:10895
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M4
@ PseudoVASUBU_VV_M4
Definition riscv/opcodes.hpp:864
LIEF::assembly::riscv::OPCODE::G_FNEG
@ G_FNEG
Definition riscv/opcodes.hpp:213
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF4_MASK
@ PseudoVSUXSEG8EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:11326
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M2
@ PseudoVLSEG2E64FF_V_M2
Definition riscv/opcodes.hpp:5092
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M4
@ PseudoVNCLIP_WX_M4
Definition riscv/opcodes.hpp:7490
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M2
@ PseudoVWADD_VV_M2
Definition riscv/opcodes.hpp:11397
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E64_V_M1
@ PseudoVLSSEG6E64_V_M1
Definition riscv/opcodes.hpp:5520
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M1
@ PseudoVNCLIP_WI_M1
Definition riscv/opcodes.hpp:7462
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M8
@ PseudoVSLIDE1UP_VX_M8
Definition riscv/opcodes.hpp:8814
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK
@ PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK
Definition riscv/opcodes.hpp:2550
LIEF::assembly::riscv::OPCODE::VFWCVT_X_F_V
@ VFWCVT_X_F_V
Definition riscv/opcodes.hpp:13283
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF8_MASK
@ PseudoVLUXSEG2EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:5761
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M1_M1_MASK
@ PseudoVLOXSEG4EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4637
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF2
@ PseudoVSMUL_VV_MF2
Definition riscv/opcodes.hpp:8972
LIEF::assembly::riscv::OPCODE::G_INTTOPTR
@ G_INTTOPTR
Definition riscv/opcodes.hpp:101
LIEF::assembly::riscv::OPCODE::PseudoCCORI
@ PseudoCCORI
Definition riscv/opcodes.hpp:350
LIEF::assembly::riscv::OPCODE::VAESEF_VV
@ VAESEF_VV
Definition riscv/opcodes.hpp:13146
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_MF2_E8
@ PseudoVREDMIN_VS_MF2_E8
Definition riscv/opcodes.hpp:7912
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M4_MASK
@ PseudoVMFLE_VFPR64_M4_MASK
Definition riscv/opcodes.hpp:6727
LIEF::assembly::riscv::OPCODE::G_INTRINSIC_FPTRUNC_ROUND
@ G_INTRINSIC_FPTRUNC_ROUND
Definition riscv/opcodes.hpp:105
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF8
@ PseudoVMSLE_VX_MF8
Definition riscv/opcodes.hpp:7161
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M2
@ PseudoVSSSEG2E32_V_M2
Definition riscv/opcodes.hpp:10259
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF2_MASK
@ PseudoVLOXSEG7EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4885
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF4
@ PseudoVLUXSEG6EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:6232
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E32_MASK
@ PseudoVFWNMACC_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3864
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_M1
@ PseudoVSUXSEG7EI64_V_M2_M1
Definition riscv/opcodes.hpp:11223
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF4_MASK
@ PseudoVSOXSEG5EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9536
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_M1_MASK
@ PseudoVLOXSEG7EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4863
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_M1_MASK
@ PseudoVLUXSEG6EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6225
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M8_E32
@ PseudoVFRDIV_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2893
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_MF2_MASK
@ PseudoTHVdotVMAQAU_VX_MF2_MASK
Definition riscv/opcodes.hpp:499
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVV_SE_M1
@ PseudoVC_V_IVV_SE_M1
Definition riscv/opcodes.hpp:1255
LIEF::assembly::riscv::OPCODE::FMSUB_D_INX
@ FMSUB_D_INX
Definition riscv/opcodes.hpp:12715
LIEF::assembly::riscv::OPCODE::VLSSEG5E16_V
@ VLSSEG5E16_V
Definition riscv/opcodes.hpp:13436
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M4_MASK
@ PseudoVSOXEI32_V_M2_M4_MASK
Definition riscv/opcodes.hpp:9054
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_M2
@ PseudoVLUXSEG4EI64_V_M2_M2
Definition riscv/opcodes.hpp:6038
LIEF::assembly::riscv::OPCODE::VC_VVV
@ VC_VVV
Definition riscv/opcodes.hpp:13180
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_M1
@ PseudoVSOXSEG3EI8_V_MF8_M1
Definition riscv/opcodes.hpp:9393
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M2
@ PseudoVMACC_VV_M2
Definition riscv/opcodes.hpp:6404
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E32
@ PseudoVFADD_VV_M8_E32
Definition riscv/opcodes.hpp:1649
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E32
@ PseudoVFWCVT_F_XU_V_M1_E32
Definition riscv/opcodes.hpp:3579
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_M1
@ PseudoVLOXSEG8EI32_V_MF2_M1
Definition riscv/opcodes.hpp:4962
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E64_MASK
@ PseudoVDIVU_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:1428
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E64_V_M1_MASK
@ PseudoVSSSEG7E64_V_M1_MASK
Definition riscv/opcodes.hpp:10390
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E16_MASK
@ PseudoVFSUB_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3422
LIEF::assembly::riscv::OPCODE::Select_FPR64_Using_CC_GPR
@ Select_FPR64_Using_CC_GPR
Definition riscv/opcodes.hpp:11922
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M8
@ PseudoVSOXEI16_V_M2_M8
Definition riscv/opcodes.hpp:9013
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M1_MASK
@ PseudoVMFEQ_VV_M1_MASK
Definition riscv/opcodes.hpp:6629
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M2_MASK
@ PseudoVWSUBU_WX_M2_MASK
Definition riscv/opcodes.hpp:11770
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E8
@ PseudoVREM_VX_MF4_E8
Definition riscv/opcodes.hpp:8256
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF8
@ PseudoVCLMULH_VV_MF8
Definition riscv/opcodes.hpp:956
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E16
@ PseudoVFDIV_VV_M1_E16
Definition riscv/opcodes.hpp:1893
LIEF::assembly::riscv::OPCODE::BEXT
@ BEXT
Definition riscv/opcodes.hpp:12122
LIEF::assembly::riscv::OPCODE::TH_SDIA
@ TH_SDIA
Definition riscv/opcodes.hpp:13105
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M1_MASK
@ PseudoVLSEG2E16_V_M1_MASK
Definition riscv/opcodes.hpp:5065
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF8_MASK
@ PseudoVSOXSEG5EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:9590
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF4
@ PseudoVLOXSEG5EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:4706
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_M1_MASK
@ PseudoVSSEG7E32_V_M1_MASK
Definition riscv/opcodes.hpp:10130
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M1_E32_MASK
@ PseudoVFWNMACC_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3850
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF8_MASK
@ PseudoVLSEG7E8FF_V_MF8_MASK
Definition riscv/opcodes.hpp:5349
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E64_MASK
@ PseudoVREDMAXU_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:7773
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M2
@ PseudoVSOXSEG4EI8_V_MF2_M2
Definition riscv/opcodes.hpp:9491
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E16_MASK
@ PseudoVFSGNJN_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:3170
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_MF2_E32_MASK
@ PseudoVFWMACC_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3748
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M4
@ PseudoVLUXEI32_V_M8_M4
Definition riscv/opcodes.hpp:5638
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M4_MASK
@ PseudoVMSGTU_VX_M4_MASK
Definition riscv/opcodes.hpp:7028
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_MF4
@ PseudoVC_V_VVW_SE_MF4
Definition riscv/opcodes.hpp:1326
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M1_MF8_MASK
@ PseudoVSOXSEG5EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:9558
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E16
@ PseudoVFREDUSUM_VS_MF2_E16
Definition riscv/opcodes.hpp:3049
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E8_MASK
@ PseudoVDIVU_VX_MF4_E8_MASK
Definition riscv/opcodes.hpp:1508
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M2_M1_MASK
@ PseudoVLOXSEG4EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4617
LIEF::assembly::riscv::OPCODE::THVdotVMAQAU_VV
@ THVdotVMAQAU_VV
Definition riscv/opcodes.hpp:13023
LIEF::assembly::riscv::OPCODE::REV8_RV32
@ REV8_RV32
Definition riscv/opcodes.hpp:12928
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_M1
@ PseudoVSSSEG8E8_V_M1
Definition riscv/opcodes.hpp:10411
LIEF::assembly::riscv::OPCODE::VFWCVT_RTZ_X_F_V
@ VFWCVT_RTZ_X_F_V
Definition riscv/opcodes.hpp:13281
LIEF::assembly::riscv::OPCODE::TH_SHIA
@ TH_SHIA
Definition riscv/opcodes.hpp:13108
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF8
@ PseudoVLSSEG3E8_V_MF8
Definition riscv/opcodes.hpp:5460
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M1_MASK
@ PseudoVSOXSEG4EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9466
LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_2x8x2_M8
@ PseudoVQMACCU_2x8x2_M8
Definition riscv/opcodes.hpp:7687
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF8_MASK
@ PseudoVSOXEI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:9040
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E16
@ PseudoVREDMAX_VS_M2_E16
Definition riscv/opcodes.hpp:7796
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF4_M1
@ PseudoVSOXSEG5EI16_V_MF4_M1
Definition riscv/opcodes.hpp:9523
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E64
@ PseudoVREDOR_VS_M8_E64
Definition riscv/opcodes.hpp:7948
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M4_MASK
@ PseudoVMULHSU_VX_M4_MASK
Definition riscv/opcodes.hpp:7296
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M2_MASK
@ PseudoVLUXSEG4EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:5975
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E16
@ PseudoVFMIN_VV_M8_E16
Definition riscv/opcodes.hpp:2180
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M4
@ PseudoVSADD_VX_M4
Definition riscv/opcodes.hpp:8678
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_M1
@ PseudoVLOXSEG8EI16_V_MF4_M1
Definition riscv/opcodes.hpp:4942
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M4_MASK
@ PseudoVRGATHEREI16_VV_M8_E32_M4_MASK
Definition riscv/opcodes.hpp:8379
LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_MF4
@ PseudoVC_IV_SE_MF4
Definition riscv/opcodes.hpp:1137
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M2
@ PseudoVLE8FF_V_M2
Definition riscv/opcodes.hpp:4145
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF2
@ PseudoVXOR_VI_MF2
Definition riscv/opcodes.hpp:11847
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M2_MASK
@ PseudoVSOXEI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9098
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E8
@ PseudoVREDMAX_VS_M8_E8
Definition riscv/opcodes.hpp:7818
LIEF::assembly::riscv::OPCODE::TH_FF1
@ TH_FF1
Definition riscv/opcodes.hpp:13045
LIEF::assembly::riscv::OPCODE::VMANDN_MM
@ VMANDN_MM
Definition riscv/opcodes.hpp:13494
LIEF::assembly::riscv::OPCODE::VNSRA_WX
@ VNSRA_WX
Definition riscv/opcodes.hpp:13579
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF4
@ PseudoVMAXU_VX_MF4
Definition riscv/opcodes.hpp:6538
LIEF::assembly::riscv::OPCODE::CV_AVG_SC_H
@ CV_AVG_SC_H
Definition riscv/opcodes.hpp:12198
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E64
@ PseudoVFREDUSUM_VS_M1_E64
Definition riscv/opcodes.hpp:3029
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E32
@ PseudoVFWMUL_VV_M1_E32
Definition riscv/opcodes.hpp:3823
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M2_E64_MASK
@ PseudoVFRDIV_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2900
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF8
@ PseudoVSRL_VI_MF8
Definition riscv/opcodes.hpp:9917
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M2
@ PseudoVSSSEG3E16_V_M2
Definition riscv/opcodes.hpp:10285
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E64_MASK
@ PseudoVFSGNJX_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:3216
LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadMax32
@ PseudoMaskedAtomicLoadMax32
Definition riscv/opcodes.hpp:408
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M2
@ PseudoVLUXSEG3EI64_V_M4_M2
Definition riscv/opcodes.hpp:5936
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M8_E64_MASK
@ PseudoVFNMACC_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2644
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF4
@ PseudoVLOXSEG5EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:4726
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E64
@ PseudoVREM_VV_M8_E64
Definition riscv/opcodes.hpp:8200
LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SC_B
@ CV_CMPGEU_SC_B
Definition riscv/opcodes.hpp:12221
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF8
@ PseudoVLSSEG6E8_V_MF8
Definition riscv/opcodes.hpp:5528
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_MF2_MASK
@ PseudoVLSEG8E32FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5373
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF8
@ PseudoVSLIDEUP_VI_MF8
Definition riscv/opcodes.hpp:8862
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M1
@ PseudoVSOXEI8_V_MF2_M1
Definition riscv/opcodes.hpp:9131
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M2_E64_MASK
@ PseudoVFADD_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:1624
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4_MASK_TIED
@ PseudoVWSUB_WV_MF4_MASK_TIED
Definition riscv/opcodes.hpp:11821
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_M1
@ PseudoVLOXSEG5EI16_V_M1_M1
Definition riscv/opcodes.hpp:4690
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E32_MASK
@ PseudoVWREDSUMU_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:11638
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E64
@ PseudoVFMADD_VV_M8_E64
Definition riscv/opcodes.hpp:2049
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M2
@ PseudoVADD_VI_M2
Definition riscv/opcodes.hpp:600
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF2
@ PseudoVSUXSEG5EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:11083
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M2_MASK
@ PseudoVRGATHEREI16_VV_M2_E16_M2_MASK
Definition riscv/opcodes.hpp:8309
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E32
@ PseudoVWREDSUMU_VS_M4_E32
Definition riscv/opcodes.hpp:11625
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF2
@ PseudoVSOXSEG3EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:9313
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF4
@ PseudoVSUXSEG6EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:11131
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M4_MASK
@ PseudoVSUXSEG2EI16_V_M2_M4_MASK
Definition riscv/opcodes.hpp:10672
LIEF::assembly::riscv::OPCODE::VFCVT_RTZ_XU_F_V
@ VFCVT_RTZ_XU_F_V
Definition riscv/opcodes.hpp:13209
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M2_E32
@ PseudoVFMACC_VFPR32_M2_E32
Definition riscv/opcodes.hpp:1951
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M2
@ PseudoVNSRL_WI_M2
Definition riscv/opcodes.hpp:7592
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M4_MASK
@ PseudoVWSUBU_WX_M4_MASK
Definition riscv/opcodes.hpp:11772
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_M1_MASK
@ PseudoVLOXEI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:4327
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF8
@ PseudoVSLL_VX_MF8
Definition riscv/opcodes.hpp:8918
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M1_MASK
@ PseudoVLOXSEG3EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4477
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M2
@ PseudoVLUXSEG2EI64_V_M2_M2
Definition riscv/opcodes.hpp:5806
LIEF::assembly::riscv::OPCODE::VLSEG5E16_V
@ VLSEG5E16_V
Definition riscv/opcodes.hpp:13393
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF4_MASK
@ PseudoVSUXSEG3EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:10866
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M1
@ PseudoVMSBC_VXM_M1
Definition riscv/opcodes.hpp:6924
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M4
@ PseudoVAADD_VX_M4
Definition riscv/opcodes.hpp:567
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_M1_MASK
@ PseudoVLUXSEG8EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6355
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M1_MASK
@ PseudoVLSSEG2E8_V_M1_MASK
Definition riscv/opcodes.hpp:5423
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK
@ PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK
Definition riscv/opcodes.hpp:8431
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M4_M1
@ PseudoVLUXSEG8EI32_V_M4_M1
Definition riscv/opcodes.hpp:6352
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF4_MASK
@ PseudoVFWCVT_X_F_V_MF4_MASK
Definition riscv/opcodes.hpp:3696
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF8_MASK
@ PseudoVSSRL_VV_MF8_MASK
Definition riscv/opcodes.hpp:10232
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF4
@ PseudoVSUXSEG8EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:11271
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M2_MASK
@ PseudoVLUXEI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:5615
LIEF::assembly::riscv::OPCODE::CV_SHUFFLE2_B
@ CV_SHUFFLE2_B
Definition riscv/opcodes.hpp:12411
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E32
@ PseudoVDIV_VV_M2_E32
Definition riscv/opcodes.hpp:1521
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E64
@ PseudoVFMAX_VV_M4_E64
Definition riscv/opcodes.hpp:2103
LIEF::assembly::riscv::OPCODE::MOPR27
@ MOPR27
Definition riscv/opcodes.hpp:12880
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M2
@ PseudoVLOXSEG3EI16_V_M1_M2
Definition riscv/opcodes.hpp:4472
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M1_MASK
@ PseudoVNMSUB_VV_M1_MASK
Definition riscv/opcodes.hpp:7527
LIEF::assembly::riscv::OPCODE::VMADC_VXM
@ VMADC_VXM
Definition riscv/opcodes.hpp:13491
LIEF::assembly::riscv::OPCODE::VSOXSEG3EI64_V
@ VSOXSEG3EI64_V
Definition riscv/opcodes.hpp:13670
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M1_E32
@ PseudoVFSUB_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3403
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M8_M1
@ PseudoVSUXSEG5EI64_V_M8_M1
Definition riscv/opcodes.hpp:11073
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF8_MASK
@ PseudoVWADD_VV_MF8_MASK
Definition riscv/opcodes.hpp:11406
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M4_MASK
@ PseudoVSSEG2E8_V_M4_MASK
Definition riscv/opcodes.hpp:10020
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M4
@ PseudoVSLIDEUP_VX_M4
Definition riscv/opcodes.hpp:8868
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M1_MASK
@ PseudoVLOXSEG2EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:4429
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF4_E16_MASK
@ PseudoVFWMACCBF16_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3724
LIEF::assembly::riscv::OPCODE::CV_DOTUP_B
@ CV_DOTUP_B
Definition riscv/opcodes.hpp:12287
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_M2
@ PseudoVC_V_XVW_SE_M2
Definition riscv/opcodes.hpp:1363
LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_MF2
@ PseudoVC_XV_SE_MF2
Definition riscv/opcodes.hpp:1413
LIEF::assembly::riscv::OPCODE::VQMACCUS_2x8x2
@ VQMACCUS_2x8x2
Definition riscv/opcodes.hpp:13588
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_MF2_E32
@ PseudoVFWSUB_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3971
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B32_MASK
@ PseudoVCPOP_M_B32_MASK
Definition riscv/opcodes.hpp:1043
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E32_MASK
@ PseudoVFSQRT_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:3388
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M1_MASK
@ PseudoVSSEG2E64_V_M1_MASK
Definition riscv/opcodes.hpp:10010
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF4_MASK
@ PseudoVLSSEG4E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5469
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M2
@ PseudoVRGATHER_VX_M2
Definition riscv/opcodes.hpp:8494
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF8
@ PseudoVMINU_VV_MF8
Definition riscv/opcodes.hpp:6838
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E16
@ PseudoVREDMAX_VS_MF4_E16
Definition riscv/opcodes.hpp:7826
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF2
@ PseudoVSSRL_VV_MF2
Definition riscv/opcodes.hpp:10227
LIEF::assembly::riscv::OPCODE::VFREC7_V
@ VFREC7_V
Definition riscv/opcodes.hpp:13254
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M1_MASK
@ PseudoVLUXEI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:5579
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M4
@ PseudoVSUXSEG2EI8_V_M2_M4
Definition riscv/opcodes.hpp:10767
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF4_E16
@ PseudoVFMSUB_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2262
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF8_MASK
@ PseudoVMSNE_VV_MF8_MASK
Definition riscv/opcodes.hpp:7248
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_MF2_MASK
@ PseudoVLOXSEG2EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:4427
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF8
@ PseudoVSUXSEG2EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:10727
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_M2_MASK
@ PseudoVWMACCUS_VX_M2_MASK
Definition riscv/opcodes.hpp:11482
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E64_MASK
@ PseudoVFMAX_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:2104
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E64_MASK
@ PseudoVFSQRT_V_M8_E64_MASK
Definition riscv/opcodes.hpp:3384
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M8_E32
@ PseudoVFMSUB_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2270
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF2
@ PseudoVLSSEG3E8_V_MF2
Definition riscv/opcodes.hpp:5456
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_MF2_MASK
@ PseudoVLSSEG3E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5447
LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_MF2
@ PseudoVC_VV_SE_MF2
Definition riscv/opcodes.hpp:1163
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_MF2
@ PseudoVC_V_VVV_SE_MF2
Definition riscv/opcodes.hpp:1313
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_MF2_MF8
@ PseudoVAESEM_VS_MF2_MF8
Definition riscv/opcodes.hpp:750
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF4
@ PseudoVSLIDEUP_VI_MF4
Definition riscv/opcodes.hpp:8860
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF2
@ PseudoVCLMULH_VX_MF2
Definition riscv/opcodes.hpp:966
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M8_M2_MASK
@ PseudoVLOXSEG4EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:4627
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E32
@ PseudoVFNCVT_ROD_F_F_W_MF2_E32
Definition riscv/opcodes.hpp:2563
LIEF::assembly::riscv::OPCODE::BSETI
@ BSETI
Definition riscv/opcodes.hpp:12133
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF2_MASK
@ PseudoVSLIDEUP_VX_MF2_MASK
Definition riscv/opcodes.hpp:8873
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E8
@ PseudoVDIV_VX_M4_E8
Definition riscv/opcodes.hpp:1577
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E8_MASK
@ PseudoVRGATHER_VV_M8_E8_MASK
Definition riscv/opcodes.hpp:8479
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M4
@ PseudoVFMV_V_FPR32_M4
Definition riscv/opcodes.hpp:2410
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E32
@ PseudoVFSGNJN_VV_M2_E32
Definition riscv/opcodes.hpp:3159
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M4
@ PseudoVFMV_V_FPR64_M4
Definition riscv/opcodes.hpp:2415
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF8
@ PseudoVMSGT_VX_MF8
Definition riscv/opcodes.hpp:7063
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF4_MASK
@ PseudoVSUXSEG6EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:11166
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_MF4_MASK
@ PseudoVSSEG3E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10034
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_M1_MASK
@ PseudoVSOXSEG6EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9612
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VW_SE_M4
@ PseudoVC_FPR32VW_SE_M4
Definition riscv/opcodes.hpp:1103
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M1_MASK
@ PseudoVWMACCU_VX_M1_MASK
Definition riscv/opcodes.hpp:11504
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF8_MASK
@ PseudoVSRL_VV_MF8_MASK
Definition riscv/opcodes.hpp:9932
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M1_E16
@ PseudoVFWNMACC_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3839
LIEF::assembly::riscv::OPCODE::FMSUB_S_INX
@ FMSUB_S_INX
Definition riscv/opcodes.hpp:12719
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M8_M4
@ PseudoVSUXSEG2EI16_V_M8_M4
Definition riscv/opcodes.hpp:10677
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M4_MASK
@ PseudoVFCVT_RM_XU_F_V_M4_MASK
Definition riscv/opcodes.hpp:1796
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_MF4
@ PseudoVAESDF_VS_M4_MF4
Definition riscv/opcodes.hpp:653
LIEF::assembly::riscv::OPCODE::PseudoLHU
@ PseudoLHU
Definition riscv/opcodes.hpp:395
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF2
@ PseudoVLOXSEG4EI32_V_M1_MF2
Definition riscv/opcodes.hpp:4612
LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadSub32
@ PseudoMaskedAtomicLoadSub32
Definition riscv/opcodes.hpp:411
LIEF::assembly::riscv::OPCODE::VAESEM_VS
@ VAESEM_VS
Definition riscv/opcodes.hpp:13147
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M2_E32
@ PseudoVFWREDOSUM_VS_M2_E32
Definition riscv/opcodes.hpp:3917
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_MF2_MASK
@ PseudoVLOXSEG2EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4385
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E8_MASK
@ PseudoVWREDSUM_VS_M2_E8_MASK
Definition riscv/opcodes.hpp:11658
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF2_MASK
@ PseudoVMUL_VV_MF2_MASK
Definition riscv/opcodes.hpp:7370
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M4_MASK
@ PseudoVNCLIPU_WI_M4_MASK
Definition riscv/opcodes.hpp:7431
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M1_MASK
@ PseudoVMFEQ_VFPR16_M1_MASK
Definition riscv/opcodes.hpp:6599
LIEF::assembly::riscv::OPCODE::C_MV_HINT
@ C_MV_HINT
Definition riscv/opcodes.hpp:12522
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF8_MASK
@ PseudoVWMACCSU_VX_MF8_MASK
Definition riscv/opcodes.hpp:11478
LIEF::assembly::riscv::OPCODE::XOR
@ XOR
Definition riscv/opcodes.hpp:13848
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32_V_MF2_MASK
@ PseudoVLSEG6E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5297
LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B16
@ PseudoVLM_V_B16
Definition riscv/opcodes.hpp:4172
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF8
@ PseudoVLUXSEG6EI64_V_M1_MF8
Definition riscv/opcodes.hpp:6208
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E32_MASK
@ PseudoVFSQRT_V_M4_E32_MASK
Definition riscv/opcodes.hpp:3376
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M4_MASK
@ PseudoVSSRL_VV_M4_MASK
Definition riscv/opcodes.hpp:10224
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M4_MASK
@ PseudoVMFNE_VV_M4_MASK
Definition riscv/opcodes.hpp:6819
LIEF::assembly::riscv::OPCODE::TH_DCACHE_IALL
@ TH_DCACHE_IALL
Definition riscv/opcodes.hpp:13038
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E32
@ PseudoVFMACC_VV_M8_E32
Definition riscv/opcodes.hpp:1987
LIEF::assembly::riscv::OPCODE::G_FLOG2
@ G_FLOG2
Definition riscv/opcodes.hpp:209
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF4
@ PseudoVLSEG5E16FF_V_MF4
Definition riscv/opcodes.hpp:5242
LIEF::assembly::riscv::OPCODE::G_INDEXED_STORE
@ G_INDEXED_STORE
Definition riscv/opcodes.hpp:120
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_M1_MASK
@ PseudoVSUXSEG5EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11036
LIEF::assembly::riscv::OPCODE::CV_PACKLO_B
@ CV_PACKLO_B
Definition riscv/opcodes.hpp:12387
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF4_MASK
@ PseudoVROR_VX_MF4_MASK
Definition riscv/opcodes.hpp:8573
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_M1
@ PseudoVLSSEG6E8_V_M1
Definition riscv/opcodes.hpp:5522
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF2_MASK
@ PseudoVMSLTU_VV_MF2_MASK
Definition riscv/opcodes.hpp:7173
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E32
@ PseudoVREDOR_VS_MF2_E32
Definition riscv/opcodes.hpp:7954
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_M4
@ PseudoVC_V_IVW_M4
Definition riscv/opcodes.hpp:1264
LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M4
@ PseudoVSM3C_VI_M4
Definition riscv/opcodes.hpp:8922
LIEF::assembly::riscv::OPCODE::SH_AQ_RL
@ SH_AQ_RL
Definition riscv/opcodes.hpp:12979
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF2_MASK
@ PseudoVWSUBU_VX_MF2_MASK
Definition riscv/opcodes.hpp:11738
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M1_E64
@ PseudoVFMAX_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2079
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M4
@ PseudoVOR_VX_M4
Definition riscv/opcodes.hpp:7658
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF4_MASK
@ PseudoVLSEG8E8FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5387
LIEF::assembly::riscv::OPCODE::FMIN_H
@ FMIN_H
Definition riscv/opcodes.hpp:12709
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_M1_MASK
@ PseudoVSOXSEG8EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9800
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF4_MASK
@ PseudoVSLIDE1DOWN_VX_MF4_MASK
Definition riscv/opcodes.hpp:8805
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M1_E32
@ PseudoVFMIN_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2144
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMAX
@ G_VECREDUCE_FMAX
Definition riscv/opcodes.hpp:304
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M2_E16_MASK
@ PseudoVFWSUB_WFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3994
LIEF::assembly::riscv::OPCODE::VREDSUM_VS
@ VREDSUM_VS
Definition riscv/opcodes.hpp:13600
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_M1_MASK
@ PseudoVLUXSEG8EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6343
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M1_MASK
@ PseudoVNSRL_WV_M1_MASK
Definition riscv/opcodes.hpp:7603
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF2_MASK
@ PseudoVSUXSEG4EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10956
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M2_M1
@ PseudoVSOXSEG6EI16_V_M2_M1
Definition riscv/opcodes.hpp:9595
LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M1_MASK
@ PseudoVSE32_V_M1_MASK
Definition riscv/opcodes.hpp:8715
LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_MF8
@ PseudoVSPILL7_MF8
Definition riscv/opcodes.hpp:9858
LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VX
@ PseudoVMSGE_VX
Definition riscv/opcodes.hpp:7006
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M1
@ PseudoVSRA_VX_M1
Definition riscv/opcodes.hpp:9891
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF4_MASK
@ PseudoVLSSEG8E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5567
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M4
@ PseudoVLOXSEG2EI8_V_M2_M4
Definition riscv/opcodes.hpp:4442
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M4_E16_MASK
@ PseudoVFWADD_WFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3492
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E64
@ PseudoVFDIV_VV_M4_E64
Definition riscv/opcodes.hpp:1909
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_MF4
@ PseudoVAESEF_VS_M2_MF4
Definition riscv/opcodes.hpp:705
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M4
@ PseudoVMFNE_VFPR16_M4
Definition riscv/opcodes.hpp:6788
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M1_MASK
@ PseudoVSOXSEG2EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9200
LIEF::assembly::riscv::OPCODE::CV_OR_SCI_H
@ CV_OR_SCI_H
Definition riscv/opcodes.hpp:12382
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E32
@ PseudoVREM_VX_M8_E32
Definition riscv/opcodes.hpp:8242
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E64_MASK
@ PseudoVFMIN_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:2173
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF4_E16_MASK
@ PseudoVFMIN_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:2191
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_M1_MASK
@ PseudoVSRA_VX_M1_MASK
Definition riscv/opcodes.hpp:9892
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF2
@ PseudoVLUXSEG7EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:6250
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_M1
@ PseudoVLOXSEG2EI32_V_MF2_M1
Definition riscv/opcodes.hpp:4396
LIEF::assembly::riscv::OPCODE::SRLW
@ SRLW
Definition riscv/opcodes.hpp:13003
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF4_MASK
@ PseudoVNMSUB_VX_MF4_MASK
Definition riscv/opcodes.hpp:7551
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_MF2_E32_MASK
@ PseudoVFMACC_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:1958
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M2
@ PseudoVSUXEI32_V_M2_M2
Definition riscv/opcodes.hpp:10555
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M1_MASK
@ PseudoVLUXSEG4EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6001
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E64
@ PseudoVFRSQRT7_V_M1_E64
Definition riscv/opcodes.hpp:3065
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E16_MASK
@ PseudoVFMAX_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:2112
LIEF::assembly::riscv::OPCODE::VREDAND_VS
@ VREDAND_VS
Definition riscv/opcodes.hpp:13594
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF2
@ PseudoVSSEG8E8_V_MF2
Definition riscv/opcodes.hpp:10157
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M2_MASK
@ PseudoVSOXSEG4EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9404
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M1_MASK
@ PseudoVSADDU_VV_M1_MASK
Definition riscv/opcodes.hpp:8619
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF2
@ PseudoVLOXSEG4EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:4596
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M1
@ PseudoVMINU_VV_M1
Definition riscv/opcodes.hpp:6826
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M2
@ PseudoVSLL_VI_M2
Definition riscv/opcodes.hpp:8880
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M1_E32
@ PseudoVFWMUL_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3813
LIEF::assembly::riscv::OPCODE::SH_RL
@ SH_RL
Definition riscv/opcodes.hpp:12980
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_M1_MASK
@ PseudoVSOXEI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9088
LIEF::assembly::riscv::OPCODE::VSOXSEG6EI16_V
@ VSOXSEG6EI16_V
Definition riscv/opcodes.hpp:13680
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF8_E8
@ PseudoVREM_VV_MF8_E8
Definition riscv/opcodes.hpp:8214
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_MF4_MASK
@ PseudoVLUXSEG3EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:5881
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FADD
@ G_ATOMICRMW_FADD
Definition riscv/opcodes.hpp:134
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M4
@ PseudoTHVdotVMAQAU_VV_M4
Definition riscv/opcodes.hpp:484
LIEF::assembly::riscv::OPCODE::PseudoReadVL
@ PseudoReadVL
Definition riscv/opcodes.hpp:439
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_MF2_MASK
@ PseudoVSOXEI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9082
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M8
@ PseudoVSLIDEDOWN_VX_M8
Definition riscv/opcodes.hpp:8842
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M4_E32
@ PseudoVFWMUL_VV_M4_E32
Definition riscv/opcodes.hpp:3831
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF4
@ PseudoVSSSEG2E16_V_MF4
Definition riscv/opcodes.hpp:10255
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF2_MASK
@ PseudoVMSLEU_VX_MF2_MASK
Definition riscv/opcodes.hpp:7116
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E32_MASK
@ PseudoVDIV_VX_M4_E32_MASK
Definition riscv/opcodes.hpp:1574
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF2
@ PseudoVLE8_V_MF2
Definition riscv/opcodes.hpp:4165
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M4
@ PseudoVSUXEI8_V_MF2_M4
Definition riscv/opcodes.hpp:10639
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M8_MASK
@ PseudoVMACC_VX_M8_MASK
Definition riscv/opcodes.hpp:6423
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M1_MASK
@ PseudoVSOXEI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9096
LIEF::assembly::riscv::OPCODE::HLV_W
@ HLV_W
Definition riscv/opcodes.hpp:12805
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2
@ PseudoVWSUBU_WV_M2
Definition riscv/opcodes.hpp:11747
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_M1
@ PseudoVSSEG8E8_V_M1
Definition riscv/opcodes.hpp:10155
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_MF2_E16_MASK
@ PseudoVFNMSUB_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2804
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E32_V_MF2_MASK
@ PseudoVSSEG8E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10152
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E16_MASK
@ PseudoVFMAX_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:2088
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M1_E32_MASK
@ PseudoVFNMSUB_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2808
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF2
@ PseudoVWMUL_VX_MF2
Definition riscv/opcodes.hpp:11605
LIEF::assembly::riscv::OPCODE::DBG_PHI
@ DBG_PHI
Definition riscv/opcodes.hpp:40
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E32
@ PseudoVDIVU_VV_MF2_E32
Definition riscv/opcodes.hpp:1457
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF4
@ PseudoVSOXSEG8EI64_V_M2_MF4
Definition riscv/opcodes.hpp:9803
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M1
@ PseudoVSOXEI8_V_MF4_M1
Definition riscv/opcodes.hpp:9139
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M1_MASK
@ PseudoVSSRL_VI_M1_MASK
Definition riscv/opcodes.hpp:10206
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E32
@ PseudoVREDMAXU_VS_MF2_E32
Definition riscv/opcodes.hpp:7778
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E8_MASK
@ PseudoVDIVU_VX_M4_E8_MASK
Definition riscv/opcodes.hpp:1490
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M2_E16
@ PseudoVFWNMACC_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3841
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M2
@ PseudoVSUXEI8_V_MF2_M2
Definition riscv/opcodes.hpp:10637
LIEF::assembly::riscv::OPCODE::FMIN_D_IN32X
@ FMIN_D_IN32X
Definition riscv/opcodes.hpp:12707
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF8
@ PseudoVSOXSEG2EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:9189
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF8
@ PseudoVLUXSEG8EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:6340
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF8_MASK
@ PseudoVLUXSEG7EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:6289
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF8
@ PseudoVROR_VX_MF8
Definition riscv/opcodes.hpp:8574
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M4_MASK
@ PseudoVSUXSEG2EI32_V_M2_M4_MASK
Definition riscv/opcodes.hpp:10708
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M1_MASK
@ PseudoVSOXEI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9008
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF2_MASK
@ PseudoVLUXSEG6EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:6177
LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_MF4
@ PseudoVSPILL4_MF4
Definition riscv/opcodes.hpp:9845
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M2_E64
@ PseudoVFREDMAX_VS_M2_E64
Definition riscv/opcodes.hpp:2945
LIEF::assembly::riscv::OPCODE::VFNCVT_RTZ_XU_F_W
@ VFNCVT_RTZ_XU_F_W
Definition riscv/opcodes.hpp:13239
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_M1_M1_MASK
@ PseudoVLOXSEG8EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4991
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF2_MASK
@ PseudoVLOXSEG4EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4603
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK
@ PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK
Definition riscv/opcodes.hpp:8281
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E32_MASK
@ PseudoVFMSAC_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:2225
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M4_MASK
@ PseudoTHVdotVMAQAUS_VX_M4_MASK
Definition riscv/opcodes.hpp:475
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_MF4_MASK
@ PseudoVFWCVT_RM_XU_F_V_MF4_MASK
Definition riscv/opcodes.hpp:3646
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E8
@ PseudoVWREDSUM_VS_MF2_E8
Definition riscv/opcodes.hpp:11675
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M1
@ PseudoVLOXSEG3EI32_V_M4_M1
Definition riscv/opcodes.hpp:4512
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B4_MASK
@ PseudoVMSBF_M_B4_MASK
Definition riscv/opcodes.hpp:6947
LIEF::assembly::riscv::OPCODE::CV_CMPNE_SCI_B
@ CV_CMPNE_SCI_B
Definition riscv/opcodes.hpp:12267
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF2_MASK
@ PseudoVZEXT_VF2_MF2_MASK
Definition riscv/opcodes.hpp:11890
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E32
@ PseudoVREDMAX_VS_M8_E32
Definition riscv/opcodes.hpp:7814
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_MF4
@ PseudoVAESEM_VS_M1_MF4
Definition riscv/opcodes.hpp:729
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M4
@ PseudoVFMERGE_VFPR32M_M4
Definition riscv/opcodes.hpp:2125
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E8_MASK
@ PseudoVDIVU_VV_M8_E8_MASK
Definition riscv/opcodes.hpp:1454
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_M1_M1_MASK
@ PseudoVSOXSEG5EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9572
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M4_MASK
@ PseudoVWMACC_VX_M4_MASK
Definition riscv/opcodes.hpp:11532
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF8
@ PseudoVNCLIP_WI_MF8
Definition riscv/opcodes.hpp:7472
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF4
@ PseudoVLSEG4E8FF_V_MF4
Definition riscv/opcodes.hpp:5224
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M8_MASK
@ PseudoVFCLASS_V_M8_MASK
Definition riscv/opcodes.hpp:1666
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF4_MF2_MASK
@ PseudoVSUXSEG2EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:10784
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF2
@ PseudoVXOR_VX_MF2
Definition riscv/opcodes.hpp:11875
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_M1_MASK
@ PseudoVSUXSEG2EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10722
LIEF::assembly::riscv::OPCODE::CV_SH_rr_inc
@ CV_SH_rr_inc
Definition riscv/opcodes.hpp:12422
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M1_E16
@ PseudoVFNMADD_VV_M1_E16
Definition riscv/opcodes.hpp:2705
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_M4_MASK
@ PseudoVASUBU_VV_M4_MASK
Definition riscv/opcodes.hpp:865
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF8
@ PseudoVSUXSEG6EI64_V_M1_MF8
Definition riscv/opcodes.hpp:11141
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF2_MASK
@ PseudoVWSUB_VV_MF2_MASK
Definition riscv/opcodes.hpp:11786
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_M2_MASK
@ PseudoVSUXSEG4EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10936
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF4
@ PseudoVLE8FF_V_MF4
Definition riscv/opcodes.hpp:4153
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M2_E16_MASK
@ PseudoVFMIN_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2135
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_M1_MASK
@ PseudoVSUXSEG4EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:10926
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M1
@ PseudoVCLMULH_VX_M1
Definition riscv/opcodes.hpp:958
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E16_MASK
@ PseudoVFADD_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:1636
LIEF::assembly::riscv::OPCODE::ADJCALLSTACKDOWN
@ ADJCALLSTACKDOWN
Definition riscv/opcodes.hpp:319
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_M1
@ PseudoVLOXSEG6EI16_V_MF2_M1
Definition riscv/opcodes.hpp:4776
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E32
@ PseudoVREDMIN_VS_M4_E32
Definition riscv/opcodes.hpp:7894
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF8_MASK
@ PseudoVAADD_VX_MF8_MASK
Definition riscv/opcodes.hpp:576
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E16_MASK
@ PseudoVFMACC_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:1968
LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_S_INX
@ PseudoQuietFLE_S_INX
Definition riscv/opcodes.hpp:424
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF2
@ PseudoVRGATHER_VI_MF2
Definition riscv/opcodes.hpp:8442
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF4
@ PseudoVSOXSEG3EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:9309
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF4
@ PseudoVLSEG7E8FF_V_MF4
Definition riscv/opcodes.hpp:5346
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_SE_M8
@ PseudoVC_V_FPR64V_SE_M8
Definition riscv/opcodes.hpp:1247
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_M2
@ PseudoVC_FPR16VW_SE_M2
Definition riscv/opcodes.hpp:1085
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M2_MASK
@ PseudoVLSSEG4E8_V_M2_MASK
Definition riscv/opcodes.hpp:5483
LIEF::assembly::riscv::OPCODE::FLI_H
@ FLI_H
Definition riscv/opcodes.hpp:12673
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M2
@ PseudoVCLMUL_VV_M2
Definition riscv/opcodes.hpp:974
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_M1_MASK
@ PseudoVSUXSEG3EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10844
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M2_E16
@ PseudoVFSGNJ_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3243
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF4_MASK
@ PseudoVMAXU_VX_MF4_MASK
Definition riscv/opcodes.hpp:6539
LIEF::assembly::riscv::OPCODE::HSV_B
@ HSV_B
Definition riscv/opcodes.hpp:12807
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M8_M1_MASK
@ PseudoVSOXSEG5EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:9570
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E64
@ PseudoVREM_VX_M8_E64
Definition riscv/opcodes.hpp:8244
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M2_E32
@ PseudoVFDIV_VV_M2_E32
Definition riscv/opcodes.hpp:1901
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF4
@ PseudoVLUXSEG5EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:6118
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E8
@ PseudoVREDAND_VS_M4_E8
Definition riscv/opcodes.hpp:7722
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M8_MASK
@ PseudoVMFLE_VFPR32_M8_MASK
Definition riscv/opcodes.hpp:6719
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M2_E16
@ PseudoVFWMACC_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3733
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M1
@ PseudoVLUXEI64_V_M8_M1
Definition riscv/opcodes.hpp:5674
LIEF::assembly::riscv::OPCODE::FLTQ_H
@ FLTQ_H
Definition riscv/opcodes.hpp:12676
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_M1
@ PseudoVLOXSEG3EI64_V_M1_M1
Definition riscv/opcodes.hpp:4526
LIEF::assembly::riscv::OPCODE::RORW
@ RORW
Definition riscv/opcodes.hpp:12935
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M8_MASK
@ PseudoVRGATHEREI16_VV_M8_E64_M8_MASK
Definition riscv/opcodes.hpp:8387
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF4_MASK
@ PseudoVSUXEI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:10580
LIEF::assembly::riscv::OPCODE::G_BZERO
@ G_BZERO
Definition riscv/opcodes.hpp:296
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M2
@ PseudoVSUXSEG2EI64_V_M4_M2
Definition riscv/opcodes.hpp:10747
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_MF2
@ PseudoVLSEG5E32_V_MF2
Definition riscv/opcodes.hpp:5256
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M4_MASK
@ PseudoVLUXEI8_V_M2_M4_MASK
Definition riscv/opcodes.hpp:5693
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_M1
@ PseudoVSOXSEG3EI64_V_M1_M1
Definition riscv/opcodes.hpp:9347
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF2_MF2
@ PseudoVLUXSEG4EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:6064
LIEF::assembly::riscv::OPCODE::ARITH_FENCE
@ ARITH_FENCE
Definition riscv/opcodes.hpp:48
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF4
@ PseudoVSUXSEG5EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:11091
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M8_MASK
@ PseudoVMSLT_VV_M8_MASK
Definition riscv/opcodes.hpp:7200
LIEF::assembly::riscv::OPCODE::AMOMIN_B_AQ
@ AMOMIN_B_AQ
Definition riscv/opcodes.hpp:12052
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M8_MASK
@ PseudoVMFEQ_VFPR64_M8_MASK
Definition riscv/opcodes.hpp:6627
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64_V_M1
@ PseudoVLSEG6E64_V_M1
Definition riscv/opcodes.hpp:5300
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M4_MASK
@ PseudoVNSRA_WI_M4_MASK
Definition riscv/opcodes.hpp:7559
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E16_MASK
@ PseudoVFSGNJX_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3224
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M4
@ PseudoVLSSEG2E32_V_M4
Definition riscv/opcodes.hpp:5412
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M1
@ PseudoVLSSEG3E16_V_M1
Definition riscv/opcodes.hpp:5434
LIEF::assembly::riscv::OPCODE::FMV_X_D
@ FMV_X_D
Definition riscv/opcodes.hpp:12732
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M4_MASK
@ PseudoVSADDU_VV_M4_MASK
Definition riscv/opcodes.hpp:8623
LIEF::assembly::riscv::OPCODE::VCLMULH_VX
@ VCLMULH_VX
Definition riscv/opcodes.hpp:13164
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M1_E64
@ PseudoVFRSUB_VFPR64_M1_E64
Definition riscv/opcodes.hpp:3113
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M2_MASK
@ PseudoVLSEG3E16_V_M2_MASK
Definition riscv/opcodes.hpp:5137
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF4
@ PseudoVMULHU_VV_MF4
Definition riscv/opcodes.hpp:7315
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E8_MASK
@ PseudoVREDXOR_VS_M1_E8_MASK
Definition riscv/opcodes.hpp:8015
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_MF8
@ PseudoVRELOAD8_MF8
Definition riscv/opcodes.hpp:8083
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E64_MASK
@ PseudoVREDMAX_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:7809
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF8_MASK
@ PseudoVSOXSEG7EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:9750
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M2_MASK
@ PseudoTHVdotVMAQASU_VV_M2_MASK
Definition riscv/opcodes.hpp:453
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF4
@ PseudoVSOXEI16_V_MF4_MF4
Definition riscv/opcodes.hpp:9037
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_M1_MASK
@ PseudoVLUXSEG8EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:6395
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M1_M1_MASK
@ PseudoVSUXSEG2EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10730
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M1
@ PseudoVLOXEI32_V_M2_M1
Definition riscv/opcodes.hpp:4228
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_M2
@ PseudoVSLIDEDOWN_VX_M2
Definition riscv/opcodes.hpp:8838
LIEF::assembly::riscv::OPCODE::PseudoCCSRA
@ PseudoCCSRA
Definition riscv/opcodes.hpp:356
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M1
@ PseudoVLE16FF_V_M1
Definition riscv/opcodes.hpp:4083
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF4_MASK
@ PseudoVMFEQ_VFPR16_MF4_MASK
Definition riscv/opcodes.hpp:6609
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M8_M1_MASK
@ PseudoVLOXSEG7EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:4909
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M8_MASK
@ PseudoVMUL_VX_M8_MASK
Definition riscv/opcodes.hpp:7382
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF4_MASK
@ PseudoVOR_VV_MF4_MASK
Definition riscv/opcodes.hpp:7651
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF4
@ PseudoVMADD_VV_MF4
Definition riscv/opcodes.hpp:6482
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E16
@ PseudoVDIV_VX_M2_E16
Definition riscv/opcodes.hpp:1563
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M4_MASK
@ PseudoVMADD_VV_M4_MASK
Definition riscv/opcodes.hpp:6477
LIEF::assembly::riscv::OPCODE::CV_BCLR
@ CV_BCLR
Definition riscv/opcodes.hpp:12199
LIEF::assembly::riscv::OPCODE::LIFETIME_END
@ LIFETIME_END
Definition riscv/opcodes.hpp:46
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E32
@ PseudoVFNMADD_VV_M2_E32
Definition riscv/opcodes.hpp:2713
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF8_MASK
@ PseudoVMSLE_VV_MF8_MASK
Definition riscv/opcodes.hpp:7148
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M4
@ PseudoVSEXT_VF8_M4
Definition riscv/opcodes.hpp:8775
LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_4x8x4_MF2
@ PseudoVQMACCUS_4x8x4_MF2
Definition riscv/opcodes.hpp:7683
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E32_MASK
@ PseudoVFSQRT_V_M8_E32_MASK
Definition riscv/opcodes.hpp:3382
LIEF::assembly::riscv::OPCODE::HLV_B
@ HLV_B
Definition riscv/opcodes.hpp:12800
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M1_MASK
@ PseudoVSSUBU_VV_M1_MASK
Definition riscv/opcodes.hpp:10420
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E32
@ PseudoVWREDSUM_VS_MF2_E32
Definition riscv/opcodes.hpp:11673
LIEF::assembly::riscv::OPCODE::VLUXSEG5EI32_V
@ VLUXSEG5EI32_V
Definition riscv/opcodes.hpp:13469
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M8_MASK
@ PseudoVLOXEI8_V_M2_M8_MASK
Definition riscv/opcodes.hpp:4303
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M2_MASK
@ PseudoVFWCVT_RTZ_X_F_V_M2_MASK
Definition riscv/opcodes.hpp:3670
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M2_E64_MASK
@ PseudoVFMSUB_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2277
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF4
@ PseudoVRGATHEREI16_VV_M1_E32_MF4
Definition riscv/opcodes.hpp:8288
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E8_MASK
@ PseudoVFWCVT_F_XU_V_M2_E8_MASK
Definition riscv/opcodes.hpp:3588
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK
@ PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK
Definition riscv/opcodes.hpp:2564
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M1_MASK
@ PseudoVSADD_VV_M1_MASK
Definition riscv/opcodes.hpp:8661
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M1_MASK
@ PseudoVSOXSEG2EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9156
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E16_MASK
@ PseudoVFWCVT_F_XU_V_M1_E16_MASK
Definition riscv/opcodes.hpp:3578
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M2
@ PseudoVSUXEI16_V_M1_M2
Definition riscv/opcodes.hpp:10505
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_M1_MASK
@ PseudoVLUXSEG8EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6385
LIEF::assembly::riscv::OPCODE::VLOXSEG4EI32_V
@ VLOXSEG4EI32_V
Definition riscv/opcodes.hpp:13345
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_M1
@ PseudoVC_V_IVW_SE_M1
Definition riscv/opcodes.hpp:1268
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_M1
@ PseudoVLSSEG7E8_V_M1
Definition riscv/opcodes.hpp:5542
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M2
@ PseudoVMAXU_VV_M2
Definition riscv/opcodes.hpp:6516
LIEF::assembly::riscv::OPCODE::PseudoVQMACC_4x8x4_MF2
@ PseudoVQMACC_4x8x4_MF2
Definition riscv/opcodes.hpp:7699
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B8
@ PseudoVCPOP_M_B8
Definition riscv/opcodes.hpp:1048
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M4
@ PseudoVLOXEI32_V_M4_M4
Definition riscv/opcodes.hpp:4240
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M1_MASK
@ PseudoVAND_VV_M1_MASK
Definition riscv/opcodes.hpp:833
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M4
@ PseudoVAADDU_VV_M4
Definition riscv/opcodes.hpp:525
LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M8
@ PseudoVSSE32_V_M8
Definition riscv/opcodes.hpp:9965
LIEF::assembly::riscv::OPCODE::VLSEG7E32_V
@ VLSEG7E32_V
Definition riscv/opcodes.hpp:13411
LIEF::assembly::riscv::OPCODE::TH_L2CACHE_CALL
@ TH_L2CACHE_CALL
Definition riscv/opcodes.hpp:13058
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_MF2_MASK
@ PseudoVSUXEI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:10606
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF8
@ PseudoVSUXSEG6EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:11173
LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M4
@ PseudoVSM4K_VI_M4
Definition riscv/opcodes.hpp:8932
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_MF2_MASK
@ PseudoVSUXSEG2EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10700
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF2_MASK
@ PseudoVFNCVT_RM_XU_F_W_MF2_MASK
Definition riscv/opcodes.hpp:2532
LIEF::assembly::riscv::OPCODE::VC_V_XVV
@ VC_V_XVV
Definition riscv/opcodes.hpp:13194
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF8_MASK
@ PseudoVSOXSEG7EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:9710
LIEF::assembly::riscv::OPCODE::VWADDU_WV
@ VWADDU_WV
Definition riscv/opcodes.hpp:13806
LIEF::assembly::riscv::OPCODE::VSSEG8E16_V
@ VSSEG8E16_V
Definition riscv/opcodes.hpp:13726
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32_TIED
@ PseudoVFWADD_WV_M4_E32_TIED
Definition riscv/opcodes.hpp:3528
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF4
@ PseudoVSUXEI32_V_MF2_MF4
Definition riscv/opcodes.hpp:10579
LIEF::assembly::riscv::OPCODE::VSSEG7E32_V
@ VSSEG7E32_V
Definition riscv/opcodes.hpp:13723
LIEF::assembly::riscv::OPCODE::SLLW
@ SLLW
Definition riscv/opcodes.hpp:12986
LIEF::assembly::riscv::OPCODE::G_FTAN
@ G_FTAN
Definition riscv/opcodes.hpp:265
LIEF::assembly::riscv::OPCODE::VCLMUL_VX
@ VCLMUL_VX
Definition riscv/opcodes.hpp:13166
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF4_MASK
@ PseudoVSSRA_VV_MF4_MASK
Definition riscv/opcodes.hpp:10188
LIEF::assembly::riscv::OPCODE::VFWCVT_RTZ_XU_F_V
@ VFWCVT_RTZ_XU_F_V
Definition riscv/opcodes.hpp:13280
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_MF4
@ PseudoVFMV_FPR16_S_MF4
Definition riscv/opcodes.hpp:2377
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E16
@ PseudoVFRSQRT7_V_M2_E16
Definition riscv/opcodes.hpp:3067
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF4
@ PseudoVMIN_VX_MF4
Definition riscv/opcodes.hpp:6878
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E32
@ PseudoVFSGNJ_VV_M4_E32
Definition riscv/opcodes.hpp:3285
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M2_MASK
@ PseudoVLSEG4E8_V_M2_MASK
Definition riscv/opcodes.hpp:5231
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M1
@ PseudoVCTZ_V_M1
Definition riscv/opcodes.hpp:1064
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E64
@ PseudoVFMSUB_VV_M2_E64
Definition riscv/opcodes.hpp:2292
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M1
@ PseudoVMSLEU_VI_M1
Definition riscv/opcodes.hpp:7079
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF4_MASK
@ PseudoVSRA_VI_MF4_MASK
Definition riscv/opcodes.hpp:9874
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E16
@ PseudoVFWREDOSUM_VS_M4_E16
Definition riscv/opcodes.hpp:3919
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_M1_MASK
@ PseudoVSOXSEG3EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9348
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M4_E16
@ PseudoVFWREDUSUM_VS_M4_E16
Definition riscv/opcodes.hpp:3941
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E8_MASK
@ PseudoVDIV_VV_M2_E8_MASK
Definition riscv/opcodes.hpp:1526
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E8_MASK
@ PseudoVREM_VV_M1_E8_MASK
Definition riscv/opcodes.hpp:8179
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF4_MASK
@ PseudoVMFEQ_VV_MF4_MASK
Definition riscv/opcodes.hpp:6639
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E32_MASK
@ PseudoVFNMADD_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:2732
LIEF::assembly::riscv::OPCODE::VLSE64_V
@ VLSE64_V
Definition riscv/opcodes.hpp:13366
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_M1_MASK
@ PseudoVLOXSEG3EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:4573
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF4
@ PseudoVLUXEI8_V_MF4_MF4
Definition riscv/opcodes.hpp:5716
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E8
@ PseudoVREDAND_VS_MF2_E8
Definition riscv/opcodes.hpp:7736
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E64
@ PseudoVFSQRT_V_M1_E64
Definition riscv/opcodes.hpp:3365
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M2
@ PseudoVNCLIP_WI_M2
Definition riscv/opcodes.hpp:7464
LIEF::assembly::riscv::OPCODE::VRSUB_VI
@ VRSUB_VI
Definition riscv/opcodes.hpp:13616
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M2
@ PseudoVRGATHER_VI_M2
Definition riscv/opcodes.hpp:8436
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M8
@ PseudoVMINU_VV_M8
Definition riscv/opcodes.hpp:6832
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M8_M1
@ PseudoVSUXSEG7EI64_V_M8_M1
Definition riscv/opcodes.hpp:11233
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF8_MASK
@ PseudoVSUXSEG4EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:10960
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M1
@ PseudoVSE8_V_M1
Definition riscv/opcodes.hpp:8732
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK
@ PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK
Definition riscv/opcodes.hpp:8395
LIEF::assembly::riscv::OPCODE::G_UDIVREM
@ G_UDIVREM
Definition riscv/opcodes.hpp:83
LIEF::assembly::riscv::OPCODE::AMOADD_D
@ AMOADD_D
Definition riscv/opcodes.hpp:11951
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M1_MASK
@ PseudoVFWCVT_XU_F_V_M1_MASK
Definition riscv/opcodes.hpp:3678
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M1_E32
@ PseudoVFNCVT_RM_F_XU_W_M1_E32
Definition riscv/opcodes.hpp:2491
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF4
@ PseudoVLUXSEG6EI32_V_M1_MF4
Definition riscv/opcodes.hpp:6186
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E16_MASK
@ PseudoVFWMACCBF16_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3716
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M1
@ PseudoVMULHSU_VV_M1
Definition riscv/opcodes.hpp:7277
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF4
@ PseudoVLSEG8E8_V_MF4
Definition riscv/opcodes.hpp:5394
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E16
@ PseudoVREDAND_VS_M2_E16
Definition riscv/opcodes.hpp:7708
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF2_E16
@ PseudoVFNCVT_RM_F_XU_W_MF2_E16
Definition riscv/opcodes.hpp:2501
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E32_MASK
@ PseudoVFMIN_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:2177
LIEF::assembly::riscv::OPCODE::MOPR21
@ MOPR21
Definition riscv/opcodes.hpp:12874
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E64
@ PseudoVFCVT_RM_F_X_V_M4_E64
Definition riscv/opcodes.hpp:1777
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF2
@ PseudoVLUXSEG8EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:6330
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF2_MASK
@ PseudoVSUXSEG3EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:10818
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E16
@ PseudoVFREDOSUM_VS_M8_E16
Definition riscv/opcodes.hpp:3013
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M2_MASK
@ PseudoVFSLIDE1DOWN_VFPR16_M2_MASK
Definition riscv/opcodes.hpp:3304
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M8_E32_MASK
@ PseudoVFSGNJX_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:3200
LIEF::assembly::riscv::OPCODE::VREV8_V
@ VREV8_V
Definition riscv/opcodes.hpp:13606
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M2_MASK
@ PseudoVWMACCU_VV_M2_MASK
Definition riscv/opcodes.hpp:11494
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E8
@ PseudoVREDSUM_VS_MF2_E8
Definition riscv/opcodes.hpp:8000
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M4
@ PseudoVLOXSEG2EI64_V_M8_M4
Definition riscv/opcodes.hpp:4432
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M2
@ PseudoVSOXSEG4EI32_V_M2_M2
Definition riscv/opcodes.hpp:9439
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M2_MASK
@ PseudoVRGATHEREI16_VV_M8_E64_M2_MASK
Definition riscv/opcodes.hpp:8383
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M8
@ PseudoVSADD_VV_M8
Definition riscv/opcodes.hpp:8666
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M2
@ PseudoVMFEQ_VFPR64_M2
Definition riscv/opcodes.hpp:6622
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E16_MASK
@ PseudoVFWCVT_F_X_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:3626
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M1_E32
@ PseudoVFNMADD_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2687
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF8_MASK
@ PseudoVMIN_VX_MF8_MASK
Definition riscv/opcodes.hpp:6881
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK
@ PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK
Definition riscv/opcodes.hpp:8433
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E64_MASK
@ PseudoVFADD_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:1640
LIEF::assembly::riscv::OPCODE::FEQ_H
@ FEQ_H
Definition riscv/opcodes.hpp:12656
LIEF::assembly::riscv::OPCODE::G_ATOMIC_CMPXCHG
@ G_ATOMIC_CMPXCHG
Definition riscv/opcodes.hpp:122
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M8_E16
@ PseudoVFMSAC_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2198
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M8
@ PseudoVSSUBU_VX_M8
Definition riscv/opcodes.hpp:10439
LIEF::assembly::riscv::OPCODE::G_INTRINSIC_LLRINT
@ G_INTRINSIC_LLRINT
Definition riscv/opcodes.hpp:109
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M8_MASK
@ PseudoVAND_VV_M8_MASK
Definition riscv/opcodes.hpp:839
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF2
@ PseudoVSOXSEG4EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:9451
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF4
@ PseudoVLUXSEG7EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:6278
LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B32
@ PseudoVSM_V_B32
Definition riscv/opcodes.hpp:8995
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF4_MASK
@ PseudoVMSGT_VX_MF4_MASK
Definition riscv/opcodes.hpp:7062
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M2_E32
@ PseudoVFNMSAC_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2749
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E16
@ PseudoVREM_VX_MF4_E16
Definition riscv/opcodes.hpp:8254
LIEF::assembly::riscv::OPCODE::CV_SUB_SC_H
@ CV_SUB_SC_H
Definition riscv/opcodes.hpp:12463
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF8
@ PseudoVMAX_VV_MF8
Definition riscv/opcodes.hpp:6554
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E16
@ PseudoVWREDSUMU_VS_M8_E16
Definition riscv/opcodes.hpp:11629
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E16_MASK
@ PseudoVREDMAX_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:7789
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M4_MASK
@ PseudoVLSE8_V_M4_MASK
Definition riscv/opcodes.hpp:5045
LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_MF2
@ PseudoVC_IVV_SE_MF2
Definition riscv/opcodes.hpp:1123
LIEF::assembly::riscv::OPCODE::CV_DOTUP_SCI_H
@ CV_DOTUP_SCI_H
Definition riscv/opcodes.hpp:12290
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M2
@ PseudoVSOXSEG4EI16_V_M1_M2
Definition riscv/opcodes.hpp:9403
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M2
@ PseudoVMSLEU_VX_M2
Definition riscv/opcodes.hpp:7109
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_M1
@ PseudoVSOXSEG8EI64_V_M1_M1
Definition riscv/opcodes.hpp:9791
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF4
@ PseudoVLSEG5E16_V_MF4
Definition riscv/opcodes.hpp:5248
LIEF::assembly::riscv::OPCODE::G_MERGE_VALUES
@ G_MERGE_VALUES
Definition riscv/opcodes.hpp:96
LIEF::assembly::riscv::OPCODE::TH_L2CACHE_CIALL
@ TH_L2CACHE_CIALL
Definition riscv/opcodes.hpp:13059
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF8_MASK
@ PseudoVSUB_VV_MF8_MASK
Definition riscv/opcodes.hpp:10488
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E16
@ PseudoVFSGNJ_VV_M4_E16
Definition riscv/opcodes.hpp:3283
LIEF::assembly::riscv::OPCODE::VWSUB_WX
@ VWSUB_WX
Definition riscv/opcodes.hpp:13837
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M2
@ PseudoVFSLIDE1DOWN_VFPR16_M2
Definition riscv/opcodes.hpp:3303
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF4_E16
@ PseudoVFREDUSUM_VS_MF4_E16
Definition riscv/opcodes.hpp:3053
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF4_MASK
@ PseudoVSOXSEG6EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9662
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF2
@ PseudoVMSLT_VX_MF2
Definition riscv/opcodes.hpp:7215
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M1_MF2
@ PseudoVAESEM_VS_M1_MF2
Definition riscv/opcodes.hpp:728
LIEF::assembly::riscv::OPCODE::MOPR23
@ MOPR23
Definition riscv/opcodes.hpp:12876
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VV_SE_MF2
@ PseudoVC_FPR32VV_SE_MF2
Definition riscv/opcodes.hpp:1100
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF4
@ PseudoVLOXSEG8EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:4966
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1
@ PseudoVWSUBU_WV_M1
Definition riscv/opcodes.hpp:11743
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF2_MASK
@ PseudoVMSLEU_VI_MF2_MASK
Definition riscv/opcodes.hpp:7088
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M1
@ PseudoVMULHU_VV_M1
Definition riscv/opcodes.hpp:7305
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M8_M1_MASK
@ PseudoVLOXSEG5EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:4749
LIEF::assembly::riscv::OPCODE::FCVT_W_H
@ FCVT_W_H
Definition riscv/opcodes.hpp:12639
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF4_MASK
@ PseudoVLUXEI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:5647
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M8
@ PseudoVAESEF_VV_M8
Definition riscv/opcodes.hpp:725
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M8
@ PseudoVMULHSU_VX_M8
Definition riscv/opcodes.hpp:7297
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M8
@ PseudoVMFNE_VV_M8
Definition riscv/opcodes.hpp:6820
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF8
@ PseudoVWADD_VV_MF8
Definition riscv/opcodes.hpp:11405
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E16
@ PseudoVRGATHER_VV_M4_E16
Definition riscv/opcodes.hpp:8464
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M2_E16
@ PseudoVFADD_VV_M2_E16
Definition riscv/opcodes.hpp:1635
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M1_MASK
@ PseudoVSUB_VX_M1_MASK
Definition riscv/opcodes.hpp:10490
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M4_MASK
@ PseudoVSUB_VX_M4_MASK
Definition riscv/opcodes.hpp:10494
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_MF2
@ PseudoVLSSEG4E32_V_MF2
Definition riscv/opcodes.hpp:5474
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_M8
@ PseudoVC_V_IV_M8
Definition riscv/opcodes.hpp:1277
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF4
@ PseudoVLSEG3E16FF_V_MF4
Definition riscv/opcodes.hpp:5132
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_MF4
@ PseudoVLSEG8E8FF_V_MF4
Definition riscv/opcodes.hpp:5386
LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M8_MASK
@ PseudoVLSE32_V_M8_MASK
Definition riscv/opcodes.hpp:5029
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_M1_M1
@ PseudoVLUXSEG8EI8_V_M1_M1
Definition riscv/opcodes.hpp:6382
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M8
@ PseudoVSLL_VV_M8
Definition riscv/opcodes.hpp:8898
LIEF::assembly::riscv::OPCODE::FMIN_H_INX
@ FMIN_H_INX
Definition riscv/opcodes.hpp:12710
LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_M1
@ PseudoVC_IVW_SE_M1
Definition riscv/opcodes.hpp:1126
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF2
@ PseudoVSOXEI16_V_MF2_MF2
Definition riscv/opcodes.hpp:9029
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_M1_MASK
@ PseudoVMADD_VV_M1_MASK
Definition riscv/opcodes.hpp:6473
LIEF::assembly::riscv::OPCODE::FCVT_WU_D_INX
@ FCVT_WU_D_INX
Definition riscv/opcodes.hpp:12631
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E16_MASK
@ PseudoVFCVT_F_X_V_M8_E16_MASK
Definition riscv/opcodes.hpp:1720
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M8_E16_MASK
@ PseudoVFSGNJ_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:3248
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M2_MASK
@ PseudoVSSSEG4E64_V_M2_MASK
Definition riscv/opcodes.hpp:10328
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_M2
@ PseudoVC_V_XV_SE_M2
Definition riscv/opcodes.hpp:1376
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF2
@ PseudoVFSLIDE1DOWN_VFPR16_MF2
Definition riscv/opcodes.hpp:3309
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M4_MASK
@ PseudoVLSSEG2E8_V_M4_MASK
Definition riscv/opcodes.hpp:5427
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M4
@ PseudoVCLMUL_VV_M4
Definition riscv/opcodes.hpp:976
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_M8
@ PseudoVFMV_S_FPR16_M8
Definition riscv/opcodes.hpp:2390
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E64_MASK
@ PseudoVREM_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:8185
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_MF2_MASK
@ PseudoVZEXT_VF4_MF2_MASK
Definition riscv/opcodes.hpp:11902
LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_MF8
@ PseudoVC_IVV_SE_MF8
Definition riscv/opcodes.hpp:1125
LIEF::assembly::riscv::OPCODE::MOPR19
@ MOPR19
Definition riscv/opcodes.hpp:12871
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E16_MASK
@ PseudoVFMUL_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:2367
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_MF2_E32
@ PseudoVFSGNJ_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3261
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF8_MASK
@ PseudoVSOXSEG2EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:9224
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M1_E64_MASK
@ PseudoVFSQRT_V_M1_E64_MASK
Definition riscv/opcodes.hpp:3366
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_M1_M1_MASK
@ PseudoVSOXSEG6EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9652
LIEF::assembly::riscv::OPCODE::InsnCL
@ InsnCL
Definition riscv/opcodes.hpp:12819
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M8_MASK
@ PseudoVMSGTU_VX_M8_MASK
Definition riscv/opcodes.hpp:7030
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF4_MASK
@ PseudoVLUXSEG7EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:6287
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_M1
@ PseudoVC_FPR16V_SE_M1
Definition riscv/opcodes.hpp:1090
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M2_E16_MASK
@ PseudoVFMSUB_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2255
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M2_MASK
@ PseudoVFNCVT_RTZ_XU_F_W_M2_MASK
Definition riscv/opcodes.hpp:2570
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_M1
@ PseudoVC_V_FPR64V_M1
Definition riscv/opcodes.hpp:1240
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF2_MASK
@ PseudoVSOXSEG6EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9660
LIEF::assembly::riscv::OPCODE::ADD
@ ADD
Definition riscv/opcodes.hpp:11931
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_M1_MASK
@ PseudoVLOXSEG2EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4405
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M2
@ PseudoVSUXEI16_V_MF2_M2
Definition riscv/opcodes.hpp:10531
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF2_E32_MASK
@ PseudoVFWREDUSUM_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:3952
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_MF8_MASK
@ PseudoVROR_VX_MF8_MASK
Definition riscv/opcodes.hpp:8575
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF8
@ PseudoVNSRL_WI_MF8
Definition riscv/opcodes.hpp:7600
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_MF2
@ PseudoVLOXSEG6EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:4834
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_MF4
@ PseudoVRELOAD7_MF4
Definition riscv/opcodes.hpp:8078
LIEF::assembly::riscv::OPCODE::CV_XOR_SC_H
@ CV_XOR_SC_H
Definition riscv/opcodes.hpp:12472
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M8_M8
@ PseudoVSOXEI16_V_M8_M8
Definition riscv/opcodes.hpp:9023
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_M1_MASK
@ PseudoVSOXSEG5EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9544
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M8
@ PseudoVMSGTU_VI_M8
Definition riscv/opcodes.hpp:7015
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF4
@ PseudoVLUXSEG5EI64_V_M2_MF4
Definition riscv/opcodes.hpp:6134
LIEF::assembly::riscv::OPCODE::FCVT_H_L
@ FCVT_H_L
Definition riscv/opcodes.hpp:12593
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E64
@ PseudoVREM_VV_M1_E64
Definition riscv/opcodes.hpp:8176
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M4_E32_MASK
@ PseudoVFWMSAC_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3782
LIEF::assembly::riscv::OPCODE::FCVT_H_D_IN32X
@ FCVT_H_D_IN32X
Definition riscv/opcodes.hpp:12591
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M1_MASK
@ PseudoVSUXSEG3EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10860
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M8
@ PseudoVMSBC_VV_M8
Definition riscv/opcodes.hpp:6920
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M2_MASK
@ PseudoVNCLIPU_WX_M2_MASK
Definition riscv/opcodes.hpp:7453
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32_MASK
@ PseudoVFWADD_WV_M1_E32_MASK
Definition riscv/opcodes.hpp:3510
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF4_MASK
@ PseudoVLOXEI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:4331
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M1
@ PseudoVSOXSEG2EI64_V_M8_M1
Definition riscv/opcodes.hpp:9249
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_M1_MASK
@ PseudoVSUXSEG8EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:11322
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_MF2
@ PseudoVLOXSEG3EI32_V_M2_MF2
Definition riscv/opcodes.hpp:4510
LIEF::assembly::riscv::OPCODE::AMOMIN_D_AQ
@ AMOMIN_D_AQ
Definition riscv/opcodes.hpp:12056
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF2
@ PseudoVLE8FF_V_MF2
Definition riscv/opcodes.hpp:4151
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF8
@ PseudoVSOXSEG6EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:9629
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M1
@ PseudoVWMUL_VX_M1
Definition riscv/opcodes.hpp:11599
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF2_MASK
@ PseudoVLSEG7E8FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5345
LIEF::assembly::riscv::OPCODE::C_ADDI16SP
@ C_ADDI16SP
Definition riscv/opcodes.hpp:12477
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M2_MASK
@ PseudoVNCLIP_WX_M2_MASK
Definition riscv/opcodes.hpp:7489
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_MF2_MASK
@ PseudoVSOXSEG5EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9540
LIEF::assembly::riscv::OPCODE::VLUXSEG3EI32_V
@ VLUXSEG3EI32_V
Definition riscv/opcodes.hpp:13461
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF4_MASK
@ PseudoVMFNE_VV_MF4_MASK
Definition riscv/opcodes.hpp:6825
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_MF4_E16_MASK
@ PseudoVFSUB_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3402
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M8_E32_MASK
@ PseudoVFNMSUB_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2814
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M2_M1
@ PseudoVSOXSEG4EI16_V_M2_M1
Definition riscv/opcodes.hpp:9407
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M1_E32_MASK
@ PseudoVFWADD_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3462
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF8_E8
@ PseudoVREM_VX_MF8_E8
Definition riscv/opcodes.hpp:8258
LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_MF2
@ PseudoVMAND_MM_MF2
Definition riscv/opcodes.hpp:6511
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_MF2
@ PseudoVLOXSEG5EI16_V_M1_MF2
Definition riscv/opcodes.hpp:4692
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M8_MASK
@ PseudoVADD_VX_M8_MASK
Definition riscv/opcodes.hpp:633
LIEF::assembly::riscv::OPCODE::VMSGTU_VX
@ VMSGTU_VX
Definition riscv/opcodes.hpp:13530
LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M1
@ PseudoVSHA2CL_VV_M1
Definition riscv/opcodes.hpp:8784
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M2_M1_MASK
@ PseudoVSOXSEG6EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9596
LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_MF8
@ PseudoVC_VVW_SE_MF8
Definition riscv/opcodes.hpp:1158
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M8_E64_MASK
@ PseudoVFMSUB_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2281
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF8
@ PseudoVSUXSEG6EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:11133
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E64_MASK
@ PseudoVDIV_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:1532
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M4_MASK
@ PseudoVWMULU_VX_M4_MASK
Definition riscv/opcodes.hpp:11580
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF8_MASK
@ PseudoVMSNE_VX_MF8_MASK
Definition riscv/opcodes.hpp:7262
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M1_MASK
@ PseudoVWADD_VX_M1_MASK
Definition riscv/opcodes.hpp:11408
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M2_MASK
@ PseudoVLOXEI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:4321
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M4_E8
@ PseudoVWREDSUMU_VS_M4_E8
Definition riscv/opcodes.hpp:11627
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_MF2_MASK
@ PseudoVSUXEI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10550
LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M2
@ PseudoVSSE32_V_M2
Definition riscv/opcodes.hpp:9961
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_M4
@ PseudoVC_V_FPR16V_M4
Definition riscv/opcodes.hpp:1192
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E32_MASK
@ PseudoVWREDSUM_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:11674
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M2
@ PseudoVSLL_VX_M2
Definition riscv/opcodes.hpp:8908
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E32
@ PseudoVFMIN_VV_M4_E32
Definition riscv/opcodes.hpp:2176
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_MF4_MASK
@ PseudoVSOXSEG2EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:9240
LIEF::assembly::riscv::OPCODE::CV_SUB_DIV4
@ CV_SUB_DIV4
Definition riscv/opcodes.hpp:12457
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF8
@ PseudoVLE8_V_MF8
Definition riscv/opcodes.hpp:4169
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_M2_M1_MASK
@ PseudoVSUXSEG8EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11260
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M4_E32
@ PseudoVFMSAC_VFPR32_M4_E32
Definition riscv/opcodes.hpp:2208
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_M2_MASK
@ PseudoVRSUB_VX_M2_MASK
Definition riscv/opcodes.hpp:8593
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_M1
@ PseudoVLSSEG5E8_V_M1
Definition riscv/opcodes.hpp:5502
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E64
@ PseudoVREDMAXU_VS_M4_E64
Definition riscv/opcodes.hpp:7764
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_M1_MASK
@ PseudoVSSEG7E16_V_M1_MASK
Definition riscv/opcodes.hpp:10124
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E32_MASK
@ PseudoVREM_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:8207
LIEF::assembly::riscv::OPCODE::IMPLICIT_DEF
@ IMPLICIT_DEF
Definition riscv/opcodes.hpp:34
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M2_MASK
@ PseudoVOR_VV_M2_MASK
Definition riscv/opcodes.hpp:7643
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF4
@ PseudoVSUXSEG8EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:11331
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M1_MASK
@ PseudoVLOXEI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4267
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E16_MASK
@ PseudoVFWREDUSUM_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:3934
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF8
@ PseudoVADD_VV_MF8
Definition riscv/opcodes.hpp:624
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M2_MASK
@ PseudoVLSEG4E32FF_V_M2_MASK
Definition riscv/opcodes.hpp:5201
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF2_MASK
@ PseudoVLOXSEG5EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:4765
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_M1
@ PseudoVSUXSEG6EI8_V_MF8_M1
Definition riscv/opcodes.hpp:11167
LIEF::assembly::riscv::OPCODE::VFNMACC_VF
@ VFNMACC_VF
Definition riscv/opcodes.hpp:13243
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M4
@ PseudoVMSLTU_VV_M4
Definition riscv/opcodes.hpp:7168
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E16_MASK
@ PseudoVREDMAXU_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:7761
LIEF::assembly::riscv::OPCODE::SB
@ SB
Definition riscv/opcodes.hpp:12936
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M8
@ PseudoVMULHSU_VV_M8
Definition riscv/opcodes.hpp:7283
LIEF::assembly::riscv::OPCODE::CV_CMPGE_SCI_H
@ CV_CMPGE_SCI_H
Definition riscv/opcodes.hpp:12226
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M8_MASK
@ PseudoVLUXEI8_V_M4_M8_MASK
Definition riscv/opcodes.hpp:5699
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_M2
@ PseudoVSSSEG3E8_V_M2
Definition riscv/opcodes.hpp:10303
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_M1_MASK
@ PseudoVLUXSEG6EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:6235
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E64
@ PseudoVFMSAC_VV_M2_E64
Definition riscv/opcodes.hpp:2232
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E16_MASK
@ PseudoVFMAX_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:2094
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF2_MASK
@ PseudoVCLZ_V_MF2_MASK
Definition riscv/opcodes.hpp:1009
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF4_E16
@ PseudoVCOMPRESS_VM_MF4_E16
Definition riscv/opcodes.hpp:1033
LIEF::assembly::riscv::OPCODE::VC_XVV
@ VC_XVV
Definition riscv/opcodes.hpp:13198
LIEF::assembly::riscv::OPCODE::CV_CMPGT_SCI_B
@ CV_CMPGT_SCI_B
Definition riscv/opcodes.hpp:12237
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF4_MASK
@ PseudoVMACC_VV_MF4_MASK
Definition riscv/opcodes.hpp:6413
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M4_MASK
@ PseudoVLSSEG2E64_V_M4_MASK
Definition riscv/opcodes.hpp:5421
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_M1_MASK
@ PseudoVLUXSEG3EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:5965
LIEF::assembly::riscv::OPCODE::VMINU_VX
@ VMINU_VX
Definition riscv/opcodes.hpp:13514
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M4_MASK
@ PseudoVSUXEI8_V_M1_M4_MASK
Definition riscv/opcodes.hpp:10620
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF2_MASK
@ PseudoVNSRL_WI_MF2_MASK
Definition riscv/opcodes.hpp:7597
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF4
@ PseudoVLSSEG4E8_V_MF4
Definition riscv/opcodes.hpp:5486
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E64
@ PseudoVREDMAX_VS_M1_E64
Definition riscv/opcodes.hpp:7792
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_MF2
@ PseudoVWADDU_VV_MF2
Definition riscv/opcodes.hpp:11341
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M8_E16_MASK
@ PseudoVFNMADD_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2682
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M2_MASK
@ PseudoVSUXSEG2EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10674
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF4_MASK
@ PseudoVWSUBU_VX_MF4_MASK
Definition riscv/opcodes.hpp:11740
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M4
@ PseudoVAND_VX_M4
Definition riscv/opcodes.hpp:850
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E64_V_M1_MASK
@ PseudoVSSSEG8E64_V_M1_MASK
Definition riscv/opcodes.hpp:10410
LIEF::assembly::riscv::OPCODE::AMOOR_H
@ AMOOR_H
Definition riscv/opcodes.hpp:12075
LIEF::assembly::riscv::OPCODE::VREDOR_VS
@ VREDOR_VS
Definition riscv/opcodes.hpp:13599
LIEF::assembly::riscv::OPCODE::AMOXOR_B_AQ
@ AMOXOR_B_AQ
Definition riscv/opcodes.hpp:12100
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF2_M1
@ PseudoVLUXSEG8EI8_V_MF2_M1
Definition riscv/opcodes.hpp:6384
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64V_SE_M4
@ PseudoVC_FPR64V_SE_M4
Definition riscv/opcodes.hpp:1117
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_MF2_MASK
@ PseudoVLOXSEG8EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:4987
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF2_MASK
@ PseudoVOR_VX_MF2_MASK
Definition riscv/opcodes.hpp:7663
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M1_MASK
@ PseudoVCLMUL_VV_M1_MASK
Definition riscv/opcodes.hpp:973
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF2_MASK
@ PseudoVLOXSEG5EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4713
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M2
@ PseudoVFNCVT_XU_F_W_M2
Definition riscv/opcodes.hpp:2593
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF2
@ PseudoVMAXU_VX_MF2
Definition riscv/opcodes.hpp:6536
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF2_E16_MASK
@ PseudoVFWSUB_WFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3998
LIEF::assembly::riscv::OPCODE::COPY_TO_REGCLASS
@ COPY_TO_REGCLASS
Definition riscv/opcodes.hpp:36
LIEF::assembly::riscv::OPCODE::G_PTRTOINT
@ G_PTRTOINT
Definition riscv/opcodes.hpp:100
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B2
@ PseudoVMSBF_M_B2
Definition riscv/opcodes.hpp:6942
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E64
@ PseudoVFNMACC_VV_M8_E64
Definition riscv/opcodes.hpp:2667
LIEF::assembly::riscv::OPCODE::VLSEG5E16FF_V
@ VLSEG5E16FF_V
Definition riscv/opcodes.hpp:13392
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF4_MASK
@ PseudoVFCVT_RTZ_XU_F_V_MF4_MASK
Definition riscv/opcodes.hpp:1826
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M4_E32
@ PseudoVFDIV_VFPR32_M4_E32
Definition riscv/opcodes.hpp:1879
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF2
@ PseudoVMFLT_VV_MF2
Definition riscv/opcodes.hpp:6780
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E32
@ PseudoVFNMSAC_VV_M1_E32
Definition riscv/opcodes.hpp:2767
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_MF2
@ PseudoVLOXSEG2EI32_V_M2_MF2
Definition riscv/opcodes.hpp:4384
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF4_MASK
@ PseudoVSOXEI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9032
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_MF2
@ PseudoVLSEG3E32FF_V_MF2
Definition riscv/opcodes.hpp:5146
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E64_MASK
@ PseudoVFMUL_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:2365
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_MF8
@ PseudoVMADC_VX_MF8
Definition riscv/opcodes.hpp:6471
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M1_MASK
@ PseudoTHVdotVMAQAUS_VX_M1_MASK
Definition riscv/opcodes.hpp:471
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M2
@ PseudoVLSEG4E16_V_M2
Definition riscv/opcodes.hpp:5192
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF8
@ PseudoVMSEQ_VX_MF8
Definition riscv/opcodes.hpp:6992
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M2
@ PseudoVRGATHEREI16_VV_M4_E8_M2
Definition riscv/opcodes.hpp:8364
LIEF::assembly::riscv::OPCODE::VSOXSEG3EI8_V
@ VSOXSEG3EI8_V
Definition riscv/opcodes.hpp:13671
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E16_MASK
@ PseudoVFWREDOSUM_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:3912
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M8_MASK
@ PseudoVAADD_VX_M8_MASK
Definition riscv/opcodes.hpp:570
LIEF::assembly::riscv::OPCODE::VL1RE64_V
@ VL1RE64_V
Definition riscv/opcodes.hpp:13309
LIEF::assembly::riscv::OPCODE::VLSEG8E64_V
@ VLSEG8E64_V
Definition riscv/opcodes.hpp:13421
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E64_MASK
@ PseudoVREDMAX_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:7817
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E16_MASK
@ PseudoVDIVU_VX_M2_E16_MASK
Definition riscv/opcodes.hpp:1476
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF2_E32
@ PseudoVFCVT_RM_F_X_V_MF2_E32
Definition riscv/opcodes.hpp:1787
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF2_MASK
@ PseudoVSSSEG5E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10354
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_SE_M4
@ PseudoVC_V_FPR64VV_SE_M4
Definition riscv/opcodes.hpp:1238
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_MF2
@ PseudoVLOXSEG4EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:4602
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E8
@ PseudoVFWCVT_F_X_V_M2_E8
Definition riscv/opcodes.hpp:3617
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M1
@ PseudoVLUXSEG3EI16_V_M1_M1
Definition riscv/opcodes.hpp:5862
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M4_MASK
@ PseudoVLSEG2E16_V_M4_MASK
Definition riscv/opcodes.hpp:5069
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M2
@ PseudoVSLIDE1UP_VX_M2
Definition riscv/opcodes.hpp:8810
LIEF::assembly::riscv::OPCODE::VLE8_V
@ VLE8_V
Definition riscv/opcodes.hpp:13330
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M2_MASK
@ PseudoVSSRA_VI_M2_MASK
Definition riscv/opcodes.hpp:10166
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M2
@ PseudoVSSRA_VX_M2
Definition riscv/opcodes.hpp:10193
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF4_MASK
@ PseudoVLSSEG7E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5535
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B16_MASK
@ PseudoVMSOF_M_B16_MASK
Definition riscv/opcodes.hpp:7265
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M4_MASK
@ PseudoVSUXEI32_V_M2_M4_MASK
Definition riscv/opcodes.hpp:10558
LIEF::assembly::riscv::OPCODE::LB_AQ
@ LB_AQ
Definition riscv/opcodes.hpp:12834
LIEF::assembly::riscv::OPCODE::FCLASS_D_INX
@ FCLASS_D_INX
Definition riscv/opcodes.hpp:12567
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_MF4_MASK
@ PseudoVSUXSEG2EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:10792
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF2
@ PseudoVWADD_VV_MF2
Definition riscv/opcodes.hpp:11401
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M2_MASK
@ PseudoVSUXEI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:10532
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_M1
@ PseudoVLOXSEG6EI16_V_MF4_M1
Definition riscv/opcodes.hpp:4782
LIEF::assembly::riscv::OPCODE::CV_CMPLT_SC_B
@ CV_CMPLT_SC_B
Definition riscv/opcodes.hpp:12263
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_MF2_MASK
@ PseudoVSOXSEG4EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9494
LIEF::assembly::riscv::OPCODE::VLOXSEG7EI16_V
@ VLOXSEG7EI16_V
Definition riscv/opcodes.hpp:13356
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF4
@ PseudoVSSRA_VX_MF4
Definition riscv/opcodes.hpp:10201
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M2
@ PseudoVSUXSEG3EI16_V_MF2_M2
Definition riscv/opcodes.hpp:10809
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M1
@ PseudoVMSLTU_VV_M1
Definition riscv/opcodes.hpp:7164
LIEF::assembly::riscv::OPCODE::VSSEG2E32_V
@ VSSEG2E32_V
Definition riscv/opcodes.hpp:13703
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF2_MASK
@ PseudoVLOXSEG6EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4793
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF4_MASK
@ PseudoVMULHSU_VV_MF4_MASK
Definition riscv/opcodes.hpp:7288
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E32_MASK
@ PseudoVFSGNJ_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3274
LIEF::assembly::riscv::OPCODE::BSET
@ BSET
Definition riscv/opcodes.hpp:12132
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_MF2
@ PseudoVC_V_FPR16VW_SE_MF2
Definition riscv/opcodes.hpp:1188
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF2
@ PseudoVNSRL_WX_MF2
Definition riscv/opcodes.hpp:7620
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M8_E32
@ PseudoVFNMSAC_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2753
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK
@ PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3704
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M4_E64
@ PseudoVFMACC_VFPR64_M4_E64
Definition riscv/opcodes.hpp:1963
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M1_MASK
@ PseudoVLUXSEG4EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5973
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_M4_MASK
@ PseudoVFNCVT_RTZ_X_F_W_M4_MASK
Definition riscv/opcodes.hpp:2584
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8_MASK_TIED
@ PseudoVWADDU_WV_MF8_MASK_TIED
Definition riscv/opcodes.hpp:11381
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E64
@ PseudoVREMU_VV_M2_E64
Definition riscv/opcodes.hpp:8096
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_M1
@ PseudoVLOXSEG7EI64_V_M2_M1
Definition riscv/opcodes.hpp:4898
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF4_E16_MASK
@ PseudoVFWMACC_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3766
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M4_M2_MASK
@ PseudoVSUXSEG3EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10806
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M1_MASK
@ PseudoVAADD_VX_M1_MASK
Definition riscv/opcodes.hpp:564
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E32_MASK
@ PseudoVFWADD_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3484
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_M2
@ PseudoVC_V_FPR16VW_SE_M2
Definition riscv/opcodes.hpp:1185
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF8_MASK
@ PseudoVSUXSEG3EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:10850
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M1
@ PseudoVSUXSEG4EI64_V_M4_M1
Definition riscv/opcodes.hpp:10977
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF8_MASK
@ PseudoVSLIDEDOWN_VX_MF8_MASK
Definition riscv/opcodes.hpp:8849
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF4_MASK
@ PseudoVBREV_V_MF4_MASK
Definition riscv/opcodes.hpp:941
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2_TIED
@ PseudoVWADDU_WV_MF2_TIED
Definition riscv/opcodes.hpp:11374
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M1_E64
@ PseudoVFNMACC_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2637
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF8
@ PseudoVLOXSEG6EI64_V_M1_MF8
Definition riscv/opcodes.hpp:4816
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M4
@ PseudoVLUXSEG2EI32_V_M2_M4
Definition riscv/opcodes.hpp:5774
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_MF2_MF4
@ PseudoVAESDM_VS_MF2_MF4
Definition riscv/opcodes.hpp:691
LIEF::assembly::riscv::OPCODE::AMOMINU_D_AQ
@ AMOMINU_D_AQ
Definition riscv/opcodes.hpp:12040
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_M4
@ PseudoVFNCVT_X_F_W_M4
Definition riscv/opcodes.hpp:2607
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_MF2_MASK
@ PseudoVLOXSEG4EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4649
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M2_MASK
@ PseudoVMACC_VV_M2_MASK
Definition riscv/opcodes.hpp:6405
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E8_MASK
@ PseudoVDIVU_VX_M1_E8_MASK
Definition riscv/opcodes.hpp:1474
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M4
@ PseudoVOR_VI_M4
Definition riscv/opcodes.hpp:7630
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_M1
@ PseudoVC_V_FPR16VW_SE_M1
Definition riscv/opcodes.hpp:1184
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M8_M1_MASK
@ PseudoVSUXSEG8EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:11314
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_M2
@ PseudoVSM4R_VS_M8_M2
Definition riscv/opcodes.hpp:8951
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E32_MASK
@ PseudoVFCVT_RM_F_X_V_M1_E32_MASK
Definition riscv/opcodes.hpp:1764
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M2_MASK
@ PseudoVSOXSEG2EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9210
LIEF::assembly::riscv::OPCODE::VMULH_VV
@ VMULH_VV
Definition riscv/opcodes.hpp:13552
LIEF::assembly::riscv::OPCODE::FCVT_D_W_INX
@ FCVT_D_W_INX
Definition riscv/opcodes.hpp:12589
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1_MASK_TIED
@ PseudoVWSUBU_WV_M1_MASK_TIED
Definition riscv/opcodes.hpp:11745
LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_MF8
@ PseudoVMANDN_MM_MF8
Definition riscv/opcodes.hpp:6506
LIEF::assembly::riscv::OPCODE::VLE16FF_V
@ VLE16FF_V
Definition riscv/opcodes.hpp:13323
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E16_MASK
@ PseudoVFWMACCBF16_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3708
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M2
@ PseudoVFCVT_RTZ_XU_F_V_M2
Definition riscv/opcodes.hpp:1817
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF2_MASK
@ PseudoVSOXSEG7EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:9746
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF4_E16
@ PseudoVFMIN_VV_MF4_E16
Definition riscv/opcodes.hpp:2190
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_MF4
@ PseudoVSOXSEG3EI32_V_M1_MF4
Definition riscv/opcodes.hpp:9325
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E16_MASK
@ PseudoVWREDSUM_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:11666
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M2
@ PseudoVLUXSEG3EI16_V_M2_M2
Definition riscv/opcodes.hpp:5870
LIEF::assembly::riscv::OPCODE::CV_MACURN
@ CV_MACURN
Definition riscv/opcodes.hpp:12341
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M2
@ PseudoVWMACCU_VX_M2
Definition riscv/opcodes.hpp:11505
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E32_MASK
@ PseudoVDIV_VX_M8_E32_MASK
Definition riscv/opcodes.hpp:1582
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M4_MASK
@ PseudoVWMACCSU_VV_M4_MASK
Definition riscv/opcodes.hpp:11460
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF2
@ PseudoVLUXEI64_V_M1_MF2
Definition riscv/opcodes.hpp:5652
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M2
@ PseudoVLOXSEG2EI8_V_M1_M2
Definition riscv/opcodes.hpp:4436
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M2
@ PseudoVLSSEG2E8_V_M2
Definition riscv/opcodes.hpp:5424
LIEF::assembly::riscv::OPCODE::VLUXSEG2EI8_V
@ VLUXSEG2EI8_V
Definition riscv/opcodes.hpp:13459
LIEF::assembly::riscv::OPCODE::VFWSUB_VV
@ VFWSUB_VV
Definition riscv/opcodes.hpp:13300
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E32_MASK
@ PseudoVFSUB_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3430
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR64_S_M2
@ PseudoVFMV_FPR64_S_M2
Definition riscv/opcodes.hpp:2384
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF2_MASK
@ PseudoVLOXSEG5EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4725
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E32_MASK
@ PseudoVFREDMIN_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:2968
LIEF::assembly::riscv::OPCODE::VWMULSU_VX
@ VWMULSU_VX
Definition riscv/opcodes.hpp:13820
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_MF2
@ PseudoVLUXSEG5EI32_V_M2_MF2
Definition riscv/opcodes.hpp:6110
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M1_MASK
@ PseudoVSSEG3E32_V_M1_MASK
Definition riscv/opcodes.hpp:10036
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_M2
@ PseudoVC_V_VV_M2
Definition riscv/opcodes.hpp:1329
LIEF::assembly::riscv::OPCODE::VSSSEG4E32_V
@ VSSSEG4E32_V
Definition riscv/opcodes.hpp:13745
LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W_AQ
@ SSAMOSWAP_W_AQ
Definition riscv/opcodes.hpp:13009
LIEF::assembly::riscv::OPCODE::FMV_H_X
@ FMV_H_X
Definition riscv/opcodes.hpp:12730
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M2_E16
@ PseudoVFDIV_VFPR16_M2_E16
Definition riscv/opcodes.hpp:1865
LIEF::assembly::riscv::OPCODE::CV_MIN_H
@ CV_MIN_H
Definition riscv/opcodes.hpp:12365
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF8_MASK
@ PseudoVSUXSEG4EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:10932
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_M1_MASK
@ PseudoVLUXSEG2EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:5789
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M4_E64
@ PseudoVFMSAC_VV_M4_E64
Definition riscv/opcodes.hpp:2238
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FMIN
@ G_ATOMICRMW_FMIN
Definition riscv/opcodes.hpp:137
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF4
@ PseudoVSUXSEG6EI32_V_M1_MF4
Definition riscv/opcodes.hpp:11119
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_M1
@ PseudoVLSEG8E32_V_M1
Definition riscv/opcodes.hpp:5374
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_M2
@ PseudoVC_V_VV_SE_M2
Definition riscv/opcodes.hpp:1336
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E16_MASK
@ PseudoVFSGNJN_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3158
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_MF2
@ PseudoVLSSEG5E32_V_MF2
Definition riscv/opcodes.hpp:5498
LIEF::assembly::riscv::OPCODE::HWASAN_CHECK_MEMACCESS_SHORTGRANULES
@ HWASAN_CHECK_MEMACCESS_SHORTGRANULES
Definition riscv/opcodes.hpp:327
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M2_E16
@ PseudoVFWCVT_F_F_V_M2_E16
Definition riscv/opcodes.hpp:3563
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M4_MASK
@ PseudoVLSEG2E64FF_V_M4_MASK
Definition riscv/opcodes.hpp:5095
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M1_MASK
@ PseudoVSOXSEG2EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9276
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF2
@ PseudoVWMACCSU_VX_MF2
Definition riscv/opcodes.hpp:11473
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_M1
@ PseudoVNCLIP_WX_M1
Definition riscv/opcodes.hpp:7486
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M8
@ PseudoVMSBC_VVM_M8
Definition riscv/opcodes.hpp:6913
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M2_MASK
@ PseudoVNMSAC_VV_M2_MASK
Definition riscv/opcodes.hpp:7501
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF2
@ PseudoVLOXEI16_V_MF4_MF2
Definition riscv/opcodes.hpp:4214
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M4_E16
@ PseudoVFWADD_WFPR16_M4_E16
Definition riscv/opcodes.hpp:3491
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF8_MASK
@ PseudoVMSLEU_VV_MF8_MASK
Definition riscv/opcodes.hpp:7106
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_MF2
@ PseudoVAESDF_VS_M8_MF2
Definition riscv/opcodes.hpp:658
LIEF::assembly::riscv::OPCODE::MOPRR2
@ MOPRR2
Definition riscv/opcodes.hpp:12894
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E16
@ PseudoVREMU_VV_MF4_E16
Definition riscv/opcodes.hpp:8122
LIEF::assembly::riscv::OPCODE::VWADDU_VV
@ VWADDU_VV
Definition riscv/opcodes.hpp:13804
LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_M8
@ PseudoVC_I_SE_M8
Definition riscv/opcodes.hpp:1142
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF4
@ PseudoVSADDU_VI_MF4
Definition riscv/opcodes.hpp:8614
LIEF::assembly::riscv::OPCODE::UNZIP_RV32
@ UNZIP_RV32
Definition riscv/opcodes.hpp:13130
LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_MF8
@ PseudoVC_VVV_SE_MF8
Definition riscv/opcodes.hpp:1152
LIEF::assembly::riscv::OPCODE::TH_FSURD
@ TH_FSURD
Definition riscv/opcodes.hpp:13052
LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B4
@ PseudoVSM_V_B4
Definition riscv/opcodes.hpp:8996
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M2_MASK
@ PseudoVRGATHEREI16_VV_M1_E8_M2_MASK
Definition riscv/opcodes.hpp:8301
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M8_MASK
@ PseudoVMSLEU_VV_M8_MASK
Definition riscv/opcodes.hpp:7100
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_M1_MASK
@ PseudoVSUXEI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10530
LIEF::assembly::riscv::OPCODE::VRGATHER_VI
@ VRGATHER_VI
Definition riscv/opcodes.hpp:13608
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF2
@ PseudoVLSSEG6E16_V_MF2
Definition riscv/opcodes.hpp:5512
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E8_MASK
@ PseudoVREDMIN_VS_M4_E8_MASK
Definition riscv/opcodes.hpp:7899
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF2_E16
@ PseudoVFCVT_RM_F_XU_V_MF2_E16
Definition riscv/opcodes.hpp:1755
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16
@ PseudoVFWSUB_WV_MF2_E16
Definition riscv/opcodes.hpp:4033
LIEF::assembly::riscv::OPCODE::VWMULSU_VV
@ VWMULSU_VV
Definition riscv/opcodes.hpp:13819
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF4_MASK
@ PseudoVWMUL_VX_MF4_MASK
Definition riscv/opcodes.hpp:11608
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF4_MASK
@ PseudoVADD_VV_MF4_MASK
Definition riscv/opcodes.hpp:623
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAUS_VX_M8
@ PseudoTHVdotVMAQAUS_VX_M8
Definition riscv/opcodes.hpp:476
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_MF2
@ PseudoVSUXSEG5EI64_V_M4_MF2
Definition riscv/opcodes.hpp:11071
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M8_MASK
@ PseudoVSMUL_VV_M8_MASK
Definition riscv/opcodes.hpp:8971
LIEF::assembly::riscv::OPCODE::ORC_B
@ ORC_B
Definition riscv/opcodes.hpp:12907
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E8_MASK
@ PseudoVWREDSUM_VS_M4_E8_MASK
Definition riscv/opcodes.hpp:11664
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M4_E32
@ PseudoVFNCVT_RM_F_XU_W_M4_E32
Definition riscv/opcodes.hpp:2499
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF2
@ PseudoVLUXSEG8EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:6396
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M2
@ PseudoVXOR_VX_M2
Definition riscv/opcodes.hpp:11869
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF2_MASK
@ PseudoVLSEG3E16FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5131
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF4
@ PseudoVLUXEI64_V_M1_MF4
Definition riscv/opcodes.hpp:5654
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M2_MASK
@ PseudoVSOXSEG2EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9236
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M8_MASK
@ PseudoVLUXEI8_V_M1_M8_MASK
Definition riscv/opcodes.hpp:5689
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M2
@ PseudoVLUXEI8_V_M1_M2
Definition riscv/opcodes.hpp:5684
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M2_E16_MASK
@ PseudoVFRDIV_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2878
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF4
@ PseudoVSSEG8E8_V_MF4
Definition riscv/opcodes.hpp:10159
LIEF::assembly::riscv::OPCODE::FMADD_D
@ FMADD_D
Definition riscv/opcodes.hpp:12686
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M1_E16
@ PseudoVFWSUB_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3955
LIEF::assembly::riscv::OPCODE::C_MOP11
@ C_MOP11
Definition riscv/opcodes.hpp:12513
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_M1_MASK
@ PseudoVWMULSU_VX_M1_MASK
Definition riscv/opcodes.hpp:11552
LIEF::assembly::riscv::OPCODE::C_SRAI64_HINT
@ C_SRAI64_HINT
Definition riscv/opcodes.hpp:12537
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_M1_MASK
@ PseudoVLUXSEG3EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:5883
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_M1_MASK
@ PseudoVLOXSEG5EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4711
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E16_MASK
@ PseudoVREDAND_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:7709
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M8_E32
@ PseudoVFSGNJN_VFPR32_M8_E32
Definition riscv/opcodes.hpp:3139
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF8_MASK
@ PseudoVMSGT_VX_MF8_MASK
Definition riscv/opcodes.hpp:7064
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M1_E32_MASK
@ PseudoVFMACC_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:1950
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M4_M4
@ PseudoVLUXSEG2EI8_V_M4_M4
Definition riscv/opcodes.hpp:5836
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK
@ PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:1760
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M1
@ PseudoVSUXSEG4EI16_V_M2_M1
Definition riscv/opcodes.hpp:10911
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF2_TIED
@ PseudoVWSUB_WV_MF2_TIED
Definition riscv/opcodes.hpp:11818
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_M1_MASK
@ PseudoVSSEG6E8_V_M1_MASK
Definition riscv/opcodes.hpp:10116
LIEF::assembly::riscv::OPCODE::AMOOR_D
@ AMOOR_D
Definition riscv/opcodes.hpp:12071
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E16
@ PseudoVFMAX_VV_M2_E16
Definition riscv/opcodes.hpp:2093
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF2_MASK
@ PseudoVLSEG6E8_V_MF2_MASK
Definition riscv/opcodes.hpp:5313
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF8_MASK
@ PseudoVSSSEG5E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10358
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M4_MASK
@ PseudoVWSLL_VI_M4_MASK
Definition riscv/opcodes.hpp:11688
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E16
@ PseudoVFWNMSAC_VV_M4_E16
Definition riscv/opcodes.hpp:3901
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_MF8
@ PseudoVC_V_XV_SE_MF8
Definition riscv/opcodes.hpp:1381
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_M1
@ PseudoVSOXSEG8EI32_V_M2_M1
Definition riscv/opcodes.hpp:9777
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF4_MASK
@ PseudoVLUXEI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:5603
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E32_MASK
@ PseudoVFWMUL_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3824
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF2_MASK
@ PseudoVSSEG7E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10126
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16_MASK
@ PseudoVFWSUB_WV_MF2_E16_MASK
Definition riscv/opcodes.hpp:4034
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_M1_M1
@ PseudoVLOXSEG5EI8_V_M1_M1
Definition riscv/opcodes.hpp:4750
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E32_MASK
@ PseudoVFWCVT_F_X_V_M2_E32_MASK
Definition riscv/opcodes.hpp:3616
LIEF::assembly::riscv::OPCODE::TH_SURW
@ TH_SURW
Definition riscv/opcodes.hpp:13119
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E32_MASK
@ PseudoVREDMAX_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:7823
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M4_MASK
@ PseudoVMIN_VV_M4_MASK
Definition riscv/opcodes.hpp:6859
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16_V_M1
@ PseudoVLSEG3E16_V_M1
Definition riscv/opcodes.hpp:5134
LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_MF4
@ PseudoVMXNOR_MM_MF4
Definition riscv/opcodes.hpp:7417
LIEF::assembly::riscv::OPCODE::SHA512SUM0R
@ SHA512SUM0R
Definition riscv/opcodes.hpp:12976
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E16_MASK
@ PseudoVREMU_VX_MF4_E16_MASK
Definition riscv/opcodes.hpp:8167
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M2
@ PseudoVSRA_VI_M2
Definition riscv/opcodes.hpp:9865
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M4_M1_MASK
@ PseudoVLUXSEG6EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:6193
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E16_MASK
@ PseudoVRGATHER_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:8457
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E32_MASK
@ PseudoVDIVU_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:1426
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF4_MASK
@ PseudoVWSUBU_WX_MF4_MASK
Definition riscv/opcodes.hpp:11776
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M2_MASK
@ PseudoVMIN_VV_M2_MASK
Definition riscv/opcodes.hpp:6857
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M8
@ PseudoVMV_V_X_M8
Definition riscv/opcodes.hpp:7407
LIEF::assembly::riscv::OPCODE::TH_SYNC_I
@ TH_SYNC_I
Definition riscv/opcodes.hpp:13124
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M2_MASK
@ PseudoVSOXSEG4EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9446
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_MF2
@ PseudoVLUXSEG6EI64_V_M4_MF2
Definition riscv/opcodes.hpp:6218
LIEF::assembly::riscv::OPCODE::CV_SRL_B
@ CV_SRL_B
Definition riscv/opcodes.hpp:12437
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF2
@ PseudoVMINU_VX_MF2
Definition riscv/opcodes.hpp:6848
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E16
@ PseudoVFMACC_VV_MF2_E16
Definition riscv/opcodes.hpp:1991
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_M1
@ PseudoVSUXSEG6EI64_V_M4_M1
Definition riscv/opcodes.hpp:11149
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M2
@ PseudoVNMSUB_VX_M2
Definition riscv/opcodes.hpp:7542
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M1_MASK
@ PseudoVLUXEI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:5667
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16_MASK
@ PseudoVFWADD_WV_M1_E16_MASK
Definition riscv/opcodes.hpp:3506
LIEF::assembly::riscv::OPCODE::FCVT_LU_S_INX
@ FCVT_LU_S_INX
Definition riscv/opcodes.hpp:12608
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E64_MASK
@ PseudoVREDMIN_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:7897
LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_MF2
@ PseudoVC_XVV_SE_MF2
Definition riscv/opcodes.hpp:1400
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M1
@ PseudoVASUBU_VX_M1
Definition riscv/opcodes.hpp:874
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E64_V_M1_MASK
@ PseudoVLSEG6E64_V_M1_MASK
Definition riscv/opcodes.hpp:5301
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E8_MASK
@ PseudoVREM_VV_M2_E8_MASK
Definition riscv/opcodes.hpp:8187
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF4
@ PseudoVMUL_VV_MF4
Definition riscv/opcodes.hpp:7371
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M8_M1_MASK
@ PseudoVSOXSEG6EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:9650
LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_MF2_MASK
@ PseudoVSSE32_V_MF2_MASK
Definition riscv/opcodes.hpp:9968
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M8
@ PseudoVSUXEI32_V_M4_M8
Definition riscv/opcodes.hpp:10567
LIEF::assembly::riscv::OPCODE::MOPR13
@ MOPR13
Definition riscv/opcodes.hpp:12865
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M2_MASK
@ PseudoVLUXEI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5581
LIEF::assembly::riscv::OPCODE::LBU
@ LBU
Definition riscv/opcodes.hpp:12833
LIEF::assembly::riscv::OPCODE::PseudoLongBGE
@ PseudoLongBGE
Definition riscv/opcodes.hpp:402
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF4_MASK
@ PseudoVSMUL_VV_MF4_MASK
Definition riscv/opcodes.hpp:8975
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E64
@ PseudoVRGATHER_VV_M8_E64
Definition riscv/opcodes.hpp:8476
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M2
@ PseudoVSUXEI16_V_M2_M2
Definition riscv/opcodes.hpp:10513
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF8_MASK
@ PseudoVMSLEU_VI_MF8_MASK
Definition riscv/opcodes.hpp:7092
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_M8
@ PseudoVC_V_X_M8
Definition riscv/opcodes.hpp:1385
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_MF4_MASK
@ PseudoVLUXSEG8EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:6399
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E16
@ PseudoVDIVU_VX_MF2_E16
Definition riscv/opcodes.hpp:1499
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF4_MASK
@ PseudoVLOXEI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4217
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M1_MASK
@ PseudoVSUXEI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:10562
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF8_MASK
@ PseudoVLOXSEG4EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:4635
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF8
@ PseudoVNCLIP_WV_MF8
Definition riscv/opcodes.hpp:7484
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_MF4_MASK
@ PseudoVFCVT_XU_F_V_MF4_MASK
Definition riscv/opcodes.hpp:1850
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF8
@ PseudoVSSRL_VV_MF8
Definition riscv/opcodes.hpp:10231
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E64_MASK
@ PseudoVFREC7_V_M2_E64_MASK
Definition riscv/opcodes.hpp:2916
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF2_MASK
@ PseudoVSUXSEG6EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:11170
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_MF4
@ PseudoVFSLIDE1DOWN_VFPR16_MF4
Definition riscv/opcodes.hpp:3311
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E64
@ PseudoVREDMAX_VS_M2_E64
Definition riscv/opcodes.hpp:7800
LIEF::assembly::riscv::OPCODE::G_TRUNC
@ G_TRUNC
Definition riscv/opcodes.hpp:150
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M2
@ PseudoVSUXSEG4EI16_V_MF2_M2
Definition riscv/opcodes.hpp:10919
LIEF::assembly::riscv::OPCODE::G_UREM
@ G_UREM
Definition riscv/opcodes.hpp:81
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_M1
@ PseudoVSUXSEG2EI8_V_MF8_M1
Definition riscv/opcodes.hpp:10787
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_M1_MASK
@ PseudoVSSSEG5E32_V_M1_MASK
Definition riscv/opcodes.hpp:10346
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_M1_MASK
@ PseudoVSUXSEG5EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:11070
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF8
@ PseudoVLUXSEG5EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:6120
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF4
@ PseudoVSUXSEG7EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:11185
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M4
@ PseudoVSUXSEG2EI64_V_M4_M4
Definition riscv/opcodes.hpp:10749
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF2_MASK
@ PseudoVSUB_VV_MF2_MASK
Definition riscv/opcodes.hpp:10484
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M1_MASK
@ PseudoVFWCVT_RTZ_XU_F_V_M1_MASK
Definition riscv/opcodes.hpp:3658
LIEF::assembly::riscv::OPCODE::FROUNDNX_S
@ FROUNDNX_S
Definition riscv/opcodes.hpp:12752
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF2_E16
@ PseudoVFWNMSAC_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3881
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_M1_MASK
@ PseudoVLSEG8E8FF_V_M1_MASK
Definition riscv/opcodes.hpp:5383
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M1_E16
@ PseudoVFMAX_VV_M1_E16
Definition riscv/opcodes.hpp:2087
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M1_MASK
@ PseudoTHVdotVMAQASU_VV_M1_MASK
Definition riscv/opcodes.hpp:451
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_M1
@ PseudoVSUXSEG8EI8_V_MF4_M1
Definition riscv/opcodes.hpp:11321
LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B1
@ PseudoVSM_V_B1
Definition riscv/opcodes.hpp:8992
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF8_MASK
@ PseudoVSOXSEG8EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:9790
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF4
@ PseudoVWADD_WV_MF4
Definition riscv/opcodes.hpp:11435
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF2_MASK
@ PseudoVSSSEG6E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10362
LIEF::assembly::riscv::OPCODE::VSRA_VI
@ VSRA_VI
Definition riscv/opcodes.hpp:13692
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_XOR
@ G_VECREDUCE_XOR
Definition riscv/opcodes.hpp:312
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_MF2_E32
@ PseudoVFMACC_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:1957
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF4_MASK
@ PseudoVSUXSEG4EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:10958
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF8_MASK
@ PseudoVMSEQ_VV_MF8_MASK
Definition riscv/opcodes.hpp:6979
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_M1_MASK
@ PseudoVFNRCLIP_XU_F_QF_M1_MASK
Definition riscv/opcodes.hpp:2856
LIEF::assembly::riscv::OPCODE::EBREAK
@ EBREAK
Definition riscv/opcodes.hpp:12556
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M1
@ PseudoVMFLT_VFPR32_M1
Definition riscv/opcodes.hpp:6754
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF8_MASK
@ PseudoVSUXSEG3EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:10858
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF4_MASK
@ PseudoVFNCVT_XU_F_W_MF4_MASK
Definition riscv/opcodes.hpp:2600
LIEF::assembly::riscv::OPCODE::VDIV_VX
@ VDIV_VX
Definition riscv/opcodes.hpp:13203
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M1_MASK
@ PseudoVSUXSEG2EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10738
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_M1
@ PseudoVSSEG6E16_V_M1
Definition riscv/opcodes.hpp:10103
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M1
@ PseudoVSOXSEG4EI8_V_MF4_M1
Definition riscv/opcodes.hpp:9495
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E16
@ PseudoVDIV_VV_M2_E16
Definition riscv/opcodes.hpp:1519
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M1
@ PseudoVLOXSEG4EI8_V_M1_M1
Definition riscv/opcodes.hpp:4662
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_M1
@ PseudoVSUXSEG5EI16_V_MF4_M1
Definition riscv/opcodes.hpp:11027
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M8_MASK
@ PseudoVSADD_VV_M8_MASK
Definition riscv/opcodes.hpp:8667
LIEF::assembly::riscv::OPCODE::LUI
@ LUI
Definition riscv/opcodes.hpp:12851
LIEF::assembly::riscv::OPCODE::VSUXSEG7EI8_V
@ VSUXSEG7EI8_V
Definition riscv/opcodes.hpp:13797
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E64
@ PseudoVCOMPRESS_VM_M2_E64
Definition riscv/opcodes.hpp:1020
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M2_E32
@ PseudoVFSGNJN_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3135
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M1_MASK
@ PseudoVLOXSEG2EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4355
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E64_MASK
@ PseudoVREMU_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:8089
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M1_MF2_MASK
@ PseudoVSOXSEG8EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9754
LIEF::assembly::riscv::OPCODE::FLT_D_IN32X
@ FLT_D_IN32X
Definition riscv/opcodes.hpp:12679
LIEF::assembly::riscv::OPCODE::VLSSEG2E32_V
@ VLSSEG2E32_V
Definition riscv/opcodes.hpp:13425
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK
@ PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK
Definition riscv/opcodes.hpp:2430
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M4
@ PseudoVLUXSEG2EI64_V_M8_M4
Definition riscv/opcodes.hpp:5824
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M2_M1_MASK
@ PseudoVLOXSEG4EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4645
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_MF2
@ PseudoTHVdotVMAQASU_VX_MF2
Definition riscv/opcodes.hpp:468
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M4_MASK
@ PseudoVOR_VV_M4_MASK
Definition riscv/opcodes.hpp:7645
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M4_MASK
@ PseudoVSLIDEDOWN_VI_M4_MASK
Definition riscv/opcodes.hpp:8827
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E8
@ PseudoVREDMINU_VS_M4_E8
Definition riscv/opcodes.hpp:7854
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M1
@ PseudoVSSRA_VX_M1
Definition riscv/opcodes.hpp:10191
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E32_V_MF2_MASK
@ PseudoVSSEG4E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10068
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_MF2
@ PseudoVNSRL_WV_MF2
Definition riscv/opcodes.hpp:7608
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_MF2_E32
@ PseudoVFSGNJN_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3141
LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M2
@ PseudoVSHA2CL_VV_M2
Definition riscv/opcodes.hpp:8785
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M4_M2
@ PseudoVSUXSEG4EI64_V_M4_M2
Definition riscv/opcodes.hpp:10979
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_MF2_MASK
@ PseudoVLOXSEG3EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4511
LIEF::assembly::riscv::OPCODE::CV_SUBROTMJ_DIV4
@ CV_SUBROTMJ_DIV4
Definition riscv/opcodes.hpp:12449
LIEF::assembly::riscv::OPCODE::TH_LRBU
@ TH_LRBU
Definition riscv/opcodes.hpp:13073
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF2_MASK
@ PseudoVSEXT_VF2_MF2_MASK
Definition riscv/opcodes.hpp:8758
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M2_MASK
@ PseudoVFSLIDE1UP_VFPR32_M2_MASK
Definition riscv/opcodes.hpp:3346
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E16_MASK
@ PseudoVFNMSUB_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:2838
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M1
@ PseudoVSMUL_VX_M1
Definition riscv/opcodes.hpp:8978
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M2_MASK
@ PseudoVSOXSEG2EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9166
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M1
@ PseudoVCLMUL_VX_M1
Definition riscv/opcodes.hpp:986
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M4_MASK
@ PseudoVLE8FF_V_M4_MASK
Definition riscv/opcodes.hpp:4148
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E64_MASK
@ PseudoVREMU_VX_M1_E64_MASK
Definition riscv/opcodes.hpp:8133
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF2_MASK
@ PseudoVSOXSEG8EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9794
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M8_M1_MASK
@ PseudoVLUXSEG5EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:6141
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_M1
@ PseudoVSUXSEG6EI64_V_M1_M1
Definition riscv/opcodes.hpp:11135
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF4_MASK
@ PseudoVWMACCSU_VV_MF4_MASK
Definition riscv/opcodes.hpp:11464
LIEF::assembly::riscv::OPCODE::VWMACCU_VV
@ VWMACCU_VV
Definition riscv/opcodes.hpp:13815
LIEF::assembly::riscv::OPCODE::FCVT_LU_H_INX
@ FCVT_LU_H_INX
Definition riscv/opcodes.hpp:12606
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_MF2_MASK
@ PseudoVSOXSEG3EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9384
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_M1
@ PseudoVSUXSEG5EI64_V_M4_M1
Definition riscv/opcodes.hpp:11069
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF4_MASK
@ PseudoVSOXSEG3EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:9362
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF2
@ PseudoVFWCVT_RTZ_X_F_V_MF2
Definition riscv/opcodes.hpp:3673
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_M2
@ PseudoVROR_VI_M2
Definition riscv/opcodes.hpp:8536
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF4
@ PseudoVLOXSEG2EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:4366
LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SCI_B
@ CV_DOTUSP_SCI_B
Definition riscv/opcodes.hpp:12295
LIEF::assembly::riscv::OPCODE::FCLASS_S_INX
@ FCLASS_S_INX
Definition riscv/opcodes.hpp:12571
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E32_MASK
@ PseudoVFCVT_RM_F_X_V_M2_E32_MASK
Definition riscv/opcodes.hpp:1770
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M2_MASK
@ PseudoTHVdotVMAQA_VV_M2_MASK
Definition riscv/opcodes.hpp:503
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E64
@ PseudoVREDAND_VS_M4_E64
Definition riscv/opcodes.hpp:7720
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_AND
@ G_VECREDUCE_AND
Definition riscv/opcodes.hpp:310
LIEF::assembly::riscv::OPCODE::AMOSWAP_H_AQ
@ AMOSWAP_H_AQ
Definition riscv/opcodes.hpp:12092
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF2
@ PseudoVSADD_VI_MF2
Definition riscv/opcodes.hpp:8654
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E64_V_M1_MASK
@ PseudoVLSSEG7E64_V_M1_MASK
Definition riscv/opcodes.hpp:5541
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M2_MASK
@ PseudoVLUXSEG4EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:6003
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M2
@ PseudoVSUXSEG3EI16_V_M2_M2
Definition riscv/opcodes.hpp:10803
LIEF::assembly::riscv::OPCODE::G_CTTZ_ZERO_UNDEF
@ G_CTTZ_ZERO_UNDEF
Definition riscv/opcodes.hpp:256
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF4
@ PseudoVLUXSEG3EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:5914
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E64
@ PseudoVFMAX_VV_M2_E64
Definition riscv/opcodes.hpp:2097
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_M4
@ PseudoVC_V_XVW_M4
Definition riscv/opcodes.hpp:1358
LIEF::assembly::riscv::OPCODE::G_TRAP
@ G_TRAP
Definition riscv/opcodes.hpp:297
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E64
@ PseudoVFMIN_VV_M1_E64
Definition riscv/opcodes.hpp:2166
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E64_MASK
@ PseudoVFMACC_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:1990
LIEF::assembly::riscv::OPCODE::VREDMIN_VS
@ VREDMIN_VS
Definition riscv/opcodes.hpp:13598
LIEF::assembly::riscv::OPCODE::PSEUDO_PROBE
@ PSEUDO_PROBE
Definition riscv/opcodes.hpp:47
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M8_E32_MASK
@ PseudoVFSGNJN_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:3140
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF4_E16_MASK
@ PseudoVFMADD_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:2056
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E32
@ PseudoVRGATHER_VV_MF2_E32
Definition riscv/opcodes.hpp:8482
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_MF2_MASK
@ PseudoVFWCVT_RM_X_F_V_MF2_MASK
Definition riscv/opcodes.hpp:3654
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E16_MASK
@ PseudoVFMSUB_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:2295
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR64_M4_E64
@ PseudoVFMSAC_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2218
LIEF::assembly::riscv::OPCODE::CV_SUB_B
@ CV_SUB_B
Definition riscv/opcodes.hpp:12455
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF2
@ PseudoVLUXSEG2EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:5790
LIEF::assembly::riscv::OPCODE::MOPR0
@ MOPR0
Definition riscv/opcodes.hpp:12860
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M4_MASK
@ PseudoVFWCVT_RM_XU_F_V_M4_MASK
Definition riscv/opcodes.hpp:3642
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E8
@ PseudoVREDMAX_VS_MF4_E8
Definition riscv/opcodes.hpp:7828
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_MF2_MASK
@ PseudoVLUXSEG4EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:6013
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M8
@ PseudoVMFNE_VFPR16_M8
Definition riscv/opcodes.hpp:6790
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M1
@ PseudoVSM4R_VV_M1
Definition riscv/opcodes.hpp:8959
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M4_MASK
@ PseudoVSOXSEG2EI8_V_M1_M4_MASK
Definition riscv/opcodes.hpp:9260
LIEF::assembly::riscv::OPCODE::G_FMINIMUM
@ G_FMINIMUM
Definition riscv/opcodes.hpp:228
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_M4
@ PseudoVSLL_VV_M4
Definition riscv/opcodes.hpp:8896
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E32_MASK
@ PseudoVFRSQRT7_V_M4_E32_MASK
Definition riscv/opcodes.hpp:3076
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M1
@ PseudoVSOXSEG2EI64_V_M2_M1
Definition riscv/opcodes.hpp:9233
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E16
@ PseudoVFNMSAC_VV_M8_E16
Definition riscv/opcodes.hpp:2783
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_M4
@ PseudoVC_V_FPR64V_M4
Definition riscv/opcodes.hpp:1242
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M8_E32_MASK
@ PseudoVRGATHER_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:8475
LIEF::assembly::riscv::OPCODE::SSAMOSWAP_W_RL
@ SSAMOSWAP_W_RL
Definition riscv/opcodes.hpp:13011
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M8_MASK
@ PseudoVLOXEI8_V_M4_M8_MASK
Definition riscv/opcodes.hpp:4307
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M2_M1_MASK
@ PseudoVLUXSEG7EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6247
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M4_MASK
@ PseudoVLSEG2E64_V_M4_MASK
Definition riscv/opcodes.hpp:5101
LIEF::assembly::riscv::OPCODE::PseudoVSETVLIX0
@ PseudoVSETVLIX0
Definition riscv/opcodes.hpp:8748
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M4_MASK
@ PseudoVSOXEI64_V_M8_M4_MASK
Definition riscv/opcodes.hpp:9108
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF2_MASK
@ PseudoVLUXSEG8EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6357
LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_M4
@ PseudoVC_XV_SE_M4
Definition riscv/opcodes.hpp:1411
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M1_MASK
@ PseudoVLUXSEG2EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5727
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M1
@ PseudoVWSUBU_VX_M1
Definition riscv/opcodes.hpp:11731
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF8
@ PseudoVLOXEI16_V_MF4_MF8
Definition riscv/opcodes.hpp:4218
LIEF::assembly::riscv::OPCODE::SFENCE_VMA
@ SFENCE_VMA
Definition riscv/opcodes.hpp:12953
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E32
@ PseudoVFNMACC_VV_MF2_E32
Definition riscv/opcodes.hpp:2671
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E8
@ PseudoVDIVU_VX_MF4_E8
Definition riscv/opcodes.hpp:1507
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E32
@ PseudoVDIV_VX_MF2_E32
Definition riscv/opcodes.hpp:1589
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M2_E64_MASK
@ PseudoVFSGNJX_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:3206
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E64_V_M4
@ PseudoVSSEG2E64_V_M4
Definition riscv/opcodes.hpp:10013
LIEF::assembly::riscv::OPCODE::AMOXOR_B
@ AMOXOR_B
Definition riscv/opcodes.hpp:12099
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF4_MASK
@ PseudoVSOXSEG3EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9316
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M2_E32_MASK
@ PseudoVFNMSAC_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2750
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF2
@ PseudoVSUXEI16_V_MF4_MF2
Definition riscv/opcodes.hpp:10539
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M8_E32
@ PseudoVFWREDOSUM_VS_M8_E32
Definition riscv/opcodes.hpp:3925
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF8_MASK
@ PseudoVXOR_VV_MF8_MASK
Definition riscv/opcodes.hpp:11866
LIEF::assembly::riscv::OPCODE::TH_LWIB
@ TH_LWIB
Definition riscv/opcodes.hpp:13088
LIEF::assembly::riscv::OPCODE::CTZW
@ CTZW
Definition riscv/opcodes.hpp:12160
LIEF::assembly::riscv::OPCODE::G_UADDE
@ G_UADDE
Definition riscv/opcodes.hpp:171
LIEF::assembly::riscv::OPCODE::TH_LHIB
@ TH_LHIB
Definition riscv/opcodes.hpp:13069
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK
@ PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK
Definition riscv/opcodes.hpp:8397
LIEF::assembly::riscv::OPCODE::G_UMULFIX
@ G_UMULFIX
Definition riscv/opcodes.hpp:189
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M4_MASK
@ PseudoVMSLT_VX_M4_MASK
Definition riscv/opcodes.hpp:7212
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M4_E64_MASK
@ PseudoVFNMACC_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2642
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M8_E32
@ PseudoVFCVT_F_X_V_M8_E32
Definition riscv/opcodes.hpp:1721
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M4_M1_MASK
@ PseudoVSOXSEG7EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9702
LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M1
@ PseudoVLE32_V_M1
Definition riscv/opcodes.hpp:4117
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M4_E32
@ PseudoVFWNMACC_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3853
LIEF::assembly::riscv::OPCODE::C_UNIMP
@ C_UNIMP
Definition riscv/opcodes.hpp:12546
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF4_MASK
@ PseudoVSUXSEG8EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:11332
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M4
@ PseudoVSLIDEDOWN_VI_M4
Definition riscv/opcodes.hpp:8826
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E32
@ PseudoVFSUB_VV_M4_E32
Definition riscv/opcodes.hpp:3435
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E64_MASK
@ PseudoVDIVU_VX_M8_E64_MASK
Definition riscv/opcodes.hpp:1496
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M2_MASK
@ PseudoVSSEG2E8_V_M2_MASK
Definition riscv/opcodes.hpp:10018
LIEF::assembly::riscv::OPCODE::VFMSAC_VV
@ VFMSAC_VV
Definition riscv/opcodes.hpp:13226
LIEF::assembly::riscv::OPCODE::CV_INSERT_B
@ CV_INSERT_B
Definition riscv/opcodes.hpp:12316
LIEF::assembly::riscv::OPCODE::HSV_H
@ HSV_H
Definition riscv/opcodes.hpp:12809
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_MF8
@ PseudoVLSEG2E8_V_MF8
Definition riscv/opcodes.hpp:5124
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF4
@ PseudoVSSUBU_VX_MF4
Definition riscv/opcodes.hpp:10443
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E8_V_MF4_MASK
@ PseudoVLSSEG6E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5527
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF8
@ PseudoVSOXSEG2EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:9223
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M4_M1
@ PseudoVSOXSEG5EI32_V_M4_M1
Definition riscv/opcodes.hpp:9541
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M4_MASK
@ PseudoVMFNE_VFPR16_M4_MASK
Definition riscv/opcodes.hpp:6789
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M4
@ PseudoVLUXSEG2EI16_V_M4_M4
Definition riscv/opcodes.hpp:5742
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M2_MASK
@ PseudoVSUXEI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:10638
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF2_E16_MASK
@ PseudoVFWNMACC_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3846
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_M1
@ PseudoVLOXSEG6EI64_V_M2_M1
Definition riscv/opcodes.hpp:4818
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_M1_MASK
@ PseudoVSOXEI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9034
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_M1
@ PseudoVRGATHEREI16_VV_MF2_E8_M1
Definition riscv/opcodes.hpp:8410
LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_D_IN32X
@ PseudoQuietFLT_D_IN32X
Definition riscv/opcodes.hpp:426
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M2_E16_MASK
@ PseudoVFWADD_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3454
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M1_E32_MASK
@ PseudoVFMUL_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2325
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E32_MASK
@ PseudoVFSGNJX_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3238
LIEF::assembly::riscv::OPCODE::CV_MACUN
@ CV_MACUN
Definition riscv/opcodes.hpp:12340
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_MF2
@ PseudoVLOXSEG8EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:4994
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF2
@ PseudoVMSLEU_VI_MF2
Definition riscv/opcodes.hpp:7087
LIEF::assembly::riscv::OPCODE::VWREDSUMU_VS
@ VWREDSUMU_VS
Definition riscv/opcodes.hpp:13825
LIEF::assembly::riscv::OPCODE::VWMACCSU_VX
@ VWMACCSU_VX
Definition riscv/opcodes.hpp:13813
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_M2
@ PseudoVAESEF_VS_M2_M2
Definition riscv/opcodes.hpp:703
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E32_V_M1
@ PseudoVLSSEG2E32_V_M1
Definition riscv/opcodes.hpp:5408
LIEF::assembly::riscv::OPCODE::TH_DCACHE_IPA
@ TH_DCACHE_IPA
Definition riscv/opcodes.hpp:13039
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_MF2_MF8_MASK
@ PseudoVSOXSEG6EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:9630
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_M2
@ PseudoVLSEG4E32FF_V_M2
Definition riscv/opcodes.hpp:5200
LIEF::assembly::riscv::OPCODE::G_PTRMASK
@ G_PTRMASK
Definition riscv/opcodes.hpp:237
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M8
@ PseudoVSLIDE1DOWN_VX_M8
Definition riscv/opcodes.hpp:8800
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M1
@ PseudoVSSSEG4E16_V_M1
Definition riscv/opcodes.hpp:10311
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M8_MASK
@ PseudoVMSLTU_VX_M8_MASK
Definition riscv/opcodes.hpp:7185
LIEF::assembly::riscv::OPCODE::PseudoVSETIVLI
@ PseudoVSETIVLI
Definition riscv/opcodes.hpp:8746
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF2
@ PseudoVMFNE_VFPR16_MF2
Definition riscv/opcodes.hpp:6792
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_MF2
@ PseudoVSSEG2E8_V_MF2
Definition riscv/opcodes.hpp:10021
LIEF::assembly::riscv::OPCODE::CM_MVA01S
@ CM_MVA01S
Definition riscv/opcodes.hpp:12145
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M8_E32_MASK
@ PseudoVFMAX_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2076
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF8
@ PseudoVRSUB_VX_MF8
Definition riscv/opcodes.hpp:8602
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF4
@ PseudoVSSEG4E8_V_MF4
Definition riscv/opcodes.hpp:10079
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF2
@ PseudoVSUXSEG2EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:10683
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E32
@ PseudoVDIV_VV_MF2_E32
Definition riscv/opcodes.hpp:1545
LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_2x8x2_M2
@ PseudoVQMACCUS_2x8x2_M2
Definition riscv/opcodes.hpp:7677
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M1
@ PseudoVLOXEI64_V_M2_M1
Definition riscv/opcodes.hpp:4266
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M4_MASK
@ PseudoVMSLEU_VX_M4_MASK
Definition riscv/opcodes.hpp:7112
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M4
@ PseudoVFCVT_RTZ_X_F_V_M4
Definition riscv/opcodes.hpp:1831
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF4
@ PseudoVAND_VV_MF4
Definition riscv/opcodes.hpp:842
LIEF::assembly::riscv::OPCODE::C_LH
@ C_LH
Definition riscv/opcodes.hpp:12504
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_MF2
@ PseudoVFWCVT_XU_F_V_MF2
Definition riscv/opcodes.hpp:3683
LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_M2
@ PseudoVSPILL2_M2
Definition riscv/opcodes.hpp:9832
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_M1_MASK
@ PseudoVSUXSEG7EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11202
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M4_E64_MASK
@ PseudoVFRSUB_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:3118
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR64_M8
@ PseudoVFMV_S_FPR64_M8
Definition riscv/opcodes.hpp:2401
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M2
@ PseudoVWMACCSU_VV_M2
Definition riscv/opcodes.hpp:11457
LIEF::assembly::riscv::OPCODE::VSSSEG7E32_V
@ VSSSEG7E32_V
Definition riscv/opcodes.hpp:13757
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_M1
@ PseudoVLSEG6E16FF_V_M1
Definition riscv/opcodes.hpp:5278
LIEF::assembly::riscv::OPCODE::VLSEG5E32FF_V
@ VLSEG5E32FF_V
Definition riscv/opcodes.hpp:13394
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_M1
@ PseudoVLSSEG7E32_V_M1
Definition riscv/opcodes.hpp:5536
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF8
@ PseudoVMULHSU_VV_MF8
Definition riscv/opcodes.hpp:7289
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_M1_M1
@ PseudoVLUXSEG7EI8_V_M1_M1
Definition riscv/opcodes.hpp:6302
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_M1_MASK
@ PseudoVLSSEG4E8_V_M1_MASK
Definition riscv/opcodes.hpp:5481
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M4_E16
@ PseudoVFMADD_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2001
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF8_MASK
@ PseudoVASUBU_VV_MF8_MASK
Definition riscv/opcodes.hpp:873
LIEF::assembly::riscv::OPCODE::AMOOR_H_AQ
@ AMOOR_H_AQ
Definition riscv/opcodes.hpp:12076
LIEF::assembly::riscv::OPCODE::VSOXSEG2EI8_V
@ VSOXSEG2EI8_V
Definition riscv/opcodes.hpp:13667
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E64
@ PseudoVFSUB_VV_M8_E64
Definition riscv/opcodes.hpp:3443
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E16_MASK
@ PseudoVWREDSUM_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:11648
LIEF::assembly::riscv::OPCODE::PseudoLD
@ PseudoLD
Definition riscv/opcodes.hpp:392
LIEF::assembly::riscv::OPCODE::G_INTRINSIC_CONVERGENT
@ G_INTRINSIC_CONVERGENT
Definition riscv/opcodes.hpp:147
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E16
@ PseudoVDIVU_VV_M2_E16
Definition riscv/opcodes.hpp:1431
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M2_MASK
@ PseudoVSADD_VV_M2_MASK
Definition riscv/opcodes.hpp:8663
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M1
@ PseudoVSADD_VV_M1
Definition riscv/opcodes.hpp:8660
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF2_MASK
@ PseudoVLUXSEG7EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6265
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M8_MASK
@ PseudoVSSRL_VI_M8_MASK
Definition riscv/opcodes.hpp:10212
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M1_MASK
@ PseudoVFSLIDE1UP_VFPR32_M1_MASK
Definition riscv/opcodes.hpp:3344
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M1_MASK
@ PseudoVAND_VX_M1_MASK
Definition riscv/opcodes.hpp:847
LIEF::assembly::riscv::OPCODE::VSLIDEUP_VI
@ VSLIDEUP_VI
Definition riscv/opcodes.hpp:13647
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF8
@ PseudoVSADD_VV_MF8
Definition riscv/opcodes.hpp:8672
LIEF::assembly::riscv::OPCODE::PseudoSD
@ PseudoSD
Definition riscv/opcodes.hpp:442
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M4_E32_MASK
@ PseudoVFWSUB_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3984
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_M1
@ PseudoVSUXEI64_V_M1_M1
Definition riscv/opcodes.hpp:10583
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF4_E16_MASK
@ PseudoVREMU_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:8123
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_MF2_MF8
@ PseudoVAESZ_VS_MF2_MF8
Definition riscv/opcodes.hpp:789
LIEF::assembly::riscv::OPCODE::AMOMIN_W_RL
@ AMOMIN_W_RL
Definition riscv/opcodes.hpp:12066
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF8
@ PseudoVSSE8_V_MF8
Definition riscv/opcodes.hpp:9989
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M4_E16_MASK
@ PseudoVFSGNJ_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3284
LIEF::assembly::riscv::OPCODE::TH_SURD
@ TH_SURD
Definition riscv/opcodes.hpp:13117
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E8_MASK
@ PseudoVRGATHER_VV_M1_E8_MASK
Definition riscv/opcodes.hpp:8455
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M2
@ PseudoVAESDM_VV_M2
Definition riscv/opcodes.hpp:694
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK
@ PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK
Definition riscv/opcodes.hpp:2578
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E16_MASK
@ PseudoVFWSUB_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3978
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF2_E16_MASK
@ PseudoVFNMADD_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2684
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E64
@ PseudoVFSQRT_V_M4_E64
Definition riscv/opcodes.hpp:3377
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M1_MASK
@ PseudoVMUL_VV_M1_MASK
Definition riscv/opcodes.hpp:7362
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E8_MASK
@ PseudoVREDMAX_VS_M4_E8_MASK
Definition riscv/opcodes.hpp:7811
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M8_M2_MASK
@ PseudoVSOXSEG3EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:9372
LIEF::assembly::riscv::OPCODE::VSUXSEG6EI64_V
@ VSUXSEG6EI64_V
Definition riscv/opcodes.hpp:13792
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF4_MASK
@ PseudoVSOXSEG3EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9310
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF4
@ PseudoVLOXSEG8EI32_V_M1_MF4
Definition riscv/opcodes.hpp:4954
LIEF::assembly::riscv::OPCODE::CV_AVG_SC_B
@ CV_AVG_SC_B
Definition riscv/opcodes.hpp:12197
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E8
@ PseudoVREDMAXU_VS_M1_E8
Definition riscv/opcodes.hpp:7750
LIEF::assembly::riscv::OPCODE::AMOAND_B_AQ
@ AMOAND_B_AQ
Definition riscv/opcodes.hpp:11964
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF4_E16_MASK
@ PseudoVFCVT_RM_F_X_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:1790
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M1_E64
@ PseudoVFMADD_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2019
LIEF::assembly::riscv::OPCODE::VC_V_VV
@ VC_V_VV
Definition riscv/opcodes.hpp:13189
LIEF::assembly::riscv::OPCODE::AMOMAXU_W_AQ
@ AMOMAXU_W_AQ
Definition riscv/opcodes.hpp:12016
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M4_MASK
@ PseudoVMSLE_VX_M4_MASK
Definition riscv/opcodes.hpp:7154
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF2_E32_MASK
@ PseudoVFCVT_RM_F_X_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:1788
LIEF::assembly::riscv::OPCODE::FCVT_BF16_S
@ FCVT_BF16_S
Definition riscv/opcodes.hpp:12573
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF8
@ PseudoVLUXSEG4EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:6080
LIEF::assembly::riscv::OPCODE::MOPR6
@ MOPR6
Definition riscv/opcodes.hpp:12888
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_MF4
@ PseudoVLE16_V_MF4
Definition riscv/opcodes.hpp:4105
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M2_E16_MASK
@ PseudoVFNMSAC_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2738
LIEF::assembly::riscv::OPCODE::PseudoVID_V_M8
@ PseudoVID_V_M8
Definition riscv/opcodes.hpp:4061
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_M1
@ PseudoVLSEG7E32FF_V_M1
Definition riscv/opcodes.hpp:5330
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR16_MF4_E16_MASK
@ PseudoVFNMACC_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2626
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E64_MASK
@ PseudoVFNMACC_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:2662
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF4_E16
@ PseudoVREDOR_VS_MF4_E16
Definition riscv/opcodes.hpp:7958
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M1_MASK
@ PseudoVWMULSU_VV_M1_MASK
Definition riscv/opcodes.hpp:11540
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_MF2_E32_MASK
@ PseudoVFWNMSAC_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3892
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF8
@ PseudoVMSLE_VV_MF8
Definition riscv/opcodes.hpp:7147
LIEF::assembly::riscv::OPCODE::C_LUI_HINT
@ C_LUI_HINT
Definition riscv/opcodes.hpp:12509
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E16
@ PseudoVREDOR_VS_M8_E16
Definition riscv/opcodes.hpp:7944
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M1_MASK
@ PseudoVADD_VI_M1_MASK
Definition riscv/opcodes.hpp:599
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF2
@ PseudoVCLMUL_VX_MF2
Definition riscv/opcodes.hpp:994
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M1_E16_MASK
@ PseudoVFWMUL_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3804
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M4_M1_MASK
@ PseudoVSUXSEG6EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:11126
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E64_MASK
@ PseudoVFCVT_RM_F_XU_V_M8_E64_MASK
Definition riscv/opcodes.hpp:1754
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B8
@ PseudoVMSIF_M_B8
Definition riscv/opcodes.hpp:7077
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF4_MASK
@ PseudoVSLIDEUP_VI_MF4_MASK
Definition riscv/opcodes.hpp:8861
LIEF::assembly::riscv::OPCODE::VSSSEG6E8_V
@ VSSSEG6E8_V
Definition riscv/opcodes.hpp:13755
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_MF2_E32_MASK
@ PseudoVFWSUB_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3972
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E32_MASK
@ PseudoVREDMINU_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:7843
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E16
@ PseudoVREDMAX_VS_MF2_E16
Definition riscv/opcodes.hpp:7820
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_MF2
@ PseudoTHVdotVMAQAU_VX_MF2
Definition riscv/opcodes.hpp:498
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF4
@ PseudoVSOXSEG3EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:9397
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_MF2_E32
@ PseudoVFNMSUB_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2815
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_M8
@ PseudoVC_V_XVV_M8
Definition riscv/opcodes.hpp:1345
LIEF::assembly::riscv::OPCODE::VLSSEG4E32_V
@ VLSSEG4E32_V
Definition riscv/opcodes.hpp:13433
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E16
@ PseudoVREM_VV_M4_E16
Definition riscv/opcodes.hpp:8188
LIEF::assembly::riscv::OPCODE::G_USHLSAT
@ G_USHLSAT
Definition riscv/opcodes.hpp:186
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_MF2
@ PseudoVAESEF_VS_M1_MF2
Definition riscv/opcodes.hpp:699
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M4_MASK
@ PseudoVMFGT_VFPR64_M4_MASK
Definition riscv/opcodes.hpp:6697
LIEF::assembly::riscv::OPCODE::G_FSUB
@ G_FSUB
Definition riscv/opcodes.hpp:197
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF2_MASK
@ PseudoVSOXSEG4EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9452
LIEF::assembly::riscv::OPCODE::VMAXU_VX
@ VMAXU_VX
Definition riscv/opcodes.hpp:13497
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M1_MASK
@ PseudoVMAX_VX_M1_MASK
Definition riscv/opcodes.hpp:6557
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E32
@ PseudoVFWCVT_F_F_V_MF2_E32
Definition riscv/opcodes.hpp:3573
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF2_MASK
@ PseudoVSOXSEG5EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9562
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E64
@ PseudoVDIV_VV_M4_E64
Definition riscv/opcodes.hpp:1531
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_MF4
@ PseudoVSUXSEG4EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:11011
LIEF::assembly::riscv::OPCODE::LOAD_STACK_GUARD
@ LOAD_STACK_GUARD
Definition riscv/opcodes.hpp:52
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_M1
@ PseudoVSUXSEG3EI32_V_MF2_M1
Definition riscv/opcodes.hpp:10843
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF4
@ PseudoVSOXSEG3EI64_V_M2_MF4
Definition riscv/opcodes.hpp:9361
LIEF::assembly::riscv::OPCODE::HLVX_WU
@ HLVX_WU
Definition riscv/opcodes.hpp:12799
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_M1_MASK
@ PseudoVSUXSEG5EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11064
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_M1_MASK
@ PseudoVLOXSEG6EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4833
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_M1
@ PseudoVAESDM_VS_M8_M1
Definition riscv/opcodes.hpp:684
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M4_E16_MASK
@ PseudoVFWMSAC_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3772
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M2_E64
@ PseudoVDIV_VX_M2_E64
Definition riscv/opcodes.hpp:1567
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_MF2_MASK
@ PseudoVSUXSEG6EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:11124
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_M2_E32
@ PseudoVFMSAC_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2206
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E8_MASK
@ PseudoVREDMAX_VS_M8_E8_MASK
Definition riscv/opcodes.hpp:7819
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_M4
@ PseudoVAESZ_VS_M8_M4
Definition riscv/opcodes.hpp:783
LIEF::assembly::riscv::OPCODE::TH_LURWU
@ TH_LURWU
Definition riscv/opcodes.hpp:13085
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M1
@ PseudoVSOXSEG2EI32_V_M4_M1
Definition riscv/opcodes.hpp:9207
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF8_MASK
@ PseudoVBREV8_V_MF8_MASK
Definition riscv/opcodes.hpp:929
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF4_MASK
@ PseudoVWMUL_VV_MF4_MASK
Definition riscv/opcodes.hpp:11596
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4_TIED
@ PseudoVWADDU_WV_M4_TIED
Definition riscv/opcodes.hpp:11370
LIEF::assembly::riscv::OPCODE::FCVT_S_WU
@ FCVT_S_WU
Definition riscv/opcodes.hpp:12626
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E16_MASK
@ PseudoVFNMSAC_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:2766
LIEF::assembly::riscv::OPCODE::VROL_VX
@ VROL_VX
Definition riscv/opcodes.hpp:13612
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M2_MASK
@ PseudoVLOXSEG2EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4441
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_M1
@ PseudoVSOXSEG6EI16_V_MF4_M1
Definition riscv/opcodes.hpp:9603
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M4_M4_MASK
@ PseudoVSOXEI64_V_M4_M4_MASK
Definition riscv/opcodes.hpp:9100
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M2_E16_MASK
@ PseudoVFWMACCBF16_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3700
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_M1
@ PseudoVSUXSEG7EI32_V_M1_M1
Definition riscv/opcodes.hpp:11195
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M4
@ PseudoVLUXEI64_V_M8_M4
Definition riscv/opcodes.hpp:5678
LIEF::assembly::riscv::OPCODE::AMOMAX_H_AQ
@ AMOMAX_H_AQ
Definition riscv/opcodes.hpp:12028
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M1_MASK
@ PseudoVSOXSEG4EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9430
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M1_MASK
@ PseudoVSOXSEG4EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9474
LIEF::assembly::riscv::OPCODE::PseudoLA_TLS_GD
@ PseudoLA_TLS_GD
Definition riscv/opcodes.hpp:388
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E16
@ PseudoVFCVT_F_XU_V_M1_E16
Definition riscv/opcodes.hpp:1671
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF8_MASK
@ PseudoVLOXSEG8EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:4969
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E16
@ PseudoVFWCVT_F_X_V_MF2_E16
Definition riscv/opcodes.hpp:3625
LIEF::assembly::riscv::OPCODE::PseudoRVVInitUndefM2
@ PseudoRVVInitUndefM2
Definition riscv/opcodes.hpp:436
LIEF::assembly::riscv::OPCODE::VFWADD_WV
@ VFWADD_WV
Definition riscv/opcodes.hpp:13275
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M4_MASK
@ PseudoTHVdotVMAQAU_VX_M4_MASK
Definition riscv/opcodes.hpp:495
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M1_MASK
@ PseudoVLOXSEG2EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4343
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M1
@ PseudoVLOXSEG2EI8_V_M1_M1
Definition riscv/opcodes.hpp:4434
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_M1_MASK
@ PseudoVLSSEG8E32_V_M1_MASK
Definition riscv/opcodes.hpp:5557
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF4
@ PseudoVNSRL_WI_MF4
Definition riscv/opcodes.hpp:7598
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF4
@ PseudoVSUXEI64_V_M2_MF4
Definition riscv/opcodes.hpp:10597
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M1_MASK
@ PseudoVSE8_V_M1_MASK
Definition riscv/opcodes.hpp:8733
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF8
@ PseudoVMACC_VX_MF8
Definition riscv/opcodes.hpp:6428
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_MF2
@ PseudoVSUXSEG8EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:11289
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VX_M2_MASK
@ PseudoVWADDU_VX_M2_MASK
Definition riscv/opcodes.hpp:11350
LIEF::assembly::riscv::OPCODE::AMOXOR_W_AQ_RL
@ AMOXOR_W_AQ_RL
Definition riscv/opcodes.hpp:12113
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M1
@ PseudoVSUXSEG2EI64_V_M4_M1
Definition riscv/opcodes.hpp:10745
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32_V_M1_MASK
@ PseudoVLSEG4E32_V_M1_MASK
Definition riscv/opcodes.hpp:5205
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M2
@ PseudoVMSGTU_VI_M2
Definition riscv/opcodes.hpp:7011
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_MF2_E32_MASK
@ PseudoVFSGNJN_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3178
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E64_MASK
@ PseudoVFREDUSUM_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:3042
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF2_M1_MASK
@ PseudoVLOXSEG3EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4559
LIEF::assembly::riscv::OPCODE::FMSUB_D
@ FMSUB_D
Definition riscv/opcodes.hpp:12713
LIEF::assembly::riscv::OPCODE::VSSEG5E8_V
@ VSSEG5E8_V
Definition riscv/opcodes.hpp:13717
LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_MF2
@ PseudoVSHA2MS_VV_MF2
Definition riscv/opcodes.hpp:8793
LIEF::assembly::riscv::OPCODE::AMOCAS_H
@ AMOCAS_H
Definition riscv/opcodes.hpp:11991
LIEF::assembly::riscv::OPCODE::EXTRACT_SUBREG
@ EXTRACT_SUBREG
Definition riscv/opcodes.hpp:32
LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SCI_H
@ CV_CMPGEU_SCI_H
Definition riscv/opcodes.hpp:12220
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF8
@ PseudoVAADDU_VV_MF8
Definition riscv/opcodes.hpp:533
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M1_E16
@ PseudoVFWMUL_VV_M1_E16
Definition riscv/opcodes.hpp:3821
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E16_MASK
@ PseudoVFREDMIN_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:2978
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E32_MASK
@ PseudoVWREDSUMU_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:11620
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32_M4
@ PseudoVFMV_S_FPR32_M4
Definition riscv/opcodes.hpp:2395
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M1_MASK
@ PseudoVFCVT_RM_X_F_V_M1_MASK
Definition riscv/opcodes.hpp:1804
LIEF::assembly::riscv::OPCODE::SLL
@ SLL
Definition riscv/opcodes.hpp:12982
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M2_M1
@ PseudoVLOXSEG6EI16_V_M2_M1
Definition riscv/opcodes.hpp:4774
LIEF::assembly::riscv::OPCODE::ADDIW
@ ADDIW
Definition riscv/opcodes.hpp:11933
LIEF::assembly::riscv::OPCODE::VFWMACC_VV
@ VFWMACC_VV
Definition riscv/opcodes.hpp:13288
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M2_E64
@ PseudoVFMUL_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2336
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M1_MASK
@ PseudoVSSUBU_VX_M1_MASK
Definition riscv/opcodes.hpp:10434
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF4_MASK
@ PseudoVRGATHER_VX_MF4_MASK
Definition riscv/opcodes.hpp:8503
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M1_MASK
@ PseudoVWSUB_VV_M1_MASK
Definition riscv/opcodes.hpp:11780
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M1_E32
@ PseudoVFMIN_VV_M1_E32
Definition riscv/opcodes.hpp:2164
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E32
@ PseudoVREDMAXU_VS_M1_E32
Definition riscv/opcodes.hpp:7746
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_MF4
@ PseudoVFWCVT_RTZ_XU_F_V_MF4
Definition riscv/opcodes.hpp:3665
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M1
@ PseudoVLOXEI16_V_M2_M1
Definition riscv/opcodes.hpp:4186
LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M8
@ PseudoVAESKF1_VI_M8
Definition riscv/opcodes.hpp:759
LIEF::assembly::riscv::OPCODE::TH_SWD
@ TH_SWD
Definition riscv/opcodes.hpp:13120
LIEF::assembly::riscv::OPCODE::VSUXSEG7EI32_V
@ VSUXSEG7EI32_V
Definition riscv/opcodes.hpp:13795
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E64
@ PseudoVFNMSUB_VV_M8_E64
Definition riscv/opcodes.hpp:2847
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E8
@ PseudoVDIVU_VV_MF2_E8
Definition riscv/opcodes.hpp:1459
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_MF2_E32
@ PseudoVFWADD_WFPR32_MF2_E32
Definition riscv/opcodes.hpp:3503
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_MF2_E32_MASK
@ PseudoVFMUL_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2333
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E32_MASK
@ PseudoVREDMIN_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:7887
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF2_MASK
@ PseudoVSUXSEG6EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:11110
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M2_E16
@ PseudoVFSGNJX_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3183
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E32
@ PseudoVREDMINU_VS_M4_E32
Definition riscv/opcodes.hpp:7850
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E64
@ PseudoVFADD_VV_M4_E64
Definition riscv/opcodes.hpp:1645
LIEF::assembly::riscv::OPCODE::VSUXSEG2EI32_V
@ VSUXSEG2EI32_V
Definition riscv/opcodes.hpp:13775
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF2_M2_MASK
@ PseudoVLOXEI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:4207
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M8_MASK
@ PseudoVSRL_VX_M8_MASK
Definition riscv/opcodes.hpp:9940
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF8_MASK
@ PseudoVNCLIPU_WV_MF8_MASK
Definition riscv/opcodes.hpp:7449
LIEF::assembly::riscv::OPCODE::PseudoVLE64FF_V_M4_MASK
@ PseudoVLE64FF_V_M4_MASK
Definition riscv/opcodes.hpp:4132
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M1_E32
@ PseudoVFNCVT_F_XU_W_M1_E32
Definition riscv/opcodes.hpp:2455
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M2_E32_MASK
@ PseudoVFMAX_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2072
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_MF2_E16
@ PseudoVFMSUB_VV_MF2_E16
Definition riscv/opcodes.hpp:2306
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4
@ PseudoVWSUB_WV_M4
Definition riscv/opcodes.hpp:11811
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF4_MASK
@ PseudoVSSSEG6E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10376
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M8
@ PseudoVCTZ_V_M8
Definition riscv/opcodes.hpp:1070
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M4_M2
@ PseudoVLUXSEG3EI16_V_M4_M2
Definition riscv/opcodes.hpp:5872
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_M1
@ PseudoVSOXSEG3EI32_V_MF2_M1
Definition riscv/opcodes.hpp:9339
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M4
@ PseudoTHVdotVMAQA_VX_M4
Definition riscv/opcodes.hpp:514
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M2_M2
@ PseudoVSUXSEG4EI16_V_M2_M2
Definition riscv/opcodes.hpp:10913
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E32_MASK
@ PseudoVFNMSAC_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:2792
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M4_E64_MASK
@ PseudoVREDMINU_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:7853
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M2_MASK
@ PseudoVMULHSU_VV_M2_MASK
Definition riscv/opcodes.hpp:7280
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_M1
@ PseudoVLOXSEG7EI32_V_M1_M1
Definition riscv/opcodes.hpp:4870
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E16
@ PseudoVREMU_VX_M8_E16
Definition riscv/opcodes.hpp:8152
LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_MF2
@ PseudoVSHA2CL_VV_MF2
Definition riscv/opcodes.hpp:8788
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_MF2_MASK
@ PseudoVSOXEI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9056
LIEF::assembly::riscv::OPCODE::VSUXSEG2EI8_V
@ VSUXSEG2EI8_V
Definition riscv/opcodes.hpp:13777
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E16
@ PseudoVREDMAXU_VS_M8_E16
Definition riscv/opcodes.hpp:7768
LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M1_MASK
@ PseudoVLE32FF_V_M1_MASK
Definition riscv/opcodes.hpp:4108
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_MF4_MASK
@ PseudoVLOXSEG4EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4615
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E16
@ PseudoVREDMIN_VS_M2_E16
Definition riscv/opcodes.hpp:7884
LIEF::assembly::riscv::OPCODE::VLSSEG3E32_V
@ VLSSEG3E32_V
Definition riscv/opcodes.hpp:13429
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M8_MASK
@ PseudoVSLIDEUP_VX_M8_MASK
Definition riscv/opcodes.hpp:8871
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M2
@ PseudoVMADC_VVM_M2
Definition riscv/opcodes.hpp:6445
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF4_MASK
@ PseudoVLUXSEG6EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:6207
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E64_V_M1
@ PseudoVLSSEG2E64_V_M1
Definition riscv/opcodes.hpp:5416
LIEF::assembly::riscv::OPCODE::FSGNJN_H
@ FSGNJN_H
Definition riscv/opcodes.hpp:12760
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M8_MASK
@ PseudoVMFGT_VFPR64_M8_MASK
Definition riscv/opcodes.hpp:6699
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M4_E32_MASK
@ PseudoVFNCVT_RM_F_X_W_M4_E32_MASK
Definition riscv/opcodes.hpp:2518
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E16
@ PseudoVFSGNJN_VV_M2_E16
Definition riscv/opcodes.hpp:3157
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M4_MASK
@ PseudoVRGATHEREI16_VV_M2_E8_M4_MASK
Definition riscv/opcodes.hpp:8335
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M4_E32
@ PseudoVDIV_VX_M4_E32
Definition riscv/opcodes.hpp:1573
LIEF::assembly::riscv::OPCODE::VSUXSEG4EI16_V
@ VSUXSEG4EI16_V
Definition riscv/opcodes.hpp:13782
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32_MASK_TIED
@ PseudoVFWSUB_WV_M2_E32_MASK_TIED
Definition riscv/opcodes.hpp:4023
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M4_M4_MASK
@ PseudoVLUXSEG2EI16_V_M4_M4_MASK
Definition riscv/opcodes.hpp:5743
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M2_MASK
@ PseudoVSUXSEG3EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:10810
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF2_MASK
@ PseudoVSOXSEG2EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9220
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M4_MASK
@ PseudoVMIN_VX_M4_MASK
Definition riscv/opcodes.hpp:6873
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32V_SE_M2
@ PseudoVC_FPR32V_SE_M2
Definition riscv/opcodes.hpp:1107
LIEF::assembly::riscv::OPCODE::VLSEG3E16_V
@ VLSEG3E16_V
Definition riscv/opcodes.hpp:13377
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M4_E16_MASK
@ PseudoVREDMIN_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:7893
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M8_E16
@ PseudoVFMACC_VV_M8_E16
Definition riscv/opcodes.hpp:1985
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E32
@ PseudoVFWCVT_F_XU_V_M4_E32
Definition riscv/opcodes.hpp:3591
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF2
@ PseudoVSOXSEG2EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:9185
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_M2
@ PseudoVAESEM_VS_M8_M2
Definition riscv/opcodes.hpp:743
LIEF::assembly::riscv::OPCODE::SFENCE_INVAL_IR
@ SFENCE_INVAL_IR
Definition riscv/opcodes.hpp:12952
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF2
@ PseudoVLUXSEG4EI32_V_M1_MF2
Definition riscv/opcodes.hpp:6004
LIEF::assembly::riscv::OPCODE::SHA512SUM0
@ SHA512SUM0
Definition riscv/opcodes.hpp:12975
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M2_MASK
@ PseudoVWADDU_VV_M2_MASK
Definition riscv/opcodes.hpp:11338
LIEF::assembly::riscv::OPCODE::HSV_D
@ HSV_D
Definition riscv/opcodes.hpp:12808
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E16
@ PseudoVREDAND_VS_M4_E16
Definition riscv/opcodes.hpp:7716
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_M1_MASK
@ PseudoVLOXSEG5EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4757
LIEF::assembly::riscv::OPCODE::CV_SHUFFLE2_H
@ CV_SHUFFLE2_H
Definition riscv/opcodes.hpp:12412
LIEF::assembly::riscv::OPCODE::CV_LW_rr_inc
@ CV_LW_rr_inc
Definition riscv/opcodes.hpp:12332
LIEF::assembly::riscv::OPCODE::FEQ_D_INX
@ FEQ_D_INX
Definition riscv/opcodes.hpp:12655
LIEF::assembly::riscv::OPCODE::VWSUBU_VV
@ VWSUBU_VV
Definition riscv/opcodes.hpp:13830
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M2_MASK
@ PseudoVLSEG4E8FF_V_M2_MASK
Definition riscv/opcodes.hpp:5221
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR32_M8_E32_MASK
@ PseudoVFMACC_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:1956
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_M1_MASK
@ PseudoVSOXSEG7EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9678
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E16_MASK
@ PseudoVREDMINU_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:7841
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M4
@ PseudoVLUXSEG2EI16_V_M2_M4
Definition riscv/opcodes.hpp:5738
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_M4
@ PseudoVC_V_VVV_M4
Definition riscv/opcodes.hpp:1304
LIEF::assembly::riscv::OPCODE::VMACC_VX
@ VMACC_VX
Definition riscv/opcodes.hpp:13485
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M1
@ PseudoVMFLE_VV_M1
Definition riscv/opcodes.hpp:6730
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_M1
@ PseudoVSOXSEG5EI64_V_M4_M1
Definition riscv/opcodes.hpp:9565
LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_M2
@ PseudoVMXNOR_MM_M2
Definition riscv/opcodes.hpp:7413
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M1
@ PseudoVLOXSEG2EI32_V_M1_M1
Definition riscv/opcodes.hpp:4370
LIEF::assembly::riscv::OPCODE::AMOAND_H_AQ
@ AMOAND_H_AQ
Definition riscv/opcodes.hpp:11972
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M4
@ PseudoVLSE16_V_M4
Definition riscv/opcodes.hpp:5014
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF4_MASK
@ PseudoVASUB_VX_MF4_MASK
Definition riscv/opcodes.hpp:913
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M4_MASK
@ PseudoVFNCVT_RM_XU_F_W_M4_MASK
Definition riscv/opcodes.hpp:2530
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_MF4
@ PseudoVAESDM_VS_M8_MF4
Definition riscv/opcodes.hpp:688
LIEF::assembly::riscv::OPCODE::VADD_VI
@ VADD_VI
Definition riscv/opcodes.hpp:13138
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF4_MASK
@ PseudoVLSE8_V_MF4_MASK
Definition riscv/opcodes.hpp:5051
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M4_M1_MASK
@ PseudoVSOXSEG8EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9782
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_MF2_E16
@ PseudoVFWSUB_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3961
LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M1
@ PseudoVGMUL_VV_M1
Definition riscv/opcodes.hpp:4050
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF4
@ PseudoVSRL_VX_MF4
Definition riscv/opcodes.hpp:9943
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_M1_MASK
@ PseudoVLUXSEG6EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6183
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M1_MASK
@ PseudoVWSLL_VI_M1_MASK
Definition riscv/opcodes.hpp:11684
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF4_MASK
@ PseudoVMSGTU_VX_MF4_MASK
Definition riscv/opcodes.hpp:7034
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M8_E16
@ PseudoVFSGNJ_VFPR16_M8_E16
Definition riscv/opcodes.hpp:3247
LIEF::assembly::riscv::OPCODE::VLSEG2E16_V
@ VLSEG2E16_V
Definition riscv/opcodes.hpp:13369
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M2
@ PseudoVCLMULH_VX_M2
Definition riscv/opcodes.hpp:960
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M1
@ PseudoVSOXSEG4EI32_V_M1_M1
Definition riscv/opcodes.hpp:9429
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E16
@ PseudoVREMU_VV_M2_E16
Definition riscv/opcodes.hpp:8092
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M4_MASK
@ PseudoVSLL_VI_M4_MASK
Definition riscv/opcodes.hpp:8883
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M2
@ PseudoVOR_VV_M2
Definition riscv/opcodes.hpp:7642
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK
@ PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:1756
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M2_MASK
@ PseudoVSOXEI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9010
LIEF::assembly::riscv::OPCODE::PATCHPOINT
@ PATCHPOINT
Definition riscv/opcodes.hpp:51
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_M4
@ PseudoVNSRA_WI_M4
Definition riscv/opcodes.hpp:7558
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_M1_MASK
@ PseudoVSSSEG3E16_V_M1_MASK
Definition riscv/opcodes.hpp:10284
LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_M1
@ PseudoVMAND_MM_M1
Definition riscv/opcodes.hpp:6507
LIEF::assembly::riscv::OPCODE::FCVT_D_WU
@ FCVT_D_WU
Definition riscv/opcodes.hpp:12585
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M1_MASK
@ PseudoVMFLE_VFPR16_M1_MASK
Definition riscv/opcodes.hpp:6701
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF8_MASK
@ PseudoVMINU_VV_MF8_MASK
Definition riscv/opcodes.hpp:6839
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M2_M2_MASK
@ PseudoVLUXSEG3EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5871
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M1_E16_MASK
@ PseudoVFSGNJ_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3272
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M1
@ PseudoTHVdotVMAQASU_VX_M1
Definition riscv/opcodes.hpp:460
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M8_M1_MASK
@ PseudoVSOXSEG7EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:9730
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M1_MASK
@ PseudoVLUXEI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:5703
LIEF::assembly::riscv::OPCODE::VSLIDE1UP_VX
@ VSLIDE1UP_VX
Definition riscv/opcodes.hpp:13644
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_MF2
@ PseudoVSSSEG2E32_V_MF2
Definition riscv/opcodes.hpp:10263
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_M4_MASK
@ PseudoVLUXSEG2EI64_V_M4_M4_MASK
Definition riscv/opcodes.hpp:5817
LIEF::assembly::riscv::OPCODE::FSGNJX_H_INX
@ FSGNJX_H_INX
Definition riscv/opcodes.hpp:12768
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_MF2_E32
@ PseudoVFNMACC_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2635
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF8
@ PseudoVFNCVT_X_F_W_MF8
Definition riscv/opcodes.hpp:2613
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M8_MASK
@ PseudoVMFNE_VFPR32_M8_MASK
Definition riscv/opcodes.hpp:6803
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M2_MASK
@ PseudoVLOXEI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:4313
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF4
@ PseudoVSLIDEDOWN_VI_MF4
Definition riscv/opcodes.hpp:8832
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M1
@ PseudoVMFLE_VFPR32_M1
Definition riscv/opcodes.hpp:6712
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_MF4
@ PseudoVC_V_XVV_MF4
Definition riscv/opcodes.hpp:1347
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E32
@ PseudoVFSGNJX_VV_M2_E32
Definition riscv/opcodes.hpp:3219
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF4_MASK
@ PseudoVSSSEG4E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10336
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_MF2_MASK
@ PseudoVLSSEG8E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5559
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF8_MASK
@ PseudoVMSLE_VI_MF8_MASK
Definition riscv/opcodes.hpp:7134
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M2_MASK
@ PseudoVMINU_VX_M2_MASK
Definition riscv/opcodes.hpp:6843
LIEF::assembly::riscv::OPCODE::VFMERGE_VFM
@ VFMERGE_VFM
Definition riscv/opcodes.hpp:13222
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M2
@ PseudoVLE16_V_M2
Definition riscv/opcodes.hpp:4097
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF4_MASK
@ PseudoVBREV8_V_MF4_MASK
Definition riscv/opcodes.hpp:927
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_M1_MASK
@ PseudoVFWCVT_RTZ_X_F_V_M1_MASK
Definition riscv/opcodes.hpp:3668
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M4_MASK
@ PseudoVMACC_VV_M4_MASK
Definition riscv/opcodes.hpp:6407
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E8_MASK
@ PseudoVREMU_VV_M2_E8_MASK
Definition riscv/opcodes.hpp:8099
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_M1_MASK
@ PseudoVLUXSEG7EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6283
LIEF::assembly::riscv::OPCODE::VS1R_V
@ VS1R_V
Definition riscv/opcodes.hpp:13618
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_M4
@ PseudoVSADDU_VV_M4
Definition riscv/opcodes.hpp:8622
LIEF::assembly::riscv::OPCODE::AES64ES
@ AES64ES
Definition riscv/opcodes.hpp:11942
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M2_E32
@ PseudoVFMADD_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2011
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF2_MASK
@ PseudoVSSRA_VV_MF2_MASK
Definition riscv/opcodes.hpp:10186
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16_MASK
@ PseudoVFWSUB_WV_M1_E16_MASK
Definition riscv/opcodes.hpp:4010
LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_M1
@ PseudoVC_VV_SE_M1
Definition riscv/opcodes.hpp:1159
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E64_MASK
@ PseudoVFRSQRT7_V_M2_E64_MASK
Definition riscv/opcodes.hpp:3072
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M4_MASK
@ PseudoVLSE16_V_M4_MASK
Definition riscv/opcodes.hpp:5015
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M2_MASK
@ PseudoVMSLT_VV_M2_MASK
Definition riscv/opcodes.hpp:7196
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E8
@ PseudoVREDXOR_VS_M1_E8
Definition riscv/opcodes.hpp:8014
LIEF::assembly::riscv::OPCODE::VSSE8_V
@ VSSE8_V
Definition riscv/opcodes.hpp:13701
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_V_MF8
@ PseudoVMV_V_V_MF8
Definition riscv/opcodes.hpp:7403
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M1
@ PseudoVSUXSEG3EI8_V_M1_M1
Definition riscv/opcodes.hpp:10877
LIEF::assembly::riscv::OPCODE::CV_SRL_SC_H
@ CV_SRL_SC_H
Definition riscv/opcodes.hpp:12442
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF4_MASK
@ PseudoVRSUB_VI_MF4_MASK
Definition riscv/opcodes.hpp:8587
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF4_E16
@ PseudoVFREDMIN_VS_MF4_E16
Definition riscv/opcodes.hpp:2993
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_M1_M1_MASK
@ PseudoVLUXSEG6EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6223
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF8
@ PseudoVLOXSEG2EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:4368
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M2
@ PseudoVSUXSEG2EI64_V_M2_M2
Definition riscv/opcodes.hpp:10739
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M1_MASK
@ PseudoVLUXSEG4EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6055
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_M1_MASK
@ PseudoVSSEG7E8_V_M1_MASK
Definition riscv/opcodes.hpp:10136
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_M1_MASK
@ PseudoVLOXSEG4EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4629
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M1
@ PseudoVWMULU_VX_M1
Definition riscv/opcodes.hpp:11575
LIEF::assembly::riscv::OPCODE::AMOMINU_W_RL
@ AMOMINU_W_RL
Definition riscv/opcodes.hpp:12050
LIEF::assembly::riscv::OPCODE::PseudoJump
@ PseudoJump
Definition riscv/opcodes.hpp:384
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_MF4
@ PseudoVMSLT_VX_MF4
Definition riscv/opcodes.hpp:7217
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M1_MASK
@ PseudoVLSEG4E64_V_M1_MASK
Definition riscv/opcodes.hpp:5215
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_MF2_E16_MASK
@ PseudoVFMSAC_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2201
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_MF2_E16_MASK
@ PseudoVFCVT_RM_F_X_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:1786
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M1
@ PseudoVLUXEI8_V_MF2_M1
Definition riscv/opcodes.hpp:5702
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E8_MASK
@ PseudoVREDSUM_VS_M4_E8_MASK
Definition riscv/opcodes.hpp:7987
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_MF2
@ PseudoVMFGE_VFPR32_MF2
Definition riscv/opcodes.hpp:6660
LIEF::assembly::riscv::OPCODE::AES64DSM
@ AES64DSM
Definition riscv/opcodes.hpp:11941
LIEF::assembly::riscv::OPCODE::CV_SUB_SCI_H
@ CV_SUB_SCI_H
Definition riscv/opcodes.hpp:12461
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_M2
@ PseudoVLOXSEG3EI64_V_M2_M2
Definition riscv/opcodes.hpp:4536
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF2_MASK
@ PseudoVSRL_VX_MF2_MASK
Definition riscv/opcodes.hpp:9942
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M2
@ PseudoVLUXSEG3EI32_V_M1_M2
Definition riscv/opcodes.hpp:5892
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M8
@ PseudoVLOXEI64_V_M8_M8
Definition riscv/opcodes.hpp:4288
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_MF2
@ PseudoVSSEG3E32_V_MF2
Definition riscv/opcodes.hpp:10039
LIEF::assembly::riscv::OPCODE::G_UMULO
@ G_UMULO
Definition riscv/opcodes.hpp:178
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M4
@ PseudoVSSRL_VV_M4
Definition riscv/opcodes.hpp:10223
LIEF::assembly::riscv::OPCODE::VFCVT_F_XU_V
@ VFCVT_F_XU_V
Definition riscv/opcodes.hpp:13207
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M4_MF2
@ PseudoVSUXSEG6EI64_V_M4_MF2
Definition riscv/opcodes.hpp:11151
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF2_MF2
@ PseudoVLOXSEG4EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:4672
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF4
@ PseudoVLOXEI16_V_MF4_MF4
Definition riscv/opcodes.hpp:4216
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16
@ PseudoVFWADD_WV_MF2_E16
Definition riscv/opcodes.hpp:3529
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_MF8_MASK
@ PseudoVLE8FF_V_MF8_MASK
Definition riscv/opcodes.hpp:4156
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E64
@ PseudoVFCVT_F_X_V_M4_E64
Definition riscv/opcodes.hpp:1717
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_M1
@ PseudoVSUXSEG8EI64_V_M1_M1
Definition riscv/opcodes.hpp:11295
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M2_MASK
@ PseudoVMINU_VV_M2_MASK
Definition riscv/opcodes.hpp:6829
LIEF::assembly::riscv::OPCODE::FDIV_D_IN32X
@ FDIV_D_IN32X
Definition riscv/opcodes.hpp:12644
LIEF::assembly::riscv::OPCODE::CV_AVG_SCI_H
@ CV_AVG_SCI_H
Definition riscv/opcodes.hpp:12196
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF8_MF8
@ PseudoVLOXSEG5EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:4768
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF8_MASK
@ PseudoVXOR_VX_MF8_MASK
Definition riscv/opcodes.hpp:11880
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF8
@ PseudoVLOXSEG6EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:4788
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF8_MASK
@ PseudoVSOXSEG4EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:9510
LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M4
@ PseudoVSHA2CH_VV_M4
Definition riscv/opcodes.hpp:8781
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF4_MASK
@ PseudoVMSGTU_VI_MF4_MASK
Definition riscv/opcodes.hpp:7020
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E16_MASK
@ PseudoVREDOR_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:7929
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF4_MASK
@ PseudoVLUXSEG6EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:6215
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M2
@ PseudoVLOXSEG2EI32_V_M4_M2
Definition riscv/opcodes.hpp:4388
LIEF::assembly::riscv::OPCODE::CV_EXTHS
@ CV_EXTHS
Definition riscv/opcodes.hpp:12302
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E64
@ PseudoVFSUB_VV_M1_E64
Definition riscv/opcodes.hpp:3425
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M1
@ PseudoVNCLIP_WV_M1
Definition riscv/opcodes.hpp:7474
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_MF2
@ PseudoVC_V_VV_MF2
Definition riscv/opcodes.hpp:1332
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_M1
@ PseudoVAESZ_VS_M8_M1
Definition riscv/opcodes.hpp:781
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M1_M1
@ PseudoVAESEF_VS_M1_M1
Definition riscv/opcodes.hpp:698
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M4_MASK
@ PseudoVLUXEI32_V_M2_M4_MASK
Definition riscv/opcodes.hpp:5625
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E32
@ PseudoVDIVU_VV_M8_E32
Definition riscv/opcodes.hpp:1449
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_M1
@ PseudoVLOXSEG7EI16_V_MF4_M1
Definition riscv/opcodes.hpp:4862
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E64_MASK
@ PseudoVFCVT_RM_F_X_V_M2_E64_MASK
Definition riscv/opcodes.hpp:1772
LIEF::assembly::riscv::OPCODE::CV_MINU_B
@ CV_MINU_B
Definition riscv/opcodes.hpp:12358
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_MF4_MASK
@ PseudoVLUXSEG2EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:5753
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M4_MASK
@ PseudoVWMACCSU_VX_M4_MASK
Definition riscv/opcodes.hpp:11472
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_MF2_MASK
@ PseudoVFCVT_RM_X_F_V_MF2_MASK
Definition riscv/opcodes.hpp:1812
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF2_MASK
@ PseudoVWMACC_VX_MF2_MASK
Definition riscv/opcodes.hpp:11534
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M8_M2
@ PseudoVLOXSEG4EI32_V_M8_M2
Definition riscv/opcodes.hpp:4626
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF4
@ PseudoVSOXSEG7EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:9681
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E8_MASK
@ PseudoVDIV_VV_MF2_E8_MASK
Definition riscv/opcodes.hpp:1548
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF8_MASK
@ PseudoVNCLIPU_WX_MF8_MASK
Definition riscv/opcodes.hpp:7461
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E8_MASK
@ PseudoVREDOR_VS_M1_E8_MASK
Definition riscv/opcodes.hpp:7927
LIEF::assembly::riscv::OPCODE::LD
@ LD
Definition riscv/opcodes.hpp:12836
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B32
@ PseudoVFIRST_M_B32
Definition riscv/opcodes.hpp:1929
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M2_E64
@ PseudoVFMIN_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2156
LIEF::assembly::riscv::OPCODE::TH_DCACHE_ISW
@ TH_DCACHE_ISW
Definition riscv/opcodes.hpp:13040
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M4
@ PseudoVSOXEI64_V_M8_M4
Definition riscv/opcodes.hpp:9107
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF2
@ PseudoVLOXSEG2EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:4458
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF4_MASK
@ PseudoVMSEQ_VV_MF4_MASK
Definition riscv/opcodes.hpp:6977
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M1
@ PseudoVRGATHEREI16_VV_M2_E16_M1
Definition riscv/opcodes.hpp:8306
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF4_E16
@ PseudoVFNMACC_VV_MF4_E16
Definition riscv/opcodes.hpp:2673
LIEF::assembly::riscv::OPCODE::AMOCAS_W_RL
@ AMOCAS_W_RL
Definition riscv/opcodes.hpp:12002
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M8_M1
@ PseudoVLOXSEG7EI64_V_M8_M1
Definition riscv/opcodes.hpp:4908
LIEF::assembly::riscv::OPCODE::VSSEG4E32_V
@ VSSEG4E32_V
Definition riscv/opcodes.hpp:13711
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E16
@ PseudoVFMADD_VV_M8_E16
Definition riscv/opcodes.hpp:2045
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M4
@ PseudoVSRL_VI_M4
Definition riscv/opcodes.hpp:9909
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M1_M1_MASK
@ PseudoVLUXSEG2EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5827
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M4_M4
@ PseudoVSUXEI8_V_M4_M4
Definition riscv/opcodes.hpp:10629
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M4_E32_MASK
@ PseudoVFWNMSAC_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3890
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF2
@ PseudoVSSEG5E8_V_MF2
Definition riscv/opcodes.hpp:10097
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_MF4_MASK
@ PseudoVSSSEG2E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10256
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M2_E64_MASK
@ PseudoVFMADD_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2022
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E32_MASK
@ PseudoVFNMSAC_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:2780
LIEF::assembly::riscv::OPCODE::AMOOR_D_AQ_RL
@ AMOOR_D_AQ_RL
Definition riscv/opcodes.hpp:12073
LIEF::assembly::riscv::OPCODE::VLSSEG6E8_V
@ VLSSEG6E8_V
Definition riscv/opcodes.hpp:13443
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_M1
@ PseudoVSUXSEG2EI16_V_MF4_M1
Definition riscv/opcodes.hpp:10687
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M2_M1
@ PseudoVSUXSEG5EI16_V_M2_M1
Definition riscv/opcodes.hpp:11019
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF4
@ PseudoVSSRA_VV_MF4
Definition riscv/opcodes.hpp:10187
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M8_MASK
@ PseudoVMSEQ_VV_M8_MASK
Definition riscv/opcodes.hpp:6973
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M2_E16_MASK
@ PseudoVFSUB_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3394
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_M1
@ PseudoVSOXSEG2EI8_V_MF8_M1
Definition riscv/opcodes.hpp:9283
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF2
@ PseudoVSSRA_VV_MF2
Definition riscv/opcodes.hpp:10185
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_M2_MASK
@ PseudoVWMUL_VV_M2_MASK
Definition riscv/opcodes.hpp:11590
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M2_MASK
@ PseudoVFCVT_RM_X_F_V_M2_MASK
Definition riscv/opcodes.hpp:1806
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M2_MASK
@ PseudoVSSSEG4E16_V_M2_MASK
Definition riscv/opcodes.hpp:10314
LIEF::assembly::riscv::OPCODE::MOPR20
@ MOPR20
Definition riscv/opcodes.hpp:12873
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF8
@ PseudoVLUXSEG5EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:6160
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF2
@ PseudoVXOR_VV_MF2
Definition riscv/opcodes.hpp:11861
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M2_MASK
@ PseudoVSOXSEG4EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9476
LIEF::assembly::riscv::OPCODE::MOPRR5
@ MOPRR5
Definition riscv/opcodes.hpp:12897
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_M4_MASK
@ PseudoVSSRL_VI_M4_MASK
Definition riscv/opcodes.hpp:10210
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF2_E32
@ PseudoVFWMACC_VV_MF2_E32
Definition riscv/opcodes.hpp:3763
LIEF::assembly::riscv::OPCODE::VLOXSEG2EI32_V
@ VLOXSEG2EI32_V
Definition riscv/opcodes.hpp:13337
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_MF2_MASK
@ PseudoVLOXSEG4EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4679
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_MF2
@ PseudoVC_V_VVW_SE_MF2
Definition riscv/opcodes.hpp:1325
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M1
@ PseudoVSOXSEG3EI32_V_M4_M1
Definition riscv/opcodes.hpp:9333
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF4
@ PseudoVLUXEI32_V_MF2_MF4
Definition riscv/opcodes.hpp:5646
LIEF::assembly::riscv::OPCODE::AMOSWAP_W_AQ
@ AMOSWAP_W_AQ
Definition riscv/opcodes.hpp:12096
LIEF::assembly::riscv::OPCODE::PseudoFROUND_D
@ PseudoFROUND_D
Definition riscv/opcodes.hpp:374
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M1_E32
@ PseudoVFWNMACC_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3849
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF8
@ PseudoVSUXEI64_V_M1_MF8
Definition riscv/opcodes.hpp:10589
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK
@ PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK
Definition riscv/opcodes.hpp:8279
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M2_E16
@ PseudoVFWSUB_WFPR16_M2_E16
Definition riscv/opcodes.hpp:3993
LIEF::assembly::riscv::OPCODE::AMOMINU_W_AQ_RL
@ AMOMINU_W_AQ_RL
Definition riscv/opcodes.hpp:12049
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF8
@ PseudoVANDN_VV_MF8
Definition riscv/opcodes.hpp:802
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M4_M1_MASK
@ PseudoVLOXSEG6EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4801
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E32
@ PseudoVREDSUM_VS_M8_E32
Definition riscv/opcodes.hpp:7990
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M1
@ PseudoVLOXSEG4EI16_V_M1_M1
Definition riscv/opcodes.hpp:4580
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E64
@ PseudoVFSGNJX_VV_M4_E64
Definition riscv/opcodes.hpp:3227
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF4_M1
@ PseudoVLOXSEG5EI8_V_MF4_M1
Definition riscv/opcodes.hpp:4756
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M4
@ PseudoVMFLT_VFPR32_M4
Definition riscv/opcodes.hpp:6758
LIEF::assembly::riscv::OPCODE::VSSSEG2E8_V
@ VSSSEG2E8_V
Definition riscv/opcodes.hpp:13739
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M4_M4
@ PseudoVSUXSEG2EI8_V_M4_M4
Definition riscv/opcodes.hpp:10769
LIEF::assembly::riscv::OPCODE::G_FLDEXP
@ G_FLDEXP
Definition riscv/opcodes.hpp:211
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_X_F_W_MF2_MASK
@ PseudoVFNCVT_RTZ_X_F_W_MF2_MASK
Definition riscv/opcodes.hpp:2586
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_MF4
@ PseudoVMULH_VV_MF4
Definition riscv/opcodes.hpp:7343
LIEF::assembly::riscv::OPCODE::VMFNE_VV
@ VMFNE_VV
Definition riscv/opcodes.hpp:13512
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M4_E16_MASK
@ PseudoVFDIV_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:1868
LIEF::assembly::riscv::OPCODE::VSSSEG3E16_V
@ VSSSEG3E16_V
Definition riscv/opcodes.hpp:13740
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M2
@ PseudoVAADD_VV_M2
Definition riscv/opcodes.hpp:551
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M4_M1
@ PseudoVLOXSEG7EI32_V_M4_M1
Definition riscv/opcodes.hpp:4880
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF4_MASK
@ PseudoVSSSEG5E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10344
LIEF::assembly::riscv::OPCODE::PseudoVQMACC_2x8x2_M2
@ PseudoVQMACC_2x8x2_M2
Definition riscv/opcodes.hpp:7693
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E16
@ PseudoVFWMACC_VV_M4_E16
Definition riscv/opcodes.hpp:3757
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M4_MASK
@ PseudoVLOXEI32_V_M8_M4_MASK
Definition riscv/opcodes.hpp:4247
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF2
@ PseudoVLSEG5E8_V_MF2
Definition riscv/opcodes.hpp:5272
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF8_E8_MASK
@ PseudoVWREDSUMU_VS_MF8_E8_MASK
Definition riscv/opcodes.hpp:11646
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_M1
@ PseudoVLOXSEG4EI8_V_MF8_M1
Definition riscv/opcodes.hpp:4682
LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_MF2_MASK
@ PseudoVSE32_V_MF2_MASK
Definition riscv/opcodes.hpp:8723
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M4_M2
@ PseudoVAESDM_VS_M4_M2
Definition riscv/opcodes.hpp:679
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E32
@ PseudoVFRSQRT7_V_MF2_E32
Definition riscv/opcodes.hpp:3087
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M4
@ PseudoVROR_VV_M4
Definition riscv/opcodes.hpp:8552
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_MF4
@ PseudoVSSSEG6E16_V_MF4
Definition riscv/opcodes.hpp:10363
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF8_MASK
@ PseudoVLSEG7E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5357
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_MF2
@ PseudoVAESDM_VS_M1_MF2
Definition riscv/opcodes.hpp:670
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_M8
@ PseudoVC_V_FPR16V_SE_M8
Definition riscv/opcodes.hpp:1199
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_MF4
@ PseudoVMSLEU_VI_MF4
Definition riscv/opcodes.hpp:7089
LIEF::assembly::riscv::OPCODE::CSRRSI
@ CSRRSI
Definition riscv/opcodes.hpp:12156
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E16_MASK
@ PseudoVFWCVT_F_X_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:3632
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF2_MASK
@ PseudoVMSGT_VI_MF2_MASK
Definition riscv/opcodes.hpp:7046
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_M2
@ PseudoVC_V_XV_M2
Definition riscv/opcodes.hpp:1369
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M4_MASK
@ PseudoVSSE16_V_M4_MASK
Definition riscv/opcodes.hpp:9952
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF4_MASK
@ PseudoVNMSAC_VX_MF4_MASK
Definition riscv/opcodes.hpp:7523
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M1_MASK
@ PseudoVLOXEI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4187
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M8_E16
@ PseudoVFSGNJX_VFPR16_M8_E16
Definition riscv/opcodes.hpp:3187
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E64
@ PseudoVFREC7_V_M1_E64
Definition riscv/opcodes.hpp:2909
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M8
@ PseudoVAADDU_VX_M8
Definition riscv/opcodes.hpp:541
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF4_E16_MASK
@ PseudoVFMAX_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2068
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M8_E16
@ PseudoVFSGNJN_VFPR16_M8_E16
Definition riscv/opcodes.hpp:3127
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_MF2
@ PseudoVRELOAD6_MF2
Definition riscv/opcodes.hpp:8073
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M8
@ PseudoVMFLE_VFPR64_M8
Definition riscv/opcodes.hpp:6728
LIEF::assembly::riscv::OPCODE::VRGATHEREI16_VV
@ VRGATHEREI16_VV
Definition riscv/opcodes.hpp:13607
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M2
@ PseudoVLSEG4E16FF_V_M2
Definition riscv/opcodes.hpp:5184
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E32
@ PseudoVFMAX_VV_M4_E32
Definition riscv/opcodes.hpp:2101
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M2_MASK
@ PseudoVLUXSEG2EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5807
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VV_M2
@ PseudoTHVdotVMAQASU_VV_M2
Definition riscv/opcodes.hpp:452
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_MF2_E32
@ PseudoVFADD_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:1619
LIEF::assembly::riscv::OPCODE::G_SMIN
@ G_SMIN
Definition riscv/opcodes.hpp:238
LIEF::assembly::riscv::OPCODE::G_SMULH
@ G_SMULH
Definition riscv/opcodes.hpp:181
LIEF::assembly::riscv::OPCODE::PseudoVC_IVW_SE_MF2
@ PseudoVC_IVW_SE_MF2
Definition riscv/opcodes.hpp:1129
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF8_MF8_MASK
@ PseudoVLOXSEG8EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:5009
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E16_MASK
@ PseudoVFWMSAC_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3794
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF2_MASK
@ PseudoVNCLIPU_WI_MF2_MASK
Definition riscv/opcodes.hpp:7433
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF2
@ PseudoVMADD_VX_MF2
Definition riscv/opcodes.hpp:6494
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E32
@ PseudoVFREDMAX_VS_M4_E32
Definition riscv/opcodes.hpp:2949
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF8_MASK
@ PseudoVNMSAC_VV_MF8_MASK
Definition riscv/opcodes.hpp:7511
LIEF::assembly::riscv::OPCODE::VSSSEG5E32_V
@ VSSSEG5E32_V
Definition riscv/opcodes.hpp:13749
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_MF4
@ PseudoVC_FPR16V_SE_MF4
Definition riscv/opcodes.hpp:1095
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E32
@ PseudoVREMU_VX_M2_E32
Definition riscv/opcodes.hpp:8138
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF4_MASK
@ PseudoVSOXSEG7EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9742
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4_MASK_TIED
@ PseudoVWSUBU_WV_M4_MASK_TIED
Definition riscv/opcodes.hpp:11753
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF4_MASK
@ PseudoVLUXSEG7EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:6313
LIEF::assembly::riscv::OPCODE::PseudoFROUND_S_INX
@ PseudoFROUND_S_INX
Definition riscv/opcodes.hpp:380
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_MF4
@ PseudoVAESEM_VS_M8_MF4
Definition riscv/opcodes.hpp:746
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4
@ PseudoVWADDU_WV_M4
Definition riscv/opcodes.hpp:11367
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF8
@ PseudoVLOXSEG8EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:4948
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR32_M2_E32_MASK
@ PseudoVFNMSUB_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2810
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M8
@ PseudoVSOXEI64_V_M8_M8
Definition riscv/opcodes.hpp:9109
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_MF2_E32_MASK
@ PseudoVFNMACC_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:2672
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_MF2
@ PseudoVC_V_VVW_MF2
Definition riscv/opcodes.hpp:1319
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M2_MASK
@ PseudoVANDN_VV_M2_MASK
Definition riscv/opcodes.hpp:793
LIEF::assembly::riscv::OPCODE::TH_LURW
@ TH_LURW
Definition riscv/opcodes.hpp:13084
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E32_MASK
@ PseudoVFNCVTBF16_F_F_W_M4_E32_MASK
Definition riscv/opcodes.hpp:2428
LIEF::assembly::riscv::OPCODE::MINU
@ MINU
Definition riscv/opcodes.hpp:12859
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF4
@ PseudoVLUXSEG7EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:6258
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF2
@ PseudoVFNCVT_RM_X_F_W_MF2
Definition riscv/opcodes.hpp:2543
LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_M1
@ PseudoVMXOR_MM_M1
Definition riscv/opcodes.hpp:7419
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M2_E32_MASK
@ PseudoVFSGNJN_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3136
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E64
@ PseudoVFMUL_VV_M8_E64
Definition riscv/opcodes.hpp:2364
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E16
@ PseudoVREDMIN_VS_M1_E16
Definition riscv/opcodes.hpp:7876
LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_4x8x4_M2
@ PseudoVQMACCU_4x8x4_M2
Definition riscv/opcodes.hpp:7689
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_MF2_MASK
@ PseudoVLUXSEG7EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:6311
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF8
@ PseudoVSUXSEG7EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:11253
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_MF8
@ PseudoVSUXSEG4EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:10959
LIEF::assembly::riscv::OPCODE::G_READ_VLENB
@ G_READ_VLENB
Definition riscv/opcodes.hpp:323
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF2
@ PseudoVSUXSEG4EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:11003
LIEF::assembly::riscv::OPCODE::PseudoVC_XV_SE_MF8
@ PseudoVC_XV_SE_MF8
Definition riscv/opcodes.hpp:1415
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_MF2_MASK
@ PseudoVSOXSEG6EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9594
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF2
@ PseudoVMSGT_VI_MF2
Definition riscv/opcodes.hpp:7045
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M2_MASK
@ PseudoVSSSEG2E32_V_M2_MASK
Definition riscv/opcodes.hpp:10260
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E16_MASK
@ PseudoVFSUB_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3428
LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_MF8
@ PseudoVC_I_SE_MF8
Definition riscv/opcodes.hpp:1145
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E64
@ PseudoVREDAND_VS_M2_E64
Definition riscv/opcodes.hpp:7712
LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M2
@ PseudoVSE32_V_M2
Definition riscv/opcodes.hpp:8716
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF4_MASK
@ PseudoVWMACC_VX_MF4_MASK
Definition riscv/opcodes.hpp:11536
LIEF::assembly::riscv::OPCODE::FCVT_S_BF16
@ FCVT_S_BF16
Definition riscv/opcodes.hpp:12615
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_MF4
@ PseudoVLSSEG7E16_V_MF4
Definition riscv/opcodes.hpp:5534
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF2_MF2_MASK
@ PseudoVSUXSEG2EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10778
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_MF2
@ PseudoVLSEG2E32_V_MF2
Definition riscv/opcodes.hpp:5088
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E16_MASK
@ PseudoVFREC7_V_M4_E16_MASK
Definition riscv/opcodes.hpp:2918
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_MF4_MASK
@ PseudoVLOXSEG3EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4571
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_M2
@ PseudoVLUXEI16_V_MF2_M2
Definition riscv/opcodes.hpp:5598
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M8_M1_MASK
@ PseudoVLOXSEG8EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:4989
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M1_MASK
@ PseudoVSUXEI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:10608
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M1_MASK
@ PseudoVFNCVT_RM_XU_F_W_M1_MASK
Definition riscv/opcodes.hpp:2526
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_M1
@ PseudoVFNRCLIP_X_F_QF_M1
Definition riscv/opcodes.hpp:2865
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M8_MASK
@ PseudoVSUB_VX_M8_MASK
Definition riscv/opcodes.hpp:10496
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_M1_MASK
@ PseudoVLOXSEG7EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4891
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_M1_M1_MASK
@ PseudoVSUXSEG8EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11316
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M4
@ PseudoVLSEG2E64FF_V_M4
Definition riscv/opcodes.hpp:5094
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_I_MF4
@ PseudoVMV_V_I_MF4
Definition riscv/opcodes.hpp:7395
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M8
@ PseudoVCLMUL_VX_M8
Definition riscv/opcodes.hpp:992
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_M1
@ PseudoVSOXSEG6EI8_V_MF8_M1
Definition riscv/opcodes.hpp:9663
LIEF::assembly::riscv::OPCODE::CV_SDOTUP_H
@ CV_SDOTUP_H
Definition riscv/opcodes.hpp:12400
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_MF8_MASK
@ PseudoVWMACCSU_VV_MF8_MASK
Definition riscv/opcodes.hpp:11466
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E64
@ PseudoVDIV_VX_M8_E64
Definition riscv/opcodes.hpp:1583
LIEF::assembly::riscv::OPCODE::FMAX_S_INX
@ FMAX_S_INX
Definition riscv/opcodes.hpp:12702
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF8_E8
@ PseudoVCOMPRESS_VM_MF8_E8
Definition riscv/opcodes.hpp:1035
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M1_MF2
@ PseudoVSOXSEG6EI64_V_M1_MF2
Definition riscv/opcodes.hpp:9633
LIEF::assembly::riscv::OPCODE::TH_DCACHE_CISW
@ TH_DCACHE_CISW
Definition riscv/opcodes.hpp:13031
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR32_M4_MASK
@ PseudoVFSLIDE1UP_VFPR32_M4_MASK
Definition riscv/opcodes.hpp:3348
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_MF8
@ PseudoVMIN_VX_MF8
Definition riscv/opcodes.hpp:6880
LIEF::assembly::riscv::OPCODE::TH_DCACHE_IVA
@ TH_DCACHE_IVA
Definition riscv/opcodes.hpp:13041
LIEF::assembly::riscv::OPCODE::AMOCAS_Q_RL
@ AMOCAS_Q_RL
Definition riscv/opcodes.hpp:11998
LIEF::assembly::riscv::OPCODE::FMAX_H
@ FMAX_H
Definition riscv/opcodes.hpp:12699
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF2_MASK
@ PseudoVLOXSEG5EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4733
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF4
@ PseudoVSUXSEG7EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:11211
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E16
@ PseudoVREDMAX_VS_M8_E16
Definition riscv/opcodes.hpp:7812
LIEF::assembly::riscv::OPCODE::ECALL
@ ECALL
Definition riscv/opcodes.hpp:12557
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M8
@ PseudoVROR_VX_M8
Definition riscv/opcodes.hpp:8568
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF2_MASK
@ PseudoVMFLE_VV_MF2_MASK
Definition riscv/opcodes.hpp:6739
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M2
@ PseudoVSOXSEG4EI8_V_M1_M2
Definition riscv/opcodes.hpp:9485
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M2_MASK
@ PseudoVSOXEI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:9142
LIEF::assembly::riscv::OPCODE::VMSEQ_VV
@ VMSEQ_VV
Definition riscv/opcodes.hpp:13527
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_MF2
@ PseudoVC_V_FPR16V_MF2
Definition riscv/opcodes.hpp:1194
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M1_MASK
@ PseudoVNCLIPU_WX_M1_MASK
Definition riscv/opcodes.hpp:7451
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E32
@ PseudoVFSQRT_V_M8_E32
Definition riscv/opcodes.hpp:3381
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E64_MASK
@ PseudoVREDMINU_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:7861
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M1_M1_MASK
@ PseudoVSOXSEG3EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9320
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF8
@ PseudoVLSE8_V_MF8
Definition riscv/opcodes.hpp:5052
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_MF8
@ PseudoVXOR_VX_MF8
Definition riscv/opcodes.hpp:11879
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF2
@ PseudoVSOXEI8_V_MF4_MF2
Definition riscv/opcodes.hpp:9143
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32FF_V_MF2_MASK
@ PseudoVLSEG5E32FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5253
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_M1
@ PseudoVSUXSEG8EI32_V_M2_M1
Definition riscv/opcodes.hpp:11281
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M4_M1
@ PseudoVSUXSEG8EI32_V_M4_M1
Definition riscv/opcodes.hpp:11285
LIEF::assembly::riscv::OPCODE::FNMADD_H
@ FNMADD_H
Definition riscv/opcodes.hpp:12739
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E16
@ PseudoVREDOR_VS_M2_E16
Definition riscv/opcodes.hpp:7928
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M1
@ PseudoVMFLE_VFPR64_M1
Definition riscv/opcodes.hpp:6722
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M4_E32_MASK
@ PseudoVFMADD_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:2042
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M1
@ PseudoVLSEG3E32_V_M1
Definition riscv/opcodes.hpp:5148
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_MF8_MASK
@ PseudoVIOTA_M_MF8_MASK
Definition riscv/opcodes.hpp:4082
LIEF::assembly::riscv::OPCODE::VMV2R_V
@ VMV2R_V
Definition riscv/opcodes.hpp:13557
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M2_MASK
@ PseudoVMIN_VX_M2_MASK
Definition riscv/opcodes.hpp:6871
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E64_V_M1
@ PseudoVSSEG7E64_V_M1
Definition riscv/opcodes.hpp:10133
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M4_MASK
@ PseudoVWMULU_VV_M4_MASK
Definition riscv/opcodes.hpp:11568
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M1
@ PseudoVWSLL_VV_M1
Definition riscv/opcodes.hpp:11695
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF2_MASK
@ PseudoVAND_VV_MF2_MASK
Definition riscv/opcodes.hpp:841
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF4_MASK
@ PseudoVLOXSEG7EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4895
LIEF::assembly::riscv::OPCODE::Select_FPR16_Using_CC_GPR
@ Select_FPR16_Using_CC_GPR
Definition riscv/opcodes.hpp:11917
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_MF2
@ PseudoVFWMACC_4x4x4_MF2
Definition riscv/opcodes.hpp:3729
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M1_E16
@ PseudoVFWMACC_VV_M1_E16
Definition riscv/opcodes.hpp:3749
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M2_E64
@ PseudoVFMADD_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2021
LIEF::assembly::riscv::OPCODE::TH_DCACHE_CIALL
@ TH_DCACHE_CIALL
Definition riscv/opcodes.hpp:13029
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E32
@ PseudoVFMADD_VV_M8_E32
Definition riscv/opcodes.hpp:2047
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M4_E64
@ PseudoVFRSUB_VFPR64_M4_E64
Definition riscv/opcodes.hpp:3117
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M4
@ PseudoVRGATHEREI16_VV_M2_E8_M4
Definition riscv/opcodes.hpp:8334
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF2_MASK
@ PseudoVLOXSEG4EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4631
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E8_MASK
@ PseudoVREMU_VX_MF2_E8_MASK
Definition riscv/opcodes.hpp:8165
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_MF2_MASK
@ PseudoVMSNE_VV_MF2_MASK
Definition riscv/opcodes.hpp:7244
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_M1
@ PseudoVLUXSEG5EI8_V_MF4_M1
Definition riscv/opcodes.hpp:6148
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M1_MASK
@ PseudoVSADD_VX_M1_MASK
Definition riscv/opcodes.hpp:8675
LIEF::assembly::riscv::OPCODE::VANDN_VV
@ VANDN_VV
Definition riscv/opcodes.hpp:13152
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M1
@ PseudoVXOR_VV_M1
Definition riscv/opcodes.hpp:11853
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF4_MASK
@ PseudoVMSLTU_VX_MF4_MASK
Definition riscv/opcodes.hpp:7189
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M8_MASK
@ PseudoVMADD_VX_M8_MASK
Definition riscv/opcodes.hpp:6493
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_MF2_MASK
@ PseudoVLUXEI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:5709
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_MF2_MASK
@ PseudoVSUXSEG3EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:10872
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64V_SE_M8
@ PseudoVC_FPR64V_SE_M8
Definition riscv/opcodes.hpp:1118
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_M1_MASK
@ PseudoVLUXSEG8EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6363
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M8
@ PseudoVMFLT_VFPR64_M8
Definition riscv/opcodes.hpp:6770
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M1
@ PseudoVLOXEI64_V_M4_M1
Definition riscv/opcodes.hpp:4274
LIEF::assembly::riscv::OPCODE::FMAXM_H
@ FMAXM_H
Definition riscv/opcodes.hpp:12694
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M2_E64
@ PseudoVFDIV_VFPR64_M2_E64
Definition riscv/opcodes.hpp:1887
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_MF8_MASK
@ PseudoVMAXU_VX_MF8_MASK
Definition riscv/opcodes.hpp:6541
LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_MF4
@ PseudoVADC_VXM_MF4
Definition riscv/opcodes.hpp:596
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_MF2_E32_MASK
@ PseudoVFWSUB_WFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:4008
LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_ENTRY
@ CONVERGENCECTRL_ENTRY
Definition riscv/opcodes.hpp:68
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF8_MASK
@ PseudoVSLIDEUP_VI_MF8_MASK
Definition riscv/opcodes.hpp:8863
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M1_M1
@ PseudoVSOXSEG4EI16_V_M1_M1
Definition riscv/opcodes.hpp:9401
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M1_MASK
@ PseudoVSUXSEG3EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:10868
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF4_MASK
@ PseudoVOR_VX_MF4_MASK
Definition riscv/opcodes.hpp:7665
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_M1
@ PseudoVLOXSEG5EI64_V_M1_M1
Definition riscv/opcodes.hpp:4730
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M1_MASK
@ PseudoVNCLIPU_WV_M1_MASK
Definition riscv/opcodes.hpp:7439
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M4_MASK
@ PseudoVMFGT_VFPR32_M4_MASK
Definition riscv/opcodes.hpp:6687
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF8
@ PseudoVLOXSEG3EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:4524
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_MF4
@ PseudoVC_V_XVV_SE_MF4
Definition riscv/opcodes.hpp:1354
LIEF::assembly::riscv::OPCODE::LH_AQ_RL
@ LH_AQ_RL
Definition riscv/opcodes.hpp:12842
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF2_MASK
@ PseudoVCTZ_V_MF2_MASK
Definition riscv/opcodes.hpp:1073
LIEF::assembly::riscv::OPCODE::VLSSEG6E64_V
@ VLSSEG6E64_V
Definition riscv/opcodes.hpp:13442
LIEF::assembly::riscv::OPCODE::PseudoZEXT_W
@ PseudoZEXT_W
Definition riscv/opcodes.hpp:11912
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E32
@ PseudoVFWCVT_F_XU_V_MF2_E32
Definition riscv/opcodes.hpp:3597
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_MF2_MASK
@ PseudoVSSEG6E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10112
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B16
@ PseudoVMSBF_M_B16
Definition riscv/opcodes.hpp:6939
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M2_MASK
@ PseudoVSSE16_V_M2_MASK
Definition riscv/opcodes.hpp:9950
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M2_MASK
@ PseudoVADD_VI_M2_MASK
Definition riscv/opcodes.hpp:601
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M1_MASK
@ PseudoVSEXT_VF4_M1_MASK
Definition riscv/opcodes.hpp:8762
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E8
@ PseudoVREDMIN_VS_M2_E8
Definition riscv/opcodes.hpp:7890
LIEF::assembly::riscv::OPCODE::VDIVU_VV
@ VDIVU_VV
Definition riscv/opcodes.hpp:13200
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_SE_M1
@ PseudoVC_V_FPR64VV_SE_M1
Definition riscv/opcodes.hpp:1236
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF4_MASK
@ PseudoVSSUB_VX_MF4_MASK
Definition riscv/opcodes.hpp:10472
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_MF2
@ PseudoVLSSEG6E32_V_MF2
Definition riscv/opcodes.hpp:5518
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M1_MASK
@ PseudoVMSLE_VV_M1_MASK
Definition riscv/opcodes.hpp:7136
LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M8
@ PseudoVSSE64_V_M8
Definition riscv/opcodes.hpp:9975
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M2_E16
@ PseudoVFWSUB_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3957
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF4
@ PseudoVLOXSEG4EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:4598
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M1_E32_MASK
@ PseudoVFWADD_WFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3498
LIEF::assembly::riscv::OPCODE::InsnCS
@ InsnCS
Definition riscv/opcodes.hpp:12821
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M8_M8_MASK
@ PseudoVSUXEI8_V_M8_M8_MASK
Definition riscv/opcodes.hpp:10634
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF2_E16
@ PseudoVFWCVT_F_F_V_MF2_E16
Definition riscv/opcodes.hpp:3571
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF2_MASK
@ PseudoVMFNE_VFPR16_MF2_MASK
Definition riscv/opcodes.hpp:6793
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF2
@ PseudoVASUB_VX_MF2
Definition riscv/opcodes.hpp:910
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E32
@ PseudoVRGATHER_VV_M1_E32
Definition riscv/opcodes.hpp:8450
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF4
@ PseudoVWSUBU_WX_MF4
Definition riscv/opcodes.hpp:11775
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF4_MASK
@ PseudoVSUXSEG5EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:11032
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF2
@ PseudoVSUXSEG5EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:11049
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF2
@ PseudoVLUXEI32_V_MF2_MF2
Definition riscv/opcodes.hpp:5644
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M4
@ PseudoVWADD_VV_M4
Definition riscv/opcodes.hpp:11399
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M2_MASK
@ PseudoVOR_VI_M2_MASK
Definition riscv/opcodes.hpp:7629
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_MF8_MASK
@ PseudoVNCLIP_WI_MF8_MASK
Definition riscv/opcodes.hpp:7473
LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M2
@ PseudoVSHA2MS_VV_M2
Definition riscv/opcodes.hpp:8790
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF2
@ PseudoVNCLIPU_WV_MF2
Definition riscv/opcodes.hpp:7444
LIEF::assembly::riscv::OPCODE::VLUXSEG8EI8_V
@ VLUXSEG8EI8_V
Definition riscv/opcodes.hpp:13483
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M1_MASK
@ PseudoVSUXEI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10504
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF2_MASK
@ PseudoVSSEG6E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10118
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF4_MASK
@ PseudoVLOXSEG4EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4599
LIEF::assembly::riscv::OPCODE::VADD_VV
@ VADD_VV
Definition riscv/opcodes.hpp:13139
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_MF8_MASK
@ PseudoVMAXU_VV_MF8_MASK
Definition riscv/opcodes.hpp:6527
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_MF2
@ PseudoVLOXSEG2EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:4452
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF4_E16
@ PseudoVFWNMSAC_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3883
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M4_MASK
@ PseudoVMFLT_VV_M4_MASK
Definition riscv/opcodes.hpp:6777
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF2_MASK
@ PseudoVMULHU_VV_MF2_MASK
Definition riscv/opcodes.hpp:7314
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF2
@ PseudoVRGATHEREI16_VV_M1_E64_MF2
Definition riscv/opcodes.hpp:8294
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF4_E16
@ PseudoVREDXOR_VS_MF4_E16
Definition riscv/opcodes.hpp:8046
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M4_E16_MASK
@ PseudoVFSGNJ_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3246
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M1
@ PseudoVWADD_VV_M1
Definition riscv/opcodes.hpp:11395
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF4_MASK
@ PseudoVLOXSEG3EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:4577
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M1_E16_MASK
@ PseudoVFWCVT_F_F_V_M1_E16_MASK
Definition riscv/opcodes.hpp:3560
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_MF2_MASK
@ PseudoVWADD_VV_MF2_MASK
Definition riscv/opcodes.hpp:11402
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M1_MASK
@ PseudoVLUXSEG2EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:5839
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_M8
@ PseudoVSBC_VXM_M8
Definition riscv/opcodes.hpp:8698
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF4
@ PseudoVMSEQ_VX_MF4
Definition riscv/opcodes.hpp:6990
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_M1_MASK
@ PseudoVSOXSEG2EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9226
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF2_M1
@ PseudoVLOXSEG6EI8_V_MF2_M1
Definition riscv/opcodes.hpp:4832
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M1_MASK
@ PseudoVSOXSEG4EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9484
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF2_MASK
@ PseudoVSOXSEG8EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9802
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF2_E16_MASK
@ PseudoVFSGNJX_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3236
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF2_MASK
@ PseudoVWMULSU_VX_MF2_MASK
Definition riscv/opcodes.hpp:11558
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M8_MASK
@ PseudoVMSNE_VI_M8_MASK
Definition riscv/opcodes.hpp:7228
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_M1
@ PseudoVC_V_FPR16VV_SE_M1
Definition riscv/opcodes.hpp:1172
LIEF::assembly::riscv::OPCODE::CV_SRL_H
@ CV_SRL_H
Definition riscv/opcodes.hpp:12438
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M2
@ PseudoVMSLE_VV_M2
Definition riscv/opcodes.hpp:7137
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M1_E32
@ PseudoVFNMACC_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2627
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF8_MASK
@ PseudoVWMACC_VV_MF8_MASK
Definition riscv/opcodes.hpp:11526
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M4
@ PseudoVZEXT_VF2_M4
Definition riscv/opcodes.hpp:11885
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF2
@ PseudoVLUXSEG5EI64_V_M1_MF2
Definition riscv/opcodes.hpp:6124
LIEF::assembly::riscv::OPCODE::FCVT_H_D_INX
@ FCVT_H_D_INX
Definition riscv/opcodes.hpp:12592
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8_MASK
@ PseudoVWADDU_WV_MF8_MASK
Definition riscv/opcodes.hpp:11380
LIEF::assembly::riscv::OPCODE::Insn16
@ Insn16
Definition riscv/opcodes.hpp:12811
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_MF2
@ PseudoVSUXEI64_V_M2_MF2
Definition riscv/opcodes.hpp:10595
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF2_MASK
@ PseudoVSLIDE1DOWN_VX_MF2_MASK
Definition riscv/opcodes.hpp:8803
LIEF::assembly::riscv::OPCODE::FADD_D
@ FADD_D
Definition riscv/opcodes.hpp:12558
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF2
@ PseudoVMULHU_VX_MF2
Definition riscv/opcodes.hpp:7327
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M4
@ PseudoVSADD_VI_M4
Definition riscv/opcodes.hpp:8650
LIEF::assembly::riscv::OPCODE::VSOXSEG4EI8_V
@ VSOXSEG4EI8_V
Definition riscv/opcodes.hpp:13675
LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_MF2
@ PseudoVLE32FF_V_MF2
Definition riscv/opcodes.hpp:4115
LIEF::assembly::riscv::OPCODE::VMAXU_VV
@ VMAXU_VV
Definition riscv/opcodes.hpp:13496
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_M1
@ PseudoVSOXSEG4EI8_V_MF8_M1
Definition riscv/opcodes.hpp:9503
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M1
@ PseudoVSRL_VI_M1
Definition riscv/opcodes.hpp:9905
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_MF4_E16
@ PseudoVFMUL_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2322
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M4
@ PseudoVSSEG2E32_V_M4
Definition riscv/opcodes.hpp:10005
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_M2
@ PseudoVC_V_VVV_SE_M2
Definition riscv/opcodes.hpp:1310
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_M4_E32
@ PseudoVFWCVT_F_F_V_M4_E32
Definition riscv/opcodes.hpp:3569
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M1_E64
@ PseudoVFMACC_VFPR64_M1_E64
Definition riscv/opcodes.hpp:1959
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M1
@ PseudoVLUXSEG2EI16_V_M2_M1
Definition riscv/opcodes.hpp:5734
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E8
@ PseudoVRGATHER_VV_MF4_E8
Definition riscv/opcodes.hpp:8488
LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SCI_B
@ CV_SDOTUSP_SCI_B
Definition riscv/opcodes.hpp:12407
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M1_MASK
@ PseudoVREV8_V_M1_MASK
Definition riscv/opcodes.hpp:8261
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_M8
@ PseudoVC_V_FPR16VW_M8
Definition riscv/opcodes.hpp:1181
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M8
@ PseudoVMSGT_VI_M8
Definition riscv/opcodes.hpp:7043
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E16
@ PseudoVREDMAXU_VS_M1_E16
Definition riscv/opcodes.hpp:7744
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF4_E16
@ PseudoVFRSUB_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3101
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF8
@ PseudoVSUXEI8_V_MF8_MF8
Definition riscv/opcodes.hpp:10657
LIEF::assembly::riscv::OPCODE::G_LLROUND
@ G_LLROUND
Definition riscv/opcodes.hpp:244
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF2_MASK
@ PseudoVSUXSEG3EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10854
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M4_E64
@ PseudoVFMSUB_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2278
LIEF::assembly::riscv::OPCODE::VFMACC_VV
@ VFMACC_VV
Definition riscv/opcodes.hpp:13217
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E32_MASK
@ PseudoVFWSUB_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3980
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M8_MASK
@ PseudoVLOXEI16_V_M2_M8_MASK
Definition riscv/opcodes.hpp:4193
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF2_E16_MASK
@ PseudoVWREDSUM_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:11672
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF2_MASK
@ PseudoVAADD_VV_MF2_MASK
Definition riscv/opcodes.hpp:558
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_MF2_E32
@ PseudoVFSGNJX_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3201
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32_TIED
@ PseudoVFWADD_WV_MF2_E32_TIED
Definition riscv/opcodes.hpp:3536
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M1
@ PseudoVSOXSEG4EI64_V_M4_M1
Definition riscv/opcodes.hpp:9473
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF4
@ PseudoVLOXSEG6EI64_V_M1_MF4
Definition riscv/opcodes.hpp:4814
LIEF::assembly::riscv::OPCODE::VFWREDUSUM_VS
@ VFWREDUSUM_VS
Definition riscv/opcodes.hpp:13298
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_M1_MASK
@ PseudoVSSEG4E16_V_M1_MASK
Definition riscv/opcodes.hpp:10056
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF8_MASK
@ PseudoVWSUB_VV_MF8_MASK
Definition riscv/opcodes.hpp:11790
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M2
@ PseudoVMSEQ_VV_M2
Definition riscv/opcodes.hpp:6968
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M2_E16
@ PseudoVFWMSAC_VV_M2_E16
Definition riscv/opcodes.hpp:3789
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E16
@ PseudoVFDIV_VV_M8_E16
Definition riscv/opcodes.hpp:1911
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M2
@ PseudoVSSRA_VV_M2
Definition riscv/opcodes.hpp:10179
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M8
@ PseudoVMSEQ_VI_M8
Definition riscv/opcodes.hpp:6958
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M8
@ PseudoVMSLE_VI_M8
Definition riscv/opcodes.hpp:7127
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M2_MASK
@ PseudoVNCLIPU_WV_M2_MASK
Definition riscv/opcodes.hpp:7441
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M4_M2
@ PseudoVAESEM_VS_M4_M2
Definition riscv/opcodes.hpp:737
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E32
@ PseudoVFSGNJX_VV_M8_E32
Definition riscv/opcodes.hpp:3231
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF2_MASK
@ PseudoVSSEG8E16_V_MF2_MASK
Definition riscv/opcodes.hpp:10146
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E32
@ PseudoVFCVT_F_X_V_M2_E32
Definition riscv/opcodes.hpp:1709
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_M2
@ PseudoVAESEF_VS_M4_M2
Definition riscv/opcodes.hpp:708
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M4_MASK
@ PseudoVFSLIDE1DOWN_VFPR32_M4_MASK
Definition riscv/opcodes.hpp:3318
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E64_MASK
@ PseudoVFDIV_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:1916
LIEF::assembly::riscv::OPCODE::G_XOR
@ G_XOR
Definition riscv/opcodes.hpp:86
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_MF4
@ PseudoVLOXSEG4EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:4632
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M8
@ PseudoVFCVT_RM_X_F_V_M8
Definition riscv/opcodes.hpp:1809
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E32
@ PseudoVFWNMSAC_VV_M2_E32
Definition riscv/opcodes.hpp:3899
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M2
@ PseudoVLUXSEG2EI32_V_M4_M2
Definition riscv/opcodes.hpp:5780
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M4_E16_MASK
@ PseudoVFREDMAX_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:2948
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF2_MASK
@ PseudoVSOXEI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9144
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M4_M1
@ PseudoVSUXSEG5EI32_V_M4_M1
Definition riscv/opcodes.hpp:11045
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF2_E8_MASK
@ PseudoVFWCVT_F_X_V_MF2_E8_MASK
Definition riscv/opcodes.hpp:3630
LIEF::assembly::riscv::OPCODE::AES32ESMI
@ AES32ESMI
Definition riscv/opcodes.hpp:11939
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_M1
@ PseudoVSOXSEG7EI8_V_MF8_M1
Definition riscv/opcodes.hpp:9743
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M2
@ PseudoVIOTA_M_M2
Definition riscv/opcodes.hpp:4071
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_MF4
@ PseudoVAESDF_VS_M8_MF4
Definition riscv/opcodes.hpp:659
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M1
@ PseudoVLSEG2E16FF_V_M1
Definition riscv/opcodes.hpp:5054
LIEF::assembly::riscv::OPCODE::VFDIV_VF
@ VFDIV_VF
Definition riscv/opcodes.hpp:13213
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E16_MASK
@ PseudoVFREDMIN_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:2990
LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M1
@ PseudoVSHA2MS_VV_M1
Definition riscv/opcodes.hpp:8789
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF4
@ PseudoVMULHSU_VX_MF4
Definition riscv/opcodes.hpp:7301
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M4_MASK
@ PseudoVSUXSEG2EI8_V_M1_M4_MASK
Definition riscv/opcodes.hpp:10764
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_MF2_E32
@ PseudoVFMSUB_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2272
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF8_MASK
@ PseudoVMINU_VX_MF8_MASK
Definition riscv/opcodes.hpp:6853
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF2_MASK
@ PseudoVLSSEG5E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5493
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF2
@ PseudoVLUXSEG5EI64_V_M2_MF2
Definition riscv/opcodes.hpp:6132
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M1_MASK
@ PseudoVSSEG4E8_V_M1_MASK
Definition riscv/opcodes.hpp:10074
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M8
@ PseudoVSE8_V_M8
Definition riscv/opcodes.hpp:8738
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_M1
@ PseudoVAESEM_VS_M8_M1
Definition riscv/opcodes.hpp:742
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E16
@ PseudoVFSGNJN_VV_M1_E16
Definition riscv/opcodes.hpp:3151
LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M8
@ PseudoVSHA2CH_VV_M8
Definition riscv/opcodes.hpp:8782
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M1_MASK
@ PseudoVSOXEI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:9104
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E16_TIED
@ PseudoVFWADD_WV_MF2_E16_TIED
Definition riscv/opcodes.hpp:3532
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF2_MASK
@ PseudoVWMULSU_VV_MF2_MASK
Definition riscv/opcodes.hpp:11546
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B8
@ PseudoVMSOF_M_B8
Definition riscv/opcodes.hpp:7275
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E64_MASK
@ PseudoVFNMACC_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:2668
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M2_MF4
@ PseudoVAESDF_VS_M2_MF4
Definition riscv/opcodes.hpp:647
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E8
@ PseudoVWREDSUM_VS_M1_E8
Definition riscv/opcodes.hpp:11651
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_MF4
@ PseudoVLOXSEG6EI32_V_M1_MF4
Definition riscv/opcodes.hpp:4794
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M4
@ PseudoTHVdotVMAQA_VV_M4
Definition riscv/opcodes.hpp:504
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF4
@ PseudoVMACC_VV_MF4
Definition riscv/opcodes.hpp:6412
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E16_MASK
@ PseudoVWREDSUM_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:11654
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M8
@ PseudoVLUXEI8_V_M1_M8
Definition riscv/opcodes.hpp:5688
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M8
@ PseudoVSADD_VI_M8
Definition riscv/opcodes.hpp:8652
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M2_MASK
@ PseudoVLSEG2E64_V_M2_MASK
Definition riscv/opcodes.hpp:5099
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF4_MASK
@ PseudoVSSUB_VV_MF4_MASK
Definition riscv/opcodes.hpp:10458
LIEF::assembly::riscv::OPCODE::VSSSEG4E8_V
@ VSSSEG4E8_V
Definition riscv/opcodes.hpp:13747
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_M1_MASK
@ PseudoVLOXSEG8EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4957
LIEF::assembly::riscv::OPCODE::TH_SRB
@ TH_SRB
Definition riscv/opcodes.hpp:13110
LIEF::assembly::riscv::OPCODE::PseudoVAESKF1_VI_M4
@ PseudoVAESKF1_VI_M4
Definition riscv/opcodes.hpp:758
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR32_S_MF2
@ PseudoVFMV_FPR32_S_MF2
Definition riscv/opcodes.hpp:2382
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_M1_MASK
@ PseudoVLSSEG8E8_V_M1_MASK
Definition riscv/opcodes.hpp:5563
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M8
@ PseudoVAADD_VX_M8
Definition riscv/opcodes.hpp:569
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF4
@ PseudoVLUXSEG5EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:6098
LIEF::assembly::riscv::OPCODE::C_SRAI
@ C_SRAI
Definition riscv/opcodes.hpp:12536
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_M1
@ PseudoVLUXSEG2EI32_V_MF2_M1
Definition riscv/opcodes.hpp:5788
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR64_M8
@ PseudoVMFGE_VFPR64_M8
Definition riscv/opcodes.hpp:6668
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_M4
@ PseudoVC_V_VV_M4
Definition riscv/opcodes.hpp:1330
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M2_MASK
@ PseudoVLUXSEG4EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:6053
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF2
@ PseudoVSOXSEG5EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:9545
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M8_E64_MASK
@ PseudoVDIV_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:1540
LIEF::assembly::riscv::OPCODE::VSUXSEG6EI32_V
@ VSUXSEG6EI32_V
Definition riscv/opcodes.hpp:13791
LIEF::assembly::riscv::OPCODE::G_FCANONICALIZE
@ G_FCANONICALIZE
Definition riscv/opcodes.hpp:223
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M4
@ PseudoVRGATHEREI16_VV_M2_E64_M4
Definition riscv/opcodes.hpp:8326
LIEF::assembly::riscv::OPCODE::TH_MULSW
@ TH_MULSW
Definition riscv/opcodes.hpp:13097
LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_MF2
@ PseudoVC_X_SE_MF2
Definition riscv/opcodes.hpp:1420
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_MF2_MASK
@ PseudoVWSUBU_VV_MF2_MASK
Definition riscv/opcodes.hpp:11726
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF2_MASK
@ PseudoVSLIDEDOWN_VX_MF2_MASK
Definition riscv/opcodes.hpp:8845
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M1_MASK
@ PseudoVLOXEI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4275
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF4
@ PseudoVSSUB_VX_MF4
Definition riscv/opcodes.hpp:10471
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E32
@ PseudoVFNMACC_VV_M8_E32
Definition riscv/opcodes.hpp:2665
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E64
@ PseudoVFREDUSUM_VS_M4_E64
Definition riscv/opcodes.hpp:3041
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF8_MASK
@ PseudoVSUB_VX_MF8_MASK
Definition riscv/opcodes.hpp:10502
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M2_MASK
@ PseudoVSOXSEG2EI32_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9194
LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_MF4
@ PseudoVC_VV_SE_MF4
Definition riscv/opcodes.hpp:1164
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M4_MASK
@ PseudoVRSUB_VI_M4_MASK
Definition riscv/opcodes.hpp:8581
LIEF::assembly::riscv::OPCODE::VL1RE8_V
@ VL1RE8_V
Definition riscv/opcodes.hpp:13310
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_M1
@ PseudoVSUXEI32_V_MF2_M1
Definition riscv/opcodes.hpp:10575
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M1_MASK
@ PseudoVLUXEI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:5675
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_M1
@ PseudoVC_V_XVV_M1
Definition riscv/opcodes.hpp:1342
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M8_E32
@ PseudoVFMAX_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2075
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_MF8
@ PseudoVC_V_I_MF8
Definition riscv/opcodes.hpp:1294
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16_TIED
@ PseudoVFWADD_WV_M1_E16_TIED
Definition riscv/opcodes.hpp:3508
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2_TIED
@ PseudoVWSUB_WV_M2_TIED
Definition riscv/opcodes.hpp:11810
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF2_MASK
@ PseudoVSADD_VV_MF2_MASK
Definition riscv/opcodes.hpp:8669
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E32
@ PseudoVREDOR_VS_M1_E32
Definition riscv/opcodes.hpp:7922
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E64
@ PseudoVREMU_VV_M8_E64
Definition riscv/opcodes.hpp:8112
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M8_M2
@ PseudoVSOXSEG3EI32_V_M8_M2
Definition riscv/opcodes.hpp:9337
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E64
@ PseudoVREDMIN_VS_M1_E64
Definition riscv/opcodes.hpp:7880
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M2
@ PseudoVRGATHEREI16_VV_M8_E64_M2
Definition riscv/opcodes.hpp:8382
LIEF::assembly::riscv::OPCODE::SRLIW
@ SRLIW
Definition riscv/opcodes.hpp:13002
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_MF2_MASK
@ PseudoVLOXSEG8EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4933
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M4_MASK
@ PseudoVWADDU_WX_M4_MASK
Definition riscv/opcodes.hpp:11388
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_M2
@ PseudoVFWMACC_4x4x4_M2
Definition riscv/opcodes.hpp:3726
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M1_MF2
@ PseudoVLOXSEG5EI32_V_M1_MF2
Definition riscv/opcodes.hpp:4712
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF4_MASK
@ PseudoVXOR_VV_MF4_MASK
Definition riscv/opcodes.hpp:11864
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_MF4_MASK
@ PseudoVLSSEG6E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5515
LIEF::assembly::riscv::OPCODE::VQMACCU_2x8x2
@ VQMACCU_2x8x2
Definition riscv/opcodes.hpp:13590
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_M1
@ PseudoVLOXSEG5EI8_V_MF2_M1
Definition riscv/opcodes.hpp:4752
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E64
@ PseudoVFREDMIN_VS_M8_E64
Definition riscv/opcodes.hpp:2987
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M4
@ PseudoVSUXSEG2EI16_V_M1_M4
Definition riscv/opcodes.hpp:10663
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E16_MASK
@ PseudoVRGATHER_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:8449
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_M1_MASK
@ PseudoVLOXSEG2EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4371
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_M1_MASK
@ PseudoVSSEG8E8_V_M1_MASK
Definition riscv/opcodes.hpp:10156
LIEF::assembly::riscv::OPCODE::VLUXSEG4EI32_V
@ VLUXSEG4EI32_V
Definition riscv/opcodes.hpp:13465
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF8
@ PseudoVSOXEI8_V_MF8_MF8
Definition riscv/opcodes.hpp:9153
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E32_MASK
@ PseudoVREMU_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:8119
LIEF::assembly::riscv::OPCODE::CV_AVGU_H
@ CV_AVGU_H
Definition riscv/opcodes.hpp:12188
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_M1_MASK
@ PseudoVSUXSEG3EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:10898
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E16_MASK
@ PseudoVDIV_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:1512
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M1
@ PseudoVLUXSEG4EI32_V_M1_M1
Definition riscv/opcodes.hpp:6000
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E16
@ PseudoVFMAX_VV_M8_E16
Definition riscv/opcodes.hpp:2105
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E64_MASK
@ PseudoVREM_VX_M4_E64_MASK
Definition riscv/opcodes.hpp:8237
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M2
@ PseudoVAND_VX_M2
Definition riscv/opcodes.hpp:848
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK
@ PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK
Definition riscv/opcodes.hpp:8305
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_MF8
@ PseudoVSSRA_VV_MF8
Definition riscv/opcodes.hpp:10189
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_MF4
@ PseudoVZEXT_VF2_MF4
Definition riscv/opcodes.hpp:11891
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR64_S_M8
@ PseudoVFMV_FPR64_S_M8
Definition riscv/opcodes.hpp:2386
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M2_MASK
@ PseudoVSLL_VX_M2_MASK
Definition riscv/opcodes.hpp:8909
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E64_MASK
@ PseudoVREDAND_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:7721
LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_M8
@ PseudoVC_X_SE_M8
Definition riscv/opcodes.hpp:1419
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M1_E32
@ PseudoVFWMACC_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3741
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_MF2
@ PseudoVSOXEI32_V_M2_MF2
Definition riscv/opcodes.hpp:9055
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E32_MASK
@ PseudoVREDMINU_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:7867
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M4
@ PseudoVLSSEG2E16_V_M4
Definition riscv/opcodes.hpp:5402
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_M1_MASK
@ PseudoVSOXSEG3EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9340
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M2_E16_MASK
@ PseudoVFSGNJX_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3184
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M4_E16_MASK
@ PseudoVFWSUB_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3960
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M4_E16_MASK
@ PseudoVFNMADD_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2680
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M2_MASK
@ PseudoVLOXSEG3EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4555
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_MF2
@ PseudoVFCVT_RM_X_F_V_MF2
Definition riscv/opcodes.hpp:1811
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M2
@ PseudoVMSNE_VI_M2
Definition riscv/opcodes.hpp:7223
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M4_M1
@ PseudoVLOXSEG8EI32_V_M4_M1
Definition riscv/opcodes.hpp:4960
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF4_MASK
@ PseudoVNSRL_WI_MF4_MASK
Definition riscv/opcodes.hpp:7599
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M4_E64
@ PseudoVFNMSUB_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2821
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M1_MASK
@ PseudoVMFEQ_VFPR64_M1_MASK
Definition riscv/opcodes.hpp:6621
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M1_M1
@ PseudoVAESDM_VS_M1_M1
Definition riscv/opcodes.hpp:669
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E16
@ PseudoVFREDMIN_VS_MF2_E16
Definition riscv/opcodes.hpp:2989
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_M1_MASK
@ PseudoVSOXSEG5EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9578
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E16
@ PseudoVFSQRT_V_M4_E16
Definition riscv/opcodes.hpp:3373
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF8_MASK
@ PseudoVLUXSEG4EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:5999
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M2
@ PseudoVRGATHEREI16_VV_M4_E16_M2
Definition riscv/opcodes.hpp:8340
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E32_MASK
@ PseudoVREDAND_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:7719
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_MF2_E32_MASK
@ PseudoVFSGNJ_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3262
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M2_MF2_MASK
@ PseudoVLUXSEG7EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:6271
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M1_MASK
@ PseudoVWSLL_VV_M1_MASK
Definition riscv/opcodes.hpp:11696
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M4_M1_MASK
@ PseudoVSUXSEG7EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:11230
LIEF::assembly::riscv::OPCODE::REMU
@ REMU
Definition riscv/opcodes.hpp:12925
LIEF::assembly::riscv::OPCODE::AMOXOR_H
@ AMOXOR_H
Definition riscv/opcodes.hpp:12107
LIEF::assembly::riscv::OPCODE::FNMSUB_S
@ FNMSUB_S
Definition riscv/opcodes.hpp:12748
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M2
@ PseudoVSSE16_V_M2
Definition riscv/opcodes.hpp:9949
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M8_E16_MASK
@ PseudoVFDIV_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:1870
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M2_MASK
@ PseudoVSOXEI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:9134
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M2_MASK
@ PseudoVNMSUB_VV_M2_MASK
Definition riscv/opcodes.hpp:7529
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_M2
@ PseudoVFNRCLIP_X_F_QF_M2
Definition riscv/opcodes.hpp:2867
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_MF2_M1
@ PseudoVSUXSEG4EI32_V_MF2_M1
Definition riscv/opcodes.hpp:10953
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M1_E16
@ PseudoVFMACC_VFPR16_M1_E16
Definition riscv/opcodes.hpp:1937
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_MF2
@ PseudoVSSEG7E32_V_MF2
Definition riscv/opcodes.hpp:10131
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_MF4_MASK
@ PseudoVLSSEG2E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5407
LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SC_B
@ CV_CMPEQ_SC_B
Definition riscv/opcodes.hpp:12215
LIEF::assembly::riscv::OPCODE::AMOSWAP_D_AQ_RL
@ AMOSWAP_D_AQ_RL
Definition riscv/opcodes.hpp:12089
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M4_MF2
@ PseudoVSOXSEG5EI64_V_M4_MF2
Definition riscv/opcodes.hpp:9567
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_MF2_E16
@ PseudoVCOMPRESS_VM_MF2_E16
Definition riscv/opcodes.hpp:1030
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF2_MASK
@ PseudoVSOXSEG7EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9722
LIEF::assembly::riscv::OPCODE::G_ASSERT_SEXT
@ G_ASSERT_SEXT
Definition riscv/opcodes.hpp:72
LIEF::assembly::riscv::OPCODE::VSOXSEG8EI16_V
@ VSOXSEG8EI16_V
Definition riscv/opcodes.hpp:13688
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M2_MASK
@ PseudoVLSSEG4E32_V_M2_MASK
Definition riscv/opcodes.hpp:5473
LIEF::assembly::riscv::OPCODE::TH_SRH
@ TH_SRH
Definition riscv/opcodes.hpp:13112
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E32
@ PseudoVCOMPRESS_VM_M8_E32
Definition riscv/opcodes.hpp:1027
LIEF::assembly::riscv::OPCODE::CV_CMPNE_B
@ CV_CMPNE_B
Definition riscv/opcodes.hpp:12265
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E16
@ PseudoVREM_VV_M2_E16
Definition riscv/opcodes.hpp:8180
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E64_MASK
@ PseudoVFDIV_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:1898
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E64
@ PseudoVFCVT_RM_F_XU_V_M1_E64
Definition riscv/opcodes.hpp:1735
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M2_MASK
@ PseudoVSUXEI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10624
LIEF::assembly::riscv::OPCODE::VLOXSEG8EI64_V
@ VLOXSEG8EI64_V
Definition riscv/opcodes.hpp:13362
LIEF::assembly::riscv::OPCODE::Select_FPR32_Using_CC_GPR
@ Select_FPR32_Using_CC_GPR
Definition riscv/opcodes.hpp:11919
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_M2
@ PseudoVAESEF_VS_M8_M2
Definition riscv/opcodes.hpp:714
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M4_E16
@ PseudoVDIVU_VX_M4_E16
Definition riscv/opcodes.hpp:1483
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E16
@ PseudoVFREDMIN_VS_M2_E16
Definition riscv/opcodes.hpp:2971
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4_MASK
@ PseudoVWADDU_WV_MF4_MASK
Definition riscv/opcodes.hpp:11376
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M8_MASK
@ PseudoVAND_VX_M8_MASK
Definition riscv/opcodes.hpp:853
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_M1_M1_MASK
@ PseudoVLUXSEG3EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5945
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF2
@ PseudoVLUXSEG7EI32_V_M1_MF2
Definition riscv/opcodes.hpp:6264
LIEF::assembly::riscv::OPCODE::FNMSUB_D
@ FNMSUB_D
Definition riscv/opcodes.hpp:12743
LIEF::assembly::riscv::OPCODE::VMFLE_VF
@ VMFLE_VF
Definition riscv/opcodes.hpp:13507
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M8_MASK
@ PseudoVRGATHER_VX_M8_MASK
Definition riscv/opcodes.hpp:8499
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E16_MASK
@ PseudoVREDAND_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:7725
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M1
@ PseudoVWMACCU_VV_M1
Definition riscv/opcodes.hpp:11491
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF4_MASK
@ PseudoVSSSEG7E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10396
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF2
@ PseudoVWMACC_VV_MF2
Definition riscv/opcodes.hpp:11521
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E16_MASK
@ PseudoVFWNMSAC_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3902
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E16_V_M1_MASK
@ PseudoVSSSEG4E16_V_M1_MASK
Definition riscv/opcodes.hpp:10312
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF2
@ PseudoVLOXSEG3EI64_V_M2_MF2
Definition riscv/opcodes.hpp:4538
LIEF::assembly::riscv::OPCODE::VSUXSEG8EI8_V
@ VSUXSEG8EI8_V
Definition riscv/opcodes.hpp:13801
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF8_MASK
@ PseudoVCLMULH_VV_MF8_MASK
Definition riscv/opcodes.hpp:957
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M2_MASK
@ PseudoVMSGT_VX_M2_MASK
Definition riscv/opcodes.hpp:7054
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16_TIED
@ PseudoVFWSUB_WV_M1_E16_TIED
Definition riscv/opcodes.hpp:4012
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M4_E32_MASK
@ PseudoVFMAX_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2074
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M2
@ PseudoVROL_VX_M2
Definition riscv/opcodes.hpp:8522
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M4_M1_MASK
@ PseudoVSUXSEG8EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:11286
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M4
@ PseudoVSUXEI16_V_M1_M4
Definition riscv/opcodes.hpp:10507
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF4_MASK
@ PseudoVLUXSEG3EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:5915
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_SE_M2
@ PseudoVC_V_FPR64VV_SE_M2
Definition riscv/opcodes.hpp:1237
LIEF::assembly::riscv::OPCODE::LR_D_AQ
@ LR_D_AQ
Definition riscv/opcodes.hpp:12844
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M1
@ PseudoVLUXEI16_V_M2_M1
Definition riscv/opcodes.hpp:5578
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF8_E8_MASK
@ PseudoVFWCVT_F_XU_V_MF8_E8_MASK
Definition riscv/opcodes.hpp:3606
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_MF2_MASK
@ PseudoVMFGE_VFPR32_MF2_MASK
Definition riscv/opcodes.hpp:6661
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M1
@ PseudoVWSUB_WX_M1
Definition riscv/opcodes.hpp:11827
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M4_MASK
@ PseudoVWMUL_VX_M4_MASK
Definition riscv/opcodes.hpp:11604
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M1
@ PseudoVWSUB_VV_M1
Definition riscv/opcodes.hpp:11779
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E16_MASK
@ PseudoVFDIV_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:1912
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_M1
@ PseudoVLUXSEG6EI8_V_MF4_M1
Definition riscv/opcodes.hpp:6228
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_MF2_MASK
@ PseudoVLOXSEG3EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:4547
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M1_MF8_MASK
@ PseudoVLUXSEG8EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:6369
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_MF4
@ PseudoVLUXSEG8EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:6392
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E64
@ PseudoVFNMACC_VV_M1_E64
Definition riscv/opcodes.hpp:2649
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF8
@ PseudoVCLMUL_VV_MF8
Definition riscv/opcodes.hpp:984
LIEF::assembly::riscv::OPCODE::Select_GPR_Using_CC_Imm
@ Select_GPR_Using_CC_Imm
Definition riscv/opcodes.hpp:11924
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M1
@ PseudoVWADDU_VV_M1
Definition riscv/opcodes.hpp:11335
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E16_MASK
@ PseudoVREDMAX_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:7797
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M2_E32_MASK
@ PseudoVFCVT_RM_F_XU_V_M2_E32_MASK
Definition riscv/opcodes.hpp:1740
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E32_MASK
@ PseudoVFWMACC_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3756
LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M2_MASK
@ PseudoVLSE32_V_M2_MASK
Definition riscv/opcodes.hpp:5025
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF4
@ PseudoVLUXSEG7EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:6252
LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SC_B
@ CV_DOTUSP_SC_B
Definition riscv/opcodes.hpp:12297
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF2
@ PseudoVSLL_VI_MF2
Definition riscv/opcodes.hpp:8886
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M4
@ PseudoVLSEG2E64_V_M4
Definition riscv/opcodes.hpp:5100
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M2_M2_MASK
@ PseudoVLOXSEG4EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4589
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_MF2_MASK
@ PseudoVSUXSEG3EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:10836
LIEF::assembly::riscv::OPCODE::CV_ADDURN
@ CV_ADDURN
Definition riscv/opcodes.hpp:12170
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_MUL
@ G_VECREDUCE_MUL
Definition riscv/opcodes.hpp:309
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M1
@ PseudoVLUXSEG4EI8_V_MF4_M1
Definition riscv/opcodes.hpp:6066
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M1_E16_MASK_TIED
@ PseudoVFWSUB_WV_M1_E16_MASK_TIED
Definition riscv/opcodes.hpp:4011
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M2
@ PseudoVLUXSEG2EI16_V_M2_M2
Definition riscv/opcodes.hpp:5736
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M2_MF4
@ PseudoVSOXSEG6EI64_V_M2_MF4
Definition riscv/opcodes.hpp:9643
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF2
@ PseudoVLOXSEG4EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:4684
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E32
@ PseudoVREDMAXU_VS_M8_E32
Definition riscv/opcodes.hpp:7770
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M2
@ PseudoVSOXSEG2EI8_V_M1_M2
Definition riscv/opcodes.hpp:9257
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_MF2
@ PseudoVSUXSEG8EI64_V_M4_MF2
Definition riscv/opcodes.hpp:11311
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M4
@ PseudoVCLMULH_VV_M4
Definition riscv/opcodes.hpp:948
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M2
@ PseudoVLSEG2E8FF_V_M2
Definition riscv/opcodes.hpp:5104
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M1
@ PseudoVRGATHEREI16_VV_M4_E16_M1
Definition riscv/opcodes.hpp:8338
LIEF::assembly::riscv::OPCODE::VC_FVW
@ VC_FVW
Definition riscv/opcodes.hpp:13174
LIEF::assembly::riscv::OPCODE::VMSGT_VI
@ VMSGT_VI
Definition riscv/opcodes.hpp:13531
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF2_MASK
@ PseudoVWSLL_VV_MF2_MASK
Definition riscv/opcodes.hpp:11702
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF4
@ PseudoVXOR_VI_MF4
Definition riscv/opcodes.hpp:11849
LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_MF2
@ PseudoVGMUL_VV_MF2
Definition riscv/opcodes.hpp:4054
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M8
@ PseudoVAADD_VV_M8
Definition riscv/opcodes.hpp:555
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_MF2
@ PseudoVC_V_XV_SE_MF2
Definition riscv/opcodes.hpp:1379
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_MF2_MASK
@ PseudoVSOXSEG7EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9700
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M8
@ PseudoVLE16_V_M8
Definition riscv/opcodes.hpp:4101
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_MF2
@ PseudoVSUXSEG6EI32_V_M2_MF2
Definition riscv/opcodes.hpp:11123
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M2_MASK
@ PseudoVCTZ_V_M2_MASK
Definition riscv/opcodes.hpp:1067
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_F_V_MF4_E16_MASK
@ PseudoVFWCVT_F_F_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:3576
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF8_E8_MASK
@ PseudoVDIVU_VX_MF8_E8_MASK
Definition riscv/opcodes.hpp:1510
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M4
@ PseudoVNCLIP_WV_M4
Definition riscv/opcodes.hpp:7478
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M2
@ PseudoVLSEG3E64FF_V_M2
Definition riscv/opcodes.hpp:5156
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M8_E64
@ PseudoVFMACC_VFPR64_M8_E64
Definition riscv/opcodes.hpp:1965
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8_MASK
@ PseudoVWSUB_WV_MF8_MASK
Definition riscv/opcodes.hpp:11824
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_MF2_E32
@ PseudoVFMIN_VV_MF2_E32
Definition riscv/opcodes.hpp:2188
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_MF2
@ PseudoVLOXSEG3EI16_V_M1_MF2
Definition riscv/opcodes.hpp:4474
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M8
@ PseudoVSSUB_VX_M8
Definition riscv/opcodes.hpp:10467
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E64_MASK
@ PseudoVFREDOSUM_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:3012
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF8
@ PseudoVSUB_VV_MF8
Definition riscv/opcodes.hpp:10487
LIEF::assembly::riscv::OPCODE::AMOMAX_D_AQ_RL
@ AMOMAX_D_AQ_RL
Definition riscv/opcodes.hpp:12025
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF4
@ PseudoVLSEG8E16_V_MF4
Definition riscv/opcodes.hpp:5368
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF2
@ PseudoVMSLTU_VX_MF2
Definition riscv/opcodes.hpp:7186
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M8
@ PseudoVMULHU_VX_M8
Definition riscv/opcodes.hpp:7325
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF2
@ PseudoVLSSEG4E16_V_MF2
Definition riscv/opcodes.hpp:5466
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_M1_MASK
@ PseudoVLSEG4E16_V_M1_MASK
Definition riscv/opcodes.hpp:5191
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF2
@ PseudoVLOXSEG3EI64_V_M1_MF2
Definition riscv/opcodes.hpp:4528
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_M1_MASK
@ PseudoVSUXEI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10584
LIEF::assembly::riscv::OPCODE::CV_AND_SC_B
@ CV_AND_SC_B
Definition riscv/opcodes.hpp:12185
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E16
@ PseudoVFWSUB_WV_M4_E16
Definition riscv/opcodes.hpp:4025
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF2
@ PseudoVSSRL_VI_MF2
Definition riscv/opcodes.hpp:10213
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF4_MASK
@ PseudoVLOXSEG2EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4361
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M8
@ PseudoVFCVT_RTZ_XU_F_V_M8
Definition riscv/opcodes.hpp:1821
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF2_MASK
@ PseudoVSUXSEG6EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:11164
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF8
@ PseudoVMSGTU_VX_MF8
Definition riscv/opcodes.hpp:7035
LIEF::assembly::riscv::OPCODE::VLOXSEG7EI64_V
@ VLOXSEG7EI64_V
Definition riscv/opcodes.hpp:13358
LIEF::assembly::riscv::OPCODE::CV_XOR_SC_B
@ CV_XOR_SC_B
Definition riscv/opcodes.hpp:12471
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4_MASK_TIED
@ PseudoVWADDU_WV_M4_MASK_TIED
Definition riscv/opcodes.hpp:11369
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF8_MASK
@ PseudoVLSEG6E8FF_V_MF8_MASK
Definition riscv/opcodes.hpp:5309
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_MF8
@ PseudoVC_V_XVW_MF8
Definition riscv/opcodes.hpp:1361
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M1
@ PseudoTHVdotVMAQAU_VV_M1
Definition riscv/opcodes.hpp:480
LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M1_MASK
@ PseudoVLE32_V_M1_MASK
Definition riscv/opcodes.hpp:4118
LIEF::assembly::riscv::OPCODE::CV_SLL_SCI_H
@ CV_SLL_SCI_H
Definition riscv/opcodes.hpp:12428
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_M1_MASK
@ PseudoVLSEG8E8_V_M1_MASK
Definition riscv/opcodes.hpp:5391
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF4
@ PseudoVSSSEG3E8_V_MF4
Definition riscv/opcodes.hpp:10307
LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M4
@ PseudoVSE32_V_M4
Definition riscv/opcodes.hpp:8718
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M4_E64
@ PseudoVFRDIV_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2901
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF8_MASK
@ PseudoVSLIDE1UP_VX_MF8_MASK
Definition riscv/opcodes.hpp:8821
LIEF::assembly::riscv::OPCODE::PseudoCCADDW
@ PseudoCCADDW
Definition riscv/opcodes.hpp:343
LIEF::assembly::riscv::OPCODE::VSSSEG3E8_V
@ VSSSEG3E8_V
Definition riscv/opcodes.hpp:13743
LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B64
@ PseudoVSM_V_B64
Definition riscv/opcodes.hpp:8997
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M2
@ PseudoVLSSEG3E16_V_M2
Definition riscv/opcodes.hpp:5436
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_M2_MASK
@ PseudoVAADD_VX_M2_MASK
Definition riscv/opcodes.hpp:566
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF8
@ PseudoVFNCVT_RM_X_F_W_MF8
Definition riscv/opcodes.hpp:2547
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M4_M1
@ PseudoVLOXSEG8EI64_V_M4_M1
Definition riscv/opcodes.hpp:4984
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M1_MF8_MASK
@ PseudoVSOXSEG4EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:9464
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF2_MASK
@ PseudoVMFLT_VV_MF2_MASK
Definition riscv/opcodes.hpp:6781
LIEF::assembly::riscv::OPCODE::TH_LRB
@ TH_LRB
Definition riscv/opcodes.hpp:13072
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M2
@ PseudoVSOXSEG3EI16_V_M1_M2
Definition riscv/opcodes.hpp:9293
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E16
@ PseudoVFNCVT_F_XU_W_M4_E16
Definition riscv/opcodes.hpp:2461
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF4_MASK
@ PseudoVOR_VI_MF4_MASK
Definition riscv/opcodes.hpp:7637
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M1_E64
@ PseudoVREMU_VX_M1_E64
Definition riscv/opcodes.hpp:8132
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF4
@ PseudoVLUXEI32_V_M1_MF4
Definition riscv/opcodes.hpp:5618
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M1_MASK
@ PseudoVLSEG2E16FF_V_M1_MASK
Definition riscv/opcodes.hpp:5055
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M1
@ PseudoVSRL_VX_M1
Definition riscv/opcodes.hpp:9933
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_M2
@ PseudoVC_V_FPR64VV_M2
Definition riscv/opcodes.hpp:1233
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E16_MASK
@ PseudoVWREDSUMU_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:11642
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_MF4_MASK
@ PseudoVLOXSEG6EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4781
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF2_MASK
@ PseudoVSOXSEG6EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9614
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M1_MASK
@ PseudoVRGATHEREI16_VV_M1_E16_M1_MASK
Definition riscv/opcodes.hpp:8275
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M2_MASK
@ PseudoVLSE16_V_M2_MASK
Definition riscv/opcodes.hpp:5013
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_MF4_MASK
@ PseudoVCTZ_V_MF4_MASK
Definition riscv/opcodes.hpp:1075
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M4_MASK
@ PseudoVSMUL_VV_M4_MASK
Definition riscv/opcodes.hpp:8969
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_M4_MASK
@ PseudoVSSUBU_VV_M4_MASK
Definition riscv/opcodes.hpp:10424
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M4_MASK
@ PseudoVLUXEI16_V_M4_M4_MASK
Definition riscv/opcodes.hpp:5589
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_M1_M1
@ PseudoVLOXSEG7EI8_V_M1_M1
Definition riscv/opcodes.hpp:4910
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E16
@ PseudoVFWADD_VV_M1_E16
Definition riscv/opcodes.hpp:3469
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M1
@ PseudoVSSSEG3E64_V_M1
Definition riscv/opcodes.hpp:10297
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_MF2
@ PseudoVLUXSEG3EI16_V_M1_MF2
Definition riscv/opcodes.hpp:5866
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_M1
@ PseudoVLSEG8E8_V_M1
Definition riscv/opcodes.hpp:5390
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_MF8
@ PseudoVC_V_X_MF8
Definition riscv/opcodes.hpp:1388
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E64_V_M4
@ PseudoVSSSEG2E64_V_M4
Definition riscv/opcodes.hpp:10269
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M4_M1
@ PseudoVSUXSEG7EI32_V_M4_M1
Definition riscv/opcodes.hpp:11205
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_MF8
@ PseudoVMSBC_VV_MF8
Definition riscv/opcodes.hpp:6923
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_MF2_MASK
@ PseudoVSUXSEG4EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:10946
LIEF::assembly::riscv::OPCODE::PseudoCALLIndirectNonX7
@ PseudoCALLIndirectNonX7
Definition riscv/opcodes.hpp:338
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M2
@ PseudoVFWCVT_XU_F_V_M2
Definition riscv/opcodes.hpp:3679
LIEF::assembly::riscv::OPCODE::AMOAND_B
@ AMOAND_B
Definition riscv/opcodes.hpp:11963
LIEF::assembly::riscv::OPCODE::PseudoCCSRL
@ PseudoCCSRL
Definition riscv/opcodes.hpp:360
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_M1_MASK
@ PseudoVSUXEI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:10538
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M4
@ PseudoVMSEQ_VX_M4
Definition riscv/opcodes.hpp:6984
LIEF::assembly::riscv::OPCODE::VFSGNJ_VF
@ VFSGNJ_VF
Definition riscv/opcodes.hpp:13265
LIEF::assembly::riscv::OPCODE::VMULHU_VV
@ VMULHU_VV
Definition riscv/opcodes.hpp:13550
LIEF::assembly::riscv::OPCODE::PseudoVQMACCU_2x8x2_M2
@ PseudoVQMACCU_2x8x2_M2
Definition riscv/opcodes.hpp:7685
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M2
@ PseudoVMSEQ_VX_M2
Definition riscv/opcodes.hpp:6982
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M1
@ PseudoVSUXSEG3EI64_V_M4_M1
Definition riscv/opcodes.hpp:10867
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF2
@ PseudoVSOXSEG3EI64_V_M1_MF2
Definition riscv/opcodes.hpp:9349
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M1
@ PseudoVLOXEI32_V_M1_M1
Definition riscv/opcodes.hpp:4220
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF2_MASK
@ PseudoVSUXSEG3EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:10864
LIEF::assembly::riscv::OPCODE::SC_D_AQ
@ SC_D_AQ
Definition riscv/opcodes.hpp:12940
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M2
@ PseudoVAESDF_VV_M2
Definition riscv/opcodes.hpp:665
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF4_MASK_TIED
@ PseudoVWADDU_WV_MF4_MASK_TIED
Definition riscv/opcodes.hpp:11377
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M8_E64
@ PseudoVFNMADD_VV_M8_E64
Definition riscv/opcodes.hpp:2727
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E16
@ PseudoVFREDOSUM_VS_M2_E16
Definition riscv/opcodes.hpp:3001
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8_MASK
@ PseudoVWSUBU_WV_MF8_MASK
Definition riscv/opcodes.hpp:11764
LIEF::assembly::riscv::OPCODE::PATCHABLE_TAIL_CALL
@ PATCHABLE_TAIL_CALL
Definition riscv/opcodes.hpp:62
LIEF::assembly::riscv::OPCODE::LIFETIME_START
@ LIFETIME_START
Definition riscv/opcodes.hpp:45
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M1_E32
@ PseudoVFMUL_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2324
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M1
@ PseudoVSUXSEG2EI32_V_M4_M1
Definition riscv/opcodes.hpp:10711
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M2_M2
@ PseudoVLOXSEG2EI32_V_M2_M2
Definition riscv/opcodes.hpp:4380
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF8
@ PseudoVWSLL_VI_MF8
Definition riscv/opcodes.hpp:11693
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_MF4_E16
@ PseudoVFNMADD_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:2685
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E16
@ PseudoVFWCVT_F_XU_V_MF2_E16
Definition riscv/opcodes.hpp:3595
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M4
@ PseudoVMSLT_VX_M4
Definition riscv/opcodes.hpp:7211
LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_S
@ PseudoQuietFLT_S
Definition riscv/opcodes.hpp:430
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF8
@ PseudoVWMULSU_VV_MF8
Definition riscv/opcodes.hpp:11549
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF2_MASK
@ PseudoVRSUB_VI_MF2_MASK
Definition riscv/opcodes.hpp:8585
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M1_M1_MASK
@ PseudoVLUXSEG3EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5891
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M4_MASK
@ PseudoVMFGE_VFPR16_M4_MASK
Definition riscv/opcodes.hpp:6645
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M2
@ PseudoVLOXSEG4EI64_V_M4_M2
Definition riscv/opcodes.hpp:4654
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E16_MASK
@ PseudoVDIVU_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:1448
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_M1
@ PseudoVRGATHEREI16_VV_MF2_E32_M1
Definition riscv/opcodes.hpp:8402
LIEF::assembly::riscv::OPCODE::PACKW
@ PACKW
Definition riscv/opcodes.hpp:12912
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF4_MASK
@ PseudoVSOXSEG5EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:9564
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M2
@ PseudoVRGATHEREI16_VV_M1_E32_M2
Definition riscv/opcodes.hpp:8284
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF2_MASK
@ PseudoVLUXEI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:5607
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M2_M1
@ PseudoVSUXSEG6EI16_V_M2_M1
Definition riscv/opcodes.hpp:11099
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_M1_MASK
@ PseudoVLOXSEG8EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4971
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M2_MF2_MASK
@ PseudoVLUXSEG5EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:6111
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M8_E32_MASK
@ PseudoVFMUL_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2331
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_MF2_MASK
@ PseudoTHVdotVMAQASU_VX_MF2_MASK
Definition riscv/opcodes.hpp:469
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16_MASK
@ PseudoVFWADD_WV_M2_E16_MASK
Definition riscv/opcodes.hpp:3514
LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M2
@ PseudoVGHSH_VV_M2
Definition riscv/opcodes.hpp:4046
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M2
@ PseudoVSADDU_VI_M2
Definition riscv/opcodes.hpp:8606
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M4_MASK
@ PseudoVSSUB_VX_M4_MASK
Definition riscv/opcodes.hpp:10466
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M4_E8_MASK
@ PseudoVFWCVT_F_XU_V_M4_E8_MASK
Definition riscv/opcodes.hpp:3594
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF8_MASK
@ PseudoVLSEG3E8FF_V_MF8_MASK
Definition riscv/opcodes.hpp:5171
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E32_MASK
@ PseudoVFSGNJN_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3154
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E16_MASK
@ PseudoVREM_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:8189
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF8_MASK_TIED
@ PseudoVWSUBU_WV_MF8_MASK_TIED
Definition riscv/opcodes.hpp:11765
LIEF::assembly::riscv::OPCODE::AMOAND_B_AQ_RL
@ AMOAND_B_AQ_RL
Definition riscv/opcodes.hpp:11965
LIEF::assembly::riscv::OPCODE::AMOCAS_Q_AQ
@ AMOCAS_Q_AQ
Definition riscv/opcodes.hpp:11996
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_M2
@ PseudoVLUXSEG3EI8_V_MF4_M2
Definition riscv/opcodes.hpp:5958
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M2
@ PseudoVSSUBU_VX_M2
Definition riscv/opcodes.hpp:10435
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M8_E16
@ PseudoVREMU_VV_M8_E16
Definition riscv/opcodes.hpp:8108
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E64_MASK
@ PseudoVFSUB_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:3438
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_MF2
@ PseudoVC_V_XVV_SE_MF2
Definition riscv/opcodes.hpp:1353
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E32
@ PseudoVFNMSAC_VV_MF2_E32
Definition riscv/opcodes.hpp:2791
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_M1
@ PseudoVSUXSEG6EI64_V_M2_M1
Definition riscv/opcodes.hpp:11143
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4_MASK_TIED
@ PseudoVWADD_WV_M4_MASK_TIED
Definition riscv/opcodes.hpp:11429
LIEF::assembly::riscv::OPCODE::AMOXOR_H_AQ_RL
@ AMOXOR_H_AQ_RL
Definition riscv/opcodes.hpp:12109
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VI_M1_MASK
@ PseudoVMSNE_VI_M1_MASK
Definition riscv/opcodes.hpp:7222
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E32_MASK
@ PseudoVRGATHER_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:8459
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_MF2_E16
@ PseudoVFWADD_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3457
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E32_MASK
@ PseudoVFCVT_F_X_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:1728
LIEF::assembly::riscv::OPCODE::PseudoVMSGE_VX_M
@ PseudoVMSGE_VX_M
Definition riscv/opcodes.hpp:7007
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_MF2_E32_MASK
@ PseudoVFMSAC_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:2249
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF8_MASK
@ PseudoVLSSEG5E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5509
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M2_MASK
@ PseudoVMFGT_VFPR32_M2_MASK
Definition riscv/opcodes.hpp:6685
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M2_E32_MASK
@ PseudoVFMAX_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:2096
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_MF2
@ PseudoVLSE8_V_MF2
Definition riscv/opcodes.hpp:5048
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_MF2_E32_MASK
@ PseudoVFMSAC_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2213
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E8_MASK
@ PseudoVREDMINU_VS_M2_E8_MASK
Definition riscv/opcodes.hpp:7847
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M8_MASK
@ PseudoVZEXT_VF8_M8_MASK
Definition riscv/opcodes.hpp:11910
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VV_M4_MASK
@ PseudoVWADD_VV_M4_MASK
Definition riscv/opcodes.hpp:11400
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_MF2
@ PseudoVSUXSEG5EI16_V_M1_MF2
Definition riscv/opcodes.hpp:11017
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E8_MASK
@ PseudoVWREDSUMU_VS_M2_E8_MASK
Definition riscv/opcodes.hpp:11622
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF4_MF4_MASK
@ PseudoVSUXEI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:10542
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E16
@ PseudoVFCVT_F_XU_V_MF2_E16
Definition riscv/opcodes.hpp:1695
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1_MASK_TIED
@ PseudoVWADDU_WV_M1_MASK_TIED
Definition riscv/opcodes.hpp:11361
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF4
@ PseudoVFNCVT_XU_F_W_MF4
Definition riscv/opcodes.hpp:2599
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_MF2
@ PseudoVLOXEI8_V_MF4_MF2
Definition riscv/opcodes.hpp:4322
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR64_M2_E64
@ PseudoVFRDIV_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2899
LIEF::assembly::riscv::OPCODE::VLSEG8E8_V
@ VLSEG8E8_V
Definition riscv/opcodes.hpp:13423
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_M4
@ PseudoVC_V_VV_SE_M4
Definition riscv/opcodes.hpp:1337
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_4x4x4_M4
@ PseudoVFWMACC_4x4x4_M4
Definition riscv/opcodes.hpp:3727
LIEF::assembly::riscv::OPCODE::FADD_S
@ FADD_S
Definition riscv/opcodes.hpp:12563
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M2
@ PseudoVLOXSEG2EI64_V_M4_M2
Definition riscv/opcodes.hpp:4422
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_MF8_MASK
@ PseudoVNSRL_WI_MF8_MASK
Definition riscv/opcodes.hpp:7601
LIEF::assembly::riscv::OPCODE::PseudoLW
@ PseudoLW
Definition riscv/opcodes.hpp:399
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M8_MASK
@ PseudoVCLMULH_VX_M8_MASK
Definition riscv/opcodes.hpp:965
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_M1
@ PseudoVLSSEG7E16_V_M1
Definition riscv/opcodes.hpp:5530
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M4
@ PseudoVSSEG2E8_V_M4
Definition riscv/opcodes.hpp:10019
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M4_MASK
@ PseudoVRGATHEREI16_VV_M8_E64_M4_MASK
Definition riscv/opcodes.hpp:8385
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M8_E64
@ PseudoVFNMADD_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2703
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR16_M2_E16
@ PseudoVFMIN_VFPR16_M2_E16
Definition riscv/opcodes.hpp:2134
LIEF::assembly::riscv::OPCODE::VMADC_VX
@ VMADC_VX
Definition riscv/opcodes.hpp:13490
LIEF::assembly::riscv::OPCODE::VLUXSEG7EI16_V
@ VLUXSEG7EI16_V
Definition riscv/opcodes.hpp:13476
LIEF::assembly::riscv::OPCODE::VC_FVV
@ VC_FVV
Definition riscv/opcodes.hpp:13173
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF2
@ PseudoVMFLT_VFPR16_MF2
Definition riscv/opcodes.hpp:6750
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E16_MASK
@ PseudoVREM_VX_M4_E16_MASK
Definition riscv/opcodes.hpp:8233
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_MF4_MASK
@ PseudoVSUXSEG8EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:11266
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M8
@ PseudoVMUL_VV_M8
Definition riscv/opcodes.hpp:7367
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_MF8
@ PseudoVWSUBU_WX_MF8
Definition riscv/opcodes.hpp:11777
LIEF::assembly::riscv::OPCODE::VLE64_V
@ VLE64_V
Definition riscv/opcodes.hpp:13328
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M4_MASK
@ PseudoTHVdotVMAQA_VV_M4_MASK
Definition riscv/opcodes.hpp:505
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_M1
@ PseudoVSOXEI32_V_M1_M1
Definition riscv/opcodes.hpp:9041
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_MF2_MASK
@ PseudoVLSEG8E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5377
LIEF::assembly::riscv::OPCODE::MOPR29
@ MOPR29
Definition riscv/opcodes.hpp:12882
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M2_E16_MASK
@ PseudoVFREDMIN_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:2972
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E16_MASK
@ PseudoVFCVT_F_XU_V_M2_E16_MASK
Definition riscv/opcodes.hpp:1678
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_MF4
@ PseudoVMSNE_VX_MF4
Definition riscv/opcodes.hpp:7259
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E16_MASK
@ PseudoVREDMINU_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:7865
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF2_MASK
@ PseudoVLSEG4E16FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5187
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M4_E32
@ PseudoVFSGNJ_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3257
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VX_M4_MASK
@ PseudoVMAXU_VX_M4_MASK
Definition riscv/opcodes.hpp:6533
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF4_MF4_MASK
@ PseudoVSUXSEG5EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:11086
LIEF::assembly::riscv::OPCODE::VMADC_VIM
@ VMADC_VIM
Definition riscv/opcodes.hpp:13487
LIEF::assembly::riscv::OPCODE::VNSRA_WI
@ VNSRA_WI
Definition riscv/opcodes.hpp:13577
LIEF::assembly::riscv::OPCODE::CM_POPRETZ
@ CM_POPRETZ
Definition riscv/opcodes.hpp:12149
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M2_M1_MASK
@ PseudoVLUXSEG8EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6327
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF4
@ PseudoVCLZ_V_MF4
Definition riscv/opcodes.hpp:1010
LIEF::assembly::riscv::OPCODE::VOR_VX
@ VOR_VX
Definition riscv/opcodes.hpp:13585
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF8
@ PseudoVASUB_VV_MF8
Definition riscv/opcodes.hpp:900
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF4
@ PseudoVSUXSEG7EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:11251
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M2_E16
@ PseudoVFMACC_VFPR16_M2_E16
Definition riscv/opcodes.hpp:1939
LIEF::assembly::riscv::OPCODE::CV_AVGU_SCI_H
@ CV_AVGU_SCI_H
Definition riscv/opcodes.hpp:12190
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M1_MASK
@ PseudoVSUXEI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10546
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF4_E16_MASK
@ PseudoVFWADD_WFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3496
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_M1
@ PseudoVSSEG6E32_V_M1
Definition riscv/opcodes.hpp:10109
LIEF::assembly::riscv::OPCODE::VWMUL_VX
@ VWMUL_VX
Definition riscv/opcodes.hpp:13824
LIEF::assembly::riscv::OPCODE::VL1RE32_V
@ VL1RE32_V
Definition riscv/opcodes.hpp:13308
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M1
@ PseudoVLOXSEG2EI64_V_M8_M1
Definition riscv/opcodes.hpp:4428
LIEF::assembly::riscv::OPCODE::AMOADD_W_RL
@ AMOADD_W_RL
Definition riscv/opcodes.hpp:11962
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M2
@ PseudoVMADD_VX_M2
Definition riscv/opcodes.hpp:6488
LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_GLUE
@ CONVERGENCECTRL_GLUE
Definition riscv/opcodes.hpp:71
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_MF2_E32_MASK
@ PseudoVFWADD_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3468
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF4_MASK
@ PseudoVFNCVT_RM_X_F_W_MF4_MASK
Definition riscv/opcodes.hpp:2546
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M4_E64_MASK
@ PseudoVFSGNJ_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:3268
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF2
@ PseudoVLUXSEG8EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:6336
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M1_MASK
@ PseudoVSSSEG3E64_V_M1_MASK
Definition riscv/opcodes.hpp:10298
LIEF::assembly::riscv::OPCODE::AMOMIN_B_AQ_RL
@ AMOMIN_B_AQ_RL
Definition riscv/opcodes.hpp:12053
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M4_MASK
@ PseudoVLOXEI8_V_M2_M4_MASK
Definition riscv/opcodes.hpp:4301
LIEF::assembly::riscv::OPCODE::VMULHSU_VX
@ VMULHSU_VX
Definition riscv/opcodes.hpp:13549
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF2_MASK
@ PseudoVLSEG6E8FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5305
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_MF4
@ PseudoVMFLE_VFPR16_MF4
Definition riscv/opcodes.hpp:6710
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M8
@ PseudoVCLZ_V_M8
Definition riscv/opcodes.hpp:1006
LIEF::assembly::riscv::OPCODE::PseudoRET
@ PseudoRET
Definition riscv/opcodes.hpp:432
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_MF2_MASK
@ PseudoVSOXEI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9036
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M1_MASK
@ PseudoVAADDU_VV_M1_MASK
Definition riscv/opcodes.hpp:522
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E32
@ PseudoVREDAND_VS_M2_E32
Definition riscv/opcodes.hpp:7710
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M1
@ PseudoVMFEQ_VFPR16_M1
Definition riscv/opcodes.hpp:6598
LIEF::assembly::riscv::OPCODE::G_UMULH
@ G_UMULH
Definition riscv/opcodes.hpp:180
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E64
@ PseudoVFCVT_RM_F_XU_V_M8_E64
Definition riscv/opcodes.hpp:1753
LIEF::assembly::riscv::OPCODE::PseudoVMXNOR_MM_MF2
@ PseudoVMXNOR_MM_MF2
Definition riscv/opcodes.hpp:7416
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF2_MASK
@ PseudoVLOXSEG5EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4741
LIEF::assembly::riscv::OPCODE::G_FREEZE
@ G_FREEZE
Definition riscv/opcodes.hpp:103
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M1
@ PseudoVMSGTU_VX_M1
Definition riscv/opcodes.hpp:7023
LIEF::assembly::riscv::OPCODE::CV_EXTHZ
@ CV_EXTHZ
Definition riscv/opcodes.hpp:12303
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E32
@ PseudoVFNMACC_VV_M4_E32
Definition riscv/opcodes.hpp:2659
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M2_E32_MASK
@ PseudoVREDMAX_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:7799
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M4
@ PseudoVNMSAC_VX_M4
Definition riscv/opcodes.hpp:7516
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF8
@ PseudoVLSEG3E8_V_MF8
Definition riscv/opcodes.hpp:5180
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF2
@ PseudoVWMACCUS_VX_MF2
Definition riscv/opcodes.hpp:11485
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_MF2
@ PseudoVSUXEI32_V_M2_MF2
Definition riscv/opcodes.hpp:10559
LIEF::assembly::riscv::OPCODE::VSUXSEG5EI16_V
@ VSUXSEG5EI16_V
Definition riscv/opcodes.hpp:13786
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF2_MASK
@ PseudoVANDN_VV_MF2_MASK
Definition riscv/opcodes.hpp:799
LIEF::assembly::riscv::OPCODE::C_NOP
@ C_NOP
Definition riscv/opcodes.hpp:12523
LIEF::assembly::riscv::OPCODE::VMSLEU_VI
@ VMSLEU_VI
Definition riscv/opcodes.hpp:13534
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E32_V_MF2_MASK
@ PseudoVLSSEG6E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5519
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M1_MASK
@ PseudoVLUXSEG2EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:5805
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF2_MASK
@ PseudoVLUXSEG3EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:5921
LIEF::assembly::riscv::OPCODE::VLSSEG4E16_V
@ VLSSEG4E16_V
Definition riscv/opcodes.hpp:13432
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E16
@ PseudoVFNCVT_ROD_F_F_W_M1_E16
Definition riscv/opcodes.hpp:2549
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E16
@ PseudoVFADD_VV_MF2_E16
Definition riscv/opcodes.hpp:1653
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M8_MASK
@ PseudoVSADD_VX_M8_MASK
Definition riscv/opcodes.hpp:8681
LIEF::assembly::riscv::OPCODE::PseudoLongBNE
@ PseudoLongBNE
Definition riscv/opcodes.hpp:406
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_M1_MASK
@ PseudoVWMACC_VX_M1_MASK
Definition riscv/opcodes.hpp:11528
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M2_E16_MASK
@ PseudoVFWMACC_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3734
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E16_MASK
@ PseudoVFNCVT_F_X_W_M1_E16_MASK
Definition riscv/opcodes.hpp:2472
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF2_MASK
@ PseudoVASUBU_VV_MF2_MASK
Definition riscv/opcodes.hpp:869
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M2_MASK
@ PseudoVMFNE_VV_M2_MASK
Definition riscv/opcodes.hpp:6817
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_M1_M1_MASK
@ PseudoVSOXSEG3EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9374
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF4
@ PseudoVSOXEI8_V_MF8_MF4
Definition riscv/opcodes.hpp:9151
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M2_E32
@ PseudoVFSGNJ_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3255
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M1
@ PseudoVADD_VX_M1
Definition riscv/opcodes.hpp:626
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF8_MASK
@ PseudoVMSGTU_VX_MF8_MASK
Definition riscv/opcodes.hpp:7036
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M1
@ PseudoVSUXSEG3EI64_V_M8_M1
Definition riscv/opcodes.hpp:10873
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_MF2_E16
@ PseudoVFMAX_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2065
LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_MF8
@ PseudoVMXOR_MM_MF8
Definition riscv/opcodes.hpp:7425
LIEF::assembly::riscv::OPCODE::PseudoVID_V_M1
@ PseudoVID_V_M1
Definition riscv/opcodes.hpp:4055
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E16
@ PseudoVREM_VX_M8_E16
Definition riscv/opcodes.hpp:8240
LIEF::assembly::riscv::OPCODE::VT_MASKCN
@ VT_MASKCN
Definition riscv/opcodes.hpp:13803
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E16_M8
@ PseudoVRGATHEREI16_VV_M4_E16_M8
Definition riscv/opcodes.hpp:8344
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M8
@ PseudoVMSLT_VX_M8
Definition riscv/opcodes.hpp:7213
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M4_MASK
@ PseudoVFSLIDE1UP_VFPR16_M4_MASK
Definition riscv/opcodes.hpp:3336
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_MF2
@ PseudoVSOXSEG2EI32_V_M2_MF2
Definition riscv/opcodes.hpp:9205
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF2
@ PseudoVAADD_VV_MF2
Definition riscv/opcodes.hpp:557
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF4
@ PseudoVLOXEI32_V_M1_MF4
Definition riscv/opcodes.hpp:4226
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M8_M2_MASK
@ PseudoVSOXSEG3EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:9338
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF2_MASK
@ PseudoVLOXSEG2EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4399
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M1_E32
@ PseudoVFWMSAC_VV_M1_E32
Definition riscv/opcodes.hpp:3787
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E64_MASK
@ PseudoVDIV_VX_M8_E64_MASK
Definition riscv/opcodes.hpp:1584
LIEF::assembly::riscv::OPCODE::AMOADD_B_RL
@ AMOADD_B_RL
Definition riscv/opcodes.hpp:11950
LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M4
@ PseudoVSSE32_V_M4
Definition riscv/opcodes.hpp:9963
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E32_MASK
@ PseudoVFADD_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:1656
LIEF::assembly::riscv::OPCODE::VMV_V_X
@ VMV_V_X
Definition riscv/opcodes.hpp:13563
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M8_MASK
@ PseudoVMFEQ_VFPR32_M8_MASK
Definition riscv/opcodes.hpp:6617
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_MF2
@ PseudoVSUXEI16_V_M1_MF2
Definition riscv/opcodes.hpp:10509
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E16_MASK
@ PseudoVREDSUM_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:7973
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_M1_MASK
@ PseudoVLOXSEG8EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4937
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M8_M1
@ PseudoVSOXSEG6EI64_V_M8_M1
Definition riscv/opcodes.hpp:9649
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_M1_MASK
@ PseudoVSOXSEG3EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:9394
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF8
@ PseudoVCLZ_V_MF8
Definition riscv/opcodes.hpp:1012
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF4_MASK
@ PseudoVSUXSEG7EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:11192
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_MF2_E32
@ PseudoVFREDMIN_VS_MF2_E32
Definition riscv/opcodes.hpp:2991
LIEF::assembly::riscv::OPCODE::AMOMINU_H_RL
@ AMOMINU_H_RL
Definition riscv/opcodes.hpp:12046
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B16_MASK
@ PseudoVCPOP_M_B16_MASK
Definition riscv/opcodes.hpp:1038
LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M1
@ PseudoVAESKF2_VI_M1
Definition riscv/opcodes.hpp:761
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M1_MASK
@ PseudoVSSSEG4E64_V_M1_MASK
Definition riscv/opcodes.hpp:10326
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M4_E64
@ PseudoVFSUB_VFPR64_M4_E64
Definition riscv/opcodes.hpp:3417
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF4
@ PseudoVLOXSEG7EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:4926
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF8
@ PseudoVLOXSEG5EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:4728
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_M1
@ PseudoVSOXSEG7EI16_V_MF4_M1
Definition riscv/opcodes.hpp:9683
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M4_MASK
@ PseudoVMACC_VX_M4_MASK
Definition riscv/opcodes.hpp:6421
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VI_MF8
@ PseudoVSSRL_VI_MF8
Definition riscv/opcodes.hpp:10217
LIEF::assembly::riscv::OPCODE::CV_SB_ri_inc
@ CV_SB_ri_inc
Definition riscv/opcodes.hpp:12390
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF4_MASK
@ PseudoVLUXSEG7EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:6319
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_M1_M1_MASK
@ PseudoVSUXSEG7EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11236
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_MF2_E32_MASK
@ PseudoVFMUL_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:2369
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M1_MF4_MASK
@ PseudoVLUXSEG2EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:5801
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M2
@ PseudoVZEXT_VF8_M2
Definition riscv/opcodes.hpp:11905
LIEF::assembly::riscv::OPCODE::VMV_V_V
@ VMV_V_V
Definition riscv/opcodes.hpp:13562
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M8_E32
@ PseudoVFRSUB_VFPR32_M8_E32
Definition riscv/opcodes.hpp:3109
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M1
@ PseudoVSLIDEUP_VX_M1
Definition riscv/opcodes.hpp:8864
LIEF::assembly::riscv::OPCODE::VC_V_FV
@ VC_V_FV
Definition riscv/opcodes.hpp:13182
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M2_MASK
@ PseudoVFSLIDE1DOWN_VFPR64_M2_MASK
Definition riscv/opcodes.hpp:3326
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF2_E16_MASK
@ PseudoVFWMSAC_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3774
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M8_M2
@ PseudoVLOXSEG2EI32_V_M8_M2
Definition riscv/opcodes.hpp:4392
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF4
@ PseudoVSUXSEG4EI32_V_M1_MF4
Definition riscv/opcodes.hpp:10939
LIEF::assembly::riscv::OPCODE::PseudoVSSE32_V_M8_MASK
@ PseudoVSSE32_V_M8_MASK
Definition riscv/opcodes.hpp:9966
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF2_MF4_MASK
@ PseudoVSUXSEG7EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:11186
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF4_MF2
@ PseudoVSOXSEG7EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:9739
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_MF2_E32_MASK
@ PseudoVFWADD_WFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3504
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E16_MASK
@ PseudoVFWCVT_F_X_V_M1_E16_MASK
Definition riscv/opcodes.hpp:3608
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_MF4
@ PseudoVMADC_VV_MF4
Definition riscv/opcodes.hpp:6456
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_M8
@ PseudoVC_V_X_SE_M8
Definition riscv/opcodes.hpp:1392
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF4_MASK
@ PseudoVLUXSEG8EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:6333
LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B64
@ PseudoVLM_V_B64
Definition riscv/opcodes.hpp:4176
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M1_MASK
@ PseudoVFSLIDE1UP_VFPR64_M1_MASK
Definition riscv/opcodes.hpp:3354
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E16_MASK
@ PseudoVFMADD_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:2046
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M1_E64
@ PseudoVFDIV_VFPR64_M1_E64
Definition riscv/opcodes.hpp:1885
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_M1
@ PseudoVC_V_FPR32V_M1
Definition riscv/opcodes.hpp:1222
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M2
@ PseudoVSUXEI32_V_M4_M2
Definition riscv/opcodes.hpp:10563
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M2_MASK
@ PseudoVROL_VX_M2_MASK
Definition riscv/opcodes.hpp:8523
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M2_MASK
@ PseudoVRGATHEREI16_VV_M2_E64_M2_MASK
Definition riscv/opcodes.hpp:8325
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_MF2_MASK
@ PseudoVSUXSEG7EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:11244
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M2_MASK
@ PseudoVSSEG3E8_V_M2_MASK
Definition riscv/opcodes.hpp:10048
LIEF::assembly::riscv::OPCODE::VSSEG4E8_V
@ VSSEG4E8_V
Definition riscv/opcodes.hpp:13713
LIEF::assembly::riscv::OPCODE::VLSEG3E8_V
@ VLSEG3E8_V
Definition riscv/opcodes.hpp:13383
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E8_MASK
@ PseudoVWREDSUMU_VS_MF4_E8_MASK
Definition riscv/opcodes.hpp:11644
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_M1_MASK
@ PseudoVLOXSEG2EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4335
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF2
@ PseudoVSUXSEG7EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:11209
LIEF::assembly::riscv::OPCODE::G_UDIVFIXSAT
@ G_UDIVFIXSAT
Definition riscv/opcodes.hpp:195
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_MF2
@ PseudoVLOXSEG7EI16_V_M1_MF2
Definition riscv/opcodes.hpp:4852
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M1_MASK
@ PseudoVSSRA_VI_M1_MASK
Definition riscv/opcodes.hpp:10164
LIEF::assembly::riscv::OPCODE::VMSNE_VV
@ VMSNE_VV
Definition riscv/opcodes.hpp:13545
LIEF::assembly::riscv::OPCODE::SHA256SUM0
@ SHA256SUM0
Definition riscv/opcodes.hpp:12967
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_M2_MASK
@ PseudoVSOXSEG4EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9440
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_MF2_MASK
@ PseudoVSUXEI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:10648
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF8
@ PseudoVFNCVT_RTZ_XU_F_W_MF8
Definition riscv/opcodes.hpp:2577
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M1_MASK
@ PseudoVMSLE_VX_M1_MASK
Definition riscv/opcodes.hpp:7150
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E64_MASK
@ PseudoVRGATHER_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:8453
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_M1
@ PseudoVLUXSEG2EI64_V_M2_M1
Definition riscv/opcodes.hpp:5804
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M1
@ PseudoVMFLT_VFPR16_M1
Definition riscv/opcodes.hpp:6742
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_MF2_MASK
@ PseudoVLUXEI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:5627
LIEF::assembly::riscv::OPCODE::PACKH
@ PACKH
Definition riscv/opcodes.hpp:12911
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_M4_MASK
@ PseudoVNCLIP_WV_M4_MASK
Definition riscv/opcodes.hpp:7479
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E16
@ PseudoVDIVU_VX_MF4_E16
Definition riscv/opcodes.hpp:1505
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF4_MASK
@ PseudoVSOXSEG2EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9188
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E16
@ PseudoVFWMACCBF16_VV_MF2_E16
Definition riscv/opcodes.hpp:3719
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E16
@ PseudoVFREDUSUM_VS_M2_E16
Definition riscv/opcodes.hpp:3031
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M1_E64
@ PseudoVFNMSAC_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2757
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E64_MASK
@ PseudoVREDMINU_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:7845
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF8_MF8
@ PseudoVLUXSEG3EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:5970
LIEF::assembly::riscv::OPCODE::CV_BSETR
@ CV_BSETR
Definition riscv/opcodes.hpp:12205
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_MF4
@ PseudoVMSBC_VXM_MF4
Definition riscv/opcodes.hpp:6929
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M2_MASK
@ PseudoVNSRA_WX_M2_MASK
Definition riscv/opcodes.hpp:7581
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF2_MASK
@ PseudoVSRL_VV_MF2_MASK
Definition riscv/opcodes.hpp:9928
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF2
@ PseudoVLUXSEG6EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:6176
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M1_E32_MASK
@ PseudoVFWSUB_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3966
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_MF2_MASK
@ PseudoVSOXSEG7EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:9728
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF4
@ PseudoVLUXSEG4EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:6072
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M2_M1
@ PseudoVSUXSEG6EI32_V_M2_M1
Definition riscv/opcodes.hpp:11121
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M2
@ PseudoVLUXSEG4EI64_V_M4_M2
Definition riscv/opcodes.hpp:6046
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M4_M2
@ PseudoVSOXSEG4EI64_V_M4_M2
Definition riscv/opcodes.hpp:9475
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E16
@ PseudoVREM_VV_M8_E16
Definition riscv/opcodes.hpp:8196
LIEF::assembly::riscv::OPCODE::FNMSUB_D_INX
@ FNMSUB_D_INX
Definition riscv/opcodes.hpp:12745
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_M4
@ PseudoVC_V_IVW_SE_M4
Definition riscv/opcodes.hpp:1270
LIEF::assembly::riscv::OPCODE::VSSSEG4E16_V
@ VSSSEG4E16_V
Definition riscv/opcodes.hpp:13744
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M8_E64
@ PseudoVFSUB_VFPR64_M8_E64
Definition riscv/opcodes.hpp:3419
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF8_MASK
@ PseudoVFNCVT_RM_X_F_W_MF8_MASK
Definition riscv/opcodes.hpp:2548
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF2_MASK
@ PseudoVLOXSEG3EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4529
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VV_MF4
@ PseudoVASUBU_VV_MF4
Definition riscv/opcodes.hpp:870
LIEF::assembly::riscv::OPCODE::VFMV_V_F
@ VFMV_V_F
Definition riscv/opcodes.hpp:13233
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VX_M1
@ PseudoVMADC_VX_M1
Definition riscv/opcodes.hpp:6465
LIEF::assembly::riscv::OPCODE::VLSEG5E64_V
@ VLSEG5E64_V
Definition riscv/opcodes.hpp:13397
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M1_M1_MASK
@ PseudoVLOXSEG5EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4691
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_MF4
@ PseudoVAESZ_VS_M4_MF4
Definition riscv/opcodes.hpp:779
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_M8
@ PseudoVC_V_VV_M8
Definition riscv/opcodes.hpp:1331
LIEF::assembly::riscv::OPCODE::CV_LBU_rr
@ CV_LBU_rr
Definition riscv/opcodes.hpp:12319
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E32_MASK
@ PseudoVDIV_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:1530
LIEF::assembly::riscv::OPCODE::AMOADD_D_AQ_RL
@ AMOADD_D_AQ_RL
Definition riscv/opcodes.hpp:11953
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M1
@ PseudoVSUXEI8_V_MF4_M1
Definition riscv/opcodes.hpp:10643
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_M2
@ PseudoVLOXEI64_V_M2_M2
Definition riscv/opcodes.hpp:4268
LIEF::assembly::riscv::OPCODE::AMOAND_H_AQ_RL
@ AMOAND_H_AQ_RL
Definition riscv/opcodes.hpp:11973
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_MF4
@ PseudoVSUXSEG3EI64_V_M2_MF4
Definition riscv/opcodes.hpp:10865
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M4_E64_MASK
@ PseudoVFMIN_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2159
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M4_E32_MASK
@ PseudoVFSGNJX_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3198
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E32_MASK
@ PseudoVFSGNJ_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3298
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M8_E32
@ PseudoVFMIN_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2150
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E16
@ PseudoVFNCVT_F_F_W_M1_E16
Definition riscv/opcodes.hpp:2435
LIEF::assembly::riscv::OPCODE::FCVT_H_LU
@ FCVT_H_LU
Definition riscv/opcodes.hpp:12594
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M2_E16_MASK
@ PseudoVFWMACCBF16_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3712
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M2_M2
@ PseudoVSOXEI32_V_M2_M2
Definition riscv/opcodes.hpp:9051
LIEF::assembly::riscv::OPCODE::FSGNJ_D_IN32X
@ FSGNJ_D_IN32X
Definition riscv/opcodes.hpp:12772
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M4_E16_MASK
@ PseudoVFRSQRT7_V_M4_E16_MASK
Definition riscv/opcodes.hpp:3074
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E8_MASK
@ PseudoVREDMINU_VS_M1_E8_MASK
Definition riscv/opcodes.hpp:7839
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M4_MASK
@ PseudoVMSLTU_VX_M4_MASK
Definition riscv/opcodes.hpp:7183
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF2_MASK
@ PseudoVSOXSEG6EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:9666
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_MF2_E16
@ PseudoVFWNMACC_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3845
LIEF::assembly::riscv::OPCODE::FMINM_D
@ FMINM_D
Definition riscv/opcodes.hpp:12703
LIEF::assembly::riscv::OPCODE::PseudoVLE32_V_M4
@ PseudoVLE32_V_M4
Definition riscv/opcodes.hpp:4121
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M2_MASK
@ PseudoVLUXSEG2EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:5823
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M8_M4
@ PseudoVLOXSEG2EI16_V_M8_M4
Definition riscv/opcodes.hpp:4352
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M1
@ PseudoVSUXSEG4EI64_V_M2_M1
Definition riscv/opcodes.hpp:10969
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_MF2
@ PseudoVOR_VX_MF2
Definition riscv/opcodes.hpp:7662
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF4
@ PseudoVSUXEI16_V_MF2_MF4
Definition riscv/opcodes.hpp:10535
LIEF::assembly::riscv::OPCODE::ANDN
@ ANDN
Definition riscv/opcodes.hpp:12117
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF8_MASK
@ PseudoVLUXSEG2EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:5795
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32_MASK
@ PseudoVFWADD_WV_M4_E32_MASK
Definition riscv/opcodes.hpp:3526
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M4_MASK
@ PseudoVLOXSEG2EI8_V_M1_M4_MASK
Definition riscv/opcodes.hpp:4439
LIEF::assembly::riscv::OPCODE::VFMIN_VF
@ VFMIN_VF
Definition riscv/opcodes.hpp:13223
LIEF::assembly::riscv::OPCODE::VSUXSEG3EI16_V
@ VSUXSEG3EI16_V
Definition riscv/opcodes.hpp:13778
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF8
@ PseudoVMINU_VX_MF8
Definition riscv/opcodes.hpp:6852
LIEF::assembly::riscv::OPCODE::LW
@ LW
Definition riscv/opcodes.hpp:12852
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M2
@ PseudoVSOXSEG2EI8_V_MF2_M2
Definition riscv/opcodes.hpp:9269
LIEF::assembly::riscv::OPCODE::AMOMAX_B_AQ_RL
@ AMOMAX_B_AQ_RL
Definition riscv/opcodes.hpp:12021
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M1_E64
@ PseudoVFCVT_RM_F_X_V_M1_E64
Definition riscv/opcodes.hpp:1765
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF4
@ PseudoVSSE16_V_MF4
Definition riscv/opcodes.hpp:9957
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M1_MASK
@ PseudoVSUXSEG2EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:10746
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_M1
@ PseudoVLSSEG8E16_V_M1
Definition riscv/opcodes.hpp:5550
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVW_SE_MF8
@ PseudoVC_V_VVW_SE_MF8
Definition riscv/opcodes.hpp:1327
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M2
@ PseudoVMFEQ_VFPR16_M2
Definition riscv/opcodes.hpp:6600
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF2
@ PseudoVFCVT_RTZ_X_F_V_MF2
Definition riscv/opcodes.hpp:1835
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF8
@ PseudoVLUXSEG2EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:5760
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M8_MASK
@ PseudoVMIN_VX_M8_MASK
Definition riscv/opcodes.hpp:6875
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M8
@ PseudoVLSE16_V_M8
Definition riscv/opcodes.hpp:5016
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF4_MASK
@ PseudoVSOXSEG3EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9344
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M8_M4_MASK
@ PseudoVLUXEI32_V_M8_M4_MASK
Definition riscv/opcodes.hpp:5639
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_MF4
@ PseudoVSSRL_VV_MF4
Definition riscv/opcodes.hpp:10229
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF4_MASK
@ PseudoVLSEG8E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5369
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M2_E16
@ PseudoVFNCVT_RM_F_X_W_M2_E16
Definition riscv/opcodes.hpp:2511
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF4_MASK
@ PseudoVSOXSEG3EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:9398
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_MF2
@ PseudoVSOXSEG3EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:9307
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M8
@ PseudoTHVdotVMAQAU_VX_M8
Definition riscv/opcodes.hpp:496
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF8
@ PseudoVSRL_VX_MF8
Definition riscv/opcodes.hpp:9945
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_MF2_E16
@ PseudoVFMSUB_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2260
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M2_E32
@ PseudoVFWSUB_WFPR32_M2_E32
Definition riscv/opcodes.hpp:4003
LIEF::assembly::riscv::OPCODE::FDIV_D
@ FDIV_D
Definition riscv/opcodes.hpp:12643
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M2_MF8
@ PseudoVAESEM_VS_M2_MF8
Definition riscv/opcodes.hpp:735
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_MF4
@ PseudoVWADD_WX_MF4
Definition riscv/opcodes.hpp:11451
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M2_MASK
@ PseudoVMSLEU_VI_M2_MASK
Definition riscv/opcodes.hpp:7082
LIEF::assembly::riscv::OPCODE::TH_ICACHE_IALLS
@ TH_ICACHE_IALLS
Definition riscv/opcodes.hpp:13055
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M2
@ PseudoVMULH_VV_M2
Definition riscv/opcodes.hpp:7335
LIEF::assembly::riscv::OPCODE::G_SHUFFLE_VECTOR
@ G_SHUFFLE_VECTOR
Definition riscv/opcodes.hpp:252
LIEF::assembly::riscv::OPCODE::AMOOR_B
@ AMOOR_B
Definition riscv/opcodes.hpp:12067
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_M1
@ PseudoVLUXSEG4EI16_V_MF2_M1
Definition riscv/opcodes.hpp:5984
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E32
@ PseudoVFMSAC_VV_M8_E32
Definition riscv/opcodes.hpp:2242
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M1_MASK
@ PseudoVSUXSEG3EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10878
LIEF::assembly::riscv::OPCODE::VSSEG2E64_V
@ VSSEG2E64_V
Definition riscv/opcodes.hpp:13704
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_MF2
@ PseudoVLUXSEG5EI64_V_M4_MF2
Definition riscv/opcodes.hpp:6138
LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B64
@ PseudoVMSET_M_B64
Definition riscv/opcodes.hpp:6999
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M4_MASK
@ PseudoVLUXSEG2EI32_V_M4_M4_MASK
Definition riscv/opcodes.hpp:5783
LIEF::assembly::riscv::OPCODE::CV_LH_ri_inc
@ CV_LH_ri_inc
Definition riscv/opcodes.hpp:12327
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_M2_M1_MASK
@ PseudoVSOXSEG8EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9756
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E16_MASK
@ PseudoVFWADD_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:3482
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M8_MASK
@ PseudoVFCVT_RTZ_XU_F_V_M8_MASK
Definition riscv/opcodes.hpp:1822
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B1
@ PseudoVMSBF_M_B1
Definition riscv/opcodes.hpp:6938
LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SCI_B
@ CV_CMPGTU_SCI_B
Definition riscv/opcodes.hpp:12231
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M1
@ PseudoVCLZ_V_M1
Definition riscv/opcodes.hpp:1000
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_MF2_MASK
@ PseudoVLSEG7E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5327
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_M1_MASK
@ PseudoVSUXEI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:10652
LIEF::assembly::riscv::OPCODE::PATCHABLE_FUNCTION_EXIT
@ PATCHABLE_FUNCTION_EXIT
Definition riscv/opcodes.hpp:61
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_M1_MASK
@ PseudoVASUBU_VX_M1_MASK
Definition riscv/opcodes.hpp:875
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF4_MASK
@ PseudoVASUBU_VX_MF4_MASK
Definition riscv/opcodes.hpp:885
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M1_MF4
@ PseudoVLOXSEG2EI32_V_M1_MF4
Definition riscv/opcodes.hpp:4376
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_MF2_MASK
@ PseudoVSOXSEG7EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9674
LIEF::assembly::riscv::OPCODE::CV_CMPGE_SC_B
@ CV_CMPGE_SC_B
Definition riscv/opcodes.hpp:12227
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M4_MASK
@ PseudoVSE8_V_M4_MASK
Definition riscv/opcodes.hpp:8737
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E64
@ PseudoVFSGNJN_VV_M1_E64
Definition riscv/opcodes.hpp:3155
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E64
@ PseudoVDIVU_VX_M1_E64
Definition riscv/opcodes.hpp:1471
LIEF::assembly::riscv::OPCODE::C_JR
@ C_JR
Definition riscv/opcodes.hpp:12500
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M1
@ PseudoVMSLE_VX_M1
Definition riscv/opcodes.hpp:7149
LIEF::assembly::riscv::OPCODE::VL1RE16_V
@ VL1RE16_V
Definition riscv/opcodes.hpp:13307
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M4
@ PseudoVMINU_VX_M4
Definition riscv/opcodes.hpp:6844
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E64
@ PseudoVFSGNJN_VV_M4_E64
Definition riscv/opcodes.hpp:3167
LIEF::assembly::riscv::OPCODE::VSM4R_VS
@ VSM4R_VS
Definition riscv/opcodes.hpp:13655
LIEF::assembly::riscv::OPCODE::VFWMACCBF16_VF
@ VFWMACCBF16_VF
Definition riscv/opcodes.hpp:13284
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M2_M1_MASK
@ PseudoVLUXSEG6EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6167
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_M4_MASK
@ PseudoVWMACCU_VX_M4_MASK
Definition riscv/opcodes.hpp:11508
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E64
@ PseudoVDIV_VV_M2_E64
Definition riscv/opcodes.hpp:1523
LIEF::assembly::riscv::OPCODE::VNSRL_WI
@ VNSRL_WI
Definition riscv/opcodes.hpp:13580
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M1_MASK
@ PseudoVSSEG3E8_V_M1_MASK
Definition riscv/opcodes.hpp:10046
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_MF2_E32
@ PseudoVFWNMACC_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3855
LIEF::assembly::riscv::OPCODE::PACK
@ PACK
Definition riscv/opcodes.hpp:12910
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E8
@ PseudoVREMU_VX_M2_E8
Definition riscv/opcodes.hpp:8142
LIEF::assembly::riscv::OPCODE::CV_BEQIMM
@ CV_BEQIMM
Definition riscv/opcodes.hpp:12201
LIEF::assembly::riscv::OPCODE::VFWADD_WF
@ VFWADD_WF
Definition riscv/opcodes.hpp:13274
LIEF::assembly::riscv::OPCODE::TH_SURH
@ TH_SURH
Definition riscv/opcodes.hpp:13118
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF2
@ PseudoVSOXSEG4EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:9417
LIEF::assembly::riscv::OPCODE::VLOXSEG3EI32_V
@ VLOXSEG3EI32_V
Definition riscv/opcodes.hpp:13341
LIEF::assembly::riscv::OPCODE::SH3ADD_UW
@ SH3ADD_UW
Definition riscv/opcodes.hpp:12964
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF8
@ PseudoVLUXSEG8EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:6360
LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_M2
@ PseudoVC_VVW_SE_M2
Definition riscv/opcodes.hpp:1154
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M4
@ PseudoVRGATHER_VX_M4
Definition riscv/opcodes.hpp:8496
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_MF2_MASK
@ PseudoVLUXSEG4EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:6049
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF2_MASK
@ PseudoVLOXEI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4261
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF2_MASK
@ PseudoVADD_VI_MF2_MASK
Definition riscv/opcodes.hpp:607
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M2_E32
@ PseudoVFWSUB_VV_M2_E32
Definition riscv/opcodes.hpp:3979
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_MF2
@ PseudoVMERGE_VXM_MF2
Definition riscv/opcodes.hpp:6595
LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_M1_MASK
@ PseudoVLSE32_V_M1_MASK
Definition riscv/opcodes.hpp:5023
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_M4_MASK
@ PseudoVLOXEI32_V_M2_M4_MASK
Definition riscv/opcodes.hpp:4233
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M2_M2
@ PseudoVLOXEI16_V_M2_M2
Definition riscv/opcodes.hpp:4188
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M4_MASK
@ PseudoVMUL_VX_M4_MASK
Definition riscv/opcodes.hpp:7380
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E16_MASK
@ PseudoVFCVT_F_X_V_M1_E16_MASK
Definition riscv/opcodes.hpp:1702
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF2
@ PseudoVLOXSEG7EI32_V_M1_MF2
Definition riscv/opcodes.hpp:4872
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_M2
@ PseudoVC_V_FPR16V_M2
Definition riscv/opcodes.hpp:1191
LIEF::assembly::riscv::OPCODE::VSADD_VX
@ VSADD_VX
Definition riscv/opcodes.hpp:13627
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_MF8
@ PseudoVMADC_VV_MF8
Definition riscv/opcodes.hpp:6457
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M8_MASK
@ PseudoVMFNE_VV_M8_MASK
Definition riscv/opcodes.hpp:6821
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E32_V_M1_MASK
@ PseudoVSSEG5E32_V_M1_MASK
Definition riscv/opcodes.hpp:10090
LIEF::assembly::riscv::OPCODE::SLT
@ SLT
Definition riscv/opcodes.hpp:12987
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M2_E32_MASK
@ PseudoVFWSUB_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3968
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_MF2_MASK
@ PseudoVSUXSEG8EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11278
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M1
@ PseudoVLSEG2E8_V_M1
Definition riscv/opcodes.hpp:5114
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M1_MASK
@ PseudoVSOXSEG4EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9490
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_MF4_MASK
@ PseudoVNCLIPU_WV_MF4_MASK
Definition riscv/opcodes.hpp:7447
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_M4_E16_MASK
@ PseudoVFSGNJX_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3186
LIEF::assembly::riscv::OPCODE::CV_CMPLT_H
@ CV_CMPLT_H
Definition riscv/opcodes.hpp:12260
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF4_MASK
@ PseudoVSOXSEG4EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9454
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M4_E32
@ PseudoVFNMSAC_VV_M4_E32
Definition riscv/opcodes.hpp:2779
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E32
@ PseudoVFSUB_VV_M8_E32
Definition riscv/opcodes.hpp:3441
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M4_M8
@ PseudoVLOXEI32_V_M4_M8
Definition riscv/opcodes.hpp:4242
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_M1
@ PseudoVSOXSEG8EI16_V_MF2_M1
Definition riscv/opcodes.hpp:9757
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_MF4
@ PseudoVLOXSEG3EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:4488
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M2_E16
@ PseudoVREDMINU_VS_M2_E16
Definition riscv/opcodes.hpp:7840
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M2
@ PseudoVLUXSEG3EI32_V_M4_M2
Definition riscv/opcodes.hpp:5906
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E64
@ PseudoVREMU_VX_M8_E64
Definition riscv/opcodes.hpp:8156
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64_V_M1
@ PseudoVLSEG7E64_V_M1
Definition riscv/opcodes.hpp:5340
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E16_MASK
@ PseudoVDIVU_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:1462
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M2_MF4_MASK
@ PseudoVLOXSEG6EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:4823
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF8_MASK
@ PseudoVMSLTU_VX_MF8_MASK
Definition riscv/opcodes.hpp:7191
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B1_MASK
@ PseudoVMSIF_M_B1_MASK
Definition riscv/opcodes.hpp:7068
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF8_TIED
@ PseudoVWADDU_WV_MF8_TIED
Definition riscv/opcodes.hpp:11382
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E16
@ PseudoVDIVU_VX_M8_E16
Definition riscv/opcodes.hpp:1491
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_MF2
@ PseudoVC_V_XV_MF2
Definition riscv/opcodes.hpp:1372
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M2_MASK
@ PseudoTHVdotVMAQASU_VX_M2_MASK
Definition riscv/opcodes.hpp:463
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32V_SE_M8
@ PseudoVC_V_FPR32V_SE_M8
Definition riscv/opcodes.hpp:1230
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_M1_M2
@ PseudoVLOXSEG4EI16_V_M1_M2
Definition riscv/opcodes.hpp:4582
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M8_MASK
@ PseudoVLE8_V_M8_MASK
Definition riscv/opcodes.hpp:4164
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M4_E16
@ PseudoVFWADD_VV_M4_E16
Definition riscv/opcodes.hpp:3477
LIEF::assembly::riscv::OPCODE::VFNCVT_RTZ_X_F_W
@ VFNCVT_RTZ_X_F_W
Definition riscv/opcodes.hpp:13240
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_M4_MASK
@ PseudoVADD_VV_M4_MASK
Definition riscv/opcodes.hpp:617
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4_TIED
@ PseudoVWSUBU_WV_M4_TIED
Definition riscv/opcodes.hpp:11754
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M8_MASK
@ PseudoVLUXEI64_V_M8_M8_MASK
Definition riscv/opcodes.hpp:5681
LIEF::assembly::riscv::OPCODE::G_FPTOUI
@ G_FPTOUI
Definition riscv/opcodes.hpp:217
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M4_E16_MASK
@ PseudoVFWNMSAC_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3880
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M4_E32
@ PseudoVFWNMSAC_VV_M4_E32
Definition riscv/opcodes.hpp:3903
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_M4_MASK
@ PseudoVSOXEI8_V_MF2_M4_MASK
Definition riscv/opcodes.hpp:9136
LIEF::assembly::riscv::OPCODE::G_FSHR
@ G_FSHR
Definition riscv/opcodes.hpp:162
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_MF2_MASK
@ PseudoVSUXSEG2EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:10752
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M8_M8_MASK
@ PseudoVLOXEI16_V_M8_M8_MASK
Definition riscv/opcodes.hpp:4203
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M2
@ PseudoVSOXSEG4EI16_V_MF2_M2
Definition riscv/opcodes.hpp:9415
LIEF::assembly::riscv::OPCODE::CV_SDOTUP_SCI_B
@ CV_SDOTUP_SCI_B
Definition riscv/opcodes.hpp:12401
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF8
@ PseudoVASUB_VX_MF8
Definition riscv/opcodes.hpp:914
LIEF::assembly::riscv::OPCODE::C_FLWSP
@ C_FLWSP
Definition riscv/opcodes.hpp:12492
LIEF::assembly::riscv::OPCODE::CV_CMPLE_SC_H
@ CV_CMPLE_SC_H
Definition riscv/opcodes.hpp:12252
LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_MF2
@ PseudoVMNOR_MM_MF2
Definition riscv/opcodes.hpp:6893
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E16_MASK
@ PseudoVFSGNJN_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3152
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF2_M2
@ PseudoVLUXSEG3EI16_V_MF2_M2
Definition riscv/opcodes.hpp:5876
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF4_M2_MASK
@ PseudoVLOXSEG4EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:4677
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_MF2_MASK
@ PseudoVNMSUB_VX_MF2_MASK
Definition riscv/opcodes.hpp:7549
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M2
@ PseudoVSOXSEG2EI16_V_M1_M2
Definition riscv/opcodes.hpp:9157
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF4_MASK
@ PseudoVSLL_VX_MF4_MASK
Definition riscv/opcodes.hpp:8917
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M4_MASK
@ PseudoVBREV_V_M4_MASK
Definition riscv/opcodes.hpp:935
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_MF2_MF4
@ PseudoVLUXSEG8EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:6358
LIEF::assembly::riscv::OPCODE::C_FLD
@ C_FLD
Definition riscv/opcodes.hpp:12489
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M2_MASK
@ PseudoVWSLL_VX_M2_MASK
Definition riscv/opcodes.hpp:11710
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M8_MASK
@ PseudoVLUXEI32_V_M4_M8_MASK
Definition riscv/opcodes.hpp:5635
LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_MF8
@ PseudoVMOR_MM_MF8
Definition riscv/opcodes.hpp:6909
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF4_M1
@ PseudoVSUXSEG7EI8_V_MF4_M1
Definition riscv/opcodes.hpp:11241
LIEF::assembly::riscv::OPCODE::G_READCYCLECOUNTER
@ G_READCYCLECOUNTER
Definition riscv/opcodes.hpp:111
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M1_MASK
@ PseudoVLUXEI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:5621
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E32_M2_MASK
@ PseudoVRGATHEREI16_VV_M8_E32_M2_MASK
Definition riscv/opcodes.hpp:8377
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M4_MASK
@ PseudoVMFGE_VFPR32_M4_MASK
Definition riscv/opcodes.hpp:6657
LIEF::assembly::riscv::OPCODE::VLUXSEG7EI32_V
@ VLUXSEG7EI32_V
Definition riscv/opcodes.hpp:13477
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF4
@ PseudoVMULH_VX_MF4
Definition riscv/opcodes.hpp:7357
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B16
@ PseudoVMSIF_M_B16
Definition riscv/opcodes.hpp:7066
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF4
@ PseudoVSOXSEG5EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:9547
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M2_M1_MASK
@ PseudoVSOXSEG8EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9778
LIEF::assembly::riscv::OPCODE::PseudoVADD_VV_MF4
@ PseudoVADD_VV_MF4
Definition riscv/opcodes.hpp:622
LIEF::assembly::riscv::OPCODE::MOPR2
@ MOPR2
Definition riscv/opcodes.hpp:12872
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_M1
@ PseudoVLSEG5E32_V_M1
Definition riscv/opcodes.hpp:5254
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M2_E32_MASK
@ PseudoVFNMACC_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2630
LIEF::assembly::riscv::OPCODE::VSSEG5E32_V
@ VSSEG5E32_V
Definition riscv/opcodes.hpp:13715
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E16_V_MF2
@ PseudoVSSEG6E16_V_MF2
Definition riscv/opcodes.hpp:10105
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16_V_MF2
@ PseudoVLSEG4E16_V_MF2
Definition riscv/opcodes.hpp:5194
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M8_M2
@ PseudoVSOXSEG4EI32_V_M8_M2
Definition riscv/opcodes.hpp:9447
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M4
@ PseudoVLOXEI64_V_M8_M4
Definition riscv/opcodes.hpp:4286
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M2_E16_MASK
@ PseudoVFSGNJN_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3124
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M2_MASK
@ PseudoVSRA_VI_M2_MASK
Definition riscv/opcodes.hpp:9866
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF2_MASK
@ PseudoVMACC_VX_MF2_MASK
Definition riscv/opcodes.hpp:6425
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M2_M2_MASK
@ PseudoVSUXSEG4EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10944
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_MF2
@ PseudoVSOXSEG7EI16_V_M1_MF2
Definition riscv/opcodes.hpp:9673
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M1_E32_MASK
@ PseudoVFREDOSUM_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:2998
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E32_V_MF2
@ PseudoVSSSEG6E32_V_MF2
Definition riscv/opcodes.hpp:10367
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M2_E16
@ PseudoVFNCVTBF16_F_F_W_M2_E16
Definition riscv/opcodes.hpp:2421
LIEF::assembly::riscv::OPCODE::G_SDIVFIXSAT
@ G_SDIVFIXSAT
Definition riscv/opcodes.hpp:194
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF4
@ PseudoVANDN_VX_MF4
Definition riscv/opcodes.hpp:814
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_M1
@ PseudoVLUXSEG6EI8_V_MF8_M1
Definition riscv/opcodes.hpp:6234
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E32
@ PseudoVFNMACC_VV_M1_E32
Definition riscv/opcodes.hpp:2647
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M1_MASK
@ PseudoVSUXEI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10512
LIEF::assembly::riscv::OPCODE::FCVT_S_H_INX
@ FCVT_S_H_INX
Definition riscv/opcodes.hpp:12620
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF8_MASK
@ PseudoVLSEG5E8FF_V_MF8_MASK
Definition riscv/opcodes.hpp:5269
LIEF::assembly::riscv::OPCODE::HLV_H
@ HLV_H
Definition riscv/opcodes.hpp:12803
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF2_MASK
@ PseudoVSOXEI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9074
LIEF::assembly::riscv::OPCODE::PseudoVMORN_MM_M4
@ PseudoVMORN_MM_M4
Definition riscv/opcodes.hpp:6898
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M8
@ PseudoVCPOP_V_M8
Definition riscv/opcodes.hpp:1056
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M4_E64
@ PseudoVFNMSAC_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2761
LIEF::assembly::riscv::OPCODE::LHU
@ LHU
Definition riscv/opcodes.hpp:12840
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_MF2
@ PseudoVLUXSEG8EI32_V_M1_MF2
Definition riscv/opcodes.hpp:6344
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M2_M1
@ PseudoVSOXEI16_V_M2_M1
Definition riscv/opcodes.hpp:9007
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_MF2_M1
@ PseudoVSUXSEG8EI32_V_MF2_M1
Definition riscv/opcodes.hpp:11287
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF8
@ PseudoVRGATHER_VX_MF8
Definition riscv/opcodes.hpp:8504
LIEF::assembly::riscv::OPCODE::CV_SB_rr_inc
@ CV_SB_rr_inc
Definition riscv/opcodes.hpp:12392
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M2_MASK
@ PseudoVSEXT_VF2_M2_MASK
Definition riscv/opcodes.hpp:8752
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_M1
@ PseudoVLOXEI8_V_MF2_M1
Definition riscv/opcodes.hpp:4310
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M1_E16_MASK
@ PseudoVFNMSUB_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:2826
LIEF::assembly::riscv::OPCODE::TH_SRRI
@ TH_SRRI
Definition riscv/opcodes.hpp:13113
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E16_MASK
@ PseudoVFWREDOSUM_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:3920
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M1_MASK
@ PseudoVLSEG2E64_V_M1_MASK
Definition riscv/opcodes.hpp:5097
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_MF4
@ PseudoVROL_VX_MF4
Definition riscv/opcodes.hpp:8530
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_MF2_MASK
@ PseudoVLSSEG4E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5475
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M8_E64
@ PseudoVFNMSAC_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2763
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_MF2_MASK
@ PseudoVLSEG3E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5153
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_MF8_MASK
@ PseudoVMULHSU_VV_MF8_MASK
Definition riscv/opcodes.hpp:7290
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF8
@ PseudoVSLIDEUP_VX_MF8
Definition riscv/opcodes.hpp:8876
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M8_MASK
@ PseudoVSUXEI32_V_M8_M8_MASK
Definition riscv/opcodes.hpp:10574
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR64_M2_E64
@ PseudoVFNMACC_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2639
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_MF2
@ PseudoVMSEQ_VV_MF2
Definition riscv/opcodes.hpp:6974
LIEF::assembly::riscv::OPCODE::SSPUSH
@ SSPUSH
Definition riscv/opcodes.hpp:13013
LIEF::assembly::riscv::OPCODE::VLOXSEG8EI16_V
@ VLOXSEG8EI16_V
Definition riscv/opcodes.hpp:13360
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF8_E8
@ PseudoVFWCVT_F_XU_V_MF8_E8
Definition riscv/opcodes.hpp:3605
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M8_E8_MASK
@ PseudoVWREDSUM_VS_M8_E8_MASK
Definition riscv/opcodes.hpp:11670
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR64_M4_E64
@ PseudoVFSGNJ_VFPR64_M4_E64
Definition riscv/opcodes.hpp:3267
LIEF::assembly::riscv::OPCODE::CZERO_EQZ
@ CZERO_EQZ
Definition riscv/opcodes.hpp:12473
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M4_MASK
@ PseudoVNSRA_WX_M4_MASK
Definition riscv/opcodes.hpp:7583
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M2_MASK
@ PseudoTHVdotVMAQAU_VV_M2_MASK
Definition riscv/opcodes.hpp:483
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_M4_MASK
@ PseudoVMSLEU_VV_M4_MASK
Definition riscv/opcodes.hpp:7098
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M2_MASK
@ PseudoVSSRA_VV_M2_MASK
Definition riscv/opcodes.hpp:10180
LIEF::assembly::riscv::OPCODE::LB
@ LB
Definition riscv/opcodes.hpp:12832
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_M1
@ PseudoVAESEF_VS_M2_M1
Definition riscv/opcodes.hpp:702
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_MF2
@ PseudoVFCVT_RM_XU_F_V_MF2
Definition riscv/opcodes.hpp:1799
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M2_MASK
@ PseudoVROR_VX_M2_MASK
Definition riscv/opcodes.hpp:8565
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF2_E16_MASK
@ PseudoVFWMUL_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3810
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E64_MASK
@ PseudoVREDOR_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:7925
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_MF4_MASK
@ PseudoVLUXEI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:5619
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M4_MASK
@ PseudoVWSUB_VX_M4_MASK
Definition riscv/opcodes.hpp:11796
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M2_MASK
@ PseudoVFCVT_X_F_V_M2_MASK
Definition riscv/opcodes.hpp:1854
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E16
@ PseudoVREDXOR_VS_M1_E16
Definition riscv/opcodes.hpp:8008
LIEF::assembly::riscv::OPCODE::SM3P0
@ SM3P0
Definition riscv/opcodes.hpp:12991
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF8_MASK
@ PseudoVSRA_VX_MF8_MASK
Definition riscv/opcodes.hpp:9904
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF4_MF2
@ PseudoVLOXSEG8EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:4944
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M1
@ PseudoVLSEG2E64FF_V_M1
Definition riscv/opcodes.hpp:5090
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M8_E64
@ PseudoVFSGNJ_VV_M8_E64
Definition riscv/opcodes.hpp:3293
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF4_E16_MASK
@ PseudoVFWREDOSUM_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:3932
LIEF::assembly::riscv::OPCODE::VSSEG3E16_V
@ VSSEG3E16_V
Definition riscv/opcodes.hpp:13706
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M4_MASK
@ PseudoVSOXEI8_V_M4_M4_MASK
Definition riscv/opcodes.hpp:9126
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR16_M2_E16_MASK
@ PseudoVFWSUB_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3958
LIEF::assembly::riscv::OPCODE::VMSLE_VV
@ VMSLE_VV
Definition riscv/opcodes.hpp:13538
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF2
@ PseudoVLUXEI8_V_MF4_MF2
Definition riscv/opcodes.hpp:5714
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF4
@ PseudoVSUXSEG6EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:11111
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M2_E32_MASK
@ PseudoVFWADD_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3464
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_M1_MASK
@ PseudoVLOXSEG5EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4697
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M8_E16
@ PseudoVFNMADD_VFPR16_M8_E16
Definition riscv/opcodes.hpp:2681
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E8_MASK
@ PseudoVREDOR_VS_MF2_E8_MASK
Definition riscv/opcodes.hpp:7957
LIEF::assembly::riscv::OPCODE::CLMUL
@ CLMUL
Definition riscv/opcodes.hpp:12138
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_M4_MASK
@ PseudoVSOXSEG2EI32_V_M2_M4_MASK
Definition riscv/opcodes.hpp:9204
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E64_MASK
@ PseudoVREDMAX_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:7793
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF8
@ PseudoVLUXSEG4EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:5998
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF4_MASK
@ PseudoVMULH_VX_MF4_MASK
Definition riscv/opcodes.hpp:7358
LIEF::assembly::riscv::OPCODE::G_INTRINSIC_ROUNDEVEN
@ G_INTRINSIC_ROUNDEVEN
Definition riscv/opcodes.hpp:110
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M4
@ PseudoVWSLL_VI_M4
Definition riscv/opcodes.hpp:11687
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M8
@ PseudoVMUL_VX_M8
Definition riscv/opcodes.hpp:7381
LIEF::assembly::riscv::OPCODE::G_CONCAT_VECTORS
@ G_CONCAT_VECTORS
Definition riscv/opcodes.hpp:99
LIEF::assembly::riscv::OPCODE::AMOCAS_W
@ AMOCAS_W
Definition riscv/opcodes.hpp:11999
LIEF::assembly::riscv::OPCODE::SSRDP
@ SSRDP
Definition riscv/opcodes.hpp:13014
LIEF::assembly::riscv::OPCODE::G_SMULFIX
@ G_SMULFIX
Definition riscv/opcodes.hpp:188
LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M4_MASK
@ PseudoVSSE64_V_M4_MASK
Definition riscv/opcodes.hpp:9974
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M2
@ PseudoVSSSEG2E8_V_M2
Definition riscv/opcodes.hpp:10273
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M4_E32_MASK
@ PseudoVFWMACC_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3746
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M1_M1_MASK
@ PseudoVSUXSEG7EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11196
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E8_MASK
@ PseudoVREDXOR_VS_M8_E8_MASK
Definition riscv/opcodes.hpp:8039
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF2
@ PseudoVWSUBU_VX_MF2
Definition riscv/opcodes.hpp:11737
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF2_MASK
@ PseudoVSOXSEG4EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:9506
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M1
@ PseudoVWSUBU_VV_M1
Definition riscv/opcodes.hpp:11719
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M8_MASK
@ PseudoVXOR_VV_M8_MASK
Definition riscv/opcodes.hpp:11860
LIEF::assembly::riscv::OPCODE::VWMACCUS_VX
@ VWMACCUS_VX
Definition riscv/opcodes.hpp:13814
LIEF::assembly::riscv::OPCODE::AMOSWAP_B_AQ_RL
@ AMOSWAP_B_AQ_RL
Definition riscv/opcodes.hpp:12085
LIEF::assembly::riscv::OPCODE::AMOMIN_W_AQ
@ AMOMIN_W_AQ
Definition riscv/opcodes.hpp:12064
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M2
@ PseudoVLUXSEG3EI64_V_M8_M2
Definition riscv/opcodes.hpp:5942
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF8
@ PseudoVMSGTU_VI_MF8
Definition riscv/opcodes.hpp:7021
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR64VV_SE_M1
@ PseudoVC_FPR64VV_SE_M1
Definition riscv/opcodes.hpp:1111
LIEF::assembly::riscv::OPCODE::VLOXSEG6EI8_V
@ VLOXSEG6EI8_V
Definition riscv/opcodes.hpp:13355
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M2_E32_MASK
@ PseudoVFNCVT_RM_F_X_W_M2_E32_MASK
Definition riscv/opcodes.hpp:2514
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M4_MASK
@ PseudoVFSLIDE1UP_VFPR64_M4_MASK
Definition riscv/opcodes.hpp:3358
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_M1
@ PseudoVLOXSEG3EI8_V_MF8_M1
Definition riscv/opcodes.hpp:4572
LIEF::assembly::riscv::OPCODE::CV_MSU
@ CV_MSU
Definition riscv/opcodes.hpp:12370
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_M1
@ PseudoVSUXSEG8EI64_V_M2_M1
Definition riscv/opcodes.hpp:11303
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_M1_E32_MASK
@ PseudoVFWSUB_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3976
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF4
@ PseudoVWMACCSU_VX_MF4
Definition riscv/opcodes.hpp:11475
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M2_MASK
@ PseudoVLSEG3E32FF_V_M2_MASK
Definition riscv/opcodes.hpp:5145
LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M1
@ PseudoVLSE64_V_M1
Definition riscv/opcodes.hpp:5032
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_VV_M2
@ PseudoVWADDU_VV_M2
Definition riscv/opcodes.hpp:11337
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M1_MASK
@ PseudoVSADD_VI_M1_MASK
Definition riscv/opcodes.hpp:8647
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E16_MASK
@ PseudoVFWMUL_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3826
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M1
@ PseudoVSSUB_VX_M1
Definition riscv/opcodes.hpp:10461
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_MF8_MASK
@ PseudoVLUXSEG3EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:5925
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF2
@ PseudoVSOXSEG2EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:9279
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E16_MASK
@ PseudoVFDIV_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:1918
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF4_MASK
@ PseudoVLSSEG7E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5547
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M2
@ PseudoVLOXEI64_V_M4_M2
Definition riscv/opcodes.hpp:4276
LIEF::assembly::riscv::OPCODE::CV_CMPLE_H
@ CV_CMPLE_H
Definition riscv/opcodes.hpp:12248
LIEF::assembly::riscv::OPCODE::PseudoVMV_X_S
@ PseudoVMV_X_S
Definition riscv/opcodes.hpp:7411
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF2_MASK
@ PseudoVLE16FF_V_MF2_MASK
Definition riscv/opcodes.hpp:4092
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M4_MASK
@ PseudoTHVdotVMAQAU_VV_M4_MASK
Definition riscv/opcodes.hpp:485
LIEF::assembly::riscv::OPCODE::FCVT_WU_S_INX
@ FCVT_WU_S_INX
Definition riscv/opcodes.hpp:12635
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF8
@ PseudoVSOXSEG7EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:9689
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF4_M2_MASK
@ PseudoVLOXSEG3EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:4567
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF2_M1_MASK
@ PseudoVLOXSEG6EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4777
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF2_MASK
@ PseudoVNSRA_WV_MF2_MASK
Definition riscv/opcodes.hpp:7573
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK
@ PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK
Definition riscv/opcodes.hpp:8409
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF8_MASK
@ PseudoVANDN_VX_MF8_MASK
Definition riscv/opcodes.hpp:817
LIEF::assembly::riscv::OPCODE::PseudoFROUND_D_IN32X
@ PseudoFROUND_D_IN32X
Definition riscv/opcodes.hpp:375
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M1
@ PseudoVLUXSEG3EI32_V_M2_M1
Definition riscv/opcodes.hpp:5898
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M8_M2
@ PseudoVAESDF_VS_M8_M2
Definition riscv/opcodes.hpp:656
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M2
@ PseudoVSOXSEG4EI8_V_MF4_M2
Definition riscv/opcodes.hpp:9497
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M4_E32
@ PseudoVFWMACC_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3745
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M4_E8_MASK
@ PseudoVREDAND_VS_M4_E8_MASK
Definition riscv/opcodes.hpp:7723
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E16_MASK
@ PseudoVFRSQRT7_V_M1_E16_MASK
Definition riscv/opcodes.hpp:3062
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_MF4
@ PseudoVC_V_I_SE_MF4
Definition riscv/opcodes.hpp:1300
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M2
@ PseudoVWSUBU_VX_M2
Definition riscv/opcodes.hpp:11733
LIEF::assembly::riscv::OPCODE::MOPRR7
@ MOPRR7
Definition riscv/opcodes.hpp:12899
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_M2
@ PseudoVAESEM_VV_M2
Definition riscv/opcodes.hpp:752
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF8
@ PseudoVLOXSEG7EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:4868
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_MF2
@ PseudoVSOXSEG2EI16_V_M1_MF2
Definition riscv/opcodes.hpp:9161
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF8_E8
@ PseudoVFWCVT_F_X_V_MF8_E8
Definition riscv/opcodes.hpp:3635
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_MF4
@ PseudoVFMV_V_FPR16_MF4
Definition riscv/opcodes.hpp:2407
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M4_E32_MASK
@ PseudoVFREDOSUM_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:3010
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M4_E64
@ PseudoVFNMADD_VFPR64_M4_E64
Definition riscv/opcodes.hpp:2701
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M2_E32_MASK
@ PseudoVFSGNJX_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3196
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF8
@ PseudoVSRL_VV_MF8
Definition riscv/opcodes.hpp:9931
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF8
@ PseudoVWMACCUS_VX_MF8
Definition riscv/opcodes.hpp:11489
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_M1
@ PseudoVC_V_XVW_M1
Definition riscv/opcodes.hpp:1356
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M2
@ PseudoVMFNE_VV_M2
Definition riscv/opcodes.hpp:6816
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M2
@ PseudoVLOXEI8_V_M1_M2
Definition riscv/opcodes.hpp:4292
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M1
@ PseudoVLOXSEG4EI32_V_M1_M1
Definition riscv/opcodes.hpp:4608
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_MF2
@ PseudoVMUL_VV_MF2
Definition riscv/opcodes.hpp:7369
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF2_MASK
@ PseudoVSOXSEG2EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9196
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF8_E8
@ PseudoVREMU_VX_MF8_E8
Definition riscv/opcodes.hpp:8170
LIEF::assembly::riscv::OPCODE::VFWCVT_F_X_V
@ VFWCVT_F_X_V
Definition riscv/opcodes.hpp:13279
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_M1
@ PseudoVNSRL_WX_M1
Definition riscv/opcodes.hpp:7614
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E16
@ PseudoVREM_VX_M2_E16
Definition riscv/opcodes.hpp:8224
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_M2_E16
@ PseudoVFRDIV_VFPR16_M2_E16
Definition riscv/opcodes.hpp:2877
LIEF::assembly::riscv::OPCODE::PseudoCALLReg
@ PseudoCALLReg
Definition riscv/opcodes.hpp:339
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_MF2
@ PseudoVMADC_VXM_MF2
Definition riscv/opcodes.hpp:6462
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M2_E32_MASK
@ PseudoVFWNMSAC_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3900
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M4_E32
@ PseudoVFADD_VFPR32_M4_E32
Definition riscv/opcodes.hpp:1615
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M4_M1
@ PseudoVLOXSEG4EI32_V_M4_M1
Definition riscv/opcodes.hpp:4622
LIEF::assembly::riscv::OPCODE::G_FADD
@ G_FADD
Definition riscv/opcodes.hpp:196
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF4
@ PseudoVSSE8_V_MF4
Definition riscv/opcodes.hpp:9987
LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_2x8x2_M1
@ PseudoVQMACCUS_2x8x2_M1
Definition riscv/opcodes.hpp:7676
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M2
@ PseudoVOR_VI_M2
Definition riscv/opcodes.hpp:7628
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M2
@ PseudoVSEXT_VF2_M2
Definition riscv/opcodes.hpp:8751
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF2
@ PseudoVRGATHEREI16_VV_MF2_E32_MF2
Definition riscv/opcodes.hpp:8404
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_MF8_M1_MASK
@ PseudoVSUXSEG2EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:10788
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M2_MASK
@ PseudoVSUXSEG3EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10834
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF2_MASK
@ PseudoVASUB_VV_MF2_MASK
Definition riscv/opcodes.hpp:897
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M8
@ PseudoVRGATHEREI16_VV_M4_E64_M8
Definition riscv/opcodes.hpp:8360
LIEF::assembly::riscv::OPCODE::FSGNJX_S_INX
@ FSGNJX_S_INX
Definition riscv/opcodes.hpp:12770
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF2_MF2_MASK
@ PseudoVLUXSEG8EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6331
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_M1
@ PseudoVRELOAD4_M1
Definition riscv/opcodes.hpp:8063
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64VV_M1
@ PseudoVC_V_FPR64VV_M1
Definition riscv/opcodes.hpp:1232
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M8
@ PseudoVSSE16_V_M8
Definition riscv/opcodes.hpp:9953
LIEF::assembly::riscv::OPCODE::C_ADDI
@ C_ADDI
Definition riscv/opcodes.hpp:12476
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_M1
@ PseudoVLSSEG6E16_V_M1
Definition riscv/opcodes.hpp:5510
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_MF8
@ PseudoVSUXSEG3EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:10821
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E64_V_M1
@ PseudoVSSSEG6E64_V_M1
Definition riscv/opcodes.hpp:10369
LIEF::assembly::riscv::OPCODE::VREM_VX
@ VREM_VX
Definition riscv/opcodes.hpp:13605
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M4_E16_MASK
@ PseudoVFMIN_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:2175
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M2
@ PseudoVLUXSEG4EI8_V_M1_M2
Definition riscv/opcodes.hpp:6056
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_M1
@ PseudoVSOXSEG2EI8_V_MF4_M1
Definition riscv/opcodes.hpp:9275
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_MF8_MASK
@ PseudoVSUXSEG7EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:11214
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_MF2
@ PseudoVSOXSEG6EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:9659
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF2_E32
@ PseudoVFCVT_F_XU_V_MF2_E32
Definition riscv/opcodes.hpp:1697
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E64FF_V_M1_MASK
@ PseudoVLSEG3E64FF_V_M1_MASK
Definition riscv/opcodes.hpp:5155
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_M1
@ PseudoVSUXSEG5EI64_V_M1_M1
Definition riscv/opcodes.hpp:11055
LIEF::assembly::riscv::OPCODE::VXOR_VV
@ VXOR_VV
Definition riscv/opcodes.hpp:13839
LIEF::assembly::riscv::OPCODE::REG_SEQUENCE
@ REG_SEQUENCE
Definition riscv/opcodes.hpp:42
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_MF4_MASK
@ PseudoVSOXSEG8EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9768
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF8
@ PseudoVSOXSEG3EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:9345
LIEF::assembly::riscv::OPCODE::CV_AVG_SCI_B
@ CV_AVG_SCI_B
Definition riscv/opcodes.hpp:12195
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_M1_MASK
@ PseudoVSSSEG5E8_V_M1_MASK
Definition riscv/opcodes.hpp:10352
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VVM_MF2
@ PseudoVSBC_VVM_MF2
Definition riscv/opcodes.hpp:8692
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR32_M2_E32
@ PseudoVFSGNJX_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3195
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32FF_V_M1_MASK
@ PseudoVLSEG8E32FF_V_M1_MASK
Definition riscv/opcodes.hpp:5371
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_M4_E16
@ PseudoVFSGNJN_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3125
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M8_M1
@ PseudoVLOXSEG8EI64_V_M8_M1
Definition riscv/opcodes.hpp:4988
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF2_MASK
@ PseudoVSUXSEG7EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:11250
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_M4_E32
@ PseudoVFSUB_VFPR32_M4_E32
Definition riscv/opcodes.hpp:3407
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_M1_MASK
@ PseudoVSOXSEG8EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9784
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_MF4_MASK
@ PseudoVAADDU_VX_MF4_MASK
Definition riscv/opcodes.hpp:546
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E8_MASK
@ PseudoVREDMAXU_VS_MF4_E8_MASK
Definition riscv/opcodes.hpp:7785
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E16_MASK
@ PseudoVREDSUM_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:7989
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_MF8_MF2_MASK
@ PseudoVLOXSEG4EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:4685
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_M1_E64_MASK
@ PseudoVFREDMAX_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:2940
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_M2_E32
@ PseudoVFDIV_VFPR32_M2_E32
Definition riscv/opcodes.hpp:1877
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF4
@ PseudoVSADD_VV_MF4
Definition riscv/opcodes.hpp:8670
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M2
@ PseudoVMERGE_VIM_M2
Definition riscv/opcodes.hpp:6578
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M4_M2
@ PseudoVSUXSEG4EI16_V_M4_M2
Definition riscv/opcodes.hpp:10915
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M2
@ PseudoVRGATHEREI16_VV_M2_E64_M2
Definition riscv/opcodes.hpp:8324
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_M1
@ PseudoVSUXSEG3EI8_V_MF2_M1
Definition riscv/opcodes.hpp:10883
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_M1_E32
@ PseudoVFWADD_VV_M1_E32
Definition riscv/opcodes.hpp:3471
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VXM_M2
@ PseudoVMSBC_VXM_M2
Definition riscv/opcodes.hpp:6925
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M1_E8
@ PseudoVRGATHER_VV_M1_E8
Definition riscv/opcodes.hpp:8454
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M4_M1_MASK
@ PseudoVLUXSEG8EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:6353
LIEF::assembly::riscv::OPCODE::BCLR
@ BCLR
Definition riscv/opcodes.hpp:12119
LIEF::assembly::riscv::OPCODE::PseudoVMNOR_MM_M2
@ PseudoVMNOR_MM_M2
Definition riscv/opcodes.hpp:6890
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_M8
@ PseudoVMSLTU_VX_M8
Definition riscv/opcodes.hpp:7184
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_M8
@ PseudoVC_V_I_M8
Definition riscv/opcodes.hpp:1291
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M2_E32
@ PseudoVFWMUL_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3815
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VS_M8_MF2
@ PseudoVAESDM_VS_M8_MF2
Definition riscv/opcodes.hpp:687
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_MF2
@ PseudoVLOXSEG2EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:4358
LIEF::assembly::riscv::OPCODE::PseudoVSM4K_VI_M1
@ PseudoVSM4K_VI_M1
Definition riscv/opcodes.hpp:8930
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_M4_E16
@ PseudoVFWMSAC_VV_M4_E16
Definition riscv/opcodes.hpp:3793
LIEF::assembly::riscv::OPCODE::FLEQ_H
@ FLEQ_H
Definition riscv/opcodes.hpp:12662
LIEF::assembly::riscv::OPCODE::RORIW
@ RORIW
Definition riscv/opcodes.hpp:12934
LIEF::assembly::riscv::OPCODE::FNMADD_D
@ FNMADD_D
Definition riscv/opcodes.hpp:12736
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_M8_MASK
@ PseudoVOR_VI_M8_MASK
Definition riscv/opcodes.hpp:7633
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF4_MASK
@ PseudoVSUXSEG6EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:11120
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M4_MASK
@ PseudoVCLZ_V_M4_MASK
Definition riscv/opcodes.hpp:1005
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M4_MASK
@ PseudoVLOXSEG2EI16_V_M2_M4_MASK
Definition riscv/opcodes.hpp:4347
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M2
@ PseudoVWSUB_WV_M2
Definition riscv/opcodes.hpp:11807
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_MF2_MASK
@ PseudoVSOXSEG4EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9500
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_M1
@ PseudoVLSEG7E8_V_M1
Definition riscv/opcodes.hpp:5350
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF8_M1
@ PseudoVLUXSEG8EI8_V_MF8_M1
Definition riscv/opcodes.hpp:6394
LIEF::assembly::riscv::OPCODE::G_BITREVERSE
@ G_BITREVERSE
Definition riscv/opcodes.hpp:261
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M2
@ PseudoVSSRL_VX_M2
Definition riscv/opcodes.hpp:10235
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M1_M4
@ PseudoVSUXEI8_V_M1_M4
Definition riscv/opcodes.hpp:10619
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_MF2_MASK
@ PseudoVSOXSEG2EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9162
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M1_MASK
@ PseudoVNMSAC_VV_M1_MASK
Definition riscv/opcodes.hpp:7499
LIEF::assembly::riscv::OPCODE::G_SPLAT_VECTOR_SPLIT_I64_VL
@ G_SPLAT_VECTOR_SPLIT_I64_VL
Definition riscv/opcodes.hpp:324
LIEF::assembly::riscv::OPCODE::CV_LW_ri_inc
@ CV_LW_ri_inc
Definition riscv/opcodes.hpp:12330
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M2_E32
@ PseudoVFNCVT_F_XU_W_M2_E32
Definition riscv/opcodes.hpp:2459
LIEF::assembly::riscv::OPCODE::PseudoLLA
@ PseudoLLA
Definition riscv/opcodes.hpp:397
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M2_E16_MASK
@ PseudoVFMADD_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:2034
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR16_M1_E16_MASK
@ PseudoVFNMSUB_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:2796
LIEF::assembly::riscv::OPCODE::CV_SUBURN
@ CV_SUBURN
Definition riscv/opcodes.hpp:12453
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF4_MASK
@ PseudoVSUXSEG3EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:10848
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF8_MF2
@ PseudoVLOXSEG6EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:4844
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF2_MASK
@ PseudoVSSSEG7E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10394
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M2_MF4
@ PseudoVSM4R_VS_M2_MF4
Definition riscv/opcodes.hpp:8942
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E64
@ PseudoVREDOR_VS_M1_E64
Definition riscv/opcodes.hpp:7924
LIEF::assembly::riscv::OPCODE::FCVT_LU_D
@ FCVT_LU_D
Definition riscv/opcodes.hpp:12603
LIEF::assembly::riscv::OPCODE::CV_ADD_DIV2
@ CV_ADD_DIV2
Definition riscv/opcodes.hpp:12173
LIEF::assembly::riscv::OPCODE::VSSUB_VX
@ VSSUB_VX
Definition riscv/opcodes.hpp:13767
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M2_MASK
@ PseudoVAADDU_VX_M2_MASK
Definition riscv/opcodes.hpp:538
LIEF::assembly::riscv::OPCODE::SRAI
@ SRAI
Definition riscv/opcodes.hpp:12996
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF4
@ PseudoVSOXSEG4EI32_V_M1_MF4
Definition riscv/opcodes.hpp:9435
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_MF2_E32
@ PseudoVREMU_VV_MF2_E32
Definition riscv/opcodes.hpp:8118
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_M8
@ PseudoVC_V_VVV_M8
Definition riscv/opcodes.hpp:1305
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF8_MASK
@ PseudoVSUXSEG7EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:11194
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E16
@ PseudoVREDXOR_VS_M2_E16
Definition riscv/opcodes.hpp:8016
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_M2
@ PseudoVNCLIPU_WI_M2
Definition riscv/opcodes.hpp:7428
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M4_MASK
@ PseudoVFWCVT_XU_F_V_M4_MASK
Definition riscv/opcodes.hpp:3682
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_M1
@ PseudoVSOXSEG5EI16_V_MF2_M1
Definition riscv/opcodes.hpp:9517
LIEF::assembly::riscv::OPCODE::MOPR22
@ MOPR22
Definition riscv/opcodes.hpp:12875
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E32
@ PseudoVCOMPRESS_VM_M2_E32
Definition riscv/opcodes.hpp:1019
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M2
@ PseudoVSOXEI8_V_MF4_M2
Definition riscv/opcodes.hpp:9141
LIEF::assembly::riscv::OPCODE::CV_SRA_B
@ CV_SRA_B
Definition riscv/opcodes.hpp:12431
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF8_MASK
@ PseudoVLUXSEG5EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:6129
LIEF::assembly::riscv::OPCODE::WriteFRMImm
@ WriteFRMImm
Definition riscv/opcodes.hpp:11929
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M8_MASK
@ PseudoVAADDU_VX_M8_MASK
Definition riscv/opcodes.hpp:542
LIEF::assembly::riscv::OPCODE::VMADD_VX
@ VMADD_VX
Definition riscv/opcodes.hpp:13493
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_MF8
@ PseudoVSM4R_VS_M4_MF8
Definition riscv/opcodes.hpp:8949
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_MF2_MASK
@ PseudoVSSUB_VV_MF2_MASK
Definition riscv/opcodes.hpp:10456
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E8_V_M2
@ PseudoVSSEG2E8_V_M2
Definition riscv/opcodes.hpp:10017
LIEF::assembly::riscv::OPCODE::FROUND_S
@ FROUND_S
Definition riscv/opcodes.hpp:12755
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_SE_M4
@ PseudoVC_V_FPR32VW_SE_M4
Definition riscv/opcodes.hpp:1219
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M1
@ PseudoVMADC_VVM_M1
Definition riscv/opcodes.hpp:6444
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E16
@ PseudoVFREDUSUM_VS_M8_E16
Definition riscv/opcodes.hpp:3043
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_MF8_MASK
@ PseudoVCLZ_V_MF8_MASK
Definition riscv/opcodes.hpp:1013
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M2_E16
@ PseudoVFWCVTBF16_F_F_V_M2_E16
Definition riscv/opcodes.hpp:3545
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF4_E16
@ PseudoVFMACC_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:1947
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M2
@ PseudoVFSLIDE1DOWN_VFPR32_M2
Definition riscv/opcodes.hpp:3315
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_M2
@ PseudoVRELOAD2_M2
Definition riscv/opcodes.hpp:8053
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M4_MASK
@ PseudoVFWCVT_RM_X_F_V_M4_MASK
Definition riscv/opcodes.hpp:3652
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M8
@ PseudoVSRL_VX_M8
Definition riscv/opcodes.hpp:9939
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M8_E32_MASK
@ PseudoVDIVU_VX_M8_E32_MASK
Definition riscv/opcodes.hpp:1494
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_M1
@ PseudoVLSEG3E16FF_V_M1
Definition riscv/opcodes.hpp:5126
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M4_M2_MASK
@ PseudoVSUXSEG2EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10714
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E8
@ PseudoVDIV_VX_MF4_E8
Definition riscv/opcodes.hpp:1595
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M1_MASK
@ PseudoVSOXSEG3EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9328
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E16_MASK
@ PseudoVFMACC_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:1974
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M2
@ PseudoVMULHSU_VX_M2
Definition riscv/opcodes.hpp:7293
LIEF::assembly::riscv::OPCODE::FCVT_WU_S
@ FCVT_WU_S
Definition riscv/opcodes.hpp:12634
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M1_E16_MASK
@ PseudoVFSGNJ_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3242
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E8
@ PseudoVREMU_VX_MF4_E8
Definition riscv/opcodes.hpp:8168
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_MF2_MASK
@ PseudoVLSEG8E16FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5361
LIEF::assembly::riscv::OPCODE::FSQRT_H
@ FSQRT_H
Definition riscv/opcodes.hpp:12782
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E32
@ PseudoVFMAX_VV_MF2_E32
Definition riscv/opcodes.hpp:2113
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF4
@ PseudoVSUXEI64_V_M1_MF4
Definition riscv/opcodes.hpp:10587
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M8_E16_MASK
@ PseudoVFMAX_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2064
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF8
@ PseudoVMAX_VX_MF8
Definition riscv/opcodes.hpp:6568
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF2
@ PseudoVSSRA_VX_MF2
Definition riscv/opcodes.hpp:10199
LIEF::assembly::riscv::OPCODE::CV_MINU_H
@ CV_MINU_H
Definition riscv/opcodes.hpp:12359
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M4_MASK
@ PseudoVMFLE_VFPR16_M4_MASK
Definition riscv/opcodes.hpp:6705
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E16
@ PseudoVFMACC_VV_M4_E16
Definition riscv/opcodes.hpp:1979
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_MF2_MASK
@ PseudoVSSSEG8E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10408
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M2_MASK
@ PseudoVOR_VX_M2_MASK
Definition riscv/opcodes.hpp:7657
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF8
@ PseudoVLUXSEG6EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:6200
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M4_MASK
@ PseudoVMFLT_VFPR32_M4_MASK
Definition riscv/opcodes.hpp:6759
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M2
@ PseudoVBREV_V_M2
Definition riscv/opcodes.hpp:932
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E32
@ PseudoVDIVU_VV_M4_E32
Definition riscv/opcodes.hpp:1441
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M1
@ PseudoVLSEG2E32FF_V_M1
Definition riscv/opcodes.hpp:5074
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_MF2_E32
@ PseudoVFWADD_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3467
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_MAX
@ G_ATOMICRMW_MAX
Definition riscv/opcodes.hpp:130
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF4
@ PseudoVSSEG3E8_V_MF4
Definition riscv/opcodes.hpp:10051
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_MF4_E16
@ PseudoVFNMSUB_VV_MF4_E16
Definition riscv/opcodes.hpp:2853
LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_MF2
@ PseudoVSPILL8_MF2
Definition riscv/opcodes.hpp:9860
LIEF::assembly::riscv::OPCODE::G_BITCAST
@ G_BITCAST
Definition riscv/opcodes.hpp:102
LIEF::assembly::riscv::OPCODE::MIN
@ MIN
Definition riscv/opcodes.hpp:12858
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M8_M1_MASK
@ PseudoVSOXSEG4EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:9480
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_AND
@ G_ATOMICRMW_AND
Definition riscv/opcodes.hpp:126
LIEF::assembly::riscv::OPCODE::VFSGNJ_VV
@ VFSGNJ_VV
Definition riscv/opcodes.hpp:13266
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M8
@ PseudoVSUB_VV_M8
Definition riscv/opcodes.hpp:10481
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_MF2_E16
@ PseudoVFNMSAC_VV_MF2_E16
Definition riscv/opcodes.hpp:2789
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF2_MASK
@ PseudoVLUXSEG7EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6277
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_MF4_MASK
@ PseudoVSOXSEG2EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:9198
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_MF2
@ PseudoVSUXSEG2EI64_V_M4_MF2
Definition riscv/opcodes.hpp:10751
LIEF::assembly::riscv::OPCODE::VMSNE_VI
@ VMSNE_VI
Definition riscv/opcodes.hpp:13544
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32_MASK_TIED
@ PseudoVFWADD_WV_MF2_E32_MASK_TIED
Definition riscv/opcodes.hpp:3535
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF8
@ PseudoVADD_VI_MF8
Definition riscv/opcodes.hpp:610
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M2_MF2_MASK
@ PseudoVSUXSEG8EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:11284
LIEF::assembly::riscv::OPCODE::G_INTRINSIC_TRUNC
@ G_INTRINSIC_TRUNC
Definition riscv/opcodes.hpp:106
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_MF8
@ PseudoVC_V_IVW_SE_MF8
Definition riscv/opcodes.hpp:1273
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M4_MASK
@ PseudoVMAX_VV_M4_MASK
Definition riscv/opcodes.hpp:6547
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF4
@ PseudoVFNRCLIP_X_F_QF_MF4
Definition riscv/opcodes.hpp:2871
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF2_E16
@ PseudoVFMAX_VV_MF2_E16
Definition riscv/opcodes.hpp:2111
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E64
@ PseudoVFMAX_VV_M8_E64
Definition riscv/opcodes.hpp:2109
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M8
@ PseudoVMSEQ_VV_M8
Definition riscv/opcodes.hpp:6972
LIEF::assembly::riscv::OPCODE::CLMULH
@ CLMULH
Definition riscv/opcodes.hpp:12139
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF8_E8_MASK
@ PseudoVRGATHER_VV_MF8_E8_MASK
Definition riscv/opcodes.hpp:8491
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_MF4
@ PseudoVC_V_IVW_SE_MF4
Definition riscv/opcodes.hpp:1272
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_MF8_MASK
@ PseudoVSSRL_VX_MF8_MASK
Definition riscv/opcodes.hpp:10246
LIEF::assembly::riscv::OPCODE::SINVAL_VMA
@ SINVAL_VMA
Definition riscv/opcodes.hpp:12981
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_M4_M1_MASK
@ PseudoVLOXSEG2EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4387
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E32
@ PseudoVFMUL_VV_M1_E32
Definition riscv/opcodes.hpp:2344
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M4
@ PseudoVSRA_VV_M4
Definition riscv/opcodes.hpp:9881
LIEF::assembly::riscv::OPCODE::VSOXSEG2EI32_V
@ VSOXSEG2EI32_V
Definition riscv/opcodes.hpp:13665
LIEF::assembly::riscv::OPCODE::VSETVLI
@ VSETVLI
Definition riscv/opcodes.hpp:13636
LIEF::assembly::riscv::OPCODE::VLUXSEG6EI32_V
@ VLUXSEG6EI32_V
Definition riscv/opcodes.hpp:13473
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF2
@ PseudoVSOXSEG8EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:9785
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M1
@ PseudoVSOXEI8_V_M1_M1
Definition riscv/opcodes.hpp:9111
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR32_M8
@ PseudoVMFGE_VFPR32_M8
Definition riscv/opcodes.hpp:6658
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E16
@ PseudoVREDSUM_VS_M4_E16
Definition riscv/opcodes.hpp:7980
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_MF2_MASK
@ PseudoVSSEG2E16_V_MF2_MASK
Definition riscv/opcodes.hpp:9998
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF4_MASK
@ PseudoVASUB_VV_MF4_MASK
Definition riscv/opcodes.hpp:899
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M4_E64_MASK
@ PseudoVFDIV_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:1890
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M2_M2
@ PseudoVSUXSEG3EI64_V_M2_M2
Definition riscv/opcodes.hpp:10861
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E32
@ PseudoVFCVT_RM_F_X_V_M2_E32
Definition riscv/opcodes.hpp:1769
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF2_MASK
@ PseudoVCLMULH_VV_MF2_MASK
Definition riscv/opcodes.hpp:953
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E32
@ PseudoVFSQRT_V_M2_E32
Definition riscv/opcodes.hpp:3369
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR64V_M2
@ PseudoVC_V_FPR64V_M2
Definition riscv/opcodes.hpp:1241
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E64
@ PseudoVFNMADD_VV_M2_E64
Definition riscv/opcodes.hpp:2715
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF4
@ PseudoVRGATHEREI16_VV_MF4_E8_MF4
Definition riscv/opcodes.hpp:8426
LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_MF2
@ PseudoVC_IV_SE_MF2
Definition riscv/opcodes.hpp:1136
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF8
@ PseudoVRGATHEREI16_VV_MF4_E8_MF8
Definition riscv/opcodes.hpp:8428
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M2_E16
@ PseudoVFCVT_RM_F_X_V_M2_E16
Definition riscv/opcodes.hpp:1767
LIEF::assembly::riscv::OPCODE::VAADD_VX
@ VAADD_VX
Definition riscv/opcodes.hpp:13134
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M1_M1
@ PseudoVLUXSEG3EI64_V_M1_M1
Definition riscv/opcodes.hpp:5918
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF8_MASK
@ PseudoVMULH_VX_MF8_MASK
Definition riscv/opcodes.hpp:7360
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_M1
@ PseudoVSSEG7E16_V_M1
Definition riscv/opcodes.hpp:10123
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF4
@ PseudoVLOXEI64_V_M2_MF4
Definition riscv/opcodes.hpp:4272
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_MF8
@ PseudoVNMSAC_VV_MF8
Definition riscv/opcodes.hpp:7510
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_M1
@ PseudoVSOXSEG2EI32_V_MF2_M1
Definition riscv/opcodes.hpp:9217
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF4
@ PseudoVMSGTU_VX_MF4
Definition riscv/opcodes.hpp:7033
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_M1_MASK
@ PseudoVSUXSEG6EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11158
LIEF::assembly::riscv::OPCODE::VGHSH_VV
@ VGHSH_VV
Definition riscv/opcodes.hpp:13303
LIEF::assembly::riscv::OPCODE::AMOCAS_D_RV64_RL
@ AMOCAS_D_RV64_RL
Definition riscv/opcodes.hpp:11990
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF2_E16_MASK
@ PseudoVFNCVT_F_XU_W_MF2_E16_MASK
Definition riscv/opcodes.hpp:2466
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_MF2
@ PseudoVSOXSEG3EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:9389
LIEF::assembly::riscv::OPCODE::VFMSUB_VV
@ VFMSUB_VV
Definition riscv/opcodes.hpp:13228
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E16
@ PseudoVFWCVT_F_XU_V_M1_E16
Definition riscv/opcodes.hpp:3577
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M1
@ PseudoVLOXSEG3EI16_V_M1_M1
Definition riscv/opcodes.hpp:4470
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WX_M1
@ PseudoVWSUBU_WX_M1
Definition riscv/opcodes.hpp:11767
LIEF::assembly::riscv::OPCODE::FMAX_D
@ FMAX_D
Definition riscv/opcodes.hpp:12696
LIEF::assembly::riscv::OPCODE::FSUB_D_INX
@ FSUB_D_INX
Definition riscv/opcodes.hpp:12788
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M2
@ PseudoVSE8_V_M2
Definition riscv/opcodes.hpp:8734
LIEF::assembly::riscv::OPCODE::VCTZ_V
@ VCTZ_V
Definition riscv/opcodes.hpp:13171
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF8
@ PseudoVSOXSEG4EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:9509
LIEF::assembly::riscv::OPCODE::CV_ADD_H
@ CV_ADD_H
Definition riscv/opcodes.hpp:12176
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E32_MASK
@ PseudoVFRSQRT7_V_M2_E32_MASK
Definition riscv/opcodes.hpp:3070
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_MF2_MASK
@ PseudoVMADD_VX_MF2_MASK
Definition riscv/opcodes.hpp:6495
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M4
@ PseudoVMSNE_VX_M4
Definition riscv/opcodes.hpp:7253
LIEF::assembly::riscv::OPCODE::VLSE32_V
@ VLSE32_V
Definition riscv/opcodes.hpp:13365
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M2_MF2_MASK
@ PseudoVSOXSEG3EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9360
LIEF::assembly::riscv::OPCODE::VLSEG6E8FF_V
@ VLSEG6E8FF_V
Definition riscv/opcodes.hpp:13406
LIEF::assembly::riscv::OPCODE::CV_MAX_SCI_B
@ CV_MAX_SCI_B
Definition riscv/opcodes.hpp:12352
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M1_MASK
@ PseudoVFSLIDE1DOWN_VFPR32_M1_MASK
Definition riscv/opcodes.hpp:3314
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M4
@ PseudoVASUB_VV_M4
Definition riscv/opcodes.hpp:892
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_MF4
@ PseudoVRELOAD4_MF4
Definition riscv/opcodes.hpp:8066
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF4
@ PseudoVSOXEI32_V_M1_MF4
Definition riscv/opcodes.hpp:9047
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M4
@ PseudoVFWCVT_X_F_V_M4
Definition riscv/opcodes.hpp:3691
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M2_E64
@ PseudoVFREDOSUM_VS_M2_E64
Definition riscv/opcodes.hpp:3005
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF2_M1
@ PseudoVSUXSEG8EI8_V_MF2_M1
Definition riscv/opcodes.hpp:11317
LIEF::assembly::riscv::OPCODE::CBO_INVAL
@ CBO_INVAL
Definition riscv/opcodes.hpp:12136
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF4_E16_MASK
@ PseudoVFMADD_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:2008
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_M2
@ PseudoVAESDF_VS_M4_M2
Definition riscv/opcodes.hpp:650
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_MF2_MASK
@ PseudoVLOXSEG8EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4953
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M4_M4_MASK
@ PseudoVLUXSEG2EI8_V_M4_M4_MASK
Definition riscv/opcodes.hpp:5837
LIEF::assembly::riscv::OPCODE::G_FMINNUM
@ G_FMINNUM
Definition riscv/opcodes.hpp:224
LIEF::assembly::riscv::OPCODE::FCVT_S_H
@ FCVT_S_H
Definition riscv/opcodes.hpp:12619
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_MF2
@ PseudoVFCVT_RTZ_XU_F_V_MF2
Definition riscv/opcodes.hpp:1823
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M4
@ PseudoVCTZ_V_M4
Definition riscv/opcodes.hpp:1068
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF4_MASK
@ PseudoVSOXSEG8EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:9804
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF8_MASK
@ PseudoVSLIDEDOWN_VI_MF8_MASK
Definition riscv/opcodes.hpp:8835
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M1_E32_MASK
@ PseudoVREDMAXU_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:7747
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M8_E16_MASK
@ PseudoVFMACC_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:1944
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI64_V_M4_MF2_MASK
@ PseudoVSOXSEG6EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:9648
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M8_MASK
@ PseudoVASUB_VV_M8_MASK
Definition riscv/opcodes.hpp:895
LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M8_MASK
@ PseudoVFROUND_NOEXCEPT_V_M8_MASK
Definition riscv/opcodes.hpp:3058
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M2_MASK
@ PseudoVMFLE_VFPR64_M2_MASK
Definition riscv/opcodes.hpp:6725
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E32
@ PseudoVFWREDUSUM_VS_M8_E32
Definition riscv/opcodes.hpp:3947
LIEF::assembly::riscv::OPCODE::VLUXSEG2EI32_V
@ VLUXSEG2EI32_V
Definition riscv/opcodes.hpp:13457
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E32
@ PseudoVFMUL_VV_M4_E32
Definition riscv/opcodes.hpp:2356
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E32_MASK
@ PseudoVFMSUB_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:2297
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD7_M1
@ PseudoVRELOAD7_M1
Definition riscv/opcodes.hpp:8076
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF4_E16
@ PseudoVFSQRT_V_MF4_E16
Definition riscv/opcodes.hpp:3389
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M8_M4
@ PseudoVLUXSEG2EI16_V_M8_M4
Definition riscv/opcodes.hpp:5744
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M4_E64_MASK
@ PseudoVFNMADD_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2702
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M1_MF4_MASK
@ PseudoVSUXSEG8EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:11300
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M4_M1_MASK
@ PseudoVLOXSEG5EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4721
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF2_MASK
@ PseudoVSSE8_V_MF2_MASK
Definition riscv/opcodes.hpp:9986
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_M1
@ PseudoVRELOAD3_M1
Definition riscv/opcodes.hpp:8058
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_MF2
@ PseudoVLOXSEG8EI64_V_M2_MF2
Definition riscv/opcodes.hpp:4980
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_M1_MASK
@ PseudoVLUXSEG5EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6089
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF4
@ PseudoVLUXSEG8EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:6338
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M1_MF8
@ PseudoVLOXSEG5EI64_V_M1_MF8
Definition riscv/opcodes.hpp:4736
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_M2_MASK
@ PseudoVSE16_V_M2_MASK
Definition riscv/opcodes.hpp:8705
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M2_MASK
@ PseudoVROL_VV_M2_MASK
Definition riscv/opcodes.hpp:8509
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF8_MASK
@ PseudoVSUXSEG5EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:11094
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M1
@ PseudoVSSUBU_VX_M1
Definition riscv/opcodes.hpp:10433
LIEF::assembly::riscv::OPCODE::AMOMAX_H_RL
@ AMOMAX_H_RL
Definition riscv/opcodes.hpp:12030
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E16
@ PseudoVREDSUM_VS_MF4_E16
Definition riscv/opcodes.hpp:8002
LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_M4
@ PseudoVC_VVV_SE_M4
Definition riscv/opcodes.hpp:1148
LIEF::assembly::riscv::OPCODE::VNCLIPU_WI
@ VNCLIPU_WI
Definition riscv/opcodes.hpp:13567
LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M8
@ PseudoVLE64_V_M8
Definition riscv/opcodes.hpp:4141
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M2
@ PseudoVLUXSEG2EI32_V_M2_M2
Definition riscv/opcodes.hpp:5772
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E64
@ PseudoVCOMPRESS_VM_M8_E64
Definition riscv/opcodes.hpp:1028
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_MF8_MF4
@ PseudoVSOXSEG7EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:9747
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M4
@ PseudoVLUXEI32_V_M4_M4
Definition riscv/opcodes.hpp:5632
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF4
@ PseudoVLUXSEG3EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:5886
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_SE_M4
@ PseudoVC_V_FPR16VW_SE_M4
Definition riscv/opcodes.hpp:1186
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M4_E32_MASK
@ PseudoVFREC7_V_M4_E32_MASK
Definition riscv/opcodes.hpp:2920
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M4
@ PseudoVSSRA_VI_M4
Definition riscv/opcodes.hpp:10167
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF2
@ PseudoVLSSEG2E8_V_MF2
Definition riscv/opcodes.hpp:5428
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B2_MASK
@ PseudoVMSOF_M_B2_MASK
Definition riscv/opcodes.hpp:7268
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M8
@ PseudoVRGATHEREI16_VV_M4_E8_M8
Definition riscv/opcodes.hpp:8368
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M1_MASK
@ PseudoVMULHU_VX_M1_MASK
Definition riscv/opcodes.hpp:7320
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M2
@ PseudoVWADD_VX_M2
Definition riscv/opcodes.hpp:11409
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M2_MASK
@ PseudoVMUL_VV_M2_MASK
Definition riscv/opcodes.hpp:7364
LIEF::assembly::riscv::OPCODE::PseudoCCSRLI
@ PseudoCCSRLI
Definition riscv/opcodes.hpp:361
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_MF2_E32_MASK
@ PseudoVFSGNJN_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3142
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF2
@ PseudoVASUBU_VX_MF2
Definition riscv/opcodes.hpp:882
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF4_MASK
@ PseudoVSOXSEG6EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9602
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M2
@ PseudoVLSSEG4E32_V_M2
Definition riscv/opcodes.hpp:5472
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VX_MF2_MASK
@ PseudoVWMACCU_VX_MF2_MASK
Definition riscv/opcodes.hpp:11510
LIEF::assembly::riscv::OPCODE::PseudoVSPILL8_MF4
@ PseudoVSPILL8_MF4
Definition riscv/opcodes.hpp:9861
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M1_MASK
@ PseudoVLUXSEG4EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:6045
LIEF::assembly::riscv::OPCODE::PseudoVFROUND_NOEXCEPT_V_M2_MASK
@ PseudoVFROUND_NOEXCEPT_V_M2_MASK
Definition riscv/opcodes.hpp:3056
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_M8
@ PseudoVADD_VI_M8
Definition riscv/opcodes.hpp:604
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M4
@ PseudoVSUB_VV_M4
Definition riscv/opcodes.hpp:10479
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M2_M1
@ PseudoVSOXSEG5EI32_V_M2_M1
Definition riscv/opcodes.hpp:9537
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E32_M1_MASK
@ PseudoVRGATHEREI16_VV_M4_E32_M1_MASK
Definition riscv/opcodes.hpp:8347
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_MF2
@ PseudoVSM4R_VS_M4_MF2
Definition riscv/opcodes.hpp:8947
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_M2_MASK
@ PseudoVLOXSEG2EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:4457
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M2_MASK
@ PseudoVLUXSEG3EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:5907
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E16
@ PseudoVFWCVT_F_X_V_M1_E16
Definition riscv/opcodes.hpp:3607
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VV_MF2_MASK
@ PseudoVMADD_VV_MF2_MASK
Definition riscv/opcodes.hpp:6481
LIEF::assembly::riscv::OPCODE::PseudoCCSRLIW
@ PseudoCCSRLIW
Definition riscv/opcodes.hpp:362
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_M8_MASK
@ PseudoVSLIDE1UP_VX_M8_MASK
Definition riscv/opcodes.hpp:8815
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_M1
@ PseudoVSUXSEG6EI32_V_M1_M1
Definition riscv/opcodes.hpp:11115
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M1
@ PseudoVSSE8_V_M1
Definition riscv/opcodes.hpp:9977
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M4_M2
@ PseudoVLOXSEG3EI16_V_M4_M2
Definition riscv/opcodes.hpp:4480
LIEF::assembly::riscv::OPCODE::VWMACCU_VX
@ VWMACCU_VX
Definition riscv/opcodes.hpp:13816
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E64
@ PseudoVFSGNJN_VV_M2_E64
Definition riscv/opcodes.hpp:3161
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF2_MASK
@ PseudoVMAX_VV_MF2_MASK
Definition riscv/opcodes.hpp:6551
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M8_MASK
@ PseudoVMSLTU_VV_M8_MASK
Definition riscv/opcodes.hpp:7171
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M8
@ PseudoVANDN_VX_M8
Definition riscv/opcodes.hpp:810
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E64
@ PseudoVREMU_VV_M1_E64
Definition riscv/opcodes.hpp:8088
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF8
@ PseudoVSUXSEG6EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:11113
LIEF::assembly::riscv::OPCODE::VLSSEG4E8_V
@ VLSSEG4E8_V
Definition riscv/opcodes.hpp:13435
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_MF2_E16
@ PseudoVFWMACC_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3737
LIEF::assembly::riscv::OPCODE::VMACC_VV
@ VMACC_VV
Definition riscv/opcodes.hpp:13484
LIEF::assembly::riscv::OPCODE::PseudoVQMACCUS_4x8x4_M2
@ PseudoVQMACCUS_4x8x4_M2
Definition riscv/opcodes.hpp:7681
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M1_M1
@ PseudoVLUXSEG8EI32_V_M1_M1
Definition riscv/opcodes.hpp:6342
LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadUMin32
@ PseudoMaskedAtomicLoadUMin32
Definition riscv/opcodes.hpp:413
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M1_MF2
@ PseudoVSUXSEG4EI32_V_M1_MF2
Definition riscv/opcodes.hpp:10937
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF4_MF4
@ PseudoVSUXSEG4EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:10929
LIEF::assembly::riscv::OPCODE::C_SEXT_B
@ C_SEXT_B
Definition riscv/opcodes.hpp:12530
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF2
@ PseudoVLOXSEG7EI64_V_M1_MF2
Definition riscv/opcodes.hpp:4892
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_MF2_E16_MASK
@ PseudoVFDIV_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:1872
LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_M2
@ PseudoVMXOR_MM_M2
Definition riscv/opcodes.hpp:7420
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M2_MF2
@ PseudoVLOXEI32_V_M2_MF2
Definition riscv/opcodes.hpp:4234
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M2_MASK
@ PseudoVSUXSEG2EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10670
LIEF::assembly::riscv::OPCODE::MULHU
@ MULHU
Definition riscv/opcodes.hpp:12904
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_MF4
@ PseudoVSRA_VI_MF4
Definition riscv/opcodes.hpp:9873
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M4_E8
@ PseudoVREM_VV_M4_E8
Definition riscv/opcodes.hpp:8194
LIEF::assembly::riscv::OPCODE::VSSEG8E8_V
@ VSSEG8E8_V
Definition riscv/opcodes.hpp:13729
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF8_MASK
@ PseudoVNMSUB_VV_MF8_MASK
Definition riscv/opcodes.hpp:7539
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF2_MASK
@ PseudoVLOXSEG6EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4839
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_SE_M4
@ PseudoVC_V_VVV_SE_M4
Definition riscv/opcodes.hpp:1311
LIEF::assembly::riscv::OPCODE::VLSSEG3E8_V
@ VLSSEG3E8_V
Definition riscv/opcodes.hpp:13431
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF2_MF2
@ PseudoVLUXSEG5EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:6090
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E64_MASK
@ PseudoVFMSAC_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:2227
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR64_M1_E64_MASK
@ PseudoVFNMADD_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2698
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF2_MASK
@ PseudoVSOXSEG3EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:9396
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF4_E16
@ PseudoVFWMSAC_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3775
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_MF2
@ PseudoVSSEG6E32_V_MF2
Definition riscv/opcodes.hpp:10111
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M8_MASK
@ PseudoVMINU_VV_M8_MASK
Definition riscv/opcodes.hpp:6833
LIEF::assembly::riscv::OPCODE::HFENCE_VVMA
@ HFENCE_VVMA
Definition riscv/opcodes.hpp:12795
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M4_M4
@ PseudoVLOXSEG2EI8_V_M4_M4
Definition riscv/opcodes.hpp:4444
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E16
@ PseudoVFNMSAC_VV_M2_E16
Definition riscv/opcodes.hpp:2771
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_M4
@ PseudoVRSUB_VI_M4
Definition riscv/opcodes.hpp:8580
LIEF::assembly::riscv::OPCODE::CV_EXTRACTUR
@ CV_EXTRACTUR
Definition riscv/opcodes.hpp:12307
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B32
@ PseudoVMSIF_M_B32
Definition riscv/opcodes.hpp:7071
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M4
@ PseudoVFSLIDE1DOWN_VFPR64_M4
Definition riscv/opcodes.hpp:3327
LIEF::assembly::riscv::OPCODE::CV_FL1
@ CV_FL1
Definition riscv/opcodes.hpp:12313
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M2
@ PseudoVMULHU_VV_M2
Definition riscv/opcodes.hpp:7307
LIEF::assembly::riscv::OPCODE::PseudoVMCLR_M_B16
@ PseudoVMCLR_M_B16
Definition riscv/opcodes.hpp:6571
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M2
@ PseudoVRGATHEREI16_VV_M2_E16_M2
Definition riscv/opcodes.hpp:8308
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M4
@ PseudoVRGATHEREI16_VV_M8_E8_M4
Definition riscv/opcodes.hpp:8390
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_M2_MASK
@ PseudoVMFEQ_VFPR16_M2_MASK
Definition riscv/opcodes.hpp:6601
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_MF2_MASK
@ PseudoVRGATHER_VX_MF2_MASK
Definition riscv/opcodes.hpp:8501
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF8
@ PseudoVOR_VV_MF8
Definition riscv/opcodes.hpp:7652
LIEF::assembly::riscv::OPCODE::SRLI
@ SRLI
Definition riscv/opcodes.hpp:13001
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF4_MASK
@ PseudoVWMULU_VV_MF4_MASK
Definition riscv/opcodes.hpp:11572
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M4_MASK
@ PseudoVWSUB_WV_M4_MASK
Definition riscv/opcodes.hpp:11812
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_M2
@ PseudoVRELOAD4_M2
Definition riscv/opcodes.hpp:8064
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M2_E16_MASK
@ PseudoVREM_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:8181
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_MF2_MASK
@ PseudoVSOXSEG6EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9600
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_MF2
@ PseudoVSUXSEG2EI32_V_M2_MF2
Definition riscv/opcodes.hpp:10709
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M2_M1
@ PseudoVAESZ_VS_M2_M1
Definition riscv/opcodes.hpp:770
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M8_E32_MASK
@ PseudoVFMIN_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2151
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_MF2_TIED
@ PseudoVWADD_WV_MF2_TIED
Definition riscv/opcodes.hpp:11434
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF2_MASK
@ PseudoVWSLL_VX_MF2_MASK
Definition riscv/opcodes.hpp:11714
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_MF4_MF2_MASK
@ PseudoVLUXSEG5EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:6097
LIEF::assembly::riscv::OPCODE::VLUXSEG5EI8_V
@ VLUXSEG5EI8_V
Definition riscv/opcodes.hpp:13471
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M2_E16
@ PseudoVFMADD_VFPR16_M2_E16
Definition riscv/opcodes.hpp:1999
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M4_M1
@ PseudoVLUXSEG4EI64_V_M4_M1
Definition riscv/opcodes.hpp:6044
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M8_M2
@ PseudoVLUXSEG2EI64_V_M8_M2
Definition riscv/opcodes.hpp:5822
LIEF::assembly::riscv::OPCODE::VROR_VX
@ VROR_VX
Definition riscv/opcodes.hpp:13615
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_MF4
@ PseudoVC_V_VV_MF4
Definition riscv/opcodes.hpp:1333
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M1_M2
@ PseudoVLUXEI32_V_M1_M2
Definition riscv/opcodes.hpp:5614
LIEF::assembly::riscv::OPCODE::CV_MAXU_SC_H
@ CV_MAXU_SC_H
Definition riscv/opcodes.hpp:12349
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_M2_E16
@ PseudoVFWMUL_VV_M2_E16
Definition riscv/opcodes.hpp:3825
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B64
@ PseudoVMSIF_M_B64
Definition riscv/opcodes.hpp:7075
LIEF::assembly::riscv::OPCODE::VLSEG7E64FF_V
@ VLSEG7E64FF_V
Definition riscv/opcodes.hpp:13412
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M1_E32
@ PseudoVFMACC_VV_M1_E32
Definition riscv/opcodes.hpp:1969
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E16_M2_MASK
@ PseudoVRGATHEREI16_VV_M1_E16_M2_MASK
Definition riscv/opcodes.hpp:8277
LIEF::assembly::riscv::OPCODE::LD_AQ_RL
@ LD_AQ_RL
Definition riscv/opcodes.hpp:12838
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M2_M1_MASK
@ PseudoVSUXSEG3EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10802
LIEF::assembly::riscv::OPCODE::G_ROTL
@ G_ROTL
Definition riscv/opcodes.hpp:164
LIEF::assembly::riscv::OPCODE::G_SMAX
@ G_SMAX
Definition riscv/opcodes.hpp:239
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_M4
@ PseudoVMSBC_VX_M4
Definition riscv/opcodes.hpp:6933
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E64_MASK
@ PseudoVFCVT_F_XU_V_M8_E64_MASK
Definition riscv/opcodes.hpp:1694
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M8_MASK
@ PseudoVFCVT_RTZ_X_F_V_M8_MASK
Definition riscv/opcodes.hpp:1834
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E16_MASK
@ PseudoVFCVT_RM_F_XU_V_M8_E16_MASK
Definition riscv/opcodes.hpp:1750
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E16
@ PseudoVRGATHER_VV_MF2_E16
Definition riscv/opcodes.hpp:8480
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK
@ PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK
Definition riscv/opcodes.hpp:2522
LIEF::assembly::riscv::OPCODE::C_ADDI_NOP
@ C_ADDI_NOP
Definition riscv/opcodes.hpp:12481
LIEF::assembly::riscv::OPCODE::CV_CMPGTU_SC_H
@ CV_CMPGTU_SC_H
Definition riscv/opcodes.hpp:12234
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF8_MASK
@ PseudoVSOXSEG3EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:9346
LIEF::assembly::riscv::OPCODE::CV_MACHHUN
@ CV_MACHHUN
Definition riscv/opcodes.hpp:12336
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M2_MASK
@ PseudoVSOXSEG3EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9330
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M4_M1
@ PseudoVLOXSEG7EI64_V_M4_M1
Definition riscv/opcodes.hpp:4904
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF2
@ PseudoVLSSEG4E8_V_MF2
Definition riscv/opcodes.hpp:5484
LIEF::assembly::riscv::OPCODE::AES64IM
@ AES64IM
Definition riscv/opcodes.hpp:11944
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_MF2_MASK
@ PseudoVLOXSEG2EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:4465
LIEF::assembly::riscv::OPCODE::VROR_VV
@ VROR_VV
Definition riscv/opcodes.hpp:13614
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M4_E16
@ PseudoVFMSUB_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2256
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M8_E32_MASK
@ PseudoVFNMSAC_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2754
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF2_MF2
@ PseudoVLUXSEG6EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:6170
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF4
@ PseudoVBREV8_V_MF4
Definition riscv/opcodes.hpp:926
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF8_E8
@ PseudoVDIV_VX_MF8_E8
Definition riscv/opcodes.hpp:1597
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M8_E32_MASK
@ PseudoVFWREDUSUM_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:3948
LIEF::assembly::riscv::OPCODE::VSLL_VI
@ VSLL_VI
Definition riscv/opcodes.hpp:13649
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M2_MASK
@ PseudoVMFLT_VV_M2_MASK
Definition riscv/opcodes.hpp:6775
LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_4x8x4_M4
@ PseudoVQMACCSU_4x8x4_M4
Definition riscv/opcodes.hpp:7674
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF2_E16
@ PseudoVFSGNJN_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3129
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_MF2
@ PseudoVC_V_FPR16VV_MF2
Definition riscv/opcodes.hpp:1170
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M1
@ PseudoVAESDF_VV_M1
Definition riscv/opcodes.hpp:664
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M4_M4
@ PseudoVSOXSEG2EI16_V_M4_M4
Definition riscv/opcodes.hpp:9171
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M4_MF2_MASK
@ PseudoVSUXSEG5EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:11072
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M2_E32
@ PseudoVFMAX_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2071
LIEF::assembly::riscv::OPCODE::FLE_D
@ FLE_D
Definition riscv/opcodes.hpp:12664
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_M1_MASK
@ PseudoVSOXSEG6EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9658
LIEF::assembly::riscv::OPCODE::WriteFRM
@ WriteFRM
Definition riscv/opcodes.hpp:11928
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E16_MASK
@ PseudoVREDXOR_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:8041
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M2
@ PseudoVSOXSEG4EI32_V_M4_M2
Definition riscv/opcodes.hpp:9445
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF8_E8
@ PseudoVDIVU_VV_MF8_E8
Definition riscv/opcodes.hpp:1465
LIEF::assembly::riscv::OPCODE::VSLL_VX
@ VSLL_VX
Definition riscv/opcodes.hpp:13651
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M1
@ PseudoVNSRA_WV_M1
Definition riscv/opcodes.hpp:7566
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_MF2_MF2_MASK
@ PseudoVLUXEI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:5645
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF2
@ PseudoVSUXSEG5EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:11029
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF4_MASK
@ PseudoVSUXSEG5EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:11040
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_MF2
@ PseudoVSOXEI8_V_MF2_MF2
Definition riscv/opcodes.hpp:9137
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M1_TIED
@ PseudoVWADD_WV_M1_TIED
Definition riscv/opcodes.hpp:11422
LIEF::assembly::riscv::OPCODE::CV_MULHHSRN
@ CV_MULHHSRN
Definition riscv/opcodes.hpp:12372
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M1
@ PseudoVSSEG4E64_V_M1
Definition riscv/opcodes.hpp:10069
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR32_M2_E32
@ PseudoVFWNMACC_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3851
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_M2
@ PseudoVMSLE_VX_M2
Definition riscv/opcodes.hpp:7151
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_MF4
@ PseudoVC_FPR16VW_SE_MF4
Definition riscv/opcodes.hpp:1089
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_M2_MASK
@ PseudoVSMUL_VX_M2_MASK
Definition riscv/opcodes.hpp:8981
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E8
@ PseudoVWREDSUMU_VS_M1_E8
Definition riscv/opcodes.hpp:11615
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI32_V_M1_MF4
@ PseudoVSOXSEG6EI32_V_M1_MF4
Definition riscv/opcodes.hpp:9615
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M8
@ PseudoVOR_VV_M8
Definition riscv/opcodes.hpp:7646
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI8_V_MF2_MF2
@ PseudoVLOXSEG5EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:4754
LIEF::assembly::riscv::OPCODE::ADDI
@ ADDI
Definition riscv/opcodes.hpp:11932
LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF2
@ PseudoVID_V_MF2
Definition riscv/opcodes.hpp:4063
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M1
@ PseudoVLSEG4E8_V_M1
Definition riscv/opcodes.hpp:5228
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M4_M1_MASK
@ PseudoVLUXSEG3EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:5935
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E32
@ PseudoVDIV_VV_M1_E32
Definition riscv/opcodes.hpp:1513
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M2_M8
@ PseudoVLUXEI16_V_M2_M8
Definition riscv/opcodes.hpp:5584
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M8_M4
@ PseudoVSUXEI32_V_M8_M4
Definition riscv/opcodes.hpp:10571
LIEF::assembly::riscv::OPCODE::PseudoVLM_V_B32
@ PseudoVLM_V_B32
Definition riscv/opcodes.hpp:4174
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M1_E32
@ PseudoVFRDIV_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2887
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_M4
@ PseudoVSADD_VV_M4
Definition riscv/opcodes.hpp:8664
LIEF::assembly::riscv::OPCODE::FEQ_D_IN32X
@ FEQ_D_IN32X
Definition riscv/opcodes.hpp:12654
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF8
@ PseudoVLOXSEG5EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:4708
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M2_E64_MASK
@ PseudoVFMUL_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2337
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF2_E32_MASK
@ PseudoVDIV_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:1546
LIEF::assembly::riscv::OPCODE::THVdotVMAQAU_VX
@ THVdotVMAQAU_VX
Definition riscv/opcodes.hpp:13024
LIEF::assembly::riscv::OPCODE::FEQ_D
@ FEQ_D
Definition riscv/opcodes.hpp:12653
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E32
@ PseudoVFNCVT_F_F_W_M2_E32
Definition riscv/opcodes.hpp:2441
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_FMUL
@ G_VECREDUCE_FMUL
Definition riscv/opcodes.hpp:303
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M4
@ PseudoVMFEQ_VFPR64_M4
Definition riscv/opcodes.hpp:6624
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_M1
@ PseudoVMSGTU_VI_M1
Definition riscv/opcodes.hpp:7009
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E8_M4_MASK
@ PseudoVRGATHEREI16_VV_M4_E8_M4_MASK
Definition riscv/opcodes.hpp:8367
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_MF2_MASK
@ PseudoVWADDU_WV_MF2_MASK
Definition riscv/opcodes.hpp:11372
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M4_M1_MASK
@ PseudoVSOXSEG7EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9726
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M4_MASK
@ PseudoVFWCVT_X_F_V_M4_MASK
Definition riscv/opcodes.hpp:3692
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF4_MASK
@ PseudoVNCLIPU_WI_MF4_MASK
Definition riscv/opcodes.hpp:7435
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M4
@ PseudoVREV8_V_M4
Definition riscv/opcodes.hpp:8264
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF2_MASK
@ PseudoVSOXSEG5EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:9586
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M2_MF2_MASK
@ PseudoVSOXSEG4EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9442
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M1_E32_MASK
@ PseudoVFWNMSAC_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3886
LIEF::assembly::riscv::OPCODE::FMSUB_D_IN32X
@ FMSUB_D_IN32X
Definition riscv/opcodes.hpp:12714
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M8
@ PseudoVSUXEI16_V_M2_M8
Definition riscv/opcodes.hpp:10517
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF4
@ PseudoVSUXSEG5EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:11025
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E64_V_M1_MASK
@ PseudoVLSEG7E64_V_M1_MASK
Definition riscv/opcodes.hpp:5341
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVV_SE_M2
@ PseudoVC_V_XVV_SE_M2
Definition riscv/opcodes.hpp:1350
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E8_MASK
@ PseudoVFWCVT_F_X_V_M4_E8_MASK
Definition riscv/opcodes.hpp:3624
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_MF2_MASK
@ PseudoVSUXSEG2EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10666
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M2
@ PseudoVFNCVT_RM_XU_F_W_M2
Definition riscv/opcodes.hpp:2527
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_MF2_E32
@ PseudoVFWMACC_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3747
LIEF::assembly::riscv::OPCODE::G_SREM
@ G_SREM
Definition riscv/opcodes.hpp:80
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_M4_M2_MASK
@ PseudoVSOXSEG4EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9412
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_MF8
@ PseudoVMV_V_X_MF8
Definition riscv/opcodes.hpp:7410
LIEF::assembly::riscv::OPCODE::MEMBARRIER
@ MEMBARRIER
Definition riscv/opcodes.hpp:66
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF2_MF2_MASK
@ PseudoVSUXSEG3EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10888
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF2_MASK
@ PseudoVLUXSEG2EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:5851
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_MF4
@ PseudoVLUXSEG2EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:5758
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M4
@ PseudoVROR_VX_M4
Definition riscv/opcodes.hpp:8566
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E64_MASK
@ PseudoVREDAND_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:7713
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF4
@ PseudoVSUXSEG5EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:11051
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_M1_E16_MASK
@ PseudoVFWNMSAC_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3876
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M1
@ PseudoVSSEG3E16_V_M1
Definition riscv/opcodes.hpp:10027
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E64_V_M1_MASK
@ PseudoVSSEG5E64_V_M1_MASK
Definition riscv/opcodes.hpp:10094
LIEF::assembly::riscv::OPCODE::FLEQ_S
@ FLEQ_S
Definition riscv/opcodes.hpp:12663
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M8_E64
@ PseudoVFSGNJN_VFPR64_M8_E64
Definition riscv/opcodes.hpp:3149
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF4_MF4_MASK
@ PseudoVSOXSEG2EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9282
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M2
@ PseudoVLOXSEG4EI64_V_M8_M2
Definition riscv/opcodes.hpp:4660
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_MF2
@ PseudoVSUXSEG3EI32_V_M2_MF2
Definition riscv/opcodes.hpp:10835
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M4_M4_MASK
@ PseudoVLOXEI64_V_M4_M4_MASK
Definition riscv/opcodes.hpp:4279
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_M8_MASK
@ PseudoVMSLE_VI_M8_MASK
Definition riscv/opcodes.hpp:7128
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_MF2
@ PseudoVSOXSEG3EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:9383
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF2_MASK
@ PseudoVSLL_VI_MF2_MASK
Definition riscv/opcodes.hpp:8887
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF4
@ PseudoVLSEG3E8_V_MF4
Definition riscv/opcodes.hpp:5178
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF2
@ PseudoVWADDU_WX_MF2
Definition riscv/opcodes.hpp:11389
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_MF2_MASK
@ PseudoVSUXSEG5EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11050
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_M1
@ PseudoVLUXSEG7EI16_V_MF4_M1
Definition riscv/opcodes.hpp:6254
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_MF4_MASK
@ PseudoVSSE8_V_MF4_MASK
Definition riscv/opcodes.hpp:9988
LIEF::assembly::riscv::OPCODE::PseudoVSPILL2_M4
@ PseudoVSPILL2_M4
Definition riscv/opcodes.hpp:9833
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_M1_MF2
@ PseudoVLUXSEG8EI16_V_M1_MF2
Definition riscv/opcodes.hpp:6324
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_MF4_MASK
@ PseudoVMAX_VX_MF4_MASK
Definition riscv/opcodes.hpp:6567
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M1
@ PseudoVFWCVT_RM_X_F_V_M1
Definition riscv/opcodes.hpp:3647
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_M2_MASK
@ PseudoVLOXSEG4EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:4655
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF8_MASK
@ PseudoVLUXSEG2EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:5861
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M8_M4_MASK
@ PseudoVSUXSEG2EI32_V_M8_M4_MASK
Definition riscv/opcodes.hpp:10720
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_MF8
@ PseudoVC_V_VV_MF8
Definition riscv/opcodes.hpp:1334
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VXM_M4
@ PseudoVMADC_VXM_M4
Definition riscv/opcodes.hpp:6460
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF4
@ PseudoVSSRA_VI_MF4
Definition riscv/opcodes.hpp:10173
LIEF::assembly::riscv::OPCODE::VLUXSEG6EI64_V
@ VLUXSEG6EI64_V
Definition riscv/opcodes.hpp:13474
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI8_V_M1_M1
@ PseudoVSOXSEG7EI8_V_M1_M1
Definition riscv/opcodes.hpp:9731
LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_M4
@ PseudoVMANDN_MM_M4
Definition riscv/opcodes.hpp:6502
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M2_MASK
@ PseudoVMFEQ_VFPR64_M2_MASK
Definition riscv/opcodes.hpp:6623
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_M8
@ PseudoVC_FPR16VW_SE_M8
Definition riscv/opcodes.hpp:1087
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E16
@ PseudoVFMIN_VV_M2_E16
Definition riscv/opcodes.hpp:2168
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR64_M2_E64
@ PseudoVFRSUB_VFPR64_M2_E64
Definition riscv/opcodes.hpp:3115
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M8
@ PseudoVMADC_VIM_M8
Definition riscv/opcodes.hpp:6433
LIEF::assembly::riscv::OPCODE::CV_MAXU_SCI_B
@ CV_MAXU_SCI_B
Definition riscv/opcodes.hpp:12346
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M1_E32_MASK
@ PseudoVFNMSAC_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2748
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M1_E16_MASK
@ PseudoVFDIV_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:1894
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M2_E64
@ PseudoVFREC7_V_M2_E64
Definition riscv/opcodes.hpp:2915
LIEF::assembly::riscv::OPCODE::PseudoVADC_VXM_M1
@ PseudoVADC_VXM_M1
Definition riscv/opcodes.hpp:591
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_MF2
@ PseudoVSUXSEG6EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:11109
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_MF2_MASK
@ PseudoVLOXSEG6EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4773
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF4_MF2
@ PseudoVSUXSEG8EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:11269
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF4_MASK
@ PseudoVSOXSEG7EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9708
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M2_MASK
@ PseudoVWADD_WV_M2_MASK
Definition riscv/opcodes.hpp:11424
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF2_MASK
@ PseudoVLUXEI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:5715
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_MF2
@ PseudoVC_V_FPR32VV_MF2
Definition riscv/opcodes.hpp:1206
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M4_MASK
@ PseudoVXOR_VV_M4_MASK
Definition riscv/opcodes.hpp:11858
LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_MF4
@ PseudoVMOR_MM_MF4
Definition riscv/opcodes.hpp:6908
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_MF4
@ PseudoVLE16FF_V_MF4
Definition riscv/opcodes.hpp:4093
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF4
@ PseudoVMFEQ_VFPR16_MF4
Definition riscv/opcodes.hpp:6608
LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_MF2_MASK
@ PseudoVLSE32_V_MF2_MASK
Definition riscv/opcodes.hpp:5031
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_MF4
@ PseudoVSM4R_VS_M1_MF4
Definition riscv/opcodes.hpp:8937
LIEF::assembly::riscv::OPCODE::ZEXT_H_RV64
@ ZEXT_H_RV64
Definition riscv/opcodes.hpp:13853
LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M2
@ PseudoVSM3C_VI_M2
Definition riscv/opcodes.hpp:8921
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E16_MASK
@ PseudoVDIV_VX_MF4_E16_MASK
Definition riscv/opcodes.hpp:1594
LIEF::assembly::riscv::OPCODE::MOPR18
@ MOPR18
Definition riscv/opcodes.hpp:12870
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_M1_MF2
@ PseudoVLOXSEG6EI16_V_M1_MF2
Definition riscv/opcodes.hpp:4772
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E32
@ PseudoVFADD_VV_M4_E32
Definition riscv/opcodes.hpp:1643
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M1
@ PseudoVLSE8_V_M1
Definition riscv/opcodes.hpp:5040
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M2_MF2_MASK
@ PseudoVLUXSEG8EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:6373
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M1_M2_MASK
@ PseudoVSUXSEG2EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10662
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M2
@ PseudoVSSEG3E8_V_M2
Definition riscv/opcodes.hpp:10047
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF4_MASK
@ PseudoVSSEG3E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10052
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_MF2
@ PseudoVMADC_VVM_MF2
Definition riscv/opcodes.hpp:6448
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M4_MASK
@ PseudoVMAX_VX_M4_MASK
Definition riscv/opcodes.hpp:6561
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M1_MASK
@ PseudoVMFGE_VFPR16_M1_MASK
Definition riscv/opcodes.hpp:6641
LIEF::assembly::riscv::OPCODE::TH_MVNEZ
@ TH_MVNEZ
Definition riscv/opcodes.hpp:13099
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF2
@ PseudoVRGATHEREI16_VV_M1_E32_MF2
Definition riscv/opcodes.hpp:8286
LIEF::assembly::riscv::OPCODE::MOPR15
@ MOPR15
Definition riscv/opcodes.hpp:12867
LIEF::assembly::riscv::OPCODE::VROR_VI
@ VROR_VI
Definition riscv/opcodes.hpp:13613
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF2
@ PseudoVLUXEI16_V_MF2_MF2
Definition riscv/opcodes.hpp:5600
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M2_M2_MASK
@ PseudoVSUXSEG3EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10882
LIEF::assembly::riscv::OPCODE::CV_CLIPUR
@ CV_CLIPUR
Definition riscv/opcodes.hpp:12210
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M4_M2_MASK
@ PseudoVLUXEI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:5631
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M2_M1_MASK
@ PseudoVLUXSEG5EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6087
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF4_MASK
@ PseudoVRSUB_VX_MF4_MASK
Definition riscv/opcodes.hpp:8601
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M4_M1_MASK
@ PseudoVSOXSEG4EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9444
LIEF::assembly::riscv::OPCODE::BUNDLE
@ BUNDLE
Definition riscv/opcodes.hpp:44
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF4_M2
@ PseudoVSUXEI8_V_MF4_M2
Definition riscv/opcodes.hpp:10645
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_MF2_MASK
@ PseudoVMACC_VV_MF2_MASK
Definition riscv/opcodes.hpp:6411
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E32_V_MF2
@ PseudoVLSEG8E32_V_MF2
Definition riscv/opcodes.hpp:5376
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16_TIED
@ PseudoVFWSUB_WV_MF4_E16_TIED
Definition riscv/opcodes.hpp:4044
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_M4_E16
@ PseudoVFADD_VFPR16_M4_E16
Definition riscv/opcodes.hpp:1603
LIEF::assembly::riscv::OPCODE::CV_MAC
@ CV_MAC
Definition riscv/opcodes.hpp:12333
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF2_MASK
@ PseudoVWMULU_VV_MF2_MASK
Definition riscv/opcodes.hpp:11570
LIEF::assembly::riscv::OPCODE::AMOMAXU_W_RL
@ AMOMAXU_W_RL
Definition riscv/opcodes.hpp:12018
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_MF4_MASK
@ PseudoVSSE16_V_MF4_MASK
Definition riscv/opcodes.hpp:9958
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M2
@ PseudoVSUXSEG4EI32_V_M4_M2
Definition riscv/opcodes.hpp:10949
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E32
@ PseudoVFWREDOSUM_VS_MF2_E32
Definition riscv/opcodes.hpp:3929
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64_V_M2_MASK
@ PseudoVLSEG4E64_V_M2_MASK
Definition riscv/opcodes.hpp:5217
LIEF::assembly::riscv::OPCODE::VAESZ_VS
@ VAESZ_VS
Definition riscv/opcodes.hpp:13151
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E64
@ PseudoVFNMSUB_VV_M4_E64
Definition riscv/opcodes.hpp:2841
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M1_E64_MASK
@ PseudoVFDIV_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:1886
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_MF2_MF2
@ PseudoVAESEM_VS_MF2_MF2
Definition riscv/opcodes.hpp:748
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF4_M2
@ PseudoVSUXSEG3EI8_V_MF4_M2
Definition riscv/opcodes.hpp:10891
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M2_MASK
@ PseudoVSSSEG3E32_V_M2_MASK
Definition riscv/opcodes.hpp:10294
LIEF::assembly::riscv::OPCODE::G_MEMCPY
@ G_MEMCPY
Definition riscv/opcodes.hpp:292
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF8_MASK
@ PseudoVSADD_VI_MF8_MASK
Definition riscv/opcodes.hpp:8659
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M1
@ PseudoVLUXSEG2EI16_V_M1_M1
Definition riscv/opcodes.hpp:5726
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E16_MASK
@ PseudoVFNMACC_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:2664
LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M8
@ PseudoVLE32FF_V_M8
Definition riscv/opcodes.hpp:4113
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_MF2
@ PseudoVLOXSEG2EI16_V_M1_MF2
Definition riscv/opcodes.hpp:4340
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_M2
@ PseudoVSMUL_VV_M2
Definition riscv/opcodes.hpp:8966
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M2
@ PseudoVANDN_VX_M2
Definition riscv/opcodes.hpp:806
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_MF4_MASK
@ PseudoVMUL_VX_MF4_MASK
Definition riscv/opcodes.hpp:7386
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_M1_MF4_MASK
@ PseudoVLOXSEG7EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4875
LIEF::assembly::riscv::OPCODE::VMV8R_V
@ VMV8R_V
Definition riscv/opcodes.hpp:13559
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M4_MASK
@ PseudoVSOXEI16_V_M1_M4_MASK
Definition riscv/opcodes.hpp:9004
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_MF4_E16
@ PseudoVFWREDUSUM_VS_MF4_E16
Definition riscv/opcodes.hpp:3953
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M2_MF2
@ PseudoVSOXSEG8EI64_V_M2_MF2
Definition riscv/opcodes.hpp:9801
LIEF::assembly::riscv::OPCODE::HSV_W
@ HSV_W
Definition riscv/opcodes.hpp:12810
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF8
@ PseudoVSLL_VV_MF8
Definition riscv/opcodes.hpp:8904
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E64_MASK
@ PseudoVDIV_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:1516
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M2
@ PseudoVLUXEI64_V_M8_M2
Definition riscv/opcodes.hpp:5676
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M1_E32_MASK
@ PseudoVFNMACC_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2628
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD3_M2
@ PseudoVRELOAD3_M2
Definition riscv/opcodes.hpp:8059
LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_M8
@ PseudoVMAND_MM_M8
Definition riscv/opcodes.hpp:6510
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E32_MASK
@ PseudoVFMUL_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:2345
LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_SC_B
@ CV_SDOTUSP_SC_B
Definition riscv/opcodes.hpp:12409
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF8_E8_MASK
@ PseudoVREDXOR_VS_MF8_E8_MASK
Definition riscv/opcodes.hpp:8051
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_M1_M1
@ PseudoVSOXSEG8EI8_V_M1_M1
Definition riscv/opcodes.hpp:9811
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E32
@ PseudoVFREDUSUM_VS_M1_E32
Definition riscv/opcodes.hpp:3027
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M1_MASK
@ PseudoVSOXSEG4EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9414
LIEF::assembly::riscv::OPCODE::VASUBU_VX
@ VASUBU_VX
Definition riscv/opcodes.hpp:13158
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M8_MASK
@ PseudoVNMSUB_VX_M8_MASK
Definition riscv/opcodes.hpp:7547
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M4
@ PseudoVSSRL_VX_M4
Definition riscv/opcodes.hpp:10237
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_M2
@ PseudoVWMULU_VX_M2
Definition riscv/opcodes.hpp:11577
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M1_MASK
@ PseudoVXOR_VV_M1_MASK
Definition riscv/opcodes.hpp:11854
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF2_M1
@ PseudoVSUXEI8_V_MF2_M1
Definition riscv/opcodes.hpp:10635
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_M1
@ PseudoVC_FPR16VV_SE_M1
Definition riscv/opcodes.hpp:1078
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_MF2_MASK
@ PseudoVSOXSEG8EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9816
LIEF::assembly::riscv::OPCODE::VLSEG3E64_V
@ VLSEG3E64_V
Definition riscv/opcodes.hpp:13381
LIEF::assembly::riscv::OPCODE::PseudoSEXT_B
@ PseudoSEXT_B
Definition riscv/opcodes.hpp:443
LIEF::assembly::riscv::OPCODE::AMOCAS_Q_AQ_RL
@ AMOCAS_Q_AQ_RL
Definition riscv/opcodes.hpp:11997
LIEF::assembly::riscv::OPCODE::FMV_X_W_FPR64
@ FMV_X_W_FPR64
Definition riscv/opcodes.hpp:12735
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M8_MASK
@ PseudoVANDN_VX_M8_MASK
Definition riscv/opcodes.hpp:811
LIEF::assembly::riscv::OPCODE::AMOSWAP_W
@ AMOSWAP_W
Definition riscv/opcodes.hpp:12095
LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF4
@ PseudoVID_V_MF4
Definition riscv/opcodes.hpp:4065
LIEF::assembly::riscv::OPCODE::AMOMAXU_D_AQ_RL
@ AMOMAXU_D_AQ_RL
Definition riscv/opcodes.hpp:12009
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF2
@ PseudoVSUXSEG5EI64_V_M1_MF2
Definition riscv/opcodes.hpp:11057
LIEF::assembly::riscv::OPCODE::XPERM8
@ XPERM8
Definition riscv/opcodes.hpp:13851
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF2
@ PseudoVLOXEI8_V_MF8_MF2
Definition riscv/opcodes.hpp:4328
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M4_M1_MASK
@ PseudoVLUXSEG6EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:6217
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF8
@ PseudoVSSEG5E8_V_MF8
Definition riscv/opcodes.hpp:10101
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_MF2_E8
@ PseudoVREM_VV_MF2_E8
Definition riscv/opcodes.hpp:8208
LIEF::assembly::riscv::OPCODE::TH_MULAW
@ TH_MULAW
Definition riscv/opcodes.hpp:13094
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_MF2
@ PseudoVLOXEI16_V_M1_MF2
Definition riscv/opcodes.hpp:4184
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_MF8
@ PseudoVSOXSEG7EI64_V_M1_MF8
Definition riscv/opcodes.hpp:9717
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E32_MASK
@ PseudoVFSUB_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3436
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF4_M1_MASK
@ PseudoVSOXSEG3EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9386
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M4_MASK
@ PseudoVLUXEI8_V_MF2_M4_MASK
Definition riscv/opcodes.hpp:5707
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M2_MASK
@ PseudoVZEXT_VF4_M2_MASK
Definition riscv/opcodes.hpp:11896
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_ADD
@ G_VECREDUCE_ADD
Definition riscv/opcodes.hpp:308
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E64_MASK
@ PseudoVFSGNJN_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:3174
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M1
@ PseudoVLUXSEG4EI16_V_M1_M1
Definition riscv/opcodes.hpp:5972
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E32_V_M2_MASK
@ PseudoVSSSEG4E32_V_M2_MASK
Definition riscv/opcodes.hpp:10322
LIEF::assembly::riscv::OPCODE::ROR
@ ROR
Definition riscv/opcodes.hpp:12932
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M4_M4
@ PseudoVSOXSEG2EI32_V_M4_M4
Definition riscv/opcodes.hpp:9211
LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_M2
@ PseudoVSHA2CH_VV_M2
Definition riscv/opcodes.hpp:8780
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E8_MASK
@ PseudoVREDAND_VS_MF4_E8_MASK
Definition riscv/opcodes.hpp:7741
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E16_MASK_TIED
@ PseudoVFWADD_WV_M1_E16_MASK_TIED
Definition riscv/opcodes.hpp:3507
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF2_MASK
@ PseudoVMSGTU_VI_MF2_MASK
Definition riscv/opcodes.hpp:7018
LIEF::assembly::riscv::OPCODE::C_BNEZ
@ C_BNEZ
Definition riscv/opcodes.hpp:12487
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF4
@ PseudoVSUXSEG3EI64_V_M1_MF4
Definition riscv/opcodes.hpp:10855
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF8
@ PseudoVSSSEG4E8_V_MF8
Definition riscv/opcodes.hpp:10337
LIEF::assembly::riscv::OPCODE::AMOCAS_H_RL
@ AMOCAS_H_RL
Definition riscv/opcodes.hpp:11994
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M4_MASK
@ PseudoVSUXEI16_V_M4_M4_MASK
Definition riscv/opcodes.hpp:10522
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR32M_M2
@ PseudoVFMERGE_VFPR32M_M2
Definition riscv/opcodes.hpp:2124
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M1_MASK
@ PseudoVSUXSEG3EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10824
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_M4
@ PseudoVLSEG2E8FF_V_M4
Definition riscv/opcodes.hpp:5106
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF8_MASK
@ PseudoVMULHU_VV_MF8_MASK
Definition riscv/opcodes.hpp:7318
LIEF::assembly::riscv::OPCODE::VLSE16_V
@ VLSE16_V
Definition riscv/opcodes.hpp:13364
LIEF::assembly::riscv::OPCODE::CV_MACSRN
@ CV_MACSRN
Definition riscv/opcodes.hpp:12339
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF4_MF2_MASK
@ PseudoVLUXSEG4EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:5995
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF4
@ PseudoVRSUB_VX_MF4
Definition riscv/opcodes.hpp:8600
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M2_MASK
@ PseudoVLUXSEG3EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:5953
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M4_E32_MASK
@ PseudoVFWADD_WFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3502
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M4_MASK
@ PseudoTHVdotVMAQA_VX_M4_MASK
Definition riscv/opcodes.hpp:515
LIEF::assembly::riscv::OPCODE::G_SCMP
@ G_SCMP
Definition riscv/opcodes.hpp:167
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_MF8_MASK
@ PseudoVOR_VV_MF8_MASK
Definition riscv/opcodes.hpp:7653
LIEF::assembly::riscv::OPCODE::MOPR8
@ MOPR8
Definition riscv/opcodes.hpp:12890
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M4_E32
@ PseudoVFWNMACC_VV_M4_E32
Definition riscv/opcodes.hpp:3867
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF8_MASK
@ PseudoVSLL_VI_MF8_MASK
Definition riscv/opcodes.hpp:8891
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF4_MASK
@ PseudoVSSEG4E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10080
LIEF::assembly::riscv::OPCODE::AMOAND_W_RL
@ AMOAND_W_RL
Definition riscv/opcodes.hpp:11978
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E32_V_MF2
@ PseudoVLSSEG8E32_V_MF2
Definition riscv/opcodes.hpp:5558
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M2_M1_MASK
@ PseudoVSOXSEG2EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9234
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M8_M4
@ PseudoVSOXSEG2EI32_V_M8_M4
Definition riscv/opcodes.hpp:9215
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_M1_MASK
@ PseudoVLOXSEG3EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4491
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_MF2_MASK
@ PseudoVSUXSEG4EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:10974
LIEF::assembly::riscv::OPCODE::G_BSWAP
@ G_BSWAP
Definition riscv/opcodes.hpp:260
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_M1
@ PseudoVSUXSEG4EI16_V_MF2_M1
Definition riscv/opcodes.hpp:10917
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_M2
@ PseudoVMSBC_VV_M2
Definition riscv/opcodes.hpp:6918
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E64_MASK
@ PseudoVREDAND_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:7705
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B32
@ PseudoVCPOP_M_B32
Definition riscv/opcodes.hpp:1042
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M8
@ PseudoVFMV_V_FPR32_M8
Definition riscv/opcodes.hpp:2411
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M4
@ PseudoVSUXEI8_V_M2_M4
Definition riscv/opcodes.hpp:10625
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M8
@ PseudoVSSE8_V_M8
Definition riscv/opcodes.hpp:9983
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E32_MASK
@ PseudoVFMACC_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:1994
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF8
@ PseudoVLOXEI8_V_MF8_MF8
Definition riscv/opcodes.hpp:4332
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_MF2_E32_MASK
@ PseudoVFMSUB_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2273
LIEF::assembly::riscv::OPCODE::VFWSUB_WV
@ VFWSUB_WV
Definition riscv/opcodes.hpp:13302
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_M8
@ PseudoVC_V_FPR16V_M8
Definition riscv/opcodes.hpp:1193
LIEF::assembly::riscv::OPCODE::VWSLL_VI
@ VWSLL_VI
Definition riscv/opcodes.hpp:13827
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_MF8
@ PseudoVREV8_V_MF8
Definition riscv/opcodes.hpp:8272
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF4_MASK
@ PseudoVSUXSEG3EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:10830
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF8_MASK
@ PseudoVLUXEI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:5725
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M1_E64
@ PseudoVFMUL_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2334
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M2_MASK
@ PseudoVSRL_VI_M2_MASK
Definition riscv/opcodes.hpp:9908
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF4_MF4_MASK
@ PseudoVLUXSEG3EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:5963
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF4_MASK
@ PseudoVSOXSEG5EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:9588
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_MF2_E32
@ PseudoVFNMADD_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2695
LIEF::assembly::riscv::OPCODE::TH_LRH
@ TH_LRH
Definition riscv/opcodes.hpp:13075
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16_V_MF2
@ PseudoVLSEG6E16_V_MF2
Definition riscv/opcodes.hpp:5286
LIEF::assembly::riscv::OPCODE::VSOXSEG5EI8_V
@ VSOXSEG5EI8_V
Definition riscv/opcodes.hpp:13679
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E32
@ PseudoVFDIV_VV_M4_E32
Definition riscv/opcodes.hpp:1907
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M4_E32_MASK
@ PseudoVFREDUSUM_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:3040
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M8_MASK
@ PseudoVMULHSU_VX_M8_MASK
Definition riscv/opcodes.hpp:7298
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M1_E32_MASK
@ PseudoVFSUB_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3424
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E32FF_V_MF2
@ PseudoVLSEG4E32FF_V_MF2
Definition riscv/opcodes.hpp:5202
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_M2
@ PseudoVMINU_VX_M2
Definition riscv/opcodes.hpp:6842
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1_MASK
@ PseudoVWADDU_WV_M1_MASK
Definition riscv/opcodes.hpp:11360
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M4_M1_MASK
@ PseudoVLOXSEG3EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4543
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M4_E32_MASK
@ PseudoVFWADD_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3466
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8FF_V_MF2
@ PseudoVLSEG2E8FF_V_MF2
Definition riscv/opcodes.hpp:5108
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M8_MASK
@ PseudoVLSE8_V_M8_MASK
Definition riscv/opcodes.hpp:5047
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_MF2_MASK
@ PseudoVLUXSEG7EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6245
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF4_MASK
@ PseudoVSRL_VI_MF4_MASK
Definition riscv/opcodes.hpp:9916
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF2_M2_MASK
@ PseudoVLUXEI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:5705
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M2_M1_MASK
@ PseudoVSUXSEG7EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11224
LIEF::assembly::riscv::OPCODE::VC_V_I
@ VC_V_I
Definition riscv/opcodes.hpp:13185
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M2_M2
@ PseudoVSUXSEG2EI8_V_M2_M2
Definition riscv/opcodes.hpp:10765
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_M1_MASK
@ PseudoVLOXEI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4251
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E32
@ PseudoVREM_VX_M2_E32
Definition riscv/opcodes.hpp:8226
LIEF::assembly::riscv::OPCODE::CV_DOTSP_SC_H
@ CV_DOTSP_SC_H
Definition riscv/opcodes.hpp:12286
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_MF2
@ PseudoVROR_VV_MF2
Definition riscv/opcodes.hpp:8556
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M1_E32
@ PseudoVFWADD_WV_M1_E32
Definition riscv/opcodes.hpp:3509
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF2_MASK
@ PseudoVLUXSEG3EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:5885
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_M2_MF2
@ PseudoVSUXSEG7EI32_V_M2_MF2
Definition riscv/opcodes.hpp:11203
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_MF2
@ PseudoVMULH_VX_MF2
Definition riscv/opcodes.hpp:7355
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_M4
@ PseudoVSM4R_VS_M4_M4
Definition riscv/opcodes.hpp:8946
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_MF4
@ PseudoVRELOAD2_MF4
Definition riscv/opcodes.hpp:8056
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_MF2_E16_MASK
@ PseudoVFMADD_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:2006
LIEF::assembly::riscv::OPCODE::SRET
@ SRET
Definition riscv/opcodes.hpp:12999
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI32_V_M1_M1
@ PseudoVSUXSEG8EI32_V_M1_M1
Definition riscv/opcodes.hpp:11275
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E16_V_MF2
@ PseudoVLSSEG8E16_V_MF2
Definition riscv/opcodes.hpp:5552
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E64
@ PseudoVFADD_VV_M8_E64
Definition riscv/opcodes.hpp:1651
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_MF2
@ PseudoVSEXT_VF2_MF2
Definition riscv/opcodes.hpp:8757
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_MF2_MASK
@ PseudoVWMACCSU_VX_MF2_MASK
Definition riscv/opcodes.hpp:11474
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M4
@ PseudoVSRL_VV_M4
Definition riscv/opcodes.hpp:9923
LIEF::assembly::riscv::OPCODE::QK_C_SBSP
@ QK_C_SBSP
Definition riscv/opcodes.hpp:12921
LIEF::assembly::riscv::OPCODE::FSGNJX_D
@ FSGNJX_D
Definition riscv/opcodes.hpp:12764
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M4
@ PseudoVASUB_VX_M4
Definition riscv/opcodes.hpp:906
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B64
@ PseudoVMSBF_M_B64
Definition riscv/opcodes.hpp:6948
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M1_E64_MASK
@ PseudoVFMUL_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:2347
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_M1_MASK_TIED
@ PseudoVWSUB_WV_M1_MASK_TIED
Definition riscv/opcodes.hpp:11805
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VVM_M2
@ PseudoVMSBC_VVM_M2
Definition riscv/opcodes.hpp:6911
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_M8
@ PseudoVADD_VX_M8
Definition riscv/opcodes.hpp:632
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M1_MF8_MASK
@ PseudoVLOXSEG7EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:4897
LIEF::assembly::riscv::OPCODE::VNMSUB_VV
@ VNMSUB_VV
Definition riscv/opcodes.hpp:13575
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD8_MF2
@ PseudoVRELOAD8_MF2
Definition riscv/opcodes.hpp:8081
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF2_E16
@ PseudoVFADD_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:1607
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF4
@ PseudoVLOXSEG3EI32_V_M1_MF4
Definition riscv/opcodes.hpp:4504
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M4_MASK
@ PseudoVWMACC_VV_M4_MASK
Definition riscv/opcodes.hpp:11520
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M4
@ PseudoVWMACCSU_VX_M4
Definition riscv/opcodes.hpp:11471
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M4_MASK
@ PseudoVNMSUB_VV_M4_MASK
Definition riscv/opcodes.hpp:7531
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16_V_M1_MASK
@ PseudoVLSEG7E16_V_M1_MASK
Definition riscv/opcodes.hpp:5325
LIEF::assembly::riscv::OPCODE::AMOADD_W
@ AMOADD_W
Definition riscv/opcodes.hpp:11959
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E32_V_MF2_MASK
@ PseudoVSSSEG5E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10348
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI16_V_MF4_MF2
@ PseudoVLOXSEG6EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:4784
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M1_E16_MASK
@ PseudoVFWMACC_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3732
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WV_M4
@ PseudoVNSRL_WV_M4
Definition riscv/opcodes.hpp:7606
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M2
@ PseudoVZEXT_VF2_M2
Definition riscv/opcodes.hpp:11883
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK
@ PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK
Definition riscv/opcodes.hpp:2432
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_MF2_E16_MASK
@ PseudoVFMADD_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:2052
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E32_MASK
@ PseudoVFCVT_F_X_V_M1_E32_MASK
Definition riscv/opcodes.hpp:1704
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M1_E8_MASK
@ PseudoVWREDSUMU_VS_M1_E8_MASK
Definition riscv/opcodes.hpp:11616
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M1_M1_MASK
@ PseudoVLOXSEG6EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4791
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E32_MASK
@ PseudoVREDMAX_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:7815
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_MF2_MF2
@ PseudoVAESDF_VS_MF2_MF2
Definition riscv/opcodes.hpp:661
LIEF::assembly::riscv::OPCODE::PATCHABLE_FUNCTION_ENTER
@ PATCHABLE_FUNCTION_ENTER
Definition riscv/opcodes.hpp:59
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF4
@ PseudoVSSSEG7E8_V_MF4
Definition riscv/opcodes.hpp:10395
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_MF8_MASK
@ PseudoVAADD_VV_MF8_MASK
Definition riscv/opcodes.hpp:562
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VV_M1_MASK
@ PseudoVWSUBU_VV_M1_MASK
Definition riscv/opcodes.hpp:11720
LIEF::assembly::riscv::OPCODE::VSSEG5E16_V
@ VSSEG5E16_V
Definition riscv/opcodes.hpp:13714
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M1_E16_MASK
@ PseudoVFNMACC_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:2646
LIEF::assembly::riscv::OPCODE::PseudoVSPILL5_MF2
@ PseudoVSPILL5_MF2
Definition riscv/opcodes.hpp:9848
LIEF::assembly::riscv::OPCODE::SH2ADD
@ SH2ADD
Definition riscv/opcodes.hpp:12961
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR64_M1_E64_MASK
@ PseudoVFMACC_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:1960
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF8_MASK
@ PseudoVLSSEG2E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5433
LIEF::assembly::riscv::OPCODE::VC_V_VVV
@ VC_V_VVV
Definition riscv/opcodes.hpp:13190
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E16
@ PseudoVFMSAC_VV_M1_E16
Definition riscv/opcodes.hpp:2222
LIEF::assembly::riscv::OPCODE::VREDMINU_VS
@ VREDMINU_VS
Definition riscv/opcodes.hpp:13597
LIEF::assembly::riscv::OPCODE::VLSEG8E32FF_V
@ VLSEG8E32FF_V
Definition riscv/opcodes.hpp:13418
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M8_MASK
@ PseudoVMAX_VV_M8_MASK
Definition riscv/opcodes.hpp:6549
LIEF::assembly::riscv::OPCODE::CV_CMPGT_SC_B
@ CV_CMPGT_SC_B
Definition riscv/opcodes.hpp:12239
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR64_M1
@ PseudoVFMV_S_FPR64_M1
Definition riscv/opcodes.hpp:2398
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32FF_V_MF2
@ PseudoVLSEG7E32FF_V_MF2
Definition riscv/opcodes.hpp:5332
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_MF2
@ PseudoVC_V_X_SE_MF2
Definition riscv/opcodes.hpp:1393
LIEF::assembly::riscv::OPCODE::TH_DCACHE_CPAL1
@ TH_DCACHE_CPAL1
Definition riscv/opcodes.hpp:13034
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_M4_E16_MASK
@ PseudoVFWSUB_WFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3996
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VV_M8
@ PseudoVSSRA_VV_M8
Definition riscv/opcodes.hpp:10183
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E16
@ PseudoVFSGNJN_VV_M4_E16
Definition riscv/opcodes.hpp:3163
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF4
@ PseudoVMFLE_VV_MF4
Definition riscv/opcodes.hpp:6740
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M4_M1
@ PseudoVLOXSEG6EI64_V_M4_M1
Definition riscv/opcodes.hpp:4824
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M2_E64_MASK
@ PseudoVFSUB_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:3416
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E32
@ PseudoVFCVT_F_XU_V_M8_E32
Definition riscv/opcodes.hpp:1691
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK
@ PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK
Definition riscv/opcodes.hpp:2560
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E16_V_MF4
@ PseudoVSSEG8E16_V_MF4
Definition riscv/opcodes.hpp:10147
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M4_M1
@ PseudoVSOXSEG8EI64_V_M4_M1
Definition riscv/opcodes.hpp:9805
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_MF2
@ PseudoVRELOAD2_MF2
Definition riscv/opcodes.hpp:8055
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_M1
@ PseudoVSUXSEG3EI32_V_M1_M1
Definition riscv/opcodes.hpp:10823
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF4
@ PseudoVLSEG7E16FF_V_MF4
Definition riscv/opcodes.hpp:5322
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF2_E32
@ PseudoVREDSUM_VS_MF2_E32
Definition riscv/opcodes.hpp:7998
LIEF::assembly::riscv::OPCODE::VFIRST_M
@ VFIRST_M
Definition riscv/opcodes.hpp:13215
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E64_MASK
@ PseudoVFREDUSUM_VS_M2_E64_MASK
Definition riscv/opcodes.hpp:3036
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_MF2
@ PseudoVLUXSEG2EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:5844
LIEF::assembly::riscv::OPCODE::C_ADDI_HINT_IMM_ZERO
@ C_ADDI_HINT_IMM_ZERO
Definition riscv/opcodes.hpp:12480
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M2_E32_MASK
@ PseudoVREDAND_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:7711
LIEF::assembly::riscv::OPCODE::CSRRCI
@ CSRRCI
Definition riscv/opcodes.hpp:12154
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_M2_M1_MASK
@ PseudoVLOXSEG6EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4797
LIEF::assembly::riscv::OPCODE::InsnCIW
@ InsnCIW
Definition riscv/opcodes.hpp:12817
LIEF::assembly::riscv::OPCODE::VMADC_VVM
@ VMADC_VVM
Definition riscv/opcodes.hpp:13489
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M1_MASK
@ PseudoVLUXSEG2EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:5735
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_MF2
@ PseudoVC_V_XVW_MF2
Definition riscv/opcodes.hpp:1359
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_MF4_MASK
@ PseudoVNCLIPU_WX_MF4_MASK
Definition riscv/opcodes.hpp:7459
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF2_E8_MASK
@ PseudoVDIVU_VV_MF2_E8_MASK
Definition riscv/opcodes.hpp:1460
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_M1
@ PseudoVLSEG8E16_V_M1
Definition riscv/opcodes.hpp:5364
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF2
@ PseudoVSOXEI32_V_M1_MF2
Definition riscv/opcodes.hpp:9045
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B32_MASK
@ PseudoVMSIF_M_B32_MASK
Definition riscv/opcodes.hpp:7072
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M2_E64_MASK
@ PseudoVFMSUB_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:2293
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M2_E64
@ PseudoVFNMSUB_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2819
LIEF::assembly::riscv::OPCODE::PseudoVADD_VI_MF4_MASK
@ PseudoVADD_VI_MF4_MASK
Definition riscv/opcodes.hpp:609
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E32
@ PseudoVREDMAXU_VS_M2_E32
Definition riscv/opcodes.hpp:7754
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M2_E64
@ PseudoVFMAX_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2081
LIEF::assembly::riscv::OPCODE::VFMADD_VV
@ VFMADD_VV
Definition riscv/opcodes.hpp:13219
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E16_MASK
@ PseudoVFWMACC_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3754
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E8
@ PseudoVREDAND_VS_M8_E8
Definition riscv/opcodes.hpp:7730
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M2_MASK
@ PseudoVSOXSEG2EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9258
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR32_M2_E32
@ PseudoVFWADD_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3463
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M1_MF2_MASK
@ PseudoVLUXSEG5EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6105
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF2_MASK
@ PseudoVLUXSEG4EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6031
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF8_MF8
@ PseudoVLUXSEG2EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:5860
LIEF::assembly::riscv::OPCODE::TH_LURBU
@ TH_LURBU
Definition riscv/opcodes.hpp:13080
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF2_MASK
@ PseudoVSOXSEG8EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9760
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E16_MASK
@ PseudoVREM_VX_M8_E16_MASK
Definition riscv/opcodes.hpp:8241
LIEF::assembly::riscv::OPCODE::PseudoVSE64_V_M1
@ PseudoVSE64_V_M1
Definition riscv/opcodes.hpp:8724
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_MF2
@ PseudoVLUXSEG4EI16_V_M1_MF2
Definition riscv/opcodes.hpp:5976
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M1_MF2_MASK
@ PseudoVLOXSEG2EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4341
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M8_M1_MASK
@ PseudoVSOXSEG8EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:9810
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M2_M1_MASK
@ PseudoVLOXSEG8EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4935
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF8_MASK
@ PseudoVSLL_VV_MF8_MASK
Definition riscv/opcodes.hpp:8905
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E16
@ PseudoVFNMSUB_VV_M4_E16
Definition riscv/opcodes.hpp:2837
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32_MASK
@ PseudoVFWSUB_WV_M4_E32_MASK
Definition riscv/opcodes.hpp:4030
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_M1
@ PseudoVSADD_VI_M1
Definition riscv/opcodes.hpp:8646
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M4
@ PseudoVNCLIP_WI_M4
Definition riscv/opcodes.hpp:7466
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E8_V_MF2_MASK
@ PseudoVSSSEG8E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10414
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VV_M8_MASK
@ PseudoVAADD_VV_M8_MASK
Definition riscv/opcodes.hpp:556
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M4_MF2_MASK
@ PseudoVLOXSEG4EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:4657
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF4_MASK
@ PseudoVSE8_V_MF4_MASK
Definition riscv/opcodes.hpp:8743
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_M2
@ PseudoVLUXSEG4EI32_V_M1_M2
Definition riscv/opcodes.hpp:6002
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M2
@ PseudoVLUXEI16_V_M4_M2
Definition riscv/opcodes.hpp:5586
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M4_MASK
@ PseudoVFCVT_RTZ_X_F_V_M4_MASK
Definition riscv/opcodes.hpp:1832
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF8
@ PseudoVWSUBU_VX_MF8
Definition riscv/opcodes.hpp:11741
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF2_MF2_MASK
@ PseudoVLUXEI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:5601
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF8_MASK
@ PseudoVSOXSEG3EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:9354
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_M8
@ PseudoVSLL_VX_M8
Definition riscv/opcodes.hpp:8912
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_MF2_MASK
@ PseudoTHVdotVMAQAU_VV_MF2_MASK
Definition riscv/opcodes.hpp:489
LIEF::assembly::riscv::OPCODE::InsnR4
@ InsnR4
Definition riscv/opcodes.hpp:12827
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E16FF_V_MF4_MASK
@ PseudoVLSEG3E16FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5133
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI64_V_M2_MF4
@ PseudoVSOXSEG5EI64_V_M2_MF4
Definition riscv/opcodes.hpp:9563
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M4_MASK
@ PseudoVSOXEI8_V_M2_M4_MASK
Definition riscv/opcodes.hpp:9122
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E16FF_V_MF4_MASK
@ PseudoVLSEG7E16FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5323
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF4
@ PseudoVLOXEI64_V_M1_MF4
Definition riscv/opcodes.hpp:4262
LIEF::assembly::riscv::OPCODE::PseudoVQMACC_4x8x4_M4
@ PseudoVQMACC_4x8x4_M4
Definition riscv/opcodes.hpp:7698
LIEF::assembly::riscv::OPCODE::FCLASS_H_INX
@ FCLASS_H_INX
Definition riscv/opcodes.hpp:12569
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E16
@ PseudoVFWNMSAC_VV_MF2_E16
Definition riscv/opcodes.hpp:3905
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M2
@ PseudoVMSLEU_VI_M2
Definition riscv/opcodes.hpp:7081
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M2_E64
@ PseudoVREDOR_VS_M2_E64
Definition riscv/opcodes.hpp:7932
LIEF::assembly::riscv::OPCODE::AMOXOR_D
@ AMOXOR_D
Definition riscv/opcodes.hpp:12103
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B64_MASK
@ PseudoVMSOF_M_B64_MASK
Definition riscv/opcodes.hpp:7274
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_MF4
@ PseudoVMSLEU_VX_MF4
Definition riscv/opcodes.hpp:7117
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E32_MASK
@ PseudoVDIVU_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:1450
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E32_MASK
@ PseudoVFMUL_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:2357
LIEF::assembly::riscv::OPCODE::CV_ADD_SCI_B
@ CV_ADD_SCI_B
Definition riscv/opcodes.hpp:12177
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M1
@ PseudoVLUXEI64_V_M2_M1
Definition riscv/opcodes.hpp:5658
LIEF::assembly::riscv::OPCODE::FCVT_S_WU_INX
@ FCVT_S_WU_INX
Definition riscv/opcodes.hpp:12627
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M2
@ PseudoVROR_VV_M2
Definition riscv/opcodes.hpp:8550
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M2_E64_MASK
@ PseudoVFSGNJN_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:3162
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_M2
@ PseudoVLOXEI32_V_M1_M2
Definition riscv/opcodes.hpp:4222
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E16_MASK
@ PseudoVFNMSAC_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:2784
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF4
@ PseudoVSOXSEG4EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:9419
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF2_E16
@ PseudoVFSGNJX_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3189
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M8_MASK
@ PseudoVSRA_VV_M8_MASK
Definition riscv/opcodes.hpp:9884
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M8
@ PseudoVFCLASS_V_M8
Definition riscv/opcodes.hpp:1665
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_M1
@ PseudoVSSEG4E8_V_M1
Definition riscv/opcodes.hpp:10073
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF4_E16
@ PseudoVFCVT_F_X_V_MF4_E16
Definition riscv/opcodes.hpp:1729
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M8_M4
@ PseudoVSOXSEG2EI64_V_M8_M4
Definition riscv/opcodes.hpp:9253
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_MF4_MASK
@ PseudoVSLIDEDOWN_VI_MF4_MASK
Definition riscv/opcodes.hpp:8833
LIEF::assembly::riscv::OPCODE::THVdotVMAQA_VV
@ THVdotVMAQA_VV
Definition riscv/opcodes.hpp:13025
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF2_MASK
@ PseudoVLSSEG3E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5439
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M4
@ PseudoVLUXEI8_V_M2_M4
Definition riscv/opcodes.hpp:5692
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E16_MASK
@ PseudoVFREDUSUM_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:3050
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF4
@ PseudoVSUXSEG4EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:10923
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M4
@ PseudoVWADD_VX_M4
Definition riscv/opcodes.hpp:11411
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_M1
@ PseudoVSSSEG7E16_V_M1
Definition riscv/opcodes.hpp:10379
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR16_MF2_E16_MASK
@ PseudoVFADD_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:1608
LIEF::assembly::riscv::OPCODE::G_BRJT
@ G_BRJT
Definition riscv/opcodes.hpp:246
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_M1
@ PseudoVSUXSEG6EI8_V_MF2_M1
Definition riscv/opcodes.hpp:11157
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32FF_V_M2_MASK
@ PseudoVLSEG2E32FF_V_M2_MASK
Definition riscv/opcodes.hpp:5077
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_MF2
@ PseudoVLUXSEG7EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:6276
LIEF::assembly::riscv::OPCODE::LOCAL_ESCAPE
@ LOCAL_ESCAPE
Definition riscv/opcodes.hpp:56
LIEF::assembly::riscv::OPCODE::CV_MAX_SCI_H
@ CV_MAX_SCI_H
Definition riscv/opcodes.hpp:12353
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M2_MASK
@ PseudoVSSEG3E32_V_M2_MASK
Definition riscv/opcodes.hpp:10038
LIEF::assembly::riscv::OPCODE::G_PTR_ADD
@ G_PTR_ADD
Definition riscv/opcodes.hpp:236
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E64_MASK
@ PseudoVFCVT_RM_F_XU_V_M4_E64_MASK
Definition riscv/opcodes.hpp:1748
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VFPR32_M8_E32
@ PseudoVFNMACC_VFPR32_M8_E32
Definition riscv/opcodes.hpp:2633
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M1
@ PseudoVSRA_VI_M1
Definition riscv/opcodes.hpp:9863
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_MF2
@ PseudoVLSSEG7E32_V_MF2
Definition riscv/opcodes.hpp:5538
LIEF::assembly::riscv::OPCODE::VSUXSEG5EI32_V
@ VSUXSEG5EI32_V
Definition riscv/opcodes.hpp:13787
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_X_F_V_M8
@ PseudoVFCVT_X_F_V_M8
Definition riscv/opcodes.hpp:1857
LIEF::assembly::riscv::OPCODE::PseudoVLSE32_V_MF2
@ PseudoVLSE32_V_MF2
Definition riscv/opcodes.hpp:5030
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_MF8
@ PseudoVMADC_VIM_MF8
Definition riscv/opcodes.hpp:6436
LIEF::assembly::riscv::OPCODE::VLUXSEG6EI8_V
@ VLUXSEG6EI8_V
Definition riscv/opcodes.hpp:13475
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E64_V_M2
@ PseudoVSSEG4E64_V_M2
Definition riscv/opcodes.hpp:10071
LIEF::assembly::riscv::OPCODE::VLUXEI64_V
@ VLUXEI64_V
Definition riscv/opcodes.hpp:13454
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_MF2
@ PseudoVSUXSEG4EI16_V_M1_MF2
Definition riscv/opcodes.hpp:10909
LIEF::assembly::riscv::OPCODE::TH_SURB
@ TH_SURB
Definition riscv/opcodes.hpp:13116
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_M8
@ PseudoVFMV_FPR16_S_M8
Definition riscv/opcodes.hpp:2375
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M8
@ PseudoVSSRA_VI_M8
Definition riscv/opcodes.hpp:10169
LIEF::assembly::riscv::OPCODE::G_DYN_STACKALLOC
@ G_DYN_STACKALLOC
Definition riscv/opcodes.hpp:279
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR16_M1_E16
@ PseudoVFSGNJ_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3241
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF4_MASK
@ PseudoVLSSEG4E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5487
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQASU_VX_M8_MASK
@ PseudoTHVdotVMAQASU_VX_M8_MASK
Definition riscv/opcodes.hpp:467
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VX_M1
@ PseudoVRGATHER_VX_M1
Definition riscv/opcodes.hpp:8492
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M4_MASK
@ PseudoVMSEQ_VI_M4_MASK
Definition riscv/opcodes.hpp:6957
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK
@ PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK
Definition riscv/opcodes.hpp:8415
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M1
@ PseudoVSLIDE1DOWN_VX_M1
Definition riscv/opcodes.hpp:8794
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E8
@ PseudoVREMU_VX_M4_E8
Definition riscv/opcodes.hpp:8150
LIEF::assembly::riscv::OPCODE::VFREDMIN_VS
@ VFREDMIN_VS
Definition riscv/opcodes.hpp:13256
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_M4
@ PseudoVMSEQ_VI_M4
Definition riscv/opcodes.hpp:6956
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E32
@ PseudoVFSUB_VV_M2_E32
Definition riscv/opcodes.hpp:3429
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VI_M2
@ PseudoVMADC_VI_M2
Definition riscv/opcodes.hpp:6438
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF2
@ PseudoVSUXEI16_V_MF2_MF2
Definition riscv/opcodes.hpp:10533
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M8_E32_MASK
@ PseudoVFMIN_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:2183
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_MF2
@ PseudoVLSEG4E8_V_MF2
Definition riscv/opcodes.hpp:5232
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_MF8
@ PseudoVMULHU_VV_MF8
Definition riscv/opcodes.hpp:7317
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M8_M4
@ PseudoVSOXEI32_V_M8_M4
Definition riscv/opcodes.hpp:9067
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF2_E32
@ PseudoVREDAND_VS_MF2_E32
Definition riscv/opcodes.hpp:7734
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16_MASK
@ PseudoVFWSUB_WV_MF4_E16_MASK
Definition riscv/opcodes.hpp:4042
LIEF::assembly::riscv::OPCODE::FMUL_H
@ FMUL_H
Definition riscv/opcodes.hpp:12723
LIEF::assembly::riscv::OPCODE::AES64DS
@ AES64DS
Definition riscv/opcodes.hpp:11940
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_M1
@ PseudoVLOXSEG5EI32_V_M2_M1
Definition riscv/opcodes.hpp:4716
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M2_E32_MASK
@ PseudoVFWMSAC_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3780
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF2
@ PseudoVLOXSEG8EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:4998
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK
@ PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK
Definition riscv/opcodes.hpp:8321
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI64_V_M2_MF4_MASK
@ PseudoVLOXSEG5EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:4743
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VV_MF4
@ PseudoVMSBC_VV_MF4
Definition riscv/opcodes.hpp:6922
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_MF2
@ PseudoVBREV8_V_MF2
Definition riscv/opcodes.hpp:924
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M4_MASK
@ PseudoVSUXSEG2EI16_V_M4_M4_MASK
Definition riscv/opcodes.hpp:10676
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E32_MASK
@ PseudoVFSGNJX_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:3232
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M1
@ PseudoVLUXSEG2EI32_V_M4_M1
Definition riscv/opcodes.hpp:5778
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_M1_MASK
@ PseudoVLSEG3E32FF_V_M1_MASK
Definition riscv/opcodes.hpp:5143
LIEF::assembly::riscv::OPCODE::PseudoVC_IVV_SE_M8
@ PseudoVC_IVV_SE_M8
Definition riscv/opcodes.hpp:1122
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_M1_MASK
@ PseudoVLOXSEG3EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4527
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8_V_MF2
@ PseudoVLSEG7E8_V_MF2
Definition riscv/opcodes.hpp:5352
LIEF::assembly::riscv::OPCODE::FCVT_D_H
@ FCVT_D_H
Definition riscv/opcodes.hpp:12574
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M2
@ PseudoVOR_VX_M2
Definition riscv/opcodes.hpp:7656
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_XU_F_V_M2
@ PseudoVFWCVT_RTZ_XU_F_V_M2
Definition riscv/opcodes.hpp:3659
LIEF::assembly::riscv::OPCODE::AMOOR_B_AQ_RL
@ AMOOR_B_AQ_RL
Definition riscv/opcodes.hpp:12069
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_M1_MASK
@ PseudoVLSEG6E8FF_V_M1_MASK
Definition riscv/opcodes.hpp:5303
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_M4_MASK
@ PseudoVSOXSEG2EI8_V_MF2_M4_MASK
Definition riscv/opcodes.hpp:9272
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF8_MASK
@ PseudoVSUXSEG2EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:10694
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_M1_MF2_MASK
@ PseudoVSUXSEG5EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11038
LIEF::assembly::riscv::OPCODE::WRS_STO
@ WRS_STO
Definition riscv/opcodes.hpp:13846
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF8_MF4
@ PseudoVSUXSEG6EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:11171
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_MF2
@ PseudoVMADC_VIM_MF2
Definition riscv/opcodes.hpp:6434
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_M1
@ PseudoVSUXEI8_V_MF8_M1
Definition riscv/opcodes.hpp:10651
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M2_MASK
@ PseudoVASUB_VV_M2_MASK
Definition riscv/opcodes.hpp:891
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_M1
@ PseudoVLOXSEG3EI32_V_MF2_M1
Definition riscv/opcodes.hpp:4518
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M2
@ PseudoVLUXSEG4EI64_V_M8_M2
Definition riscv/opcodes.hpp:6052
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_MF2_E32
@ PseudoVFMACC_VV_MF2_E32
Definition riscv/opcodes.hpp:1993
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M2_MASK
@ PseudoVLSSEG2E16_V_M2_MASK
Definition riscv/opcodes.hpp:5401
LIEF::assembly::riscv::OPCODE::PseudoVFWREDUSUM_VS_M1_E16
@ PseudoVFWREDUSUM_VS_M1_E16
Definition riscv/opcodes.hpp:3933
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M4_MASK
@ PseudoVASUB_VV_M4_MASK
Definition riscv/opcodes.hpp:893
LIEF::assembly::riscv::OPCODE::TH_FLRW
@ TH_FLRW
Definition riscv/opcodes.hpp:13047
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M1_MASK
@ PseudoVSUXEI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10592
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI32_V_M2_M2_MASK
@ PseudoVLUXEI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5623
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_MF2_MF8_MASK
@ PseudoVSOXSEG4EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:9456
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E8
@ PseudoVREDAND_VS_M1_E8
Definition riscv/opcodes.hpp:7706
LIEF::assembly::riscv::OPCODE::VC_FV
@ VC_FV
Definition riscv/opcodes.hpp:13172
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR16_M4
@ PseudoVFSLIDE1DOWN_VFPR16_M4
Definition riscv/opcodes.hpp:3305
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF4_M1
@ PseudoVLUXSEG7EI8_V_MF4_M1
Definition riscv/opcodes.hpp:6308
LIEF::assembly::riscv::OPCODE::VFMAX_VV
@ VFMAX_VV
Definition riscv/opcodes.hpp:13221
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF8_MASK
@ PseudoVSSEG5E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10102
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M1_M2_MASK
@ PseudoVLUXSEG4EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:6057
LIEF::assembly::riscv::OPCODE::PseudoVSSE64_V_M2
@ PseudoVSSE64_V_M2
Definition riscv/opcodes.hpp:9971
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M8_M8_MASK
@ PseudoVSOXEI64_V_M8_M8_MASK
Definition riscv/opcodes.hpp:9110
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M2_MF4_MASK
@ PseudoVLUXSEG2EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:5811
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI32_V_MF2_M1
@ PseudoVSUXSEG5EI32_V_MF2_M1
Definition riscv/opcodes.hpp:11047
LIEF::assembly::riscv::OPCODE::VSLIDE1DOWN_VX
@ VSLIDE1DOWN_VX
Definition riscv/opcodes.hpp:13643
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M1
@ PseudoVLOXSEG3EI8_V_M1_M1
Definition riscv/opcodes.hpp:4552
LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_MF4
@ PseudoVSPILL3_MF4
Definition riscv/opcodes.hpp:9840
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M8
@ PseudoVMFLE_VFPR32_M8
Definition riscv/opcodes.hpp:6718
LIEF::assembly::riscv::OPCODE::AMOMAX_W
@ AMOMAX_W
Definition riscv/opcodes.hpp:12031
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_M1_MF2
@ PseudoVSOXSEG5EI32_V_M1_MF2
Definition riscv/opcodes.hpp:9533
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M1
@ PseudoVFNCVT_RTZ_XU_F_W_M1
Definition riscv/opcodes.hpp:2567
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M4_M4_MASK
@ PseudoVLUXEI8_V_M4_M4_MASK
Definition riscv/opcodes.hpp:5697
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E64_V_M1
@ PseudoVSSSEG8E64_V_M1
Definition riscv/opcodes.hpp:10409
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M2_MF2
@ PseudoVLOXSEG2EI64_V_M2_MF2
Definition riscv/opcodes.hpp:4416
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VX_M2_MASK
@ PseudoVSSRL_VX_M2_MASK
Definition riscv/opcodes.hpp:10236
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_MF4
@ PseudoVC_V_IV_SE_MF4
Definition riscv/opcodes.hpp:1286
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_MF2
@ PseudoVLUXSEG5EI16_V_M1_MF2
Definition riscv/opcodes.hpp:6084
LIEF::assembly::riscv::OPCODE::VSUB_VV
@ VSUB_VV
Definition riscv/opcodes.hpp:13768
LIEF::assembly::riscv::OPCODE::FLE_D_IN32X
@ FLE_D_IN32X
Definition riscv/opcodes.hpp:12665
LIEF::assembly::riscv::OPCODE::VADD_VX
@ VADD_VX
Definition riscv/opcodes.hpp:13140
LIEF::assembly::riscv::OPCODE::G_VECREDUCE_SMAX
@ G_VECREDUCE_SMAX
Definition riscv/opcodes.hpp:313
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_M2_MASK
@ PseudoVFNCVT_XU_F_W_M2_MASK
Definition riscv/opcodes.hpp:2594
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M2_M4
@ PseudoVSUXEI32_V_M2_M4
Definition riscv/opcodes.hpp:10557
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E8_MASK
@ PseudoVFWCVT_F_XU_V_MF4_E8_MASK
Definition riscv/opcodes.hpp:3604
LIEF::assembly::riscv::OPCODE::PseudoZEXT_H
@ PseudoZEXT_H
Definition riscv/opcodes.hpp:11911
LIEF::assembly::riscv::OPCODE::PseudoVSPILL3_MF2
@ PseudoVSPILL3_MF2
Definition riscv/opcodes.hpp:9839
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_MF2_E16_MASK
@ PseudoVFCVT_F_X_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:1726
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M8_E64
@ PseudoVFADD_VFPR64_M8_E64
Definition riscv/opcodes.hpp:1627
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_M1
@ PseudoVCLMUL_VV_M1
Definition riscv/opcodes.hpp:972
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF8_MF2
@ PseudoVSOXSEG5EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:9585
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M2_M1
@ PseudoVLOXSEG8EI64_V_M2_M1
Definition riscv/opcodes.hpp:4978
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_M1
@ PseudoVLUXSEG3EI16_V_MF4_M1
Definition riscv/opcodes.hpp:5882
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_SE_MF2
@ PseudoVC_V_FPR32VW_SE_MF2
Definition riscv/opcodes.hpp:1221
LIEF::assembly::riscv::OPCODE::FSGNJN_H_INX
@ FSGNJN_H_INX
Definition riscv/opcodes.hpp:12761
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E8
@ PseudoVREM_VX_M4_E8
Definition riscv/opcodes.hpp:8238
LIEF::assembly::riscv::OPCODE::CV_PACKHI_B
@ CV_PACKHI_B
Definition riscv/opcodes.hpp:12386
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG6E16_V_M1_MASK
@ PseudoVLSSEG6E16_V_M1_MASK
Definition riscv/opcodes.hpp:5511
LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B8
@ PseudoVSM_V_B8
Definition riscv/opcodes.hpp:8998
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_M2_MASK
@ PseudoVNSRA_WV_M2_MASK
Definition riscv/opcodes.hpp:7569
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M2_MASK
@ PseudoVSUXEI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10506
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M2_MASK
@ PseudoVLSEG2E16_V_M2_MASK
Definition riscv/opcodes.hpp:5067
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF2
@ PseudoVSSRA_VI_MF2
Definition riscv/opcodes.hpp:10171
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_MF2
@ PseudoVSSSEG3E32_V_MF2
Definition riscv/opcodes.hpp:10295
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M4
@ PseudoVLUXSEG2EI8_V_MF2_M4
Definition riscv/opcodes.hpp:5842
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_M1_E32
@ PseudoVFWNMSAC_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3885
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF2_MASK
@ PseudoVANDN_VX_MF2_MASK
Definition riscv/opcodes.hpp:813
LIEF::assembly::riscv::OPCODE::PseudoVMSBC_VX_MF4
@ PseudoVMSBC_VX_MF4
Definition riscv/opcodes.hpp:6936
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M4_M1_MASK
@ PseudoVSOXSEG3EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:9334
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E8_MASK
@ PseudoVDIV_VX_M8_E8_MASK
Definition riscv/opcodes.hpp:1586
LIEF::assembly::riscv::OPCODE::VWSUB_WV
@ VWSUB_WV
Definition riscv/opcodes.hpp:13836
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E16
@ PseudoVFSGNJX_VV_M4_E16
Definition riscv/opcodes.hpp:3223
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR32_M4_E32_MASK
@ PseudoVFMADD_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:2014
LIEF::assembly::riscv::OPCODE::G_FCOS
@ G_FCOS
Definition riscv/opcodes.hpp:263
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M8_MASK
@ PseudoVSUXEI64_V_M8_M8_MASK
Definition riscv/opcodes.hpp:10614
LIEF::assembly::riscv::OPCODE::G_WRITE_REGISTER
@ G_WRITE_REGISTER
Definition riscv/opcodes.hpp:291
LIEF::assembly::riscv::OPCODE::AMOAND_W_AQ_RL
@ AMOAND_W_AQ_RL
Definition riscv/opcodes.hpp:11977
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E8_V_M4_MASK
@ PseudoVSSSEG2E8_V_M4_MASK
Definition riscv/opcodes.hpp:10276
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF2_MASK
@ PseudoVSUXSEG4EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10964
LIEF::assembly::riscv::OPCODE::AMOAND_D_AQ
@ AMOAND_D_AQ
Definition riscv/opcodes.hpp:11968
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E32_MASK
@ PseudoVFWREDOSUM_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:3922
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_FMAX
@ G_ATOMICRMW_FMAX
Definition riscv/opcodes.hpp:136
LIEF::assembly::riscv::OPCODE::BuildPairF64Pseudo
@ BuildPairF64Pseudo
Definition riscv/opcodes.hpp:321
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF2_MF2
@ PseudoVSOXSEG2EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:9273
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF2
@ PseudoVSSUBU_VX_MF2
Definition riscv/opcodes.hpp:10441
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_M1
@ PseudoVSUXSEG5EI16_V_M1_M1
Definition riscv/opcodes.hpp:11015
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_M1_MASK
@ PseudoVLUXSEG8EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:6335
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF2_M2_MASK
@ PseudoVSOXSEG4EI8_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:9492
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VV_MF2_E32_MASK
@ PseudoVFWSUB_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3988
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M2
@ PseudoVXOR_VV_M2
Definition riscv/opcodes.hpp:11855
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M1_TIED
@ PseudoVWSUBU_WV_M1_TIED
Definition riscv/opcodes.hpp:11746
LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B32
@ PseudoVMSET_M_B32
Definition riscv/opcodes.hpp:6997
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_MF2
@ PseudoVSOXSEG7EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:9705
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M8_E64_MASK
@ PseudoVFMAX_VFPR64_M8_E64_MASK
Definition riscv/opcodes.hpp:2086
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_M2
@ PseudoVC_V_I_SE_M2
Definition riscv/opcodes.hpp:1296
LIEF::assembly::riscv::OPCODE::VFWCVT_F_XU_V
@ VFWCVT_F_XU_V
Definition riscv/opcodes.hpp:13278
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M1_MASK
@ PseudoVMACC_VV_M1_MASK
Definition riscv/opcodes.hpp:6403
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M2_E64_MASK
@ PseudoVFSQRT_V_M2_E64_MASK
Definition riscv/opcodes.hpp:3372
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_MF2_MASK
@ PseudoVLOXSEG4EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4597
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M1
@ PseudoVSSEG2E32_V_M1
Definition riscv/opcodes.hpp:10001
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16_MASK_TIED
@ PseudoVFWADD_WV_M4_E16_MASK_TIED
Definition riscv/opcodes.hpp:3523
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF8_MASK
@ PseudoVMSEQ_VI_MF8_MASK
Definition riscv/opcodes.hpp:6965
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M8_MASK
@ PseudoVOR_VV_M8_MASK
Definition riscv/opcodes.hpp:7647
LIEF::assembly::riscv::OPCODE::PseudoVMSET_M_B8
@ PseudoVMSET_M_B8
Definition riscv/opcodes.hpp:7000
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E16_MASK
@ PseudoVFNMADD_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:2718
LIEF::assembly::riscv::OPCODE::PseudoLongBLTU
@ PseudoLongBLTU
Definition riscv/opcodes.hpp:405
LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicSwap32
@ PseudoMaskedAtomicSwap32
Definition riscv/opcodes.hpp:414
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E64
@ PseudoVREDXOR_VS_M4_E64
Definition riscv/opcodes.hpp:8028
LIEF::assembly::riscv::OPCODE::RORI
@ RORI
Definition riscv/opcodes.hpp:12933
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E16
@ PseudoVWREDSUM_VS_M2_E16
Definition riscv/opcodes.hpp:11653
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M8_MASK
@ PseudoVSLL_VI_M8_MASK
Definition riscv/opcodes.hpp:8885
LIEF::assembly::riscv::OPCODE::CV_AND_SC_H
@ CV_AND_SC_H
Definition riscv/opcodes.hpp:12186
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M1_MF8_MASK
@ PseudoVSUXSEG5EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:11062
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VV_MF8_MASK
@ PseudoVSADD_VV_MF8_MASK
Definition riscv/opcodes.hpp:8673
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E16_MASK
@ PseudoVDIVU_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:1432
LIEF::assembly::riscv::OPCODE::FSGNJN_S_INX
@ FSGNJN_S_INX
Definition riscv/opcodes.hpp:12763
LIEF::assembly::riscv::OPCODE::VLSEG6E64_V
@ VLSEG6E64_V
Definition riscv/opcodes.hpp:13405
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M2
@ PseudoVFMV_V_FPR64_M2
Definition riscv/opcodes.hpp:2414
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK
@ PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK
Definition riscv/opcodes.hpp:8401
LIEF::assembly::riscv::OPCODE::CV_EXTRACT_B
@ CV_EXTRACT_B
Definition riscv/opcodes.hpp:12310
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M4_M8
@ PseudoVLOXEI8_V_M4_M8
Definition riscv/opcodes.hpp:4306
LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_M2
@ PseudoVMOR_MM_M2
Definition riscv/opcodes.hpp:6904
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E16
@ PseudoVFDIV_VV_M4_E16
Definition riscv/opcodes.hpp:1905
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M1_MF2
@ PseudoVAESZ_VS_M1_MF2
Definition riscv/opcodes.hpp:767
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_M4
@ PseudoVWSUBU_VX_M4
Definition riscv/opcodes.hpp:11735
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_M1_MASK
@ PseudoVLUXSEG7EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6263
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M2
@ PseudoVAADDU_VV_M2
Definition riscv/opcodes.hpp:523
LIEF::assembly::riscv::OPCODE::CV_CLB
@ CV_CLB
Definition riscv/opcodes.hpp:12206
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M4_E32_MASK
@ PseudoVFNMADD_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:2720
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_M2_MASK
@ PseudoVSUXSEG3EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10870
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF2
@ PseudoVWSLL_VI_MF2
Definition riscv/opcodes.hpp:11689
LIEF::assembly::riscv::OPCODE::G_ANYEXT
@ G_ANYEXT
Definition riscv/opcodes.hpp:149
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF4_MASK
@ PseudoVLOXSEG7EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4867
LIEF::assembly::riscv::OPCODE::FCVT_D_L_INX
@ FCVT_D_L_INX
Definition riscv/opcodes.hpp:12580
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E16_MASK
@ PseudoVREDMAXU_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:7753
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_MF2_MASK
@ PseudoVFNCVT_RM_X_F_W_MF2_MASK
Definition riscv/opcodes.hpp:2544
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF4
@ PseudoVLUXSEG4EI64_V_M2_MF4
Definition riscv/opcodes.hpp:6042
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M2_E16
@ PseudoVFNMADD_VFPR16_M2_E16
Definition riscv/opcodes.hpp:2677
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WV_M1
@ PseudoVNCLIPU_WV_M1
Definition riscv/opcodes.hpp:7438
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E8_V_MF8
@ PseudoVLSSEG5E8_V_MF8
Definition riscv/opcodes.hpp:5508
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF4
@ PseudoVROR_VI_MF4
Definition riscv/opcodes.hpp:8544
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF2_E32
@ PseudoVFWNMSAC_VV_MF2_E32
Definition riscv/opcodes.hpp:3907
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E16
@ PseudoVFSQRT_V_M8_E16
Definition riscv/opcodes.hpp:3379
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_MF2
@ PseudoVAESEF_VS_M8_MF2
Definition riscv/opcodes.hpp:716
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E32
@ PseudoVWREDSUMU_VS_M8_E32
Definition riscv/opcodes.hpp:11631
LIEF::assembly::riscv::OPCODE::PseudoVSHA2MS_VV_M4
@ PseudoVSHA2MS_VV_M4
Definition riscv/opcodes.hpp:8791
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF2_MF4
@ PseudoVLOXSEG5EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:4700
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M4
@ PseudoVSUXSEG2EI8_V_M1_M4
Definition riscv/opcodes.hpp:10763
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_M2
@ PseudoVSOXSEG4EI32_V_M1_M2
Definition riscv/opcodes.hpp:9431
LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_LOOP
@ CONVERGENCECTRL_LOOP
Definition riscv/opcodes.hpp:70
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E64
@ PseudoVFCVT_F_XU_V_M2_E64
Definition riscv/opcodes.hpp:1681
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E16_MF8
@ PseudoVRGATHEREI16_VV_MF2_E16_MF8
Definition riscv/opcodes.hpp:8400
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_MF4
@ PseudoVSOXSEG4EI64_V_M2_MF4
Definition riscv/opcodes.hpp:9471
LIEF::assembly::riscv::OPCODE::CV_ADD_SCI_H
@ CV_ADD_SCI_H
Definition riscv/opcodes.hpp:12178
LIEF::assembly::riscv::OPCODE::G_BRINDIRECT
@ G_BRINDIRECT
Definition riscv/opcodes.hpp:143
LIEF::assembly::riscv::OPCODE::VQMACCU_4x8x4
@ VQMACCU_4x8x4
Definition riscv/opcodes.hpp:13591
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_MF2_MASK
@ PseudoVMSGTU_VX_MF2_MASK
Definition riscv/opcodes.hpp:7032
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M4
@ PseudoVSLIDEUP_VI_M4
Definition riscv/opcodes.hpp:8854
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E16_V_MF4_MASK
@ PseudoVLSSEG5E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5495
LIEF::assembly::riscv::OPCODE::VLSEG8E16_V
@ VLSEG8E16_V
Definition riscv/opcodes.hpp:13417
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M1_MASK
@ PseudoVSUB_VV_M1_MASK
Definition riscv/opcodes.hpp:10476
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E8
@ PseudoVREDXOR_VS_M2_E8
Definition riscv/opcodes.hpp:8022
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_M1_MASK
@ PseudoVSOXSEG7EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9720
LIEF::assembly::riscv::OPCODE::PseudoCCSRAIW
@ PseudoCCSRAIW
Definition riscv/opcodes.hpp:358
LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M4
@ PseudoVAESKF2_VI_M4
Definition riscv/opcodes.hpp:763
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M4_MASK
@ PseudoVMULHSU_VV_M4_MASK
Definition riscv/opcodes.hpp:7282
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E16_MASK
@ PseudoVFWREDOSUM_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:3928
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_M1
@ PseudoVLUXSEG4EI32_V_MF2_M1
Definition riscv/opcodes.hpp:6020
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_MF4_MASK
@ PseudoVSSRA_VX_MF4_MASK
Definition riscv/opcodes.hpp:10202
LIEF::assembly::riscv::OPCODE::PseudoVMXOR_MM_M8
@ PseudoVMXOR_MM_M8
Definition riscv/opcodes.hpp:7422
LIEF::assembly::riscv::OPCODE::CM_POPRET
@ CM_POPRET
Definition riscv/opcodes.hpp:12148
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E32
@ PseudoVFWADD_WV_M4_E32
Definition riscv/opcodes.hpp:3525
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF2
@ PseudoVWSLL_VX_MF2
Definition riscv/opcodes.hpp:11713
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF8_MASK
@ PseudoVWMUL_VV_MF8_MASK
Definition riscv/opcodes.hpp:11598
LIEF::assembly::riscv::OPCODE::PseudoVSM_V_B16
@ PseudoVSM_V_B16
Definition riscv/opcodes.hpp:8993
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E8
@ PseudoVREM_VV_M8_E8
Definition riscv/opcodes.hpp:8202
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M8
@ PseudoVREV8_V_M8
Definition riscv/opcodes.hpp:8266
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M4_MASK
@ PseudoVSUXEI8_V_M2_M4_MASK
Definition riscv/opcodes.hpp:10626
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M1_MASK
@ PseudoVMFLE_VV_M1_MASK
Definition riscv/opcodes.hpp:6731
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E32
@ PseudoVFWCVTBF16_F_F_V_MF2_E32
Definition riscv/opcodes.hpp:3555
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_MF4_MASK
@ PseudoVWMULSU_VV_MF4_MASK
Definition riscv/opcodes.hpp:11548
LIEF::assembly::riscv::OPCODE::VWADDU_WX
@ VWADDU_WX
Definition riscv/opcodes.hpp:13807
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_M8
@ PseudoVANDN_VV_M8
Definition riscv/opcodes.hpp:796
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M8_E32
@ PseudoVFCVT_RM_F_XU_V_M8_E32
Definition riscv/opcodes.hpp:1751
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M8_MASK
@ PseudoVMFLE_VFPR64_M8_MASK
Definition riscv/opcodes.hpp:6729
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF2_E16_MASK
@ PseudoVRGATHER_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:8481
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E16
@ PseudoVDIVU_VV_M8_E16
Definition riscv/opcodes.hpp:1447
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR16_M2_E16_MASK
@ PseudoVFMAX_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2060
LIEF::assembly::riscv::OPCODE::BNE
@ BNE
Definition riscv/opcodes.hpp:12130
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M8
@ PseudoVZEXT_VF2_M8
Definition riscv/opcodes.hpp:11887
LIEF::assembly::riscv::OPCODE::CV_SRL_SCI_H
@ CV_SRL_SCI_H
Definition riscv/opcodes.hpp:12440
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_MF2_MF4_MASK
@ PseudoVSOXSEG5EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9522
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M8_E8
@ PseudoVREDMAXU_VS_M8_E8
Definition riscv/opcodes.hpp:7774
LIEF::assembly::riscv::OPCODE::CV_AND_H
@ CV_AND_H
Definition riscv/opcodes.hpp:12182
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E32_MASK
@ PseudoVFMUL_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:2351
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E64_MASK
@ PseudoVFDIV_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:1910
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E8
@ PseudoVREM_VX_M2_E8
Definition riscv/opcodes.hpp:8230
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_M1_M1_MASK
@ PseudoVLUXSEG8EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6383
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M4_E64
@ PseudoVREM_VX_M4_E64
Definition riscv/opcodes.hpp:8236
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VI
@ PseudoVMSLT_VI
Definition riscv/opcodes.hpp:7192
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_M4_MASK
@ PseudoVCLMULH_VV_M4_MASK
Definition riscv/opcodes.hpp:949
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_M4_E16_MASK
@ PseudoVFNCVTBF16_F_F_W_M4_E16_MASK
Definition riscv/opcodes.hpp:2426
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD6_MF8
@ PseudoVRELOAD6_MF8
Definition riscv/opcodes.hpp:8075
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E8_M8_MASK
@ PseudoVRGATHEREI16_VV_M8_E8_M8_MASK
Definition riscv/opcodes.hpp:8393
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E16_MASK
@ PseudoVFADD_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:1648
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M2
@ PseudoVSLIDEDOWN_VI_M2
Definition riscv/opcodes.hpp:8824
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M2
@ PseudoVZEXT_VF4_M2
Definition riscv/opcodes.hpp:11895
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M2
@ PseudoVAESEF_VV_M2
Definition riscv/opcodes.hpp:723
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M1_MASK
@ PseudoVMINU_VV_M1_MASK
Definition riscv/opcodes.hpp:6827
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF2_M1_MASK
@ PseudoVSUXSEG6EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11102
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M2
@ PseudoVMV_V_X_M2
Definition riscv/opcodes.hpp:7405
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M4
@ PseudoVMFEQ_VV_M4
Definition riscv/opcodes.hpp:6632
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF4
@ PseudoVLOXSEG7EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:4920
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M1_E32
@ PseudoVFMSUB_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2264
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF4
@ PseudoVRGATHEREI16_VV_MF2_E32_MF4
Definition riscv/opcodes.hpp:8406
LIEF::assembly::riscv::OPCODE::CV_LHU_ri_inc
@ CV_LHU_ri_inc
Definition riscv/opcodes.hpp:12324
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF4
@ PseudoVLSSEG7E8_V_MF4
Definition riscv/opcodes.hpp:5546
LIEF::assembly::riscv::OPCODE::G_ICMP
@ G_ICMP
Definition riscv/opcodes.hpp:165
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M8_E16_MASK
@ PseudoVFNMSAC_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2742
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VW_SE_M2
@ PseudoVC_FPR32VW_SE_M2
Definition riscv/opcodes.hpp:1102
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E32_MASK
@ PseudoVFWCVT_F_XU_V_M2_E32_MASK
Definition riscv/opcodes.hpp:3586
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_M1_MF2_MASK
@ PseudoVSUXSEG5EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11018
LIEF::assembly::riscv::OPCODE::PseudoVID_V_MF8_MASK
@ PseudoVID_V_MF8_MASK
Definition riscv/opcodes.hpp:4068
LIEF::assembly::riscv::OPCODE::FNMADD_S
@ FNMADD_S
Definition riscv/opcodes.hpp:12741
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M8_M1
@ PseudoVLUXSEG7EI64_V_M8_M1
Definition riscv/opcodes.hpp:6300
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M8_M1
@ PseudoVSM4R_VS_M8_M1
Definition riscv/opcodes.hpp:8950
LIEF::assembly::riscv::OPCODE::CV_CMPLT_B
@ CV_CMPLT_B
Definition riscv/opcodes.hpp:12259
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M4_MASK
@ PseudoVMFLT_VFPR64_M4_MASK
Definition riscv/opcodes.hpp:6769
LIEF::assembly::riscv::OPCODE::CONVERGENCECTRL_ANCHOR
@ CONVERGENCECTRL_ANCHOR
Definition riscv/opcodes.hpp:69
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_MF2_MASK
@ PseudoVLOXSEG2EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4453
LIEF::assembly::riscv::OPCODE::MRET
@ MRET
Definition riscv/opcodes.hpp:12900
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M4
@ PseudoVLE8_V_M4
Definition riscv/opcodes.hpp:4161
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_M1
@ PseudoVSUXSEG7EI64_V_M1_M1
Definition riscv/opcodes.hpp:11215
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF4_E16_MASK
@ PseudoVDIVU_VX_MF4_E16_MASK
Definition riscv/opcodes.hpp:1506
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64_V_M2
@ PseudoVLSEG2E64_V_M2
Definition riscv/opcodes.hpp:5098
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_M1_MASK
@ PseudoVWMACCU_VV_M1_MASK
Definition riscv/opcodes.hpp:11492
LIEF::assembly::riscv::OPCODE::PseudoCCMOVGPR
@ PseudoCCMOVGPR
Definition riscv/opcodes.hpp:347
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF2_MASK
@ PseudoVLUXSEG8EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:6337
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF4_MASK
@ PseudoVLSSEG3E16_V_MF4_MASK
Definition riscv/opcodes.hpp:5441
LIEF::assembly::riscv::OPCODE::XNOR
@ XNOR
Definition riscv/opcodes.hpp:13847
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF8
@ PseudoVSOXSEG3EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:9317
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF4_MASK
@ PseudoVLSSEG2E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5431
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WX_M4_MASK
@ PseudoVNCLIPU_WX_M4_MASK
Definition riscv/opcodes.hpp:7455
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E32
@ PseudoVREDAND_VS_M1_E32
Definition riscv/opcodes.hpp:7702
LIEF::assembly::riscv::OPCODE::PseudoVSSE16_V_M1_MASK
@ PseudoVSSE16_V_M1_MASK
Definition riscv/opcodes.hpp:9948
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_MF2_MF4_MASK
@ PseudoVLOXSEG5EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4727
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_M1
@ PseudoVLOXSEG7EI8_V_MF4_M1
Definition riscv/opcodes.hpp:4916
LIEF::assembly::riscv::OPCODE::PseudoLLAImm
@ PseudoLLAImm
Definition riscv/opcodes.hpp:398
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M2_MF2
@ PseudoVAESEF_VS_M2_MF2
Definition riscv/opcodes.hpp:704
LIEF::assembly::riscv::OPCODE::CV_MULUN
@ CV_MULUN
Definition riscv/opcodes.hpp:12377
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF8_MASK
@ PseudoVSSEG3E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10054
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF4_M1
@ PseudoVSUXSEG3EI16_V_MF4_M1
Definition riscv/opcodes.hpp:10815
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E16_V_MF2
@ PseudoVSSEG7E16_V_MF2
Definition riscv/opcodes.hpp:10125
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M1
@ PseudoVLSSEG4E32_V_M1
Definition riscv/opcodes.hpp:5470
LIEF::assembly::riscv::OPCODE::TH_LURH
@ TH_LURH
Definition riscv/opcodes.hpp:13082
LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M4
@ PseudoVLSE64_V_M4
Definition riscv/opcodes.hpp:5036
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M2_MASK
@ PseudoVMFLT_VFPR64_M2_MASK
Definition riscv/opcodes.hpp:6767
LIEF::assembly::riscv::OPCODE::FSGNJ_H_INX
@ FSGNJ_H_INX
Definition riscv/opcodes.hpp:12775
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M8_E32_MASK
@ PseudoVFADD_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:1618
LIEF::assembly::riscv::OPCODE::PseudoCCORN
@ PseudoCCORN
Definition riscv/opcodes.hpp:351
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF2
@ PseudoVLUXSEG4EI64_V_M1_MF2
Definition riscv/opcodes.hpp:6030
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M1_M1_MASK
@ PseudoVLOXSEG8EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4951
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF4_M1
@ PseudoVSOXSEG6EI8_V_MF4_M1
Definition riscv/opcodes.hpp:9657
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VX_M4
@ PseudoTHVdotVMAQAU_VX_M4
Definition riscv/opcodes.hpp:494
LIEF::assembly::riscv::OPCODE::G_FFREXP
@ G_FFREXP
Definition riscv/opcodes.hpp:212
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E16
@ PseudoVFWMACC_VV_M2_E16
Definition riscv/opcodes.hpp:3753
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E8
@ PseudoVWREDSUMU_VS_MF2_E8
Definition riscv/opcodes.hpp:11639
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M2_MASK
@ PseudoVSUXSEG2EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:10756
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR16_MF2_E16_MASK
@ PseudoVFRSUB_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3100
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_MF4
@ PseudoVMFLT_VV_MF4
Definition riscv/opcodes.hpp:6782
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR16_MF4_E16
@ PseudoVFSGNJN_VFPR16_MF4_E16
Definition riscv/opcodes.hpp:3131
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M2
@ PseudoVMFEQ_VV_M2
Definition riscv/opcodes.hpp:6630
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_M8_MASK
@ PseudoVMSGT_VI_M8_MASK
Definition riscv/opcodes.hpp:7044
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16V_SE_MF2
@ PseudoVC_FPR16V_SE_MF2
Definition riscv/opcodes.hpp:1094
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E64
@ PseudoVFNMSAC_VV_M2_E64
Definition riscv/opcodes.hpp:2775
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_MF8
@ PseudoVSADDU_VI_MF8
Definition riscv/opcodes.hpp:8616
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M2_M2_MASK
@ PseudoVSUXSEG2EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10706
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M2_MASK
@ PseudoVWSUB_VX_M2_MASK
Definition riscv/opcodes.hpp:11794
LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M4
@ PseudoVSM3ME_VV_M4
Definition riscv/opcodes.hpp:8927
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E64_V_M1
@ PseudoVSSEG5E64_V_M1
Definition riscv/opcodes.hpp:10093
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E32_V_M1_MASK
@ PseudoVSSSEG7E32_V_M1_MASK
Definition riscv/opcodes.hpp:10386
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI8_V_MF4_M1
@ PseudoVSOXSEG5EI8_V_MF4_M1
Definition riscv/opcodes.hpp:9577
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VI_MF2_MASK
@ PseudoVMSEQ_VI_MF2_MASK
Definition riscv/opcodes.hpp:6961
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF8_E8_MF8
@ PseudoVRGATHEREI16_VV_MF8_E8_MF8
Definition riscv/opcodes.hpp:8432
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF2_MASK
@ PseudoVLUXSEG5EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6125
LIEF::assembly::riscv::OPCODE::PseudoFLH
@ PseudoFLH
Definition riscv/opcodes.hpp:372
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_MF2_MASK
@ PseudoVSLIDEUP_VI_MF2_MASK
Definition riscv/opcodes.hpp:8859
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_MF4_E16
@ PseudoVFNCVT_F_XU_W_MF4_E16
Definition riscv/opcodes.hpp:2469
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_M1
@ PseudoVLUXSEG5EI16_V_M1_M1
Definition riscv/opcodes.hpp:6082
LIEF::assembly::riscv::OPCODE::FSGNJN_D_IN32X
@ FSGNJN_D_IN32X
Definition riscv/opcodes.hpp:12758
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_XU_W_M4_E32
@ PseudoVFNCVT_F_XU_W_M4_E32
Definition riscv/opcodes.hpp:2463
LIEF::assembly::riscv::OPCODE::VSSSEG6E32_V
@ VSSSEG6E32_V
Definition riscv/opcodes.hpp:13753
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_MF8
@ PseudoVSRA_VV_MF8
Definition riscv/opcodes.hpp:9889
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_M4
@ PseudoVWMULU_VV_M4
Definition riscv/opcodes.hpp:11567
LIEF::assembly::riscv::OPCODE::FCVT_W_D_INX
@ FCVT_W_D_INX
Definition riscv/opcodes.hpp:12638
LIEF::assembly::riscv::OPCODE::PseudoVC_X_SE_M1
@ PseudoVC_X_SE_M1
Definition riscv/opcodes.hpp:1416
LIEF::assembly::riscv::OPCODE::AMOSWAP_B
@ AMOSWAP_B
Definition riscv/opcodes.hpp:12083
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF2_MF2
@ PseudoVLUXSEG6EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:6226
LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_M1
@ PseudoVMOR_MM_M1
Definition riscv/opcodes.hpp:6903
LIEF::assembly::riscv::OPCODE::AMOMAX_H_AQ_RL
@ AMOMAX_H_AQ_RL
Definition riscv/opcodes.hpp:12029
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E16
@ PseudoVFWMUL_VV_MF2_E16
Definition riscv/opcodes.hpp:3833
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M8_MASK
@ PseudoVMFEQ_VV_M8_MASK
Definition riscv/opcodes.hpp:6635
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF4_MF8_MASK
@ PseudoVSOXSEG4EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:9428
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF2_MASK
@ PseudoVSUXSEG6EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11118
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16_TIED
@ PseudoVFWADD_WV_M2_E16_TIED
Definition riscv/opcodes.hpp:3516
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M2_E32
@ PseudoVDIVU_VX_M2_E32
Definition riscv/opcodes.hpp:1477
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M1_MASK
@ PseudoVSUXSEG4EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:10984
LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_MF8
@ PseudoVMNAND_MM_MF8
Definition riscv/opcodes.hpp:6888
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF4_MASK
@ PseudoVLUXSEG3EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:5887
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF2_E8
@ PseudoVDIV_VX_MF2_E8
Definition riscv/opcodes.hpp:1591
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M4_MASK
@ PseudoVFCLASS_V_M4_MASK
Definition riscv/opcodes.hpp:1664
LIEF::assembly::riscv::OPCODE::PseudoVNCLIPU_WI_MF4
@ PseudoVNCLIPU_WI_MF4
Definition riscv/opcodes.hpp:7434
LIEF::assembly::riscv::OPCODE::PseudoVWMACCUS_VX_MF8_MASK
@ PseudoVWMACCUS_VX_MF8_MASK
Definition riscv/opcodes.hpp:11490
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M8
@ PseudoVNMSAC_VV_M8
Definition riscv/opcodes.hpp:7504
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_MF4_E16
@ PseudoVFWADD_WFPR16_MF4_E16
Definition riscv/opcodes.hpp:3495
LIEF::assembly::riscv::OPCODE::VGMUL_VV
@ VGMUL_VV
Definition riscv/opcodes.hpp:13304
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M2_M2
@ PseudoVLOXEI8_V_M2_M2
Definition riscv/opcodes.hpp:4298
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_MF2_E16
@ PseudoVFNMSAC_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2743
LIEF::assembly::riscv::OPCODE::VFWMACC_VF
@ VFWMACC_VF
Definition riscv/opcodes.hpp:13287
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_MF2_MF4
@ PseudoVLOXEI32_V_MF2_MF4
Definition riscv/opcodes.hpp:4254
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF4
@ PseudoVSSUBU_VV_MF4
Definition riscv/opcodes.hpp:10429
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_M4
@ PseudoVC_V_X_M4
Definition riscv/opcodes.hpp:1384
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VX_MF8
@ PseudoVWMACC_VX_MF8
Definition riscv/opcodes.hpp:11537
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E32
@ PseudoVFCVT_F_X_V_M1_E32
Definition riscv/opcodes.hpp:1703
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M2_E16_MASK
@ PseudoVFMUL_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:2349
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M4_M2
@ PseudoVLOXEI16_V_M4_M2
Definition riscv/opcodes.hpp:4194
LIEF::assembly::riscv::OPCODE::PseudoVSHA2CH_VV_MF2
@ PseudoVSHA2CH_VV_MF2
Definition riscv/opcodes.hpp:8783
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M1_MASK
@ PseudoVNSRA_WX_M1_MASK
Definition riscv/opcodes.hpp:7579
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WV_MF4
@ PseudoVNCLIP_WV_MF4
Definition riscv/opcodes.hpp:7482
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR64_M1_MASK
@ PseudoVMFLT_VFPR64_M1_MASK
Definition riscv/opcodes.hpp:6765
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_M1
@ PseudoVMSLT_VV_M1
Definition riscv/opcodes.hpp:7193
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VV_MF4
@ PseudoVWMULU_VV_MF4
Definition riscv/opcodes.hpp:11571
LIEF::assembly::riscv::OPCODE::PseudoVWMACCU_VV_MF4_MASK
@ PseudoVWMACCU_VV_MF4_MASK
Definition riscv/opcodes.hpp:11500
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF4_E16
@ PseudoVFNMADD_VV_MF4_E16
Definition riscv/opcodes.hpp:2733
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M4
@ PseudoVLUXEI8_V_M1_M4
Definition riscv/opcodes.hpp:5686
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E64_V_M2
@ PseudoVSSSEG3E64_V_M2
Definition riscv/opcodes.hpp:10299
LIEF::assembly::riscv::OPCODE::PseudoQuietFLT_H_INX
@ PseudoQuietFLT_H_INX
Definition riscv/opcodes.hpp:429
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR16_M2_E16
@ PseudoVFMUL_VFPR16_M2_E16
Definition riscv/opcodes.hpp:2314
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_MF2
@ PseudoTHVdotVMAQA_VX_MF2
Definition riscv/opcodes.hpp:518
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_M1_M2_MASK
@ PseudoVSOXSEG4EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9486
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B32_MASK
@ PseudoVMSOF_M_B32_MASK
Definition riscv/opcodes.hpp:7270
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_MF2
@ PseudoVLSEG4E16FF_V_MF2
Definition riscv/opcodes.hpp:5186
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_M1_M1
@ PseudoVSUXSEG7EI8_V_M1_M1
Definition riscv/opcodes.hpp:11235
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_MF2
@ PseudoVSUXSEG6EI32_V_M1_MF2
Definition riscv/opcodes.hpp:11117
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR16_MF4_E16_MASK
@ PseudoVFSGNJX_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3192
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M4_M1
@ PseudoVLUXSEG3EI32_V_M4_M1
Definition riscv/opcodes.hpp:5904
LIEF::assembly::riscv::OPCODE::PseudoVMV_V_X_M1
@ PseudoVMV_V_X_M1
Definition riscv/opcodes.hpp:7404
LIEF::assembly::riscv::OPCODE::SLTIU
@ SLTIU
Definition riscv/opcodes.hpp:12989
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M2
@ PseudoVSSUB_VV_M2
Definition riscv/opcodes.hpp:10449
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M2
@ PseudoVRGATHEREI16_VV_M4_E64_M2
Definition riscv/opcodes.hpp:8356
LIEF::assembly::riscv::OPCODE::VLSEG2E64_V
@ VLSEG2E64_V
Definition riscv/opcodes.hpp:13373
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_MF2
@ PseudoVLSEG3E8_V_MF2
Definition riscv/opcodes.hpp:5176
LIEF::assembly::riscv::OPCODE::AMOMAXU_B
@ AMOMAXU_B
Definition riscv/opcodes.hpp:12003
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_M2_E32
@ PseudoVFSGNJ_VV_M2_E32
Definition riscv/opcodes.hpp:3279
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_MF2_MF2
@ PseudoVSM4R_VS_MF2_MF2
Definition riscv/opcodes.hpp:8956
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M4_MASK
@ PseudoVWADD_VX_M4_MASK
Definition riscv/opcodes.hpp:11412
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_M2
@ PseudoVSRL_VX_M2
Definition riscv/opcodes.hpp:9935
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_MF2_MF2
@ PseudoVLOXSEG8EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:4964
LIEF::assembly::riscv::OPCODE::CV_SUB_DIV2
@ CV_SUB_DIV2
Definition riscv/opcodes.hpp:12456
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M8_MASK
@ PseudoVSEXT_VF8_M8_MASK
Definition riscv/opcodes.hpp:8778
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK
@ PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK
Definition riscv/opcodes.hpp:2558
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF2_MASK
@ PseudoVSADD_VI_MF2_MASK
Definition riscv/opcodes.hpp:8655
LIEF::assembly::riscv::OPCODE::VSOXEI8_V
@ VSOXEI8_V
Definition riscv/opcodes.hpp:13663
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M1_MF2_MASK
@ PseudoVSOXSEG3EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9350
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M1
@ PseudoVOR_VX_M1
Definition riscv/opcodes.hpp:7654
LIEF::assembly::riscv::OPCODE::FSQRT_D_IN32X
@ FSQRT_D_IN32X
Definition riscv/opcodes.hpp:12780
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF8_M2_MASK
@ PseudoVZEXT_VF8_M2_MASK
Definition riscv/opcodes.hpp:11906
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_M1_MASK
@ PseudoTHVdotVMAQAU_VV_M1_MASK
Definition riscv/opcodes.hpp:481
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M2_MASK
@ PseudoVLOXSEG3EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4473
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M8
@ PseudoVSADDU_VX_M8
Definition riscv/opcodes.hpp:8638
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF8_MF2
@ PseudoVSUXSEG7EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:11249
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF8_MASK
@ PseudoVLSEG6E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5317
LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SC_H
@ CV_SDOTSP_SC_H
Definition riscv/opcodes.hpp:12398
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M8_E64_MASK
@ PseudoVFSGNJX_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:3234
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF4_MF4
@ PseudoVSUXSEG2EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:10691
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_MF4
@ PseudoVC_V_FPR16VV_SE_MF4
Definition riscv/opcodes.hpp:1177
LIEF::assembly::riscv::OPCODE::FCVT_W_H_INX
@ FCVT_W_H_INX
Definition riscv/opcodes.hpp:12640
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_M8
@ PseudoVMADC_VVM_M8
Definition riscv/opcodes.hpp:6447
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_MF2
@ PseudoVSUB_VV_MF2
Definition riscv/opcodes.hpp:10483
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_MF2
@ PseudoVLUXSEG2EI64_V_M4_MF2
Definition riscv/opcodes.hpp:5818
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VV_M2_MASK
@ PseudoVMSEQ_VV_M2_MASK
Definition riscv/opcodes.hpp:6969
LIEF::assembly::riscv::OPCODE::C_LI
@ C_LI
Definition riscv/opcodes.hpp:12506
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M1_MF2_MASK
@ PseudoVSUXSEG3EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10828
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M4_MASK
@ PseudoVSADDU_VI_M4_MASK
Definition riscv/opcodes.hpp:8609
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_M1
@ PseudoVLUXSEG7EI64_V_M2_M1
Definition riscv/opcodes.hpp:6290
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_M2
@ PseudoVC_V_X_M2
Definition riscv/opcodes.hpp:1383
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_M4
@ PseudoVSOXEI16_V_M1_M4
Definition riscv/opcodes.hpp:9003
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M8_M4
@ PseudoVSUXEI64_V_M8_M4
Definition riscv/opcodes.hpp:10611
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M1
@ PseudoVMFEQ_VV_M1
Definition riscv/opcodes.hpp:6628
LIEF::assembly::riscv::OPCODE::G_FSHL
@ G_FSHL
Definition riscv/opcodes.hpp:161
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF2_E8_MASK
@ PseudoVWREDSUMU_VS_MF2_E8_MASK
Definition riscv/opcodes.hpp:11640
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M4
@ PseudoVWADDU_WX_M4
Definition riscv/opcodes.hpp:11387
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E16_MASK
@ PseudoVFWNMACC_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3862
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M2
@ PseudoVSM4R_VV_M2
Definition riscv/opcodes.hpp:8960
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VV_M2_E32_MASK
@ PseudoVFMIN_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:2171
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M1_MF2
@ PseudoVLOXEI32_V_M1_MF2
Definition riscv/opcodes.hpp:4224
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_MF8_MASK
@ PseudoVLE8_V_MF8_MASK
Definition riscv/opcodes.hpp:4170
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_X_F_W_M4_MASK
@ PseudoVFNCVT_RM_X_F_W_M4_MASK
Definition riscv/opcodes.hpp:2542
LIEF::assembly::riscv::OPCODE::VADC_VVM
@ VADC_VVM
Definition riscv/opcodes.hpp:13136
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M4_MASK
@ PseudoVLE16FF_V_M4_MASK
Definition riscv/opcodes.hpp:4088
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_M1_E32
@ PseudoVFMAX_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2069
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M2_MF4_MASK
@ PseudoVLOXSEG3EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:4541
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M2
@ PseudoVLUXSEG2EI16_V_MF2_M2
Definition riscv/opcodes.hpp:5748
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M2
@ PseudoVSOXSEG3EI16_V_M2_M2
Definition riscv/opcodes.hpp:9299
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_M4
@ PseudoVFNCVT_RTZ_XU_F_W_M4
Definition riscv/opcodes.hpp:2571
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF8_MF2_MASK
@ PseudoVLUXSEG4EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:6077
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M8_MASK
@ PseudoVMFLT_VFPR16_M8_MASK
Definition riscv/opcodes.hpp:6749
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E8_V_MF8_MASK
@ PseudoVSSEG4E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10082
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_M1
@ PseudoVAESZ_VS_M4_M1
Definition riscv/opcodes.hpp:775
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_M1
@ PseudoVLSSEG8E8_V_M1
Definition riscv/opcodes.hpp:5562
LIEF::assembly::riscv::OPCODE::CV_LH_rr
@ CV_LH_rr
Definition riscv/opcodes.hpp:12328
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M1
@ PseudoVFCVT_RTZ_X_F_V_M1
Definition riscv/opcodes.hpp:1827
LIEF::assembly::riscv::OPCODE::FCVT_H_LU_INX
@ FCVT_H_LU_INX
Definition riscv/opcodes.hpp:12595
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF2_M8
@ PseudoVSEXT_VF2_M8
Definition riscv/opcodes.hpp:8755
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_MF2_MASK
@ PseudoVLOXSEG6EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4813
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF4
@ PseudoVLUXSEG6EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:6198
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E16_MASK
@ PseudoVREDMAXU_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:7777
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF4_MASK
@ PseudoVLSEG5E8FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5267
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK
@ PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:3556
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E16
@ PseudoVFREDUSUM_VS_M1_E16
Definition riscv/opcodes.hpp:3025
LIEF::assembly::riscv::OPCODE::CV_AND_SCI_H
@ CV_AND_SCI_H
Definition riscv/opcodes.hpp:12184
LIEF::assembly::riscv::OPCODE::CV_OR_SC_H
@ CV_OR_SC_H
Definition riscv/opcodes.hpp:12384
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M1
@ PseudoVLUXSEG4EI32_V_M4_M1
Definition riscv/opcodes.hpp:6014
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VV_MF2
@ PseudoVANDN_VV_MF2
Definition riscv/opcodes.hpp:798
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VX_MF2
@ PseudoVSLL_VX_MF2
Definition riscv/opcodes.hpp:8914
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_M2
@ PseudoVSOXEI16_V_MF2_M2
Definition riscv/opcodes.hpp:9027
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M1_E16_MASK
@ PseudoVFWADD_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3452
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_MF4_MASK
@ PseudoVWSLL_VV_MF4_MASK
Definition riscv/opcodes.hpp:11704
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M2_MASK
@ PseudoVLUXEI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:5669
LIEF::assembly::riscv::OPCODE::VLSSEG7E16_V
@ VLSSEG7E16_V
Definition riscv/opcodes.hpp:13444
LIEF::assembly::riscv::OPCODE::TH_LHUIB
@ TH_LHUIB
Definition riscv/opcodes.hpp:13071
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VV_MF4_E16_MASK
@ PseudoVFWMSAC_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3802
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M1_E16
@ PseudoVFNMSAC_VFPR16_M1_E16
Definition riscv/opcodes.hpp:2735
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF4_MF2_MASK
@ PseudoVSUXSEG4EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:11004
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M4_M1_MASK
@ PseudoVLUXSEG5EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:6137
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF2_MF2_MASK
@ PseudoVSOXEI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9138
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E16_MASK
@ PseudoVFWCVT_F_X_V_M2_E16_MASK
Definition riscv/opcodes.hpp:3614
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_MF2_MASK
@ PseudoVLUXSEG4EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:6071
LIEF::assembly::riscv::OPCODE::FCVT_D_W
@ FCVT_D_W
Definition riscv/opcodes.hpp:12584
LIEF::assembly::riscv::OPCODE::VSSSEG7E16_V
@ VSSSEG7E16_V
Definition riscv/opcodes.hpp:13756
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_M1_MASK
@ PseudoVSOXEI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9140
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF2_M1
@ PseudoVLOXSEG7EI8_V_MF2_M1
Definition riscv/opcodes.hpp:4912
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF2_MASK
@ PseudoVLUXSEG6EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6197
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF8_M1_MASK
@ PseudoVLOXSEG2EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:4463
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M8_M2_MASK
@ PseudoVLOXSEG2EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:4431
LIEF::assembly::riscv::OPCODE::VSSEG4E16_V
@ VSSEG4E16_V
Definition riscv/opcodes.hpp:13710
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI16_V_MF4_MF8_MASK
@ PseudoVLUXSEG8EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:6341
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF4
@ PseudoVSOXSEG6EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:9607
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_M1_M8
@ PseudoVLOXEI8_V_M1_M8
Definition riscv/opcodes.hpp:4296
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M2_E64_MASK
@ PseudoVFNMACC_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:2656
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M1
@ PseudoVSUXEI16_V_M1_M1
Definition riscv/opcodes.hpp:10503
LIEF::assembly::riscv::OPCODE::FLT_D
@ FLT_D
Definition riscv/opcodes.hpp:12678
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF2
@ PseudoVSUXSEG2EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:10723
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E32_V_MF2_MASK
@ PseudoVLSSEG5E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5499
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M2_MASK
@ PseudoVSE8_V_M2_MASK
Definition riscv/opcodes.hpp:8735
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI32_V_MF2_MF2_MASK
@ PseudoVSOXSEG5EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9546
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF2
@ PseudoVSRL_VV_MF2
Definition riscv/opcodes.hpp:9927
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M2_E64
@ PseudoVFRSQRT7_V_M2_E64
Definition riscv/opcodes.hpp:3071
LIEF::assembly::riscv::OPCODE::C_SRLI64_HINT
@ C_SRLI64_HINT
Definition riscv/opcodes.hpp:12539
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M2_MF2_MASK
@ PseudoVSOXSEG2EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:9206
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_MF2
@ PseudoVSOXSEG2EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:9285
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32FF_V_MF2_MASK
@ PseudoVLSEG3E32FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5147
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF4_E16_MASK
@ PseudoVREDMAX_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:7827
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E64FF_V_M2_MASK
@ PseudoVLSEG2E64FF_V_M2_MASK
Definition riscv/opcodes.hpp:5093
LIEF::assembly::riscv::OPCODE::VSSSEG5E8_V
@ VSSSEG5E8_V
Definition riscv/opcodes.hpp:13751
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_M8
@ PseudoVAND_VX_M8
Definition riscv/opcodes.hpp:852
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_MF2
@ PseudoVSOXSEG8EI8_V_MF2_MF2
Definition riscv/opcodes.hpp:9815
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_M1_M1_MASK
@ PseudoVSOXSEG2EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9192
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M8_MASK
@ PseudoTHVdotVMAQA_VV_M8_MASK
Definition riscv/opcodes.hpp:507
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_M1_M2_MASK
@ PseudoVSUXSEG3EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10880
LIEF::assembly::riscv::OPCODE::CV_MIN_SC_H
@ CV_MIN_SC_H
Definition riscv/opcodes.hpp:12369
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR32_M1_E32_MASK
@ PseudoVFWSUB_WFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:4002
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF4_MASK
@ PseudoVSUXSEG6EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:11132
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M1_MASK
@ PseudoVCLMUL_VX_M1_MASK
Definition riscv/opcodes.hpp:987
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VX_M1_MASK
@ PseudoVWSUB_VX_M1_MASK
Definition riscv/opcodes.hpp:11792
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M4_E32_MASK
@ PseudoVFSGNJX_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:3226
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF4_MASK
@ PseudoVMACC_VX_MF4_MASK
Definition riscv/opcodes.hpp:6427
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_MF4_MASK
@ PseudoVMFLE_VV_MF4_MASK
Definition riscv/opcodes.hpp:6741
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M4_MASK
@ PseudoVWADDU_WV_M4_MASK
Definition riscv/opcodes.hpp:11368
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M1_E32_MASK
@ PseudoVREDMAX_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:7791
LIEF::assembly::riscv::OPCODE::FSD
@ FSD
Definition riscv/opcodes.hpp:12756
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E64
@ PseudoVFMACC_VV_M4_E64
Definition riscv/opcodes.hpp:1983
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M8_E16
@ PseudoVFNMACC_VV_M8_E16
Definition riscv/opcodes.hpp:2663
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M1_MASK
@ PseudoVCLMULH_VX_M1_MASK
Definition riscv/opcodes.hpp:959
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M1_E64
@ PseudoVREDSUM_VS_M1_E64
Definition riscv/opcodes.hpp:7968
LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I_DIV2
@ CV_CPLXMUL_I_DIV2
Definition riscv/opcodes.hpp:12274
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B4
@ PseudoVFIRST_M_B4
Definition riscv/opcodes.hpp:1931
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF8
@ PseudoVLUXSEG5EI64_V_M1_MF8
Definition riscv/opcodes.hpp:6128
LIEF::assembly::riscv::OPCODE::InsnI_Mem
@ InsnI_Mem
Definition riscv/opcodes.hpp:12824
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF8
@ PseudoVLUXSEG2EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:5794
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M1_E32
@ PseudoVFMSAC_VV_M1_E32
Definition riscv/opcodes.hpp:2224
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF4_MASK
@ PseudoVLOXEI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:4273
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M4_MF4
@ PseudoVAESEF_VS_M4_MF4
Definition riscv/opcodes.hpp:711
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_M1_M2
@ PseudoVLOXSEG3EI8_V_M1_M2
Definition riscv/opcodes.hpp:4554
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_M1_E32_MASK
@ PseudoVFWMUL_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3814
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M2
@ PseudoVFMV_V_FPR32_M2
Definition riscv/opcodes.hpp:2409
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_M1
@ PseudoVLSEG4E8FF_V_M1
Definition riscv/opcodes.hpp:5218
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E8_MASK
@ PseudoVREM_VX_M8_E8_MASK
Definition riscv/opcodes.hpp:8247
LIEF::assembly::riscv::OPCODE::CV_ELW
@ CV_ELW
Definition riscv/opcodes.hpp:12299
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M1
@ PseudoVSLIDEUP_VI_M1
Definition riscv/opcodes.hpp:8850
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E16_V_M1
@ PseudoVSSSEG6E16_V_M1
Definition riscv/opcodes.hpp:10359
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WX_M1
@ PseudoVNSRA_WX_M1
Definition riscv/opcodes.hpp:7578
LIEF::assembly::riscv::OPCODE::FCVT_WU_H_INX
@ FCVT_WU_H_INX
Definition riscv/opcodes.hpp:12633
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M1_E64
@ PseudoVDIV_VX_M1_E64
Definition riscv/opcodes.hpp:1559
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8_V_M2
@ PseudoVLSEG4E8_V_M2
Definition riscv/opcodes.hpp:5230
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E8_V_MF8_MASK
@ PseudoVSSEG7E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10142
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M1_MF4
@ PseudoVLUXSEG6EI64_V_M1_MF4
Definition riscv/opcodes.hpp:6206
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_M1_M1
@ PseudoVLUXSEG7EI16_V_M1_M1
Definition riscv/opcodes.hpp:6242
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E16_MASK
@ PseudoVFWCVT_F_XU_V_M2_E16_MASK
Definition riscv/opcodes.hpp:3584
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF8
@ PseudoVMSLTU_VX_MF8
Definition riscv/opcodes.hpp:7190
LIEF::assembly::riscv::OPCODE::PseudoVMADD_VX_M8
@ PseudoVMADD_VX_M8
Definition riscv/opcodes.hpp:6492
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQAU_VV_MF2
@ PseudoTHVdotVMAQAU_VV_MF2
Definition riscv/opcodes.hpp:488
LIEF::assembly::riscv::OPCODE::VLSEG2E32FF_V
@ VLSEG2E32FF_V
Definition riscv/opcodes.hpp:13370
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF4_E16_MASK
@ PseudoVFREDMAX_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:2964
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M2
@ PseudoVMSGT_VX_M2
Definition riscv/opcodes.hpp:7053
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF4_MASK
@ PseudoVSOXEI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9076
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M2_M1
@ PseudoVSUXSEG7EI16_V_M2_M1
Definition riscv/opcodes.hpp:11179
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_MF2_MASK
@ PseudoVWSLL_VI_MF2_MASK
Definition riscv/opcodes.hpp:11690
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF4
@ PseudoVSSSEG6E8_V_MF4
Definition riscv/opcodes.hpp:10375
LIEF::assembly::riscv::OPCODE::FCVT_H_S_INX
@ FCVT_H_S_INX
Definition riscv/opcodes.hpp:12598
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_MF4_MASK
@ PseudoVSOXSEG2EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9182
LIEF::assembly::riscv::OPCODE::VMERGE_VIM
@ VMERGE_VIM
Definition riscv/opcodes.hpp:13500
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E64_MASK
@ PseudoVFMSUB_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:2299
LIEF::assembly::riscv::OPCODE::CV_ADDURNR
@ CV_ADDURNR
Definition riscv/opcodes.hpp:12171
LIEF::assembly::riscv::OPCODE::PseudoVCTZ_V_M8_MASK
@ PseudoVCTZ_V_M8_MASK
Definition riscv/opcodes.hpp:1071
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_MF4
@ PseudoVFCVT_RTZ_X_F_V_MF4
Definition riscv/opcodes.hpp:1837
LIEF::assembly::riscv::OPCODE::CV_CMPLTU_B
@ CV_CMPLTU_B
Definition riscv/opcodes.hpp:12253
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VV_M1
@ PseudoTHVdotVMAQA_VV_M1
Definition riscv/opcodes.hpp:500
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M1_MASK
@ PseudoVLOXSEG4EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4609
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VX_MF8_MASK
@ PseudoVSRL_VX_MF8_MASK
Definition riscv/opcodes.hpp:9946
LIEF::assembly::riscv::OPCODE::CV_ADD_SC_H
@ CV_ADD_SC_H
Definition riscv/opcodes.hpp:12180
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8_V_MF2
@ PseudoVLSEG6E8_V_MF2
Definition riscv/opcodes.hpp:5312
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E32_MASK
@ PseudoVREMU_VX_M8_E32_MASK
Definition riscv/opcodes.hpp:8155
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M1_E32
@ PseudoVFWNMACC_VV_M1_E32
Definition riscv/opcodes.hpp:3859
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M1
@ PseudoVAADDU_VX_M1
Definition riscv/opcodes.hpp:535
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_M2
@ PseudoVCLMUL_VX_M2
Definition riscv/opcodes.hpp:988
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M8_MASK
@ PseudoVMSEQ_VX_M8_MASK
Definition riscv/opcodes.hpp:6987
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_MF8_MASK
@ PseudoVSUXSEG6EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:11142
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E32
@ PseudoVREDMIN_VS_M1_E32
Definition riscv/opcodes.hpp:7878
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG5E64_V_M1_MASK
@ PseudoVLSSEG5E64_V_M1_MASK
Definition riscv/opcodes.hpp:5501
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_M8
@ PseudoVSRL_VI_M8
Definition riscv/opcodes.hpp:9911
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M1_M4_MASK
@ PseudoVSUXEI16_V_M1_M4_MASK
Definition riscv/opcodes.hpp:10508
LIEF::assembly::riscv::OPCODE::G_FSIN
@ G_FSIN
Definition riscv/opcodes.hpp:264
LIEF::assembly::riscv::OPCODE::VLOXSEG6EI16_V
@ VLOXSEG6EI16_V
Definition riscv/opcodes.hpp:13352
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VX_MF2_MASK
@ PseudoVMINU_VX_MF2_MASK
Definition riscv/opcodes.hpp:6849
LIEF::assembly::riscv::OPCODE::PseudoVREV8_V_M4_MASK
@ PseudoVREV8_V_M4_MASK
Definition riscv/opcodes.hpp:8265
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF2
@ PseudoVLOXSEG3EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:4574
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_M1_MASK
@ PseudoVLSEG8E16FF_V_M1_MASK
Definition riscv/opcodes.hpp:5359
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E16_MASK
@ PseudoVFMAX_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:2100
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M8_E64_MASK
@ PseudoVFMAX_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:2110
LIEF::assembly::riscv::OPCODE::FAULTING_OP
@ FAULTING_OP
Definition riscv/opcodes.hpp:57
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VV_MF2_E32
@ PseudoVFWMUL_VV_MF2_E32
Definition riscv/opcodes.hpp:3835
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_M1_MASK
@ PseudoVLUXSEG3EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:5951
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI32_V_MF2_MF4
@ PseudoVLOXSEG2EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:4400
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16_MASK_TIED
@ PseudoVFWADD_WV_MF4_E16_MASK_TIED
Definition riscv/opcodes.hpp:3539
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WX_M4
@ PseudoVWADD_WX_M4
Definition riscv/opcodes.hpp:11447
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI8_V_MF2_MF2_MASK
@ PseudoVLUXSEG3EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:5955
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_MF8
@ PseudoVC_V_VVV_MF8
Definition riscv/opcodes.hpp:1308
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF8_MASK
@ PseudoVLUXSEG5EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:6121
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR32_MF2_E32_MASK
@ PseudoVFWMUL_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3820
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_M1
@ PseudoVLUXSEG6EI32_V_MF2_M1
Definition riscv/opcodes.hpp:6194
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M8_E32_MASK
@ PseudoVFREDMIN_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:2986
LIEF::assembly::riscv::OPCODE::CV_AVGU_SC_B
@ CV_AVGU_SC_B
Definition riscv/opcodes.hpp:12191
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VI_M8
@ PseudoVSADDU_VI_M8
Definition riscv/opcodes.hpp:8610
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M2_E16
@ PseudoVFWCVT_F_XU_V_M2_E16
Definition riscv/opcodes.hpp:3583
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_M2_MASK
@ PseudoVFWCVT_RM_X_F_V_M2_MASK
Definition riscv/opcodes.hpp:3650
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M4_MASK
@ PseudoVNMSAC_VV_M4_MASK
Definition riscv/opcodes.hpp:7503
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_MF2
@ PseudoVLUXSEG2EI16_V_M1_MF2
Definition riscv/opcodes.hpp:5732
LIEF::assembly::riscv::OPCODE::InsnU
@ InsnU
Definition riscv/opcodes.hpp:12829
LIEF::assembly::riscv::OPCODE::AES32DSMI
@ AES32DSMI
Definition riscv/opcodes.hpp:11937
LIEF::assembly::riscv::OPCODE::PseudoRV32ZdinxLD
@ PseudoRV32ZdinxLD
Definition riscv/opcodes.hpp:433
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_M8
@ PseudoVSM4R_VV_M8
Definition riscv/opcodes.hpp:8962
LIEF::assembly::riscv::OPCODE::VSETVL
@ VSETVL
Definition riscv/opcodes.hpp:13635
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M8_E16
@ PseudoVREDSUM_VS_M8_E16
Definition riscv/opcodes.hpp:7988
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E16_MASK
@ PseudoVREMU_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:8085
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_XU_F_V_M4
@ PseudoVFWCVT_RM_XU_F_V_M4
Definition riscv/opcodes.hpp:3641
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M2
@ PseudoVLSEG2E16FF_V_M2
Definition riscv/opcodes.hpp:5056
LIEF::assembly::riscv::OPCODE::AMOMIN_B
@ AMOMIN_B
Definition riscv/opcodes.hpp:12051
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF4_M1_MASK
@ PseudoVLOXSEG4EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4601
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M2_MF4_MASK
@ PseudoVLUXSEG4EI64_V_M2_MF4_MASK
Definition riscv/opcodes.hpp:6043
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M1_E16
@ PseudoVFWMSAC_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3767
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E16_V_M1_MASK
@ PseudoVSSEG3E16_V_M1_MASK
Definition riscv/opcodes.hpp:10028
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RM_X_F_V_MF2
@ PseudoVFWCVT_RM_X_F_V_MF2
Definition riscv/opcodes.hpp:3653
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_MF8
@ PseudoVSE8_V_MF8
Definition riscv/opcodes.hpp:8744
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M2_M1
@ PseudoVLOXSEG3EI16_V_M2_M1
Definition riscv/opcodes.hpp:4476
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E16_MASK
@ PseudoVWREDSUM_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:11678
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M2_E32
@ PseudoVREMU_VV_M2_E32
Definition riscv/opcodes.hpp:8094
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_M2_MASK
@ PseudoVAND_VV_M2_MASK
Definition riscv/opcodes.hpp:835
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_M1
@ PseudoVFMV_FPR16_S_M1
Definition riscv/opcodes.hpp:2372
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_MF4
@ PseudoVSUXSEG2EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:10685
LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_M4
@ PseudoVMAND_MM_M4
Definition riscv/opcodes.hpp:6509
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M4_E16
@ PseudoVFNCVT_F_X_W_M4_E16
Definition riscv/opcodes.hpp:2479
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_MF2_MF2_MASK
@ PseudoVSOXSEG3EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9342
LIEF::assembly::riscv::OPCODE::CV_SDOTUSP_B
@ CV_SDOTUSP_B
Definition riscv/opcodes.hpp:12405
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UINC_WRAP
@ G_ATOMICRMW_UINC_WRAP
Definition riscv/opcodes.hpp:138
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M1_E16
@ PseudoVFWCVTBF16_F_F_V_M1_E16
Definition riscv/opcodes.hpp:3541
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_MF4_E16_MASK
@ PseudoVFCVT_F_XU_V_MF4_E16_MASK
Definition riscv/opcodes.hpp:1700
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_MF2_E16_MASK
@ PseudoVREDOR_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:7953
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M2
@ PseudoVSOXSEG2EI16_V_M2_M2
Definition riscv/opcodes.hpp:9165
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M8
@ PseudoVLE8_V_M8
Definition riscv/opcodes.hpp:4163
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M2
@ PseudoVLSEG3E8_V_M2
Definition riscv/opcodes.hpp:5174
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M8
@ PseudoVSRA_VI_M8
Definition riscv/opcodes.hpp:9869
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E16_MASK
@ PseudoVFSGNJX_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:3212
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M4_M8
@ PseudoVSOXEI8_V_M4_M8
Definition riscv/opcodes.hpp:9127
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16FF_V_M1
@ PseudoVLSEG8E16FF_V_M1
Definition riscv/opcodes.hpp:5358
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M8_E16_MASK
@ PseudoVFMSAC_VV_M8_E16_MASK
Definition riscv/opcodes.hpp:2241
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M1
@ PseudoVNMSUB_VX_M1
Definition riscv/opcodes.hpp:7540
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M1_MASK
@ PseudoVSOXSEG3EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9304
LIEF::assembly::riscv::OPCODE::VSUXSEG4EI32_V
@ VSUXSEG4EI32_V
Definition riscv/opcodes.hpp:13783
LIEF::assembly::riscv::OPCODE::PseudoVWADD_WV_M4_MASK
@ PseudoVWADD_WV_M4_MASK
Definition riscv/opcodes.hpp:11428
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M4_E64
@ PseudoVFREDMIN_VS_M4_E64
Definition riscv/opcodes.hpp:2981
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M4_MASK
@ PseudoVAADDU_VV_M4_MASK
Definition riscv/opcodes.hpp:526
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF4_E16_MASK
@ PseudoVFNCVT_F_X_W_MF4_E16_MASK
Definition riscv/opcodes.hpp:2488
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M2
@ PseudoVLOXSEG2EI16_V_M2_M2
Definition riscv/opcodes.hpp:4344
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF2_M1_MASK
@ PseudoVLOXSEG8EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4993
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR16_M4_E16
@ PseudoVFNMSAC_VFPR16_M4_E16
Definition riscv/opcodes.hpp:2739
LIEF::assembly::riscv::OPCODE::PseudoVOR_VI_MF2_MASK
@ PseudoVOR_VI_MF2_MASK
Definition riscv/opcodes.hpp:7635
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M2_MF2
@ PseudoVLUXSEG4EI32_V_M2_MF2
Definition riscv/opcodes.hpp:6012
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF2_MASK
@ PseudoVLUXSEG2EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:5791
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF4_E8
@ PseudoVFWCVT_F_X_V_MF4_E8
Definition riscv/opcodes.hpp:3633
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M1_E32_MASK
@ PseudoVFNMSAC_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:2768
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VI_MF8
@ PseudoVRSUB_VI_MF8
Definition riscv/opcodes.hpp:8588
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M8
@ PseudoVMFEQ_VFPR32_M8
Definition riscv/opcodes.hpp:6616
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M8
@ PseudoVROR_VV_M8
Definition riscv/opcodes.hpp:8554
LIEF::assembly::riscv::OPCODE::CV_MAXU
@ CV_MAXU
Definition riscv/opcodes.hpp:12343
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E32_V_M2_MASK
@ PseudoVSSEG2E32_V_M2_MASK
Definition riscv/opcodes.hpp:10004
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_M4
@ PseudoVMFNE_VV_M4
Definition riscv/opcodes.hpp:6818
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VV_M2_MASK
@ PseudoVWMACCSU_VV_M2_MASK
Definition riscv/opcodes.hpp:11458
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M4_E32
@ PseudoVFWMACCBF16_VV_M4_E32
Definition riscv/opcodes.hpp:3717
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B8_MASK
@ PseudoVMSIF_M_B8_MASK
Definition riscv/opcodes.hpp:7078
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E8
@ PseudoVREDMAX_VS_M4_E8
Definition riscv/opcodes.hpp:7810
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E16_V_M1_MASK
@ PseudoVLSSEG7E16_V_M1_MASK
Definition riscv/opcodes.hpp:5531
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_MF2
@ PseudoVWSUB_WX_MF2
Definition riscv/opcodes.hpp:11833
LIEF::assembly::riscv::OPCODE::CV_SHUFFLEI2_SCI_B
@ CV_SHUFFLEI2_SCI_B
Definition riscv/opcodes.hpp:12415
LIEF::assembly::riscv::OPCODE::CV_SRA_SCI_B
@ CV_SRA_SCI_B
Definition riscv/opcodes.hpp:12433
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E32_MASK
@ PseudoVFREDUSUM_VS_M2_E32_MASK
Definition riscv/opcodes.hpp:3034
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E64_V_M2_MASK
@ PseudoVLSSEG4E64_V_M2_MASK
Definition riscv/opcodes.hpp:5479
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M8_E64_MASK
@ PseudoVDIVU_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:1452
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR32_MF2_E32
@ PseudoVFWNMSAC_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:3891
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E32_MASK
@ PseudoVREMU_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:8103
LIEF::assembly::riscv::OPCODE::VFNCVT_F_F_W
@ VFNCVT_F_F_W
Definition riscv/opcodes.hpp:13235
LIEF::assembly::riscv::OPCODE::VC_V_IVW
@ VC_V_IVW
Definition riscv/opcodes.hpp:13188
LIEF::assembly::riscv::OPCODE::CV_SRA_SC_B
@ CV_SRA_SC_B
Definition riscv/opcodes.hpp:12435
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M1_M4_MASK
@ PseudoVLUXSEG2EI16_V_M1_M4_MASK
Definition riscv/opcodes.hpp:5731
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF2_MASK
@ PseudoVSOXSEG2EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9186
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M2_MASK
@ PseudoVMFGE_VFPR16_M2_MASK
Definition riscv/opcodes.hpp:6643
LIEF::assembly::riscv::OPCODE::PseudoCCANDI
@ PseudoCCANDI
Definition riscv/opcodes.hpp:345
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M2_E32
@ PseudoVWREDSUM_VS_M2_E32
Definition riscv/opcodes.hpp:11655
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M2_M2_MASK
@ PseudoVLOXSEG3EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:4509
LIEF::assembly::riscv::OPCODE::G_FTANH
@ G_FTANH
Definition riscv/opcodes.hpp:271
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_MF2_E16
@ PseudoVFNMADD_VV_MF2_E16
Definition riscv/opcodes.hpp:2729
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VFPR64_M2_E64_MASK
@ PseudoVFNMSUB_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2820
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E32
@ PseudoVREDXOR_VS_M4_E32
Definition riscv/opcodes.hpp:8026
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF2
@ PseudoVNCLIP_WX_MF2
Definition riscv/opcodes.hpp:7492
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_VFPR32_M1_E32
@ PseudoVFWSUB_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3965
LIEF::assembly::riscv::OPCODE::VSSSEG3E64_V
@ VSSSEG3E64_V
Definition riscv/opcodes.hpp:13742
LIEF::assembly::riscv::OPCODE::VASUB_VV
@ VASUB_VV
Definition riscv/opcodes.hpp:13159
LIEF::assembly::riscv::OPCODE::VLSEG3E32_V
@ VLSEG3E32_V
Definition riscv/opcodes.hpp:13379
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E32_V_M2
@ PseudoVLSEG3E32_V_M2
Definition riscv/opcodes.hpp:5150
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VX_M4
@ PseudoVAADDU_VX_M4
Definition riscv/opcodes.hpp:539
LIEF::assembly::riscv::OPCODE::G_SADDSAT
@ G_SADDSAT
Definition riscv/opcodes.hpp:183
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8FF_V_M1
@ PseudoVLSEG8E8FF_V_M1
Definition riscv/opcodes.hpp:5382
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF2_MASK
@ PseudoVSUXSEG7EI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:11218
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_MF2_M1_MASK
@ PseudoVLUXSEG7EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6275
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_MF2_MASK
@ PseudoVMFEQ_VFPR32_MF2_MASK
Definition riscv/opcodes.hpp:6619
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF8_E8_MASK
@ PseudoVDIV_VV_MF8_E8_MASK
Definition riscv/opcodes.hpp:1554
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF2
@ PseudoVCPOP_V_MF2
Definition riscv/opcodes.hpp:1058
LIEF::assembly::riscv::OPCODE::COPY
@ COPY
Definition riscv/opcodes.hpp:43
LIEF::assembly::riscv::OPCODE::PseudoVMOR_MM_MF2
@ PseudoVMOR_MM_MF2
Definition riscv/opcodes.hpp:6907
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M1_MF4
@ PseudoVLUXSEG7EI64_V_M1_MF4
Definition riscv/opcodes.hpp:6286
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_MF4_E16
@ PseudoVDIV_VV_MF4_E16
Definition riscv/opcodes.hpp:1549
LIEF::assembly::riscv::OPCODE::PseudoVMNAND_MM_M2
@ PseudoVMNAND_MM_M2
Definition riscv/opcodes.hpp:6883
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF4_MF2_MASK
@ PseudoVLUXSEG5EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:6151
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF8
@ PseudoVAND_VI_MF8
Definition riscv/opcodes.hpp:830
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M1_M1_MASK
@ PseudoVSOXSEG7EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9712
LIEF::assembly::riscv::OPCODE::CV_SUBN
@ CV_SUBN
Definition riscv/opcodes.hpp:12443
LIEF::assembly::riscv::OPCODE::PseudoTAIL
@ PseudoTAIL
Definition riscv/opcodes.hpp:447
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF8_MASK
@ PseudoVLUXSEG3EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:5889
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E32_MASK
@ PseudoVREM_VX_M2_E32_MASK
Definition riscv/opcodes.hpp:8227
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WX_MF4_MASK
@ PseudoVNCLIP_WX_MF4_MASK
Definition riscv/opcodes.hpp:7495
LIEF::assembly::riscv::OPCODE::PseudoVROL_VX_M8
@ PseudoVROL_VX_M8
Definition riscv/opcodes.hpp:8526
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M8_MASK
@ PseudoVSSUBU_VX_M8_MASK
Definition riscv/opcodes.hpp:10440
LIEF::assembly::riscv::OPCODE::PseudoVC_XVW_SE_MF2
@ PseudoVC_XVW_SE_MF2
Definition riscv/opcodes.hpp:1406
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M2
@ PseudoVLE8_V_M2
Definition riscv/opcodes.hpp:4159
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M1_E32
@ PseudoVFNCVT_ROD_F_F_W_M1_E32
Definition riscv/opcodes.hpp:2551
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_MF4
@ PseudoVSLL_VI_MF4
Definition riscv/opcodes.hpp:8888
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_MF2_MF2
@ PseudoVLOXSEG3EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:4520
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E8_V_MF2
@ PseudoVSSSEG4E8_V_MF2
Definition riscv/opcodes.hpp:10333
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M2_MF2_MASK
@ PseudoVSUXSEG6EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:11146
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_MF4_E8
@ PseudoVWREDSUMU_VS_MF4_E8
Definition riscv/opcodes.hpp:11643
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E32
@ PseudoVFMACC_VV_M4_E32
Definition riscv/opcodes.hpp:1981
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M8_MASK
@ PseudoVMFNE_VFPR16_M8_MASK
Definition riscv/opcodes.hpp:6791
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_MF4_MASK
@ PseudoVLUXSEG6EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:6233
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_MF4_MF8
@ PseudoVLUXSEG3EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:5888
LIEF::assembly::riscv::OPCODE::FCVT_LU_H
@ FCVT_LU_H
Definition riscv/opcodes.hpp:12605
LIEF::assembly::riscv::OPCODE::PseudoVSBC_VXM_MF8
@ PseudoVSBC_VXM_MF8
Definition riscv/opcodes.hpp:8701
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E32
@ PseudoVFRSQRT7_V_M1_E32
Definition riscv/opcodes.hpp:3063
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_MF4_M1
@ PseudoVSUXSEG6EI16_V_MF4_M1
Definition riscv/opcodes.hpp:11107
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_MF4_MASK
@ PseudoVMFNE_VFPR16_MF4_MASK
Definition riscv/opcodes.hpp:6795
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_MF4_MF2_MASK
@ PseudoVLOXEI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4215
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_M1
@ PseudoVRELOAD2_M1
Definition riscv/opcodes.hpp:8052
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M2
@ PseudoVMULH_VX_M2
Definition riscv/opcodes.hpp:7349
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M2_MASK
@ PseudoVSOXSEG3EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9294
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M1
@ PseudoVMAXU_VV_M1
Definition riscv/opcodes.hpp:6514
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF4_MASK
@ PseudoVSOXSEG7EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9682
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E64_M1
@ PseudoVRGATHEREI16_VV_M2_E64_M1
Definition riscv/opcodes.hpp:8322
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E32_V_M1_MASK
@ PseudoVSSSEG3E32_V_M1_MASK
Definition riscv/opcodes.hpp:10292
LIEF::assembly::riscv::OPCODE::FLEQ_D
@ FLEQ_D
Definition riscv/opcodes.hpp:12661
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M2_MASK
@ PseudoVSEXT_VF4_M2_MASK
Definition riscv/opcodes.hpp:8764
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF4
@ PseudoVLOXSEG7EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:4886
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_MF2_E32
@ PseudoVFNMSAC_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2755
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M2_E64_MASK
@ PseudoVRGATHER_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:8461
LIEF::assembly::riscv::OPCODE::CV_DOTSP_H
@ CV_DOTSP_H
Definition riscv/opcodes.hpp:12282
LIEF::assembly::riscv::OPCODE::PseudoVLE16FF_V_M8
@ PseudoVLE16FF_V_M8
Definition riscv/opcodes.hpp:4089
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M1
@ PseudoVMSNE_VX_M1
Definition riscv/opcodes.hpp:7249
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16_V_M2
@ PseudoVLSEG2E16_V_M2
Definition riscv/opcodes.hpp:5066
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B64
@ PseudoVFIRST_M_B64
Definition riscv/opcodes.hpp:1933
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_MF2
@ PseudoVSSUB_VX_MF2
Definition riscv/opcodes.hpp:10469
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M8_MASK
@ PseudoVSLIDE1DOWN_VX_M8_MASK
Definition riscv/opcodes.hpp:8801
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M4_E16_MASK
@ PseudoVFSQRT_V_M4_E16_MASK
Definition riscv/opcodes.hpp:3374
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF4_E16
@ PseudoVFNCVTBF16_F_F_W_MF4_E16
Definition riscv/opcodes.hpp:2433
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_M8
@ PseudoVMSEQ_VX_M8
Definition riscv/opcodes.hpp:6986
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M2
@ PseudoVLOXEI16_V_M1_M2
Definition riscv/opcodes.hpp:4180
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_MF2_MASK
@ PseudoVLOXSEG3EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:4475
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M4
@ PseudoVMIN_VX_M4
Definition riscv/opcodes.hpp:6872
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VX_MF8
@ PseudoVSLIDEDOWN_VX_MF8
Definition riscv/opcodes.hpp:8848
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VX_M1_MASK
@ PseudoVSADDU_VX_M1_MASK
Definition riscv/opcodes.hpp:8633
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VV_SE_MF4
@ PseudoVC_V_VV_SE_MF4
Definition riscv/opcodes.hpp:1340
LIEF::assembly::riscv::OPCODE::PseudoVMSEQ_VX_MF4_MASK
@ PseudoVMSEQ_VX_MF4_MASK
Definition riscv/opcodes.hpp:6991
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M8_E16
@ PseudoVFADD_VV_M8_E16
Definition riscv/opcodes.hpp:1647
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M2_E64
@ PseudoVFSGNJN_VFPR64_M2_E64
Definition riscv/opcodes.hpp:3145
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_MF2
@ PseudoVMFLE_VFPR32_MF2
Definition riscv/opcodes.hpp:6720
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF2_MASK
@ PseudoVSUXSEG5EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:11090
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VV_MF2
@ PseudoVWMUL_VV_MF2
Definition riscv/opcodes.hpp:11593
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M1_MASK
@ PseudoVSUXSEG4EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:10970
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF2_MF2_MASK
@ PseudoVLUXSEG5EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6147
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_VX_MF8_MASK
@ PseudoVWSUBU_VX_MF8_MASK
Definition riscv/opcodes.hpp:11742
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M1
@ PseudoVLSE16_V_M1
Definition riscv/opcodes.hpp:5010
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_M1_M1_MASK
@ PseudoVSUXSEG5EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11076
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VXM_MF8
@ PseudoVMERGE_VXM_MF8
Definition riscv/opcodes.hpp:6597
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_M2_MASK
@ PseudoVSUXSEG3EI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:10798
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E16
@ PseudoVFDIV_VV_MF2_E16
Definition riscv/opcodes.hpp:1917
LIEF::assembly::riscv::OPCODE::VL8RE32_V
@ VL8RE32_V
Definition riscv/opcodes.hpp:13320
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E16
@ PseudoVREDMINU_VS_M8_E16
Definition riscv/opcodes.hpp:7856
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_MF2_MF2_MASK
@ PseudoVLUXSEG4EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6023
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF2
@ PseudoVLSEG6E16FF_V_MF2
Definition riscv/opcodes.hpp:5280
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_M2
@ PseudoVLUXSEG3EI64_V_M2_M2
Definition riscv/opcodes.hpp:5928
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VX_MF4
@ PseudoVCLMUL_VX_MF4
Definition riscv/opcodes.hpp:996
LIEF::assembly::riscv::OPCODE::PseudoVSSEG2E16_V_M1
@ PseudoVSSEG2E16_V_M1
Definition riscv/opcodes.hpp:9991
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E16_MASK
@ PseudoVFMACC_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:1980
LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_MF4
@ PseudoVC_I_SE_MF4
Definition riscv/opcodes.hpp:1144
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M8_M1_MASK
@ PseudoVSUXSEG7EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:11234
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M2
@ PseudoVMERGE_VVM_M2
Definition riscv/opcodes.hpp:6585
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR32_M1_E32
@ PseudoVFNMSAC_VFPR32_M1_E32
Definition riscv/opcodes.hpp:2747
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E16_TIED
@ PseudoVFWSUB_WV_M2_E16_TIED
Definition riscv/opcodes.hpp:4020
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_X_F_V_M8
@ PseudoVFCVT_RTZ_X_F_V_M8
Definition riscv/opcodes.hpp:1833
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E32_V_M2
@ PseudoVLSEG2E32_V_M2
Definition riscv/opcodes.hpp:5084
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR32_M2_E32
@ PseudoVFMSUB_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2266
LIEF::assembly::riscv::OPCODE::VWADD_WX
@ VWADD_WX
Definition riscv/opcodes.hpp:13811
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI16_V_M1_M2_MASK
@ PseudoVLOXEI16_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4181
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M1_MASK
@ PseudoVMFGT_VFPR32_M1_MASK
Definition riscv/opcodes.hpp:6683
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VV_M4_MASK
@ PseudoVWSLL_VV_M4_MASK
Definition riscv/opcodes.hpp:11700
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16
@ PseudoVFWADD_WV_M2_E16
Definition riscv/opcodes.hpp:3513
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E32_V_M1_MASK
@ PseudoVSSEG6E32_V_M1_MASK
Definition riscv/opcodes.hpp:10110
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E32
@ PseudoVFCVT_RM_F_X_V_M8_E32
Definition riscv/opcodes.hpp:1781
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M1
@ PseudoVFCLASS_V_M1
Definition riscv/opcodes.hpp:1659
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_M1_M1_MASK
@ PseudoVLOXSEG3EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4471
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_MF2_MASK
@ PseudoVMFLT_VFPR16_MF2_MASK
Definition riscv/opcodes.hpp:6751
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M2_MASK
@ PseudoVSOXSEG4EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:9416
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1UP_VX_MF4
@ PseudoVSLIDE1UP_VX_MF4
Definition riscv/opcodes.hpp:8818
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M4_E32
@ PseudoVFCVT_F_XU_V_M4_E32
Definition riscv/opcodes.hpp:1685
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VS_M8_M4
@ PseudoVAESEF_VS_M8_M4
Definition riscv/opcodes.hpp:715
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR32_M8_E32
@ PseudoVFADD_VFPR32_M8_E32
Definition riscv/opcodes.hpp:1617
LIEF::assembly::riscv::OPCODE::VSUXEI64_V
@ VSUXEI64_V
Definition riscv/opcodes.hpp:13772
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_MF8
@ PseudoVSOXSEG8EI64_V_M1_MF8
Definition riscv/opcodes.hpp:9797
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_MF2
@ PseudoVLSSEG3E16_V_MF2
Definition riscv/opcodes.hpp:5438
LIEF::assembly::riscv::OPCODE::CV_EXTRACTU
@ CV_EXTRACTU
Definition riscv/opcodes.hpp:12306
LIEF::assembly::riscv::OPCODE::VNCLIP_WI
@ VNCLIP_WI
Definition riscv/opcodes.hpp:13570
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_MF2_MASK
@ PseudoVSUXSEG2EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:10742
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF2_MASK
@ PseudoVSOXSEG8EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9774
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M1_M1_MASK
@ PseudoVSUXSEG4EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10906
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VFPR64_M2_E64
@ PseudoVFADD_VFPR64_M2_E64
Definition riscv/opcodes.hpp:1623
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF4_MASK
@ PseudoVFNRCLIP_X_F_QF_MF4_MASK
Definition riscv/opcodes.hpp:2872
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_M1_MASK
@ PseudoVSUXSEG8EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:11310
LIEF::assembly::riscv::OPCODE::MULHSU
@ MULHSU
Definition riscv/opcodes.hpp:12903
LIEF::assembly::riscv::OPCODE::CV_OR_SC_B
@ CV_OR_SC_B
Definition riscv/opcodes.hpp:12383
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VV_M1
@ PseudoVWMULSU_VV_M1
Definition riscv/opcodes.hpp:11539
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M1_M4_MASK
@ PseudoVSOXSEG2EI16_V_M1_M4_MASK
Definition riscv/opcodes.hpp:9160
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_MF2_E32_MASK
@ PseudoVFWREDOSUM_VS_MF2_E32_MASK
Definition riscv/opcodes.hpp:3930
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VX_M4
@ PseudoVMSGTU_VX_M4
Definition riscv/opcodes.hpp:7027
LIEF::assembly::riscv::OPCODE::PseudoVSE16_V_MF4_MASK
@ PseudoVSE16_V_MF4_MASK
Definition riscv/opcodes.hpp:8713
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_M1_E32_MASK
@ PseudoVFRSQRT7_V_M1_E32_MASK
Definition riscv/opcodes.hpp:3064
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF2_E16
@ PseudoVREDMAXU_VS_MF2_E16
Definition riscv/opcodes.hpp:7776
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_MF8
@ PseudoVCPOP_V_MF8
Definition riscv/opcodes.hpp:1062
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF4_E8_MASK
@ PseudoVREM_VX_MF4_E8_MASK
Definition riscv/opcodes.hpp:8257
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_MF4_MASK
@ PseudoVANDN_VX_MF4_MASK
Definition riscv/opcodes.hpp:815
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M4_M1_MASK
@ PseudoVSUXSEG3EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:10838
LIEF::assembly::riscv::OPCODE::PseudoVQMACCSU_2x8x2_M2
@ PseudoVQMACCSU_2x8x2_M2
Definition riscv/opcodes.hpp:7669
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF2_MASK
@ PseudoVSOXSEG7EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:9686
LIEF::assembly::riscv::OPCODE::VSSRA_VX
@ VSSRA_VX
Definition riscv/opcodes.hpp:13732
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_MF2_MASK
@ PseudoVSOXSEG4EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9418
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR16_MF2_E16
@ PseudoVFRDIV_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:2883
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_RTZ_X_F_V_MF4
@ PseudoVFWCVT_RTZ_X_F_V_MF4
Definition riscv/opcodes.hpp:3675
LIEF::assembly::riscv::OPCODE::FCVT_S_D
@ FCVT_S_D
Definition riscv/opcodes.hpp:12616
LIEF::assembly::riscv::OPCODE::CV_CMPLEU_SCI_H
@ CV_CMPLEU_SCI_H
Definition riscv/opcodes.hpp:12244
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI16_V_MF2_M1
@ PseudoVSUXSEG8EI16_V_MF2_M1
Definition riscv/opcodes.hpp:11261
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_M4_MASK
@ PseudoVMSLE_VV_M4_MASK
Definition riscv/opcodes.hpp:7140
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_M2_MASK
@ PseudoVRGATHER_VI_M2_MASK
Definition riscv/opcodes.hpp:8437
LIEF::assembly::riscv::OPCODE::AMOMIN_D
@ AMOMIN_D
Definition riscv/opcodes.hpp:12055
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_MF2
@ PseudoVSUXEI64_V_M4_MF2
Definition riscv/opcodes.hpp:10605
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_MF8
@ PseudoVSM4R_VS_M1_MF8
Definition riscv/opcodes.hpp:8938
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M1_MASK
@ PseudoVLUXEI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5683
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_M4_M2_MASK
@ PseudoVSUXSEG4EI16_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10916
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_M1_MASK
@ PseudoVMAX_VV_M1_MASK
Definition riscv/opcodes.hpp:6543
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M4_MASK
@ PseudoVROR_VV_M4_MASK
Definition riscv/opcodes.hpp:8553
LIEF::assembly::riscv::OPCODE::VMFEQ_VF
@ VMFEQ_VF
Definition riscv/opcodes.hpp:13503
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_MF2_MASK
@ PseudoVLUXSEG5EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:6117
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_MF2_MF4
@ PseudoVLUXSEG2EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:5792
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M4
@ PseudoVFCVT_RTZ_XU_F_V_M4
Definition riscv/opcodes.hpp:1819
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR16_M1_E16_MASK
@ PseudoVFSUB_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3392
LIEF::assembly::riscv::OPCODE::AMOSWAP_W_RL
@ AMOSWAP_W_RL
Definition riscv/opcodes.hpp:12098
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M2_MASK
@ PseudoVLOXEI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:4245
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_M1_MASK
@ PseudoVLOXSEG7EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:4917
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M1
@ PseudoVLSSEG3E64_V_M1
Definition riscv/opcodes.hpp:5448
LIEF::assembly::riscv::OPCODE::PseudoVROR_VV_M1
@ PseudoVROR_VV_M1
Definition riscv/opcodes.hpp:8548
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR64_M8
@ PseudoVMFEQ_VFPR64_M8
Definition riscv/opcodes.hpp:6626
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF4_M2_MASK
@ PseudoVSOXSEG4EI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:9498
LIEF::assembly::riscv::OPCODE::HLV_D
@ HLV_D
Definition riscv/opcodes.hpp:12802
LIEF::assembly::riscv::OPCODE::PseudoVAESDM_VV_M8
@ PseudoVAESDM_VV_M8
Definition riscv/opcodes.hpp:696
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M2_M4_MASK
@ PseudoVLOXSEG2EI8_V_M2_M4_MASK
Definition riscv/opcodes.hpp:4443
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M4_E64_MASK
@ PseudoVFMUL_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2339
LIEF::assembly::riscv::OPCODE::PseudoVBREV8_V_M4_MASK
@ PseudoVBREV8_V_M4_MASK
Definition riscv/opcodes.hpp:921
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR64_M1_E64
@ PseudoVFMIN_VFPR64_M1_E64
Definition riscv/opcodes.hpp:2154
LIEF::assembly::riscv::OPCODE::PseudoVSPILL4_M2
@ PseudoVSPILL4_M2
Definition riscv/opcodes.hpp:9843
LIEF::assembly::riscv::OPCODE::PseudoVMSBF_M_B8_MASK
@ PseudoVMSBF_M_B8_MASK
Definition riscv/opcodes.hpp:6951
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E32
@ PseudoVREM_VV_M1_E32
Definition riscv/opcodes.hpp:8174
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_MF2_E16_MASK
@ PseudoVFNCVT_F_F_W_MF2_E16_MASK
Definition riscv/opcodes.hpp:2448
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M4_E32_MASK
@ PseudoVREDXOR_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:8027
LIEF::assembly::riscv::OPCODE::FCVT_D_WU_INX
@ FCVT_D_WU_INX
Definition riscv/opcodes.hpp:12587
LIEF::assembly::riscv::OPCODE::PseudoVWMULU_VX_MF4_MASK
@ PseudoVWMULU_VX_MF4_MASK
Definition riscv/opcodes.hpp:11584
LIEF::assembly::riscv::OPCODE::VMSNE_VX
@ VMSNE_VX
Definition riscv/opcodes.hpp:13546
LIEF::assembly::riscv::OPCODE::PseudoVSHA2CL_VV_M8
@ PseudoVSHA2CL_VV_M8
Definition riscv/opcodes.hpp:8787
LIEF::assembly::riscv::OPCODE::FMINM_H
@ FMINM_H
Definition riscv/opcodes.hpp:12704
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M8_M1
@ PseudoVLUXSEG4EI64_V_M8_M1
Definition riscv/opcodes.hpp:6050
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E32_V_M1_MASK
@ PseudoVLSSEG7E32_V_M1_MASK
Definition riscv/opcodes.hpp:5537
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_MF2_M1_MASK
@ PseudoVSUXSEG2EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10680
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M2_MASK
@ PseudoVMSLEU_VX_M2_MASK
Definition riscv/opcodes.hpp:7110
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E16
@ PseudoVREMU_VV_M4_E16
Definition riscv/opcodes.hpp:8100
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_M2
@ PseudoVMINU_VV_M2
Definition riscv/opcodes.hpp:6828
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E16_V_MF4
@ PseudoVSSSEG8E16_V_MF4
Definition riscv/opcodes.hpp:10403
LIEF::assembly::riscv::OPCODE::CV_SHUFFLE_SCI_H
@ CV_SHUFFLE_SCI_H
Definition riscv/opcodes.hpp:12419
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI64_V_M2_MF2_MASK
@ PseudoVLUXSEG6EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:6213
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_MF4_E16
@ PseudoVFWNMSAC_VV_MF4_E16
Definition riscv/opcodes.hpp:3909
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR16_M4_E16
@ PseudoVFWMACC_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3735
LIEF::assembly::riscv::OPCODE::VSSE16_V
@ VSSE16_V
Definition riscv/opcodes.hpp:13698
LIEF::assembly::riscv::OPCODE::G_STRICT_FSQRT
@ G_STRICT_FSQRT
Definition riscv/opcodes.hpp:288
LIEF::assembly::riscv::OPCODE::PseudoVC_VV_SE_MF8
@ PseudoVC_VV_SE_MF8
Definition riscv/opcodes.hpp:1165
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR16_M1_MASK
@ PseudoVMFLT_VFPR16_M1_MASK
Definition riscv/opcodes.hpp:6743
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8_V_M1
@ PseudoVLSEG3E8_V_M1
Definition riscv/opcodes.hpp:5172
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M1
@ PseudoVMUL_VX_M1
Definition riscv/opcodes.hpp:7375
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VV_MF2
@ PseudoVSSUBU_VV_MF2
Definition riscv/opcodes.hpp:10427
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E32_MASK
@ PseudoVFCVT_RM_F_X_V_M8_E32_MASK
Definition riscv/opcodes.hpp:1782
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_MF4_E8
@ PseudoVREDAND_VS_MF4_E8
Definition riscv/opcodes.hpp:7740
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M8_E16
@ PseudoVFSUB_VV_M8_E16
Definition riscv/opcodes.hpp:3439
LIEF::assembly::riscv::OPCODE::AMOXOR_D_RL
@ AMOXOR_D_RL
Definition riscv/opcodes.hpp:12106
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF8_MASK
@ PseudoVLUXSEG7EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:6321
LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SCI_B
@ CV_SDOTSP_SCI_B
Definition riscv/opcodes.hpp:12395
LIEF::assembly::riscv::OPCODE::VLOXSEG6EI32_V
@ VLOXSEG6EI32_V
Definition riscv/opcodes.hpp:13353
LIEF::assembly::riscv::OPCODE::PseudoVID_V_M4
@ PseudoVID_V_M4
Definition riscv/opcodes.hpp:4059
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M4_MASK
@ PseudoVMSNE_VX_M4_MASK
Definition riscv/opcodes.hpp:7254
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF2
@ PseudoVMFNE_VV_MF2
Definition riscv/opcodes.hpp:6822
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF8_MF4_MASK
@ PseudoVSOXEI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:9152
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_M2_M2_MASK
@ PseudoVSUXSEG4EI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10992
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_MF8_MASK
@ PseudoVSLIDE1DOWN_VX_MF8_MASK
Definition riscv/opcodes.hpp:8807
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR32_M1_E32
@ PseudoVFWMSAC_VFPR32_M1_E32
Definition riscv/opcodes.hpp:3777
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_M2
@ PseudoVC_V_IV_M2
Definition riscv/opcodes.hpp:1275
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI64_V_M1_MF4_MASK
@ PseudoVLOXSEG3EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4531
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M1_MASK
@ PseudoVFCLASS_V_M1_MASK
Definition riscv/opcodes.hpp:1660
LIEF::assembly::riscv::OPCODE::PseudoVADD_VX_MF4
@ PseudoVADD_VX_MF4
Definition riscv/opcodes.hpp:636
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E32
@ PseudoVREDXOR_VS_M1_E32
Definition riscv/opcodes.hpp:8010
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF4_MASK
@ PseudoVMULHSU_VX_MF4_MASK
Definition riscv/opcodes.hpp:7302
LIEF::assembly::riscv::OPCODE::AMOMAXU_D_AQ
@ AMOMAXU_D_AQ
Definition riscv/opcodes.hpp:12008
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M4_E32
@ PseudoVREDOR_VS_M4_E32
Definition riscv/opcodes.hpp:7938
LIEF::assembly::riscv::OPCODE::PseudoVCLZ_V_M2_MASK
@ PseudoVCLZ_V_M2_MASK
Definition riscv/opcodes.hpp:1003
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_MF2_E16_MASK
@ PseudoVFREDOSUM_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:3020
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF8_MASK
@ PseudoVSSEG6E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10122
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_M1
@ PseudoVC_V_FPR32VV_M1
Definition riscv/opcodes.hpp:1202
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF2
@ PseudoVLSEG3E8FF_V_MF2
Definition riscv/opcodes.hpp:5166
LIEF::assembly::riscv::OPCODE::PseudoVLE16_V_M4
@ PseudoVLE16_V_M4
Definition riscv/opcodes.hpp:4099
LIEF::assembly::riscv::OPCODE::PseudoVANDN_VX_M4
@ PseudoVANDN_VX_M4
Definition riscv/opcodes.hpp:808
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF8_MASK
@ PseudoVLSEG4E8FF_V_MF8_MASK
Definition riscv/opcodes.hpp:5227
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VFPR32_M1_E32_MASK
@ PseudoVFSGNJ_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:3254
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI16_V_MF2_MF2_MASK
@ PseudoVSUXSEG4EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10922
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VV_M2_MASK
@ PseudoVSUB_VV_M2_MASK
Definition riscv/opcodes.hpp:10478
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VV_MF2
@ PseudoVSM4R_VV_MF2
Definition riscv/opcodes.hpp:8963
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_MF4
@ PseudoVWSLL_VX_MF4
Definition riscv/opcodes.hpp:11715
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_M1_MASK
@ PseudoVLSSEG4E16_V_M1_MASK
Definition riscv/opcodes.hpp:5463
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF8
@ PseudoVLUXSEG3EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:5916
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M1_MF2_MASK
@ PseudoVSOXEI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9046
LIEF::assembly::riscv::OPCODE::VFWNMSAC_VF
@ VFWNMSAC_VF
Definition riscv/opcodes.hpp:13295
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_M1_M1
@ PseudoVSUXSEG2EI32_V_M1_M1
Definition riscv/opcodes.hpp:10695
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WFPR16_MF2_E16
@ PseudoVFWSUB_WFPR16_MF2_E16
Definition riscv/opcodes.hpp:3997
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M8_M2
@ PseudoVSUXSEG3EI64_V_M8_M2
Definition riscv/opcodes.hpp:10875
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VI_M1_MASK
@ PseudoVSRA_VI_M1_MASK
Definition riscv/opcodes.hpp:9864
LIEF::assembly::riscv::OPCODE::PseudoCCXNOR
@ PseudoCCXNOR
Definition riscv/opcodes.hpp:366
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E32_MASK
@ PseudoVREDAND_VS_M8_E32_MASK
Definition riscv/opcodes.hpp:7727
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8FF_V_MF8
@ PseudoVLSEG5E8FF_V_MF8
Definition riscv/opcodes.hpp:5268
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E8_V_MF8
@ PseudoVSSSEG5E8_V_MF8
Definition riscv/opcodes.hpp:10357
LIEF::assembly::riscv::OPCODE::PseudoVMAND_MM_MF8
@ PseudoVMAND_MM_MF8
Definition riscv/opcodes.hpp:6513
LIEF::assembly::riscv::OPCODE::SH
@ SH
Definition riscv/opcodes.hpp:12958
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M1_E64
@ PseudoVFCVT_F_X_V_M1_E64
Definition riscv/opcodes.hpp:1705
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF2_MASK
@ PseudoVMSLE_VV_MF2_MASK
Definition riscv/opcodes.hpp:7144
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF4_M1_MASK
@ PseudoVLUXSEG6EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:6229
LIEF::assembly::riscv::OPCODE::VNSRL_WX
@ VNSRL_WX
Definition riscv/opcodes.hpp:13582
LIEF::assembly::riscv::OPCODE::PseudoVMFGE_VFPR16_M1
@ PseudoVMFGE_VFPR16_M1
Definition riscv/opcodes.hpp:6640
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK
@ PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK
Definition riscv/opcodes.hpp:8289
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF2_MF2_MASK
@ PseudoVLOXEI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:4317
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_M1_E32
@ PseudoVFWMACCBF16_VV_M1_E32
Definition riscv/opcodes.hpp:3709
LIEF::assembly::riscv::OPCODE::C_MOP7
@ C_MOP7
Definition riscv/opcodes.hpp:12518
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M1_MASK
@ PseudoVWADDU_WX_M1_MASK
Definition riscv/opcodes.hpp:11384
LIEF::assembly::riscv::OPCODE::VLSSEG3E64_V
@ VLSSEG3E64_V
Definition riscv/opcodes.hpp:13430
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E8
@ PseudoVDIVU_VX_MF2_E8
Definition riscv/opcodes.hpp:1503
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_M2_M2
@ PseudoVLUXSEG4EI8_V_M2_M2
Definition riscv/opcodes.hpp:6058
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI16_V_MF2_M1_MASK
@ PseudoVLOXSEG4EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4593
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E32
@ PseudoVFREDUSUM_VS_M2_E32
Definition riscv/opcodes.hpp:3033
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR64_M4
@ PseudoVFMV_S_FPR64_M4
Definition riscv/opcodes.hpp:2400
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF8_MASK
@ PseudoVSUXSEG6EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:11134
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M1_MASK
@ PseudoVROL_VV_M1_MASK
Definition riscv/opcodes.hpp:8507
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32V_SE_M4
@ PseudoVC_FPR32V_SE_M4
Definition riscv/opcodes.hpp:1108
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI8_V_MF8_MF8_MASK
@ PseudoVLUXSEG5EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:6161
LIEF::assembly::riscv::OPCODE::PseudoVSE8_V_M4
@ PseudoVSE8_V_M4
Definition riscv/opcodes.hpp:8736
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VFPR32_M2
@ PseudoVMFLT_VFPR32_M2
Definition riscv/opcodes.hpp:6756
LIEF::assembly::riscv::OPCODE::TH_FSRD
@ TH_FSRD
Definition riscv/opcodes.hpp:13050
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF2_MASK
@ PseudoVSOXSEG8EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9786
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG4E64_V_M1
@ PseudoVSSSEG4E64_V_M1
Definition riscv/opcodes.hpp:10325
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M1
@ PseudoVWMACCSU_VX_M1
Definition riscv/opcodes.hpp:11467
LIEF::assembly::riscv::OPCODE::VFREDOSUM_VS
@ VFREDOSUM_VS
Definition riscv/opcodes.hpp:13257
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI32_V_M8_M8_MASK
@ PseudoVLOXEI32_V_M8_M8_MASK
Definition riscv/opcodes.hpp:4249
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_ROD_F_F_W_M2_E32
@ PseudoVFNCVT_ROD_F_F_W_M2_E32
Definition riscv/opcodes.hpp:2555
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_M1_MASK
@ PseudoVLUXSEG7EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6305
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_M2_E16
@ PseudoVFWNMACC_VV_M2_E16
Definition riscv/opcodes.hpp:3861
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_MF4_MASK
@ PseudoVSUXSEG5EI8_V_MF8_MF4_MASK
Definition riscv/opcodes.hpp:11092
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF8_MF8_MASK
@ PseudoVLOXSEG7EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:4929
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VV_MF4
@ PseudoVMFNE_VV_MF4
Definition riscv/opcodes.hpp:6824
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF8_MASK
@ PseudoVLUXSEG3EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:5917
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M2_M4
@ PseudoVSUXSEG2EI16_V_M2_M4
Definition riscv/opcodes.hpp:10671
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M4_M8_MASK
@ PseudoVSUXEI16_V_M4_M8_MASK
Definition riscv/opcodes.hpp:10524
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M4_E16
@ PseudoVFWADD_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3455
LIEF::assembly::riscv::OPCODE::DBG_INSTR_REF
@ DBG_INSTR_REF
Definition riscv/opcodes.hpp:39
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E16_V_MF4_MASK
@ PseudoVSSSEG7E16_V_MF4_MASK
Definition riscv/opcodes.hpp:10384
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI64_V_M2_MF2_MASK
@ PseudoVSUXSEG5EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:11066
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_M1_MF2
@ PseudoVLUXSEG6EI16_V_M1_MF2
Definition riscv/opcodes.hpp:6164
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M4_M2
@ PseudoVLOXSEG2EI16_V_M4_M2
Definition riscv/opcodes.hpp:4348
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_MF8_MASK
@ PseudoVXOR_VI_MF8_MASK
Definition riscv/opcodes.hpp:11852
LIEF::assembly::riscv::OPCODE::VFSLIDE1UP_VF
@ VFSLIDE1UP_VF
Definition riscv/opcodes.hpp:13268
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF4
@ PseudoVAADD_VX_MF4
Definition riscv/opcodes.hpp:573
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD2_M4
@ PseudoVRELOAD2_M4
Definition riscv/opcodes.hpp:8054
LIEF::assembly::riscv::OPCODE::CV_PACK_H
@ CV_PACK_H
Definition riscv/opcodes.hpp:12388
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VI_M4_MASK
@ PseudoVMSLEU_VI_M4_MASK
Definition riscv/opcodes.hpp:7084
LIEF::assembly::riscv::OPCODE::C_LWSP
@ C_LWSP
Definition riscv/opcodes.hpp:12511
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16V_SE_M4
@ PseudoVC_V_FPR16V_SE_M4
Definition riscv/opcodes.hpp:1198
LIEF::assembly::riscv::OPCODE::TH_SWIA
@ TH_SWIA
Definition riscv/opcodes.hpp:13121
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF4_M4_MASK
@ PseudoVZEXT_VF4_M4_MASK
Definition riscv/opcodes.hpp:11898
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_SE_M2
@ PseudoVC_V_FPR32VW_SE_M2
Definition riscv/opcodes.hpp:1218
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M1_E32
@ PseudoVFWCVT_F_X_V_M1_E32
Definition riscv/opcodes.hpp:3609
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI8_V_MF8_MF8
@ PseudoVLOXSEG3EI8_V_MF8_MF8
Definition riscv/opcodes.hpp:4578
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VX_M8_MASK
@ PseudoVMAX_VX_M8_MASK
Definition riscv/opcodes.hpp:6563
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M1_MASK
@ PseudoVWMACCSU_VX_M1_MASK
Definition riscv/opcodes.hpp:11468
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VV_SE_M1
@ PseudoVC_V_FPR32VV_SE_M1
Definition riscv/opcodes.hpp:1207
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_SE_M2
@ PseudoVC_V_FPR16VV_SE_M2
Definition riscv/opcodes.hpp:1173
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M2_E16
@ PseudoVFNCVT_F_X_W_M2_E16
Definition riscv/opcodes.hpp:2475
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR32VW_SE_M8
@ PseudoVC_V_FPR32VW_SE_M8
Definition riscv/opcodes.hpp:1220
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF2
@ PseudoVSOXSEG8EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:9759
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M8_M2_MASK
@ PseudoVSUXSEG4EI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:10986
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR32_M1_E32_MASK
@ PseudoVFNMADD_VFPR32_M1_E32_MASK
Definition riscv/opcodes.hpp:2688
LIEF::assembly::riscv::OPCODE::VSE8_V
@ VSE8_V
Definition riscv/opcodes.hpp:13633
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M1_MASK
@ PseudoVSEXT_VF8_M1_MASK
Definition riscv/opcodes.hpp:8772
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF8
@ PseudoVSUXSEG7EI16_V_MF4_MF8
Definition riscv/opcodes.hpp:11193
LIEF::assembly::riscv::OPCODE::CV_CMPGEU_B
@ CV_CMPGEU_B
Definition riscv/opcodes.hpp:12217
LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M1
@ PseudoVGHSH_VV_M1
Definition riscv/opcodes.hpp:4045
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IVW_SE_MF2
@ PseudoVC_V_IVW_SE_MF2
Definition riscv/opcodes.hpp:1271
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_MF2_E16_MASK
@ PseudoVREDMAX_VS_MF2_E16_MASK
Definition riscv/opcodes.hpp:7821
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M1_E16_MASK
@ PseudoVFMACC_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:1938
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E16_MASK
@ PseudoVFSQRT_V_M8_E16_MASK
Definition riscv/opcodes.hpp:3380
LIEF::assembly::riscv::OPCODE::FMAXM_S
@ FMAXM_S
Definition riscv/opcodes.hpp:12695
LIEF::assembly::riscv::OPCODE::G_ASSERT_ZEXT
@ G_ASSERT_ZEXT
Definition riscv/opcodes.hpp:73
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M1_MASK
@ PseudoVSLIDEDOWN_VI_M1_MASK
Definition riscv/opcodes.hpp:8823
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF2_E32
@ PseudoVFWADD_VV_MF2_E32
Definition riscv/opcodes.hpp:3483
LIEF::assembly::riscv::OPCODE::PseudoVLSE64_V_M2
@ PseudoVLSE64_V_M2
Definition riscv/opcodes.hpp:5034
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR32VV_SE_M4
@ PseudoVC_FPR32VV_SE_M4
Definition riscv/opcodes.hpp:1098
LIEF::assembly::riscv::OPCODE::FLT_H_INX
@ FLT_H_INX
Definition riscv/opcodes.hpp:12682
LIEF::assembly::riscv::OPCODE::REMUW
@ REMUW
Definition riscv/opcodes.hpp:12926
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR32_M4_E32_MASK
@ PseudoVFSGNJN_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3138
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VFPR16_M4_E16_MASK
@ PseudoVFWNMACC_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3844
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WV_M1_TIED
@ PseudoVWADDU_WV_M1_TIED
Definition riscv/opcodes.hpp:11362
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF2
@ PseudoVMULHSU_VX_MF2
Definition riscv/opcodes.hpp:7299
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_MF4
@ PseudoVSOXEI32_V_MF2_MF4
Definition riscv/opcodes.hpp:9075
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK
@ PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK
Definition riscv/opcodes.hpp:8303
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR64_M8_MASK
@ PseudoVFSLIDE1DOWN_VFPR64_M8_MASK
Definition riscv/opcodes.hpp:3330
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M4_E16_MASK
@ PseudoVFDIV_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:1906
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M2_TIED
@ PseudoVWSUBU_WV_M2_TIED
Definition riscv/opcodes.hpp:11750
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_M4
@ PseudoVWSUBU_WV_M4
Definition riscv/opcodes.hpp:11751
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M2_MASK
@ PseudoVSRL_VV_M2_MASK
Definition riscv/opcodes.hpp:9922
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M8_M2
@ PseudoVSUXSEG4EI32_V_M8_M2
Definition riscv/opcodes.hpp:10951
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF2_M2
@ PseudoVLOXSEG2EI16_V_MF2_M2
Definition riscv/opcodes.hpp:4356
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_MF4_MASK
@ PseudoVLSEG7E8FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5347
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR32_M4
@ PseudoVMFLE_VFPR32_M4
Definition riscv/opcodes.hpp:6716
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_MF2_E16_MASK
@ PseudoVFSQRT_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:3386
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E16
@ PseudoVREMU_VX_M4_E16
Definition riscv/opcodes.hpp:8144
LIEF::assembly::riscv::OPCODE::VCPOP_M
@ VCPOP_M
Definition riscv/opcodes.hpp:13169
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_MF2
@ PseudoVMFNE_VFPR32_MF2
Definition riscv/opcodes.hpp:6804
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M2_E32
@ PseudoVFMUL_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2326
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR64_M1
@ PseudoVFMV_V_FPR64_M1
Definition riscv/opcodes.hpp:2413
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M4_E16_MASK
@ PseudoVFWADD_WV_M4_E16_MASK
Definition riscv/opcodes.hpp:3522
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_XU_F_V_M4
@ PseudoVFWCVT_XU_F_V_M4
Definition riscv/opcodes.hpp:3681
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M1_MF8_MASK
@ PseudoVLOXEI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:4265
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VVM_MF8
@ PseudoVMADC_VVM_MF8
Definition riscv/opcodes.hpp:6450
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E8_V_MF8_MASK
@ PseudoVLSSEG7E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5549
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_M8_MASK
@ PseudoVMIN_VV_M8_MASK
Definition riscv/opcodes.hpp:6861
LIEF::assembly::riscv::OPCODE::VLE32FF_V
@ VLE32FF_V
Definition riscv/opcodes.hpp:13325
LIEF::assembly::riscv::OPCODE::AMOMAXU_D_RL
@ AMOMAXU_D_RL
Definition riscv/opcodes.hpp:12010
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI8_V_MF4_MF4
@ PseudoVLOXSEG6EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:4840
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_MF2_M1_MASK
@ PseudoVSOXEI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9072
LIEF::assembly::riscv::OPCODE::VL8RE16_V
@ VL8RE16_V
Definition riscv/opcodes.hpp:13319
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI64_V_M2_M1
@ PseudoVSOXSEG4EI64_V_M2_M1
Definition riscv/opcodes.hpp:9465
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M1
@ PseudoVWSLL_VX_M1
Definition riscv/opcodes.hpp:11707
LIEF::assembly::riscv::OPCODE::PseudoVC_XVV_SE_M2
@ PseudoVC_XVV_SE_M2
Definition riscv/opcodes.hpp:1397
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M2
@ PseudoVLUXEI16_V_M1_M2
Definition riscv/opcodes.hpp:5572
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M4_M2_MASK
@ PseudoVSUXSEG2EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:10748
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF2_M2
@ PseudoVLOXSEG2EI8_V_MF2_M2
Definition riscv/opcodes.hpp:4448
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_M8
@ PseudoVAADDU_VV_M8
Definition riscv/opcodes.hpp:527
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E32_MASK
@ PseudoVREDMIN_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:7879
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_MF2_E32
@ PseudoVFMUL_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2332
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M2_MASK
@ PseudoVMFGT_VFPR16_M2_MASK
Definition riscv/opcodes.hpp:6673
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR64_M8_E64
@ PseudoVFDIV_VFPR64_M8_E64
Definition riscv/opcodes.hpp:1891
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_MF8_MASK
@ PseudoVCLMULH_VX_MF8_MASK
Definition riscv/opcodes.hpp:971
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E8
@ PseudoVDIVU_VV_M4_E8
Definition riscv/opcodes.hpp:1445
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E8
@ PseudoVWREDSUM_VS_MF4_E8
Definition riscv/opcodes.hpp:11679
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_M1
@ PseudoVFNCVT_RM_XU_F_W_M1
Definition riscv/opcodes.hpp:2525
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M8_E8
@ PseudoVREDMINU_VS_M8_E8
Definition riscv/opcodes.hpp:7862
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M2_E16
@ PseudoVFMACC_VV_M2_E16
Definition riscv/opcodes.hpp:1973
LIEF::assembly::riscv::OPCODE::PseudoVSPILL7_M1
@ PseudoVSPILL7_M1
Definition riscv/opcodes.hpp:9855
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M4
@ PseudoVWMACC_VV_M4
Definition riscv/opcodes.hpp:11519
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M2_M1
@ PseudoVSUXEI64_V_M2_M1
Definition riscv/opcodes.hpp:10591
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_M2_E16_MASK
@ PseudoVFWMSAC_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:3770
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF4_E8
@ PseudoVFWCVT_F_XU_V_MF4_E8
Definition riscv/opcodes.hpp:3603
LIEF::assembly::riscv::OPCODE::CV_MULHHURN
@ CV_MULHHURN
Definition riscv/opcodes.hpp:12374
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M2_MF2
@ PseudoVLOXEI64_V_M2_MF2
Definition riscv/opcodes.hpp:4270
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VX_MF4
@ PseudoVMSLTU_VX_MF4
Definition riscv/opcodes.hpp:7188
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_M1
@ PseudoVLUXSEG5EI32_V_MF2_M1
Definition riscv/opcodes.hpp:6114
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M4_E64_MASK
@ PseudoVFSGNJN_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:3148
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF4
@ PseudoVLUXSEG4EI32_V_M1_MF4
Definition riscv/opcodes.hpp:6006
LIEF::assembly::riscv::OPCODE::G_STACKSAVE
@ G_STACKSAVE
Definition riscv/opcodes.hpp:280
LIEF::assembly::riscv::OPCODE::PseudoQuietFLE_H
@ PseudoQuietFLE_H
Definition riscv/opcodes.hpp:421
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF8_MF8_MASK
@ PseudoVSOXSEG3EI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:9400
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M1_E64_MASK
@ PseudoVFSGNJN_VV_M1_E64_MASK
Definition riscv/opcodes.hpp:3156
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E8
@ PseudoVREDMAXU_VS_MF4_E8
Definition riscv/opcodes.hpp:7784
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI16_V_MF2_M1
@ PseudoVSOXSEG4EI16_V_MF2_M1
Definition riscv/opcodes.hpp:9413
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF4_MASK
@ PseudoVSUXSEG2EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:10726
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M1
@ PseudoVMSNE_VV_M1
Definition riscv/opcodes.hpp:7235
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M8_E32
@ PseudoVREDOR_VS_M8_E32
Definition riscv/opcodes.hpp:7946
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_M2_M4
@ PseudoVLOXSEG2EI16_V_M2_M4
Definition riscv/opcodes.hpp:4346
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M4
@ PseudoVSOXSEG2EI16_V_M2_M4
Definition riscv/opcodes.hpp:9167
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_MF4_E8_MASK
@ PseudoVDIVU_VV_MF4_E8_MASK
Definition riscv/opcodes.hpp:1464
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF8
@ PseudoVSMUL_VV_MF8
Definition riscv/opcodes.hpp:8976
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M8_MASK
@ PseudoVMFLE_VV_M8_MASK
Definition riscv/opcodes.hpp:6737
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M4_E32
@ PseudoVFWCVT_F_X_V_M4_E32
Definition riscv/opcodes.hpp:3621
LIEF::assembly::riscv::OPCODE::VC_V_FVV
@ VC_V_FVV
Definition riscv/opcodes.hpp:13183
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M8_E16
@ PseudoVFREC7_V_M8_E16
Definition riscv/opcodes.hpp:2923
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M1_M2
@ PseudoVSUXEI32_V_M1_M2
Definition riscv/opcodes.hpp:10547
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E16_V_MF2
@ PseudoVSSSEG3E16_V_MF2
Definition riscv/opcodes.hpp:10287
LIEF::assembly::riscv::OPCODE::AMOADD_W_AQ_RL
@ AMOADD_W_AQ_RL
Definition riscv/opcodes.hpp:11961
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_MF4
@ PseudoVNMSUB_VV_MF4
Definition riscv/opcodes.hpp:7536
LIEF::assembly::riscv::OPCODE::PseudoVAESEF_VV_M4
@ PseudoVAESEF_VV_M4
Definition riscv/opcodes.hpp:724
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M8_E16
@ PseudoVFCVT_F_XU_V_M8_E16
Definition riscv/opcodes.hpp:1689
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_M2_MASK
@ PseudoVSADD_VX_M2_MASK
Definition riscv/opcodes.hpp:8677
LIEF::assembly::riscv::OPCODE::STATEPOINT
@ STATEPOINT
Definition riscv/opcodes.hpp:55
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_MF4_E16
@ PseudoVFWMACC_VV_MF4_E16
Definition riscv/opcodes.hpp:3765
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M2_E32
@ PseudoVREDXOR_VS_M2_E32
Definition riscv/opcodes.hpp:8018
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI64_V_M1_M1_MASK
@ PseudoVSUXSEG6EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11136
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M2_M1
@ PseudoVSOXSEG7EI32_V_M2_M1
Definition riscv/opcodes.hpp:9697
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VX_M1_MASK
@ PseudoVSSUB_VX_M1_MASK
Definition riscv/opcodes.hpp:10462
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF4_E16
@ PseudoVFWSUB_WV_MF4_E16
Definition riscv/opcodes.hpp:4041
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_MF4_E16
@ PseudoVDIV_VX_MF4_E16
Definition riscv/opcodes.hpp:1593
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_MF2_M1
@ PseudoVLOXSEG4EI32_V_MF2_M1
Definition riscv/opcodes.hpp:4628
LIEF::assembly::riscv::OPCODE::PREFETCH_I
@ PREFETCH_I
Definition riscv/opcodes.hpp:12913
LIEF::assembly::riscv::OPCODE::MOPRR6
@ MOPRR6
Definition riscv/opcodes.hpp:12898
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF8_MASK
@ PseudoVLSSEG4E8_V_MF8_MASK
Definition riscv/opcodes.hpp:5489
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VI_M2_MASK
@ PseudoVSLL_VI_M2_MASK
Definition riscv/opcodes.hpp:8881
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E32
@ PseudoVWREDSUMU_VS_M2_E32
Definition riscv/opcodes.hpp:11619
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M4
@ PseudoVSUB_VX_M4
Definition riscv/opcodes.hpp:10493
LIEF::assembly::riscv::OPCODE::LR_D_AQ_RL
@ LR_D_AQ_RL
Definition riscv/opcodes.hpp:12845
LIEF::assembly::riscv::OPCODE::CV_SDOTSP_SC_B
@ CV_SDOTSP_SC_B
Definition riscv/opcodes.hpp:12397
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M8_MASK
@ PseudoVSSRA_VI_M8_MASK
Definition riscv/opcodes.hpp:10170
LIEF::assembly::riscv::OPCODE::G_USUBO
@ G_USUBO
Definition riscv/opcodes.hpp:172
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M1
@ PseudoVLUXSEG3EI64_V_M8_M1
Definition riscv/opcodes.hpp:5940
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI8_V_MF8_MF2_MASK
@ PseudoVSUXSEG3EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:10900
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF8_MF2
@ PseudoVLUXSEG7EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:6316
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI64_V_M1_MF4
@ PseudoVLUXSEG4EI64_V_M1_MF4
Definition riscv/opcodes.hpp:6032
LIEF::assembly::riscv::OPCODE::FSGNJX_S
@ FSGNJX_S
Definition riscv/opcodes.hpp:12769
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_MF2_MASK
@ PseudoVSUXSEG8EI8_V_MF8_MF2_MASK
Definition riscv/opcodes.hpp:11330
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_M4_E16
@ PseudoVFMACC_VFPR16_M4_E16
Definition riscv/opcodes.hpp:1941
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_M2_E16_MASK_TIED
@ PseudoVFWADD_WV_M2_E16_MASK_TIED
Definition riscv/opcodes.hpp:3515
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M8_MASK
@ PseudoVMULHU_VX_M8_MASK
Definition riscv/opcodes.hpp:7326
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E32_MASK
@ PseudoVFWNMSAC_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3896
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF8_MASK
@ PseudoVSSSEG3E8_V_MF8_MASK
Definition riscv/opcodes.hpp:10310
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_MF2
@ PseudoVMFGT_VFPR16_MF2
Definition riscv/opcodes.hpp:6678
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_MF8
@ PseudoVAESZ_VS_M4_MF8
Definition riscv/opcodes.hpp:780
LIEF::assembly::riscv::OPCODE::FCVT_L_S_INX
@ FCVT_L_S_INX
Definition riscv/opcodes.hpp:12614
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_MF2
@ PseudoVSUB_VX_MF2
Definition riscv/opcodes.hpp:10497
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M4
@ PseudoVFSLIDE1UP_VFPR16_M4
Definition riscv/opcodes.hpp:3335
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VX_M8_MASK
@ PseudoVXOR_VX_M8_MASK
Definition riscv/opcodes.hpp:11874
LIEF::assembly::riscv::OPCODE::CV_CMPGEU_SCI_B
@ CV_CMPGEU_SCI_B
Definition riscv/opcodes.hpp:12219
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E32_V_M1_MASK
@ PseudoVLSEG5E32_V_M1_MASK
Definition riscv/opcodes.hpp:5255
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_MF4_E16
@ PseudoVFCVT_RM_F_XU_V_MF4_E16
Definition riscv/opcodes.hpp:1759
LIEF::assembly::riscv::OPCODE::PseudoVMAX_VV_MF8_MASK
@ PseudoVMAX_VV_MF8_MASK
Definition riscv/opcodes.hpp:6555
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_M1_M1
@ PseudoVSUXSEG8EI8_V_M1_M1
Definition riscv/opcodes.hpp:11315
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI32_V_MF2_MF8
@ PseudoVLOXSEG7EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:4888
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_M1_MF2
@ PseudoVSOXSEG8EI32_V_M1_MF2
Definition riscv/opcodes.hpp:9773
LIEF::assembly::riscv::OPCODE::PseudoBR
@ PseudoBR
Definition riscv/opcodes.hpp:332
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_MF4
@ PseudoVLUXSEG6EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:6178
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E16_MASK
@ PseudoVFSUB_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:3434
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M4_E16
@ PseudoVFWMUL_VFPR16_M4_E16
Definition riscv/opcodes.hpp:3807
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_MF4_MF2
@ PseudoVSUXSEG7EI16_V_MF4_MF2
Definition riscv/opcodes.hpp:11189
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR32_MF2_E32
@ PseudoVFMSAC_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:2212
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF2
@ PseudoVSMUL_VX_MF2
Definition riscv/opcodes.hpp:8986
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF2_MASK
@ PseudoVBREV_V_MF2_MASK
Definition riscv/opcodes.hpp:939
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M2_E8
@ PseudoVWREDSUMU_VS_M2_E8
Definition riscv/opcodes.hpp:11621
LIEF::assembly::riscv::OPCODE::CV_DOTUSP_SC_H
@ CV_DOTUSP_SC_H
Definition riscv/opcodes.hpp:12298
LIEF::assembly::riscv::OPCODE::EH_LABEL
@ EH_LABEL
Definition riscv/opcodes.hpp:28
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M4_E32_MASK
@ PseudoVREDSUM_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:7983
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_MF4_MF2_MASK
@ PseudoVLOXSEG2EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4459
LIEF::assembly::riscv::OPCODE::PseudoVFRSUB_VFPR32_M4_E32_MASK
@ PseudoVFRSUB_VFPR32_M4_E32_MASK
Definition riscv/opcodes.hpp:3108
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M4_E32
@ PseudoVFWMACC_VV_M4_E32
Definition riscv/opcodes.hpp:3759
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VV_M1
@ PseudoVNMSAC_VV_M1
Definition riscv/opcodes.hpp:7498
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_MF8_M1_MASK
@ PseudoVSOXSEG2EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:9284
LIEF::assembly::riscv::OPCODE::FCVT_D_WU_IN32X
@ FCVT_D_WU_IN32X
Definition riscv/opcodes.hpp:12586
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_MF2
@ PseudoVLOXSEG8EI16_V_MF2_MF2
Definition riscv/opcodes.hpp:4938
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E8FF_V_M1_MASK
@ PseudoVLSEG7E8FF_V_M1_MASK
Definition riscv/opcodes.hpp:5343
LIEF::assembly::riscv::OPCODE::SH2ADD_UW
@ SH2ADD_UW
Definition riscv/opcodes.hpp:12962
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF8_MF2
@ PseudoVSOXSEG8EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:9825
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF8_MF2
@ PseudoVLUXEI8_V_MF8_MF2
Definition riscv/opcodes.hpp:5720
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M4_E32
@ PseudoVFCVT_RM_F_X_V_M4_E32
Definition riscv/opcodes.hpp:1775
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M2_MF2
@ PseudoVLUXSEG3EI64_V_M2_MF2
Definition riscv/opcodes.hpp:5930
LIEF::assembly::riscv::OPCODE::PseudoVWSUBU_WV_MF4_MASK
@ PseudoVWSUBU_WV_MF4_MASK
Definition riscv/opcodes.hpp:11760
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M1_E32_MASK
@ PseudoVFNCVT_F_F_W_M1_E32_MASK
Definition riscv/opcodes.hpp:2438
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M2
@ PseudoVSLIDE1DOWN_VX_M2
Definition riscv/opcodes.hpp:8796
LIEF::assembly::riscv::OPCODE::TH_LDIA
@ TH_LDIA
Definition riscv/opcodes.hpp:13066
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_X_F_QF_MF8
@ PseudoVFNRCLIP_X_F_QF_MF8
Definition riscv/opcodes.hpp:2873
LIEF::assembly::riscv::OPCODE::FNMSUB_S_INX
@ FNMSUB_S_INX
Definition riscv/opcodes.hpp:12749
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_MF2_MF4_MASK
@ PseudoVSUXEI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:10536
LIEF::assembly::riscv::OPCODE::G_SEXT
@ G_SEXT
Definition riscv/opcodes.hpp:155
LIEF::assembly::riscv::OPCODE::VFMIN_VV
@ VFMIN_VV
Definition riscv/opcodes.hpp:13224
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M2_E32
@ PseudoVFRDIV_VFPR32_M2_E32
Definition riscv/opcodes.hpp:2889
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_MF4
@ PseudoVSM4R_VS_M4_MF4
Definition riscv/opcodes.hpp:8948
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI64_V_M1_M1_MASK
@ PseudoVSOXSEG8EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9792
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR64_M1_E64
@ PseudoVFSUB_VFPR64_M1_E64
Definition riscv/opcodes.hpp:3413
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XV_SE_M8
@ PseudoVC_V_XV_SE_M8
Definition riscv/opcodes.hpp:1378
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_M8_MASK
@ PseudoVSRL_VV_M8_MASK
Definition riscv/opcodes.hpp:9926
LIEF::assembly::riscv::OPCODE::PseudoVREDOR_VS_M1_E16_MASK
@ PseudoVREDOR_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:7921
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M8_M8_MASK
@ PseudoVSUXEI16_V_M8_M8_MASK
Definition riscv/opcodes.hpp:10528
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_MF4_E16_MASK
@ PseudoVFMAX_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:2116
LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M2_MASK
@ PseudoVLE32FF_V_M2_MASK
Definition riscv/opcodes.hpp:4110
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF8
@ PseudoVSSSEG3E8_V_MF8
Definition riscv/opcodes.hpp:10309
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_MF8
@ PseudoVRELOAD5_MF8
Definition riscv/opcodes.hpp:8071
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_M4_E16_MASK
@ PseudoVFADD_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:1642
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF4
@ PseudoVSUXSEG8EI64_V_M2_MF4
Definition riscv/opcodes.hpp:11307
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_MF4
@ PseudoVC_FPR16VV_SE_MF4
Definition riscv/opcodes.hpp:1083
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_MF8
@ PseudoVWMACC_VV_MF8
Definition riscv/opcodes.hpp:11525
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR16_MF2
@ PseudoVMFEQ_VFPR16_MF2
Definition riscv/opcodes.hpp:6606
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VX_M2
@ PseudoVMIN_VX_M2
Definition riscv/opcodes.hpp:6870
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_MF4_E16_MASK
@ PseudoVREDMAXU_VS_MF4_E16_MASK
Definition riscv/opcodes.hpp:7783
LIEF::assembly::riscv::OPCODE::VCOMPRESS_VM
@ VCOMPRESS_VM
Definition riscv/opcodes.hpp:13168
LIEF::assembly::riscv::OPCODE::FCVT_S_D_IN32X
@ FCVT_S_D_IN32X
Definition riscv/opcodes.hpp:12617
LIEF::assembly::riscv::OPCODE::AMOOR_W_AQ_RL
@ AMOOR_W_AQ_RL
Definition riscv/opcodes.hpp:12081
LIEF::assembly::riscv::OPCODE::VMULHU_VX
@ VMULHU_VX
Definition riscv/opcodes.hpp:13551
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E32_MASK
@ PseudoVFSGNJX_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:3220
LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_R
@ CV_CPLXMUL_R
Definition riscv/opcodes.hpp:12277
LIEF::assembly::riscv::OPCODE::PseudoVSUB_VX_M8
@ PseudoVSUB_VX_M8
Definition riscv/opcodes.hpp:10495
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF4
@ PseudoVRGATHEREI16_VV_M1_E64_MF4
Definition riscv/opcodes.hpp:8296
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VV_M2_MASK
@ PseudoVMFLE_VV_M2_MASK
Definition riscv/opcodes.hpp:6733
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR64_M1_E64_MASK
@ PseudoVFMAX_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2080
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_M2
@ PseudoVFMV_V_FPR16_M2
Definition riscv/opcodes.hpp:2403
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_M4_E8
@ PseudoVRGATHER_VV_M4_E8
Definition riscv/opcodes.hpp:8470
LIEF::assembly::riscv::OPCODE::C_SUB
@ C_SUB
Definition riscv/opcodes.hpp:12542
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF2
@ PseudoVSSEG6E8_V_MF2
Definition riscv/opcodes.hpp:10117
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M1_E32_MASK
@ PseudoVFMSUB_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:2285
LIEF::assembly::riscv::OPCODE::InsnI
@ InsnI
Definition riscv/opcodes.hpp:12823
LIEF::assembly::riscv::OPCODE::FMUL_D
@ FMUL_D
Definition riscv/opcodes.hpp:12720
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF8_E8
@ PseudoVWREDSUM_VS_MF8_E8
Definition riscv/opcodes.hpp:11681
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M2
@ PseudoVLSSEG3E8_V_M2
Definition riscv/opcodes.hpp:5454
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI8_V_MF2_M1
@ PseudoVLUXSEG7EI8_V_MF2_M1
Definition riscv/opcodes.hpp:6304
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B1_MASK
@ PseudoVMSOF_M_B1_MASK
Definition riscv/opcodes.hpp:7266
LIEF::assembly::riscv::OPCODE::PseudoVFREDMIN_VS_M1_E16
@ PseudoVFREDMIN_VS_M1_E16
Definition riscv/opcodes.hpp:2965
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_M1_E8
@ PseudoVFWCVT_F_XU_V_M1_E8
Definition riscv/opcodes.hpp:3581
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E16_MASK
@ PseudoVFWCVTBF16_F_F_V_M4_E16_MASK
Definition riscv/opcodes.hpp:3550
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M1_E64
@ PseudoVFSGNJN_VFPR64_M1_E64
Definition riscv/opcodes.hpp:3143
LIEF::assembly::riscv::OPCODE::VSUXSEG6EI8_V
@ VSUXSEG6EI8_V
Definition riscv/opcodes.hpp:13793
LIEF::assembly::riscv::OPCODE::PseudoVSSEG8E8_V_MF8
@ PseudoVSSEG8E8_V_MF8
Definition riscv/opcodes.hpp:10161
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WV_MF8_MASK
@ PseudoVNSRA_WV_MF8_MASK
Definition riscv/opcodes.hpp:7577
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E32_V_M1
@ PseudoVSSEG3E32_V_M1
Definition riscv/opcodes.hpp:10035
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG8E32_V_MF2
@ PseudoVSSSEG8E32_V_MF2
Definition riscv/opcodes.hpp:10407
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF8_E8_MASK
@ PseudoVREM_VX_MF8_E8_MASK
Definition riscv/opcodes.hpp:8259
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR32_MF2
@ PseudoVFMV_S_FPR32_MF2
Definition riscv/opcodes.hpp:2397
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_M1
@ PseudoVLSEG7E32_V_M1
Definition riscv/opcodes.hpp:5334
LIEF::assembly::riscv::OPCODE::PseudoLongBEQ
@ PseudoLongBEQ
Definition riscv/opcodes.hpp:401
LIEF::assembly::riscv::OPCODE::FNMADD_H_INX
@ FNMADD_H_INX
Definition riscv/opcodes.hpp:12740
LIEF::assembly::riscv::OPCODE::PseudoVFMIN_VFPR32_M2_E32_MASK
@ PseudoVFMIN_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2147
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_MF4_E16
@ PseudoVWREDSUM_VS_MF4_E16
Definition riscv/opcodes.hpp:11677
LIEF::assembly::riscv::OPCODE::CV_CMPGTU_H
@ CV_CMPGTU_H
Definition riscv/opcodes.hpp:12230
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E32_MASK
@ PseudoVFREC7_V_M1_E32_MASK
Definition riscv/opcodes.hpp:2908
LIEF::assembly::riscv::OPCODE::FSQRT_D_INX
@ FSQRT_D_INX
Definition riscv/opcodes.hpp:12781
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG7E64_V_M1
@ PseudoVLSSEG7E64_V_M1
Definition riscv/opcodes.hpp:5540
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF2_MF2_MASK
@ PseudoVSUXSEG5EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11024
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_MF2_M1_MASK
@ PseudoVLUXSEG5EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:6115
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_MF8
@ PseudoVC_V_IV_MF8
Definition riscv/opcodes.hpp:1280
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_MF4_MASK
@ PseudoVLOXSEG2EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4409
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M2_E64_MASK
@ PseudoVDIV_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:1524
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_MF4_MF4
@ PseudoVSOXEI8_V_MF4_MF4
Definition riscv/opcodes.hpp:9145
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF4_E16
@ PseudoVFREDMAX_VS_MF4_E16
Definition riscv/opcodes.hpp:2963
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI8_V_MF8_MF4
@ PseudoVLUXSEG6EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:6238
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI8_V_MF8_MF2
@ PseudoVSOXSEG6EI8_V_MF8_MF2
Definition riscv/opcodes.hpp:9665
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M2_E16
@ PseudoVFMSAC_VFPR16_M2_E16
Definition riscv/opcodes.hpp:2194
LIEF::assembly::riscv::OPCODE::PseudoVSM3ME_VV_M1
@ PseudoVSM3ME_VV_M1
Definition riscv/opcodes.hpp:8925
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF4_MF4
@ PseudoVSOXSEG3EI16_V_MF4_MF4
Definition riscv/opcodes.hpp:9315
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M8
@ PseudoVNMSUB_VX_M8
Definition riscv/opcodes.hpp:7546
LIEF::assembly::riscv::OPCODE::VFADD_VF
@ VFADD_VF
Definition riscv/opcodes.hpp:13204
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR64_M1
@ PseudoVFSLIDE1UP_VFPR64_M1
Definition riscv/opcodes.hpp:3353
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E16FF_V_MF4
@ PseudoVLSEG6E16FF_V_MF4
Definition riscv/opcodes.hpp:5282
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M8_M2
@ PseudoVAESZ_VS_M8_M2
Definition riscv/opcodes.hpp:782
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M4_MF2_MASK
@ PseudoVSUXSEG8EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:11312
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M4_MASK
@ PseudoVASUB_VX_M4_MASK
Definition riscv/opcodes.hpp:907
LIEF::assembly::riscv::OPCODE::VFNRCLIP_XU_F_QF
@ VFNRCLIP_XU_F_QF
Definition riscv/opcodes.hpp:13251
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VI_M8
@ PseudoVSLIDEUP_VI_M8
Definition riscv/opcodes.hpp:8856
LIEF::assembly::riscv::OPCODE::PseudoVC_V_X_SE_M4
@ PseudoVC_V_X_SE_M4
Definition riscv/opcodes.hpp:1391
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_M1
@ PseudoVLSEG6E8FF_V_M1
Definition riscv/opcodes.hpp:5302
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M1_E64
@ PseudoVREDXOR_VS_M1_E64
Definition riscv/opcodes.hpp:8012
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_MF2_MF2
@ PseudoVLUXSEG3EI32_V_MF2_MF2
Definition riscv/opcodes.hpp:5912
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF4_MF2
@ PseudoVLUXSEG2EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:5850
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E32_MASK
@ PseudoVREDMAX_VS_M4_E32_MASK
Definition riscv/opcodes.hpp:7807
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WX_MF4
@ PseudoVNSRL_WX_MF4
Definition riscv/opcodes.hpp:7622
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_MF8_MASK
@ PseudoVSLIDEUP_VX_MF8_MASK
Definition riscv/opcodes.hpp:8877
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF4_E16_MASK
@ PseudoVFSGNJX_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3240
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI64_V_M1_MF8_MASK
@ PseudoVSOXSEG2EI64_V_M1_MF8_MASK
Definition riscv/opcodes.hpp:9232
LIEF::assembly::riscv::OPCODE::MOPR28
@ MOPR28
Definition riscv/opcodes.hpp:12881
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E64FF_V_M1_MASK
@ PseudoVLSEG4E64FF_V_M1_MASK
Definition riscv/opcodes.hpp:5211
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M2_E8
@ PseudoVREDMAXU_VS_M2_E8
Definition riscv/opcodes.hpp:7758
LIEF::assembly::riscv::OPCODE::AMOSWAP_B_AQ
@ AMOSWAP_B_AQ
Definition riscv/opcodes.hpp:12084
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M2_E32_MASK
@ PseudoVFWSUB_WV_M2_E32_MASK
Definition riscv/opcodes.hpp:4022
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_M8_E32_MASK
@ PseudoVFDIV_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:1914
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M1_MASK
@ PseudoVLOXSEG3EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:4483
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI64_V_M4_MF2_MASK
@ PseudoVLUXSEG2EI64_V_M4_MF2_MASK
Definition riscv/opcodes.hpp:5819
LIEF::assembly::riscv::OPCODE::PseudoVAESKF2_VI_M8
@ PseudoVAESKF2_VI_M8
Definition riscv/opcodes.hpp:764
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VV_M2_E32
@ PseudoVFWMACC_VV_M2_E32
Definition riscv/opcodes.hpp:3755
LIEF::assembly::riscv::OPCODE::VASUBU_VV
@ VASUBU_VV
Definition riscv/opcodes.hpp:13157
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI16_V_MF4_M1
@ PseudoVLUXSEG6EI16_V_MF4_M1
Definition riscv/opcodes.hpp:6174
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI16_V_MF4_MF2_MASK
@ PseudoVSUXSEG5EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:11030
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M1_M1
@ PseudoVSOXSEG2EI8_V_M1_M1
Definition riscv/opcodes.hpp:9255
LIEF::assembly::riscv::OPCODE::LD_AQ
@ LD_AQ
Definition riscv/opcodes.hpp:12837
LIEF::assembly::riscv::OPCODE::PseudoVSLL_VV_MF4_MASK
@ PseudoVSLL_VV_MF4_MASK
Definition riscv/opcodes.hpp:8903
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI64_V_M2_M1_MASK
@ PseudoVLUXSEG7EI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6291
LIEF::assembly::riscv::OPCODE::CV_CMPLTU_SC_H
@ CV_CMPLTU_SC_H
Definition riscv/opcodes.hpp:12258
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M4_M1_MASK
@ PseudoVLUXSEG4EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:6015
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M4_MASK
@ PseudoVSSUB_VV_M4_MASK
Definition riscv/opcodes.hpp:10452
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_M4_E32_MASK_TIED
@ PseudoVFWSUB_WV_M4_E32_MASK_TIED
Definition riscv/opcodes.hpp:4031
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_M1_MASK
@ PseudoVLUXEI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5651
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_M8
@ PseudoVMFEQ_VV_M8
Definition riscv/opcodes.hpp:6634
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M1_E32_MASK
@ PseudoVFSGNJX_VV_M1_E32_MASK
Definition riscv/opcodes.hpp:3214
LIEF::assembly::riscv::OPCODE::VLSSEG8E8_V
@ VLSSEG8E8_V
Definition riscv/opcodes.hpp:13451
LIEF::assembly::riscv::OPCODE::PseudoVFNRCLIP_XU_F_QF_MF2_MASK
@ PseudoVFNRCLIP_XU_F_QF_MF2_MASK
Definition riscv/opcodes.hpp:2860
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF2
@ PseudoVFNCVT_X_F_W_MF2
Definition riscv/opcodes.hpp:2609
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF4_E16_MASK
@ PseudoVFWNMACC_VV_MF4_E16_MASK
Definition riscv/opcodes.hpp:3874
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M2_E16
@ PseudoVFSUB_VV_M2_E16
Definition riscv/opcodes.hpp:3427
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E16_MASK
@ PseudoVFCVT_F_XU_V_M1_E16_MASK
Definition riscv/opcodes.hpp:1672
LIEF::assembly::riscv::OPCODE::TH_DCACHE_CVA
@ TH_DCACHE_CVA
Definition riscv/opcodes.hpp:13036
LIEF::assembly::riscv::OPCODE::MOPR3
@ MOPR3
Definition riscv/opcodes.hpp:12883
LIEF::assembly::riscv::OPCODE::PseudoVMANDN_MM_MF2
@ PseudoVMANDN_MM_MF2
Definition riscv/opcodes.hpp:6504
LIEF::assembly::riscv::OPCODE::LR_D
@ LR_D
Definition riscv/opcodes.hpp:12843
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M1
@ PseudoVSSRL_VV_M1
Definition riscv/opcodes.hpp:10219
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VIM_M4
@ PseudoVMADC_VIM_M4
Definition riscv/opcodes.hpp:6432
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR64_M2_E64
@ PseudoVFMSUB_VFPR64_M2_E64
Definition riscv/opcodes.hpp:2276
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF4_M1
@ PseudoVLOXEI8_V_MF4_M1
Definition riscv/opcodes.hpp:4318
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_M8_MASK
@ PseudoVFCVT_RM_X_F_V_M8_MASK
Definition riscv/opcodes.hpp:1810
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M8_MASK
@ PseudoVSOXEI32_V_M4_M8_MASK
Definition riscv/opcodes.hpp:9064
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_MF4_E8_MASK
@ PseudoVREDSUM_VS_MF4_E8_MASK
Definition riscv/opcodes.hpp:8005
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_M1_M1_MASK
@ PseudoVSUXSEG6EI32_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11116
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M8_E32
@ PseudoVREMU_VX_M8_E32
Definition riscv/opcodes.hpp:8154
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_M1_MASK
@ PseudoVLUXEI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5571
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_M2_E32
@ PseudoVFWCVT_F_X_V_M2_E32
Definition riscv/opcodes.hpp:3615
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M1_MASK
@ PseudoVMSLTU_VV_M1_MASK
Definition riscv/opcodes.hpp:7165
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_MF2
@ PseudoVMERGE_VVM_MF2
Definition riscv/opcodes.hpp:6588
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF4_M8_MASK
@ PseudoVSEXT_VF4_M8_MASK
Definition riscv/opcodes.hpp:8768
LIEF::assembly::riscv::OPCODE::VLSSEG2E64_V
@ VLSSEG2E64_V
Definition riscv/opcodes.hpp:13426
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M1_MASK
@ PseudoVLUXSEG2EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:5771
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VV_M1
@ PseudoVNMSUB_VV_M1
Definition riscv/opcodes.hpp:7526
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_M2
@ PseudoVMACC_VX_M2
Definition riscv/opcodes.hpp:6418
LIEF::assembly::riscv::OPCODE::VCLMULH_VV
@ VCLMULH_VV
Definition riscv/opcodes.hpp:13163
LIEF::assembly::riscv::OPCODE::PseudoVGHSH_VV_M4
@ PseudoVGHSH_VV_M4
Definition riscv/opcodes.hpp:4047
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF8_MASK
@ PseudoVLUXEI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:5611
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VV_M2
@ PseudoVMSNE_VV_M2
Definition riscv/opcodes.hpp:7237
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_NAND
@ G_ATOMICRMW_NAND
Definition riscv/opcodes.hpp:127
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG5EI16_V_M2_M1_MASK
@ PseudoVSOXSEG5EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9516
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF8
@ PseudoVSADD_VX_MF8
Definition riscv/opcodes.hpp:8686
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M8_E32
@ PseudoVFMSUB_VV_M8_E32
Definition riscv/opcodes.hpp:2302
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M8_E64
@ PseudoVFSGNJX_VFPR64_M8_E64
Definition riscv/opcodes.hpp:3209
LIEF::assembly::riscv::OPCODE::PseudoCCOR
@ PseudoCCOR
Definition riscv/opcodes.hpp:349
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_MF4
@ PseudoVLSSEG2E8_V_MF4
Definition riscv/opcodes.hpp:5430
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M1_E8_MASK
@ PseudoVREMU_VV_M1_E8_MASK
Definition riscv/opcodes.hpp:8091
LIEF::assembly::riscv::OPCODE::PseudoVSEXT_VF8_M8
@ PseudoVSEXT_VF8_M8
Definition riscv/opcodes.hpp:8777
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_M8_E64_MASK
@ PseudoVREDXOR_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:8037
LIEF::assembly::riscv::OPCODE::VMV_V_I
@ VMV_V_I
Definition riscv/opcodes.hpp:13561
LIEF::assembly::riscv::OPCODE::PseudoVSSRL_VV_M2_MASK
@ PseudoVSSRL_VV_M2_MASK
Definition riscv/opcodes.hpp:10222
LIEF::assembly::riscv::OPCODE::C_AND
@ C_AND
Definition riscv/opcodes.hpp:12484
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M4_M1
@ PseudoVSUXEI64_V_M4_M1
Definition riscv/opcodes.hpp:10599
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E64_MASK
@ PseudoVDIVU_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:1444
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VFPR16_M1_E16_MASK
@ PseudoVFNMADD_VFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:2676
LIEF::assembly::riscv::OPCODE::PseudoVMADC_VV_M1
@ PseudoVMADC_VV_M1
Definition riscv/opcodes.hpp:6451
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M1_MASK
@ PseudoVFWCVT_X_F_V_M1_MASK
Definition riscv/opcodes.hpp:3688
LIEF::assembly::riscv::OPCODE::PseudoVLSE8_V_M2_MASK
@ PseudoVLSE8_V_M2_MASK
Definition riscv/opcodes.hpp:5043
LIEF::assembly::riscv::OPCODE::PseudoVWMACC_VV_M1
@ PseudoVWMACC_VV_M1
Definition riscv/opcodes.hpp:11515
LIEF::assembly::riscv::OPCODE::VLSEG7E16_V
@ VLSEG7E16_V
Definition riscv/opcodes.hpp:13409
LIEF::assembly::riscv::OPCODE::G_CONSTANT_FOLD_BARRIER
@ G_CONSTANT_FOLD_BARRIER
Definition riscv/opcodes.hpp:104
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E32
@ PseudoVFCVT_F_XU_V_M1_E32
Definition riscv/opcodes.hpp:1673
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_MF8
@ PseudoVLUXEI16_V_MF4_MF8
Definition riscv/opcodes.hpp:5610
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VV_M1_E32
@ PseudoVFWNMSAC_VV_M1_E32
Definition riscv/opcodes.hpp:3895
LIEF::assembly::riscv::OPCODE::PseudoAtomicLoadNand64
@ PseudoAtomicLoadNand64
Definition riscv/opcodes.hpp:331
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_M1_E16
@ PseudoVFWMUL_VFPR16_M1_E16
Definition riscv/opcodes.hpp:3803
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VI_MF2_MASK
@ PseudoVMSLE_VI_MF2_MASK
Definition riscv/opcodes.hpp:7130
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI32_V_MF2_M1_MASK
@ PseudoVSUXSEG7EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:11208
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M4_E64
@ PseudoVDIVU_VV_M4_E64
Definition riscv/opcodes.hpp:1443
LIEF::assembly::riscv::OPCODE::PseudoVASUBU_VX_MF8_MASK
@ PseudoVASUBU_VX_MF8_MASK
Definition riscv/opcodes.hpp:887
LIEF::assembly::riscv::OPCODE::C_SDSP
@ C_SDSP
Definition riscv/opcodes.hpp:12529
LIEF::assembly::riscv::OPCODE::PseudoVFWNMACC_VV_MF2_E32_MASK
@ PseudoVFWNMACC_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3872
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E16
@ PseudoVFNMSUB_VV_M8_E16
Definition riscv/opcodes.hpp:2843
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_MF8
@ PseudoVMERGE_VVM_MF8
Definition riscv/opcodes.hpp:6590
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_M1_MASK
@ PseudoVRGATHEREI16_VV_M2_E16_M1_MASK
Definition riscv/opcodes.hpp:8307
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_M1_MASK
@ PseudoVLUXSEG8EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:6349
LIEF::assembly::riscv::OPCODE::AMOXOR_B_AQ_RL
@ AMOXOR_B_AQ_RL
Definition riscv/opcodes.hpp:12101
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M4_E32
@ PseudoVREDMAX_VS_M4_E32
Definition riscv/opcodes.hpp:7806
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E16FF_V_M1
@ PseudoVLSEG4E16FF_V_M1
Definition riscv/opcodes.hpp:5182
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_M4_MASK
@ PseudoVMSGT_VX_M4_MASK
Definition riscv/opcodes.hpp:7056
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI32_V_M4_M1_MASK
@ PseudoVSUXSEG4EI32_V_M4_M1_MASK
Definition riscv/opcodes.hpp:10948
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M1
@ PseudoVMULH_VV_M1
Definition riscv/opcodes.hpp:7333
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF4_MF8_MASK
@ PseudoVSOXSEG2EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:9190
LIEF::assembly::riscv::OPCODE::PseudoVMAXU_VV_M8_MASK
@ PseudoVMAXU_VV_M8_MASK
Definition riscv/opcodes.hpp:6521
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR16_M2_E16_MASK
@ PseudoVFDIV_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:1866
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF2_E32_MASK
@ PseudoVREMU_VX_MF2_E32_MASK
Definition riscv/opcodes.hpp:8163
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VS_M8_MF8
@ PseudoVAESEM_VS_M8_MF8
Definition riscv/opcodes.hpp:747
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF4_MASK
@ PseudoVLSEG6E8FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5307
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI32_V_M2_M1
@ PseudoVSOXSEG3EI32_V_M2_M1
Definition riscv/opcodes.hpp:9327
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI8_V_MF4_M1
@ PseudoVLUXSEG8EI8_V_MF4_M1
Definition riscv/opcodes.hpp:6388
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_XU_F_W_MF8_MASK
@ PseudoVFNCVT_XU_F_W_MF8_MASK
Definition riscv/opcodes.hpp:2602
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VV_M4_E32
@ PseudoVREMU_VV_M4_E32
Definition riscv/opcodes.hpp:8102
LIEF::assembly::riscv::OPCODE::PseudoVFNMACC_VV_M4_E16
@ PseudoVFNMACC_VV_M4_E16
Definition riscv/opcodes.hpp:2657
LIEF::assembly::riscv::OPCODE::TH_LHUIA
@ TH_LHUIA
Definition riscv/opcodes.hpp:13070
LIEF::assembly::riscv::OPCODE::VMERGE_VXM
@ VMERGE_VXM
Definition riscv/opcodes.hpp:13502
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M4_MASK
@ PseudoVROL_VV_M4_MASK
Definition riscv/opcodes.hpp:8511
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M1_M1
@ PseudoVLOXSEG7EI16_V_M1_M1
Definition riscv/opcodes.hpp:4850
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD4_MF2
@ PseudoVRELOAD4_MF2
Definition riscv/opcodes.hpp:8065
LIEF::assembly::riscv::OPCODE::CV_MULSN
@ CV_MULSN
Definition riscv/opcodes.hpp:12375
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E8
@ PseudoVWREDSUM_VS_M4_E8
Definition riscv/opcodes.hpp:11663
LIEF::assembly::riscv::OPCODE::G_FPTRUNC
@ G_FPTRUNC
Definition riscv/opcodes.hpp:215
LIEF::assembly::riscv::OPCODE::FSGNJN_D
@ FSGNJN_D
Definition riscv/opcodes.hpp:12757
LIEF::assembly::riscv::OPCODE::VLSEG7E16FF_V
@ VLSEG7E16FF_V
Definition riscv/opcodes.hpp:13408
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VV_M8_E64_MASK
@ PseudoVFMADD_VV_M8_E64_MASK
Definition riscv/opcodes.hpp:2050
LIEF::assembly::riscv::OPCODE::PseudoVFSQRT_V_M8_E64
@ PseudoVFSQRT_V_M8_E64
Definition riscv/opcodes.hpp:3383
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK
@ PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK
Definition riscv/opcodes.hpp:2506
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI32_V_M4_M1
@ PseudoVLUXSEG5EI32_V_M4_M1
Definition riscv/opcodes.hpp:6112
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M1_MF2
@ PseudoVLUXEI16_V_M1_MF2
Definition riscv/opcodes.hpp:5576
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI8_V_MF8_MF4
@ PseudoVSOXSEG4EI8_V_MF8_MF4
Definition riscv/opcodes.hpp:9507
LIEF::assembly::riscv::OPCODE::QK_C_SH
@ QK_C_SH
Definition riscv/opcodes.hpp:12922
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M1_MASK
@ PseudoVLE8FF_V_M1_MASK
Definition riscv/opcodes.hpp:4144
LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M8
@ PseudoVSE32_V_M8
Definition riscv/opcodes.hpp:8720
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M2_E32_MASK
@ PseudoVFWMACC_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3744
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG8E8_V_MF4
@ PseudoVLSSEG8E8_V_MF4
Definition riscv/opcodes.hpp:5566
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_MF2_M1
@ PseudoVLOXSEG8EI16_V_MF2_M1
Definition riscv/opcodes.hpp:4936
LIEF::assembly::riscv::OPCODE::PseudoVZEXT_VF2_M2_MASK
@ PseudoVZEXT_VF2_M2_MASK
Definition riscv/opcodes.hpp:11884
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VI_MF4
@ PseudoVRGATHER_VI_MF4
Definition riscv/opcodes.hpp:8444
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M8
@ PseudoVMFNE_VFPR32_M8
Definition riscv/opcodes.hpp:6802
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_MF2_M1_MASK
@ PseudoVSUXSEG3EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:10808
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR16_M2_E16_MASK
@ PseudoVFMADD_VFPR16_M2_E16_MASK
Definition riscv/opcodes.hpp:2000
LIEF::assembly::riscv::OPCODE::VSSSEG3E32_V
@ VSSSEG3E32_V
Definition riscv/opcodes.hpp:13741
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_XU_F_V_M1
@ PseudoVFCVT_XU_F_V_M1
Definition riscv/opcodes.hpp:1839
LIEF::assembly::riscv::OPCODE::VFNCVT_F_X_W
@ VFNCVT_F_X_W
Definition riscv/opcodes.hpp:13237
LIEF::assembly::riscv::OPCODE::VL4RE16_V
@ VL4RE16_V
Definition riscv/opcodes.hpp:13315
LIEF::assembly::riscv::OPCODE::PseudoVFREC7_V_M1_E16
@ PseudoVFREC7_V_M1_E16
Definition riscv/opcodes.hpp:2905
LIEF::assembly::riscv::OPCODE::PseudoVNMSUB_VX_M4
@ PseudoVNMSUB_VX_M4
Definition riscv/opcodes.hpp:7544
LIEF::assembly::riscv::OPCODE::C_SEXT_H
@ C_SEXT_H
Definition riscv/opcodes.hpp:12531
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_MF4_MASK
@ PseudoVSSUBU_VX_MF4_MASK
Definition riscv/opcodes.hpp:10444
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M4_E16_MASK
@ PseudoVFCVT_F_X_V_M4_E16_MASK
Definition riscv/opcodes.hpp:1714
LIEF::assembly::riscv::OPCODE::WRS_NTO
@ WRS_NTO
Definition riscv/opcodes.hpp:13845
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF2_MF2_MASK
@ PseudoVSUXSEG6EI8_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11160
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_XU_V_MF2_E16_MASK
@ PseudoVFWCVT_F_XU_V_MF2_E16_MASK
Definition riscv/opcodes.hpp:3596
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_M1_MASK
@ PseudoVSSSEG5E16_V_M1_MASK
Definition riscv/opcodes.hpp:10340
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E64_MASK
@ PseudoVREDMAXU_VS_M4_E64_MASK
Definition riscv/opcodes.hpp:7765
LIEF::assembly::riscv::OPCODE::LWU
@ LWU
Definition riscv/opcodes.hpp:12853
LIEF::assembly::riscv::OPCODE::FDIV_D_INX
@ FDIV_D_INX
Definition riscv/opcodes.hpp:12645
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M1_M2_MASK
@ PseudoVLUXEI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:5685
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR32_M2_E32_MASK
@ PseudoVFWADD_WFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:3500
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E32_MASK
@ PseudoVREMU_VX_M4_E32_MASK
Definition riscv/opcodes.hpp:8147
LIEF::assembly::riscv::OPCODE::PseudoVROR_VX_M4_MASK
@ PseudoVROR_VX_M4_MASK
Definition riscv/opcodes.hpp:8567
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_M1_MF2_MASK
@ PseudoVSOXEI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:9006
LIEF::assembly::riscv::OPCODE::FCVT_H_S
@ FCVT_H_S
Definition riscv/opcodes.hpp:12597
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M1_MASK
@ PseudoVLUXSEG3EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:5863
LIEF::assembly::riscv::OPCODE::REM
@ REM
Definition riscv/opcodes.hpp:12924
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI64_V_M8_M1_MASK
@ PseudoVLUXSEG3EI64_V_M8_M1_MASK
Definition riscv/opcodes.hpp:5941
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF4_E16_MASK
@ PseudoVFMACC_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:1948
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M8_E64
@ PseudoVFSGNJN_VV_M8_E64
Definition riscv/opcodes.hpp:3173
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VFPR32_M4
@ PseudoVMFEQ_VFPR32_M4
Definition riscv/opcodes.hpp:6614
LIEF::assembly::riscv::OPCODE::PseudoVC_IV_SE_M4
@ PseudoVC_IV_SE_M4
Definition riscv/opcodes.hpp:1134
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M1_E64_MASK
@ PseudoVFCVT_RM_F_XU_V_M1_E64_MASK
Definition riscv/opcodes.hpp:1736
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VI_M8_MASK
@ PseudoVXOR_VI_M8_MASK
Definition riscv/opcodes.hpp:11846
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_M2_MASK
@ PseudoVXOR_VV_M2_MASK
Definition riscv/opcodes.hpp:11856
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_X_F_V_MF4
@ PseudoVFCVT_RM_X_F_V_MF4
Definition riscv/opcodes.hpp:1813
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_M1_MASK
@ PseudoVSUXSEG6EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11096
LIEF::assembly::riscv::OPCODE::G_VASTART
@ G_VASTART
Definition riscv/opcodes.hpp:153
LIEF::assembly::riscv::OPCODE::CV_CPLXMUL_I_DIV8
@ CV_CPLXMUL_I_DIV8
Definition riscv/opcodes.hpp:12276
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M4_E64_MASK
@ PseudoVREMU_VX_M4_E64_MASK
Definition riscv/opcodes.hpp:8149
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_X_V_M8_E16
@ PseudoVFCVT_RM_F_X_V_M8_E16
Definition riscv/opcodes.hpp:1779
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M1_E64_MASK
@ PseudoVREDMIN_VS_M1_E64_MASK
Definition riscv/opcodes.hpp:7881
LIEF::assembly::riscv::OPCODE::PseudoVSM3C_VI_M8
@ PseudoVSM3C_VI_M8
Definition riscv/opcodes.hpp:8923
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF4_E16_TIED
@ PseudoVFWADD_WV_MF4_E16_TIED
Definition riscv/opcodes.hpp:3540
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VX_M8_MASK
@ PseudoVMSLEU_VX_M8_MASK
Definition riscv/opcodes.hpp:7114
LIEF::assembly::riscv::OPCODE::PseudoVMSGTU_VI_MF4
@ PseudoVMSGTU_VI_MF4
Definition riscv/opcodes.hpp:7019
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF2_M1_MASK
@ PseudoVSOXSEG6EI16_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9598
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E32_MASK
@ PseudoVFNMADD_VV_M2_E32_MASK
Definition riscv/opcodes.hpp:2714
LIEF::assembly::riscv::OPCODE::PseudoVWMACCSU_VX_M2
@ PseudoVWMACCSU_VX_M2
Definition riscv/opcodes.hpp:11469
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI32_V_MF2_MF8
@ PseudoVSOXSEG8EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:9789
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK
@ PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK
Definition riscv/opcodes.hpp:2498
LIEF::assembly::riscv::OPCODE::PseudoVNSRA_WI_MF4_MASK
@ PseudoVNSRA_WI_MF4_MASK
Definition riscv/opcodes.hpp:7563
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK
@ PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK
Definition riscv/opcodes.hpp:8313
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VV_M4_E64
@ PseudoVFSUB_VV_M4_E64
Definition riscv/opcodes.hpp:3437
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_M1_MASK
@ PseudoVSUXSEG6EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:11162
LIEF::assembly::riscv::OPCODE::PseudoVSSEG7E32_V_MF2_MASK
@ PseudoVSSEG7E32_V_MF2_MASK
Definition riscv/opcodes.hpp:10132
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF4_MASK
@ PseudoVAND_VX_MF4_MASK
Definition riscv/opcodes.hpp:857
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VX_M2
@ PseudoVWSLL_VX_M2
Definition riscv/opcodes.hpp:11709
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E8_M1_MASK
@ PseudoVRGATHEREI16_VV_M2_E8_M1_MASK
Definition riscv/opcodes.hpp:8331
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_M4_MASK
@ PseudoVLSEG2E16FF_V_M4_MASK
Definition riscv/opcodes.hpp:5059
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_XU_F_W_MF4_MASK
@ PseudoVFNCVT_RM_XU_F_W_MF4_MASK
Definition riscv/opcodes.hpp:2534
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF4_MF2_MASK
@ PseudoVLUXSEG7EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:6257
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_UDEC_WRAP
@ G_ATOMICRMW_UDEC_WRAP
Definition riscv/opcodes.hpp:139
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR16_M2_MASK
@ PseudoVMFNE_VFPR16_M2_MASK
Definition riscv/opcodes.hpp:6787
LIEF::assembly::riscv::OPCODE::VMOR_MM
@ VMOR_MM
Definition riscv/opcodes.hpp:13520
LIEF::assembly::riscv::OPCODE::PseudoVLSE16_V_M8_MASK
@ PseudoVLSE16_V_M8_MASK
Definition riscv/opcodes.hpp:5017
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF2_MF4_MASK
@ PseudoVLOXSEG7EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:4861
LIEF::assembly::riscv::OPCODE::VBREV_V
@ VBREV_V
Definition riscv/opcodes.hpp:13162
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M8_M2_MASK
@ PseudoVLUXSEG3EI32_V_M8_M2_MASK
Definition riscv/opcodes.hpp:5909
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_M2_M4_MASK
@ PseudoVLUXSEG2EI8_V_M2_M4_MASK
Definition riscv/opcodes.hpp:5835
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI32_V_M1_MF4_MASK
@ PseudoVLUXSEG7EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:6267
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M8
@ PseudoVMFGT_VFPR64_M8
Definition riscv/opcodes.hpp:6698
LIEF::assembly::riscv::OPCODE::C_SLLI64_HINT
@ C_SLLI64_HINT
Definition riscv/opcodes.hpp:12534
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M4_M2
@ PseudoVLUXSEG4EI16_V_M4_M2
Definition riscv/opcodes.hpp:5982
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E16_MASK
@ PseudoVFSGNJX_VV_M2_E16_MASK
Definition riscv/opcodes.hpp:3218
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B16
@ PseudoVFIRST_M_B16
Definition riscv/opcodes.hpp:1924
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUMU_VS_M8_E16_MASK
@ PseudoVWREDSUMU_VS_M8_E16_MASK
Definition riscv/opcodes.hpp:11630
LIEF::assembly::riscv::OPCODE::PseudoVCLMUL_VV_MF2_MASK
@ PseudoVCLMUL_VV_MF2_MASK
Definition riscv/opcodes.hpp:981
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E16
@ PseudoVREDMINU_VS_M1_E16
Definition riscv/opcodes.hpp:7832
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VX_M1
@ PseudoVMSLT_VX_M1
Definition riscv/opcodes.hpp:7207
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E32
@ PseudoVFNMSUB_VV_M4_E32
Definition riscv/opcodes.hpp:2839
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR64_M1_E64_MASK
@ PseudoVFMUL_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2335
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M4_E32_MASK
@ PseudoVFNMSUB_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:2840
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M4_MASK
@ PseudoVLOXEI64_V_M8_M4_MASK
Definition riscv/opcodes.hpp:4287
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VI_MF4
@ PseudoVSADD_VI_MF4
Definition riscv/opcodes.hpp:8656
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1DOWN_VFPR32_M4
@ PseudoVFSLIDE1DOWN_VFPR32_M4
Definition riscv/opcodes.hpp:3317
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VV_MF4
@ PseudoVSMUL_VV_MF4
Definition riscv/opcodes.hpp:8974
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF4_M1_MASK
@ PseudoVSOXSEG8EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:9764
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M4_E64_M4
@ PseudoVRGATHEREI16_VV_M4_E64_M4
Definition riscv/opcodes.hpp:8358
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VV_MF4_E16
@ PseudoVFWADD_VV_MF4_E16
Definition riscv/opcodes.hpp:3485
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VV_MF4
@ PseudoVMSLE_VV_MF4
Definition riscv/opcodes.hpp:7145
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VV_M2
@ PseudoVMUL_VV_M2
Definition riscv/opcodes.hpp:7363
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_VFPR16_M4_E16_MASK
@ PseudoVFWADD_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:3456
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M1_M1
@ PseudoVSOXSEG3EI16_V_M1_M1
Definition riscv/opcodes.hpp:9291
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF4_MASK
@ PseudoVMULHU_VX_MF4_MASK
Definition riscv/opcodes.hpp:7330
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEDOWN_VI_M1
@ PseudoVSLIDEDOWN_VI_M1
Definition riscv/opcodes.hpp:8822
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M4_E32
@ PseudoVFWREDOSUM_VS_M4_E32
Definition riscv/opcodes.hpp:3921
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_X_V_M2_E16
@ PseudoVFCVT_F_X_V_M2_E16
Definition riscv/opcodes.hpp:1707
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E8_V_MF8
@ PseudoVLSEG5E8_V_MF8
Definition riscv/opcodes.hpp:5276
LIEF::assembly::riscv::OPCODE::PseudoVRGATHER_VV_MF4_E16
@ PseudoVRGATHER_VV_MF4_E16
Definition riscv/opcodes.hpp:8486
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VX_M4_MASK
@ PseudoVCLMULH_VX_M4_MASK
Definition riscv/opcodes.hpp:963
LIEF::assembly::riscv::OPCODE::VFREDUSUM_VS
@ VFREDUSUM_VS
Definition riscv/opcodes.hpp:13258
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_MF8
@ PseudoVSSEG3E8_V_MF8
Definition riscv/opcodes.hpp:10053
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF2
@ PseudoVSUXSEG8EI64_V_M2_MF2
Definition riscv/opcodes.hpp:11305
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_MF4_MF2_MASK
@ PseudoVLOXSEG7EI16_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4865
LIEF::assembly::riscv::OPCODE::G_AND
@ G_AND
Definition riscv/opcodes.hpp:84
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_MF4_MASK
@ PseudoVSUXSEG7EI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:11220
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M1_E16_MASK
@ PseudoVREM_VV_M1_E16_MASK
Definition riscv/opcodes.hpp:8173
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_M1_MASK
@ PseudoVLUXSEG5EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:6083
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_M2_M2_MASK
@ PseudoVLUXSEG2EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5737
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E8
@ PseudoVREM_VX_MF2_E8
Definition riscv/opcodes.hpp:8252
LIEF::assembly::riscv::OPCODE::PseudoVGMUL_VV_M4
@ PseudoVGMUL_VV_M4
Definition riscv/opcodes.hpp:4052
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_MF4
@ PseudoVSOXSEG2EI32_V_MF2_MF4
Definition riscv/opcodes.hpp:9221
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_MF8
@ PseudoVWSUB_VV_MF8
Definition riscv/opcodes.hpp:11789
LIEF::assembly::riscv::OPCODE::BCLRI
@ BCLRI
Definition riscv/opcodes.hpp:12120
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI16_V_M2_M1
@ PseudoVSUXEI16_V_M2_M1
Definition riscv/opcodes.hpp:10511
LIEF::assembly::riscv::OPCODE::PseudoVLE64_V_M2_MASK
@ PseudoVLE64_V_M2_MASK
Definition riscv/opcodes.hpp:4138
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_M2_MASK
@ PseudoVFWCVT_X_F_V_M2_MASK
Definition riscv/opcodes.hpp:3690
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M2_E16_MASK
@ PseudoVREM_VX_M2_E16_MASK
Definition riscv/opcodes.hpp:8225
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_MF4_E16
@ PseudoVFSGNJX_VV_MF4_E16
Definition riscv/opcodes.hpp:3239
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M4_E16
@ PseudoVDIV_VV_M4_E16
Definition riscv/opcodes.hpp:1527
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VV_M4_E32_MASK
@ PseudoVFMACC_VV_M4_E32_MASK
Definition riscv/opcodes.hpp:1982
LIEF::assembly::riscv::OPCODE::PseudoVSADD_VX_MF4
@ PseudoVSADD_VX_MF4
Definition riscv/opcodes.hpp:8684
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M8_E16
@ PseudoVCOMPRESS_VM_M8_E16
Definition riscv/opcodes.hpp:1026
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M4_M1_MASK
@ PseudoVLOXSEG2EI64_V_M4_M1_MASK
Definition riscv/opcodes.hpp:4421
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF2_M1
@ PseudoVSOXSEG8EI8_V_MF2_M1
Definition riscv/opcodes.hpp:9813
LIEF::assembly::riscv::OPCODE::QK_C_LBUSP
@ QK_C_LBUSP
Definition riscv/opcodes.hpp:12917
LIEF::assembly::riscv::OPCODE::PseudoVMFNE_VFPR32_M1_MASK
@ PseudoVMFNE_VFPR32_M1_MASK
Definition riscv/opcodes.hpp:6797
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI8_V_MF4_MF2
@ PseudoVSOXSEG8EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:9819
LIEF::assembly::riscv::OPCODE::TH_SYNC_IS
@ TH_SYNC_IS
Definition riscv/opcodes.hpp:13125
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M1_E16_MASK
@ PseudoVFREDUSUM_VS_M1_E16_MASK
Definition riscv/opcodes.hpp:3026
LIEF::assembly::riscv::OPCODE::PseudoVMINU_VV_MF4
@ PseudoVMINU_VV_MF4
Definition riscv/opcodes.hpp:6836
LIEF::assembly::riscv::OPCODE::PseudoVLSEG3E8FF_V_MF8
@ PseudoVLSEG3E8FF_V_MF8
Definition riscv/opcodes.hpp:5170
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF2_MASK
@ PseudoVSSSEG3E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10306
LIEF::assembly::riscv::OPCODE::G_RESET_FPENV
@ G_RESET_FPENV
Definition riscv/opcodes.hpp:232
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI32_V_M2_MF2_MASK
@ PseudoVLOXSEG8EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4959
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VV_MF2_E32_MASK
@ PseudoVFWMACCBF16_VV_MF2_E32_MASK
Definition riscv/opcodes.hpp:3722
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E32_V_M1_MASK
@ PseudoVLSSEG4E32_V_M1_MASK
Definition riscv/opcodes.hpp:5471
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M2_E64_MASK
@ PseudoVFNMSAC_VFPR64_M2_E64_MASK
Definition riscv/opcodes.hpp:2760
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M4_E16_MASK
@ PseudoVFMSUB_VFPR16_M4_E16_MASK
Definition riscv/opcodes.hpp:2257
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VV_M4_E64
@ PseudoVFMSUB_VV_M4_E64
Definition riscv/opcodes.hpp:2298
LIEF::assembly::riscv::OPCODE::PseudoVIOTA_M_M1_MASK
@ PseudoVIOTA_M_M1_MASK
Definition riscv/opcodes.hpp:4070
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M2_M4
@ PseudoVSOXSEG2EI8_V_M2_M4
Definition riscv/opcodes.hpp:9263
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_MF8_MASK
@ PseudoVMSLTU_VV_MF8_MASK
Definition riscv/opcodes.hpp:7177
LIEF::assembly::riscv::OPCODE::G_ADD
@ G_ADD
Definition riscv/opcodes.hpp:75
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_SE_M1
@ PseudoVC_V_I_SE_M1
Definition riscv/opcodes.hpp:1295
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF2_M2_MASK
@ PseudoVLUXSEG2EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:5749
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF2_MF4
@ PseudoVSOXEI16_V_MF2_MF4
Definition riscv/opcodes.hpp:9031
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI8_V_M1_M1_MASK
@ PseudoVLOXSEG4EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:4663
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF4_MF4_MASK
@ PseudoVLOXSEG3EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4495
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI64_V_M1_MF2_MASK
@ PseudoVSUXEI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10586
LIEF::assembly::riscv::OPCODE::PseudoVMSIF_M_B4
@ PseudoVMSIF_M_B4
Definition riscv/opcodes.hpp:7073
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_MF4
@ PseudoVASUB_VX_MF4
Definition riscv/opcodes.hpp:912
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI8_V_MF4_MF4
@ PseudoVSUXSEG6EI8_V_MF4_MF4
Definition riscv/opcodes.hpp:11165
LIEF::assembly::riscv::OPCODE::PseudoVMIN_VV_MF4
@ PseudoVMIN_VV_MF4
Definition riscv/opcodes.hpp:6864
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_MF2
@ PseudoVMERGE_VIM_MF2
Definition riscv/opcodes.hpp:6581
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VV_M8
@ PseudoVAESDF_VV_M8
Definition riscv/opcodes.hpp:667
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF2_MASK
@ PseudoVLUXEI64_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:5653
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VV_M1
@ PseudoVMACC_VV_M1
Definition riscv/opcodes.hpp:6402
LIEF::assembly::riscv::OPCODE::G_FMAXNUM_IEEE
@ G_FMAXNUM_IEEE
Definition riscv/opcodes.hpp:227
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M2
@ PseudoVMFGT_VFPR64_M2
Definition riscv/opcodes.hpp:6694
LIEF::assembly::riscv::OPCODE::FSGNJ_D_INX
@ FSGNJ_D_INX
Definition riscv/opcodes.hpp:12773
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E8_V_M4
@ PseudoVLSSEG2E8_V_M4
Definition riscv/opcodes.hpp:5426
LIEF::assembly::riscv::OPCODE::PseudoVSSUB_VV_M8
@ PseudoVSSUB_VV_M8
Definition riscv/opcodes.hpp:10453
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_MF2_MF8
@ PseudoVSUXSEG3EI32_V_MF2_MF8
Definition riscv/opcodes.hpp:10849
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M8_E32_MASK
@ PseudoVREM_VX_M8_E32_MASK
Definition riscv/opcodes.hpp:8243
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M8_M4
@ PseudoVSUXSEG2EI64_V_M8_M4
Definition riscv/opcodes.hpp:10757
LIEF::assembly::riscv::OPCODE::G_SUB
@ G_SUB
Definition riscv/opcodes.hpp:76
LIEF::assembly::riscv::OPCODE::PseudoVC_VVW_SE_MF4
@ PseudoVC_VVW_SE_MF4
Definition riscv/opcodes.hpp:1157
LIEF::assembly::riscv::OPCODE::G_FACOS
@ G_FACOS
Definition riscv/opcodes.hpp:266
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VFPR32_MF2_E32
@ PseudoVFDIV_VFPR32_MF2_E32
Definition riscv/opcodes.hpp:1883
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_MF8
@ PseudoVWADDU_WX_MF8
Definition riscv/opcodes.hpp:11393
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_M1_MASK
@ PseudoVSUXSEG8EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:11328
LIEF::assembly::riscv::OPCODE::PseudoVMSOF_M_B32
@ PseudoVMSOF_M_B32
Definition riscv/opcodes.hpp:7269
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK
@ PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK
Definition riscv/opcodes.hpp:2520
LIEF::assembly::riscv::OPCODE::PseudoVFREDOSUM_VS_M8_E32
@ PseudoVFREDOSUM_VS_M8_E32
Definition riscv/opcodes.hpp:3015
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_MF8_MASK
@ PseudoVMULHU_VX_MF8_MASK
Definition riscv/opcodes.hpp:7332
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M1_MASK
@ PseudoVSSSEG2E16_V_M1_MASK
Definition riscv/opcodes.hpp:10248
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_MF4_E16
@ PseudoVREMU_VX_MF4_E16
Definition riscv/opcodes.hpp:8166
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI32_V_MF2_MF2_MASK
@ PseudoVSUXSEG2EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:10724
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_MF2_E8_MASK
@ PseudoVREDMINU_VS_MF2_E8_MASK
Definition riscv/opcodes.hpp:7869
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_M1_MF4_MASK
@ PseudoVLUXSEG6EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:6187
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VV_M4_E16
@ PseudoVFMAX_VV_M4_E16
Definition riscv/opcodes.hpp:2099
LIEF::assembly::riscv::OPCODE::VSSSEG5E16_V
@ VSSSEG5E16_V
Definition riscv/opcodes.hpp:13748
LIEF::assembly::riscv::OPCODE::PseudoVFADD_VV_MF2_E16_MASK
@ PseudoVFADD_VV_MF2_E16_MASK
Definition riscv/opcodes.hpp:1654
LIEF::assembly::riscv::OPCODE::PseudoVMFEQ_VV_MF2
@ PseudoVMFEQ_VV_MF2
Definition riscv/opcodes.hpp:6636
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VV_M1
@ PseudoVSRA_VV_M1
Definition riscv/opcodes.hpp:9877
LIEF::assembly::riscv::OPCODE::G_STRICT_FSUB
@ G_STRICT_FSUB
Definition riscv/opcodes.hpp:283
LIEF::assembly::riscv::OPCODE::PseudoVSADDU_VV_MF2_MASK
@ PseudoVSADDU_VV_MF2_MASK
Definition riscv/opcodes.hpp:8627
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M2_M1_MASK
@ PseudoVLUXEI64_V_M2_M1_MASK
Definition riscv/opcodes.hpp:5659
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M1_E8_MASK
@ PseudoVWREDSUM_VS_M1_E8_MASK
Definition riscv/opcodes.hpp:11652
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M4_E16_MASK
@ PseudoVFMUL_VV_M4_E16_MASK
Definition riscv/opcodes.hpp:2355
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_M1_E32
@ PseudoVREM_VX_M1_E32
Definition riscv/opcodes.hpp:8218
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M8_E32
@ PseudoVFNMSUB_VV_M8_E32
Definition riscv/opcodes.hpp:2845
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF8
@ PseudoVWSUB_WV_MF8
Definition riscv/opcodes.hpp:11823
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF4_MASK
@ PseudoVLUXSEG6EI32_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:6199
LIEF::assembly::riscv::OPCODE::VL8RE8_V
@ VL8RE8_V
Definition riscv/opcodes.hpp:13322
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG5E16_V_MF4
@ PseudoVSSSEG5E16_V_MF4
Definition riscv/opcodes.hpp:10343
LIEF::assembly::riscv::OPCODE::PseudoVFMERGE_VFPR16M_M4
@ PseudoVFMERGE_VFPR16M_M4
Definition riscv/opcodes.hpp:2119
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M4_M1
@ PseudoVSOXSEG7EI32_V_M4_M1
Definition riscv/opcodes.hpp:9701
LIEF::assembly::riscv::OPCODE::PseudoVLE8FF_V_M8_MASK
@ PseudoVLE8FF_V_M8_MASK
Definition riscv/opcodes.hpp:4150
LIEF::assembly::riscv::OPCODE::PseudoVC_V_VVV_MF2
@ PseudoVC_V_VVV_MF2
Definition riscv/opcodes.hpp:1306
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16_TIED
@ PseudoVFWSUB_WV_MF2_E16_TIED
Definition riscv/opcodes.hpp:4036
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E32_M2_MASK
@ PseudoVRGATHEREI16_VV_M1_E32_M2_MASK
Definition riscv/opcodes.hpp:8285
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK
@ PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK
Definition riscv/opcodes.hpp:8295
LIEF::assembly::riscv::OPCODE::G_FPTOSI
@ G_FPTOSI
Definition riscv/opcodes.hpp:216
LIEF::assembly::riscv::OPCODE::PseudoVFWMACC_VFPR32_M2_E32
@ PseudoVFWMACC_VFPR32_M2_E32
Definition riscv/opcodes.hpp:3743
LIEF::assembly::riscv::OPCODE::AMOCAS_B
@ AMOCAS_B
Definition riscv/opcodes.hpp:11979
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_MF2_M2
@ PseudoVSOXSEG3EI16_V_MF2_M2
Definition riscv/opcodes.hpp:9305
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF4_MF2
@ PseudoVSUXSEG8EI8_V_MF4_MF2
Definition riscv/opcodes.hpp:11323
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI32_V_M1_M2
@ PseudoVLOXSEG4EI32_V_M1_M2
Definition riscv/opcodes.hpp:4610
LIEF::assembly::riscv::OPCODE::CV_SW_rr
@ CV_SW_rr
Definition riscv/opcodes.hpp:12465
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_M1
@ PseudoVC_FPR16VW_SE_M1
Definition riscv/opcodes.hpp:1084
LIEF::assembly::riscv::OPCODE::PseudoVREDSUM_VS_M2_E8_MASK
@ PseudoVREDSUM_VS_M2_E8_MASK
Definition riscv/opcodes.hpp:7979
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M4_MASK
@ PseudoVCPOP_V_M4_MASK
Definition riscv/opcodes.hpp:1055
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_M4
@ PseudoVC_V_FPR16VV_M4
Definition riscv/opcodes.hpp:1168
LIEF::assembly::riscv::OPCODE::PseudoVLE8_V_M2_MASK
@ PseudoVLE8_V_M2_MASK
Definition riscv/opcodes.hpp:4160
LIEF::assembly::riscv::OPCODE::VMFEQ_VV
@ VMFEQ_VV
Definition riscv/opcodes.hpp:13504
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_M1_MF2
@ PseudoVSOXSEG7EI32_V_M1_MF2
Definition riscv/opcodes.hpp:9693
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M1_MF8
@ PseudoVSUXSEG3EI64_V_M1_MF8
Definition riscv/opcodes.hpp:10857
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_MF2
@ PseudoVLSEG6E32FF_V_MF2
Definition riscv/opcodes.hpp:5292
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M1_MF8
@ PseudoVAESDF_VS_M1_MF8
Definition riscv/opcodes.hpp:643
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VW_SE_MF2
@ PseudoVC_FPR16VW_SE_MF2
Definition riscv/opcodes.hpp:1088
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_M1_E16
@ PseudoVFNCVT_F_X_W_M1_E16
Definition riscv/opcodes.hpp:2471
LIEF::assembly::riscv::OPCODE::CV_SLL_SC_B
@ CV_SLL_SC_B
Definition riscv/opcodes.hpp:12429
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_M4_M1
@ PseudoVSUXEI32_V_M4_M1
Definition riscv/opcodes.hpp:10561
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M8_E16_MASK
@ PseudoVFMSUB_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2259
LIEF::assembly::riscv::OPCODE::AMOMINU_D
@ AMOMINU_D
Definition riscv/opcodes.hpp:12039
LIEF::assembly::riscv::OPCODE::VSEXT_VF2
@ VSEXT_VF2
Definition riscv/opcodes.hpp:13637
LIEF::assembly::riscv::OPCODE::PseudoVC_FPR16VV_SE_M2
@ PseudoVC_FPR16VV_SE_M2
Definition riscv/opcodes.hpp:1079
LIEF::assembly::riscv::OPCODE::G_SDIVFIX
@ G_SDIVFIX
Definition riscv/opcodes.hpp:192
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_MF2_M2_MASK
@ PseudoVSOXSEG2EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:9178
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M2_MASK
@ PseudoVMSLTU_VV_M2_MASK
Definition riscv/opcodes.hpp:7167
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M1_MF4
@ PseudoVLUXSEG5EI64_V_M1_MF4
Definition riscv/opcodes.hpp:6126
LIEF::assembly::riscv::OPCODE::SHA512SIG1H
@ SHA512SIG1H
Definition riscv/opcodes.hpp:12973
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI16_V_M1_M1
@ PseudoVSUXSEG6EI16_V_M1_M1
Definition riscv/opcodes.hpp:11095
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M2_MASK
@ PseudoVWSLL_VI_M2_MASK
Definition riscv/opcodes.hpp:11686
LIEF::assembly::riscv::OPCODE::CV_AVGU_B
@ CV_AVGU_B
Definition riscv/opcodes.hpp:12187
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_M8_MASK
@ PseudoVMFGT_VFPR32_M8_MASK
Definition riscv/opcodes.hpp:6689
LIEF::assembly::riscv::OPCODE::PseudoVAND_VI_MF2
@ PseudoVAND_VI_MF2
Definition riscv/opcodes.hpp:826
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E8_MASK
@ PseudoVREDMAXU_VS_M4_E8_MASK
Definition riscv/opcodes.hpp:7767
LIEF::assembly::riscv::OPCODE::C_FSD
@ C_FSD
Definition riscv/opcodes.hpp:12493
LIEF::assembly::riscv::OPCODE::PseudoVREM_VV_M8_E32
@ PseudoVREM_VV_M8_E32
Definition riscv/opcodes.hpp:8198
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_M1_M2
@ PseudoVLUXSEG4EI16_V_M1_M2
Definition riscv/opcodes.hpp:5974
LIEF::assembly::riscv::OPCODE::PseudoVNCLIP_WI_M1_MASK
@ PseudoVNCLIP_WI_M1_MASK
Definition riscv/opcodes.hpp:7463
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR64_M1
@ PseudoVMFGT_VFPR64_M1
Definition riscv/opcodes.hpp:6692
LIEF::assembly::riscv::OPCODE::PseudoVREDMINU_VS_M1_E32
@ PseudoVREDMINU_VS_M1_E32
Definition riscv/opcodes.hpp:7834
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI64_V_M2_MF2_MASK
@ PseudoVLUXSEG5EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:6133
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG6EI32_V_MF2_MF2_MASK
@ PseudoVSUXSEG6EI32_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:11130
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M2_MASK
@ PseudoVLUXSEG3EI32_V_M2_M2_MASK
Definition riscv/opcodes.hpp:5901
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_X_F_W_MF4
@ PseudoVFNCVT_X_F_W_MF4
Definition riscv/opcodes.hpp:2611
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E32_V_M4_MASK
@ PseudoVSSSEG2E32_V_M4_MASK
Definition riscv/opcodes.hpp:10262
LIEF::assembly::riscv::OPCODE::VLSEG6E32FF_V
@ VLSEG6E32FF_V
Definition riscv/opcodes.hpp:13402
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI32_V_MF2_M1_MASK
@ PseudoVSOXSEG7EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9704
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16_V_MF2_MASK
@ PseudoVLSEG5E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5247
LIEF::assembly::riscv::OPCODE::PseudoVFWREDOSUM_VS_M1_E32_MASK
@ PseudoVFWREDOSUM_VS_M1_E32_MASK
Definition riscv/opcodes.hpp:3914
LIEF::assembly::riscv::OPCODE::PseudoVFRSQRT7_V_MF2_E32_MASK
@ PseudoVFRSQRT7_V_MF2_E32_MASK
Definition riscv/opcodes.hpp:3088
LIEF::assembly::riscv::OPCODE::PseudoVNSRL_WI_M2_MASK
@ PseudoVNSRL_WI_M2_MASK
Definition riscv/opcodes.hpp:7593
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_MF4_MF8_MASK
@ PseudoVLOXSEG5EI16_V_MF4_MF8_MASK
Definition riscv/opcodes.hpp:4709
LIEF::assembly::riscv::OPCODE::FSUB_S
@ FSUB_S
Definition riscv/opcodes.hpp:12791
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E32FF_V_MF2_MASK
@ PseudoVLSEG6E32FF_V_MF2_MASK
Definition riscv/opcodes.hpp:5293
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_MF2_E32_MASK
@ PseudoVDIVU_VX_MF2_E32_MASK
Definition riscv/opcodes.hpp:1502
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VX_M8_E16_MASK
@ PseudoVDIV_VX_M8_E16_MASK
Definition riscv/opcodes.hpp:1580
LIEF::assembly::riscv::OPCODE::PseudoVFWMUL_VFPR16_MF4_E16_MASK
@ PseudoVFWMUL_VFPR16_MF4_E16_MASK
Definition riscv/opcodes.hpp:3812
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VFPR64_M4_E64
@ PseudoVFSGNJN_VFPR64_M4_E64
Definition riscv/opcodes.hpp:3147
LIEF::assembly::riscv::OPCODE::PseudoVFSLIDE1UP_VFPR16_M8
@ PseudoVFSLIDE1UP_VFPR16_M8
Definition riscv/opcodes.hpp:3337
LIEF::assembly::riscv::OPCODE::PseudoVAADDU_VV_MF2
@ PseudoVAADDU_VV_MF2
Definition riscv/opcodes.hpp:529
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG4EI32_V_M1_MF2
@ PseudoVSOXSEG4EI32_V_M1_MF2
Definition riscv/opcodes.hpp:9433
LIEF::assembly::riscv::OPCODE::VFCVT_X_F_V
@ VFCVT_X_F_V
Definition riscv/opcodes.hpp:13212
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_MF8_MF4
@ PseudoVSUXEI8_V_MF8_MF4
Definition riscv/opcodes.hpp:10655
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF4_MF4_MASK
@ PseudoVSOXSEG7EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9688
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_MF4_MASK
@ PseudoVLSSEG3E8_V_MF4_MASK
Definition riscv/opcodes.hpp:5459
LIEF::assembly::riscv::OPCODE::PseudoVFWNMSAC_VFPR16_MF2_E16_MASK
@ PseudoVFWNMSAC_VFPR16_MF2_E16_MASK
Definition riscv/opcodes.hpp:3882
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M2_E16_MASK
@ PseudoVREDMIN_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:7885
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E64_M4
@ PseudoVRGATHEREI16_VV_M8_E64_M4
Definition riscv/opcodes.hpp:8384
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E8_V_M2_MASK
@ PseudoVLSEG2E8_V_M2_MASK
Definition riscv/opcodes.hpp:5117
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI8_V_MF4_MF4_MASK
@ PseudoVLOXSEG7EI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4921
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI8_V_MF4_M1_MASK
@ PseudoVLUXSEG4EI8_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:6067
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI16_V_M2_M1_MASK
@ PseudoVSOXSEG2EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9164
LIEF::assembly::riscv::OPCODE::PseudoVFMAX_VFPR32_MF2_E32_MASK
@ PseudoVFMAX_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:2078
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI16_V_M2_M1
@ PseudoVLOXSEG7EI16_V_M2_M1
Definition riscv/opcodes.hpp:4854
LIEF::assembly::riscv::OPCODE::PseudoVDIV_VV_M1_E16
@ PseudoVDIV_VV_M1_E16
Definition riscv/opcodes.hpp:1511
LIEF::assembly::riscv::OPCODE::PseudoVMACC_VX_MF4
@ PseudoVMACC_VX_MF4
Definition riscv/opcodes.hpp:6426
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M2_E64_MASK
@ PseudoVFNMSAC_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:2776
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_VV_M4
@ PseudoVWSUB_VV_M4
Definition riscv/opcodes.hpp:11783
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_M8
@ PseudoVBREV_V_M8
Definition riscv/opcodes.hpp:936
LIEF::assembly::riscv::OPCODE::VMORN_MM
@ VMORN_MM
Definition riscv/opcodes.hpp:13519
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI8_V_MF8_M1
@ PseudoVSUXSEG8EI8_V_MF8_M1
Definition riscv/opcodes.hpp:11327
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WX_M4_MASK
@ PseudoVWSUB_WX_M4_MASK
Definition riscv/opcodes.hpp:11832
LIEF::assembly::riscv::OPCODE::PseudoVC_V_I_M4
@ PseudoVC_V_I_M4
Definition riscv/opcodes.hpp:1290
LIEF::assembly::riscv::OPCODE::PseudoVAESZ_VS_M4_M2
@ PseudoVAESZ_VS_M4_M2
Definition riscv/opcodes.hpp:776
LIEF::assembly::riscv::OPCODE::VSSEG3E32_V
@ VSSEG3E32_V
Definition riscv/opcodes.hpp:13707
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI32_V_M2_M2
@ PseudoVSUXSEG3EI32_V_M2_M2
Definition riscv/opcodes.hpp:10833
LIEF::assembly::riscv::OPCODE::CV_AVGU_SCI_B
@ CV_AVGU_SCI_B
Definition riscv/opcodes.hpp:12189
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI8_V_M1_M2_MASK
@ PseudoVLOXSEG2EI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:4437
LIEF::assembly::riscv::OPCODE::PseudoVSSE8_V_M2
@ PseudoVSSE8_V_M2
Definition riscv/opcodes.hpp:9979
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_M2_MASK
@ PseudoVLUXEI8_V_MF4_M2_MASK
Definition riscv/opcodes.hpp:5713
LIEF::assembly::riscv::OPCODE::PseudoVFMACC_VFPR16_MF2_E16
@ PseudoVFMACC_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:1945
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E16_MF2
@ PseudoVRGATHEREI16_VV_M2_E16_MF2
Definition riscv/opcodes.hpp:8312
LIEF::assembly::riscv::OPCODE::PseudoVCLMULH_VV_MF2
@ PseudoVCLMULH_VV_MF2
Definition riscv/opcodes.hpp:952
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M8_E64
@ PseudoVFMADD_VFPR64_M8_E64
Definition riscv/opcodes.hpp:2025
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI8_V_MF2_M1
@ PseudoVLUXSEG2EI8_V_MF2_M1
Definition riscv/opcodes.hpp:5838
LIEF::assembly::riscv::OPCODE::G_FMAXNUM
@ G_FMAXNUM
Definition riscv/opcodes.hpp:225
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VX_M2_MASK
@ PseudoVSSRA_VX_M2_MASK
Definition riscv/opcodes.hpp:10194
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_M1_MASK
@ PseudoVSOXSEG6EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9592
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_F_X_V_MF8_E8_MASK
@ PseudoVFWCVT_F_X_V_MF8_E8_MASK
Definition riscv/opcodes.hpp:3636
LIEF::assembly::riscv::OPCODE::PseudoVROL_VV_M4
@ PseudoVROL_VV_M4
Definition riscv/opcodes.hpp:8510
LIEF::assembly::riscv::OPCODE::PseudoVFDIV_VV_MF2_E32
@ PseudoVFDIV_VV_MF2_E32
Definition riscv/opcodes.hpp:1919
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VV_M4
@ PseudoVMULH_VV_M4
Definition riscv/opcodes.hpp:7337
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI16_V_MF4_M1
@ PseudoVSOXEI16_V_MF4_M1
Definition riscv/opcodes.hpp:9033
LIEF::assembly::riscv::OPCODE::PseudoVSSEG6E8_V_MF4_MASK
@ PseudoVSSEG6E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10120
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR32_MF2
@ PseudoVMFGT_VFPR32_MF2
Definition riscv/opcodes.hpp:6690
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI16_V_M2_M1_MASK
@ PseudoVLOXSEG5EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:4695
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M1_M2_MASK
@ PseudoVSOXEI8_V_M1_M2_MASK
Definition riscv/opcodes.hpp:9114
LIEF::assembly::riscv::OPCODE::PseudoVFRDIV_VFPR32_M8_E32_MASK
@ PseudoVFRDIV_VFPR32_M8_E32_MASK
Definition riscv/opcodes.hpp:2894
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B2
@ PseudoVCPOP_M_B2
Definition riscv/opcodes.hpp:1040
LIEF::assembly::riscv::OPCODE::VSSEG6E64_V
@ VSSEG6E64_V
Definition riscv/opcodes.hpp:13720
LIEF::assembly::riscv::OPCODE::PseudoVAESEM_VV_MF2
@ PseudoVAESEM_VV_MF2
Definition riscv/opcodes.hpp:755
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VV_M2_E16
@ PseudoVFMSAC_VV_M2_E16
Definition riscv/opcodes.hpp:2228
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF8
@ PseudoVAND_VV_MF8
Definition riscv/opcodes.hpp:844
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI8_V_M4_M4
@ PseudoVSOXSEG2EI8_V_M4_M4
Definition riscv/opcodes.hpp:9265
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M2_M2_MASK
@ PseudoVSUXSEG4EI64_V_M2_M2_MASK
Definition riscv/opcodes.hpp:10972
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VFPR32_M2_E32_MASK
@ PseudoVFMUL_VFPR32_M2_E32_MASK
Definition riscv/opcodes.hpp:2327
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E16_V_MF2
@ PseudoVSSEG5E16_V_MF2
Definition riscv/opcodes.hpp:10085
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VX_M2_MASK
@ PseudoVMULHU_VX_M2_MASK
Definition riscv/opcodes.hpp:7322
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI8_V_MF8_MF8_MASK
@ PseudoVLOXEI8_V_MF8_MF8_MASK
Definition riscv/opcodes.hpp:4333
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E64_V_M1_MASK
@ PseudoVLSSEG3E64_V_M1_MASK
Definition riscv/opcodes.hpp:5449
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RTZ_XU_F_V_M4_MASK
@ PseudoVFCVT_RTZ_XU_F_V_M4_MASK
Definition riscv/opcodes.hpp:1820
LIEF::assembly::riscv::OPCODE::PseudoVMSNE_VX_M8
@ PseudoVMSNE_VX_M8
Definition riscv/opcodes.hpp:7255
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI16_V_M1_M2
@ PseudoVLUXSEG3EI16_V_M1_M2
Definition riscv/opcodes.hpp:5864
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M2
@ PseudoVLOXEI64_V_M8_M2
Definition riscv/opcodes.hpp:4284
LIEF::assembly::riscv::OPCODE::CV_LBU_rr_inc
@ CV_LBU_rr_inc
Definition riscv/opcodes.hpp:12320
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M2_E64
@ PseudoVFSGNJX_VFPR64_M2_E64
Definition riscv/opcodes.hpp:3205
LIEF::assembly::riscv::OPCODE::G_CONSTANT
@ G_CONSTANT
Definition riscv/opcodes.hpp:151
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M2_E16_MASK
@ PseudoVFREDUSUM_VS_M2_E16_MASK
Definition riscv/opcodes.hpp:3032
LIEF::assembly::riscv::OPCODE::PseudoVSMUL_VX_MF2_MASK
@ PseudoVSMUL_VX_MF2_MASK
Definition riscv/opcodes.hpp:8987
LIEF::assembly::riscv::OPCODE::FEQ_S_INX
@ FEQ_S_INX
Definition riscv/opcodes.hpp:12659
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG2E16_V_M4_MASK
@ PseudoVSSSEG2E16_V_M4_MASK
Definition riscv/opcodes.hpp:10252
LIEF::assembly::riscv::OPCODE::PseudoVFWMSAC_VFPR16_MF2_E16
@ PseudoVFWMSAC_VFPR16_MF2_E16
Definition riscv/opcodes.hpp:3773
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M2_E16_MASK
@ PseudoVFNCVT_F_F_W_M2_E16_MASK
Definition riscv/opcodes.hpp:2440
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI64_V_M2_MF2
@ PseudoVSOXSEG7EI64_V_M2_MF2
Definition riscv/opcodes.hpp:9721
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_MF2_MASK
@ PseudoVNMSAC_VX_MF2_MASK
Definition riscv/opcodes.hpp:7521
LIEF::assembly::riscv::OPCODE::PseudoVREDMAXU_VS_M4_E8
@ PseudoVREDMAXU_VS_M4_E8
Definition riscv/opcodes.hpp:7766
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG4EI64_V_M8_M1
@ PseudoVLOXSEG4EI64_V_M8_M1
Definition riscv/opcodes.hpp:4658
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG8EI64_V_M2_MF2_MASK
@ PseudoVSUXSEG8EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:11306
LIEF::assembly::riscv::OPCODE::VFWNMACC_VF
@ VFWNMACC_VF
Definition riscv/opcodes.hpp:13293
LIEF::assembly::riscv::OPCODE::PseudoVFREDMAX_VS_MF2_E16
@ PseudoVFREDMAX_VS_MF2_E16
Definition riscv/opcodes.hpp:2959
LIEF::assembly::riscv::OPCODE::PseudoVFWCVTBF16_F_F_V_M4_E32
@ PseudoVFWCVTBF16_F_F_V_M4_E32
Definition riscv/opcodes.hpp:3551
LIEF::assembly::riscv::OPCODE::CV_CMPLE_SC_B
@ CV_CMPLE_SC_B
Definition riscv/opcodes.hpp:12251
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M2_E8_MASK
@ PseudoVDIVU_VV_M2_E8_MASK
Definition riscv/opcodes.hpp:1438
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI32_V_MF2_M1
@ PseudoVLOXSEG6EI32_V_MF2_M1
Definition riscv/opcodes.hpp:4802
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M4_M2_MASK
@ PseudoVLUXSEG2EI32_V_M4_M2_MASK
Definition riscv/opcodes.hpp:5781
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG7EI16_V_MF2_MF4_MASK
@ PseudoVLUXSEG7EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:6253
LIEF::assembly::riscv::OPCODE::FCVT_W_D_IN32X
@ FCVT_W_D_IN32X
Definition riscv/opcodes.hpp:12637
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VX_M1_E16
@ PseudoVDIVU_VX_M1_E16
Definition riscv/opcodes.hpp:1467
LIEF::assembly::riscv::OPCODE::PseudoVWADD_VX_M2_MASK
@ PseudoVWADD_VX_M2_MASK
Definition riscv/opcodes.hpp:11410
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG7E8_V_MF8
@ PseudoVSSSEG7E8_V_MF8
Definition riscv/opcodes.hpp:10397
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VV_M8_E32_MASK
@ PseudoVFNMSAC_VV_M8_E32_MASK
Definition riscv/opcodes.hpp:2786
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_M1_M1
@ PseudoVSOXSEG6EI16_V_M1_M1
Definition riscv/opcodes.hpp:9591
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_M2_M8_MASK
@ PseudoVLUXEI8_V_M2_M8_MASK
Definition riscv/opcodes.hpp:5695
LIEF::assembly::riscv::OPCODE::PseudoVFNMADD_VV_M2_E16
@ PseudoVFNMADD_VV_M2_E16
Definition riscv/opcodes.hpp:2711
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M4_M4
@ PseudoVLUXEI64_V_M4_M4
Definition riscv/opcodes.hpp:5670
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG2E16_V_M1
@ PseudoVLSSEG2E16_V_M1
Definition riscv/opcodes.hpp:5398
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VX_M2_MASK
@ PseudoVASUB_VX_M2_MASK
Definition riscv/opcodes.hpp:905
LIEF::assembly::riscv::OPCODE::CV_MAXU_SC_B
@ CV_MAXU_SC_B
Definition riscv/opcodes.hpp:12348
LIEF::assembly::riscv::OPCODE::PseudoVSSEG3E8_V_M1
@ PseudoVSSEG3E8_V_M1
Definition riscv/opcodes.hpp:10045
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E64FF_V_M1_MASK
@ PseudoVLSEG8E64FF_V_M1_MASK
Definition riscv/opcodes.hpp:5379
LIEF::assembly::riscv::OPCODE::CV_SUBUNR
@ CV_SUBUNR
Definition riscv/opcodes.hpp:12452
LIEF::assembly::riscv::OPCODE::PseudoVBREV_V_MF4
@ PseudoVBREV_V_MF4
Definition riscv/opcodes.hpp:940
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_MF4
@ PseudoVFCLASS_V_MF4
Definition riscv/opcodes.hpp:1669
LIEF::assembly::riscv::OPCODE::PseudoVLSEG7E32_V_MF2_MASK
@ PseudoVLSEG7E32_V_MF2_MASK
Definition riscv/opcodes.hpp:5337
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI32_V_M1_MF2_MASK
@ PseudoVLUXSEG4EI32_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6005
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI16_V_M1_MF2
@ PseudoVLOXSEG8EI16_V_M1_MF2
Definition riscv/opcodes.hpp:4932
LIEF::assembly::riscv::OPCODE::PseudoVC_I_SE_M4
@ PseudoVC_I_SE_M4
Definition riscv/opcodes.hpp:1141
LIEF::assembly::riscv::OPCODE::PseudoVLSEG5E16FF_V_MF4_MASK
@ PseudoVLSEG5E16FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5243
LIEF::assembly::riscv::OPCODE::PseudoVFNMSUB_VV_M2_E64
@ PseudoVFNMSUB_VV_M2_E64
Definition riscv/opcodes.hpp:2835
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR16_MF2
@ PseudoVFMV_V_FPR16_MF2
Definition riscv/opcodes.hpp:2406
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI8_V_M2_M2_MASK
@ PseudoVSOXEI8_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9120
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_M4
@ PseudoVWMUL_VX_M4
Definition riscv/opcodes.hpp:11603
LIEF::assembly::riscv::OPCODE::PseudoVROR_VI_MF2
@ PseudoVROR_VI_MF2
Definition riscv/opcodes.hpp:8542
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI32_V_M4_M8
@ PseudoVSOXEI32_V_M4_M8
Definition riscv/opcodes.hpp:9063
LIEF::assembly::riscv::OPCODE::PseudoVMULH_VX_M4
@ PseudoVMULH_VX_M4
Definition riscv/opcodes.hpp:7351
LIEF::assembly::riscv::OPCODE::CV_ADD_DIV8
@ CV_ADD_DIV8
Definition riscv/opcodes.hpp:12175
LIEF::assembly::riscv::OPCODE::PseudoVREM_VX_MF2_E16
@ PseudoVREM_VX_MF2_E16
Definition riscv/opcodes.hpp:8248
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_M8_E64_MASK
@ PseudoVFREDUSUM_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:3048
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI64_V_M2_M1
@ PseudoVSUXSEG2EI64_V_M2_M1
Definition riscv/opcodes.hpp:10737
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF4
@ PseudoVXOR_VV_MF4
Definition riscv/opcodes.hpp:11863
LIEF::assembly::riscv::OPCODE::PseudoVMSLE_VX_MF8_MASK
@ PseudoVMSLE_VX_MF8_MASK
Definition riscv/opcodes.hpp:7162
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI16_V_MF4_M1_MASK
@ PseudoVLUXSEG2EI16_V_MF4_M1_MASK
Definition riscv/opcodes.hpp:5755
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M1_MASK
@ PseudoVNMSAC_VX_M1_MASK
Definition riscv/opcodes.hpp:7513
LIEF::assembly::riscv::OPCODE::PseudoVFNCVTBF16_F_F_W_MF2_E16
@ PseudoVFNCVTBF16_F_F_W_MF2_E16
Definition riscv/opcodes.hpp:2429
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI8_V_MF2_M1
@ PseudoVSUXSEG7EI8_V_MF2_M1
Definition riscv/opcodes.hpp:11237
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M2_E32_M1
@ PseudoVRGATHEREI16_VV_M2_E32_M1
Definition riscv/opcodes.hpp:8314
LIEF::assembly::riscv::OPCODE::PseudoVMSGEU_VI
@ PseudoVMSGEU_VI
Definition riscv/opcodes.hpp:7001
LIEF::assembly::riscv::OPCODE::PseudoVWSLL_VI_M2
@ PseudoVWSLL_VI_M2
Definition riscv/opcodes.hpp:11685
LIEF::assembly::riscv::OPCODE::PseudoVFMSAC_VFPR16_M8_E16_MASK
@ PseudoVFMSAC_VFPR16_M8_E16_MASK
Definition riscv/opcodes.hpp:2199
LIEF::assembly::riscv::OPCODE::PseudoVREDXOR_VS_MF2_E8
@ PseudoVREDXOR_VS_MF2_E8
Definition riscv/opcodes.hpp:8044
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E16_V_MF2_MASK
@ PseudoVLSEG8E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5367
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG7EI64_V_M2_MF2_MASK
@ PseudoVLOXSEG7EI64_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4901
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF2_M1
@ PseudoVSUXSEG4EI8_V_MF2_M1
Definition riscv/opcodes.hpp:10993
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M1_MASK
@ PseudoVSOXSEG3EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:9298
LIEF::assembly::riscv::OPCODE::PseudoVAESDF_VS_M4_MF2
@ PseudoVAESDF_VS_M4_MF2
Definition riscv/opcodes.hpp:652
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_V_M1_MASK
@ PseudoVCPOP_V_M1_MASK
Definition riscv/opcodes.hpp:1051
LIEF::assembly::riscv::OPCODE::PseudoVSE32_V_M4_MASK
@ PseudoVSE32_V_M4_MASK
Definition riscv/opcodes.hpp:8719
LIEF::assembly::riscv::OPCODE::PseudoVNMSAC_VX_M8_MASK
@ PseudoVNMSAC_VX_M8_MASK
Definition riscv/opcodes.hpp:7519
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI16_V_M2_M2_MASK
@ PseudoVSOXSEG3EI16_V_M2_M2_MASK
Definition riscv/opcodes.hpp:9300
LIEF::assembly::riscv::OPCODE::CSRRC
@ CSRRC
Definition riscv/opcodes.hpp:12153
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_MF4_M1
@ PseudoVLUXEI16_V_MF4_M1
Definition riscv/opcodes.hpp:5604
LIEF::assembly::riscv::OPCODE::PseudoVAND_VV_MF2
@ PseudoVAND_VV_MF2
Definition riscv/opcodes.hpp:840
LIEF::assembly::riscv::OPCODE::PseudoVXOR_VV_MF8
@ PseudoVXOR_VV_MF8
Definition riscv/opcodes.hpp:11865
LIEF::assembly::riscv::OPCODE::SH1ADD_UW
@ SH1ADD_UW
Definition riscv/opcodes.hpp:12960
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_MF4_MASK
@ PseudoVSSRA_VI_MF4_MASK
Definition riscv/opcodes.hpp:10174
LIEF::assembly::riscv::OPCODE::G_SADDE
@ G_SADDE
Definition riscv/opcodes.hpp:175
LIEF::assembly::riscv::OPCODE::PseudoVSSEG4E16_V_MF4
@ PseudoVSSEG4E16_V_MF4
Definition riscv/opcodes.hpp:10061
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VV_MF4_MASK
@ PseudoVSRL_VV_MF4_MASK
Definition riscv/opcodes.hpp:9930
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG3EI32_V_M2_M1_MASK
@ PseudoVLUXSEG3EI32_V_M2_M1_MASK
Definition riscv/opcodes.hpp:5899
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M8_E16_M2_MASK
@ PseudoVRGATHEREI16_VV_M8_E16_M2_MASK
Definition riscv/opcodes.hpp:8371
LIEF::assembly::riscv::OPCODE::PseudoVSSRA_VI_M1
@ PseudoVSSRA_VI_M1
Definition riscv/opcodes.hpp:10163
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI16_V_M4_M8_MASK
@ PseudoVLUXEI16_V_M4_M8_MASK
Definition riscv/opcodes.hpp:5591
LIEF::assembly::riscv::OPCODE::PseudoMaskedAtomicLoadAdd32
@ PseudoMaskedAtomicLoadAdd32
Definition riscv/opcodes.hpp:407
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E8_V_MF8
@ PseudoVLSSEG4E8_V_MF8
Definition riscv/opcodes.hpp:5488
LIEF::assembly::riscv::OPCODE::FEQ_H_INX
@ FEQ_H_INX
Definition riscv/opcodes.hpp:12657
LIEF::assembly::riscv::OPCODE::FLI_S
@ FLI_S
Definition riscv/opcodes.hpp:12674
LIEF::assembly::riscv::OPCODE::CV_LHU_rr_inc
@ CV_LHU_rr_inc
Definition riscv/opcodes.hpp:12326
LIEF::assembly::riscv::OPCODE::PseudoVMFLT_VV_M8
@ PseudoVMFLT_VV_M8
Definition riscv/opcodes.hpp:6778
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M2_MF4
@ PseudoVSOXEI64_V_M2_MF4
Definition riscv/opcodes.hpp:9093
LIEF::assembly::riscv::OPCODE::PseudoVMSLT_VV_MF8_MASK
@ PseudoVMSLT_VV_MF8_MASK
Definition riscv/opcodes.hpp:7206
LIEF::assembly::riscv::OPCODE::PseudoVFWSUB_WV_MF2_E16_MASK_TIED
@ PseudoVFWSUB_WV_MF2_E16_MASK_TIED
Definition riscv/opcodes.hpp:4035
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M4
@ PseudoVMULHSU_VV_M4
Definition riscv/opcodes.hpp:7281
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI8_V_MF8_M1
@ PseudoVSUXSEG4EI8_V_MF8_M1
Definition riscv/opcodes.hpp:11007
LIEF::assembly::riscv::OPCODE::PseudoVSSEG5E8_V_MF2_MASK
@ PseudoVSSEG5E8_V_MF2_MASK
Definition riscv/opcodes.hpp:10098
LIEF::assembly::riscv::OPCODE::PseudoVSSUBU_VX_M4
@ PseudoVSSUBU_VX_M4
Definition riscv/opcodes.hpp:10437
LIEF::assembly::riscv::OPCODE::FMUL_D_IN32X
@ FMUL_D_IN32X
Definition riscv/opcodes.hpp:12721
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG5EI32_V_M2_MF2_MASK
@ PseudoVLOXSEG5EI32_V_M2_MF2_MASK
Definition riscv/opcodes.hpp:4719
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E8_V_M1_MASK
@ PseudoVLSSEG3E8_V_M1_MASK
Definition riscv/opcodes.hpp:5453
LIEF::assembly::riscv::OPCODE::VCLMUL_VV
@ VCLMUL_VV
Definition riscv/opcodes.hpp:13165
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VV_M2_E64_MASK
@ PseudoVFSGNJX_VV_M2_E64_MASK
Definition riscv/opcodes.hpp:3222
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M1_E64
@ PseudoVFCVT_F_XU_V_M1_E64
Definition riscv/opcodes.hpp:1675
LIEF::assembly::riscv::OPCODE::PseudoVLSEG8E8_V_MF2
@ PseudoVLSEG8E8_V_MF2
Definition riscv/opcodes.hpp:5392
LIEF::assembly::riscv::OPCODE::PseudoVMSLEU_VV_MF2_MASK
@ PseudoVMSLEU_VV_MF2_MASK
Definition riscv/opcodes.hpp:7102
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR16_MF2
@ PseudoVFMV_S_FPR16_MF2
Definition riscv/opcodes.hpp:2391
LIEF::assembly::riscv::OPCODE::PseudoVAND_VX_MF4
@ PseudoVAND_VX_MF4
Definition riscv/opcodes.hpp:856
LIEF::assembly::riscv::OPCODE::PseudoVFMV_S_FPR64_M2
@ PseudoVFMV_S_FPR64_M2
Definition riscv/opcodes.hpp:2399
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M8_MASK
@ PseudoVMULHU_VV_M8_MASK
Definition riscv/opcodes.hpp:7312
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_F_XU_V_M4_E16
@ PseudoVFCVT_RM_F_XU_V_M4_E16
Definition riscv/opcodes.hpp:1743
LIEF::assembly::riscv::OPCODE::FMUL_S_INX
@ FMUL_S_INX
Definition riscv/opcodes.hpp:12726
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VX_MF4
@ PseudoVMSGT_VX_MF4
Definition riscv/opcodes.hpp:7061
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_MF4
@ PseudoVASUB_VV_MF4
Definition riscv/opcodes.hpp:898
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR64_M4
@ PseudoVMFLE_VFPR64_M4
Definition riscv/opcodes.hpp:6726
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI8_V_MF4_MF2_MASK
@ PseudoVLOXSEG8EI8_V_MF4_MF2_MASK
Definition riscv/opcodes.hpp:4999
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI64_V_M1_M1
@ PseudoVLOXSEG2EI64_V_M1_M1
Definition riscv/opcodes.hpp:4404
LIEF::assembly::riscv::OPCODE::PseudoVFCLASS_V_M2_MASK
@ PseudoVFCLASS_V_M2_MASK
Definition riscv/opcodes.hpp:1662
LIEF::assembly::riscv::OPCODE::LR_W_AQ
@ LR_W_AQ
Definition riscv/opcodes.hpp:12848
LIEF::assembly::riscv::OPCODE::TH_MULAH
@ TH_MULAH
Definition riscv/opcodes.hpp:13093
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG6EI16_V_MF4_MF4_MASK
@ PseudoVSOXSEG6EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:9608
LIEF::assembly::riscv::OPCODE::PseudoVOR_VV_M1_MASK
@ PseudoVOR_VV_M1_MASK
Definition riscv/opcodes.hpp:7641
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VW_M2
@ PseudoVC_V_FPR16VW_M2
Definition riscv/opcodes.hpp:1179
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI64_V_M4_MF2
@ PseudoVSUXSEG3EI64_V_M4_MF2
Definition riscv/opcodes.hpp:10871
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M1_MF4_MASK
@ PseudoVLOXSEG3EI32_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:4505
LIEF::assembly::riscv::OPCODE::PseudoVFREDUSUM_VS_MF2_E32
@ PseudoVFREDUSUM_VS_MF2_E32
Definition riscv/opcodes.hpp:3051
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E32_V_M2
@ PseudoVLSSEG3E32_V_M2
Definition riscv/opcodes.hpp:5444
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJ_VV_MF2_E16
@ PseudoVFSGNJ_VV_MF2_E16
Definition riscv/opcodes.hpp:3295
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI32_V_MF2_MF2
@ PseudoVSUXEI32_V_MF2_MF2
Definition riscv/opcodes.hpp:10577
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_X_W_M1_E16
@ PseudoVFNCVT_RM_F_X_W_M1_E16
Definition riscv/opcodes.hpp:2507
LIEF::assembly::riscv::OPCODE::PseudoVLE32FF_V_M4_MASK
@ PseudoVLE32FF_V_M4_MASK
Definition riscv/opcodes.hpp:4112
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M8_E32
@ PseudoVREDAND_VS_M8_E32
Definition riscv/opcodes.hpp:7726
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI16_V_M2_M1_MASK
@ PseudoVSUXSEG7EI16_V_M2_M1_MASK
Definition riscv/opcodes.hpp:11180
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI32_V_M2_M1
@ PseudoVLUXSEG8EI32_V_M2_M1
Definition riscv/opcodes.hpp:6348
LIEF::assembly::riscv::OPCODE::PseudoVOR_VX_M1_MASK
@ PseudoVOR_VX_M1_MASK
Definition riscv/opcodes.hpp:7655
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M1_M1
@ PseudoVSM4R_VS_M1_M1
Definition riscv/opcodes.hpp:8935
LIEF::assembly::riscv::OPCODE::PseudoVSRL_VI_MF4
@ PseudoVSRL_VI_MF4
Definition riscv/opcodes.hpp:9915
LIEF::assembly::riscv::OPCODE::PseudoVREMU_VX_M2_E16
@ PseudoVREMU_VX_M2_E16
Definition riscv/opcodes.hpp:8136
LIEF::assembly::riscv::OPCODE::PseudoVSLIDE1DOWN_VX_M1_MASK
@ PseudoVSLIDE1DOWN_VX_M1_MASK
Definition riscv/opcodes.hpp:8795
LIEF::assembly::riscv::OPCODE::PseudoVAADD_VX_MF2
@ PseudoVAADD_VX_MF2
Definition riscv/opcodes.hpp:571
LIEF::assembly::riscv::OPCODE::PseudoVWREDSUM_VS_M4_E16_MASK
@ PseudoVWREDSUM_VS_M4_E16_MASK
Definition riscv/opcodes.hpp:11660
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG4EI64_V_M1_MF2
@ PseudoVSUXSEG4EI64_V_M1_MF2
Definition riscv/opcodes.hpp:10963
LIEF::assembly::riscv::OPCODE::PseudoVSM4R_VS_M4_M1
@ PseudoVSM4R_VS_M4_M1
Definition riscv/opcodes.hpp:8944
LIEF::assembly::riscv::OPCODE::C_MOP1
@ C_MOP1
Definition riscv/opcodes.hpp:12512
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_M4
@ PseudoVC_V_XVW_SE_M4
Definition riscv/opcodes.hpp:1364
LIEF::assembly::riscv::OPCODE::THVdotVMAQASU_VX
@ THVdotVMAQASU_VX
Definition riscv/opcodes.hpp:13021
LIEF::assembly::riscv::OPCODE::PseudoVWMULSU_VX_MF8_MASK
@ PseudoVWMULSU_VX_MF8_MASK
Definition riscv/opcodes.hpp:11562
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI8_V_M1_M1_MASK
@ PseudoVSUXSEG2EI8_V_M1_M1_MASK
Definition riscv/opcodes.hpp:10760
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VVM_M1
@ PseudoVMERGE_VVM_M1
Definition riscv/opcodes.hpp:6584
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG6EI64_V_M1_M1
@ PseudoVLOXSEG6EI64_V_M1_M1
Definition riscv/opcodes.hpp:4810
LIEF::assembly::riscv::OPCODE::PseudoVRSUB_VX_MF8_MASK
@ PseudoVRSUB_VX_MF8_MASK
Definition riscv/opcodes.hpp:8603
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_M1_E8_M1
@ PseudoVRGATHEREI16_VV_M1_E8_M1
Definition riscv/opcodes.hpp:8298
LIEF::assembly::riscv::OPCODE::WriteFFLAGS
@ WriteFFLAGS
Definition riscv/opcodes.hpp:11927
LIEF::assembly::riscv::OPCODE::CV_SLETU
@ CV_SLETU
Definition riscv/opcodes.hpp:12424
LIEF::assembly::riscv::OPCODE::PseudoVLSEG4E8FF_V_MF8
@ PseudoVLSEG4E8FF_V_MF8
Definition riscv/opcodes.hpp:5226
LIEF::assembly::riscv::OPCODE::InsnCI
@ InsnCI
Definition riscv/opcodes.hpp:12816
LIEF::assembly::riscv::OPCODE::PseudoVCOMPRESS_VM_M2_E16
@ PseudoVCOMPRESS_VM_M2_E16
Definition riscv/opcodes.hpp:1018
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WV_MF2_E32
@ PseudoVFWADD_WV_MF2_E32
Definition riscv/opcodes.hpp:3533
LIEF::assembly::riscv::OPCODE::PseudoVSLIDEUP_VX_M1_MASK
@ PseudoVSLIDEUP_VX_M1_MASK
Definition riscv/opcodes.hpp:8865
LIEF::assembly::riscv::OPCODE::PseudoVFWMACCBF16_VFPR16_M2_E16
@ PseudoVFWMACCBF16_VFPR16_M2_E16
Definition riscv/opcodes.hpp:3699
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI8_V_MF2_M1_MASK
@ PseudoVSOXSEG3EI8_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9380
LIEF::assembly::riscv::OPCODE::PseudoVASUB_VV_M8
@ PseudoVASUB_VV_M8
Definition riscv/opcodes.hpp:894
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_MF8_MASK
@ PseudoVMULHSU_VX_MF8_MASK
Definition riscv/opcodes.hpp:7304
LIEF::assembly::riscv::OPCODE::PseudoVMSGT_VI_MF4_MASK
@ PseudoVMSGT_VI_MF4_MASK
Definition riscv/opcodes.hpp:7048
LIEF::assembly::riscv::OPCODE::PseudoVFIRST_M_B64_MASK
@ PseudoVFIRST_M_B64_MASK
Definition riscv/opcodes.hpp:1934
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M8_M2_MASK
@ PseudoVLUXEI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:5677
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M8_M2
@ PseudoVLUXSEG2EI32_V_M8_M2
Definition riscv/opcodes.hpp:5784
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M1
@ PseudoVMERGE_VIM_M1
Definition riscv/opcodes.hpp:6577
LIEF::assembly::riscv::OPCODE::CV_SRA_H
@ CV_SRA_H
Definition riscv/opcodes.hpp:12432
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG6E8_V_MF2
@ PseudoVSSSEG6E8_V_MF2
Definition riscv/opcodes.hpp:10373
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_F_XU_V_M2_E32
@ PseudoVFCVT_F_XU_V_M2_E32
Definition riscv/opcodes.hpp:1679
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_M1_M1_MASK
@ PseudoVSOXSEG7EI16_V_M1_M1_MASK
Definition riscv/opcodes.hpp:9672
LIEF::assembly::riscv::OPCODE::PseudoVFNMSAC_VFPR64_M1_E64_MASK
@ PseudoVFNMSAC_VFPR64_M1_E64_MASK
Definition riscv/opcodes.hpp:2758
LIEF::assembly::riscv::OPCODE::PseudoVFMV_FPR16_S_MF2
@ PseudoVFMV_FPR16_S_MF2
Definition riscv/opcodes.hpp:2376
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG5EI8_V_MF8_M1_MASK
@ PseudoVSUXSEG5EI8_V_MF8_M1_MASK
Definition riscv/opcodes.hpp:11088
LIEF::assembly::riscv::OPCODE::PseudoVWSUB_WV_MF4
@ PseudoVWSUB_WV_MF4
Definition riscv/opcodes.hpp:11819
LIEF::assembly::riscv::OPCODE::SC_D
@ SC_D
Definition riscv/opcodes.hpp:12939
LIEF::assembly::riscv::OPCODE::VC_XVW
@ VC_XVW
Definition riscv/opcodes.hpp:13199
LIEF::assembly::riscv::OPCODE::CV_CMPEQ_SC_H
@ CV_CMPEQ_SC_H
Definition riscv/opcodes.hpp:12216
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK
@ PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK
Definition riscv/opcodes.hpp:8407
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VX_M2_MASK
@ PseudoVMULHSU_VX_M2_MASK
Definition riscv/opcodes.hpp:7294
LIEF::assembly::riscv::OPCODE::VAADD_VV
@ VAADD_VV
Definition riscv/opcodes.hpp:13133
LIEF::assembly::riscv::OPCODE::PseudoVMFLE_VFPR16_M4
@ PseudoVMFLE_VFPR16_M4
Definition riscv/opcodes.hpp:6704
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG7EI16_V_MF2_MF2_MASK
@ PseudoVSOXSEG7EI16_V_MF2_MF2_MASK
Definition riscv/opcodes.hpp:9680
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG2EI16_V_MF4_MF4_MASK
@ PseudoVLOXSEG2EI16_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:4367
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI16_V_MF2_M2_MASK
@ PseudoVLOXSEG3EI16_V_MF2_M2_MASK
Definition riscv/opcodes.hpp:4485
LIEF::assembly::riscv::OPCODE::VLUXSEG3EI64_V
@ VLUXSEG3EI64_V
Definition riscv/opcodes.hpp:13462
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG3EI16_V_M1_MF2_MASK
@ PseudoVSUXSEG3EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:10800
LIEF::assembly::riscv::OPCODE::PseudoVREDAND_VS_M1_E8_MASK
@ PseudoVREDAND_VS_M1_E8_MASK
Definition riscv/opcodes.hpp:7707
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG8EI64_V_M4_M1
@ PseudoVLUXSEG8EI64_V_M4_M1
Definition riscv/opcodes.hpp:6376
LIEF::assembly::riscv::OPCODE::VBREV8_V
@ VBREV8_V
Definition riscv/opcodes.hpp:13161
LIEF::assembly::riscv::OPCODE::PseudoVC_V_XVW_SE_MF8
@ PseudoVC_V_XVW_SE_MF8
Definition riscv/opcodes.hpp:1367
LIEF::assembly::riscv::OPCODE::PseudoVLOXEI64_V_M8_M2_MASK
@ PseudoVLOXEI64_V_M8_M2_MASK
Definition riscv/opcodes.hpp:4285
LIEF::assembly::riscv::OPCODE::PseudoVFSUB_VFPR32_MF2_E32_MASK
@ PseudoVFSUB_VFPR32_MF2_E32_MASK
Definition riscv/opcodes.hpp:3412
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_X_W_MF2_E16
@ PseudoVFNCVT_F_X_W_MF2_E16
Definition riscv/opcodes.hpp:2483
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG3E16_V_M2_MASK
@ PseudoVLSSEG3E16_V_M2_MASK
Definition riscv/opcodes.hpp:5437
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF2
@ PseudoVRGATHEREI16_VV_MF4_E8_MF2
Definition riscv/opcodes.hpp:8424
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG2EI32_V_M2_M4_MASK
@ PseudoVLUXSEG2EI32_V_M2_M4_MASK
Definition riscv/opcodes.hpp:5775
LIEF::assembly::riscv::OPCODE::PseudoVFMSUB_VFPR16_M1_E16
@ PseudoVFMSUB_VFPR16_M1_E16
Definition riscv/opcodes.hpp:2252
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_M1
@ PseudoVC_V_IV_M1
Definition riscv/opcodes.hpp:1274
LIEF::assembly::riscv::OPCODE::PseudoVWMUL_VX_MF2_MASK
@ PseudoVWMUL_VX_MF2_MASK
Definition riscv/opcodes.hpp:11606
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_F_F_W_M4_E32
@ PseudoVFNCVT_F_F_W_M4_E32
Definition riscv/opcodes.hpp:2445
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG4EI16_V_MF2_MF4
@ PseudoVLUXSEG4EI16_V_MF2_MF4
Definition riscv/opcodes.hpp:5990
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJX_VFPR64_M4_E64_MASK
@ PseudoVFSGNJX_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:3208
LIEF::assembly::riscv::OPCODE::PseudoVLSSEG4E16_V_MF2_MASK
@ PseudoVLSSEG4E16_V_MF2_MASK
Definition riscv/opcodes.hpp:5467
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG2EI16_V_M4_M4
@ PseudoVSUXSEG2EI16_V_M4_M4
Definition riscv/opcodes.hpp:10675
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_M2
@ PseudoVC_V_FPR16VV_M2
Definition riscv/opcodes.hpp:1167
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG6EI32_V_MF2_MF8_MASK
@ PseudoVLUXSEG6EI32_V_MF2_MF8_MASK
Definition riscv/opcodes.hpp:6201
LIEF::assembly::riscv::OPCODE::SM4KS
@ SM4KS
Definition riscv/opcodes.hpp:12994
LIEF::assembly::riscv::OPCODE::Select_GPR_Using_CC_GPR
@ Select_GPR_Using_CC_GPR
Definition riscv/opcodes.hpp:11923
LIEF::assembly::riscv::OPCODE::PseudoVLSEG2E16FF_V_MF4_MASK
@ PseudoVLSEG2E16FF_V_MF4_MASK
Definition riscv/opcodes.hpp:5063
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI64_V_M1_MF4_MASK
@ PseudoVLUXEI64_V_M1_MF4_MASK
Definition riscv/opcodes.hpp:5655
LIEF::assembly::riscv::OPCODE::PseudoVMULHU_VV_M8
@ PseudoVMULHU_VV_M8
Definition riscv/opcodes.hpp:7311
LIEF::assembly::riscv::OPCODE::PseudoVREDMAX_VS_M8_E64
@ PseudoVREDMAX_VS_M8_E64
Definition riscv/opcodes.hpp:7816
LIEF::assembly::riscv::OPCODE::PseudoTHVdotVMAQA_VX_M2
@ PseudoTHVdotVMAQA_VX_M2
Definition riscv/opcodes.hpp:512
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK
@ PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK
Definition riscv/opcodes.hpp:2574
LIEF::assembly::riscv::OPCODE::C_LW
@ C_LW
Definition riscv/opcodes.hpp:12510
LIEF::assembly::riscv::OPCODE::PseudoVC_V_IV_SE_M8
@ PseudoVC_V_IV_SE_M8
Definition riscv/opcodes.hpp:1284
LIEF::assembly::riscv::OPCODE::CV_SUB_H
@ CV_SUB_H
Definition riscv/opcodes.hpp:12459
LIEF::assembly::riscv::OPCODE::PseudoVDIVU_VV_M1_E8
@ PseudoVDIVU_VV_M1_E8
Definition riscv/opcodes.hpp:1429
LIEF::assembly::riscv::OPCODE::PseudoVFMV_V_FPR32_M1
@ PseudoVFMV_V_FPR32_M1
Definition riscv/opcodes.hpp:2408
LIEF::assembly::riscv::OPCODE::PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK
@ PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK
Definition riscv/opcodes.hpp:2504
LIEF::assembly::riscv::OPCODE::PseudoVC_VVV_SE_MF2
@ PseudoVC_VVV_SE_MF2
Definition riscv/opcodes.hpp:1150
LIEF::assembly::riscv::OPCODE::PseudoVMSLTU_VV_M4_MASK
@ PseudoVMSLTU_VV_M4_MASK
Definition riscv/opcodes.hpp:7169
LIEF::assembly::riscv::OPCODE::PseudoVCPOP_M_B1
@ PseudoVCPOP_M_B1
Definition riscv/opcodes.hpp:1036
LIEF::assembly::riscv::OPCODE::VLSEG4E32_V
@ VLSEG4E32_V
Definition riscv/opcodes.hpp:13387
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG3EI32_V_M4_M2
@ PseudoVLOXSEG3EI32_V_M4_M2
Definition riscv/opcodes.hpp:4514
LIEF::assembly::riscv::OPCODE::G_ATOMICRMW_MIN
@ G_ATOMICRMW_MIN
Definition riscv/opcodes.hpp:131
LIEF::assembly::riscv::OPCODE::PseudoVMERGE_VIM_M4
@ PseudoVMERGE_VIM_M4
Definition riscv/opcodes.hpp:6579
LIEF::assembly::riscv::OPCODE::PseudoVSRA_VX_MF4_MASK
@ PseudoVSRA_VX_MF4_MASK
Definition riscv/opcodes.hpp:9902
LIEF::assembly::riscv::OPCODE::PseudoVFCVT_RM_XU_F_V_M1
@ PseudoVFCVT_RM_XU_F_V_M1
Definition riscv/opcodes.hpp:1791
LIEF::assembly::riscv::OPCODE::TH_SRRIW
@ TH_SRRIW
Definition riscv/opcodes.hpp:13114
LIEF::assembly::riscv::OPCODE::PseudoVFMUL_VV_M8_E16
@ PseudoVFMUL_VV_M8_E16
Definition riscv/opcodes.hpp:2360
LIEF::assembly::riscv::OPCODE::PseudoVFWCVT_X_F_V_MF2_MASK
@ PseudoVFWCVT_X_F_V_MF2_MASK
Definition riscv/opcodes.hpp:3694
LIEF::assembly::riscv::OPCODE::PseudoVSUXSEG7EI64_V_M1_M1_MASK
@ PseudoVSUXSEG7EI64_V_M1_M1_MASK
Definition riscv/opcodes.hpp:11216
LIEF::assembly::riscv::OPCODE::PseudoVSUXEI8_V_M2_M8_MASK
@ PseudoVSUXEI8_V_M2_M8_MASK
Definition riscv/opcodes.hpp:10628
LIEF::assembly::riscv::OPCODE::PseudoVLUXEI8_V_MF4_MF4_MASK
@ PseudoVLUXEI8_V_MF4_MF4_MASK
Definition riscv/opcodes.hpp:5717
LIEF::assembly::riscv::OPCODE::PseudoVFWADD_WFPR16_M1_E16_MASK
@ PseudoVFWADD_WFPR16_M1_E16_MASK
Definition riscv/opcodes.hpp:3488
LIEF::assembly::riscv::OPCODE::PseudoVSSSEG3E8_V_MF4_MASK
@ PseudoVSSSEG3E8_V_MF4_MASK
Definition riscv/opcodes.hpp:10308
LIEF::assembly::riscv::OPCODE::PseudoVFMADD_VFPR64_M4_E64_MASK
@ PseudoVFMADD_VFPR64_M4_E64_MASK
Definition riscv/opcodes.hpp:2024
LIEF::assembly::riscv::OPCODE::G_SET_FPMODE
@ G_SET_FPMODE
Definition riscv/opcodes.hpp:234
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG8EI16_V_MF2_MF4_MASK
@ PseudoVSOXSEG8EI16_V_MF2_MF4_MASK
Definition riscv/opcodes.hpp:9762
LIEF::assembly::riscv::OPCODE::PseudoVLSEG6E8FF_V_MF4
@ PseudoVLSEG6E8FF_V_MF4
Definition riscv/opcodes.hpp:5306
LIEF::assembly::riscv::OPCODE::PseudoVMFGT_VFPR16_M4
@ PseudoVMFGT_VFPR16_M4
Definition riscv/opcodes.hpp:6674
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG3EI64_V_M4_M2_MASK
@ PseudoVSOXSEG3EI64_V_M4_M2_MASK
Definition riscv/opcodes.hpp:9366
LIEF::assembly::riscv::OPCODE::PseudoVMULHSU_VV_M1_MASK
@ PseudoVMULHSU_VV_M1_MASK
Definition riscv/opcodes.hpp:7278
LIEF::assembly::riscv::OPCODE::PseudoVMUL_VX_M1_MASK
@ PseudoVMUL_VX_M1_MASK
Definition riscv/opcodes.hpp:7376
LIEF::assembly::riscv::OPCODE::PseudoVSOXEI64_V_M1_M1
@ PseudoVSOXEI64_V_M1_M1
Definition riscv/opcodes.hpp:9079
LIEF::assembly::riscv::OPCODE::PseudoVLOXSEG8EI64_V_M1_MF2
@ PseudoVLOXSEG8EI64_V_M1_MF2
Definition riscv/opcodes.hpp:4972
LIEF::assembly::riscv::OPCODE::PseudoVLUXSEG5EI16_V_M1_MF2_MASK
@ PseudoVLUXSEG5EI16_V_M1_MF2_MASK
Definition riscv/opcodes.hpp:6085
LIEF::assembly::riscv::OPCODE::PseudoVSOXSEG2EI32_V_MF2_M1_MASK
@ PseudoVSOXSEG2EI32_V_MF2_M1_MASK
Definition riscv/opcodes.hpp:9218
LIEF::assembly::riscv::OPCODE::PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK
@ PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK
Definition riscv/opcodes.hpp:8427
LIEF::assembly::riscv::OPCODE::PseudoVWADDU_WX_M2
@ PseudoVWADDU_WX_M2
Definition riscv/opcodes.hpp:11385
LIEF::assembly::riscv::OPCODE::PseudoVRELOAD5_MF4
@ PseudoVRELOAD5_MF4
Definition riscv/opcodes.hpp:8070
LIEF::assembly::riscv::OPCODE::PseudoVC_V_FPR16VV_M8
@ PseudoVC_V_FPR16VV_M8
Definition riscv/opcodes.hpp:1169
LIEF::assembly::riscv::OPCODE::PseudoVREDMIN_VS_M8_E64_MASK
@ PseudoVREDMIN_VS_M8_E64_MASK
Definition riscv/opcodes.hpp:7905
LIEF::assembly::riscv::OPCODE::PseudoVFSGNJN_VV_M4_E64_MASK
@ PseudoVFSGNJN_VV_M4_E64_MASK
Definition riscv/opcodes.hpp:3168
LIEF::assembly::riscv::OPCODE::PATCHABLE_EVENT_CALL
@ PATCHABLE_EVENT_CALL
Definition riscv/opcodes.hpp:63
LIEF::assembly
Namespace related to assembly/disassembly support.
Definition Abstract/Binary.hpp:43
LIEF
LIEF namespace.
Definition Abstract/Binary.hpp:36
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