RISC-V¶

Instruction¶

class lief.assembly.riscv.Instruction¶

Bases: Instruction

This class represents a RISC-V (32 or 64 bit) instruction

property opcode → lief.assembly.riscv.OPCODE¶: The instruction opcode as defined in LLVM

property operands → Iterator[lief.assembly.riscv.Operand | None]¶: Iterator over the operands of the current instruction

See: lief.assembly.riscv.OPCODE

class lief.assembly.riscv.Operand¶

Bases: object

This class represents an operand for a RISC-V instruction

class lief.assembly.riscv.operands.Immediate¶

Bases: Operand

This class represents an immediate operand (i.e. a constant)

For instance:

addi a0, a1, 8
             |
             +---> Immediate(8)

class lief.assembly.riscv.operands.Register¶

Bases: Operand

This class represents a register operand.

csrr    a0, mstatus
        |   |
 +------+   +-------+
 |                  |
 v                  v
 REG              SYSREG

property value → lief.assembly.riscv.REG | lief.assembly.riscv.SYSREG | None¶: The effective register as either: a lief.assembly.riscv.REG or a lief.assembly.riscv.SYSREG.

class lief.assembly.riscv.operands.Memory¶

Bases: Operand

This class represents a memory operand.

lw   a0, 8(sp)
         |  |
         |  +----> Base: sp
         |
         +-------> Displacement: 8

property base → lief.assembly.riscv.REG¶

The base register.

For lw a0, 8(sp) it would return sp.

property displacement → int¶

The displacement value.

For lw a0, 8(sp) it would return 8.

class lief.assembly.riscv.operands.PCRelative¶

Bases: Operand

This class represents a PC-relative operand.

auipc a0, 0x1
          |
          v
       PC Relative operand

property value → int¶: The effective value that is relative to the current pc register